1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include <drm/drmP.h> 27 #include <drm/radeon_drm.h> 28 #include "radeon.h" 29 30 #include "atom.h" 31 #include <asm/div64.h> 32 33 #include <linux/pm_runtime.h> 34 #include <drm/drm_crtc_helper.h> 35 #include <drm/drm_plane_helper.h> 36 #include <drm/drm_edid.h> 37 38 #include <linux/gcd.h> 39 40 static void avivo_crtc_load_lut(struct drm_crtc *crtc) 41 { 42 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 43 struct drm_device *dev = crtc->dev; 44 struct radeon_device *rdev = dev->dev_private; 45 int i; 46 47 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); 48 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); 49 50 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 51 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 52 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 53 54 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 55 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 56 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 57 58 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id); 59 WREG32(AVIVO_DC_LUT_RW_MODE, 0); 60 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f); 61 62 WREG8(AVIVO_DC_LUT_RW_INDEX, 0); 63 for (i = 0; i < 256; i++) { 64 WREG32(AVIVO_DC_LUT_30_COLOR, 65 (radeon_crtc->lut_r[i] << 20) | 66 (radeon_crtc->lut_g[i] << 10) | 67 (radeon_crtc->lut_b[i] << 0)); 68 } 69 70 /* Only change bit 0 of LUT_SEL, other bits are set elsewhere */ 71 WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1); 72 } 73 74 static void dce4_crtc_load_lut(struct drm_crtc *crtc) 75 { 76 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 77 struct drm_device *dev = crtc->dev; 78 struct radeon_device *rdev = dev->dev_private; 79 int i; 80 81 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); 82 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); 83 84 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 85 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 86 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 87 88 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 89 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 90 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 91 92 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); 93 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); 94 95 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); 96 for (i = 0; i < 256; i++) { 97 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, 98 (radeon_crtc->lut_r[i] << 20) | 99 (radeon_crtc->lut_g[i] << 10) | 100 (radeon_crtc->lut_b[i] << 0)); 101 } 102 } 103 104 static void dce5_crtc_load_lut(struct drm_crtc *crtc) 105 { 106 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 107 struct drm_device *dev = crtc->dev; 108 struct radeon_device *rdev = dev->dev_private; 109 int i; 110 111 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); 112 113 WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset, 114 (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) | 115 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS))); 116 WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset, 117 NI_GRPH_PRESCALE_BYPASS); 118 WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset, 119 NI_OVL_PRESCALE_BYPASS); 120 WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset, 121 (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) | 122 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT))); 123 124 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); 125 126 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 127 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 128 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 129 130 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 131 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 132 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 133 134 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); 135 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); 136 137 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); 138 for (i = 0; i < 256; i++) { 139 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, 140 (radeon_crtc->lut_r[i] << 20) | 141 (radeon_crtc->lut_g[i] << 10) | 142 (radeon_crtc->lut_b[i] << 0)); 143 } 144 145 WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset, 146 (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 147 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 148 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 149 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS))); 150 WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset, 151 (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) | 152 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS))); 153 WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset, 154 (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) | 155 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS))); 156 WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset, 157 (NI_OUTPUT_CSC_GRPH_MODE(radeon_crtc->output_csc) | 158 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS))); 159 /* XXX match this to the depth of the crtc fmt block, move to modeset? */ 160 WREG32(0x6940 + radeon_crtc->crtc_offset, 0); 161 if (ASIC_IS_DCE8(rdev)) { 162 /* XXX this only needs to be programmed once per crtc at startup, 163 * not sure where the best place for it is 164 */ 165 WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset, 166 CIK_CURSOR_ALPHA_BLND_ENA); 167 } 168 } 169 170 static void legacy_crtc_load_lut(struct drm_crtc *crtc) 171 { 172 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 173 struct drm_device *dev = crtc->dev; 174 struct radeon_device *rdev = dev->dev_private; 175 int i; 176 uint32_t dac2_cntl; 177 178 dac2_cntl = RREG32(RADEON_DAC_CNTL2); 179 if (radeon_crtc->crtc_id == 0) 180 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL; 181 else 182 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL; 183 WREG32(RADEON_DAC_CNTL2, dac2_cntl); 184 185 WREG8(RADEON_PALETTE_INDEX, 0); 186 for (i = 0; i < 256; i++) { 187 WREG32(RADEON_PALETTE_30_DATA, 188 (radeon_crtc->lut_r[i] << 20) | 189 (radeon_crtc->lut_g[i] << 10) | 190 (radeon_crtc->lut_b[i] << 0)); 191 } 192 } 193 194 void radeon_crtc_load_lut(struct drm_crtc *crtc) 195 { 196 struct drm_device *dev = crtc->dev; 197 struct radeon_device *rdev = dev->dev_private; 198 199 if (!crtc->enabled) 200 return; 201 202 if (ASIC_IS_DCE5(rdev)) 203 dce5_crtc_load_lut(crtc); 204 else if (ASIC_IS_DCE4(rdev)) 205 dce4_crtc_load_lut(crtc); 206 else if (ASIC_IS_AVIVO(rdev)) 207 avivo_crtc_load_lut(crtc); 208 else 209 legacy_crtc_load_lut(crtc); 210 } 211 212 /** Sets the color ramps on behalf of fbcon */ 213 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, 214 u16 blue, int regno) 215 { 216 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 217 218 radeon_crtc->lut_r[regno] = red >> 6; 219 radeon_crtc->lut_g[regno] = green >> 6; 220 radeon_crtc->lut_b[regno] = blue >> 6; 221 } 222 223 /** Gets the color ramps on behalf of fbcon */ 224 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, 225 u16 *blue, int regno) 226 { 227 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 228 229 *red = radeon_crtc->lut_r[regno] << 6; 230 *green = radeon_crtc->lut_g[regno] << 6; 231 *blue = radeon_crtc->lut_b[regno] << 6; 232 } 233 234 static int radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 235 u16 *blue, uint32_t size) 236 { 237 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 238 int i; 239 240 /* userspace palettes are always correct as is */ 241 for (i = 0; i < size; i++) { 242 radeon_crtc->lut_r[i] = red[i] >> 6; 243 radeon_crtc->lut_g[i] = green[i] >> 6; 244 radeon_crtc->lut_b[i] = blue[i] >> 6; 245 } 246 radeon_crtc_load_lut(crtc); 247 248 return 0; 249 } 250 251 static void radeon_crtc_destroy(struct drm_crtc *crtc) 252 { 253 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 254 255 drm_crtc_cleanup(crtc); 256 destroy_workqueue(radeon_crtc->flip_queue); 257 kfree(radeon_crtc); 258 } 259 260 /** 261 * radeon_unpin_work_func - unpin old buffer object 262 * 263 * @__work - kernel work item 264 * 265 * Unpin the old frame buffer object outside of the interrupt handler 266 */ 267 static void radeon_unpin_work_func(struct work_struct *__work) 268 { 269 struct radeon_flip_work *work = 270 container_of(__work, struct radeon_flip_work, unpin_work); 271 int r; 272 273 /* unpin of the old buffer */ 274 r = radeon_bo_reserve(work->old_rbo, false); 275 if (likely(r == 0)) { 276 r = radeon_bo_unpin(work->old_rbo); 277 if (unlikely(r != 0)) { 278 DRM_ERROR("failed to unpin buffer after flip\n"); 279 } 280 radeon_bo_unreserve(work->old_rbo); 281 } else 282 DRM_ERROR("failed to reserve buffer after flip\n"); 283 284 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base); 285 kfree(work); 286 } 287 288 void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id) 289 { 290 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 291 unsigned long flags; 292 u32 update_pending; 293 int vpos, hpos; 294 295 /* can happen during initialization */ 296 if (radeon_crtc == NULL) 297 return; 298 299 /* Skip the pageflip completion check below (based on polling) on 300 * asics which reliably support hw pageflip completion irqs. pflip 301 * irqs are a reliable and race-free method of handling pageflip 302 * completion detection. A use_pflipirq module parameter < 2 allows 303 * to override this in case of asics with faulty pflip irqs. 304 * A module parameter of 0 would only use this polling based path, 305 * a parameter of 1 would use pflip irq only as a backup to this 306 * path, as in Linux 3.16. 307 */ 308 if ((radeon_use_pflipirq == 2) && ASIC_IS_DCE4(rdev)) 309 return; 310 311 spin_lock_irqsave(&rdev->ddev->event_lock, flags); 312 if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) { 313 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != " 314 "RADEON_FLIP_SUBMITTED(%d)\n", 315 radeon_crtc->flip_status, 316 RADEON_FLIP_SUBMITTED); 317 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); 318 return; 319 } 320 321 update_pending = radeon_page_flip_pending(rdev, crtc_id); 322 323 /* Has the pageflip already completed in crtc, or is it certain 324 * to complete in this vblank? GET_DISTANCE_TO_VBLANKSTART provides 325 * distance to start of "fudged earlier" vblank in vpos, distance to 326 * start of real vblank in hpos. vpos >= 0 && hpos < 0 means we are in 327 * the last few scanlines before start of real vblank, where the vblank 328 * irq can fire, so we have sampled update_pending a bit too early and 329 * know the flip will complete at leading edge of the upcoming real 330 * vblank. On pre-AVIVO hardware, flips also complete inside the real 331 * vblank, not only at leading edge, so if update_pending for hpos >= 0 332 * == inside real vblank, the flip will complete almost immediately. 333 * Note that this method of completion handling is still not 100% race 334 * free, as we could execute before the radeon_flip_work_func managed 335 * to run and set the RADEON_FLIP_SUBMITTED status, thereby we no-op, 336 * but the flip still gets programmed into hw and completed during 337 * vblank, leading to a delayed emission of the flip completion event. 338 * This applies at least to pre-AVIVO hardware, where flips are always 339 * completing inside vblank, not only at leading edge of vblank. 340 */ 341 if (update_pending && 342 (DRM_SCANOUTPOS_VALID & 343 radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id, 344 GET_DISTANCE_TO_VBLANKSTART, 345 &vpos, &hpos, NULL, NULL, 346 &rdev->mode_info.crtcs[crtc_id]->base.hwmode)) && 347 ((vpos >= 0 && hpos < 0) || (hpos >= 0 && !ASIC_IS_AVIVO(rdev)))) { 348 /* crtc didn't flip in this target vblank interval, 349 * but flip is pending in crtc. Based on the current 350 * scanout position we know that the current frame is 351 * (nearly) complete and the flip will (likely) 352 * complete before the start of the next frame. 353 */ 354 update_pending = 0; 355 } 356 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); 357 if (!update_pending) 358 radeon_crtc_handle_flip(rdev, crtc_id); 359 } 360 361 /** 362 * radeon_crtc_handle_flip - page flip completed 363 * 364 * @rdev: radeon device pointer 365 * @crtc_id: crtc number this event is for 366 * 367 * Called when we are sure that a page flip for this crtc is completed. 368 */ 369 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id) 370 { 371 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 372 struct radeon_flip_work *work; 373 unsigned long flags; 374 375 /* this can happen at init */ 376 if (radeon_crtc == NULL) 377 return; 378 379 spin_lock_irqsave(&rdev->ddev->event_lock, flags); 380 work = radeon_crtc->flip_work; 381 if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) { 382 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != " 383 "RADEON_FLIP_SUBMITTED(%d)\n", 384 radeon_crtc->flip_status, 385 RADEON_FLIP_SUBMITTED); 386 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); 387 return; 388 } 389 390 /* Pageflip completed. Clean up. */ 391 radeon_crtc->flip_status = RADEON_FLIP_NONE; 392 radeon_crtc->flip_work = NULL; 393 394 /* wakeup userspace */ 395 if (work->event) 396 drm_crtc_send_vblank_event(&radeon_crtc->base, work->event); 397 398 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); 399 400 drm_crtc_vblank_put(&radeon_crtc->base); 401 radeon_irq_kms_pflip_irq_put(rdev, work->crtc_id); 402 queue_work(radeon_crtc->flip_queue, &work->unpin_work); 403 } 404 405 /** 406 * radeon_flip_work_func - page flip framebuffer 407 * 408 * @work - kernel work item 409 * 410 * Wait for the buffer object to become idle and do the actual page flip 411 */ 412 static void radeon_flip_work_func(struct work_struct *__work) 413 { 414 struct radeon_flip_work *work = 415 container_of(__work, struct radeon_flip_work, flip_work); 416 struct radeon_device *rdev = work->rdev; 417 struct drm_device *dev = rdev->ddev; 418 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[work->crtc_id]; 419 420 struct drm_crtc *crtc = &radeon_crtc->base; 421 unsigned long flags; 422 int r; 423 int vpos, hpos; 424 425 down_read(&rdev->exclusive_lock); 426 if (work->fence) { 427 struct radeon_fence *fence; 428 429 fence = to_radeon_fence(work->fence); 430 if (fence && fence->rdev == rdev) { 431 r = radeon_fence_wait(fence, false); 432 if (r == -EDEADLK) { 433 up_read(&rdev->exclusive_lock); 434 do { 435 r = radeon_gpu_reset(rdev); 436 } while (r == -EAGAIN); 437 down_read(&rdev->exclusive_lock); 438 } 439 } else 440 r = dma_fence_wait(work->fence, false); 441 442 if (r) 443 DRM_ERROR("failed to wait on page flip fence (%d)!\n", r); 444 445 /* We continue with the page flip even if we failed to wait on 446 * the fence, otherwise the DRM core and userspace will be 447 * confused about which BO the CRTC is scanning out 448 */ 449 450 dma_fence_put(work->fence); 451 work->fence = NULL; 452 } 453 454 /* Wait until we're out of the vertical blank period before the one 455 * targeted by the flip. Always wait on pre DCE4 to avoid races with 456 * flip completion handling from vblank irq, as these old asics don't 457 * have reliable pageflip completion interrupts. 458 */ 459 while (radeon_crtc->enabled && 460 (radeon_get_crtc_scanoutpos(dev, work->crtc_id, 0, 461 &vpos, &hpos, NULL, NULL, 462 &crtc->hwmode) 463 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) == 464 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) && 465 (!ASIC_IS_AVIVO(rdev) || 466 ((int) (work->target_vblank - 467 dev->driver->get_vblank_counter(dev, work->crtc_id)) > 0))) 468 usleep_range(1000, 2000); 469 470 /* We borrow the event spin lock for protecting flip_status */ 471 spin_lock_irqsave(&crtc->dev->event_lock, flags); 472 473 /* set the proper interrupt */ 474 radeon_irq_kms_pflip_irq_get(rdev, radeon_crtc->crtc_id); 475 476 /* do the flip (mmio) */ 477 radeon_page_flip(rdev, radeon_crtc->crtc_id, work->base, work->async); 478 479 radeon_crtc->flip_status = RADEON_FLIP_SUBMITTED; 480 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 481 up_read(&rdev->exclusive_lock); 482 } 483 484 static int radeon_crtc_page_flip_target(struct drm_crtc *crtc, 485 struct drm_framebuffer *fb, 486 struct drm_pending_vblank_event *event, 487 uint32_t page_flip_flags, 488 uint32_t target, 489 struct drm_modeset_acquire_ctx *ctx) 490 { 491 struct drm_device *dev = crtc->dev; 492 struct radeon_device *rdev = dev->dev_private; 493 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 494 struct radeon_framebuffer *old_radeon_fb; 495 struct radeon_framebuffer *new_radeon_fb; 496 struct drm_gem_object *obj; 497 struct radeon_flip_work *work; 498 struct radeon_bo *new_rbo; 499 uint32_t tiling_flags, pitch_pixels; 500 uint64_t base; 501 unsigned long flags; 502 int r; 503 504 work = kzalloc(sizeof *work, GFP_KERNEL); 505 if (work == NULL) 506 return -ENOMEM; 507 508 INIT_WORK(&work->flip_work, radeon_flip_work_func); 509 INIT_WORK(&work->unpin_work, radeon_unpin_work_func); 510 511 work->rdev = rdev; 512 work->crtc_id = radeon_crtc->crtc_id; 513 work->event = event; 514 work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0; 515 516 /* schedule unpin of the old buffer */ 517 old_radeon_fb = to_radeon_framebuffer(crtc->primary->fb); 518 obj = old_radeon_fb->obj; 519 520 /* take a reference to the old object */ 521 drm_gem_object_reference(obj); 522 work->old_rbo = gem_to_radeon_bo(obj); 523 524 new_radeon_fb = to_radeon_framebuffer(fb); 525 obj = new_radeon_fb->obj; 526 new_rbo = gem_to_radeon_bo(obj); 527 528 /* pin the new buffer */ 529 DRM_DEBUG_DRIVER("flip-ioctl() cur_rbo = %p, new_rbo = %p\n", 530 work->old_rbo, new_rbo); 531 532 r = radeon_bo_reserve(new_rbo, false); 533 if (unlikely(r != 0)) { 534 DRM_ERROR("failed to reserve new rbo buffer before flip\n"); 535 goto cleanup; 536 } 537 /* Only 27 bit offset for legacy CRTC */ 538 r = radeon_bo_pin_restricted(new_rbo, RADEON_GEM_DOMAIN_VRAM, 539 ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base); 540 if (unlikely(r != 0)) { 541 radeon_bo_unreserve(new_rbo); 542 r = -EINVAL; 543 DRM_ERROR("failed to pin new rbo buffer before flip\n"); 544 goto cleanup; 545 } 546 work->fence = dma_fence_get(reservation_object_get_excl(new_rbo->tbo.resv)); 547 radeon_bo_get_tiling_flags(new_rbo, &tiling_flags, NULL); 548 radeon_bo_unreserve(new_rbo); 549 550 if (!ASIC_IS_AVIVO(rdev)) { 551 /* crtc offset is from display base addr not FB location */ 552 base -= radeon_crtc->legacy_display_base_addr; 553 pitch_pixels = fb->pitches[0] / fb->format->cpp[0]; 554 555 if (tiling_flags & RADEON_TILING_MACRO) { 556 if (ASIC_IS_R300(rdev)) { 557 base &= ~0x7ff; 558 } else { 559 int byteshift = fb->format->cpp[0] * 8 >> 4; 560 int tile_addr = (((crtc->y >> 3) * pitch_pixels + crtc->x) >> (8 - byteshift)) << 11; 561 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8); 562 } 563 } else { 564 int offset = crtc->y * pitch_pixels + crtc->x; 565 switch (fb->format->cpp[0] * 8) { 566 case 8: 567 default: 568 offset *= 1; 569 break; 570 case 15: 571 case 16: 572 offset *= 2; 573 break; 574 case 24: 575 offset *= 3; 576 break; 577 case 32: 578 offset *= 4; 579 break; 580 } 581 base += offset; 582 } 583 base &= ~7; 584 } 585 work->base = base; 586 work->target_vblank = target - drm_crtc_vblank_count(crtc) + 587 dev->driver->get_vblank_counter(dev, work->crtc_id); 588 589 /* We borrow the event spin lock for protecting flip_work */ 590 spin_lock_irqsave(&crtc->dev->event_lock, flags); 591 592 if (radeon_crtc->flip_status != RADEON_FLIP_NONE) { 593 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); 594 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 595 r = -EBUSY; 596 goto pflip_cleanup; 597 } 598 radeon_crtc->flip_status = RADEON_FLIP_PENDING; 599 radeon_crtc->flip_work = work; 600 601 /* update crtc fb */ 602 crtc->primary->fb = fb; 603 604 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 605 606 queue_work(radeon_crtc->flip_queue, &work->flip_work); 607 return 0; 608 609 pflip_cleanup: 610 if (unlikely(radeon_bo_reserve(new_rbo, false) != 0)) { 611 DRM_ERROR("failed to reserve new rbo in error path\n"); 612 goto cleanup; 613 } 614 if (unlikely(radeon_bo_unpin(new_rbo) != 0)) { 615 DRM_ERROR("failed to unpin new rbo in error path\n"); 616 } 617 radeon_bo_unreserve(new_rbo); 618 619 cleanup: 620 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base); 621 dma_fence_put(work->fence); 622 kfree(work); 623 return r; 624 } 625 626 static int 627 radeon_crtc_set_config(struct drm_mode_set *set, 628 struct drm_modeset_acquire_ctx *ctx) 629 { 630 struct drm_device *dev; 631 struct radeon_device *rdev; 632 struct drm_crtc *crtc; 633 bool active = false; 634 int ret; 635 636 if (!set || !set->crtc) 637 return -EINVAL; 638 639 dev = set->crtc->dev; 640 641 ret = pm_runtime_get_sync(dev->dev); 642 if (ret < 0) 643 return ret; 644 645 ret = drm_crtc_helper_set_config(set, ctx); 646 647 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) 648 if (crtc->enabled) 649 active = true; 650 651 pm_runtime_mark_last_busy(dev->dev); 652 653 rdev = dev->dev_private; 654 /* if we have active crtcs and we don't have a power ref, 655 take the current one */ 656 if (active && !rdev->have_disp_power_ref) { 657 rdev->have_disp_power_ref = true; 658 return ret; 659 } 660 /* if we have no active crtcs, then drop the power ref 661 we got before */ 662 if (!active && rdev->have_disp_power_ref) { 663 pm_runtime_put_autosuspend(dev->dev); 664 rdev->have_disp_power_ref = false; 665 } 666 667 /* drop the power reference we got coming in here */ 668 pm_runtime_put_autosuspend(dev->dev); 669 return ret; 670 } 671 672 static const struct drm_crtc_funcs radeon_crtc_funcs = { 673 .cursor_set2 = radeon_crtc_cursor_set2, 674 .cursor_move = radeon_crtc_cursor_move, 675 .gamma_set = radeon_crtc_gamma_set, 676 .set_config = radeon_crtc_set_config, 677 .destroy = radeon_crtc_destroy, 678 .page_flip_target = radeon_crtc_page_flip_target, 679 }; 680 681 static void radeon_crtc_init(struct drm_device *dev, int index) 682 { 683 struct radeon_device *rdev = dev->dev_private; 684 struct radeon_crtc *radeon_crtc; 685 int i; 686 687 radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); 688 if (radeon_crtc == NULL) 689 return; 690 691 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs); 692 693 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256); 694 radeon_crtc->crtc_id = index; 695 radeon_crtc->flip_queue = alloc_workqueue("radeon-crtc", WQ_HIGHPRI, 0); 696 rdev->mode_info.crtcs[index] = radeon_crtc; 697 698 if (rdev->family >= CHIP_BONAIRE) { 699 radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH; 700 radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT; 701 } else { 702 radeon_crtc->max_cursor_width = CURSOR_WIDTH; 703 radeon_crtc->max_cursor_height = CURSOR_HEIGHT; 704 } 705 dev->mode_config.cursor_width = radeon_crtc->max_cursor_width; 706 dev->mode_config.cursor_height = radeon_crtc->max_cursor_height; 707 708 #if 0 709 radeon_crtc->mode_set.crtc = &radeon_crtc->base; 710 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1); 711 radeon_crtc->mode_set.num_connectors = 0; 712 #endif 713 714 for (i = 0; i < 256; i++) { 715 radeon_crtc->lut_r[i] = i << 2; 716 radeon_crtc->lut_g[i] = i << 2; 717 radeon_crtc->lut_b[i] = i << 2; 718 } 719 720 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)) 721 radeon_atombios_init_crtc(dev, radeon_crtc); 722 else 723 radeon_legacy_init_crtc(dev, radeon_crtc); 724 } 725 726 static const char *encoder_names[38] = { 727 "NONE", 728 "INTERNAL_LVDS", 729 "INTERNAL_TMDS1", 730 "INTERNAL_TMDS2", 731 "INTERNAL_DAC1", 732 "INTERNAL_DAC2", 733 "INTERNAL_SDVOA", 734 "INTERNAL_SDVOB", 735 "SI170B", 736 "CH7303", 737 "CH7301", 738 "INTERNAL_DVO1", 739 "EXTERNAL_SDVOA", 740 "EXTERNAL_SDVOB", 741 "TITFP513", 742 "INTERNAL_LVTM1", 743 "VT1623", 744 "HDMI_SI1930", 745 "HDMI_INTERNAL", 746 "INTERNAL_KLDSCP_TMDS1", 747 "INTERNAL_KLDSCP_DVO1", 748 "INTERNAL_KLDSCP_DAC1", 749 "INTERNAL_KLDSCP_DAC2", 750 "SI178", 751 "MVPU_FPGA", 752 "INTERNAL_DDI", 753 "VT1625", 754 "HDMI_SI1932", 755 "DP_AN9801", 756 "DP_DP501", 757 "INTERNAL_UNIPHY", 758 "INTERNAL_KLDSCP_LVTMA", 759 "INTERNAL_UNIPHY1", 760 "INTERNAL_UNIPHY2", 761 "NUTMEG", 762 "TRAVIS", 763 "INTERNAL_VCE", 764 "INTERNAL_UNIPHY3", 765 }; 766 767 static const char *hpd_names[6] = { 768 "HPD1", 769 "HPD2", 770 "HPD3", 771 "HPD4", 772 "HPD5", 773 "HPD6", 774 }; 775 776 static void radeon_print_display_setup(struct drm_device *dev) 777 { 778 struct drm_connector *connector; 779 struct radeon_connector *radeon_connector; 780 struct drm_encoder *encoder; 781 struct radeon_encoder *radeon_encoder; 782 uint32_t devices; 783 int i = 0; 784 785 DRM_INFO("Radeon Display Connectors\n"); 786 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 787 radeon_connector = to_radeon_connector(connector); 788 DRM_INFO("Connector %d:\n", i); 789 DRM_INFO(" %s\n", connector->name); 790 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) 791 DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]); 792 if (radeon_connector->ddc_bus) { 793 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", 794 radeon_connector->ddc_bus->rec.mask_clk_reg, 795 radeon_connector->ddc_bus->rec.mask_data_reg, 796 radeon_connector->ddc_bus->rec.a_clk_reg, 797 radeon_connector->ddc_bus->rec.a_data_reg, 798 radeon_connector->ddc_bus->rec.en_clk_reg, 799 radeon_connector->ddc_bus->rec.en_data_reg, 800 radeon_connector->ddc_bus->rec.y_clk_reg, 801 radeon_connector->ddc_bus->rec.y_data_reg); 802 if (radeon_connector->router.ddc_valid) 803 DRM_INFO(" DDC Router 0x%x/0x%x\n", 804 radeon_connector->router.ddc_mux_control_pin, 805 radeon_connector->router.ddc_mux_state); 806 if (radeon_connector->router.cd_valid) 807 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n", 808 radeon_connector->router.cd_mux_control_pin, 809 radeon_connector->router.cd_mux_state); 810 } else { 811 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || 812 connector->connector_type == DRM_MODE_CONNECTOR_DVII || 813 connector->connector_type == DRM_MODE_CONNECTOR_DVID || 814 connector->connector_type == DRM_MODE_CONNECTOR_DVIA || 815 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || 816 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) 817 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n"); 818 } 819 DRM_INFO(" Encoders:\n"); 820 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 821 radeon_encoder = to_radeon_encoder(encoder); 822 devices = radeon_encoder->devices & radeon_connector->devices; 823 if (devices) { 824 if (devices & ATOM_DEVICE_CRT1_SUPPORT) 825 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]); 826 if (devices & ATOM_DEVICE_CRT2_SUPPORT) 827 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]); 828 if (devices & ATOM_DEVICE_LCD1_SUPPORT) 829 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]); 830 if (devices & ATOM_DEVICE_DFP1_SUPPORT) 831 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]); 832 if (devices & ATOM_DEVICE_DFP2_SUPPORT) 833 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]); 834 if (devices & ATOM_DEVICE_DFP3_SUPPORT) 835 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]); 836 if (devices & ATOM_DEVICE_DFP4_SUPPORT) 837 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]); 838 if (devices & ATOM_DEVICE_DFP5_SUPPORT) 839 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]); 840 if (devices & ATOM_DEVICE_DFP6_SUPPORT) 841 DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]); 842 if (devices & ATOM_DEVICE_TV1_SUPPORT) 843 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]); 844 if (devices & ATOM_DEVICE_CV_SUPPORT) 845 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]); 846 } 847 } 848 i++; 849 } 850 } 851 852 static bool radeon_setup_enc_conn(struct drm_device *dev) 853 { 854 struct radeon_device *rdev = dev->dev_private; 855 bool ret = false; 856 857 if (rdev->bios) { 858 if (rdev->is_atom_bios) { 859 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev); 860 if (ret == false) 861 ret = radeon_get_atom_connector_info_from_object_table(dev); 862 } else { 863 ret = radeon_get_legacy_connector_info_from_bios(dev); 864 if (ret == false) 865 ret = radeon_get_legacy_connector_info_from_table(dev); 866 } 867 } else { 868 if (!ASIC_IS_AVIVO(rdev)) 869 ret = radeon_get_legacy_connector_info_from_table(dev); 870 } 871 if (ret) { 872 radeon_setup_encoder_clones(dev); 873 radeon_print_display_setup(dev); 874 } 875 876 return ret; 877 } 878 879 /* avivo */ 880 881 /** 882 * avivo_reduce_ratio - fractional number reduction 883 * 884 * @nom: nominator 885 * @den: denominator 886 * @nom_min: minimum value for nominator 887 * @den_min: minimum value for denominator 888 * 889 * Find the greatest common divisor and apply it on both nominator and 890 * denominator, but make nominator and denominator are at least as large 891 * as their minimum values. 892 */ 893 static void avivo_reduce_ratio(unsigned *nom, unsigned *den, 894 unsigned nom_min, unsigned den_min) 895 { 896 unsigned tmp; 897 898 /* reduce the numbers to a simpler ratio */ 899 tmp = gcd(*nom, *den); 900 *nom /= tmp; 901 *den /= tmp; 902 903 /* make sure nominator is large enough */ 904 if (*nom < nom_min) { 905 tmp = DIV_ROUND_UP(nom_min, *nom); 906 *nom *= tmp; 907 *den *= tmp; 908 } 909 910 /* make sure the denominator is large enough */ 911 if (*den < den_min) { 912 tmp = DIV_ROUND_UP(den_min, *den); 913 *nom *= tmp; 914 *den *= tmp; 915 } 916 } 917 918 /** 919 * avivo_get_fb_ref_div - feedback and ref divider calculation 920 * 921 * @nom: nominator 922 * @den: denominator 923 * @post_div: post divider 924 * @fb_div_max: feedback divider maximum 925 * @ref_div_max: reference divider maximum 926 * @fb_div: resulting feedback divider 927 * @ref_div: resulting reference divider 928 * 929 * Calculate feedback and reference divider for a given post divider. Makes 930 * sure we stay within the limits. 931 */ 932 static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div, 933 unsigned fb_div_max, unsigned ref_div_max, 934 unsigned *fb_div, unsigned *ref_div) 935 { 936 /* limit reference * post divider to a maximum */ 937 ref_div_max = max(min(100 / post_div, ref_div_max), 1u); 938 939 /* get matching reference and feedback divider */ 940 *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max); 941 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den); 942 943 /* limit fb divider to its maximum */ 944 if (*fb_div > fb_div_max) { 945 *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div); 946 *fb_div = fb_div_max; 947 } 948 } 949 950 /** 951 * radeon_compute_pll_avivo - compute PLL paramaters 952 * 953 * @pll: information about the PLL 954 * @dot_clock_p: resulting pixel clock 955 * fb_div_p: resulting feedback divider 956 * frac_fb_div_p: fractional part of the feedback divider 957 * ref_div_p: resulting reference divider 958 * post_div_p: resulting reference divider 959 * 960 * Try to calculate the PLL parameters to generate the given frequency: 961 * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div) 962 */ 963 void radeon_compute_pll_avivo(struct radeon_pll *pll, 964 u32 freq, 965 u32 *dot_clock_p, 966 u32 *fb_div_p, 967 u32 *frac_fb_div_p, 968 u32 *ref_div_p, 969 u32 *post_div_p) 970 { 971 unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ? 972 freq : freq / 10; 973 974 unsigned fb_div_min, fb_div_max, fb_div; 975 unsigned post_div_min, post_div_max, post_div; 976 unsigned ref_div_min, ref_div_max, ref_div; 977 unsigned post_div_best, diff_best; 978 unsigned nom, den; 979 980 /* determine allowed feedback divider range */ 981 fb_div_min = pll->min_feedback_div; 982 fb_div_max = pll->max_feedback_div; 983 984 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 985 fb_div_min *= 10; 986 fb_div_max *= 10; 987 } 988 989 /* determine allowed ref divider range */ 990 if (pll->flags & RADEON_PLL_USE_REF_DIV) 991 ref_div_min = pll->reference_div; 992 else 993 ref_div_min = pll->min_ref_div; 994 995 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && 996 pll->flags & RADEON_PLL_USE_REF_DIV) 997 ref_div_max = pll->reference_div; 998 else if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) 999 /* fix for problems on RS880 */ 1000 ref_div_max = min(pll->max_ref_div, 7u); 1001 else 1002 ref_div_max = pll->max_ref_div; 1003 1004 /* determine allowed post divider range */ 1005 if (pll->flags & RADEON_PLL_USE_POST_DIV) { 1006 post_div_min = pll->post_div; 1007 post_div_max = pll->post_div; 1008 } else { 1009 unsigned vco_min, vco_max; 1010 1011 if (pll->flags & RADEON_PLL_IS_LCD) { 1012 vco_min = pll->lcd_pll_out_min; 1013 vco_max = pll->lcd_pll_out_max; 1014 } else { 1015 vco_min = pll->pll_out_min; 1016 vco_max = pll->pll_out_max; 1017 } 1018 1019 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 1020 vco_min *= 10; 1021 vco_max *= 10; 1022 } 1023 1024 post_div_min = vco_min / target_clock; 1025 if ((target_clock * post_div_min) < vco_min) 1026 ++post_div_min; 1027 if (post_div_min < pll->min_post_div) 1028 post_div_min = pll->min_post_div; 1029 1030 post_div_max = vco_max / target_clock; 1031 if ((target_clock * post_div_max) > vco_max) 1032 --post_div_max; 1033 if (post_div_max > pll->max_post_div) 1034 post_div_max = pll->max_post_div; 1035 } 1036 1037 /* represent the searched ratio as fractional number */ 1038 nom = target_clock; 1039 den = pll->reference_freq; 1040 1041 /* reduce the numbers to a simpler ratio */ 1042 avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min); 1043 1044 /* now search for a post divider */ 1045 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) 1046 post_div_best = post_div_min; 1047 else 1048 post_div_best = post_div_max; 1049 diff_best = ~0; 1050 1051 for (post_div = post_div_min; post_div <= post_div_max; ++post_div) { 1052 unsigned diff; 1053 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, 1054 ref_div_max, &fb_div, &ref_div); 1055 diff = abs(target_clock - (pll->reference_freq * fb_div) / 1056 (ref_div * post_div)); 1057 1058 if (diff < diff_best || (diff == diff_best && 1059 !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) { 1060 1061 post_div_best = post_div; 1062 diff_best = diff; 1063 } 1064 } 1065 post_div = post_div_best; 1066 1067 /* get the feedback and reference divider for the optimal value */ 1068 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max, 1069 &fb_div, &ref_div); 1070 1071 /* reduce the numbers to a simpler ratio once more */ 1072 /* this also makes sure that the reference divider is large enough */ 1073 avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min); 1074 1075 /* avoid high jitter with small fractional dividers */ 1076 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) { 1077 fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 50); 1078 if (fb_div < fb_div_min) { 1079 unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div); 1080 fb_div *= tmp; 1081 ref_div *= tmp; 1082 } 1083 } 1084 1085 /* and finally save the result */ 1086 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 1087 *fb_div_p = fb_div / 10; 1088 *frac_fb_div_p = fb_div % 10; 1089 } else { 1090 *fb_div_p = fb_div; 1091 *frac_fb_div_p = 0; 1092 } 1093 1094 *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) + 1095 (pll->reference_freq * *frac_fb_div_p)) / 1096 (ref_div * post_div * 10); 1097 *ref_div_p = ref_div; 1098 *post_div_p = post_div; 1099 1100 DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n", 1101 freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p, 1102 ref_div, post_div); 1103 } 1104 1105 /* pre-avivo */ 1106 static inline uint32_t radeon_div(uint64_t n, uint32_t d) 1107 { 1108 uint64_t mod; 1109 1110 n += d / 2; 1111 1112 mod = do_div(n, d); 1113 return n; 1114 } 1115 1116 void radeon_compute_pll_legacy(struct radeon_pll *pll, 1117 uint64_t freq, 1118 uint32_t *dot_clock_p, 1119 uint32_t *fb_div_p, 1120 uint32_t *frac_fb_div_p, 1121 uint32_t *ref_div_p, 1122 uint32_t *post_div_p) 1123 { 1124 uint32_t min_ref_div = pll->min_ref_div; 1125 uint32_t max_ref_div = pll->max_ref_div; 1126 uint32_t min_post_div = pll->min_post_div; 1127 uint32_t max_post_div = pll->max_post_div; 1128 uint32_t min_fractional_feed_div = 0; 1129 uint32_t max_fractional_feed_div = 0; 1130 uint32_t best_vco = pll->best_vco; 1131 uint32_t best_post_div = 1; 1132 uint32_t best_ref_div = 1; 1133 uint32_t best_feedback_div = 1; 1134 uint32_t best_frac_feedback_div = 0; 1135 uint32_t best_freq = -1; 1136 uint32_t best_error = 0xffffffff; 1137 uint32_t best_vco_diff = 1; 1138 uint32_t post_div; 1139 u32 pll_out_min, pll_out_max; 1140 1141 DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div); 1142 freq = freq * 1000; 1143 1144 if (pll->flags & RADEON_PLL_IS_LCD) { 1145 pll_out_min = pll->lcd_pll_out_min; 1146 pll_out_max = pll->lcd_pll_out_max; 1147 } else { 1148 pll_out_min = pll->pll_out_min; 1149 pll_out_max = pll->pll_out_max; 1150 } 1151 1152 if (pll_out_min > 64800) 1153 pll_out_min = 64800; 1154 1155 if (pll->flags & RADEON_PLL_USE_REF_DIV) 1156 min_ref_div = max_ref_div = pll->reference_div; 1157 else { 1158 while (min_ref_div < max_ref_div-1) { 1159 uint32_t mid = (min_ref_div + max_ref_div) / 2; 1160 uint32_t pll_in = pll->reference_freq / mid; 1161 if (pll_in < pll->pll_in_min) 1162 max_ref_div = mid; 1163 else if (pll_in > pll->pll_in_max) 1164 min_ref_div = mid; 1165 else 1166 break; 1167 } 1168 } 1169 1170 if (pll->flags & RADEON_PLL_USE_POST_DIV) 1171 min_post_div = max_post_div = pll->post_div; 1172 1173 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 1174 min_fractional_feed_div = pll->min_frac_feedback_div; 1175 max_fractional_feed_div = pll->max_frac_feedback_div; 1176 } 1177 1178 for (post_div = max_post_div; post_div >= min_post_div; --post_div) { 1179 uint32_t ref_div; 1180 1181 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) 1182 continue; 1183 1184 /* legacy radeons only have a few post_divs */ 1185 if (pll->flags & RADEON_PLL_LEGACY) { 1186 if ((post_div == 5) || 1187 (post_div == 7) || 1188 (post_div == 9) || 1189 (post_div == 10) || 1190 (post_div == 11) || 1191 (post_div == 13) || 1192 (post_div == 14) || 1193 (post_div == 15)) 1194 continue; 1195 } 1196 1197 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) { 1198 uint32_t feedback_div, current_freq = 0, error, vco_diff; 1199 uint32_t pll_in = pll->reference_freq / ref_div; 1200 uint32_t min_feed_div = pll->min_feedback_div; 1201 uint32_t max_feed_div = pll->max_feedback_div + 1; 1202 1203 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max) 1204 continue; 1205 1206 while (min_feed_div < max_feed_div) { 1207 uint32_t vco; 1208 uint32_t min_frac_feed_div = min_fractional_feed_div; 1209 uint32_t max_frac_feed_div = max_fractional_feed_div + 1; 1210 uint32_t frac_feedback_div; 1211 uint64_t tmp; 1212 1213 feedback_div = (min_feed_div + max_feed_div) / 2; 1214 1215 tmp = (uint64_t)pll->reference_freq * feedback_div; 1216 vco = radeon_div(tmp, ref_div); 1217 1218 if (vco < pll_out_min) { 1219 min_feed_div = feedback_div + 1; 1220 continue; 1221 } else if (vco > pll_out_max) { 1222 max_feed_div = feedback_div; 1223 continue; 1224 } 1225 1226 while (min_frac_feed_div < max_frac_feed_div) { 1227 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2; 1228 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div; 1229 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div; 1230 current_freq = radeon_div(tmp, ref_div * post_div); 1231 1232 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) { 1233 if (freq < current_freq) 1234 error = 0xffffffff; 1235 else 1236 error = freq - current_freq; 1237 } else 1238 error = abs(current_freq - freq); 1239 vco_diff = abs(vco - best_vco); 1240 1241 if ((best_vco == 0 && error < best_error) || 1242 (best_vco != 0 && 1243 ((best_error > 100 && error < best_error - 100) || 1244 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) { 1245 best_post_div = post_div; 1246 best_ref_div = ref_div; 1247 best_feedback_div = feedback_div; 1248 best_frac_feedback_div = frac_feedback_div; 1249 best_freq = current_freq; 1250 best_error = error; 1251 best_vco_diff = vco_diff; 1252 } else if (current_freq == freq) { 1253 if (best_freq == -1) { 1254 best_post_div = post_div; 1255 best_ref_div = ref_div; 1256 best_feedback_div = feedback_div; 1257 best_frac_feedback_div = frac_feedback_div; 1258 best_freq = current_freq; 1259 best_error = error; 1260 best_vco_diff = vco_diff; 1261 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) || 1262 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) || 1263 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) || 1264 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) || 1265 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) || 1266 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) { 1267 best_post_div = post_div; 1268 best_ref_div = ref_div; 1269 best_feedback_div = feedback_div; 1270 best_frac_feedback_div = frac_feedback_div; 1271 best_freq = current_freq; 1272 best_error = error; 1273 best_vco_diff = vco_diff; 1274 } 1275 } 1276 if (current_freq < freq) 1277 min_frac_feed_div = frac_feedback_div + 1; 1278 else 1279 max_frac_feed_div = frac_feedback_div; 1280 } 1281 if (current_freq < freq) 1282 min_feed_div = feedback_div + 1; 1283 else 1284 max_feed_div = feedback_div; 1285 } 1286 } 1287 } 1288 1289 *dot_clock_p = best_freq / 10000; 1290 *fb_div_p = best_feedback_div; 1291 *frac_fb_div_p = best_frac_feedback_div; 1292 *ref_div_p = best_ref_div; 1293 *post_div_p = best_post_div; 1294 DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n", 1295 (long long)freq, 1296 best_freq / 1000, best_feedback_div, best_frac_feedback_div, 1297 best_ref_div, best_post_div); 1298 1299 } 1300 1301 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb) 1302 { 1303 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); 1304 1305 drm_gem_object_unreference_unlocked(radeon_fb->obj); 1306 drm_framebuffer_cleanup(fb); 1307 kfree(radeon_fb); 1308 } 1309 1310 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb, 1311 struct drm_file *file_priv, 1312 unsigned int *handle) 1313 { 1314 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); 1315 1316 return drm_gem_handle_create(file_priv, radeon_fb->obj, handle); 1317 } 1318 1319 static const struct drm_framebuffer_funcs radeon_fb_funcs = { 1320 .destroy = radeon_user_framebuffer_destroy, 1321 .create_handle = radeon_user_framebuffer_create_handle, 1322 }; 1323 1324 int 1325 radeon_framebuffer_init(struct drm_device *dev, 1326 struct radeon_framebuffer *rfb, 1327 const struct drm_mode_fb_cmd2 *mode_cmd, 1328 struct drm_gem_object *obj) 1329 { 1330 int ret; 1331 rfb->obj = obj; 1332 drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd); 1333 ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs); 1334 if (ret) { 1335 rfb->obj = NULL; 1336 return ret; 1337 } 1338 return 0; 1339 } 1340 1341 static struct drm_framebuffer * 1342 radeon_user_framebuffer_create(struct drm_device *dev, 1343 struct drm_file *file_priv, 1344 const struct drm_mode_fb_cmd2 *mode_cmd) 1345 { 1346 struct drm_gem_object *obj; 1347 struct radeon_framebuffer *radeon_fb; 1348 int ret; 1349 1350 obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]); 1351 if (obj == NULL) { 1352 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, " 1353 "can't create framebuffer\n", mode_cmd->handles[0]); 1354 return ERR_PTR(-ENOENT); 1355 } 1356 1357 radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL); 1358 if (radeon_fb == NULL) { 1359 drm_gem_object_unreference_unlocked(obj); 1360 return ERR_PTR(-ENOMEM); 1361 } 1362 1363 ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj); 1364 if (ret) { 1365 kfree(radeon_fb); 1366 drm_gem_object_unreference_unlocked(obj); 1367 return ERR_PTR(ret); 1368 } 1369 1370 return &radeon_fb->base; 1371 } 1372 1373 static void radeon_output_poll_changed(struct drm_device *dev) 1374 { 1375 struct radeon_device *rdev = dev->dev_private; 1376 radeon_fb_output_poll_changed(rdev); 1377 } 1378 1379 static const struct drm_mode_config_funcs radeon_mode_funcs = { 1380 .fb_create = radeon_user_framebuffer_create, 1381 .output_poll_changed = radeon_output_poll_changed 1382 }; 1383 1384 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] = 1385 { { 0, "driver" }, 1386 { 1, "bios" }, 1387 }; 1388 1389 static struct drm_prop_enum_list radeon_tv_std_enum_list[] = 1390 { { TV_STD_NTSC, "ntsc" }, 1391 { TV_STD_PAL, "pal" }, 1392 { TV_STD_PAL_M, "pal-m" }, 1393 { TV_STD_PAL_60, "pal-60" }, 1394 { TV_STD_NTSC_J, "ntsc-j" }, 1395 { TV_STD_SCART_PAL, "scart-pal" }, 1396 { TV_STD_PAL_CN, "pal-cn" }, 1397 { TV_STD_SECAM, "secam" }, 1398 }; 1399 1400 static struct drm_prop_enum_list radeon_underscan_enum_list[] = 1401 { { UNDERSCAN_OFF, "off" }, 1402 { UNDERSCAN_ON, "on" }, 1403 { UNDERSCAN_AUTO, "auto" }, 1404 }; 1405 1406 static struct drm_prop_enum_list radeon_audio_enum_list[] = 1407 { { RADEON_AUDIO_DISABLE, "off" }, 1408 { RADEON_AUDIO_ENABLE, "on" }, 1409 { RADEON_AUDIO_AUTO, "auto" }, 1410 }; 1411 1412 /* XXX support different dither options? spatial, temporal, both, etc. */ 1413 static struct drm_prop_enum_list radeon_dither_enum_list[] = 1414 { { RADEON_FMT_DITHER_DISABLE, "off" }, 1415 { RADEON_FMT_DITHER_ENABLE, "on" }, 1416 }; 1417 1418 static struct drm_prop_enum_list radeon_output_csc_enum_list[] = 1419 { { RADEON_OUTPUT_CSC_BYPASS, "bypass" }, 1420 { RADEON_OUTPUT_CSC_TVRGB, "tvrgb" }, 1421 { RADEON_OUTPUT_CSC_YCBCR601, "ycbcr601" }, 1422 { RADEON_OUTPUT_CSC_YCBCR709, "ycbcr709" }, 1423 }; 1424 1425 static int radeon_modeset_create_props(struct radeon_device *rdev) 1426 { 1427 int sz; 1428 1429 if (rdev->is_atom_bios) { 1430 rdev->mode_info.coherent_mode_property = 1431 drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1); 1432 if (!rdev->mode_info.coherent_mode_property) 1433 return -ENOMEM; 1434 } 1435 1436 if (!ASIC_IS_AVIVO(rdev)) { 1437 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list); 1438 rdev->mode_info.tmds_pll_property = 1439 drm_property_create_enum(rdev->ddev, 0, 1440 "tmds_pll", 1441 radeon_tmds_pll_enum_list, sz); 1442 } 1443 1444 rdev->mode_info.load_detect_property = 1445 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1); 1446 if (!rdev->mode_info.load_detect_property) 1447 return -ENOMEM; 1448 1449 drm_mode_create_scaling_mode_property(rdev->ddev); 1450 1451 sz = ARRAY_SIZE(radeon_tv_std_enum_list); 1452 rdev->mode_info.tv_std_property = 1453 drm_property_create_enum(rdev->ddev, 0, 1454 "tv standard", 1455 radeon_tv_std_enum_list, sz); 1456 1457 sz = ARRAY_SIZE(radeon_underscan_enum_list); 1458 rdev->mode_info.underscan_property = 1459 drm_property_create_enum(rdev->ddev, 0, 1460 "underscan", 1461 radeon_underscan_enum_list, sz); 1462 1463 rdev->mode_info.underscan_hborder_property = 1464 drm_property_create_range(rdev->ddev, 0, 1465 "underscan hborder", 0, 128); 1466 if (!rdev->mode_info.underscan_hborder_property) 1467 return -ENOMEM; 1468 1469 rdev->mode_info.underscan_vborder_property = 1470 drm_property_create_range(rdev->ddev, 0, 1471 "underscan vborder", 0, 128); 1472 if (!rdev->mode_info.underscan_vborder_property) 1473 return -ENOMEM; 1474 1475 sz = ARRAY_SIZE(radeon_audio_enum_list); 1476 rdev->mode_info.audio_property = 1477 drm_property_create_enum(rdev->ddev, 0, 1478 "audio", 1479 radeon_audio_enum_list, sz); 1480 1481 sz = ARRAY_SIZE(radeon_dither_enum_list); 1482 rdev->mode_info.dither_property = 1483 drm_property_create_enum(rdev->ddev, 0, 1484 "dither", 1485 radeon_dither_enum_list, sz); 1486 1487 sz = ARRAY_SIZE(radeon_output_csc_enum_list); 1488 rdev->mode_info.output_csc_property = 1489 drm_property_create_enum(rdev->ddev, 0, 1490 "output_csc", 1491 radeon_output_csc_enum_list, sz); 1492 1493 return 0; 1494 } 1495 1496 void radeon_update_display_priority(struct radeon_device *rdev) 1497 { 1498 /* adjustment options for the display watermarks */ 1499 if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) { 1500 /* set display priority to high for r3xx, rv515 chips 1501 * this avoids flickering due to underflow to the 1502 * display controllers during heavy acceleration. 1503 * Don't force high on rs4xx igp chips as it seems to 1504 * affect the sound card. See kernel bug 15982. 1505 */ 1506 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) && 1507 !(rdev->flags & RADEON_IS_IGP)) 1508 rdev->disp_priority = 2; 1509 else 1510 rdev->disp_priority = 0; 1511 } else 1512 rdev->disp_priority = radeon_disp_priority; 1513 1514 } 1515 1516 /* 1517 * Allocate hdmi structs and determine register offsets 1518 */ 1519 static void radeon_afmt_init(struct radeon_device *rdev) 1520 { 1521 int i; 1522 1523 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) 1524 rdev->mode_info.afmt[i] = NULL; 1525 1526 if (ASIC_IS_NODCE(rdev)) { 1527 /* nothing to do */ 1528 } else if (ASIC_IS_DCE4(rdev)) { 1529 static uint32_t eg_offsets[] = { 1530 EVERGREEN_CRTC0_REGISTER_OFFSET, 1531 EVERGREEN_CRTC1_REGISTER_OFFSET, 1532 EVERGREEN_CRTC2_REGISTER_OFFSET, 1533 EVERGREEN_CRTC3_REGISTER_OFFSET, 1534 EVERGREEN_CRTC4_REGISTER_OFFSET, 1535 EVERGREEN_CRTC5_REGISTER_OFFSET, 1536 0x13830 - 0x7030, 1537 }; 1538 int num_afmt; 1539 1540 /* DCE8 has 7 audio blocks tied to DIG encoders */ 1541 /* DCE6 has 6 audio blocks tied to DIG encoders */ 1542 /* DCE4/5 has 6 audio blocks tied to DIG encoders */ 1543 /* DCE4.1 has 2 audio blocks tied to DIG encoders */ 1544 if (ASIC_IS_DCE8(rdev)) 1545 num_afmt = 7; 1546 else if (ASIC_IS_DCE6(rdev)) 1547 num_afmt = 6; 1548 else if (ASIC_IS_DCE5(rdev)) 1549 num_afmt = 6; 1550 else if (ASIC_IS_DCE41(rdev)) 1551 num_afmt = 2; 1552 else /* DCE4 */ 1553 num_afmt = 6; 1554 1555 BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets)); 1556 for (i = 0; i < num_afmt; i++) { 1557 rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1558 if (rdev->mode_info.afmt[i]) { 1559 rdev->mode_info.afmt[i]->offset = eg_offsets[i]; 1560 rdev->mode_info.afmt[i]->id = i; 1561 } 1562 } 1563 } else if (ASIC_IS_DCE3(rdev)) { 1564 /* DCE3.x has 2 audio blocks tied to DIG encoders */ 1565 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1566 if (rdev->mode_info.afmt[0]) { 1567 rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0; 1568 rdev->mode_info.afmt[0]->id = 0; 1569 } 1570 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1571 if (rdev->mode_info.afmt[1]) { 1572 rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1; 1573 rdev->mode_info.afmt[1]->id = 1; 1574 } 1575 } else if (ASIC_IS_DCE2(rdev)) { 1576 /* DCE2 has at least 1 routable audio block */ 1577 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1578 if (rdev->mode_info.afmt[0]) { 1579 rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0; 1580 rdev->mode_info.afmt[0]->id = 0; 1581 } 1582 /* r6xx has 2 routable audio blocks */ 1583 if (rdev->family >= CHIP_R600) { 1584 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1585 if (rdev->mode_info.afmt[1]) { 1586 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1; 1587 rdev->mode_info.afmt[1]->id = 1; 1588 } 1589 } 1590 } 1591 } 1592 1593 static void radeon_afmt_fini(struct radeon_device *rdev) 1594 { 1595 int i; 1596 1597 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) { 1598 kfree(rdev->mode_info.afmt[i]); 1599 rdev->mode_info.afmt[i] = NULL; 1600 } 1601 } 1602 1603 int radeon_modeset_init(struct radeon_device *rdev) 1604 { 1605 int i; 1606 int ret; 1607 1608 drm_mode_config_init(rdev->ddev); 1609 rdev->mode_info.mode_config_initialized = true; 1610 1611 rdev->ddev->mode_config.funcs = &radeon_mode_funcs; 1612 1613 if (radeon_use_pflipirq == 2 && rdev->family >= CHIP_R600) 1614 rdev->ddev->mode_config.async_page_flip = true; 1615 1616 if (ASIC_IS_DCE5(rdev)) { 1617 rdev->ddev->mode_config.max_width = 16384; 1618 rdev->ddev->mode_config.max_height = 16384; 1619 } else if (ASIC_IS_AVIVO(rdev)) { 1620 rdev->ddev->mode_config.max_width = 8192; 1621 rdev->ddev->mode_config.max_height = 8192; 1622 } else { 1623 rdev->ddev->mode_config.max_width = 4096; 1624 rdev->ddev->mode_config.max_height = 4096; 1625 } 1626 1627 rdev->ddev->mode_config.preferred_depth = 24; 1628 rdev->ddev->mode_config.prefer_shadow = 1; 1629 1630 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base; 1631 1632 ret = radeon_modeset_create_props(rdev); 1633 if (ret) { 1634 return ret; 1635 } 1636 1637 /* init i2c buses */ 1638 radeon_i2c_init(rdev); 1639 1640 /* check combios for a valid hardcoded EDID - Sun servers */ 1641 if (!rdev->is_atom_bios) { 1642 /* check for hardcoded EDID in BIOS */ 1643 radeon_combios_check_hardcoded_edid(rdev); 1644 } 1645 1646 /* allocate crtcs */ 1647 for (i = 0; i < rdev->num_crtc; i++) { 1648 radeon_crtc_init(rdev->ddev, i); 1649 } 1650 1651 /* okay we should have all the bios connectors */ 1652 ret = radeon_setup_enc_conn(rdev->ddev); 1653 if (!ret) { 1654 return ret; 1655 } 1656 1657 /* init dig PHYs, disp eng pll */ 1658 if (rdev->is_atom_bios) { 1659 radeon_atom_encoder_init(rdev); 1660 radeon_atom_disp_eng_pll_init(rdev); 1661 } 1662 1663 /* initialize hpd */ 1664 radeon_hpd_init(rdev); 1665 1666 /* setup afmt */ 1667 radeon_afmt_init(rdev); 1668 1669 radeon_fbdev_init(rdev); 1670 drm_kms_helper_poll_init(rdev->ddev); 1671 1672 /* do pm late init */ 1673 ret = radeon_pm_late_init(rdev); 1674 1675 return 0; 1676 } 1677 1678 void radeon_modeset_fini(struct radeon_device *rdev) 1679 { 1680 if (rdev->mode_info.mode_config_initialized) { 1681 drm_kms_helper_poll_fini(rdev->ddev); 1682 radeon_hpd_fini(rdev); 1683 drm_crtc_force_disable_all(rdev->ddev); 1684 radeon_fbdev_fini(rdev); 1685 radeon_afmt_fini(rdev); 1686 drm_mode_config_cleanup(rdev->ddev); 1687 rdev->mode_info.mode_config_initialized = false; 1688 } 1689 1690 kfree(rdev->mode_info.bios_hardcoded_edid); 1691 1692 /* free i2c buses */ 1693 radeon_i2c_fini(rdev); 1694 } 1695 1696 static bool is_hdtv_mode(const struct drm_display_mode *mode) 1697 { 1698 /* try and guess if this is a tv or a monitor */ 1699 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */ 1700 (mode->vdisplay == 576) || /* 576p */ 1701 (mode->vdisplay == 720) || /* 720p */ 1702 (mode->vdisplay == 1080)) /* 1080p */ 1703 return true; 1704 else 1705 return false; 1706 } 1707 1708 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 1709 const struct drm_display_mode *mode, 1710 struct drm_display_mode *adjusted_mode) 1711 { 1712 struct drm_device *dev = crtc->dev; 1713 struct radeon_device *rdev = dev->dev_private; 1714 struct drm_encoder *encoder; 1715 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1716 struct radeon_encoder *radeon_encoder; 1717 struct drm_connector *connector; 1718 struct radeon_connector *radeon_connector; 1719 bool first = true; 1720 u32 src_v = 1, dst_v = 1; 1721 u32 src_h = 1, dst_h = 1; 1722 1723 radeon_crtc->h_border = 0; 1724 radeon_crtc->v_border = 0; 1725 1726 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1727 if (encoder->crtc != crtc) 1728 continue; 1729 radeon_encoder = to_radeon_encoder(encoder); 1730 connector = radeon_get_connector_for_encoder(encoder); 1731 radeon_connector = to_radeon_connector(connector); 1732 1733 if (first) { 1734 /* set scaling */ 1735 if (radeon_encoder->rmx_type == RMX_OFF) 1736 radeon_crtc->rmx_type = RMX_OFF; 1737 else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay || 1738 mode->vdisplay < radeon_encoder->native_mode.vdisplay) 1739 radeon_crtc->rmx_type = radeon_encoder->rmx_type; 1740 else 1741 radeon_crtc->rmx_type = RMX_OFF; 1742 /* copy native mode */ 1743 memcpy(&radeon_crtc->native_mode, 1744 &radeon_encoder->native_mode, 1745 sizeof(struct drm_display_mode)); 1746 src_v = crtc->mode.vdisplay; 1747 dst_v = radeon_crtc->native_mode.vdisplay; 1748 src_h = crtc->mode.hdisplay; 1749 dst_h = radeon_crtc->native_mode.hdisplay; 1750 1751 /* fix up for overscan on hdmi */ 1752 if (ASIC_IS_AVIVO(rdev) && 1753 (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) && 1754 ((radeon_encoder->underscan_type == UNDERSCAN_ON) || 1755 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) && 1756 drm_detect_hdmi_monitor(radeon_connector_edid(connector)) && 1757 is_hdtv_mode(mode)))) { 1758 if (radeon_encoder->underscan_hborder != 0) 1759 radeon_crtc->h_border = radeon_encoder->underscan_hborder; 1760 else 1761 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16; 1762 if (radeon_encoder->underscan_vborder != 0) 1763 radeon_crtc->v_border = radeon_encoder->underscan_vborder; 1764 else 1765 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16; 1766 radeon_crtc->rmx_type = RMX_FULL; 1767 src_v = crtc->mode.vdisplay; 1768 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2); 1769 src_h = crtc->mode.hdisplay; 1770 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2); 1771 } 1772 first = false; 1773 } else { 1774 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) { 1775 /* WARNING: Right now this can't happen but 1776 * in the future we need to check that scaling 1777 * are consistent across different encoder 1778 * (ie all encoder can work with the same 1779 * scaling). 1780 */ 1781 DRM_ERROR("Scaling not consistent across encoder.\n"); 1782 return false; 1783 } 1784 } 1785 } 1786 if (radeon_crtc->rmx_type != RMX_OFF) { 1787 fixed20_12 a, b; 1788 a.full = dfixed_const(src_v); 1789 b.full = dfixed_const(dst_v); 1790 radeon_crtc->vsc.full = dfixed_div(a, b); 1791 a.full = dfixed_const(src_h); 1792 b.full = dfixed_const(dst_h); 1793 radeon_crtc->hsc.full = dfixed_div(a, b); 1794 } else { 1795 radeon_crtc->vsc.full = dfixed_const(1); 1796 radeon_crtc->hsc.full = dfixed_const(1); 1797 } 1798 return true; 1799 } 1800 1801 /* 1802 * Retrieve current video scanout position of crtc on a given gpu, and 1803 * an optional accurate timestamp of when query happened. 1804 * 1805 * \param dev Device to query. 1806 * \param crtc Crtc to query. 1807 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0). 1808 * For driver internal use only also supports these flags: 1809 * 1810 * USE_REAL_VBLANKSTART to use the real start of vblank instead 1811 * of a fudged earlier start of vblank. 1812 * 1813 * GET_DISTANCE_TO_VBLANKSTART to return distance to the 1814 * fudged earlier start of vblank in *vpos and the distance 1815 * to true start of vblank in *hpos. 1816 * 1817 * \param *vpos Location where vertical scanout position should be stored. 1818 * \param *hpos Location where horizontal scanout position should go. 1819 * \param *stime Target location for timestamp taken immediately before 1820 * scanout position query. Can be NULL to skip timestamp. 1821 * \param *etime Target location for timestamp taken immediately after 1822 * scanout position query. Can be NULL to skip timestamp. 1823 * 1824 * Returns vpos as a positive number while in active scanout area. 1825 * Returns vpos as a negative number inside vblank, counting the number 1826 * of scanlines to go until end of vblank, e.g., -1 means "one scanline 1827 * until start of active scanout / end of vblank." 1828 * 1829 * \return Flags, or'ed together as follows: 1830 * 1831 * DRM_SCANOUTPOS_VALID = Query successful. 1832 * DRM_SCANOUTPOS_INVBL = Inside vblank. 1833 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of 1834 * this flag means that returned position may be offset by a constant but 1835 * unknown small number of scanlines wrt. real scanout position. 1836 * 1837 */ 1838 int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, 1839 unsigned int flags, int *vpos, int *hpos, 1840 ktime_t *stime, ktime_t *etime, 1841 const struct drm_display_mode *mode) 1842 { 1843 u32 stat_crtc = 0, vbl = 0, position = 0; 1844 int vbl_start, vbl_end, vtotal, ret = 0; 1845 bool in_vbl = true; 1846 1847 struct radeon_device *rdev = dev->dev_private; 1848 1849 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ 1850 1851 /* Get optional system timestamp before query. */ 1852 if (stime) 1853 *stime = ktime_get(); 1854 1855 if (ASIC_IS_DCE4(rdev)) { 1856 if (pipe == 0) { 1857 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1858 EVERGREEN_CRTC0_REGISTER_OFFSET); 1859 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1860 EVERGREEN_CRTC0_REGISTER_OFFSET); 1861 ret |= DRM_SCANOUTPOS_VALID; 1862 } 1863 if (pipe == 1) { 1864 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1865 EVERGREEN_CRTC1_REGISTER_OFFSET); 1866 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1867 EVERGREEN_CRTC1_REGISTER_OFFSET); 1868 ret |= DRM_SCANOUTPOS_VALID; 1869 } 1870 if (pipe == 2) { 1871 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1872 EVERGREEN_CRTC2_REGISTER_OFFSET); 1873 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1874 EVERGREEN_CRTC2_REGISTER_OFFSET); 1875 ret |= DRM_SCANOUTPOS_VALID; 1876 } 1877 if (pipe == 3) { 1878 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1879 EVERGREEN_CRTC3_REGISTER_OFFSET); 1880 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1881 EVERGREEN_CRTC3_REGISTER_OFFSET); 1882 ret |= DRM_SCANOUTPOS_VALID; 1883 } 1884 if (pipe == 4) { 1885 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1886 EVERGREEN_CRTC4_REGISTER_OFFSET); 1887 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1888 EVERGREEN_CRTC4_REGISTER_OFFSET); 1889 ret |= DRM_SCANOUTPOS_VALID; 1890 } 1891 if (pipe == 5) { 1892 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1893 EVERGREEN_CRTC5_REGISTER_OFFSET); 1894 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1895 EVERGREEN_CRTC5_REGISTER_OFFSET); 1896 ret |= DRM_SCANOUTPOS_VALID; 1897 } 1898 } else if (ASIC_IS_AVIVO(rdev)) { 1899 if (pipe == 0) { 1900 vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END); 1901 position = RREG32(AVIVO_D1CRTC_STATUS_POSITION); 1902 ret |= DRM_SCANOUTPOS_VALID; 1903 } 1904 if (pipe == 1) { 1905 vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END); 1906 position = RREG32(AVIVO_D2CRTC_STATUS_POSITION); 1907 ret |= DRM_SCANOUTPOS_VALID; 1908 } 1909 } else { 1910 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */ 1911 if (pipe == 0) { 1912 /* Assume vbl_end == 0, get vbl_start from 1913 * upper 16 bits. 1914 */ 1915 vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) & 1916 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT; 1917 /* Only retrieve vpos from upper 16 bits, set hpos == 0. */ 1918 position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 1919 stat_crtc = RREG32(RADEON_CRTC_STATUS); 1920 if (!(stat_crtc & 1)) 1921 in_vbl = false; 1922 1923 ret |= DRM_SCANOUTPOS_VALID; 1924 } 1925 if (pipe == 1) { 1926 vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) & 1927 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT; 1928 position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 1929 stat_crtc = RREG32(RADEON_CRTC2_STATUS); 1930 if (!(stat_crtc & 1)) 1931 in_vbl = false; 1932 1933 ret |= DRM_SCANOUTPOS_VALID; 1934 } 1935 } 1936 1937 /* Get optional system timestamp after query. */ 1938 if (etime) 1939 *etime = ktime_get(); 1940 1941 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ 1942 1943 /* Decode into vertical and horizontal scanout position. */ 1944 *vpos = position & 0x1fff; 1945 *hpos = (position >> 16) & 0x1fff; 1946 1947 /* Valid vblank area boundaries from gpu retrieved? */ 1948 if (vbl > 0) { 1949 /* Yes: Decode. */ 1950 ret |= DRM_SCANOUTPOS_ACCURATE; 1951 vbl_start = vbl & 0x1fff; 1952 vbl_end = (vbl >> 16) & 0x1fff; 1953 } 1954 else { 1955 /* No: Fake something reasonable which gives at least ok results. */ 1956 vbl_start = mode->crtc_vdisplay; 1957 vbl_end = 0; 1958 } 1959 1960 /* Called from driver internal vblank counter query code? */ 1961 if (flags & GET_DISTANCE_TO_VBLANKSTART) { 1962 /* Caller wants distance from real vbl_start in *hpos */ 1963 *hpos = *vpos - vbl_start; 1964 } 1965 1966 /* Fudge vblank to start a few scanlines earlier to handle the 1967 * problem that vblank irqs fire a few scanlines before start 1968 * of vblank. Some driver internal callers need the true vblank 1969 * start to be used and signal this via the USE_REAL_VBLANKSTART flag. 1970 * 1971 * The cause of the "early" vblank irq is that the irq is triggered 1972 * by the line buffer logic when the line buffer read position enters 1973 * the vblank, whereas our crtc scanout position naturally lags the 1974 * line buffer read position. 1975 */ 1976 if (!(flags & USE_REAL_VBLANKSTART)) 1977 vbl_start -= rdev->mode_info.crtcs[pipe]->lb_vblank_lead_lines; 1978 1979 /* Test scanout position against vblank region. */ 1980 if ((*vpos < vbl_start) && (*vpos >= vbl_end)) 1981 in_vbl = false; 1982 1983 /* In vblank? */ 1984 if (in_vbl) 1985 ret |= DRM_SCANOUTPOS_IN_VBLANK; 1986 1987 /* Called from driver internal vblank counter query code? */ 1988 if (flags & GET_DISTANCE_TO_VBLANKSTART) { 1989 /* Caller wants distance from fudged earlier vbl_start */ 1990 *vpos -= vbl_start; 1991 return ret; 1992 } 1993 1994 /* Check if inside vblank area and apply corrective offsets: 1995 * vpos will then be >=0 in video scanout area, but negative 1996 * within vblank area, counting down the number of lines until 1997 * start of scanout. 1998 */ 1999 2000 /* Inside "upper part" of vblank area? Apply corrective offset if so: */ 2001 if (in_vbl && (*vpos >= vbl_start)) { 2002 vtotal = mode->crtc_vtotal; 2003 *vpos = *vpos - vtotal; 2004 } 2005 2006 /* Correct for shifted end of vbl at vbl_end. */ 2007 *vpos = *vpos - vbl_end; 2008 2009 return ret; 2010 } 2011