1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include <drm/drmP.h> 27 #include <drm/radeon_drm.h> 28 #include "radeon.h" 29 30 #include "atom.h" 31 #include <asm/div64.h> 32 33 #include <linux/pm_runtime.h> 34 #include <drm/drm_crtc_helper.h> 35 #include <drm/drm_plane_helper.h> 36 #include <drm/drm_edid.h> 37 38 #include <linux/gcd.h> 39 40 static void avivo_crtc_load_lut(struct drm_crtc *crtc) 41 { 42 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 43 struct drm_device *dev = crtc->dev; 44 struct radeon_device *rdev = dev->dev_private; 45 int i; 46 47 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); 48 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); 49 50 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 51 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 52 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 53 54 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 55 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 56 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 57 58 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id); 59 WREG32(AVIVO_DC_LUT_RW_MODE, 0); 60 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f); 61 62 WREG8(AVIVO_DC_LUT_RW_INDEX, 0); 63 for (i = 0; i < 256; i++) { 64 WREG32(AVIVO_DC_LUT_30_COLOR, 65 (radeon_crtc->lut_r[i] << 20) | 66 (radeon_crtc->lut_g[i] << 10) | 67 (radeon_crtc->lut_b[i] << 0)); 68 } 69 70 /* Only change bit 0 of LUT_SEL, other bits are set elsewhere */ 71 WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1); 72 } 73 74 static void dce4_crtc_load_lut(struct drm_crtc *crtc) 75 { 76 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 77 struct drm_device *dev = crtc->dev; 78 struct radeon_device *rdev = dev->dev_private; 79 int i; 80 81 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); 82 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); 83 84 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 85 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 86 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 87 88 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 89 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 90 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 91 92 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); 93 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); 94 95 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); 96 for (i = 0; i < 256; i++) { 97 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, 98 (radeon_crtc->lut_r[i] << 20) | 99 (radeon_crtc->lut_g[i] << 10) | 100 (radeon_crtc->lut_b[i] << 0)); 101 } 102 } 103 104 static void dce5_crtc_load_lut(struct drm_crtc *crtc) 105 { 106 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 107 struct drm_device *dev = crtc->dev; 108 struct radeon_device *rdev = dev->dev_private; 109 int i; 110 111 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); 112 113 WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset, 114 (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) | 115 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS))); 116 WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset, 117 NI_GRPH_PRESCALE_BYPASS); 118 WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset, 119 NI_OVL_PRESCALE_BYPASS); 120 WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset, 121 (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) | 122 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT))); 123 124 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); 125 126 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 127 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 128 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 129 130 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 131 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 132 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 133 134 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); 135 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); 136 137 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); 138 for (i = 0; i < 256; i++) { 139 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, 140 (radeon_crtc->lut_r[i] << 20) | 141 (radeon_crtc->lut_g[i] << 10) | 142 (radeon_crtc->lut_b[i] << 0)); 143 } 144 145 WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset, 146 (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 147 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 148 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 149 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS))); 150 WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset, 151 (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) | 152 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS))); 153 WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset, 154 (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) | 155 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS))); 156 WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset, 157 (NI_OUTPUT_CSC_GRPH_MODE(radeon_crtc->output_csc) | 158 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS))); 159 /* XXX match this to the depth of the crtc fmt block, move to modeset? */ 160 WREG32(0x6940 + radeon_crtc->crtc_offset, 0); 161 if (ASIC_IS_DCE8(rdev)) { 162 /* XXX this only needs to be programmed once per crtc at startup, 163 * not sure where the best place for it is 164 */ 165 WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset, 166 CIK_CURSOR_ALPHA_BLND_ENA); 167 } 168 } 169 170 static void legacy_crtc_load_lut(struct drm_crtc *crtc) 171 { 172 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 173 struct drm_device *dev = crtc->dev; 174 struct radeon_device *rdev = dev->dev_private; 175 int i; 176 uint32_t dac2_cntl; 177 178 dac2_cntl = RREG32(RADEON_DAC_CNTL2); 179 if (radeon_crtc->crtc_id == 0) 180 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL; 181 else 182 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL; 183 WREG32(RADEON_DAC_CNTL2, dac2_cntl); 184 185 WREG8(RADEON_PALETTE_INDEX, 0); 186 for (i = 0; i < 256; i++) { 187 WREG32(RADEON_PALETTE_30_DATA, 188 (radeon_crtc->lut_r[i] << 20) | 189 (radeon_crtc->lut_g[i] << 10) | 190 (radeon_crtc->lut_b[i] << 0)); 191 } 192 } 193 194 void radeon_crtc_load_lut(struct drm_crtc *crtc) 195 { 196 struct drm_device *dev = crtc->dev; 197 struct radeon_device *rdev = dev->dev_private; 198 199 if (!crtc->enabled) 200 return; 201 202 if (ASIC_IS_DCE5(rdev)) 203 dce5_crtc_load_lut(crtc); 204 else if (ASIC_IS_DCE4(rdev)) 205 dce4_crtc_load_lut(crtc); 206 else if (ASIC_IS_AVIVO(rdev)) 207 avivo_crtc_load_lut(crtc); 208 else 209 legacy_crtc_load_lut(crtc); 210 } 211 212 /** Sets the color ramps on behalf of fbcon */ 213 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, 214 u16 blue, int regno) 215 { 216 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 217 218 radeon_crtc->lut_r[regno] = red >> 6; 219 radeon_crtc->lut_g[regno] = green >> 6; 220 radeon_crtc->lut_b[regno] = blue >> 6; 221 } 222 223 /** Gets the color ramps on behalf of fbcon */ 224 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, 225 u16 *blue, int regno) 226 { 227 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 228 229 *red = radeon_crtc->lut_r[regno] << 6; 230 *green = radeon_crtc->lut_g[regno] << 6; 231 *blue = radeon_crtc->lut_b[regno] << 6; 232 } 233 234 static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 235 u16 *blue, uint32_t start, uint32_t size) 236 { 237 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 238 int end = (start + size > 256) ? 256 : start + size, i; 239 240 /* userspace palettes are always correct as is */ 241 for (i = start; i < end; i++) { 242 radeon_crtc->lut_r[i] = red[i] >> 6; 243 radeon_crtc->lut_g[i] = green[i] >> 6; 244 radeon_crtc->lut_b[i] = blue[i] >> 6; 245 } 246 radeon_crtc_load_lut(crtc); 247 } 248 249 static void radeon_crtc_destroy(struct drm_crtc *crtc) 250 { 251 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 252 253 drm_crtc_cleanup(crtc); 254 destroy_workqueue(radeon_crtc->flip_queue); 255 kfree(radeon_crtc); 256 } 257 258 /** 259 * radeon_unpin_work_func - unpin old buffer object 260 * 261 * @__work - kernel work item 262 * 263 * Unpin the old frame buffer object outside of the interrupt handler 264 */ 265 static void radeon_unpin_work_func(struct work_struct *__work) 266 { 267 struct radeon_flip_work *work = 268 container_of(__work, struct radeon_flip_work, unpin_work); 269 int r; 270 271 /* unpin of the old buffer */ 272 r = radeon_bo_reserve(work->old_rbo, false); 273 if (likely(r == 0)) { 274 r = radeon_bo_unpin(work->old_rbo); 275 if (unlikely(r != 0)) { 276 DRM_ERROR("failed to unpin buffer after flip\n"); 277 } 278 radeon_bo_unreserve(work->old_rbo); 279 } else 280 DRM_ERROR("failed to reserve buffer after flip\n"); 281 282 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base); 283 kfree(work); 284 } 285 286 void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id) 287 { 288 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 289 unsigned long flags; 290 u32 update_pending; 291 int vpos, hpos; 292 293 /* can happen during initialization */ 294 if (radeon_crtc == NULL) 295 return; 296 297 /* Skip the pageflip completion check below (based on polling) on 298 * asics which reliably support hw pageflip completion irqs. pflip 299 * irqs are a reliable and race-free method of handling pageflip 300 * completion detection. A use_pflipirq module parameter < 2 allows 301 * to override this in case of asics with faulty pflip irqs. 302 * A module parameter of 0 would only use this polling based path, 303 * a parameter of 1 would use pflip irq only as a backup to this 304 * path, as in Linux 3.16. 305 */ 306 if ((radeon_use_pflipirq == 2) && ASIC_IS_DCE4(rdev)) 307 return; 308 309 spin_lock_irqsave(&rdev->ddev->event_lock, flags); 310 if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) { 311 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != " 312 "RADEON_FLIP_SUBMITTED(%d)\n", 313 radeon_crtc->flip_status, 314 RADEON_FLIP_SUBMITTED); 315 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); 316 return; 317 } 318 319 update_pending = radeon_page_flip_pending(rdev, crtc_id); 320 321 /* Has the pageflip already completed in crtc, or is it certain 322 * to complete in this vblank? 323 */ 324 if (update_pending && 325 (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, 326 crtc_id, 327 USE_REAL_VBLANKSTART, 328 &vpos, &hpos, NULL, NULL, 329 &rdev->mode_info.crtcs[crtc_id]->base.hwmode)) && 330 ((vpos >= (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100) || 331 (vpos < 0 && !ASIC_IS_AVIVO(rdev)))) { 332 /* crtc didn't flip in this target vblank interval, 333 * but flip is pending in crtc. Based on the current 334 * scanout position we know that the current frame is 335 * (nearly) complete and the flip will (likely) 336 * complete before the start of the next frame. 337 */ 338 update_pending = 0; 339 } 340 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); 341 if (!update_pending) 342 radeon_crtc_handle_flip(rdev, crtc_id); 343 } 344 345 /** 346 * radeon_crtc_handle_flip - page flip completed 347 * 348 * @rdev: radeon device pointer 349 * @crtc_id: crtc number this event is for 350 * 351 * Called when we are sure that a page flip for this crtc is completed. 352 */ 353 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id) 354 { 355 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 356 struct radeon_flip_work *work; 357 unsigned long flags; 358 359 /* this can happen at init */ 360 if (radeon_crtc == NULL) 361 return; 362 363 spin_lock_irqsave(&rdev->ddev->event_lock, flags); 364 work = radeon_crtc->flip_work; 365 if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) { 366 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != " 367 "RADEON_FLIP_SUBMITTED(%d)\n", 368 radeon_crtc->flip_status, 369 RADEON_FLIP_SUBMITTED); 370 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); 371 return; 372 } 373 374 /* Pageflip completed. Clean up. */ 375 radeon_crtc->flip_status = RADEON_FLIP_NONE; 376 radeon_crtc->flip_work = NULL; 377 378 /* wakeup userspace */ 379 if (work->event) 380 drm_send_vblank_event(rdev->ddev, crtc_id, work->event); 381 382 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); 383 384 drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id); 385 radeon_irq_kms_pflip_irq_put(rdev, work->crtc_id); 386 queue_work(radeon_crtc->flip_queue, &work->unpin_work); 387 } 388 389 /** 390 * radeon_flip_work_func - page flip framebuffer 391 * 392 * @work - kernel work item 393 * 394 * Wait for the buffer object to become idle and do the actual page flip 395 */ 396 static void radeon_flip_work_func(struct work_struct *__work) 397 { 398 struct radeon_flip_work *work = 399 container_of(__work, struct radeon_flip_work, flip_work); 400 struct radeon_device *rdev = work->rdev; 401 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[work->crtc_id]; 402 403 struct drm_crtc *crtc = &radeon_crtc->base; 404 unsigned long flags; 405 int r; 406 int vpos, hpos, stat, min_udelay; 407 struct drm_vblank_crtc *vblank = &crtc->dev->vblank[work->crtc_id]; 408 409 down_read(&rdev->exclusive_lock); 410 if (work->fence) { 411 struct radeon_fence *fence; 412 413 fence = to_radeon_fence(work->fence); 414 if (fence && fence->rdev == rdev) { 415 r = radeon_fence_wait(fence, false); 416 if (r == -EDEADLK) { 417 up_read(&rdev->exclusive_lock); 418 do { 419 r = radeon_gpu_reset(rdev); 420 } while (r == -EAGAIN); 421 down_read(&rdev->exclusive_lock); 422 } 423 } else 424 r = fence_wait(work->fence, false); 425 426 if (r) 427 DRM_ERROR("failed to wait on page flip fence (%d)!\n", r); 428 429 /* We continue with the page flip even if we failed to wait on 430 * the fence, otherwise the DRM core and userspace will be 431 * confused about which BO the CRTC is scanning out 432 */ 433 434 fence_put(work->fence); 435 work->fence = NULL; 436 } 437 438 /* We borrow the event spin lock for protecting flip_status */ 439 spin_lock_irqsave(&crtc->dev->event_lock, flags); 440 441 /* set the proper interrupt */ 442 radeon_irq_kms_pflip_irq_get(rdev, radeon_crtc->crtc_id); 443 444 /* If this happens to execute within the "virtually extended" vblank 445 * interval before the start of the real vblank interval then it needs 446 * to delay programming the mmio flip until the real vblank is entered. 447 * This prevents completing a flip too early due to the way we fudge 448 * our vblank counter and vblank timestamps in order to work around the 449 * problem that the hw fires vblank interrupts before actual start of 450 * vblank (when line buffer refilling is done for a frame). It 451 * complements the fudging logic in radeon_get_crtc_scanoutpos() for 452 * timestamping and radeon_get_vblank_counter_kms() for vblank counts. 453 * 454 * In practice this won't execute very often unless on very fast 455 * machines because the time window for this to happen is very small. 456 */ 457 for (;;) { 458 /* GET_DISTANCE_TO_VBLANKSTART returns distance to real vblank 459 * start in hpos, and to the "fudged earlier" vblank start in 460 * vpos. 461 */ 462 stat = radeon_get_crtc_scanoutpos(rdev->ddev, work->crtc_id, 463 GET_DISTANCE_TO_VBLANKSTART, 464 &vpos, &hpos, NULL, NULL, 465 &crtc->hwmode); 466 467 if ((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 468 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE) || 469 !(vpos >= 0 && hpos <= 0)) 470 break; 471 472 /* Sleep at least until estimated real start of hw vblank */ 473 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 474 min_udelay = (-hpos + 1) * max(vblank->linedur_ns / 1000, 5); 475 usleep_range(min_udelay, 2 * min_udelay); 476 spin_lock_irqsave(&crtc->dev->event_lock, flags); 477 }; 478 479 /* do the flip (mmio) */ 480 radeon_page_flip(rdev, radeon_crtc->crtc_id, work->base); 481 482 radeon_crtc->flip_status = RADEON_FLIP_SUBMITTED; 483 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 484 up_read(&rdev->exclusive_lock); 485 } 486 487 static int radeon_crtc_page_flip(struct drm_crtc *crtc, 488 struct drm_framebuffer *fb, 489 struct drm_pending_vblank_event *event, 490 uint32_t page_flip_flags) 491 { 492 struct drm_device *dev = crtc->dev; 493 struct radeon_device *rdev = dev->dev_private; 494 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 495 struct radeon_framebuffer *old_radeon_fb; 496 struct radeon_framebuffer *new_radeon_fb; 497 struct drm_gem_object *obj; 498 struct radeon_flip_work *work; 499 struct radeon_bo *new_rbo; 500 uint32_t tiling_flags, pitch_pixels; 501 uint64_t base; 502 unsigned long flags; 503 int r; 504 505 work = kzalloc(sizeof *work, GFP_KERNEL); 506 if (work == NULL) 507 return -ENOMEM; 508 509 INIT_WORK(&work->flip_work, radeon_flip_work_func); 510 INIT_WORK(&work->unpin_work, radeon_unpin_work_func); 511 512 work->rdev = rdev; 513 work->crtc_id = radeon_crtc->crtc_id; 514 work->event = event; 515 516 /* schedule unpin of the old buffer */ 517 old_radeon_fb = to_radeon_framebuffer(crtc->primary->fb); 518 obj = old_radeon_fb->obj; 519 520 /* take a reference to the old object */ 521 drm_gem_object_reference(obj); 522 work->old_rbo = gem_to_radeon_bo(obj); 523 524 new_radeon_fb = to_radeon_framebuffer(fb); 525 obj = new_radeon_fb->obj; 526 new_rbo = gem_to_radeon_bo(obj); 527 528 /* pin the new buffer */ 529 DRM_DEBUG_DRIVER("flip-ioctl() cur_rbo = %p, new_rbo = %p\n", 530 work->old_rbo, new_rbo); 531 532 r = radeon_bo_reserve(new_rbo, false); 533 if (unlikely(r != 0)) { 534 DRM_ERROR("failed to reserve new rbo buffer before flip\n"); 535 goto cleanup; 536 } 537 /* Only 27 bit offset for legacy CRTC */ 538 r = radeon_bo_pin_restricted(new_rbo, RADEON_GEM_DOMAIN_VRAM, 539 ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base); 540 if (unlikely(r != 0)) { 541 radeon_bo_unreserve(new_rbo); 542 r = -EINVAL; 543 DRM_ERROR("failed to pin new rbo buffer before flip\n"); 544 goto cleanup; 545 } 546 work->fence = fence_get(reservation_object_get_excl(new_rbo->tbo.resv)); 547 radeon_bo_get_tiling_flags(new_rbo, &tiling_flags, NULL); 548 radeon_bo_unreserve(new_rbo); 549 550 if (!ASIC_IS_AVIVO(rdev)) { 551 /* crtc offset is from display base addr not FB location */ 552 base -= radeon_crtc->legacy_display_base_addr; 553 pitch_pixels = fb->pitches[0] / (fb->bits_per_pixel / 8); 554 555 if (tiling_flags & RADEON_TILING_MACRO) { 556 if (ASIC_IS_R300(rdev)) { 557 base &= ~0x7ff; 558 } else { 559 int byteshift = fb->bits_per_pixel >> 4; 560 int tile_addr = (((crtc->y >> 3) * pitch_pixels + crtc->x) >> (8 - byteshift)) << 11; 561 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8); 562 } 563 } else { 564 int offset = crtc->y * pitch_pixels + crtc->x; 565 switch (fb->bits_per_pixel) { 566 case 8: 567 default: 568 offset *= 1; 569 break; 570 case 15: 571 case 16: 572 offset *= 2; 573 break; 574 case 24: 575 offset *= 3; 576 break; 577 case 32: 578 offset *= 4; 579 break; 580 } 581 base += offset; 582 } 583 base &= ~7; 584 } 585 work->base = base; 586 587 r = drm_vblank_get(crtc->dev, radeon_crtc->crtc_id); 588 if (r) { 589 DRM_ERROR("failed to get vblank before flip\n"); 590 goto pflip_cleanup; 591 } 592 593 /* We borrow the event spin lock for protecting flip_work */ 594 spin_lock_irqsave(&crtc->dev->event_lock, flags); 595 596 if (radeon_crtc->flip_status != RADEON_FLIP_NONE) { 597 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); 598 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 599 r = -EBUSY; 600 goto vblank_cleanup; 601 } 602 radeon_crtc->flip_status = RADEON_FLIP_PENDING; 603 radeon_crtc->flip_work = work; 604 605 /* update crtc fb */ 606 crtc->primary->fb = fb; 607 608 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 609 610 queue_work(radeon_crtc->flip_queue, &work->flip_work); 611 return 0; 612 613 vblank_cleanup: 614 drm_vblank_put(crtc->dev, radeon_crtc->crtc_id); 615 616 pflip_cleanup: 617 if (unlikely(radeon_bo_reserve(new_rbo, false) != 0)) { 618 DRM_ERROR("failed to reserve new rbo in error path\n"); 619 goto cleanup; 620 } 621 if (unlikely(radeon_bo_unpin(new_rbo) != 0)) { 622 DRM_ERROR("failed to unpin new rbo in error path\n"); 623 } 624 radeon_bo_unreserve(new_rbo); 625 626 cleanup: 627 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base); 628 fence_put(work->fence); 629 kfree(work); 630 return r; 631 } 632 633 static int 634 radeon_crtc_set_config(struct drm_mode_set *set) 635 { 636 struct drm_device *dev; 637 struct radeon_device *rdev; 638 struct drm_crtc *crtc; 639 bool active = false; 640 int ret; 641 642 if (!set || !set->crtc) 643 return -EINVAL; 644 645 dev = set->crtc->dev; 646 647 ret = pm_runtime_get_sync(dev->dev); 648 if (ret < 0) 649 return ret; 650 651 ret = drm_crtc_helper_set_config(set); 652 653 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) 654 if (crtc->enabled) 655 active = true; 656 657 pm_runtime_mark_last_busy(dev->dev); 658 659 rdev = dev->dev_private; 660 /* if we have active crtcs and we don't have a power ref, 661 take the current one */ 662 if (active && !rdev->have_disp_power_ref) { 663 rdev->have_disp_power_ref = true; 664 return ret; 665 } 666 /* if we have no active crtcs, then drop the power ref 667 we got before */ 668 if (!active && rdev->have_disp_power_ref) { 669 pm_runtime_put_autosuspend(dev->dev); 670 rdev->have_disp_power_ref = false; 671 } 672 673 /* drop the power reference we got coming in here */ 674 pm_runtime_put_autosuspend(dev->dev); 675 return ret; 676 } 677 static const struct drm_crtc_funcs radeon_crtc_funcs = { 678 .cursor_set2 = radeon_crtc_cursor_set2, 679 .cursor_move = radeon_crtc_cursor_move, 680 .gamma_set = radeon_crtc_gamma_set, 681 .set_config = radeon_crtc_set_config, 682 .destroy = radeon_crtc_destroy, 683 .page_flip = radeon_crtc_page_flip, 684 }; 685 686 static void radeon_crtc_init(struct drm_device *dev, int index) 687 { 688 struct radeon_device *rdev = dev->dev_private; 689 struct radeon_crtc *radeon_crtc; 690 int i; 691 692 radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); 693 if (radeon_crtc == NULL) 694 return; 695 696 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs); 697 698 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256); 699 radeon_crtc->crtc_id = index; 700 radeon_crtc->flip_queue = create_singlethread_workqueue("radeon-crtc"); 701 rdev->mode_info.crtcs[index] = radeon_crtc; 702 703 if (rdev->family >= CHIP_BONAIRE) { 704 radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH; 705 radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT; 706 } else { 707 radeon_crtc->max_cursor_width = CURSOR_WIDTH; 708 radeon_crtc->max_cursor_height = CURSOR_HEIGHT; 709 } 710 dev->mode_config.cursor_width = radeon_crtc->max_cursor_width; 711 dev->mode_config.cursor_height = radeon_crtc->max_cursor_height; 712 713 #if 0 714 radeon_crtc->mode_set.crtc = &radeon_crtc->base; 715 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1); 716 radeon_crtc->mode_set.num_connectors = 0; 717 #endif 718 719 for (i = 0; i < 256; i++) { 720 radeon_crtc->lut_r[i] = i << 2; 721 radeon_crtc->lut_g[i] = i << 2; 722 radeon_crtc->lut_b[i] = i << 2; 723 } 724 725 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)) 726 radeon_atombios_init_crtc(dev, radeon_crtc); 727 else 728 radeon_legacy_init_crtc(dev, radeon_crtc); 729 } 730 731 static const char *encoder_names[38] = { 732 "NONE", 733 "INTERNAL_LVDS", 734 "INTERNAL_TMDS1", 735 "INTERNAL_TMDS2", 736 "INTERNAL_DAC1", 737 "INTERNAL_DAC2", 738 "INTERNAL_SDVOA", 739 "INTERNAL_SDVOB", 740 "SI170B", 741 "CH7303", 742 "CH7301", 743 "INTERNAL_DVO1", 744 "EXTERNAL_SDVOA", 745 "EXTERNAL_SDVOB", 746 "TITFP513", 747 "INTERNAL_LVTM1", 748 "VT1623", 749 "HDMI_SI1930", 750 "HDMI_INTERNAL", 751 "INTERNAL_KLDSCP_TMDS1", 752 "INTERNAL_KLDSCP_DVO1", 753 "INTERNAL_KLDSCP_DAC1", 754 "INTERNAL_KLDSCP_DAC2", 755 "SI178", 756 "MVPU_FPGA", 757 "INTERNAL_DDI", 758 "VT1625", 759 "HDMI_SI1932", 760 "DP_AN9801", 761 "DP_DP501", 762 "INTERNAL_UNIPHY", 763 "INTERNAL_KLDSCP_LVTMA", 764 "INTERNAL_UNIPHY1", 765 "INTERNAL_UNIPHY2", 766 "NUTMEG", 767 "TRAVIS", 768 "INTERNAL_VCE", 769 "INTERNAL_UNIPHY3", 770 }; 771 772 static const char *hpd_names[6] = { 773 "HPD1", 774 "HPD2", 775 "HPD3", 776 "HPD4", 777 "HPD5", 778 "HPD6", 779 }; 780 781 static void radeon_print_display_setup(struct drm_device *dev) 782 { 783 struct drm_connector *connector; 784 struct radeon_connector *radeon_connector; 785 struct drm_encoder *encoder; 786 struct radeon_encoder *radeon_encoder; 787 uint32_t devices; 788 int i = 0; 789 790 DRM_INFO("Radeon Display Connectors\n"); 791 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 792 radeon_connector = to_radeon_connector(connector); 793 DRM_INFO("Connector %d:\n", i); 794 DRM_INFO(" %s\n", connector->name); 795 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) 796 DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]); 797 if (radeon_connector->ddc_bus) { 798 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", 799 radeon_connector->ddc_bus->rec.mask_clk_reg, 800 radeon_connector->ddc_bus->rec.mask_data_reg, 801 radeon_connector->ddc_bus->rec.a_clk_reg, 802 radeon_connector->ddc_bus->rec.a_data_reg, 803 radeon_connector->ddc_bus->rec.en_clk_reg, 804 radeon_connector->ddc_bus->rec.en_data_reg, 805 radeon_connector->ddc_bus->rec.y_clk_reg, 806 radeon_connector->ddc_bus->rec.y_data_reg); 807 if (radeon_connector->router.ddc_valid) 808 DRM_INFO(" DDC Router 0x%x/0x%x\n", 809 radeon_connector->router.ddc_mux_control_pin, 810 radeon_connector->router.ddc_mux_state); 811 if (radeon_connector->router.cd_valid) 812 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n", 813 radeon_connector->router.cd_mux_control_pin, 814 radeon_connector->router.cd_mux_state); 815 } else { 816 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || 817 connector->connector_type == DRM_MODE_CONNECTOR_DVII || 818 connector->connector_type == DRM_MODE_CONNECTOR_DVID || 819 connector->connector_type == DRM_MODE_CONNECTOR_DVIA || 820 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || 821 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) 822 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n"); 823 } 824 DRM_INFO(" Encoders:\n"); 825 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 826 radeon_encoder = to_radeon_encoder(encoder); 827 devices = radeon_encoder->devices & radeon_connector->devices; 828 if (devices) { 829 if (devices & ATOM_DEVICE_CRT1_SUPPORT) 830 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]); 831 if (devices & ATOM_DEVICE_CRT2_SUPPORT) 832 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]); 833 if (devices & ATOM_DEVICE_LCD1_SUPPORT) 834 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]); 835 if (devices & ATOM_DEVICE_DFP1_SUPPORT) 836 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]); 837 if (devices & ATOM_DEVICE_DFP2_SUPPORT) 838 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]); 839 if (devices & ATOM_DEVICE_DFP3_SUPPORT) 840 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]); 841 if (devices & ATOM_DEVICE_DFP4_SUPPORT) 842 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]); 843 if (devices & ATOM_DEVICE_DFP5_SUPPORT) 844 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]); 845 if (devices & ATOM_DEVICE_DFP6_SUPPORT) 846 DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]); 847 if (devices & ATOM_DEVICE_TV1_SUPPORT) 848 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]); 849 if (devices & ATOM_DEVICE_CV_SUPPORT) 850 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]); 851 } 852 } 853 i++; 854 } 855 } 856 857 static bool radeon_setup_enc_conn(struct drm_device *dev) 858 { 859 struct radeon_device *rdev = dev->dev_private; 860 bool ret = false; 861 862 if (rdev->bios) { 863 if (rdev->is_atom_bios) { 864 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev); 865 if (ret == false) 866 ret = radeon_get_atom_connector_info_from_object_table(dev); 867 } else { 868 ret = radeon_get_legacy_connector_info_from_bios(dev); 869 if (ret == false) 870 ret = radeon_get_legacy_connector_info_from_table(dev); 871 } 872 } else { 873 if (!ASIC_IS_AVIVO(rdev)) 874 ret = radeon_get_legacy_connector_info_from_table(dev); 875 } 876 if (ret) { 877 radeon_setup_encoder_clones(dev); 878 radeon_print_display_setup(dev); 879 } 880 881 return ret; 882 } 883 884 /* avivo */ 885 886 /** 887 * avivo_reduce_ratio - fractional number reduction 888 * 889 * @nom: nominator 890 * @den: denominator 891 * @nom_min: minimum value for nominator 892 * @den_min: minimum value for denominator 893 * 894 * Find the greatest common divisor and apply it on both nominator and 895 * denominator, but make nominator and denominator are at least as large 896 * as their minimum values. 897 */ 898 static void avivo_reduce_ratio(unsigned *nom, unsigned *den, 899 unsigned nom_min, unsigned den_min) 900 { 901 unsigned tmp; 902 903 /* reduce the numbers to a simpler ratio */ 904 tmp = gcd(*nom, *den); 905 *nom /= tmp; 906 *den /= tmp; 907 908 /* make sure nominator is large enough */ 909 if (*nom < nom_min) { 910 tmp = DIV_ROUND_UP(nom_min, *nom); 911 *nom *= tmp; 912 *den *= tmp; 913 } 914 915 /* make sure the denominator is large enough */ 916 if (*den < den_min) { 917 tmp = DIV_ROUND_UP(den_min, *den); 918 *nom *= tmp; 919 *den *= tmp; 920 } 921 } 922 923 /** 924 * avivo_get_fb_ref_div - feedback and ref divider calculation 925 * 926 * @nom: nominator 927 * @den: denominator 928 * @post_div: post divider 929 * @fb_div_max: feedback divider maximum 930 * @ref_div_max: reference divider maximum 931 * @fb_div: resulting feedback divider 932 * @ref_div: resulting reference divider 933 * 934 * Calculate feedback and reference divider for a given post divider. Makes 935 * sure we stay within the limits. 936 */ 937 static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div, 938 unsigned fb_div_max, unsigned ref_div_max, 939 unsigned *fb_div, unsigned *ref_div) 940 { 941 /* limit reference * post divider to a maximum */ 942 ref_div_max = max(min(100 / post_div, ref_div_max), 1u); 943 944 /* get matching reference and feedback divider */ 945 *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max); 946 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den); 947 948 /* limit fb divider to its maximum */ 949 if (*fb_div > fb_div_max) { 950 *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div); 951 *fb_div = fb_div_max; 952 } 953 } 954 955 /** 956 * radeon_compute_pll_avivo - compute PLL paramaters 957 * 958 * @pll: information about the PLL 959 * @dot_clock_p: resulting pixel clock 960 * fb_div_p: resulting feedback divider 961 * frac_fb_div_p: fractional part of the feedback divider 962 * ref_div_p: resulting reference divider 963 * post_div_p: resulting reference divider 964 * 965 * Try to calculate the PLL parameters to generate the given frequency: 966 * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div) 967 */ 968 void radeon_compute_pll_avivo(struct radeon_pll *pll, 969 u32 freq, 970 u32 *dot_clock_p, 971 u32 *fb_div_p, 972 u32 *frac_fb_div_p, 973 u32 *ref_div_p, 974 u32 *post_div_p) 975 { 976 unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ? 977 freq : freq / 10; 978 979 unsigned fb_div_min, fb_div_max, fb_div; 980 unsigned post_div_min, post_div_max, post_div; 981 unsigned ref_div_min, ref_div_max, ref_div; 982 unsigned post_div_best, diff_best; 983 unsigned nom, den; 984 985 /* determine allowed feedback divider range */ 986 fb_div_min = pll->min_feedback_div; 987 fb_div_max = pll->max_feedback_div; 988 989 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 990 fb_div_min *= 10; 991 fb_div_max *= 10; 992 } 993 994 /* determine allowed ref divider range */ 995 if (pll->flags & RADEON_PLL_USE_REF_DIV) 996 ref_div_min = pll->reference_div; 997 else 998 ref_div_min = pll->min_ref_div; 999 1000 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && 1001 pll->flags & RADEON_PLL_USE_REF_DIV) 1002 ref_div_max = pll->reference_div; 1003 else if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) 1004 /* fix for problems on RS880 */ 1005 ref_div_max = min(pll->max_ref_div, 7u); 1006 else 1007 ref_div_max = pll->max_ref_div; 1008 1009 /* determine allowed post divider range */ 1010 if (pll->flags & RADEON_PLL_USE_POST_DIV) { 1011 post_div_min = pll->post_div; 1012 post_div_max = pll->post_div; 1013 } else { 1014 unsigned vco_min, vco_max; 1015 1016 if (pll->flags & RADEON_PLL_IS_LCD) { 1017 vco_min = pll->lcd_pll_out_min; 1018 vco_max = pll->lcd_pll_out_max; 1019 } else { 1020 vco_min = pll->pll_out_min; 1021 vco_max = pll->pll_out_max; 1022 } 1023 1024 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 1025 vco_min *= 10; 1026 vco_max *= 10; 1027 } 1028 1029 post_div_min = vco_min / target_clock; 1030 if ((target_clock * post_div_min) < vco_min) 1031 ++post_div_min; 1032 if (post_div_min < pll->min_post_div) 1033 post_div_min = pll->min_post_div; 1034 1035 post_div_max = vco_max / target_clock; 1036 if ((target_clock * post_div_max) > vco_max) 1037 --post_div_max; 1038 if (post_div_max > pll->max_post_div) 1039 post_div_max = pll->max_post_div; 1040 } 1041 1042 /* represent the searched ratio as fractional number */ 1043 nom = target_clock; 1044 den = pll->reference_freq; 1045 1046 /* reduce the numbers to a simpler ratio */ 1047 avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min); 1048 1049 /* now search for a post divider */ 1050 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) 1051 post_div_best = post_div_min; 1052 else 1053 post_div_best = post_div_max; 1054 diff_best = ~0; 1055 1056 for (post_div = post_div_min; post_div <= post_div_max; ++post_div) { 1057 unsigned diff; 1058 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, 1059 ref_div_max, &fb_div, &ref_div); 1060 diff = abs(target_clock - (pll->reference_freq * fb_div) / 1061 (ref_div * post_div)); 1062 1063 if (diff < diff_best || (diff == diff_best && 1064 !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) { 1065 1066 post_div_best = post_div; 1067 diff_best = diff; 1068 } 1069 } 1070 post_div = post_div_best; 1071 1072 /* get the feedback and reference divider for the optimal value */ 1073 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max, 1074 &fb_div, &ref_div); 1075 1076 /* reduce the numbers to a simpler ratio once more */ 1077 /* this also makes sure that the reference divider is large enough */ 1078 avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min); 1079 1080 /* avoid high jitter with small fractional dividers */ 1081 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) { 1082 fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 50); 1083 if (fb_div < fb_div_min) { 1084 unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div); 1085 fb_div *= tmp; 1086 ref_div *= tmp; 1087 } 1088 } 1089 1090 /* and finally save the result */ 1091 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 1092 *fb_div_p = fb_div / 10; 1093 *frac_fb_div_p = fb_div % 10; 1094 } else { 1095 *fb_div_p = fb_div; 1096 *frac_fb_div_p = 0; 1097 } 1098 1099 *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) + 1100 (pll->reference_freq * *frac_fb_div_p)) / 1101 (ref_div * post_div * 10); 1102 *ref_div_p = ref_div; 1103 *post_div_p = post_div; 1104 1105 DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n", 1106 freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p, 1107 ref_div, post_div); 1108 } 1109 1110 /* pre-avivo */ 1111 static inline uint32_t radeon_div(uint64_t n, uint32_t d) 1112 { 1113 uint64_t mod; 1114 1115 n += d / 2; 1116 1117 mod = do_div(n, d); 1118 return n; 1119 } 1120 1121 void radeon_compute_pll_legacy(struct radeon_pll *pll, 1122 uint64_t freq, 1123 uint32_t *dot_clock_p, 1124 uint32_t *fb_div_p, 1125 uint32_t *frac_fb_div_p, 1126 uint32_t *ref_div_p, 1127 uint32_t *post_div_p) 1128 { 1129 uint32_t min_ref_div = pll->min_ref_div; 1130 uint32_t max_ref_div = pll->max_ref_div; 1131 uint32_t min_post_div = pll->min_post_div; 1132 uint32_t max_post_div = pll->max_post_div; 1133 uint32_t min_fractional_feed_div = 0; 1134 uint32_t max_fractional_feed_div = 0; 1135 uint32_t best_vco = pll->best_vco; 1136 uint32_t best_post_div = 1; 1137 uint32_t best_ref_div = 1; 1138 uint32_t best_feedback_div = 1; 1139 uint32_t best_frac_feedback_div = 0; 1140 uint32_t best_freq = -1; 1141 uint32_t best_error = 0xffffffff; 1142 uint32_t best_vco_diff = 1; 1143 uint32_t post_div; 1144 u32 pll_out_min, pll_out_max; 1145 1146 DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div); 1147 freq = freq * 1000; 1148 1149 if (pll->flags & RADEON_PLL_IS_LCD) { 1150 pll_out_min = pll->lcd_pll_out_min; 1151 pll_out_max = pll->lcd_pll_out_max; 1152 } else { 1153 pll_out_min = pll->pll_out_min; 1154 pll_out_max = pll->pll_out_max; 1155 } 1156 1157 if (pll_out_min > 64800) 1158 pll_out_min = 64800; 1159 1160 if (pll->flags & RADEON_PLL_USE_REF_DIV) 1161 min_ref_div = max_ref_div = pll->reference_div; 1162 else { 1163 while (min_ref_div < max_ref_div-1) { 1164 uint32_t mid = (min_ref_div + max_ref_div) / 2; 1165 uint32_t pll_in = pll->reference_freq / mid; 1166 if (pll_in < pll->pll_in_min) 1167 max_ref_div = mid; 1168 else if (pll_in > pll->pll_in_max) 1169 min_ref_div = mid; 1170 else 1171 break; 1172 } 1173 } 1174 1175 if (pll->flags & RADEON_PLL_USE_POST_DIV) 1176 min_post_div = max_post_div = pll->post_div; 1177 1178 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 1179 min_fractional_feed_div = pll->min_frac_feedback_div; 1180 max_fractional_feed_div = pll->max_frac_feedback_div; 1181 } 1182 1183 for (post_div = max_post_div; post_div >= min_post_div; --post_div) { 1184 uint32_t ref_div; 1185 1186 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) 1187 continue; 1188 1189 /* legacy radeons only have a few post_divs */ 1190 if (pll->flags & RADEON_PLL_LEGACY) { 1191 if ((post_div == 5) || 1192 (post_div == 7) || 1193 (post_div == 9) || 1194 (post_div == 10) || 1195 (post_div == 11) || 1196 (post_div == 13) || 1197 (post_div == 14) || 1198 (post_div == 15)) 1199 continue; 1200 } 1201 1202 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) { 1203 uint32_t feedback_div, current_freq = 0, error, vco_diff; 1204 uint32_t pll_in = pll->reference_freq / ref_div; 1205 uint32_t min_feed_div = pll->min_feedback_div; 1206 uint32_t max_feed_div = pll->max_feedback_div + 1; 1207 1208 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max) 1209 continue; 1210 1211 while (min_feed_div < max_feed_div) { 1212 uint32_t vco; 1213 uint32_t min_frac_feed_div = min_fractional_feed_div; 1214 uint32_t max_frac_feed_div = max_fractional_feed_div + 1; 1215 uint32_t frac_feedback_div; 1216 uint64_t tmp; 1217 1218 feedback_div = (min_feed_div + max_feed_div) / 2; 1219 1220 tmp = (uint64_t)pll->reference_freq * feedback_div; 1221 vco = radeon_div(tmp, ref_div); 1222 1223 if (vco < pll_out_min) { 1224 min_feed_div = feedback_div + 1; 1225 continue; 1226 } else if (vco > pll_out_max) { 1227 max_feed_div = feedback_div; 1228 continue; 1229 } 1230 1231 while (min_frac_feed_div < max_frac_feed_div) { 1232 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2; 1233 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div; 1234 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div; 1235 current_freq = radeon_div(tmp, ref_div * post_div); 1236 1237 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) { 1238 if (freq < current_freq) 1239 error = 0xffffffff; 1240 else 1241 error = freq - current_freq; 1242 } else 1243 error = abs(current_freq - freq); 1244 vco_diff = abs(vco - best_vco); 1245 1246 if ((best_vco == 0 && error < best_error) || 1247 (best_vco != 0 && 1248 ((best_error > 100 && error < best_error - 100) || 1249 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) { 1250 best_post_div = post_div; 1251 best_ref_div = ref_div; 1252 best_feedback_div = feedback_div; 1253 best_frac_feedback_div = frac_feedback_div; 1254 best_freq = current_freq; 1255 best_error = error; 1256 best_vco_diff = vco_diff; 1257 } else if (current_freq == freq) { 1258 if (best_freq == -1) { 1259 best_post_div = post_div; 1260 best_ref_div = ref_div; 1261 best_feedback_div = feedback_div; 1262 best_frac_feedback_div = frac_feedback_div; 1263 best_freq = current_freq; 1264 best_error = error; 1265 best_vco_diff = vco_diff; 1266 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) || 1267 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) || 1268 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) || 1269 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) || 1270 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) || 1271 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) { 1272 best_post_div = post_div; 1273 best_ref_div = ref_div; 1274 best_feedback_div = feedback_div; 1275 best_frac_feedback_div = frac_feedback_div; 1276 best_freq = current_freq; 1277 best_error = error; 1278 best_vco_diff = vco_diff; 1279 } 1280 } 1281 if (current_freq < freq) 1282 min_frac_feed_div = frac_feedback_div + 1; 1283 else 1284 max_frac_feed_div = frac_feedback_div; 1285 } 1286 if (current_freq < freq) 1287 min_feed_div = feedback_div + 1; 1288 else 1289 max_feed_div = feedback_div; 1290 } 1291 } 1292 } 1293 1294 *dot_clock_p = best_freq / 10000; 1295 *fb_div_p = best_feedback_div; 1296 *frac_fb_div_p = best_frac_feedback_div; 1297 *ref_div_p = best_ref_div; 1298 *post_div_p = best_post_div; 1299 DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n", 1300 (long long)freq, 1301 best_freq / 1000, best_feedback_div, best_frac_feedback_div, 1302 best_ref_div, best_post_div); 1303 1304 } 1305 1306 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb) 1307 { 1308 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); 1309 1310 if (radeon_fb->obj) { 1311 drm_gem_object_unreference_unlocked(radeon_fb->obj); 1312 } 1313 drm_framebuffer_cleanup(fb); 1314 kfree(radeon_fb); 1315 } 1316 1317 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb, 1318 struct drm_file *file_priv, 1319 unsigned int *handle) 1320 { 1321 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); 1322 1323 return drm_gem_handle_create(file_priv, radeon_fb->obj, handle); 1324 } 1325 1326 static const struct drm_framebuffer_funcs radeon_fb_funcs = { 1327 .destroy = radeon_user_framebuffer_destroy, 1328 .create_handle = radeon_user_framebuffer_create_handle, 1329 }; 1330 1331 int 1332 radeon_framebuffer_init(struct drm_device *dev, 1333 struct radeon_framebuffer *rfb, 1334 const struct drm_mode_fb_cmd2 *mode_cmd, 1335 struct drm_gem_object *obj) 1336 { 1337 int ret; 1338 rfb->obj = obj; 1339 drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd); 1340 ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs); 1341 if (ret) { 1342 rfb->obj = NULL; 1343 return ret; 1344 } 1345 return 0; 1346 } 1347 1348 static struct drm_framebuffer * 1349 radeon_user_framebuffer_create(struct drm_device *dev, 1350 struct drm_file *file_priv, 1351 const struct drm_mode_fb_cmd2 *mode_cmd) 1352 { 1353 struct drm_gem_object *obj; 1354 struct radeon_framebuffer *radeon_fb; 1355 int ret; 1356 1357 obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]); 1358 if (obj == NULL) { 1359 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, " 1360 "can't create framebuffer\n", mode_cmd->handles[0]); 1361 return ERR_PTR(-ENOENT); 1362 } 1363 1364 radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL); 1365 if (radeon_fb == NULL) { 1366 drm_gem_object_unreference_unlocked(obj); 1367 return ERR_PTR(-ENOMEM); 1368 } 1369 1370 ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj); 1371 if (ret) { 1372 kfree(radeon_fb); 1373 drm_gem_object_unreference_unlocked(obj); 1374 return ERR_PTR(ret); 1375 } 1376 1377 return &radeon_fb->base; 1378 } 1379 1380 static void radeon_output_poll_changed(struct drm_device *dev) 1381 { 1382 struct radeon_device *rdev = dev->dev_private; 1383 radeon_fb_output_poll_changed(rdev); 1384 } 1385 1386 static const struct drm_mode_config_funcs radeon_mode_funcs = { 1387 .fb_create = radeon_user_framebuffer_create, 1388 .output_poll_changed = radeon_output_poll_changed 1389 }; 1390 1391 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] = 1392 { { 0, "driver" }, 1393 { 1, "bios" }, 1394 }; 1395 1396 static struct drm_prop_enum_list radeon_tv_std_enum_list[] = 1397 { { TV_STD_NTSC, "ntsc" }, 1398 { TV_STD_PAL, "pal" }, 1399 { TV_STD_PAL_M, "pal-m" }, 1400 { TV_STD_PAL_60, "pal-60" }, 1401 { TV_STD_NTSC_J, "ntsc-j" }, 1402 { TV_STD_SCART_PAL, "scart-pal" }, 1403 { TV_STD_PAL_CN, "pal-cn" }, 1404 { TV_STD_SECAM, "secam" }, 1405 }; 1406 1407 static struct drm_prop_enum_list radeon_underscan_enum_list[] = 1408 { { UNDERSCAN_OFF, "off" }, 1409 { UNDERSCAN_ON, "on" }, 1410 { UNDERSCAN_AUTO, "auto" }, 1411 }; 1412 1413 static struct drm_prop_enum_list radeon_audio_enum_list[] = 1414 { { RADEON_AUDIO_DISABLE, "off" }, 1415 { RADEON_AUDIO_ENABLE, "on" }, 1416 { RADEON_AUDIO_AUTO, "auto" }, 1417 }; 1418 1419 /* XXX support different dither options? spatial, temporal, both, etc. */ 1420 static struct drm_prop_enum_list radeon_dither_enum_list[] = 1421 { { RADEON_FMT_DITHER_DISABLE, "off" }, 1422 { RADEON_FMT_DITHER_ENABLE, "on" }, 1423 }; 1424 1425 static struct drm_prop_enum_list radeon_output_csc_enum_list[] = 1426 { { RADEON_OUTPUT_CSC_BYPASS, "bypass" }, 1427 { RADEON_OUTPUT_CSC_TVRGB, "tvrgb" }, 1428 { RADEON_OUTPUT_CSC_YCBCR601, "ycbcr601" }, 1429 { RADEON_OUTPUT_CSC_YCBCR709, "ycbcr709" }, 1430 }; 1431 1432 static int radeon_modeset_create_props(struct radeon_device *rdev) 1433 { 1434 int sz; 1435 1436 if (rdev->is_atom_bios) { 1437 rdev->mode_info.coherent_mode_property = 1438 drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1); 1439 if (!rdev->mode_info.coherent_mode_property) 1440 return -ENOMEM; 1441 } 1442 1443 if (!ASIC_IS_AVIVO(rdev)) { 1444 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list); 1445 rdev->mode_info.tmds_pll_property = 1446 drm_property_create_enum(rdev->ddev, 0, 1447 "tmds_pll", 1448 radeon_tmds_pll_enum_list, sz); 1449 } 1450 1451 rdev->mode_info.load_detect_property = 1452 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1); 1453 if (!rdev->mode_info.load_detect_property) 1454 return -ENOMEM; 1455 1456 drm_mode_create_scaling_mode_property(rdev->ddev); 1457 1458 sz = ARRAY_SIZE(radeon_tv_std_enum_list); 1459 rdev->mode_info.tv_std_property = 1460 drm_property_create_enum(rdev->ddev, 0, 1461 "tv standard", 1462 radeon_tv_std_enum_list, sz); 1463 1464 sz = ARRAY_SIZE(radeon_underscan_enum_list); 1465 rdev->mode_info.underscan_property = 1466 drm_property_create_enum(rdev->ddev, 0, 1467 "underscan", 1468 radeon_underscan_enum_list, sz); 1469 1470 rdev->mode_info.underscan_hborder_property = 1471 drm_property_create_range(rdev->ddev, 0, 1472 "underscan hborder", 0, 128); 1473 if (!rdev->mode_info.underscan_hborder_property) 1474 return -ENOMEM; 1475 1476 rdev->mode_info.underscan_vborder_property = 1477 drm_property_create_range(rdev->ddev, 0, 1478 "underscan vborder", 0, 128); 1479 if (!rdev->mode_info.underscan_vborder_property) 1480 return -ENOMEM; 1481 1482 sz = ARRAY_SIZE(radeon_audio_enum_list); 1483 rdev->mode_info.audio_property = 1484 drm_property_create_enum(rdev->ddev, 0, 1485 "audio", 1486 radeon_audio_enum_list, sz); 1487 1488 sz = ARRAY_SIZE(radeon_dither_enum_list); 1489 rdev->mode_info.dither_property = 1490 drm_property_create_enum(rdev->ddev, 0, 1491 "dither", 1492 radeon_dither_enum_list, sz); 1493 1494 sz = ARRAY_SIZE(radeon_output_csc_enum_list); 1495 rdev->mode_info.output_csc_property = 1496 drm_property_create_enum(rdev->ddev, 0, 1497 "output_csc", 1498 radeon_output_csc_enum_list, sz); 1499 1500 return 0; 1501 } 1502 1503 void radeon_update_display_priority(struct radeon_device *rdev) 1504 { 1505 /* adjustment options for the display watermarks */ 1506 if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) { 1507 /* set display priority to high for r3xx, rv515 chips 1508 * this avoids flickering due to underflow to the 1509 * display controllers during heavy acceleration. 1510 * Don't force high on rs4xx igp chips as it seems to 1511 * affect the sound card. See kernel bug 15982. 1512 */ 1513 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) && 1514 !(rdev->flags & RADEON_IS_IGP)) 1515 rdev->disp_priority = 2; 1516 else 1517 rdev->disp_priority = 0; 1518 } else 1519 rdev->disp_priority = radeon_disp_priority; 1520 1521 } 1522 1523 /* 1524 * Allocate hdmi structs and determine register offsets 1525 */ 1526 static void radeon_afmt_init(struct radeon_device *rdev) 1527 { 1528 int i; 1529 1530 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) 1531 rdev->mode_info.afmt[i] = NULL; 1532 1533 if (ASIC_IS_NODCE(rdev)) { 1534 /* nothing to do */ 1535 } else if (ASIC_IS_DCE4(rdev)) { 1536 static uint32_t eg_offsets[] = { 1537 EVERGREEN_CRTC0_REGISTER_OFFSET, 1538 EVERGREEN_CRTC1_REGISTER_OFFSET, 1539 EVERGREEN_CRTC2_REGISTER_OFFSET, 1540 EVERGREEN_CRTC3_REGISTER_OFFSET, 1541 EVERGREEN_CRTC4_REGISTER_OFFSET, 1542 EVERGREEN_CRTC5_REGISTER_OFFSET, 1543 0x13830 - 0x7030, 1544 }; 1545 int num_afmt; 1546 1547 /* DCE8 has 7 audio blocks tied to DIG encoders */ 1548 /* DCE6 has 6 audio blocks tied to DIG encoders */ 1549 /* DCE4/5 has 6 audio blocks tied to DIG encoders */ 1550 /* DCE4.1 has 2 audio blocks tied to DIG encoders */ 1551 if (ASIC_IS_DCE8(rdev)) 1552 num_afmt = 7; 1553 else if (ASIC_IS_DCE6(rdev)) 1554 num_afmt = 6; 1555 else if (ASIC_IS_DCE5(rdev)) 1556 num_afmt = 6; 1557 else if (ASIC_IS_DCE41(rdev)) 1558 num_afmt = 2; 1559 else /* DCE4 */ 1560 num_afmt = 6; 1561 1562 BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets)); 1563 for (i = 0; i < num_afmt; i++) { 1564 rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1565 if (rdev->mode_info.afmt[i]) { 1566 rdev->mode_info.afmt[i]->offset = eg_offsets[i]; 1567 rdev->mode_info.afmt[i]->id = i; 1568 } 1569 } 1570 } else if (ASIC_IS_DCE3(rdev)) { 1571 /* DCE3.x has 2 audio blocks tied to DIG encoders */ 1572 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1573 if (rdev->mode_info.afmt[0]) { 1574 rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0; 1575 rdev->mode_info.afmt[0]->id = 0; 1576 } 1577 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1578 if (rdev->mode_info.afmt[1]) { 1579 rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1; 1580 rdev->mode_info.afmt[1]->id = 1; 1581 } 1582 } else if (ASIC_IS_DCE2(rdev)) { 1583 /* DCE2 has at least 1 routable audio block */ 1584 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1585 if (rdev->mode_info.afmt[0]) { 1586 rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0; 1587 rdev->mode_info.afmt[0]->id = 0; 1588 } 1589 /* r6xx has 2 routable audio blocks */ 1590 if (rdev->family >= CHIP_R600) { 1591 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1592 if (rdev->mode_info.afmt[1]) { 1593 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1; 1594 rdev->mode_info.afmt[1]->id = 1; 1595 } 1596 } 1597 } 1598 } 1599 1600 static void radeon_afmt_fini(struct radeon_device *rdev) 1601 { 1602 int i; 1603 1604 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) { 1605 kfree(rdev->mode_info.afmt[i]); 1606 rdev->mode_info.afmt[i] = NULL; 1607 } 1608 } 1609 1610 int radeon_modeset_init(struct radeon_device *rdev) 1611 { 1612 int i; 1613 int ret; 1614 1615 drm_mode_config_init(rdev->ddev); 1616 rdev->mode_info.mode_config_initialized = true; 1617 1618 rdev->ddev->mode_config.funcs = &radeon_mode_funcs; 1619 1620 if (ASIC_IS_DCE5(rdev)) { 1621 rdev->ddev->mode_config.max_width = 16384; 1622 rdev->ddev->mode_config.max_height = 16384; 1623 } else if (ASIC_IS_AVIVO(rdev)) { 1624 rdev->ddev->mode_config.max_width = 8192; 1625 rdev->ddev->mode_config.max_height = 8192; 1626 } else { 1627 rdev->ddev->mode_config.max_width = 4096; 1628 rdev->ddev->mode_config.max_height = 4096; 1629 } 1630 1631 rdev->ddev->mode_config.preferred_depth = 24; 1632 rdev->ddev->mode_config.prefer_shadow = 1; 1633 1634 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base; 1635 1636 ret = radeon_modeset_create_props(rdev); 1637 if (ret) { 1638 return ret; 1639 } 1640 1641 /* init i2c buses */ 1642 radeon_i2c_init(rdev); 1643 1644 /* check combios for a valid hardcoded EDID - Sun servers */ 1645 if (!rdev->is_atom_bios) { 1646 /* check for hardcoded EDID in BIOS */ 1647 radeon_combios_check_hardcoded_edid(rdev); 1648 } 1649 1650 /* allocate crtcs */ 1651 for (i = 0; i < rdev->num_crtc; i++) { 1652 radeon_crtc_init(rdev->ddev, i); 1653 } 1654 1655 /* okay we should have all the bios connectors */ 1656 ret = radeon_setup_enc_conn(rdev->ddev); 1657 if (!ret) { 1658 return ret; 1659 } 1660 1661 /* init dig PHYs, disp eng pll */ 1662 if (rdev->is_atom_bios) { 1663 radeon_atom_encoder_init(rdev); 1664 radeon_atom_disp_eng_pll_init(rdev); 1665 } 1666 1667 /* initialize hpd */ 1668 radeon_hpd_init(rdev); 1669 1670 /* setup afmt */ 1671 radeon_afmt_init(rdev); 1672 1673 radeon_fbdev_init(rdev); 1674 drm_kms_helper_poll_init(rdev->ddev); 1675 1676 /* do pm late init */ 1677 ret = radeon_pm_late_init(rdev); 1678 1679 return 0; 1680 } 1681 1682 void radeon_modeset_fini(struct radeon_device *rdev) 1683 { 1684 radeon_fbdev_fini(rdev); 1685 kfree(rdev->mode_info.bios_hardcoded_edid); 1686 1687 if (rdev->mode_info.mode_config_initialized) { 1688 radeon_afmt_fini(rdev); 1689 drm_kms_helper_poll_fini(rdev->ddev); 1690 radeon_hpd_fini(rdev); 1691 drm_mode_config_cleanup(rdev->ddev); 1692 rdev->mode_info.mode_config_initialized = false; 1693 } 1694 /* free i2c buses */ 1695 radeon_i2c_fini(rdev); 1696 } 1697 1698 static bool is_hdtv_mode(const struct drm_display_mode *mode) 1699 { 1700 /* try and guess if this is a tv or a monitor */ 1701 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */ 1702 (mode->vdisplay == 576) || /* 576p */ 1703 (mode->vdisplay == 720) || /* 720p */ 1704 (mode->vdisplay == 1080)) /* 1080p */ 1705 return true; 1706 else 1707 return false; 1708 } 1709 1710 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 1711 const struct drm_display_mode *mode, 1712 struct drm_display_mode *adjusted_mode) 1713 { 1714 struct drm_device *dev = crtc->dev; 1715 struct radeon_device *rdev = dev->dev_private; 1716 struct drm_encoder *encoder; 1717 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1718 struct radeon_encoder *radeon_encoder; 1719 struct drm_connector *connector; 1720 struct radeon_connector *radeon_connector; 1721 bool first = true; 1722 u32 src_v = 1, dst_v = 1; 1723 u32 src_h = 1, dst_h = 1; 1724 1725 radeon_crtc->h_border = 0; 1726 radeon_crtc->v_border = 0; 1727 1728 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1729 if (encoder->crtc != crtc) 1730 continue; 1731 radeon_encoder = to_radeon_encoder(encoder); 1732 connector = radeon_get_connector_for_encoder(encoder); 1733 radeon_connector = to_radeon_connector(connector); 1734 1735 if (first) { 1736 /* set scaling */ 1737 if (radeon_encoder->rmx_type == RMX_OFF) 1738 radeon_crtc->rmx_type = RMX_OFF; 1739 else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay || 1740 mode->vdisplay < radeon_encoder->native_mode.vdisplay) 1741 radeon_crtc->rmx_type = radeon_encoder->rmx_type; 1742 else 1743 radeon_crtc->rmx_type = RMX_OFF; 1744 /* copy native mode */ 1745 memcpy(&radeon_crtc->native_mode, 1746 &radeon_encoder->native_mode, 1747 sizeof(struct drm_display_mode)); 1748 src_v = crtc->mode.vdisplay; 1749 dst_v = radeon_crtc->native_mode.vdisplay; 1750 src_h = crtc->mode.hdisplay; 1751 dst_h = radeon_crtc->native_mode.hdisplay; 1752 1753 /* fix up for overscan on hdmi */ 1754 if (ASIC_IS_AVIVO(rdev) && 1755 (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) && 1756 ((radeon_encoder->underscan_type == UNDERSCAN_ON) || 1757 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) && 1758 drm_detect_hdmi_monitor(radeon_connector_edid(connector)) && 1759 is_hdtv_mode(mode)))) { 1760 if (radeon_encoder->underscan_hborder != 0) 1761 radeon_crtc->h_border = radeon_encoder->underscan_hborder; 1762 else 1763 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16; 1764 if (radeon_encoder->underscan_vborder != 0) 1765 radeon_crtc->v_border = radeon_encoder->underscan_vborder; 1766 else 1767 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16; 1768 radeon_crtc->rmx_type = RMX_FULL; 1769 src_v = crtc->mode.vdisplay; 1770 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2); 1771 src_h = crtc->mode.hdisplay; 1772 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2); 1773 } 1774 first = false; 1775 } else { 1776 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) { 1777 /* WARNING: Right now this can't happen but 1778 * in the future we need to check that scaling 1779 * are consistent across different encoder 1780 * (ie all encoder can work with the same 1781 * scaling). 1782 */ 1783 DRM_ERROR("Scaling not consistent across encoder.\n"); 1784 return false; 1785 } 1786 } 1787 } 1788 if (radeon_crtc->rmx_type != RMX_OFF) { 1789 fixed20_12 a, b; 1790 a.full = dfixed_const(src_v); 1791 b.full = dfixed_const(dst_v); 1792 radeon_crtc->vsc.full = dfixed_div(a, b); 1793 a.full = dfixed_const(src_h); 1794 b.full = dfixed_const(dst_h); 1795 radeon_crtc->hsc.full = dfixed_div(a, b); 1796 } else { 1797 radeon_crtc->vsc.full = dfixed_const(1); 1798 radeon_crtc->hsc.full = dfixed_const(1); 1799 } 1800 return true; 1801 } 1802 1803 /* 1804 * Retrieve current video scanout position of crtc on a given gpu, and 1805 * an optional accurate timestamp of when query happened. 1806 * 1807 * \param dev Device to query. 1808 * \param crtc Crtc to query. 1809 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0). 1810 * For driver internal use only also supports these flags: 1811 * 1812 * USE_REAL_VBLANKSTART to use the real start of vblank instead 1813 * of a fudged earlier start of vblank. 1814 * 1815 * GET_DISTANCE_TO_VBLANKSTART to return distance to the 1816 * fudged earlier start of vblank in *vpos and the distance 1817 * to true start of vblank in *hpos. 1818 * 1819 * \param *vpos Location where vertical scanout position should be stored. 1820 * \param *hpos Location where horizontal scanout position should go. 1821 * \param *stime Target location for timestamp taken immediately before 1822 * scanout position query. Can be NULL to skip timestamp. 1823 * \param *etime Target location for timestamp taken immediately after 1824 * scanout position query. Can be NULL to skip timestamp. 1825 * 1826 * Returns vpos as a positive number while in active scanout area. 1827 * Returns vpos as a negative number inside vblank, counting the number 1828 * of scanlines to go until end of vblank, e.g., -1 means "one scanline 1829 * until start of active scanout / end of vblank." 1830 * 1831 * \return Flags, or'ed together as follows: 1832 * 1833 * DRM_SCANOUTPOS_VALID = Query successful. 1834 * DRM_SCANOUTPOS_INVBL = Inside vblank. 1835 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of 1836 * this flag means that returned position may be offset by a constant but 1837 * unknown small number of scanlines wrt. real scanout position. 1838 * 1839 */ 1840 int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, 1841 unsigned int flags, int *vpos, int *hpos, 1842 ktime_t *stime, ktime_t *etime, 1843 const struct drm_display_mode *mode) 1844 { 1845 u32 stat_crtc = 0, vbl = 0, position = 0; 1846 int vbl_start, vbl_end, vtotal, ret = 0; 1847 bool in_vbl = true; 1848 1849 struct radeon_device *rdev = dev->dev_private; 1850 1851 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ 1852 1853 /* Get optional system timestamp before query. */ 1854 if (stime) 1855 *stime = ktime_get(); 1856 1857 if (ASIC_IS_DCE4(rdev)) { 1858 if (pipe == 0) { 1859 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1860 EVERGREEN_CRTC0_REGISTER_OFFSET); 1861 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1862 EVERGREEN_CRTC0_REGISTER_OFFSET); 1863 ret |= DRM_SCANOUTPOS_VALID; 1864 } 1865 if (pipe == 1) { 1866 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1867 EVERGREEN_CRTC1_REGISTER_OFFSET); 1868 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1869 EVERGREEN_CRTC1_REGISTER_OFFSET); 1870 ret |= DRM_SCANOUTPOS_VALID; 1871 } 1872 if (pipe == 2) { 1873 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1874 EVERGREEN_CRTC2_REGISTER_OFFSET); 1875 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1876 EVERGREEN_CRTC2_REGISTER_OFFSET); 1877 ret |= DRM_SCANOUTPOS_VALID; 1878 } 1879 if (pipe == 3) { 1880 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1881 EVERGREEN_CRTC3_REGISTER_OFFSET); 1882 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1883 EVERGREEN_CRTC3_REGISTER_OFFSET); 1884 ret |= DRM_SCANOUTPOS_VALID; 1885 } 1886 if (pipe == 4) { 1887 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1888 EVERGREEN_CRTC4_REGISTER_OFFSET); 1889 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1890 EVERGREEN_CRTC4_REGISTER_OFFSET); 1891 ret |= DRM_SCANOUTPOS_VALID; 1892 } 1893 if (pipe == 5) { 1894 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1895 EVERGREEN_CRTC5_REGISTER_OFFSET); 1896 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1897 EVERGREEN_CRTC5_REGISTER_OFFSET); 1898 ret |= DRM_SCANOUTPOS_VALID; 1899 } 1900 } else if (ASIC_IS_AVIVO(rdev)) { 1901 if (pipe == 0) { 1902 vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END); 1903 position = RREG32(AVIVO_D1CRTC_STATUS_POSITION); 1904 ret |= DRM_SCANOUTPOS_VALID; 1905 } 1906 if (pipe == 1) { 1907 vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END); 1908 position = RREG32(AVIVO_D2CRTC_STATUS_POSITION); 1909 ret |= DRM_SCANOUTPOS_VALID; 1910 } 1911 } else { 1912 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */ 1913 if (pipe == 0) { 1914 /* Assume vbl_end == 0, get vbl_start from 1915 * upper 16 bits. 1916 */ 1917 vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) & 1918 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT; 1919 /* Only retrieve vpos from upper 16 bits, set hpos == 0. */ 1920 position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 1921 stat_crtc = RREG32(RADEON_CRTC_STATUS); 1922 if (!(stat_crtc & 1)) 1923 in_vbl = false; 1924 1925 ret |= DRM_SCANOUTPOS_VALID; 1926 } 1927 if (pipe == 1) { 1928 vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) & 1929 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT; 1930 position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 1931 stat_crtc = RREG32(RADEON_CRTC2_STATUS); 1932 if (!(stat_crtc & 1)) 1933 in_vbl = false; 1934 1935 ret |= DRM_SCANOUTPOS_VALID; 1936 } 1937 } 1938 1939 /* Get optional system timestamp after query. */ 1940 if (etime) 1941 *etime = ktime_get(); 1942 1943 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ 1944 1945 /* Decode into vertical and horizontal scanout position. */ 1946 *vpos = position & 0x1fff; 1947 *hpos = (position >> 16) & 0x1fff; 1948 1949 /* Valid vblank area boundaries from gpu retrieved? */ 1950 if (vbl > 0) { 1951 /* Yes: Decode. */ 1952 ret |= DRM_SCANOUTPOS_ACCURATE; 1953 vbl_start = vbl & 0x1fff; 1954 vbl_end = (vbl >> 16) & 0x1fff; 1955 } 1956 else { 1957 /* No: Fake something reasonable which gives at least ok results. */ 1958 vbl_start = mode->crtc_vdisplay; 1959 vbl_end = 0; 1960 } 1961 1962 /* Called from driver internal vblank counter query code? */ 1963 if (flags & GET_DISTANCE_TO_VBLANKSTART) { 1964 /* Caller wants distance from real vbl_start in *hpos */ 1965 *hpos = *vpos - vbl_start; 1966 } 1967 1968 /* Fudge vblank to start a few scanlines earlier to handle the 1969 * problem that vblank irqs fire a few scanlines before start 1970 * of vblank. Some driver internal callers need the true vblank 1971 * start to be used and signal this via the USE_REAL_VBLANKSTART flag. 1972 * 1973 * The cause of the "early" vblank irq is that the irq is triggered 1974 * by the line buffer logic when the line buffer read position enters 1975 * the vblank, whereas our crtc scanout position naturally lags the 1976 * line buffer read position. 1977 */ 1978 if (!(flags & USE_REAL_VBLANKSTART)) 1979 vbl_start -= rdev->mode_info.crtcs[pipe]->lb_vblank_lead_lines; 1980 1981 /* Test scanout position against vblank region. */ 1982 if ((*vpos < vbl_start) && (*vpos >= vbl_end)) 1983 in_vbl = false; 1984 1985 /* In vblank? */ 1986 if (in_vbl) 1987 ret |= DRM_SCANOUTPOS_IN_VBLANK; 1988 1989 /* Called from driver internal vblank counter query code? */ 1990 if (flags & GET_DISTANCE_TO_VBLANKSTART) { 1991 /* Caller wants distance from fudged earlier vbl_start */ 1992 *vpos -= vbl_start; 1993 return ret; 1994 } 1995 1996 /* Check if inside vblank area and apply corrective offsets: 1997 * vpos will then be >=0 in video scanout area, but negative 1998 * within vblank area, counting down the number of lines until 1999 * start of scanout. 2000 */ 2001 2002 /* Inside "upper part" of vblank area? Apply corrective offset if so: */ 2003 if (in_vbl && (*vpos >= vbl_start)) { 2004 vtotal = mode->crtc_vtotal; 2005 *vpos = *vpos - vtotal; 2006 } 2007 2008 /* Correct for shifted end of vbl at vbl_end. */ 2009 *vpos = *vpos - vbl_end; 2010 2011 return ret; 2012 } 2013