1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include "drmP.h" 27 #include "radeon_drm.h" 28 #include "radeon.h" 29 30 #include "atom.h" 31 #include <asm/div64.h> 32 33 #include "drm_crtc_helper.h" 34 #include "drm_edid.h" 35 36 static int radeon_ddc_dump(struct drm_connector *connector); 37 38 static void avivo_crtc_load_lut(struct drm_crtc *crtc) 39 { 40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 41 struct drm_device *dev = crtc->dev; 42 struct radeon_device *rdev = dev->dev_private; 43 int i; 44 45 DRM_DEBUG("%d\n", radeon_crtc->crtc_id); 46 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); 47 48 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 49 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 50 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 51 52 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 53 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 54 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 55 56 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id); 57 WREG32(AVIVO_DC_LUT_RW_MODE, 0); 58 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f); 59 60 WREG8(AVIVO_DC_LUT_RW_INDEX, 0); 61 for (i = 0; i < 256; i++) { 62 WREG32(AVIVO_DC_LUT_30_COLOR, 63 (radeon_crtc->lut_r[i] << 20) | 64 (radeon_crtc->lut_g[i] << 10) | 65 (radeon_crtc->lut_b[i] << 0)); 66 } 67 68 WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id); 69 } 70 71 static void evergreen_crtc_load_lut(struct drm_crtc *crtc) 72 { 73 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 74 struct drm_device *dev = crtc->dev; 75 struct radeon_device *rdev = dev->dev_private; 76 int i; 77 78 DRM_DEBUG("%d\n", radeon_crtc->crtc_id); 79 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); 80 81 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 82 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 83 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 84 85 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 86 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 87 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 88 89 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); 90 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); 91 92 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); 93 for (i = 0; i < 256; i++) { 94 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, 95 (radeon_crtc->lut_r[i] << 20) | 96 (radeon_crtc->lut_g[i] << 10) | 97 (radeon_crtc->lut_b[i] << 0)); 98 } 99 } 100 101 static void legacy_crtc_load_lut(struct drm_crtc *crtc) 102 { 103 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 104 struct drm_device *dev = crtc->dev; 105 struct radeon_device *rdev = dev->dev_private; 106 int i; 107 uint32_t dac2_cntl; 108 109 dac2_cntl = RREG32(RADEON_DAC_CNTL2); 110 if (radeon_crtc->crtc_id == 0) 111 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL; 112 else 113 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL; 114 WREG32(RADEON_DAC_CNTL2, dac2_cntl); 115 116 WREG8(RADEON_PALETTE_INDEX, 0); 117 for (i = 0; i < 256; i++) { 118 WREG32(RADEON_PALETTE_30_DATA, 119 (radeon_crtc->lut_r[i] << 20) | 120 (radeon_crtc->lut_g[i] << 10) | 121 (radeon_crtc->lut_b[i] << 0)); 122 } 123 } 124 125 void radeon_crtc_load_lut(struct drm_crtc *crtc) 126 { 127 struct drm_device *dev = crtc->dev; 128 struct radeon_device *rdev = dev->dev_private; 129 130 if (!crtc->enabled) 131 return; 132 133 if (ASIC_IS_DCE4(rdev)) 134 evergreen_crtc_load_lut(crtc); 135 else if (ASIC_IS_AVIVO(rdev)) 136 avivo_crtc_load_lut(crtc); 137 else 138 legacy_crtc_load_lut(crtc); 139 } 140 141 /** Sets the color ramps on behalf of fbcon */ 142 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, 143 u16 blue, int regno) 144 { 145 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 146 147 radeon_crtc->lut_r[regno] = red >> 6; 148 radeon_crtc->lut_g[regno] = green >> 6; 149 radeon_crtc->lut_b[regno] = blue >> 6; 150 } 151 152 /** Gets the color ramps on behalf of fbcon */ 153 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, 154 u16 *blue, int regno) 155 { 156 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 157 158 *red = radeon_crtc->lut_r[regno] << 6; 159 *green = radeon_crtc->lut_g[regno] << 6; 160 *blue = radeon_crtc->lut_b[regno] << 6; 161 } 162 163 static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 164 u16 *blue, uint32_t size) 165 { 166 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 167 int i; 168 169 if (size != 256) { 170 return; 171 } 172 173 /* userspace palettes are always correct as is */ 174 for (i = 0; i < 256; i++) { 175 radeon_crtc->lut_r[i] = red[i] >> 6; 176 radeon_crtc->lut_g[i] = green[i] >> 6; 177 radeon_crtc->lut_b[i] = blue[i] >> 6; 178 } 179 radeon_crtc_load_lut(crtc); 180 } 181 182 static void radeon_crtc_destroy(struct drm_crtc *crtc) 183 { 184 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 185 186 drm_crtc_cleanup(crtc); 187 kfree(radeon_crtc); 188 } 189 190 static const struct drm_crtc_funcs radeon_crtc_funcs = { 191 .cursor_set = radeon_crtc_cursor_set, 192 .cursor_move = radeon_crtc_cursor_move, 193 .gamma_set = radeon_crtc_gamma_set, 194 .set_config = drm_crtc_helper_set_config, 195 .destroy = radeon_crtc_destroy, 196 }; 197 198 static void radeon_crtc_init(struct drm_device *dev, int index) 199 { 200 struct radeon_device *rdev = dev->dev_private; 201 struct radeon_crtc *radeon_crtc; 202 int i; 203 204 radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); 205 if (radeon_crtc == NULL) 206 return; 207 208 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs); 209 210 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256); 211 radeon_crtc->crtc_id = index; 212 rdev->mode_info.crtcs[index] = radeon_crtc; 213 214 #if 0 215 radeon_crtc->mode_set.crtc = &radeon_crtc->base; 216 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1); 217 radeon_crtc->mode_set.num_connectors = 0; 218 #endif 219 220 for (i = 0; i < 256; i++) { 221 radeon_crtc->lut_r[i] = i << 2; 222 radeon_crtc->lut_g[i] = i << 2; 223 radeon_crtc->lut_b[i] = i << 2; 224 } 225 226 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)) 227 radeon_atombios_init_crtc(dev, radeon_crtc); 228 else 229 radeon_legacy_init_crtc(dev, radeon_crtc); 230 } 231 232 static const char *encoder_names[34] = { 233 "NONE", 234 "INTERNAL_LVDS", 235 "INTERNAL_TMDS1", 236 "INTERNAL_TMDS2", 237 "INTERNAL_DAC1", 238 "INTERNAL_DAC2", 239 "INTERNAL_SDVOA", 240 "INTERNAL_SDVOB", 241 "SI170B", 242 "CH7303", 243 "CH7301", 244 "INTERNAL_DVO1", 245 "EXTERNAL_SDVOA", 246 "EXTERNAL_SDVOB", 247 "TITFP513", 248 "INTERNAL_LVTM1", 249 "VT1623", 250 "HDMI_SI1930", 251 "HDMI_INTERNAL", 252 "INTERNAL_KLDSCP_TMDS1", 253 "INTERNAL_KLDSCP_DVO1", 254 "INTERNAL_KLDSCP_DAC1", 255 "INTERNAL_KLDSCP_DAC2", 256 "SI178", 257 "MVPU_FPGA", 258 "INTERNAL_DDI", 259 "VT1625", 260 "HDMI_SI1932", 261 "DP_AN9801", 262 "DP_DP501", 263 "INTERNAL_UNIPHY", 264 "INTERNAL_KLDSCP_LVTMA", 265 "INTERNAL_UNIPHY1", 266 "INTERNAL_UNIPHY2", 267 }; 268 269 static const char *connector_names[15] = { 270 "Unknown", 271 "VGA", 272 "DVI-I", 273 "DVI-D", 274 "DVI-A", 275 "Composite", 276 "S-video", 277 "LVDS", 278 "Component", 279 "DIN", 280 "DisplayPort", 281 "HDMI-A", 282 "HDMI-B", 283 "TV", 284 "eDP", 285 }; 286 287 static const char *hpd_names[6] = { 288 "HPD1", 289 "HPD2", 290 "HPD3", 291 "HPD4", 292 "HPD5", 293 "HPD6", 294 }; 295 296 static void radeon_print_display_setup(struct drm_device *dev) 297 { 298 struct drm_connector *connector; 299 struct radeon_connector *radeon_connector; 300 struct drm_encoder *encoder; 301 struct radeon_encoder *radeon_encoder; 302 uint32_t devices; 303 int i = 0; 304 305 DRM_INFO("Radeon Display Connectors\n"); 306 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 307 radeon_connector = to_radeon_connector(connector); 308 DRM_INFO("Connector %d:\n", i); 309 DRM_INFO(" %s\n", connector_names[connector->connector_type]); 310 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) 311 DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]); 312 if (radeon_connector->ddc_bus) { 313 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", 314 radeon_connector->ddc_bus->rec.mask_clk_reg, 315 radeon_connector->ddc_bus->rec.mask_data_reg, 316 radeon_connector->ddc_bus->rec.a_clk_reg, 317 radeon_connector->ddc_bus->rec.a_data_reg, 318 radeon_connector->ddc_bus->rec.en_clk_reg, 319 radeon_connector->ddc_bus->rec.en_data_reg, 320 radeon_connector->ddc_bus->rec.y_clk_reg, 321 radeon_connector->ddc_bus->rec.y_data_reg); 322 } else { 323 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || 324 connector->connector_type == DRM_MODE_CONNECTOR_DVII || 325 connector->connector_type == DRM_MODE_CONNECTOR_DVID || 326 connector->connector_type == DRM_MODE_CONNECTOR_DVIA || 327 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || 328 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) 329 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n"); 330 } 331 DRM_INFO(" Encoders:\n"); 332 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 333 radeon_encoder = to_radeon_encoder(encoder); 334 devices = radeon_encoder->devices & radeon_connector->devices; 335 if (devices) { 336 if (devices & ATOM_DEVICE_CRT1_SUPPORT) 337 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]); 338 if (devices & ATOM_DEVICE_CRT2_SUPPORT) 339 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]); 340 if (devices & ATOM_DEVICE_LCD1_SUPPORT) 341 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]); 342 if (devices & ATOM_DEVICE_DFP1_SUPPORT) 343 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]); 344 if (devices & ATOM_DEVICE_DFP2_SUPPORT) 345 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]); 346 if (devices & ATOM_DEVICE_DFP3_SUPPORT) 347 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]); 348 if (devices & ATOM_DEVICE_DFP4_SUPPORT) 349 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]); 350 if (devices & ATOM_DEVICE_DFP5_SUPPORT) 351 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]); 352 if (devices & ATOM_DEVICE_TV1_SUPPORT) 353 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]); 354 if (devices & ATOM_DEVICE_CV_SUPPORT) 355 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]); 356 } 357 } 358 i++; 359 } 360 } 361 362 static bool radeon_setup_enc_conn(struct drm_device *dev) 363 { 364 struct radeon_device *rdev = dev->dev_private; 365 struct drm_connector *drm_connector; 366 bool ret = false; 367 368 if (rdev->bios) { 369 if (rdev->is_atom_bios) { 370 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev); 371 if (ret == false) 372 ret = radeon_get_atom_connector_info_from_object_table(dev); 373 } else { 374 ret = radeon_get_legacy_connector_info_from_bios(dev); 375 if (ret == false) 376 ret = radeon_get_legacy_connector_info_from_table(dev); 377 } 378 } else { 379 if (!ASIC_IS_AVIVO(rdev)) 380 ret = radeon_get_legacy_connector_info_from_table(dev); 381 } 382 if (ret) { 383 radeon_setup_encoder_clones(dev); 384 radeon_print_display_setup(dev); 385 list_for_each_entry(drm_connector, &dev->mode_config.connector_list, head) 386 radeon_ddc_dump(drm_connector); 387 } 388 389 return ret; 390 } 391 392 int radeon_ddc_get_modes(struct radeon_connector *radeon_connector) 393 { 394 struct drm_device *dev = radeon_connector->base.dev; 395 struct radeon_device *rdev = dev->dev_private; 396 int ret = 0; 397 398 if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) || 399 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) { 400 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; 401 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT || 402 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus) 403 radeon_connector->edid = drm_get_edid(&radeon_connector->base, &dig->dp_i2c_bus->adapter); 404 } 405 if (!radeon_connector->ddc_bus) 406 return -1; 407 if (!radeon_connector->edid) { 408 radeon_connector->edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter); 409 } 410 /* some servers provide a hardcoded edid in rom for KVMs */ 411 if (!radeon_connector->edid) 412 radeon_connector->edid = radeon_combios_get_hardcoded_edid(rdev); 413 if (radeon_connector->edid) { 414 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid); 415 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid); 416 return ret; 417 } 418 drm_mode_connector_update_edid_property(&radeon_connector->base, NULL); 419 return 0; 420 } 421 422 static int radeon_ddc_dump(struct drm_connector *connector) 423 { 424 struct edid *edid; 425 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 426 int ret = 0; 427 428 if (!radeon_connector->ddc_bus) 429 return -1; 430 edid = drm_get_edid(connector, &radeon_connector->ddc_bus->adapter); 431 if (edid) { 432 kfree(edid); 433 } 434 return ret; 435 } 436 437 static inline uint32_t radeon_div(uint64_t n, uint32_t d) 438 { 439 uint64_t mod; 440 441 n += d / 2; 442 443 mod = do_div(n, d); 444 return n; 445 } 446 447 static void radeon_compute_pll_legacy(struct radeon_pll *pll, 448 uint64_t freq, 449 uint32_t *dot_clock_p, 450 uint32_t *fb_div_p, 451 uint32_t *frac_fb_div_p, 452 uint32_t *ref_div_p, 453 uint32_t *post_div_p) 454 { 455 uint32_t min_ref_div = pll->min_ref_div; 456 uint32_t max_ref_div = pll->max_ref_div; 457 uint32_t min_post_div = pll->min_post_div; 458 uint32_t max_post_div = pll->max_post_div; 459 uint32_t min_fractional_feed_div = 0; 460 uint32_t max_fractional_feed_div = 0; 461 uint32_t best_vco = pll->best_vco; 462 uint32_t best_post_div = 1; 463 uint32_t best_ref_div = 1; 464 uint32_t best_feedback_div = 1; 465 uint32_t best_frac_feedback_div = 0; 466 uint32_t best_freq = -1; 467 uint32_t best_error = 0xffffffff; 468 uint32_t best_vco_diff = 1; 469 uint32_t post_div; 470 u32 pll_out_min, pll_out_max; 471 472 DRM_DEBUG("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div); 473 freq = freq * 1000; 474 475 if (pll->flags & RADEON_PLL_IS_LCD) { 476 pll_out_min = pll->lcd_pll_out_min; 477 pll_out_max = pll->lcd_pll_out_max; 478 } else { 479 pll_out_min = pll->pll_out_min; 480 pll_out_max = pll->pll_out_max; 481 } 482 483 if (pll->flags & RADEON_PLL_USE_REF_DIV) 484 min_ref_div = max_ref_div = pll->reference_div; 485 else { 486 while (min_ref_div < max_ref_div-1) { 487 uint32_t mid = (min_ref_div + max_ref_div) / 2; 488 uint32_t pll_in = pll->reference_freq / mid; 489 if (pll_in < pll->pll_in_min) 490 max_ref_div = mid; 491 else if (pll_in > pll->pll_in_max) 492 min_ref_div = mid; 493 else 494 break; 495 } 496 } 497 498 if (pll->flags & RADEON_PLL_USE_POST_DIV) 499 min_post_div = max_post_div = pll->post_div; 500 501 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 502 min_fractional_feed_div = pll->min_frac_feedback_div; 503 max_fractional_feed_div = pll->max_frac_feedback_div; 504 } 505 506 for (post_div = min_post_div; post_div <= max_post_div; ++post_div) { 507 uint32_t ref_div; 508 509 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) 510 continue; 511 512 /* legacy radeons only have a few post_divs */ 513 if (pll->flags & RADEON_PLL_LEGACY) { 514 if ((post_div == 5) || 515 (post_div == 7) || 516 (post_div == 9) || 517 (post_div == 10) || 518 (post_div == 11) || 519 (post_div == 13) || 520 (post_div == 14) || 521 (post_div == 15)) 522 continue; 523 } 524 525 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) { 526 uint32_t feedback_div, current_freq = 0, error, vco_diff; 527 uint32_t pll_in = pll->reference_freq / ref_div; 528 uint32_t min_feed_div = pll->min_feedback_div; 529 uint32_t max_feed_div = pll->max_feedback_div + 1; 530 531 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max) 532 continue; 533 534 while (min_feed_div < max_feed_div) { 535 uint32_t vco; 536 uint32_t min_frac_feed_div = min_fractional_feed_div; 537 uint32_t max_frac_feed_div = max_fractional_feed_div + 1; 538 uint32_t frac_feedback_div; 539 uint64_t tmp; 540 541 feedback_div = (min_feed_div + max_feed_div) / 2; 542 543 tmp = (uint64_t)pll->reference_freq * feedback_div; 544 vco = radeon_div(tmp, ref_div); 545 546 if (vco < pll_out_min) { 547 min_feed_div = feedback_div + 1; 548 continue; 549 } else if (vco > pll_out_max) { 550 max_feed_div = feedback_div; 551 continue; 552 } 553 554 while (min_frac_feed_div < max_frac_feed_div) { 555 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2; 556 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div; 557 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div; 558 current_freq = radeon_div(tmp, ref_div * post_div); 559 560 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) { 561 error = freq - current_freq; 562 error = error < 0 ? 0xffffffff : error; 563 } else 564 error = abs(current_freq - freq); 565 vco_diff = abs(vco - best_vco); 566 567 if ((best_vco == 0 && error < best_error) || 568 (best_vco != 0 && 569 (error < best_error - 100 || 570 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) { 571 best_post_div = post_div; 572 best_ref_div = ref_div; 573 best_feedback_div = feedback_div; 574 best_frac_feedback_div = frac_feedback_div; 575 best_freq = current_freq; 576 best_error = error; 577 best_vco_diff = vco_diff; 578 } else if (current_freq == freq) { 579 if (best_freq == -1) { 580 best_post_div = post_div; 581 best_ref_div = ref_div; 582 best_feedback_div = feedback_div; 583 best_frac_feedback_div = frac_feedback_div; 584 best_freq = current_freq; 585 best_error = error; 586 best_vco_diff = vco_diff; 587 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) || 588 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) || 589 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) || 590 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) || 591 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) || 592 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) { 593 best_post_div = post_div; 594 best_ref_div = ref_div; 595 best_feedback_div = feedback_div; 596 best_frac_feedback_div = frac_feedback_div; 597 best_freq = current_freq; 598 best_error = error; 599 best_vco_diff = vco_diff; 600 } 601 } 602 if (current_freq < freq) 603 min_frac_feed_div = frac_feedback_div + 1; 604 else 605 max_frac_feed_div = frac_feedback_div; 606 } 607 if (current_freq < freq) 608 min_feed_div = feedback_div + 1; 609 else 610 max_feed_div = feedback_div; 611 } 612 } 613 } 614 615 *dot_clock_p = best_freq / 10000; 616 *fb_div_p = best_feedback_div; 617 *frac_fb_div_p = best_frac_feedback_div; 618 *ref_div_p = best_ref_div; 619 *post_div_p = best_post_div; 620 } 621 622 static bool 623 calc_fb_div(struct radeon_pll *pll, 624 uint32_t freq, 625 uint32_t post_div, 626 uint32_t ref_div, 627 uint32_t *fb_div, 628 uint32_t *fb_div_frac) 629 { 630 fixed20_12 feedback_divider, a, b; 631 u32 vco_freq; 632 633 vco_freq = freq * post_div; 634 /* feedback_divider = vco_freq * ref_div / pll->reference_freq; */ 635 a.full = dfixed_const(pll->reference_freq); 636 feedback_divider.full = dfixed_const(vco_freq); 637 feedback_divider.full = dfixed_div(feedback_divider, a); 638 a.full = dfixed_const(ref_div); 639 feedback_divider.full = dfixed_mul(feedback_divider, a); 640 641 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 642 /* feedback_divider = floor((feedback_divider * 10.0) + 0.5) * 0.1; */ 643 a.full = dfixed_const(10); 644 feedback_divider.full = dfixed_mul(feedback_divider, a); 645 feedback_divider.full += dfixed_const_half(0); 646 feedback_divider.full = dfixed_floor(feedback_divider); 647 feedback_divider.full = dfixed_div(feedback_divider, a); 648 649 /* *fb_div = floor(feedback_divider); */ 650 a.full = dfixed_floor(feedback_divider); 651 *fb_div = dfixed_trunc(a); 652 /* *fb_div_frac = fmod(feedback_divider, 1.0) * 10.0; */ 653 a.full = dfixed_const(10); 654 b.full = dfixed_mul(feedback_divider, a); 655 656 feedback_divider.full = dfixed_floor(feedback_divider); 657 feedback_divider.full = dfixed_mul(feedback_divider, a); 658 feedback_divider.full = b.full - feedback_divider.full; 659 *fb_div_frac = dfixed_trunc(feedback_divider); 660 } else { 661 /* *fb_div = floor(feedback_divider + 0.5); */ 662 feedback_divider.full += dfixed_const_half(0); 663 feedback_divider.full = dfixed_floor(feedback_divider); 664 665 *fb_div = dfixed_trunc(feedback_divider); 666 *fb_div_frac = 0; 667 } 668 669 if (((*fb_div) < pll->min_feedback_div) || ((*fb_div) > pll->max_feedback_div)) 670 return false; 671 else 672 return true; 673 } 674 675 static bool 676 calc_fb_ref_div(struct radeon_pll *pll, 677 uint32_t freq, 678 uint32_t post_div, 679 uint32_t *fb_div, 680 uint32_t *fb_div_frac, 681 uint32_t *ref_div) 682 { 683 fixed20_12 ffreq, max_error, error, pll_out, a; 684 u32 vco; 685 u32 pll_out_min, pll_out_max; 686 687 if (pll->flags & RADEON_PLL_IS_LCD) { 688 pll_out_min = pll->lcd_pll_out_min; 689 pll_out_max = pll->lcd_pll_out_max; 690 } else { 691 pll_out_min = pll->pll_out_min; 692 pll_out_max = pll->pll_out_max; 693 } 694 695 ffreq.full = dfixed_const(freq); 696 /* max_error = ffreq * 0.0025; */ 697 a.full = dfixed_const(400); 698 max_error.full = dfixed_div(ffreq, a); 699 700 for ((*ref_div) = pll->min_ref_div; (*ref_div) < pll->max_ref_div; ++(*ref_div)) { 701 if (calc_fb_div(pll, freq, post_div, (*ref_div), fb_div, fb_div_frac)) { 702 vco = pll->reference_freq * (((*fb_div) * 10) + (*fb_div_frac)); 703 vco = vco / ((*ref_div) * 10); 704 705 if ((vco < pll_out_min) || (vco > pll_out_max)) 706 continue; 707 708 /* pll_out = vco / post_div; */ 709 a.full = dfixed_const(post_div); 710 pll_out.full = dfixed_const(vco); 711 pll_out.full = dfixed_div(pll_out, a); 712 713 if (pll_out.full >= ffreq.full) { 714 error.full = pll_out.full - ffreq.full; 715 if (error.full <= max_error.full) 716 return true; 717 } 718 } 719 } 720 return false; 721 } 722 723 static void radeon_compute_pll_new(struct radeon_pll *pll, 724 uint64_t freq, 725 uint32_t *dot_clock_p, 726 uint32_t *fb_div_p, 727 uint32_t *frac_fb_div_p, 728 uint32_t *ref_div_p, 729 uint32_t *post_div_p) 730 { 731 u32 fb_div = 0, fb_div_frac = 0, post_div = 0, ref_div = 0; 732 u32 best_freq = 0, vco_frequency; 733 u32 pll_out_min, pll_out_max; 734 735 if (pll->flags & RADEON_PLL_IS_LCD) { 736 pll_out_min = pll->lcd_pll_out_min; 737 pll_out_max = pll->lcd_pll_out_max; 738 } else { 739 pll_out_min = pll->pll_out_min; 740 pll_out_max = pll->pll_out_max; 741 } 742 743 /* freq = freq / 10; */ 744 do_div(freq, 10); 745 746 if (pll->flags & RADEON_PLL_USE_POST_DIV) { 747 post_div = pll->post_div; 748 if ((post_div < pll->min_post_div) || (post_div > pll->max_post_div)) 749 goto done; 750 751 vco_frequency = freq * post_div; 752 if ((vco_frequency < pll_out_min) || (vco_frequency > pll_out_max)) 753 goto done; 754 755 if (pll->flags & RADEON_PLL_USE_REF_DIV) { 756 ref_div = pll->reference_div; 757 if ((ref_div < pll->min_ref_div) || (ref_div > pll->max_ref_div)) 758 goto done; 759 if (!calc_fb_div(pll, freq, post_div, ref_div, &fb_div, &fb_div_frac)) 760 goto done; 761 } 762 } else { 763 for (post_div = pll->max_post_div; post_div >= pll->min_post_div; --post_div) { 764 if (pll->flags & RADEON_PLL_LEGACY) { 765 if ((post_div == 5) || 766 (post_div == 7) || 767 (post_div == 9) || 768 (post_div == 10) || 769 (post_div == 11)) 770 continue; 771 } 772 773 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) 774 continue; 775 776 vco_frequency = freq * post_div; 777 if ((vco_frequency < pll_out_min) || (vco_frequency > pll_out_max)) 778 continue; 779 if (pll->flags & RADEON_PLL_USE_REF_DIV) { 780 ref_div = pll->reference_div; 781 if ((ref_div < pll->min_ref_div) || (ref_div > pll->max_ref_div)) 782 goto done; 783 if (calc_fb_div(pll, freq, post_div, ref_div, &fb_div, &fb_div_frac)) 784 break; 785 } else { 786 if (calc_fb_ref_div(pll, freq, post_div, &fb_div, &fb_div_frac, &ref_div)) 787 break; 788 } 789 } 790 } 791 792 best_freq = pll->reference_freq * 10 * fb_div; 793 best_freq += pll->reference_freq * fb_div_frac; 794 best_freq = best_freq / (ref_div * post_div); 795 796 done: 797 if (best_freq == 0) 798 DRM_ERROR("Couldn't find valid PLL dividers\n"); 799 800 *dot_clock_p = best_freq / 10; 801 *fb_div_p = fb_div; 802 *frac_fb_div_p = fb_div_frac; 803 *ref_div_p = ref_div; 804 *post_div_p = post_div; 805 806 DRM_DEBUG("%u %d.%d, %d, %d\n", *dot_clock_p, *fb_div_p, *frac_fb_div_p, *ref_div_p, *post_div_p); 807 } 808 809 void radeon_compute_pll(struct radeon_pll *pll, 810 uint64_t freq, 811 uint32_t *dot_clock_p, 812 uint32_t *fb_div_p, 813 uint32_t *frac_fb_div_p, 814 uint32_t *ref_div_p, 815 uint32_t *post_div_p) 816 { 817 switch (pll->algo) { 818 case PLL_ALGO_NEW: 819 radeon_compute_pll_new(pll, freq, dot_clock_p, fb_div_p, 820 frac_fb_div_p, ref_div_p, post_div_p); 821 break; 822 case PLL_ALGO_LEGACY: 823 default: 824 radeon_compute_pll_legacy(pll, freq, dot_clock_p, fb_div_p, 825 frac_fb_div_p, ref_div_p, post_div_p); 826 break; 827 } 828 } 829 830 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb) 831 { 832 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); 833 834 if (radeon_fb->obj) 835 drm_gem_object_unreference_unlocked(radeon_fb->obj); 836 drm_framebuffer_cleanup(fb); 837 kfree(radeon_fb); 838 } 839 840 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb, 841 struct drm_file *file_priv, 842 unsigned int *handle) 843 { 844 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); 845 846 return drm_gem_handle_create(file_priv, radeon_fb->obj, handle); 847 } 848 849 static const struct drm_framebuffer_funcs radeon_fb_funcs = { 850 .destroy = radeon_user_framebuffer_destroy, 851 .create_handle = radeon_user_framebuffer_create_handle, 852 }; 853 854 void 855 radeon_framebuffer_init(struct drm_device *dev, 856 struct radeon_framebuffer *rfb, 857 struct drm_mode_fb_cmd *mode_cmd, 858 struct drm_gem_object *obj) 859 { 860 rfb->obj = obj; 861 drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs); 862 drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd); 863 } 864 865 static struct drm_framebuffer * 866 radeon_user_framebuffer_create(struct drm_device *dev, 867 struct drm_file *file_priv, 868 struct drm_mode_fb_cmd *mode_cmd) 869 { 870 struct drm_gem_object *obj; 871 struct radeon_framebuffer *radeon_fb; 872 873 obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handle); 874 if (obj == NULL) { 875 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, " 876 "can't create framebuffer\n", mode_cmd->handle); 877 return NULL; 878 } 879 880 radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL); 881 if (radeon_fb == NULL) { 882 return NULL; 883 } 884 885 radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj); 886 887 return &radeon_fb->base; 888 } 889 890 static void radeon_output_poll_changed(struct drm_device *dev) 891 { 892 struct radeon_device *rdev = dev->dev_private; 893 radeon_fb_output_poll_changed(rdev); 894 } 895 896 static const struct drm_mode_config_funcs radeon_mode_funcs = { 897 .fb_create = radeon_user_framebuffer_create, 898 .output_poll_changed = radeon_output_poll_changed 899 }; 900 901 struct drm_prop_enum_list { 902 int type; 903 char *name; 904 }; 905 906 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] = 907 { { 0, "driver" }, 908 { 1, "bios" }, 909 }; 910 911 static struct drm_prop_enum_list radeon_tv_std_enum_list[] = 912 { { TV_STD_NTSC, "ntsc" }, 913 { TV_STD_PAL, "pal" }, 914 { TV_STD_PAL_M, "pal-m" }, 915 { TV_STD_PAL_60, "pal-60" }, 916 { TV_STD_NTSC_J, "ntsc-j" }, 917 { TV_STD_SCART_PAL, "scart-pal" }, 918 { TV_STD_PAL_CN, "pal-cn" }, 919 { TV_STD_SECAM, "secam" }, 920 }; 921 922 static int radeon_modeset_create_props(struct radeon_device *rdev) 923 { 924 int i, sz; 925 926 if (rdev->is_atom_bios) { 927 rdev->mode_info.coherent_mode_property = 928 drm_property_create(rdev->ddev, 929 DRM_MODE_PROP_RANGE, 930 "coherent", 2); 931 if (!rdev->mode_info.coherent_mode_property) 932 return -ENOMEM; 933 934 rdev->mode_info.coherent_mode_property->values[0] = 0; 935 rdev->mode_info.coherent_mode_property->values[1] = 1; 936 } 937 938 if (!ASIC_IS_AVIVO(rdev)) { 939 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list); 940 rdev->mode_info.tmds_pll_property = 941 drm_property_create(rdev->ddev, 942 DRM_MODE_PROP_ENUM, 943 "tmds_pll", sz); 944 for (i = 0; i < sz; i++) { 945 drm_property_add_enum(rdev->mode_info.tmds_pll_property, 946 i, 947 radeon_tmds_pll_enum_list[i].type, 948 radeon_tmds_pll_enum_list[i].name); 949 } 950 } 951 952 rdev->mode_info.load_detect_property = 953 drm_property_create(rdev->ddev, 954 DRM_MODE_PROP_RANGE, 955 "load detection", 2); 956 if (!rdev->mode_info.load_detect_property) 957 return -ENOMEM; 958 rdev->mode_info.load_detect_property->values[0] = 0; 959 rdev->mode_info.load_detect_property->values[1] = 1; 960 961 drm_mode_create_scaling_mode_property(rdev->ddev); 962 963 sz = ARRAY_SIZE(radeon_tv_std_enum_list); 964 rdev->mode_info.tv_std_property = 965 drm_property_create(rdev->ddev, 966 DRM_MODE_PROP_ENUM, 967 "tv standard", sz); 968 for (i = 0; i < sz; i++) { 969 drm_property_add_enum(rdev->mode_info.tv_std_property, 970 i, 971 radeon_tv_std_enum_list[i].type, 972 radeon_tv_std_enum_list[i].name); 973 } 974 975 return 0; 976 } 977 978 void radeon_update_display_priority(struct radeon_device *rdev) 979 { 980 /* adjustment options for the display watermarks */ 981 if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) { 982 /* set display priority to high for r3xx, rv515 chips 983 * this avoids flickering due to underflow to the 984 * display controllers during heavy acceleration. 985 * Don't force high on rs4xx igp chips as it seems to 986 * affect the sound card. See kernel bug 15982. 987 */ 988 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) && 989 !(rdev->flags & RADEON_IS_IGP)) 990 rdev->disp_priority = 2; 991 else 992 rdev->disp_priority = 0; 993 } else 994 rdev->disp_priority = radeon_disp_priority; 995 996 } 997 998 int radeon_modeset_init(struct radeon_device *rdev) 999 { 1000 int i; 1001 int ret; 1002 1003 drm_mode_config_init(rdev->ddev); 1004 rdev->mode_info.mode_config_initialized = true; 1005 1006 rdev->ddev->mode_config.funcs = (void *)&radeon_mode_funcs; 1007 1008 if (ASIC_IS_AVIVO(rdev)) { 1009 rdev->ddev->mode_config.max_width = 8192; 1010 rdev->ddev->mode_config.max_height = 8192; 1011 } else { 1012 rdev->ddev->mode_config.max_width = 4096; 1013 rdev->ddev->mode_config.max_height = 4096; 1014 } 1015 1016 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base; 1017 1018 ret = radeon_modeset_create_props(rdev); 1019 if (ret) { 1020 return ret; 1021 } 1022 1023 /* check combios for a valid hardcoded EDID - Sun servers */ 1024 if (!rdev->is_atom_bios) { 1025 /* check for hardcoded EDID in BIOS */ 1026 radeon_combios_check_hardcoded_edid(rdev); 1027 } 1028 1029 /* allocate crtcs */ 1030 for (i = 0; i < rdev->num_crtc; i++) { 1031 radeon_crtc_init(rdev->ddev, i); 1032 } 1033 1034 /* okay we should have all the bios connectors */ 1035 ret = radeon_setup_enc_conn(rdev->ddev); 1036 if (!ret) { 1037 return ret; 1038 } 1039 /* initialize hpd */ 1040 radeon_hpd_init(rdev); 1041 1042 /* Initialize power management */ 1043 radeon_pm_init(rdev); 1044 1045 radeon_fbdev_init(rdev); 1046 drm_kms_helper_poll_init(rdev->ddev); 1047 1048 return 0; 1049 } 1050 1051 void radeon_modeset_fini(struct radeon_device *rdev) 1052 { 1053 radeon_fbdev_fini(rdev); 1054 kfree(rdev->mode_info.bios_hardcoded_edid); 1055 radeon_pm_fini(rdev); 1056 1057 if (rdev->mode_info.mode_config_initialized) { 1058 drm_kms_helper_poll_fini(rdev->ddev); 1059 radeon_hpd_fini(rdev); 1060 drm_mode_config_cleanup(rdev->ddev); 1061 rdev->mode_info.mode_config_initialized = false; 1062 } 1063 } 1064 1065 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 1066 struct drm_display_mode *mode, 1067 struct drm_display_mode *adjusted_mode) 1068 { 1069 struct drm_device *dev = crtc->dev; 1070 struct drm_encoder *encoder; 1071 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1072 struct radeon_encoder *radeon_encoder; 1073 bool first = true; 1074 1075 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1076 radeon_encoder = to_radeon_encoder(encoder); 1077 if (encoder->crtc != crtc) 1078 continue; 1079 if (first) { 1080 /* set scaling */ 1081 if (radeon_encoder->rmx_type == RMX_OFF) 1082 radeon_crtc->rmx_type = RMX_OFF; 1083 else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay || 1084 mode->vdisplay < radeon_encoder->native_mode.vdisplay) 1085 radeon_crtc->rmx_type = radeon_encoder->rmx_type; 1086 else 1087 radeon_crtc->rmx_type = RMX_OFF; 1088 /* copy native mode */ 1089 memcpy(&radeon_crtc->native_mode, 1090 &radeon_encoder->native_mode, 1091 sizeof(struct drm_display_mode)); 1092 first = false; 1093 } else { 1094 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) { 1095 /* WARNING: Right now this can't happen but 1096 * in the future we need to check that scaling 1097 * are consistent accross different encoder 1098 * (ie all encoder can work with the same 1099 * scaling). 1100 */ 1101 DRM_ERROR("Scaling not consistent accross encoder.\n"); 1102 return false; 1103 } 1104 } 1105 } 1106 if (radeon_crtc->rmx_type != RMX_OFF) { 1107 fixed20_12 a, b; 1108 a.full = dfixed_const(crtc->mode.vdisplay); 1109 b.full = dfixed_const(radeon_crtc->native_mode.hdisplay); 1110 radeon_crtc->vsc.full = dfixed_div(a, b); 1111 a.full = dfixed_const(crtc->mode.hdisplay); 1112 b.full = dfixed_const(radeon_crtc->native_mode.vdisplay); 1113 radeon_crtc->hsc.full = dfixed_div(a, b); 1114 } else { 1115 radeon_crtc->vsc.full = dfixed_const(1); 1116 radeon_crtc->hsc.full = dfixed_const(1); 1117 } 1118 return true; 1119 } 1120