1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 27 #include <linux/pci.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/gcd.h> 30 31 #include <asm/div64.h> 32 33 #include <drm/drm_crtc_helper.h> 34 #include <drm/drm_device.h> 35 #include <drm/drm_drv.h> 36 #include <drm/drm_edid.h> 37 #include <drm/drm_fourcc.h> 38 #include <drm/drm_framebuffer.h> 39 #include <drm/drm_gem_framebuffer_helper.h> 40 #include <drm/drm_modeset_helper.h> 41 #include <drm/drm_probe_helper.h> 42 #include <drm/drm_vblank.h> 43 #include <drm/radeon_drm.h> 44 #include <drm/drm_print.h> 45 46 #include "atom.h" 47 #include "radeon.h" 48 #include "radeon_kms.h" 49 50 static void avivo_crtc_load_lut(struct drm_crtc *crtc) 51 { 52 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 53 struct drm_device *dev = crtc->dev; 54 struct radeon_device *rdev = dev->dev_private; 55 u16 *r, *g, *b; 56 int i; 57 58 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); 59 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); 60 61 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 62 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 63 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 64 65 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 66 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 67 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 68 69 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id); 70 WREG32(AVIVO_DC_LUT_RW_MODE, 0); 71 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f); 72 73 WREG8(AVIVO_DC_LUT_RW_INDEX, 0); 74 r = crtc->gamma_store; 75 g = r + crtc->gamma_size; 76 b = g + crtc->gamma_size; 77 for (i = 0; i < 256; i++) { 78 WREG32(AVIVO_DC_LUT_30_COLOR, 79 ((*r++ & 0xffc0) << 14) | 80 ((*g++ & 0xffc0) << 4) | 81 (*b++ >> 6)); 82 } 83 84 /* Only change bit 0 of LUT_SEL, other bits are set elsewhere */ 85 WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1); 86 } 87 88 static void dce4_crtc_load_lut(struct drm_crtc *crtc) 89 { 90 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 91 struct drm_device *dev = crtc->dev; 92 struct radeon_device *rdev = dev->dev_private; 93 u16 *r, *g, *b; 94 int i; 95 96 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); 97 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); 98 99 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 100 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 101 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 102 103 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 104 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 105 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 106 107 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); 108 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); 109 110 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); 111 r = crtc->gamma_store; 112 g = r + crtc->gamma_size; 113 b = g + crtc->gamma_size; 114 for (i = 0; i < 256; i++) { 115 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, 116 ((*r++ & 0xffc0) << 14) | 117 ((*g++ & 0xffc0) << 4) | 118 (*b++ >> 6)); 119 } 120 } 121 122 static void dce5_crtc_load_lut(struct drm_crtc *crtc) 123 { 124 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 125 struct drm_device *dev = crtc->dev; 126 struct radeon_device *rdev = dev->dev_private; 127 u16 *r, *g, *b; 128 int i; 129 130 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); 131 132 msleep(10); 133 134 WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset, 135 (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) | 136 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS))); 137 WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset, 138 NI_GRPH_PRESCALE_BYPASS); 139 WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset, 140 NI_OVL_PRESCALE_BYPASS); 141 WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset, 142 (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) | 143 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT))); 144 145 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); 146 147 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 148 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 149 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 150 151 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 152 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 153 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 154 155 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); 156 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); 157 158 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); 159 r = crtc->gamma_store; 160 g = r + crtc->gamma_size; 161 b = g + crtc->gamma_size; 162 for (i = 0; i < 256; i++) { 163 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, 164 ((*r++ & 0xffc0) << 14) | 165 ((*g++ & 0xffc0) << 4) | 166 (*b++ >> 6)); 167 } 168 169 WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset, 170 (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 171 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 172 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 173 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS))); 174 WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset, 175 (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) | 176 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS))); 177 WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset, 178 (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) | 179 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS))); 180 WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset, 181 (NI_OUTPUT_CSC_GRPH_MODE(radeon_crtc->output_csc) | 182 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS))); 183 /* XXX match this to the depth of the crtc fmt block, move to modeset? */ 184 WREG32(0x6940 + radeon_crtc->crtc_offset, 0); 185 if (ASIC_IS_DCE8(rdev)) { 186 /* XXX this only needs to be programmed once per crtc at startup, 187 * not sure where the best place for it is 188 */ 189 WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset, 190 CIK_CURSOR_ALPHA_BLND_ENA); 191 } 192 } 193 194 static void legacy_crtc_load_lut(struct drm_crtc *crtc) 195 { 196 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 197 struct drm_device *dev = crtc->dev; 198 struct radeon_device *rdev = dev->dev_private; 199 u16 *r, *g, *b; 200 int i; 201 uint32_t dac2_cntl; 202 203 dac2_cntl = RREG32(RADEON_DAC_CNTL2); 204 if (radeon_crtc->crtc_id == 0) 205 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL; 206 else 207 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL; 208 WREG32(RADEON_DAC_CNTL2, dac2_cntl); 209 210 WREG8(RADEON_PALETTE_INDEX, 0); 211 r = crtc->gamma_store; 212 g = r + crtc->gamma_size; 213 b = g + crtc->gamma_size; 214 for (i = 0; i < 256; i++) { 215 WREG32(RADEON_PALETTE_30_DATA, 216 ((*r++ & 0xffc0) << 14) | 217 ((*g++ & 0xffc0) << 4) | 218 (*b++ >> 6)); 219 } 220 } 221 222 void radeon_crtc_load_lut(struct drm_crtc *crtc) 223 { 224 struct drm_device *dev = crtc->dev; 225 struct radeon_device *rdev = dev->dev_private; 226 227 if (!crtc->enabled) 228 return; 229 230 if (ASIC_IS_DCE5(rdev)) 231 dce5_crtc_load_lut(crtc); 232 else if (ASIC_IS_DCE4(rdev)) 233 dce4_crtc_load_lut(crtc); 234 else if (ASIC_IS_AVIVO(rdev)) 235 avivo_crtc_load_lut(crtc); 236 else 237 legacy_crtc_load_lut(crtc); 238 } 239 240 static int radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 241 u16 *blue, uint32_t size, 242 struct drm_modeset_acquire_ctx *ctx) 243 { 244 radeon_crtc_load_lut(crtc); 245 246 return 0; 247 } 248 249 static void radeon_crtc_destroy(struct drm_crtc *crtc) 250 { 251 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 252 253 drm_crtc_cleanup(crtc); 254 destroy_workqueue(radeon_crtc->flip_queue); 255 kfree(radeon_crtc); 256 } 257 258 /** 259 * radeon_unpin_work_func - unpin old buffer object 260 * 261 * @__work: kernel work item 262 * 263 * Unpin the old frame buffer object outside of the interrupt handler 264 */ 265 static void radeon_unpin_work_func(struct work_struct *__work) 266 { 267 struct radeon_flip_work *work = 268 container_of(__work, struct radeon_flip_work, unpin_work); 269 int r; 270 271 /* unpin of the old buffer */ 272 r = radeon_bo_reserve(work->old_rbo, false); 273 if (likely(r == 0)) { 274 radeon_bo_unpin(work->old_rbo); 275 radeon_bo_unreserve(work->old_rbo); 276 } else 277 drm_err(&work->rdev->ddev, "failed to reserve buffer after flip\n"); 278 279 drm_gem_object_put(&work->old_rbo->tbo.base); 280 kfree(work); 281 } 282 283 void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id) 284 { 285 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 286 unsigned long flags; 287 u32 update_pending; 288 int vpos, hpos; 289 290 /* can happen during initialization */ 291 if (radeon_crtc == NULL) 292 return; 293 294 /* Skip the pageflip completion check below (based on polling) on 295 * asics which reliably support hw pageflip completion irqs. pflip 296 * irqs are a reliable and race-free method of handling pageflip 297 * completion detection. A use_pflipirq module parameter < 2 allows 298 * to override this in case of asics with faulty pflip irqs. 299 * A module parameter of 0 would only use this polling based path, 300 * a parameter of 1 would use pflip irq only as a backup to this 301 * path, as in Linux 3.16. 302 */ 303 if ((radeon_use_pflipirq == 2) && ASIC_IS_DCE4(rdev)) 304 return; 305 306 spin_lock_irqsave(&rdev_to_drm(rdev)->event_lock, flags); 307 if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) { 308 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != " 309 "RADEON_FLIP_SUBMITTED(%d)\n", 310 radeon_crtc->flip_status, 311 RADEON_FLIP_SUBMITTED); 312 spin_unlock_irqrestore(&rdev_to_drm(rdev)->event_lock, flags); 313 return; 314 } 315 316 update_pending = radeon_page_flip_pending(rdev, crtc_id); 317 318 /* Has the pageflip already completed in crtc, or is it certain 319 * to complete in this vblank? GET_DISTANCE_TO_VBLANKSTART provides 320 * distance to start of "fudged earlier" vblank in vpos, distance to 321 * start of real vblank in hpos. vpos >= 0 && hpos < 0 means we are in 322 * the last few scanlines before start of real vblank, where the vblank 323 * irq can fire, so we have sampled update_pending a bit too early and 324 * know the flip will complete at leading edge of the upcoming real 325 * vblank. On pre-AVIVO hardware, flips also complete inside the real 326 * vblank, not only at leading edge, so if update_pending for hpos >= 0 327 * == inside real vblank, the flip will complete almost immediately. 328 * Note that this method of completion handling is still not 100% race 329 * free, as we could execute before the radeon_flip_work_func managed 330 * to run and set the RADEON_FLIP_SUBMITTED status, thereby we no-op, 331 * but the flip still gets programmed into hw and completed during 332 * vblank, leading to a delayed emission of the flip completion event. 333 * This applies at least to pre-AVIVO hardware, where flips are always 334 * completing inside vblank, not only at leading edge of vblank. 335 */ 336 if (update_pending && 337 (DRM_SCANOUTPOS_VALID & 338 radeon_get_crtc_scanoutpos(rdev_to_drm(rdev), crtc_id, 339 GET_DISTANCE_TO_VBLANKSTART, 340 &vpos, &hpos, NULL, NULL, 341 &rdev->mode_info.crtcs[crtc_id]->base.hwmode)) && 342 ((vpos >= 0 && hpos < 0) || (hpos >= 0 && !ASIC_IS_AVIVO(rdev)))) { 343 /* crtc didn't flip in this target vblank interval, 344 * but flip is pending in crtc. Based on the current 345 * scanout position we know that the current frame is 346 * (nearly) complete and the flip will (likely) 347 * complete before the start of the next frame. 348 */ 349 update_pending = 0; 350 } 351 spin_unlock_irqrestore(&rdev_to_drm(rdev)->event_lock, flags); 352 if (!update_pending) 353 radeon_crtc_handle_flip(rdev, crtc_id); 354 } 355 356 /** 357 * radeon_crtc_handle_flip - page flip completed 358 * 359 * @rdev: radeon device pointer 360 * @crtc_id: crtc number this event is for 361 * 362 * Called when we are sure that a page flip for this crtc is completed. 363 */ 364 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id) 365 { 366 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 367 struct radeon_flip_work *work; 368 unsigned long flags; 369 370 /* this can happen at init */ 371 if (radeon_crtc == NULL) 372 return; 373 374 spin_lock_irqsave(&rdev_to_drm(rdev)->event_lock, flags); 375 work = radeon_crtc->flip_work; 376 if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) { 377 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != " 378 "RADEON_FLIP_SUBMITTED(%d)\n", 379 radeon_crtc->flip_status, 380 RADEON_FLIP_SUBMITTED); 381 spin_unlock_irqrestore(&rdev_to_drm(rdev)->event_lock, flags); 382 return; 383 } 384 385 /* Pageflip completed. Clean up. */ 386 radeon_crtc->flip_status = RADEON_FLIP_NONE; 387 radeon_crtc->flip_work = NULL; 388 389 /* wakeup userspace */ 390 if (work->event) 391 drm_crtc_send_vblank_event(&radeon_crtc->base, work->event); 392 393 spin_unlock_irqrestore(&rdev_to_drm(rdev)->event_lock, flags); 394 395 drm_crtc_vblank_put(&radeon_crtc->base); 396 radeon_irq_kms_pflip_irq_put(rdev, work->crtc_id); 397 queue_work(radeon_crtc->flip_queue, &work->unpin_work); 398 } 399 400 /** 401 * radeon_flip_work_func - page flip framebuffer 402 * 403 * @__work: kernel work item 404 * 405 * Wait for the buffer object to become idle and do the actual page flip 406 */ 407 static void radeon_flip_work_func(struct work_struct *__work) 408 { 409 struct radeon_flip_work *work = 410 container_of(__work, struct radeon_flip_work, flip_work); 411 struct radeon_device *rdev = work->rdev; 412 struct drm_device *dev = rdev_to_drm(rdev); 413 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[work->crtc_id]; 414 415 struct drm_crtc *crtc = &radeon_crtc->base; 416 unsigned long flags; 417 int r; 418 int vpos, hpos; 419 420 down_read(&rdev->exclusive_lock); 421 if (work->fence) { 422 struct radeon_fence *fence; 423 424 fence = to_radeon_fence(work->fence); 425 if (fence && fence->rdev == rdev) { 426 r = radeon_fence_wait(fence, false); 427 if (r == -EDEADLK) { 428 up_read(&rdev->exclusive_lock); 429 do { 430 r = radeon_gpu_reset(rdev); 431 } while (r == -EAGAIN); 432 down_read(&rdev->exclusive_lock); 433 } 434 } else 435 r = dma_fence_wait(work->fence, false); 436 437 if (r) 438 drm_err(dev, "failed to wait on page flip fence (%d)!\n", r); 439 440 /* We continue with the page flip even if we failed to wait on 441 * the fence, otherwise the DRM core and userspace will be 442 * confused about which BO the CRTC is scanning out 443 */ 444 445 dma_fence_put(work->fence); 446 work->fence = NULL; 447 } 448 449 /* Wait until we're out of the vertical blank period before the one 450 * targeted by the flip. Always wait on pre DCE4 to avoid races with 451 * flip completion handling from vblank irq, as these old asics don't 452 * have reliable pageflip completion interrupts. 453 */ 454 while (radeon_crtc->enabled && 455 (radeon_get_crtc_scanoutpos(dev, work->crtc_id, 0, 456 &vpos, &hpos, NULL, NULL, 457 &crtc->hwmode) 458 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) == 459 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) && 460 (!ASIC_IS_AVIVO(rdev) || 461 ((int) (work->target_vblank - 462 crtc->funcs->get_vblank_counter(crtc)) > 0))) 463 usleep_range(1000, 2000); 464 465 /* We borrow the event spin lock for protecting flip_status */ 466 spin_lock_irqsave(&crtc->dev->event_lock, flags); 467 468 /* set the proper interrupt */ 469 radeon_irq_kms_pflip_irq_get(rdev, radeon_crtc->crtc_id); 470 471 /* do the flip (mmio) */ 472 radeon_page_flip(rdev, radeon_crtc->crtc_id, work->base, work->async); 473 474 radeon_crtc->flip_status = RADEON_FLIP_SUBMITTED; 475 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 476 up_read(&rdev->exclusive_lock); 477 } 478 479 static int radeon_crtc_page_flip_target(struct drm_crtc *crtc, 480 struct drm_framebuffer *fb, 481 struct drm_pending_vblank_event *event, 482 uint32_t page_flip_flags, 483 uint32_t target, 484 struct drm_modeset_acquire_ctx *ctx) 485 { 486 struct drm_device *dev = crtc->dev; 487 struct radeon_device *rdev = dev->dev_private; 488 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 489 struct drm_gem_object *obj; 490 struct radeon_flip_work *work; 491 struct radeon_bo *new_rbo; 492 uint32_t tiling_flags, pitch_pixels; 493 uint64_t base; 494 unsigned long flags; 495 int r; 496 497 work = kzalloc_obj(*work); 498 if (work == NULL) 499 return -ENOMEM; 500 501 INIT_WORK(&work->flip_work, radeon_flip_work_func); 502 INIT_WORK(&work->unpin_work, radeon_unpin_work_func); 503 504 work->rdev = rdev; 505 work->crtc_id = radeon_crtc->crtc_id; 506 work->event = event; 507 work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0; 508 509 /* schedule unpin of the old buffer */ 510 obj = crtc->primary->fb->obj[0]; 511 512 /* take a reference to the old object */ 513 drm_gem_object_get(obj); 514 work->old_rbo = gem_to_radeon_bo(obj); 515 516 obj = fb->obj[0]; 517 new_rbo = gem_to_radeon_bo(obj); 518 519 /* pin the new buffer */ 520 DRM_DEBUG_DRIVER("flip-ioctl() cur_rbo = %p, new_rbo = %p\n", 521 work->old_rbo, new_rbo); 522 523 r = radeon_bo_reserve(new_rbo, false); 524 if (unlikely(r != 0)) { 525 drm_err(dev, "failed to reserve new rbo buffer before flip\n"); 526 goto cleanup; 527 } 528 /* Only 27 bit offset for legacy CRTC */ 529 r = radeon_bo_pin_restricted(new_rbo, RADEON_GEM_DOMAIN_VRAM, 530 ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base); 531 if (unlikely(r != 0)) { 532 radeon_bo_unreserve(new_rbo); 533 r = -EINVAL; 534 drm_err(dev, "failed to pin new rbo buffer before flip\n"); 535 goto cleanup; 536 } 537 r = dma_resv_get_singleton(new_rbo->tbo.base.resv, DMA_RESV_USAGE_WRITE, 538 &work->fence); 539 if (r) { 540 radeon_bo_unreserve(new_rbo); 541 drm_err(dev, "failed to get new rbo buffer fences\n"); 542 goto cleanup; 543 } 544 radeon_bo_get_tiling_flags(new_rbo, &tiling_flags, NULL); 545 radeon_bo_unreserve(new_rbo); 546 547 if (!ASIC_IS_AVIVO(rdev)) { 548 /* crtc offset is from display base addr not FB location */ 549 base -= radeon_crtc->legacy_display_base_addr; 550 pitch_pixels = fb->pitches[0] / fb->format->cpp[0]; 551 552 if (tiling_flags & RADEON_TILING_MACRO) { 553 if (ASIC_IS_R300(rdev)) { 554 base &= ~0x7ff; 555 } else { 556 int byteshift = fb->format->cpp[0] * 8 >> 4; 557 int tile_addr = (((crtc->y >> 3) * pitch_pixels + crtc->x) >> (8 - byteshift)) << 11; 558 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8); 559 } 560 } else { 561 int offset = crtc->y * pitch_pixels + crtc->x; 562 switch (fb->format->cpp[0] * 8) { 563 case 8: 564 default: 565 offset *= 1; 566 break; 567 case 15: 568 case 16: 569 offset *= 2; 570 break; 571 case 24: 572 offset *= 3; 573 break; 574 case 32: 575 offset *= 4; 576 break; 577 } 578 base += offset; 579 } 580 base &= ~7; 581 } 582 work->base = base; 583 work->target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) + 584 crtc->funcs->get_vblank_counter(crtc); 585 586 /* We borrow the event spin lock for protecting flip_work */ 587 spin_lock_irqsave(&crtc->dev->event_lock, flags); 588 589 if (radeon_crtc->flip_status != RADEON_FLIP_NONE) { 590 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); 591 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 592 r = -EBUSY; 593 goto pflip_cleanup; 594 } 595 radeon_crtc->flip_status = RADEON_FLIP_PENDING; 596 radeon_crtc->flip_work = work; 597 598 /* update crtc fb */ 599 crtc->primary->fb = fb; 600 601 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 602 603 queue_work(radeon_crtc->flip_queue, &work->flip_work); 604 return 0; 605 606 pflip_cleanup: 607 if (unlikely(radeon_bo_reserve(new_rbo, false) != 0)) { 608 drm_err(dev, "failed to reserve new rbo in error path\n"); 609 goto cleanup; 610 } 611 radeon_bo_unpin(new_rbo); 612 radeon_bo_unreserve(new_rbo); 613 614 cleanup: 615 drm_gem_object_put(&work->old_rbo->tbo.base); 616 dma_fence_put(work->fence); 617 kfree(work); 618 return r; 619 } 620 621 static int 622 radeon_crtc_set_config(struct drm_mode_set *set, 623 struct drm_modeset_acquire_ctx *ctx) 624 { 625 struct drm_device *dev; 626 struct radeon_device *rdev; 627 struct drm_crtc *crtc; 628 bool active = false; 629 int ret; 630 631 if (!set || !set->crtc) 632 return -EINVAL; 633 634 dev = set->crtc->dev; 635 636 ret = pm_runtime_get_sync(dev->dev); 637 if (ret < 0) { 638 pm_runtime_put_autosuspend(dev->dev); 639 return ret; 640 } 641 642 ret = drm_crtc_helper_set_config(set, ctx); 643 644 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) 645 if (crtc->enabled) 646 active = true; 647 648 rdev = dev->dev_private; 649 /* if we have active crtcs and we don't have a power ref, 650 take the current one */ 651 if (active && !rdev->have_disp_power_ref) { 652 rdev->have_disp_power_ref = true; 653 return ret; 654 } 655 /* if we have no active crtcs, then drop the power ref 656 we got before */ 657 if (!active && rdev->have_disp_power_ref) { 658 pm_runtime_put_autosuspend(dev->dev); 659 rdev->have_disp_power_ref = false; 660 } 661 662 /* drop the power reference we got coming in here */ 663 pm_runtime_put_autosuspend(dev->dev); 664 return ret; 665 } 666 667 static const struct drm_crtc_funcs radeon_crtc_funcs = { 668 .cursor_set2 = radeon_crtc_cursor_set2, 669 .cursor_move = radeon_crtc_cursor_move, 670 .gamma_set = radeon_crtc_gamma_set, 671 .set_config = radeon_crtc_set_config, 672 .destroy = radeon_crtc_destroy, 673 .page_flip_target = radeon_crtc_page_flip_target, 674 .get_vblank_counter = radeon_get_vblank_counter_kms, 675 .enable_vblank = radeon_enable_vblank_kms, 676 .disable_vblank = radeon_disable_vblank_kms, 677 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, 678 }; 679 680 static void radeon_crtc_init(struct drm_device *dev, int index) 681 { 682 struct radeon_device *rdev = dev->dev_private; 683 struct radeon_crtc *radeon_crtc; 684 685 radeon_crtc = kzalloc_obj(*radeon_crtc); 686 if (radeon_crtc == NULL) 687 return; 688 689 radeon_crtc->flip_queue = alloc_workqueue("radeon-crtc", 690 WQ_HIGHPRI | WQ_PERCPU, 0); 691 if (!radeon_crtc->flip_queue) { 692 kfree(radeon_crtc); 693 return; 694 } 695 696 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs); 697 698 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256); 699 radeon_crtc->crtc_id = index; 700 rdev->mode_info.crtcs[index] = radeon_crtc; 701 702 if (rdev->family >= CHIP_BONAIRE) { 703 radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH; 704 radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT; 705 } else { 706 radeon_crtc->max_cursor_width = CURSOR_WIDTH; 707 radeon_crtc->max_cursor_height = CURSOR_HEIGHT; 708 } 709 dev->mode_config.cursor_width = radeon_crtc->max_cursor_width; 710 dev->mode_config.cursor_height = radeon_crtc->max_cursor_height; 711 712 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)) 713 radeon_atombios_init_crtc(dev, radeon_crtc); 714 else 715 radeon_legacy_init_crtc(dev, radeon_crtc); 716 } 717 718 static const char *encoder_names[38] = { 719 "NONE", 720 "INTERNAL_LVDS", 721 "INTERNAL_TMDS1", 722 "INTERNAL_TMDS2", 723 "INTERNAL_DAC1", 724 "INTERNAL_DAC2", 725 "INTERNAL_SDVOA", 726 "INTERNAL_SDVOB", 727 "SI170B", 728 "CH7303", 729 "CH7301", 730 "INTERNAL_DVO1", 731 "EXTERNAL_SDVOA", 732 "EXTERNAL_SDVOB", 733 "TITFP513", 734 "INTERNAL_LVTM1", 735 "VT1623", 736 "HDMI_SI1930", 737 "HDMI_INTERNAL", 738 "INTERNAL_KLDSCP_TMDS1", 739 "INTERNAL_KLDSCP_DVO1", 740 "INTERNAL_KLDSCP_DAC1", 741 "INTERNAL_KLDSCP_DAC2", 742 "SI178", 743 "MVPU_FPGA", 744 "INTERNAL_DDI", 745 "VT1625", 746 "HDMI_SI1932", 747 "DP_AN9801", 748 "DP_DP501", 749 "INTERNAL_UNIPHY", 750 "INTERNAL_KLDSCP_LVTMA", 751 "INTERNAL_UNIPHY1", 752 "INTERNAL_UNIPHY2", 753 "NUTMEG", 754 "TRAVIS", 755 "INTERNAL_VCE", 756 "INTERNAL_UNIPHY3", 757 }; 758 759 static const char *hpd_names[6] = { 760 "HPD1", 761 "HPD2", 762 "HPD3", 763 "HPD4", 764 "HPD5", 765 "HPD6", 766 }; 767 768 static void radeon_print_display_setup(struct drm_device *dev) 769 { 770 struct drm_connector *connector; 771 struct radeon_connector *radeon_connector; 772 struct drm_encoder *encoder; 773 struct radeon_encoder *radeon_encoder; 774 uint32_t devices; 775 int i = 0; 776 777 drm_info(dev, "Radeon Display Connectors\n"); 778 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 779 radeon_connector = to_radeon_connector(connector); 780 drm_info(dev, "Connector %d:\n", i); 781 drm_info(dev, " %s\n", connector->name); 782 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) 783 drm_info(dev, " %s\n", hpd_names[radeon_connector->hpd.hpd]); 784 if (radeon_connector->ddc_bus) { 785 drm_info(dev, " DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", 786 radeon_connector->ddc_bus->rec.mask_clk_reg, 787 radeon_connector->ddc_bus->rec.mask_data_reg, 788 radeon_connector->ddc_bus->rec.a_clk_reg, 789 radeon_connector->ddc_bus->rec.a_data_reg, 790 radeon_connector->ddc_bus->rec.en_clk_reg, 791 radeon_connector->ddc_bus->rec.en_data_reg, 792 radeon_connector->ddc_bus->rec.y_clk_reg, 793 radeon_connector->ddc_bus->rec.y_data_reg); 794 if (radeon_connector->router.ddc_valid) 795 drm_info(dev, " DDC Router 0x%x/0x%x\n", 796 radeon_connector->router.ddc_mux_control_pin, 797 radeon_connector->router.ddc_mux_state); 798 if (radeon_connector->router.cd_valid) 799 drm_info(dev, " Clock/Data Router 0x%x/0x%x\n", 800 radeon_connector->router.cd_mux_control_pin, 801 radeon_connector->router.cd_mux_state); 802 } else { 803 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || 804 connector->connector_type == DRM_MODE_CONNECTOR_DVII || 805 connector->connector_type == DRM_MODE_CONNECTOR_DVID || 806 connector->connector_type == DRM_MODE_CONNECTOR_DVIA || 807 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || 808 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) 809 drm_info(dev, " DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n"); 810 } 811 drm_info(dev, " Encoders:\n"); 812 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 813 radeon_encoder = to_radeon_encoder(encoder); 814 devices = radeon_encoder->devices & radeon_connector->devices; 815 if (devices) { 816 if (devices & ATOM_DEVICE_CRT1_SUPPORT) 817 drm_info(dev, " CRT1: %s\n", 818 encoder_names[radeon_encoder->encoder_id]); 819 if (devices & ATOM_DEVICE_CRT2_SUPPORT) 820 drm_info(dev, " CRT2: %s\n", 821 encoder_names[radeon_encoder->encoder_id]); 822 if (devices & ATOM_DEVICE_LCD1_SUPPORT) 823 drm_info(dev, " LCD1: %s\n", 824 encoder_names[radeon_encoder->encoder_id]); 825 if (devices & ATOM_DEVICE_DFP1_SUPPORT) 826 drm_info(dev, " DFP1: %s\n", 827 encoder_names[radeon_encoder->encoder_id]); 828 if (devices & ATOM_DEVICE_DFP2_SUPPORT) 829 drm_info(dev, " DFP2: %s\n", 830 encoder_names[radeon_encoder->encoder_id]); 831 if (devices & ATOM_DEVICE_DFP3_SUPPORT) 832 drm_info(dev, " DFP3: %s\n", 833 encoder_names[radeon_encoder->encoder_id]); 834 if (devices & ATOM_DEVICE_DFP4_SUPPORT) 835 drm_info(dev, " DFP4: %s\n", 836 encoder_names[radeon_encoder->encoder_id]); 837 if (devices & ATOM_DEVICE_DFP5_SUPPORT) 838 drm_info(dev, " DFP5: %s\n", 839 encoder_names[radeon_encoder->encoder_id]); 840 if (devices & ATOM_DEVICE_DFP6_SUPPORT) 841 drm_info(dev, " DFP6: %s\n", 842 encoder_names[radeon_encoder->encoder_id]); 843 if (devices & ATOM_DEVICE_TV1_SUPPORT) 844 drm_info(dev, " TV1: %s\n", 845 encoder_names[radeon_encoder->encoder_id]); 846 if (devices & ATOM_DEVICE_CV_SUPPORT) 847 drm_info(dev, " CV: %s\n", 848 encoder_names[radeon_encoder->encoder_id]); 849 } 850 } 851 i++; 852 } 853 } 854 855 static bool radeon_setup_enc_conn(struct drm_device *dev) 856 { 857 struct radeon_device *rdev = dev->dev_private; 858 bool ret = false; 859 860 if (rdev->bios) { 861 if (rdev->is_atom_bios) { 862 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev); 863 if (!ret) 864 ret = radeon_get_atom_connector_info_from_object_table(dev); 865 } else { 866 ret = radeon_get_legacy_connector_info_from_bios(dev); 867 if (!ret) 868 ret = radeon_get_legacy_connector_info_from_table(dev); 869 } 870 } else { 871 if (!ASIC_IS_AVIVO(rdev)) 872 ret = radeon_get_legacy_connector_info_from_table(dev); 873 } 874 if (ret) { 875 radeon_setup_encoder_clones(dev); 876 radeon_print_display_setup(dev); 877 } 878 879 return ret; 880 } 881 882 /* avivo */ 883 884 /** 885 * avivo_reduce_ratio - fractional number reduction 886 * 887 * @nom: nominator 888 * @den: denominator 889 * @nom_min: minimum value for nominator 890 * @den_min: minimum value for denominator 891 * 892 * Find the greatest common divisor and apply it on both nominator and 893 * denominator, but make nominator and denominator are at least as large 894 * as their minimum values. 895 */ 896 static void avivo_reduce_ratio(unsigned *nom, unsigned *den, 897 unsigned nom_min, unsigned den_min) 898 { 899 unsigned tmp; 900 901 /* reduce the numbers to a simpler ratio */ 902 tmp = gcd(*nom, *den); 903 *nom /= tmp; 904 *den /= tmp; 905 906 /* make sure nominator is large enough */ 907 if (*nom < nom_min) { 908 tmp = DIV_ROUND_UP(nom_min, *nom); 909 *nom *= tmp; 910 *den *= tmp; 911 } 912 913 /* make sure the denominator is large enough */ 914 if (*den < den_min) { 915 tmp = DIV_ROUND_UP(den_min, *den); 916 *nom *= tmp; 917 *den *= tmp; 918 } 919 } 920 921 /** 922 * avivo_get_fb_ref_div - feedback and ref divider calculation 923 * 924 * @nom: nominator 925 * @den: denominator 926 * @post_div: post divider 927 * @fb_div_max: feedback divider maximum 928 * @ref_div_max: reference divider maximum 929 * @fb_div: resulting feedback divider 930 * @ref_div: resulting reference divider 931 * 932 * Calculate feedback and reference divider for a given post divider. Makes 933 * sure we stay within the limits. 934 */ 935 static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div, 936 unsigned fb_div_max, unsigned ref_div_max, 937 unsigned *fb_div, unsigned *ref_div) 938 { 939 /* limit reference * post divider to a maximum */ 940 ref_div_max = clamp(100 / post_div, 1u, ref_div_max); 941 942 /* get matching reference and feedback divider */ 943 *ref_div = clamp(den / post_div, 1u, ref_div_max); 944 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den); 945 946 /* limit fb divider to its maximum */ 947 if (*fb_div > fb_div_max) { 948 *ref_div = (*ref_div * fb_div_max)/(*fb_div); 949 *fb_div = fb_div_max; 950 } 951 } 952 953 /** 954 * radeon_compute_pll_avivo - compute PLL paramaters 955 * 956 * @pll: information about the PLL 957 * @freq: target frequency 958 * @dot_clock_p: resulting pixel clock 959 * @fb_div_p: resulting feedback divider 960 * @frac_fb_div_p: fractional part of the feedback divider 961 * @ref_div_p: resulting reference divider 962 * @post_div_p: resulting reference divider 963 * 964 * Try to calculate the PLL parameters to generate the given frequency: 965 * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div) 966 */ 967 void radeon_compute_pll_avivo(struct radeon_pll *pll, 968 u32 freq, 969 u32 *dot_clock_p, 970 u32 *fb_div_p, 971 u32 *frac_fb_div_p, 972 u32 *ref_div_p, 973 u32 *post_div_p) 974 { 975 unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ? 976 freq : freq / 10; 977 978 unsigned fb_div_min, fb_div_max, fb_div; 979 unsigned post_div_min, post_div_max, post_div; 980 unsigned ref_div_min, ref_div_max, ref_div; 981 unsigned post_div_best, diff_best; 982 unsigned nom, den; 983 984 /* determine allowed feedback divider range */ 985 fb_div_min = pll->min_feedback_div; 986 fb_div_max = pll->max_feedback_div; 987 988 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 989 fb_div_min *= 10; 990 fb_div_max *= 10; 991 } 992 993 /* determine allowed ref divider range */ 994 if (pll->flags & RADEON_PLL_USE_REF_DIV) 995 ref_div_min = pll->reference_div; 996 else 997 ref_div_min = pll->min_ref_div; 998 999 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && 1000 pll->flags & RADEON_PLL_USE_REF_DIV) 1001 ref_div_max = pll->reference_div; 1002 else if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) 1003 /* fix for problems on RS880 */ 1004 ref_div_max = min(pll->max_ref_div, 7u); 1005 else 1006 ref_div_max = pll->max_ref_div; 1007 1008 /* determine allowed post divider range */ 1009 if (pll->flags & RADEON_PLL_USE_POST_DIV) { 1010 post_div_min = pll->post_div; 1011 post_div_max = pll->post_div; 1012 } else { 1013 unsigned vco_min, vco_max; 1014 1015 if (pll->flags & RADEON_PLL_IS_LCD) { 1016 vco_min = pll->lcd_pll_out_min; 1017 vco_max = pll->lcd_pll_out_max; 1018 } else { 1019 vco_min = pll->pll_out_min; 1020 vco_max = pll->pll_out_max; 1021 } 1022 1023 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 1024 vco_min *= 10; 1025 vco_max *= 10; 1026 } 1027 1028 post_div_min = vco_min / target_clock; 1029 if ((target_clock * post_div_min) < vco_min) 1030 ++post_div_min; 1031 if (post_div_min < pll->min_post_div) 1032 post_div_min = pll->min_post_div; 1033 1034 post_div_max = vco_max / target_clock; 1035 if ((target_clock * post_div_max) > vco_max) 1036 --post_div_max; 1037 if (post_div_max > pll->max_post_div) 1038 post_div_max = pll->max_post_div; 1039 } 1040 1041 /* represent the searched ratio as fractional number */ 1042 nom = target_clock; 1043 den = pll->reference_freq; 1044 1045 /* reduce the numbers to a simpler ratio */ 1046 avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min); 1047 1048 /* now search for a post divider */ 1049 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) 1050 post_div_best = post_div_min; 1051 else 1052 post_div_best = post_div_max; 1053 diff_best = ~0; 1054 1055 for (post_div = post_div_min; post_div <= post_div_max; ++post_div) { 1056 unsigned diff; 1057 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, 1058 ref_div_max, &fb_div, &ref_div); 1059 diff = abs(target_clock - (pll->reference_freq * fb_div) / 1060 (ref_div * post_div)); 1061 1062 if (diff < diff_best || (diff == diff_best && 1063 !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) { 1064 1065 post_div_best = post_div; 1066 diff_best = diff; 1067 } 1068 } 1069 post_div = post_div_best; 1070 1071 /* get the feedback and reference divider for the optimal value */ 1072 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max, 1073 &fb_div, &ref_div); 1074 1075 /* reduce the numbers to a simpler ratio once more */ 1076 /* this also makes sure that the reference divider is large enough */ 1077 avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min); 1078 1079 /* avoid high jitter with small fractional dividers */ 1080 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) { 1081 fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 50); 1082 if (fb_div < fb_div_min) { 1083 unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div); 1084 fb_div *= tmp; 1085 ref_div *= tmp; 1086 } 1087 } 1088 1089 /* and finally save the result */ 1090 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 1091 *fb_div_p = fb_div / 10; 1092 *frac_fb_div_p = fb_div % 10; 1093 } else { 1094 *fb_div_p = fb_div; 1095 *frac_fb_div_p = 0; 1096 } 1097 1098 *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) + 1099 (pll->reference_freq * *frac_fb_div_p)) / 1100 (ref_div * post_div * 10); 1101 *ref_div_p = ref_div; 1102 *post_div_p = post_div; 1103 1104 DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n", 1105 freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p, 1106 ref_div, post_div); 1107 } 1108 1109 /* pre-avivo */ 1110 static inline uint32_t radeon_div(uint64_t n, uint32_t d) 1111 { 1112 n += d / 2; 1113 1114 do_div(n, d); 1115 return n; 1116 } 1117 1118 void radeon_compute_pll_legacy(struct radeon_pll *pll, 1119 uint64_t freq, 1120 uint32_t *dot_clock_p, 1121 uint32_t *fb_div_p, 1122 uint32_t *frac_fb_div_p, 1123 uint32_t *ref_div_p, 1124 uint32_t *post_div_p) 1125 { 1126 uint32_t min_ref_div = pll->min_ref_div; 1127 uint32_t max_ref_div = pll->max_ref_div; 1128 uint32_t min_post_div = pll->min_post_div; 1129 uint32_t max_post_div = pll->max_post_div; 1130 uint32_t min_fractional_feed_div = 0; 1131 uint32_t max_fractional_feed_div = 0; 1132 uint32_t best_vco = pll->best_vco; 1133 uint32_t best_post_div = 1; 1134 uint32_t best_ref_div = 1; 1135 uint32_t best_feedback_div = 1; 1136 uint32_t best_frac_feedback_div = 0; 1137 uint32_t best_freq = -1; 1138 uint32_t best_error = 0xffffffff; 1139 uint32_t best_vco_diff = 1; 1140 uint32_t post_div; 1141 u32 pll_out_min, pll_out_max; 1142 1143 DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div); 1144 freq = freq * 1000; 1145 1146 if (pll->flags & RADEON_PLL_IS_LCD) { 1147 pll_out_min = pll->lcd_pll_out_min; 1148 pll_out_max = pll->lcd_pll_out_max; 1149 } else { 1150 pll_out_min = pll->pll_out_min; 1151 pll_out_max = pll->pll_out_max; 1152 } 1153 1154 if (pll_out_min > 64800) 1155 pll_out_min = 64800; 1156 1157 if (pll->flags & RADEON_PLL_USE_REF_DIV) 1158 min_ref_div = max_ref_div = pll->reference_div; 1159 else { 1160 while (min_ref_div < max_ref_div-1) { 1161 uint32_t mid = (min_ref_div + max_ref_div) / 2; 1162 uint32_t pll_in = pll->reference_freq / mid; 1163 if (pll_in < pll->pll_in_min) 1164 max_ref_div = mid; 1165 else if (pll_in > pll->pll_in_max) 1166 min_ref_div = mid; 1167 else 1168 break; 1169 } 1170 } 1171 1172 if (pll->flags & RADEON_PLL_USE_POST_DIV) 1173 min_post_div = max_post_div = pll->post_div; 1174 1175 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 1176 min_fractional_feed_div = pll->min_frac_feedback_div; 1177 max_fractional_feed_div = pll->max_frac_feedback_div; 1178 } 1179 1180 for (post_div = max_post_div; post_div >= min_post_div; --post_div) { 1181 uint32_t ref_div; 1182 1183 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) 1184 continue; 1185 1186 /* legacy radeons only have a few post_divs */ 1187 if (pll->flags & RADEON_PLL_LEGACY) { 1188 if ((post_div == 5) || 1189 (post_div == 7) || 1190 (post_div == 9) || 1191 (post_div == 10) || 1192 (post_div == 11) || 1193 (post_div == 13) || 1194 (post_div == 14) || 1195 (post_div == 15)) 1196 continue; 1197 } 1198 1199 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) { 1200 uint32_t feedback_div, current_freq = 0, error, vco_diff; 1201 uint32_t pll_in = pll->reference_freq / ref_div; 1202 uint32_t min_feed_div = pll->min_feedback_div; 1203 uint32_t max_feed_div = pll->max_feedback_div + 1; 1204 1205 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max) 1206 continue; 1207 1208 while (min_feed_div < max_feed_div) { 1209 uint32_t vco; 1210 uint32_t min_frac_feed_div = min_fractional_feed_div; 1211 uint32_t max_frac_feed_div = max_fractional_feed_div + 1; 1212 uint32_t frac_feedback_div; 1213 uint64_t tmp; 1214 1215 feedback_div = (min_feed_div + max_feed_div) / 2; 1216 1217 tmp = (uint64_t)pll->reference_freq * feedback_div; 1218 vco = radeon_div(tmp, ref_div); 1219 1220 if (vco < pll_out_min) { 1221 min_feed_div = feedback_div + 1; 1222 continue; 1223 } else if (vco > pll_out_max) { 1224 max_feed_div = feedback_div; 1225 continue; 1226 } 1227 1228 while (min_frac_feed_div < max_frac_feed_div) { 1229 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2; 1230 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div; 1231 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div; 1232 current_freq = radeon_div(tmp, ref_div * post_div); 1233 1234 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) { 1235 if (freq < current_freq) 1236 error = 0xffffffff; 1237 else 1238 error = freq - current_freq; 1239 } else 1240 error = abs(current_freq - freq); 1241 vco_diff = abs(vco - best_vco); 1242 1243 if ((best_vco == 0 && error < best_error) || 1244 (best_vco != 0 && 1245 ((best_error > 100 && error < best_error - 100) || 1246 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) { 1247 best_post_div = post_div; 1248 best_ref_div = ref_div; 1249 best_feedback_div = feedback_div; 1250 best_frac_feedback_div = frac_feedback_div; 1251 best_freq = current_freq; 1252 best_error = error; 1253 best_vco_diff = vco_diff; 1254 } else if (current_freq == freq) { 1255 if (best_freq == -1) { 1256 best_post_div = post_div; 1257 best_ref_div = ref_div; 1258 best_feedback_div = feedback_div; 1259 best_frac_feedback_div = frac_feedback_div; 1260 best_freq = current_freq; 1261 best_error = error; 1262 best_vco_diff = vco_diff; 1263 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) || 1264 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) || 1265 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) || 1266 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) || 1267 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) || 1268 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) { 1269 best_post_div = post_div; 1270 best_ref_div = ref_div; 1271 best_feedback_div = feedback_div; 1272 best_frac_feedback_div = frac_feedback_div; 1273 best_freq = current_freq; 1274 best_error = error; 1275 best_vco_diff = vco_diff; 1276 } 1277 } 1278 if (current_freq < freq) 1279 min_frac_feed_div = frac_feedback_div + 1; 1280 else 1281 max_frac_feed_div = frac_feedback_div; 1282 } 1283 if (current_freq < freq) 1284 min_feed_div = feedback_div + 1; 1285 else 1286 max_feed_div = feedback_div; 1287 } 1288 } 1289 } 1290 1291 *dot_clock_p = best_freq / 10000; 1292 *fb_div_p = best_feedback_div; 1293 *frac_fb_div_p = best_frac_feedback_div; 1294 *ref_div_p = best_ref_div; 1295 *post_div_p = best_post_div; 1296 DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n", 1297 (long long)freq, 1298 best_freq / 1000, best_feedback_div, best_frac_feedback_div, 1299 best_ref_div, best_post_div); 1300 1301 } 1302 1303 static const struct drm_framebuffer_funcs radeon_fb_funcs = { 1304 .destroy = drm_gem_fb_destroy, 1305 .create_handle = drm_gem_fb_create_handle, 1306 }; 1307 1308 int 1309 radeon_framebuffer_init(struct drm_device *dev, 1310 struct drm_framebuffer *fb, 1311 const struct drm_format_info *info, 1312 const struct drm_mode_fb_cmd2 *mode_cmd, 1313 struct drm_gem_object *obj) 1314 { 1315 int ret; 1316 fb->obj[0] = obj; 1317 drm_helper_mode_fill_fb_struct(dev, fb, info, mode_cmd); 1318 ret = drm_framebuffer_init(dev, fb, &radeon_fb_funcs); 1319 if (ret) { 1320 fb->obj[0] = NULL; 1321 return ret; 1322 } 1323 return 0; 1324 } 1325 1326 static struct drm_framebuffer * 1327 radeon_user_framebuffer_create(struct drm_device *dev, 1328 struct drm_file *file_priv, 1329 const struct drm_format_info *info, 1330 const struct drm_mode_fb_cmd2 *mode_cmd) 1331 { 1332 struct drm_gem_object *obj; 1333 struct drm_framebuffer *fb; 1334 int ret; 1335 1336 obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]); 1337 if (obj == NULL) { 1338 dev_err(dev->dev, "No GEM object associated to handle 0x%08X, " 1339 "can't create framebuffer\n", mode_cmd->handles[0]); 1340 return ERR_PTR(-ENOENT); 1341 } 1342 1343 /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */ 1344 if (obj->import_attach) { 1345 DRM_DEBUG_KMS("Cannot create framebuffer from imported dma_buf\n"); 1346 drm_gem_object_put(obj); 1347 return ERR_PTR(-EINVAL); 1348 } 1349 1350 fb = kzalloc_obj(*fb); 1351 if (fb == NULL) { 1352 drm_gem_object_put(obj); 1353 return ERR_PTR(-ENOMEM); 1354 } 1355 1356 ret = radeon_framebuffer_init(dev, fb, info, mode_cmd, obj); 1357 if (ret) { 1358 kfree(fb); 1359 drm_gem_object_put(obj); 1360 return ERR_PTR(ret); 1361 } 1362 1363 return fb; 1364 } 1365 1366 static const struct drm_mode_config_funcs radeon_mode_funcs = { 1367 .fb_create = radeon_user_framebuffer_create, 1368 }; 1369 1370 static const struct drm_prop_enum_list radeon_tmds_pll_enum_list[] = 1371 { { 0, "driver" }, 1372 { 1, "bios" }, 1373 }; 1374 1375 static const struct drm_prop_enum_list radeon_tv_std_enum_list[] = 1376 { { TV_STD_NTSC, "ntsc" }, 1377 { TV_STD_PAL, "pal" }, 1378 { TV_STD_PAL_M, "pal-m" }, 1379 { TV_STD_PAL_60, "pal-60" }, 1380 { TV_STD_NTSC_J, "ntsc-j" }, 1381 { TV_STD_SCART_PAL, "scart-pal" }, 1382 { TV_STD_PAL_CN, "pal-cn" }, 1383 { TV_STD_SECAM, "secam" }, 1384 }; 1385 1386 static const struct drm_prop_enum_list radeon_underscan_enum_list[] = 1387 { { UNDERSCAN_OFF, "off" }, 1388 { UNDERSCAN_ON, "on" }, 1389 { UNDERSCAN_AUTO, "auto" }, 1390 }; 1391 1392 static const struct drm_prop_enum_list radeon_audio_enum_list[] = 1393 { { RADEON_AUDIO_DISABLE, "off" }, 1394 { RADEON_AUDIO_ENABLE, "on" }, 1395 { RADEON_AUDIO_AUTO, "auto" }, 1396 }; 1397 1398 /* XXX support different dither options? spatial, temporal, both, etc. */ 1399 static const struct drm_prop_enum_list radeon_dither_enum_list[] = 1400 { { RADEON_FMT_DITHER_DISABLE, "off" }, 1401 { RADEON_FMT_DITHER_ENABLE, "on" }, 1402 }; 1403 1404 static const struct drm_prop_enum_list radeon_output_csc_enum_list[] = 1405 { { RADEON_OUTPUT_CSC_BYPASS, "bypass" }, 1406 { RADEON_OUTPUT_CSC_TVRGB, "tvrgb" }, 1407 { RADEON_OUTPUT_CSC_YCBCR601, "ycbcr601" }, 1408 { RADEON_OUTPUT_CSC_YCBCR709, "ycbcr709" }, 1409 }; 1410 1411 static int radeon_modeset_create_props(struct radeon_device *rdev) 1412 { 1413 int sz; 1414 1415 if (rdev->is_atom_bios) { 1416 rdev->mode_info.coherent_mode_property = 1417 drm_property_create_range(rdev_to_drm(rdev), 0, "coherent", 0, 1); 1418 if (!rdev->mode_info.coherent_mode_property) 1419 return -ENOMEM; 1420 } 1421 1422 if (!ASIC_IS_AVIVO(rdev)) { 1423 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list); 1424 rdev->mode_info.tmds_pll_property = 1425 drm_property_create_enum(rdev_to_drm(rdev), 0, 1426 "tmds_pll", 1427 radeon_tmds_pll_enum_list, sz); 1428 } 1429 1430 rdev->mode_info.load_detect_property = 1431 drm_property_create_range(rdev_to_drm(rdev), 0, "load detection", 0, 1); 1432 if (!rdev->mode_info.load_detect_property) 1433 return -ENOMEM; 1434 1435 drm_mode_create_scaling_mode_property(rdev_to_drm(rdev)); 1436 1437 sz = ARRAY_SIZE(radeon_tv_std_enum_list); 1438 rdev->mode_info.tv_std_property = 1439 drm_property_create_enum(rdev_to_drm(rdev), 0, 1440 "tv standard", 1441 radeon_tv_std_enum_list, sz); 1442 1443 sz = ARRAY_SIZE(radeon_underscan_enum_list); 1444 rdev->mode_info.underscan_property = 1445 drm_property_create_enum(rdev_to_drm(rdev), 0, 1446 "underscan", 1447 radeon_underscan_enum_list, sz); 1448 1449 rdev->mode_info.underscan_hborder_property = 1450 drm_property_create_range(rdev_to_drm(rdev), 0, 1451 "underscan hborder", 0, 128); 1452 if (!rdev->mode_info.underscan_hborder_property) 1453 return -ENOMEM; 1454 1455 rdev->mode_info.underscan_vborder_property = 1456 drm_property_create_range(rdev_to_drm(rdev), 0, 1457 "underscan vborder", 0, 128); 1458 if (!rdev->mode_info.underscan_vborder_property) 1459 return -ENOMEM; 1460 1461 sz = ARRAY_SIZE(radeon_audio_enum_list); 1462 rdev->mode_info.audio_property = 1463 drm_property_create_enum(rdev_to_drm(rdev), 0, 1464 "audio", 1465 radeon_audio_enum_list, sz); 1466 1467 sz = ARRAY_SIZE(radeon_dither_enum_list); 1468 rdev->mode_info.dither_property = 1469 drm_property_create_enum(rdev_to_drm(rdev), 0, 1470 "dither", 1471 radeon_dither_enum_list, sz); 1472 1473 sz = ARRAY_SIZE(radeon_output_csc_enum_list); 1474 rdev->mode_info.output_csc_property = 1475 drm_property_create_enum(rdev_to_drm(rdev), 0, 1476 "output_csc", 1477 radeon_output_csc_enum_list, sz); 1478 1479 return 0; 1480 } 1481 1482 void radeon_update_display_priority(struct radeon_device *rdev) 1483 { 1484 /* adjustment options for the display watermarks */ 1485 if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) { 1486 /* set display priority to high for r3xx, rv515 chips 1487 * this avoids flickering due to underflow to the 1488 * display controllers during heavy acceleration. 1489 * Don't force high on rs4xx igp chips as it seems to 1490 * affect the sound card. See kernel bug 15982. 1491 */ 1492 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) && 1493 !(rdev->flags & RADEON_IS_IGP)) 1494 rdev->disp_priority = 2; 1495 else 1496 rdev->disp_priority = 0; 1497 } else 1498 rdev->disp_priority = radeon_disp_priority; 1499 1500 } 1501 1502 /* 1503 * Allocate hdmi structs and determine register offsets 1504 */ 1505 static void radeon_afmt_init(struct radeon_device *rdev) 1506 { 1507 int i; 1508 1509 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) 1510 rdev->mode_info.afmt[i] = NULL; 1511 1512 if (ASIC_IS_NODCE(rdev)) { 1513 /* nothing to do */ 1514 } else if (ASIC_IS_DCE4(rdev)) { 1515 static uint32_t eg_offsets[] = { 1516 EVERGREEN_CRTC0_REGISTER_OFFSET, 1517 EVERGREEN_CRTC1_REGISTER_OFFSET, 1518 EVERGREEN_CRTC2_REGISTER_OFFSET, 1519 EVERGREEN_CRTC3_REGISTER_OFFSET, 1520 EVERGREEN_CRTC4_REGISTER_OFFSET, 1521 EVERGREEN_CRTC5_REGISTER_OFFSET, 1522 0x13830 - 0x7030, 1523 }; 1524 int num_afmt; 1525 1526 /* DCE8 has 7 audio blocks tied to DIG encoders */ 1527 /* DCE6 has 6 audio blocks tied to DIG encoders */ 1528 /* DCE4/5 has 6 audio blocks tied to DIG encoders */ 1529 /* DCE4.1 has 2 audio blocks tied to DIG encoders */ 1530 if (ASIC_IS_DCE8(rdev)) 1531 num_afmt = 7; 1532 else if (ASIC_IS_DCE6(rdev)) 1533 num_afmt = 6; 1534 else if (ASIC_IS_DCE5(rdev)) 1535 num_afmt = 6; 1536 else if (ASIC_IS_DCE41(rdev)) 1537 num_afmt = 2; 1538 else /* DCE4 */ 1539 num_afmt = 6; 1540 1541 BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets)); 1542 for (i = 0; i < num_afmt; i++) { 1543 rdev->mode_info.afmt[i] = kzalloc_obj(struct radeon_afmt); 1544 if (rdev->mode_info.afmt[i]) { 1545 rdev->mode_info.afmt[i]->offset = eg_offsets[i]; 1546 rdev->mode_info.afmt[i]->id = i; 1547 } 1548 } 1549 } else if (ASIC_IS_DCE3(rdev)) { 1550 /* DCE3.x has 2 audio blocks tied to DIG encoders */ 1551 rdev->mode_info.afmt[0] = kzalloc_obj(struct radeon_afmt); 1552 if (rdev->mode_info.afmt[0]) { 1553 rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0; 1554 rdev->mode_info.afmt[0]->id = 0; 1555 } 1556 rdev->mode_info.afmt[1] = kzalloc_obj(struct radeon_afmt); 1557 if (rdev->mode_info.afmt[1]) { 1558 rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1; 1559 rdev->mode_info.afmt[1]->id = 1; 1560 } 1561 } else if (ASIC_IS_DCE2(rdev)) { 1562 /* DCE2 has at least 1 routable audio block */ 1563 rdev->mode_info.afmt[0] = kzalloc_obj(struct radeon_afmt); 1564 if (rdev->mode_info.afmt[0]) { 1565 rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0; 1566 rdev->mode_info.afmt[0]->id = 0; 1567 } 1568 /* r6xx has 2 routable audio blocks */ 1569 if (rdev->family >= CHIP_R600) { 1570 rdev->mode_info.afmt[1] = kzalloc_obj(struct radeon_afmt); 1571 if (rdev->mode_info.afmt[1]) { 1572 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1; 1573 rdev->mode_info.afmt[1]->id = 1; 1574 } 1575 } 1576 } 1577 } 1578 1579 static void radeon_afmt_fini(struct radeon_device *rdev) 1580 { 1581 int i; 1582 1583 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) { 1584 kfree(rdev->mode_info.afmt[i]); 1585 rdev->mode_info.afmt[i] = NULL; 1586 } 1587 } 1588 1589 int radeon_modeset_init(struct radeon_device *rdev) 1590 { 1591 int i; 1592 int ret; 1593 1594 drm_mode_config_init(rdev_to_drm(rdev)); 1595 rdev->mode_info.mode_config_initialized = true; 1596 1597 rdev_to_drm(rdev)->mode_config.funcs = &radeon_mode_funcs; 1598 1599 if (radeon_use_pflipirq == 2 && rdev->family >= CHIP_R600) 1600 rdev_to_drm(rdev)->mode_config.async_page_flip = true; 1601 1602 if (ASIC_IS_DCE5(rdev)) { 1603 rdev_to_drm(rdev)->mode_config.max_width = 16384; 1604 rdev_to_drm(rdev)->mode_config.max_height = 16384; 1605 } else if (ASIC_IS_AVIVO(rdev)) { 1606 rdev_to_drm(rdev)->mode_config.max_width = 8192; 1607 rdev_to_drm(rdev)->mode_config.max_height = 8192; 1608 } else { 1609 rdev_to_drm(rdev)->mode_config.max_width = 4096; 1610 rdev_to_drm(rdev)->mode_config.max_height = 4096; 1611 } 1612 1613 rdev_to_drm(rdev)->mode_config.preferred_depth = 24; 1614 rdev_to_drm(rdev)->mode_config.prefer_shadow = 1; 1615 1616 rdev_to_drm(rdev)->mode_config.fb_modifiers_not_supported = true; 1617 1618 ret = radeon_modeset_create_props(rdev); 1619 if (ret) { 1620 return ret; 1621 } 1622 1623 /* init i2c buses */ 1624 radeon_i2c_init(rdev); 1625 1626 /* check combios for a valid hardcoded EDID - Sun servers */ 1627 if (!rdev->is_atom_bios) { 1628 /* check for hardcoded EDID in BIOS */ 1629 radeon_combios_check_hardcoded_edid(rdev); 1630 } 1631 1632 /* allocate crtcs */ 1633 for (i = 0; i < rdev->num_crtc; i++) { 1634 radeon_crtc_init(rdev_to_drm(rdev), i); 1635 } 1636 1637 /* okay we should have all the bios connectors */ 1638 ret = radeon_setup_enc_conn(rdev_to_drm(rdev)); 1639 if (!ret) { 1640 return ret; 1641 } 1642 1643 /* init dig PHYs, disp eng pll */ 1644 if (rdev->is_atom_bios) { 1645 radeon_atom_encoder_init(rdev); 1646 radeon_atom_disp_eng_pll_init(rdev); 1647 } 1648 1649 /* initialize hpd */ 1650 radeon_hpd_init(rdev); 1651 1652 /* setup afmt */ 1653 radeon_afmt_init(rdev); 1654 1655 drm_kms_helper_poll_init(rdev_to_drm(rdev)); 1656 1657 /* do pm late init */ 1658 ret = radeon_pm_late_init(rdev); 1659 1660 return 0; 1661 } 1662 1663 void radeon_modeset_fini(struct radeon_device *rdev) 1664 { 1665 if (rdev->mode_info.mode_config_initialized) { 1666 drm_kms_helper_poll_fini(rdev_to_drm(rdev)); 1667 radeon_hpd_fini(rdev); 1668 drm_helper_force_disable_all(rdev_to_drm(rdev)); 1669 radeon_afmt_fini(rdev); 1670 drm_mode_config_cleanup(rdev_to_drm(rdev)); 1671 rdev->mode_info.mode_config_initialized = false; 1672 } 1673 1674 drm_edid_free(rdev->mode_info.bios_hardcoded_edid); 1675 1676 /* free i2c buses */ 1677 radeon_i2c_fini(rdev); 1678 } 1679 1680 static bool is_hdtv_mode(const struct drm_display_mode *mode) 1681 { 1682 /* try and guess if this is a tv or a monitor */ 1683 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */ 1684 (mode->vdisplay == 576) || /* 576p */ 1685 (mode->vdisplay == 720) || /* 720p */ 1686 (mode->vdisplay == 1080)) /* 1080p */ 1687 return true; 1688 else 1689 return false; 1690 } 1691 1692 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 1693 const struct drm_display_mode *mode, 1694 struct drm_display_mode *adjusted_mode) 1695 { 1696 struct drm_device *dev = crtc->dev; 1697 struct radeon_device *rdev = dev->dev_private; 1698 struct drm_encoder *encoder; 1699 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1700 struct radeon_encoder *radeon_encoder; 1701 struct drm_connector *connector; 1702 bool first = true; 1703 u32 src_v = 1, dst_v = 1; 1704 u32 src_h = 1, dst_h = 1; 1705 1706 radeon_crtc->h_border = 0; 1707 radeon_crtc->v_border = 0; 1708 1709 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1710 if (encoder->crtc != crtc) 1711 continue; 1712 radeon_encoder = to_radeon_encoder(encoder); 1713 connector = radeon_get_connector_for_encoder(encoder); 1714 1715 if (first) { 1716 /* set scaling */ 1717 if (radeon_encoder->rmx_type == RMX_OFF) 1718 radeon_crtc->rmx_type = RMX_OFF; 1719 else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay || 1720 mode->vdisplay < radeon_encoder->native_mode.vdisplay) 1721 radeon_crtc->rmx_type = radeon_encoder->rmx_type; 1722 else 1723 radeon_crtc->rmx_type = RMX_OFF; 1724 /* copy native mode */ 1725 memcpy(&radeon_crtc->native_mode, 1726 &radeon_encoder->native_mode, 1727 sizeof(struct drm_display_mode)); 1728 src_v = crtc->mode.vdisplay; 1729 dst_v = radeon_crtc->native_mode.vdisplay; 1730 src_h = crtc->mode.hdisplay; 1731 dst_h = radeon_crtc->native_mode.hdisplay; 1732 1733 /* fix up for overscan on hdmi */ 1734 if (ASIC_IS_AVIVO(rdev) && 1735 (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) && 1736 ((radeon_encoder->underscan_type == UNDERSCAN_ON) || 1737 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) && 1738 connector->display_info.is_hdmi && 1739 is_hdtv_mode(mode)))) { 1740 if (radeon_encoder->underscan_hborder != 0) 1741 radeon_crtc->h_border = radeon_encoder->underscan_hborder; 1742 else 1743 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16; 1744 if (radeon_encoder->underscan_vborder != 0) 1745 radeon_crtc->v_border = radeon_encoder->underscan_vborder; 1746 else 1747 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16; 1748 radeon_crtc->rmx_type = RMX_FULL; 1749 src_v = crtc->mode.vdisplay; 1750 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2); 1751 src_h = crtc->mode.hdisplay; 1752 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2); 1753 } 1754 first = false; 1755 } else { 1756 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) { 1757 /* WARNING: Right now this can't happen but 1758 * in the future we need to check that scaling 1759 * are consistent across different encoder 1760 * (ie all encoder can work with the same 1761 * scaling). 1762 */ 1763 drm_err(dev, "Scaling not consistent across encoder.\n"); 1764 return false; 1765 } 1766 } 1767 } 1768 if (radeon_crtc->rmx_type != RMX_OFF) { 1769 fixed20_12 a, b; 1770 a.full = dfixed_const(src_v); 1771 b.full = dfixed_const(dst_v); 1772 radeon_crtc->vsc.full = dfixed_div(a, b); 1773 a.full = dfixed_const(src_h); 1774 b.full = dfixed_const(dst_h); 1775 radeon_crtc->hsc.full = dfixed_div(a, b); 1776 } else { 1777 radeon_crtc->vsc.full = dfixed_const(1); 1778 radeon_crtc->hsc.full = dfixed_const(1); 1779 } 1780 return true; 1781 } 1782 1783 /* 1784 * Retrieve current video scanout position of crtc on a given gpu, and 1785 * an optional accurate timestamp of when query happened. 1786 * 1787 * \param dev Device to query. 1788 * \param crtc Crtc to query. 1789 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0). 1790 * For driver internal use only also supports these flags: 1791 * 1792 * USE_REAL_VBLANKSTART to use the real start of vblank instead 1793 * of a fudged earlier start of vblank. 1794 * 1795 * GET_DISTANCE_TO_VBLANKSTART to return distance to the 1796 * fudged earlier start of vblank in *vpos and the distance 1797 * to true start of vblank in *hpos. 1798 * 1799 * \param *vpos Location where vertical scanout position should be stored. 1800 * \param *hpos Location where horizontal scanout position should go. 1801 * \param *stime Target location for timestamp taken immediately before 1802 * scanout position query. Can be NULL to skip timestamp. 1803 * \param *etime Target location for timestamp taken immediately after 1804 * scanout position query. Can be NULL to skip timestamp. 1805 * 1806 * Returns vpos as a positive number while in active scanout area. 1807 * Returns vpos as a negative number inside vblank, counting the number 1808 * of scanlines to go until end of vblank, e.g., -1 means "one scanline 1809 * until start of active scanout / end of vblank." 1810 * 1811 * \return Flags, or'ed together as follows: 1812 * 1813 * DRM_SCANOUTPOS_VALID = Query successful. 1814 * DRM_SCANOUTPOS_INVBL = Inside vblank. 1815 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of 1816 * this flag means that returned position may be offset by a constant but 1817 * unknown small number of scanlines wrt. real scanout position. 1818 * 1819 */ 1820 int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, 1821 unsigned int flags, int *vpos, int *hpos, 1822 ktime_t *stime, ktime_t *etime, 1823 const struct drm_display_mode *mode) 1824 { 1825 u32 stat_crtc = 0, vbl = 0, position = 0; 1826 int vbl_start, vbl_end, vtotal, ret = 0; 1827 bool in_vbl = true; 1828 1829 struct radeon_device *rdev = dev->dev_private; 1830 1831 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ 1832 1833 /* Get optional system timestamp before query. */ 1834 if (stime) 1835 *stime = ktime_get(); 1836 1837 if (ASIC_IS_DCE4(rdev)) { 1838 if (pipe == 0) { 1839 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1840 EVERGREEN_CRTC0_REGISTER_OFFSET); 1841 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1842 EVERGREEN_CRTC0_REGISTER_OFFSET); 1843 ret |= DRM_SCANOUTPOS_VALID; 1844 } 1845 if (pipe == 1) { 1846 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1847 EVERGREEN_CRTC1_REGISTER_OFFSET); 1848 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1849 EVERGREEN_CRTC1_REGISTER_OFFSET); 1850 ret |= DRM_SCANOUTPOS_VALID; 1851 } 1852 if (pipe == 2) { 1853 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1854 EVERGREEN_CRTC2_REGISTER_OFFSET); 1855 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1856 EVERGREEN_CRTC2_REGISTER_OFFSET); 1857 ret |= DRM_SCANOUTPOS_VALID; 1858 } 1859 if (pipe == 3) { 1860 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1861 EVERGREEN_CRTC3_REGISTER_OFFSET); 1862 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1863 EVERGREEN_CRTC3_REGISTER_OFFSET); 1864 ret |= DRM_SCANOUTPOS_VALID; 1865 } 1866 if (pipe == 4) { 1867 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1868 EVERGREEN_CRTC4_REGISTER_OFFSET); 1869 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1870 EVERGREEN_CRTC4_REGISTER_OFFSET); 1871 ret |= DRM_SCANOUTPOS_VALID; 1872 } 1873 if (pipe == 5) { 1874 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1875 EVERGREEN_CRTC5_REGISTER_OFFSET); 1876 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1877 EVERGREEN_CRTC5_REGISTER_OFFSET); 1878 ret |= DRM_SCANOUTPOS_VALID; 1879 } 1880 } else if (ASIC_IS_AVIVO(rdev)) { 1881 if (pipe == 0) { 1882 vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END); 1883 position = RREG32(AVIVO_D1CRTC_STATUS_POSITION); 1884 ret |= DRM_SCANOUTPOS_VALID; 1885 } 1886 if (pipe == 1) { 1887 vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END); 1888 position = RREG32(AVIVO_D2CRTC_STATUS_POSITION); 1889 ret |= DRM_SCANOUTPOS_VALID; 1890 } 1891 } else { 1892 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */ 1893 if (pipe == 0) { 1894 /* Assume vbl_end == 0, get vbl_start from 1895 * upper 16 bits. 1896 */ 1897 vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) & 1898 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT; 1899 /* Only retrieve vpos from upper 16 bits, set hpos == 0. */ 1900 position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 1901 stat_crtc = RREG32(RADEON_CRTC_STATUS); 1902 if (!(stat_crtc & 1)) 1903 in_vbl = false; 1904 1905 ret |= DRM_SCANOUTPOS_VALID; 1906 } 1907 if (pipe == 1) { 1908 vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) & 1909 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT; 1910 position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 1911 stat_crtc = RREG32(RADEON_CRTC2_STATUS); 1912 if (!(stat_crtc & 1)) 1913 in_vbl = false; 1914 1915 ret |= DRM_SCANOUTPOS_VALID; 1916 } 1917 } 1918 1919 /* Get optional system timestamp after query. */ 1920 if (etime) 1921 *etime = ktime_get(); 1922 1923 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ 1924 1925 /* Decode into vertical and horizontal scanout position. */ 1926 *vpos = position & 0x1fff; 1927 *hpos = (position >> 16) & 0x1fff; 1928 1929 /* Valid vblank area boundaries from gpu retrieved? */ 1930 if (vbl > 0) { 1931 /* Yes: Decode. */ 1932 ret |= DRM_SCANOUTPOS_ACCURATE; 1933 vbl_start = vbl & 0x1fff; 1934 vbl_end = (vbl >> 16) & 0x1fff; 1935 } 1936 else { 1937 /* No: Fake something reasonable which gives at least ok results. */ 1938 vbl_start = mode->crtc_vdisplay; 1939 vbl_end = 0; 1940 } 1941 1942 /* Called from driver internal vblank counter query code? */ 1943 if (flags & GET_DISTANCE_TO_VBLANKSTART) { 1944 /* Caller wants distance from real vbl_start in *hpos */ 1945 *hpos = *vpos - vbl_start; 1946 } 1947 1948 /* Fudge vblank to start a few scanlines earlier to handle the 1949 * problem that vblank irqs fire a few scanlines before start 1950 * of vblank. Some driver internal callers need the true vblank 1951 * start to be used and signal this via the USE_REAL_VBLANKSTART flag. 1952 * 1953 * The cause of the "early" vblank irq is that the irq is triggered 1954 * by the line buffer logic when the line buffer read position enters 1955 * the vblank, whereas our crtc scanout position naturally lags the 1956 * line buffer read position. 1957 */ 1958 if (!(flags & USE_REAL_VBLANKSTART)) 1959 vbl_start -= rdev->mode_info.crtcs[pipe]->lb_vblank_lead_lines; 1960 1961 /* Test scanout position against vblank region. */ 1962 if ((*vpos < vbl_start) && (*vpos >= vbl_end)) 1963 in_vbl = false; 1964 1965 /* In vblank? */ 1966 if (in_vbl) 1967 ret |= DRM_SCANOUTPOS_IN_VBLANK; 1968 1969 /* Called from driver internal vblank counter query code? */ 1970 if (flags & GET_DISTANCE_TO_VBLANKSTART) { 1971 /* Caller wants distance from fudged earlier vbl_start */ 1972 *vpos -= vbl_start; 1973 return ret; 1974 } 1975 1976 /* Check if inside vblank area and apply corrective offsets: 1977 * vpos will then be >=0 in video scanout area, but negative 1978 * within vblank area, counting down the number of lines until 1979 * start of scanout. 1980 */ 1981 1982 /* Inside "upper part" of vblank area? Apply corrective offset if so: */ 1983 if (in_vbl && (*vpos >= vbl_start)) { 1984 vtotal = mode->crtc_vtotal; 1985 *vpos = *vpos - vtotal; 1986 } 1987 1988 /* Correct for shifted end of vbl at vbl_end. */ 1989 *vpos = *vpos - vbl_end; 1990 1991 return ret; 1992 } 1993 1994 bool 1995 radeon_get_crtc_scanout_position(struct drm_crtc *crtc, 1996 bool in_vblank_irq, int *vpos, int *hpos, 1997 ktime_t *stime, ktime_t *etime, 1998 const struct drm_display_mode *mode) 1999 { 2000 struct drm_device *dev = crtc->dev; 2001 unsigned int pipe = crtc->index; 2002 2003 return radeon_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos, 2004 stime, etime, mode); 2005 } 2006