1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include "drmP.h" 27 #include "radeon_drm.h" 28 #include "radeon.h" 29 30 #include "atom.h" 31 #include <asm/div64.h> 32 33 #include "drm_crtc_helper.h" 34 #include "drm_edid.h" 35 36 static int radeon_ddc_dump(struct drm_connector *connector); 37 38 static void avivo_crtc_load_lut(struct drm_crtc *crtc) 39 { 40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 41 struct drm_device *dev = crtc->dev; 42 struct radeon_device *rdev = dev->dev_private; 43 int i; 44 45 DRM_DEBUG("%d\n", radeon_crtc->crtc_id); 46 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); 47 48 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 49 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 50 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 51 52 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 53 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 54 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 55 56 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id); 57 WREG32(AVIVO_DC_LUT_RW_MODE, 0); 58 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f); 59 60 WREG8(AVIVO_DC_LUT_RW_INDEX, 0); 61 for (i = 0; i < 256; i++) { 62 WREG32(AVIVO_DC_LUT_30_COLOR, 63 (radeon_crtc->lut_r[i] << 20) | 64 (radeon_crtc->lut_g[i] << 10) | 65 (radeon_crtc->lut_b[i] << 0)); 66 } 67 68 WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id); 69 } 70 71 static void legacy_crtc_load_lut(struct drm_crtc *crtc) 72 { 73 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 74 struct drm_device *dev = crtc->dev; 75 struct radeon_device *rdev = dev->dev_private; 76 int i; 77 uint32_t dac2_cntl; 78 79 dac2_cntl = RREG32(RADEON_DAC_CNTL2); 80 if (radeon_crtc->crtc_id == 0) 81 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL; 82 else 83 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL; 84 WREG32(RADEON_DAC_CNTL2, dac2_cntl); 85 86 WREG8(RADEON_PALETTE_INDEX, 0); 87 for (i = 0; i < 256; i++) { 88 WREG32(RADEON_PALETTE_30_DATA, 89 (radeon_crtc->lut_r[i] << 20) | 90 (radeon_crtc->lut_g[i] << 10) | 91 (radeon_crtc->lut_b[i] << 0)); 92 } 93 } 94 95 void radeon_crtc_load_lut(struct drm_crtc *crtc) 96 { 97 struct drm_device *dev = crtc->dev; 98 struct radeon_device *rdev = dev->dev_private; 99 100 if (!crtc->enabled) 101 return; 102 103 if (ASIC_IS_AVIVO(rdev)) 104 avivo_crtc_load_lut(crtc); 105 else 106 legacy_crtc_load_lut(crtc); 107 } 108 109 /** Sets the color ramps on behalf of RandR */ 110 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, 111 u16 blue, int regno) 112 { 113 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 114 115 if (regno == 0) 116 DRM_DEBUG("gamma set %d\n", radeon_crtc->crtc_id); 117 radeon_crtc->lut_r[regno] = red >> 6; 118 radeon_crtc->lut_g[regno] = green >> 6; 119 radeon_crtc->lut_b[regno] = blue >> 6; 120 } 121 122 static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 123 u16 *blue, uint32_t size) 124 { 125 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 126 int i, j; 127 128 if (size != 256) { 129 return; 130 } 131 if (crtc->fb == NULL) { 132 return; 133 } 134 135 if (crtc->fb->depth == 16) { 136 for (i = 0; i < 64; i++) { 137 if (i <= 31) { 138 for (j = 0; j < 8; j++) { 139 radeon_crtc->lut_r[i * 8 + j] = red[i] >> 6; 140 radeon_crtc->lut_b[i * 8 + j] = blue[i] >> 6; 141 } 142 } 143 for (j = 0; j < 4; j++) 144 radeon_crtc->lut_g[i * 4 + j] = green[i] >> 6; 145 } 146 } else { 147 for (i = 0; i < 256; i++) { 148 radeon_crtc->lut_r[i] = red[i] >> 6; 149 radeon_crtc->lut_g[i] = green[i] >> 6; 150 radeon_crtc->lut_b[i] = blue[i] >> 6; 151 } 152 } 153 154 radeon_crtc_load_lut(crtc); 155 } 156 157 static void radeon_crtc_destroy(struct drm_crtc *crtc) 158 { 159 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 160 161 if (radeon_crtc->mode_set.mode) { 162 drm_mode_destroy(crtc->dev, radeon_crtc->mode_set.mode); 163 } 164 drm_crtc_cleanup(crtc); 165 kfree(radeon_crtc); 166 } 167 168 static const struct drm_crtc_funcs radeon_crtc_funcs = { 169 .cursor_set = radeon_crtc_cursor_set, 170 .cursor_move = radeon_crtc_cursor_move, 171 .gamma_set = radeon_crtc_gamma_set, 172 .set_config = drm_crtc_helper_set_config, 173 .destroy = radeon_crtc_destroy, 174 }; 175 176 static void radeon_crtc_init(struct drm_device *dev, int index) 177 { 178 struct radeon_device *rdev = dev->dev_private; 179 struct radeon_crtc *radeon_crtc; 180 int i; 181 182 radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); 183 if (radeon_crtc == NULL) 184 return; 185 186 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs); 187 188 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256); 189 radeon_crtc->crtc_id = index; 190 rdev->mode_info.crtcs[index] = radeon_crtc; 191 192 radeon_crtc->mode_set.crtc = &radeon_crtc->base; 193 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1); 194 radeon_crtc->mode_set.num_connectors = 0; 195 196 for (i = 0; i < 256; i++) { 197 radeon_crtc->lut_r[i] = i << 2; 198 radeon_crtc->lut_g[i] = i << 2; 199 radeon_crtc->lut_b[i] = i << 2; 200 } 201 202 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)) 203 radeon_atombios_init_crtc(dev, radeon_crtc); 204 else 205 radeon_legacy_init_crtc(dev, radeon_crtc); 206 } 207 208 static const char *encoder_names[34] = { 209 "NONE", 210 "INTERNAL_LVDS", 211 "INTERNAL_TMDS1", 212 "INTERNAL_TMDS2", 213 "INTERNAL_DAC1", 214 "INTERNAL_DAC2", 215 "INTERNAL_SDVOA", 216 "INTERNAL_SDVOB", 217 "SI170B", 218 "CH7303", 219 "CH7301", 220 "INTERNAL_DVO1", 221 "EXTERNAL_SDVOA", 222 "EXTERNAL_SDVOB", 223 "TITFP513", 224 "INTERNAL_LVTM1", 225 "VT1623", 226 "HDMI_SI1930", 227 "HDMI_INTERNAL", 228 "INTERNAL_KLDSCP_TMDS1", 229 "INTERNAL_KLDSCP_DVO1", 230 "INTERNAL_KLDSCP_DAC1", 231 "INTERNAL_KLDSCP_DAC2", 232 "SI178", 233 "MVPU_FPGA", 234 "INTERNAL_DDI", 235 "VT1625", 236 "HDMI_SI1932", 237 "DP_AN9801", 238 "DP_DP501", 239 "INTERNAL_UNIPHY", 240 "INTERNAL_KLDSCP_LVTMA", 241 "INTERNAL_UNIPHY1", 242 "INTERNAL_UNIPHY2", 243 }; 244 245 static const char *connector_names[13] = { 246 "Unknown", 247 "VGA", 248 "DVI-I", 249 "DVI-D", 250 "DVI-A", 251 "Composite", 252 "S-video", 253 "LVDS", 254 "Component", 255 "DIN", 256 "DisplayPort", 257 "HDMI-A", 258 "HDMI-B", 259 }; 260 261 static void radeon_print_display_setup(struct drm_device *dev) 262 { 263 struct drm_connector *connector; 264 struct radeon_connector *radeon_connector; 265 struct drm_encoder *encoder; 266 struct radeon_encoder *radeon_encoder; 267 uint32_t devices; 268 int i = 0; 269 270 DRM_INFO("Radeon Display Connectors\n"); 271 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 272 radeon_connector = to_radeon_connector(connector); 273 DRM_INFO("Connector %d:\n", i); 274 DRM_INFO(" %s\n", connector_names[connector->connector_type]); 275 if (radeon_connector->ddc_bus) 276 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", 277 radeon_connector->ddc_bus->rec.mask_clk_reg, 278 radeon_connector->ddc_bus->rec.mask_data_reg, 279 radeon_connector->ddc_bus->rec.a_clk_reg, 280 radeon_connector->ddc_bus->rec.a_data_reg, 281 radeon_connector->ddc_bus->rec.put_clk_reg, 282 radeon_connector->ddc_bus->rec.put_data_reg, 283 radeon_connector->ddc_bus->rec.get_clk_reg, 284 radeon_connector->ddc_bus->rec.get_data_reg); 285 DRM_INFO(" Encoders:\n"); 286 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 287 radeon_encoder = to_radeon_encoder(encoder); 288 devices = radeon_encoder->devices & radeon_connector->devices; 289 if (devices) { 290 if (devices & ATOM_DEVICE_CRT1_SUPPORT) 291 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]); 292 if (devices & ATOM_DEVICE_CRT2_SUPPORT) 293 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]); 294 if (devices & ATOM_DEVICE_LCD1_SUPPORT) 295 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]); 296 if (devices & ATOM_DEVICE_DFP1_SUPPORT) 297 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]); 298 if (devices & ATOM_DEVICE_DFP2_SUPPORT) 299 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]); 300 if (devices & ATOM_DEVICE_DFP3_SUPPORT) 301 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]); 302 if (devices & ATOM_DEVICE_DFP4_SUPPORT) 303 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]); 304 if (devices & ATOM_DEVICE_DFP5_SUPPORT) 305 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]); 306 if (devices & ATOM_DEVICE_TV1_SUPPORT) 307 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]); 308 if (devices & ATOM_DEVICE_CV_SUPPORT) 309 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]); 310 } 311 } 312 i++; 313 } 314 } 315 316 bool radeon_setup_enc_conn(struct drm_device *dev) 317 { 318 struct radeon_device *rdev = dev->dev_private; 319 struct drm_connector *drm_connector; 320 bool ret = false; 321 322 if (rdev->bios) { 323 if (rdev->is_atom_bios) { 324 if (rdev->family >= CHIP_R600) 325 ret = radeon_get_atom_connector_info_from_object_table(dev); 326 else 327 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev); 328 } else 329 ret = radeon_get_legacy_connector_info_from_bios(dev); 330 } else { 331 if (!ASIC_IS_AVIVO(rdev)) 332 ret = radeon_get_legacy_connector_info_from_table(dev); 333 } 334 if (ret) { 335 radeon_print_display_setup(dev); 336 list_for_each_entry(drm_connector, &dev->mode_config.connector_list, head) 337 radeon_ddc_dump(drm_connector); 338 } 339 340 return ret; 341 } 342 343 int radeon_ddc_get_modes(struct radeon_connector *radeon_connector) 344 { 345 struct edid *edid; 346 int ret = 0; 347 348 if (!radeon_connector->ddc_bus) 349 return -1; 350 radeon_i2c_do_lock(radeon_connector, 1); 351 edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter); 352 radeon_i2c_do_lock(radeon_connector, 0); 353 if (edid) { 354 /* update digital bits here */ 355 if (edid->input & DRM_EDID_INPUT_DIGITAL) 356 radeon_connector->use_digital = 1; 357 else 358 radeon_connector->use_digital = 0; 359 drm_mode_connector_update_edid_property(&radeon_connector->base, edid); 360 ret = drm_add_edid_modes(&radeon_connector->base, edid); 361 kfree(edid); 362 return ret; 363 } 364 drm_mode_connector_update_edid_property(&radeon_connector->base, NULL); 365 return -1; 366 } 367 368 static int radeon_ddc_dump(struct drm_connector *connector) 369 { 370 struct edid *edid; 371 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 372 int ret = 0; 373 374 if (!radeon_connector->ddc_bus) 375 return -1; 376 radeon_i2c_do_lock(radeon_connector, 1); 377 edid = drm_get_edid(connector, &radeon_connector->ddc_bus->adapter); 378 radeon_i2c_do_lock(radeon_connector, 0); 379 if (edid) { 380 kfree(edid); 381 } 382 return ret; 383 } 384 385 static inline uint32_t radeon_div(uint64_t n, uint32_t d) 386 { 387 uint64_t mod; 388 389 n += d / 2; 390 391 mod = do_div(n, d); 392 return n; 393 } 394 395 void radeon_compute_pll(struct radeon_pll *pll, 396 uint64_t freq, 397 uint32_t *dot_clock_p, 398 uint32_t *fb_div_p, 399 uint32_t *frac_fb_div_p, 400 uint32_t *ref_div_p, 401 uint32_t *post_div_p, 402 int flags) 403 { 404 uint32_t min_ref_div = pll->min_ref_div; 405 uint32_t max_ref_div = pll->max_ref_div; 406 uint32_t min_fractional_feed_div = 0; 407 uint32_t max_fractional_feed_div = 0; 408 uint32_t best_vco = pll->best_vco; 409 uint32_t best_post_div = 1; 410 uint32_t best_ref_div = 1; 411 uint32_t best_feedback_div = 1; 412 uint32_t best_frac_feedback_div = 0; 413 uint32_t best_freq = -1; 414 uint32_t best_error = 0xffffffff; 415 uint32_t best_vco_diff = 1; 416 uint32_t post_div; 417 418 DRM_DEBUG("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div); 419 freq = freq * 1000; 420 421 if (flags & RADEON_PLL_USE_REF_DIV) 422 min_ref_div = max_ref_div = pll->reference_div; 423 else { 424 while (min_ref_div < max_ref_div-1) { 425 uint32_t mid = (min_ref_div + max_ref_div) / 2; 426 uint32_t pll_in = pll->reference_freq / mid; 427 if (pll_in < pll->pll_in_min) 428 max_ref_div = mid; 429 else if (pll_in > pll->pll_in_max) 430 min_ref_div = mid; 431 else 432 break; 433 } 434 } 435 436 if (flags & RADEON_PLL_USE_FRAC_FB_DIV) { 437 min_fractional_feed_div = pll->min_frac_feedback_div; 438 max_fractional_feed_div = pll->max_frac_feedback_div; 439 } 440 441 for (post_div = pll->min_post_div; post_div <= pll->max_post_div; ++post_div) { 442 uint32_t ref_div; 443 444 if ((flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) 445 continue; 446 447 /* legacy radeons only have a few post_divs */ 448 if (flags & RADEON_PLL_LEGACY) { 449 if ((post_div == 5) || 450 (post_div == 7) || 451 (post_div == 9) || 452 (post_div == 10) || 453 (post_div == 11) || 454 (post_div == 13) || 455 (post_div == 14) || 456 (post_div == 15)) 457 continue; 458 } 459 460 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) { 461 uint32_t feedback_div, current_freq = 0, error, vco_diff; 462 uint32_t pll_in = pll->reference_freq / ref_div; 463 uint32_t min_feed_div = pll->min_feedback_div; 464 uint32_t max_feed_div = pll->max_feedback_div + 1; 465 466 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max) 467 continue; 468 469 while (min_feed_div < max_feed_div) { 470 uint32_t vco; 471 uint32_t min_frac_feed_div = min_fractional_feed_div; 472 uint32_t max_frac_feed_div = max_fractional_feed_div + 1; 473 uint32_t frac_feedback_div; 474 uint64_t tmp; 475 476 feedback_div = (min_feed_div + max_feed_div) / 2; 477 478 tmp = (uint64_t)pll->reference_freq * feedback_div; 479 vco = radeon_div(tmp, ref_div); 480 481 if (vco < pll->pll_out_min) { 482 min_feed_div = feedback_div + 1; 483 continue; 484 } else if (vco > pll->pll_out_max) { 485 max_feed_div = feedback_div; 486 continue; 487 } 488 489 while (min_frac_feed_div < max_frac_feed_div) { 490 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2; 491 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div; 492 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div; 493 current_freq = radeon_div(tmp, ref_div * post_div); 494 495 if (flags & RADEON_PLL_PREFER_CLOSEST_LOWER) { 496 error = freq - current_freq; 497 error = error < 0 ? 0xffffffff : error; 498 } else 499 error = abs(current_freq - freq); 500 vco_diff = abs(vco - best_vco); 501 502 if ((best_vco == 0 && error < best_error) || 503 (best_vco != 0 && 504 (error < best_error - 100 || 505 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) { 506 best_post_div = post_div; 507 best_ref_div = ref_div; 508 best_feedback_div = feedback_div; 509 best_frac_feedback_div = frac_feedback_div; 510 best_freq = current_freq; 511 best_error = error; 512 best_vco_diff = vco_diff; 513 } else if (current_freq == freq) { 514 if (best_freq == -1) { 515 best_post_div = post_div; 516 best_ref_div = ref_div; 517 best_feedback_div = feedback_div; 518 best_frac_feedback_div = frac_feedback_div; 519 best_freq = current_freq; 520 best_error = error; 521 best_vco_diff = vco_diff; 522 } else if (((flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) || 523 ((flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) || 524 ((flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) || 525 ((flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) || 526 ((flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) || 527 ((flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) { 528 best_post_div = post_div; 529 best_ref_div = ref_div; 530 best_feedback_div = feedback_div; 531 best_frac_feedback_div = frac_feedback_div; 532 best_freq = current_freq; 533 best_error = error; 534 best_vco_diff = vco_diff; 535 } 536 } 537 if (current_freq < freq) 538 min_frac_feed_div = frac_feedback_div + 1; 539 else 540 max_frac_feed_div = frac_feedback_div; 541 } 542 if (current_freq < freq) 543 min_feed_div = feedback_div + 1; 544 else 545 max_feed_div = feedback_div; 546 } 547 } 548 } 549 550 *dot_clock_p = best_freq / 10000; 551 *fb_div_p = best_feedback_div; 552 *frac_fb_div_p = best_frac_feedback_div; 553 *ref_div_p = best_ref_div; 554 *post_div_p = best_post_div; 555 } 556 557 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb) 558 { 559 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); 560 struct drm_device *dev = fb->dev; 561 562 if (fb->fbdev) 563 radeonfb_remove(dev, fb); 564 565 if (radeon_fb->obj) { 566 radeon_gem_object_unpin(radeon_fb->obj); 567 mutex_lock(&dev->struct_mutex); 568 drm_gem_object_unreference(radeon_fb->obj); 569 mutex_unlock(&dev->struct_mutex); 570 } 571 drm_framebuffer_cleanup(fb); 572 kfree(radeon_fb); 573 } 574 575 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb, 576 struct drm_file *file_priv, 577 unsigned int *handle) 578 { 579 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); 580 581 return drm_gem_handle_create(file_priv, radeon_fb->obj, handle); 582 } 583 584 static const struct drm_framebuffer_funcs radeon_fb_funcs = { 585 .destroy = radeon_user_framebuffer_destroy, 586 .create_handle = radeon_user_framebuffer_create_handle, 587 }; 588 589 struct drm_framebuffer * 590 radeon_framebuffer_create(struct drm_device *dev, 591 struct drm_mode_fb_cmd *mode_cmd, 592 struct drm_gem_object *obj) 593 { 594 struct radeon_framebuffer *radeon_fb; 595 596 radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL); 597 if (radeon_fb == NULL) { 598 return NULL; 599 } 600 drm_framebuffer_init(dev, &radeon_fb->base, &radeon_fb_funcs); 601 drm_helper_mode_fill_fb_struct(&radeon_fb->base, mode_cmd); 602 radeon_fb->obj = obj; 603 return &radeon_fb->base; 604 } 605 606 static struct drm_framebuffer * 607 radeon_user_framebuffer_create(struct drm_device *dev, 608 struct drm_file *file_priv, 609 struct drm_mode_fb_cmd *mode_cmd) 610 { 611 struct drm_gem_object *obj; 612 613 obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handle); 614 615 return radeon_framebuffer_create(dev, mode_cmd, obj); 616 } 617 618 static const struct drm_mode_config_funcs radeon_mode_funcs = { 619 .fb_create = radeon_user_framebuffer_create, 620 .fb_changed = radeonfb_probe, 621 }; 622 623 int radeon_modeset_init(struct radeon_device *rdev) 624 { 625 int num_crtc = 2, i; 626 int ret; 627 628 drm_mode_config_init(rdev->ddev); 629 rdev->mode_info.mode_config_initialized = true; 630 631 rdev->ddev->mode_config.funcs = (void *)&radeon_mode_funcs; 632 633 if (ASIC_IS_AVIVO(rdev)) { 634 rdev->ddev->mode_config.max_width = 8192; 635 rdev->ddev->mode_config.max_height = 8192; 636 } else { 637 rdev->ddev->mode_config.max_width = 4096; 638 rdev->ddev->mode_config.max_height = 4096; 639 } 640 641 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base; 642 643 /* allocate crtcs - TODO single crtc */ 644 for (i = 0; i < num_crtc; i++) { 645 radeon_crtc_init(rdev->ddev, i); 646 } 647 648 /* okay we should have all the bios connectors */ 649 ret = radeon_setup_enc_conn(rdev->ddev); 650 if (!ret) { 651 return ret; 652 } 653 drm_helper_initial_config(rdev->ddev); 654 return 0; 655 } 656 657 void radeon_modeset_fini(struct radeon_device *rdev) 658 { 659 if (rdev->mode_info.mode_config_initialized) { 660 drm_mode_config_cleanup(rdev->ddev); 661 rdev->mode_info.mode_config_initialized = false; 662 } 663 } 664 665 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 666 struct drm_display_mode *mode, 667 struct drm_display_mode *adjusted_mode) 668 { 669 struct drm_device *dev = crtc->dev; 670 struct drm_encoder *encoder; 671 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 672 struct radeon_encoder *radeon_encoder; 673 bool first = true; 674 675 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 676 radeon_encoder = to_radeon_encoder(encoder); 677 if (encoder->crtc != crtc) 678 continue; 679 if (first) { 680 radeon_crtc->rmx_type = radeon_encoder->rmx_type; 681 radeon_crtc->devices = radeon_encoder->devices; 682 memcpy(&radeon_crtc->native_mode, 683 &radeon_encoder->native_mode, 684 sizeof(struct radeon_native_mode)); 685 first = false; 686 } else { 687 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) { 688 /* WARNING: Right now this can't happen but 689 * in the future we need to check that scaling 690 * are consistent accross different encoder 691 * (ie all encoder can work with the same 692 * scaling). 693 */ 694 DRM_ERROR("Scaling not consistent accross encoder.\n"); 695 return false; 696 } 697 } 698 } 699 if (radeon_crtc->rmx_type != RMX_OFF) { 700 fixed20_12 a, b; 701 a.full = rfixed_const(crtc->mode.vdisplay); 702 b.full = rfixed_const(radeon_crtc->native_mode.panel_xres); 703 radeon_crtc->vsc.full = rfixed_div(a, b); 704 a.full = rfixed_const(crtc->mode.hdisplay); 705 b.full = rfixed_const(radeon_crtc->native_mode.panel_yres); 706 radeon_crtc->hsc.full = rfixed_div(a, b); 707 } else { 708 radeon_crtc->vsc.full = rfixed_const(1); 709 radeon_crtc->hsc.full = rfixed_const(1); 710 } 711 return true; 712 } 713