1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/console.h> 29 #include <linux/slab.h> 30 #include <drm/drmP.h> 31 #include <drm/drm_crtc_helper.h> 32 #include <drm/radeon_drm.h> 33 #include <linux/vgaarb.h> 34 #include <linux/vga_switcheroo.h> 35 #include <linux/efi.h> 36 #include "radeon_reg.h" 37 #include "radeon.h" 38 #include "atom.h" 39 40 static const char radeon_family_name[][16] = { 41 "R100", 42 "RV100", 43 "RS100", 44 "RV200", 45 "RS200", 46 "R200", 47 "RV250", 48 "RS300", 49 "RV280", 50 "R300", 51 "R350", 52 "RV350", 53 "RV380", 54 "R420", 55 "R423", 56 "RV410", 57 "RS400", 58 "RS480", 59 "RS600", 60 "RS690", 61 "RS740", 62 "RV515", 63 "R520", 64 "RV530", 65 "RV560", 66 "RV570", 67 "R580", 68 "R600", 69 "RV610", 70 "RV630", 71 "RV670", 72 "RV620", 73 "RV635", 74 "RS780", 75 "RS880", 76 "RV770", 77 "RV730", 78 "RV710", 79 "RV740", 80 "CEDAR", 81 "REDWOOD", 82 "JUNIPER", 83 "CYPRESS", 84 "HEMLOCK", 85 "PALM", 86 "SUMO", 87 "SUMO2", 88 "BARTS", 89 "TURKS", 90 "CAICOS", 91 "CAYMAN", 92 "ARUBA", 93 "TAHITI", 94 "PITCAIRN", 95 "VERDE", 96 "OLAND", 97 "HAINAN", 98 "BONAIRE", 99 "KAVERI", 100 "KABINI", 101 "HAWAII", 102 "LAST", 103 }; 104 105 #if defined(CONFIG_VGA_SWITCHEROO) 106 bool radeon_is_px(void); 107 #else 108 static inline bool radeon_is_px(void) { return false; } 109 #endif 110 111 /** 112 * radeon_program_register_sequence - program an array of registers. 113 * 114 * @rdev: radeon_device pointer 115 * @registers: pointer to the register array 116 * @array_size: size of the register array 117 * 118 * Programs an array or registers with and and or masks. 119 * This is a helper for setting golden registers. 120 */ 121 void radeon_program_register_sequence(struct radeon_device *rdev, 122 const u32 *registers, 123 const u32 array_size) 124 { 125 u32 tmp, reg, and_mask, or_mask; 126 int i; 127 128 if (array_size % 3) 129 return; 130 131 for (i = 0; i < array_size; i +=3) { 132 reg = registers[i + 0]; 133 and_mask = registers[i + 1]; 134 or_mask = registers[i + 2]; 135 136 if (and_mask == 0xffffffff) { 137 tmp = or_mask; 138 } else { 139 tmp = RREG32(reg); 140 tmp &= ~and_mask; 141 tmp |= or_mask; 142 } 143 WREG32(reg, tmp); 144 } 145 } 146 147 /** 148 * radeon_surface_init - Clear GPU surface registers. 149 * 150 * @rdev: radeon_device pointer 151 * 152 * Clear GPU surface registers (r1xx-r5xx). 153 */ 154 void radeon_surface_init(struct radeon_device *rdev) 155 { 156 /* FIXME: check this out */ 157 if (rdev->family < CHIP_R600) { 158 int i; 159 160 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { 161 if (rdev->surface_regs[i].bo) 162 radeon_bo_get_surface_reg(rdev->surface_regs[i].bo); 163 else 164 radeon_clear_surface_reg(rdev, i); 165 } 166 /* enable surfaces */ 167 WREG32(RADEON_SURFACE_CNTL, 0); 168 } 169 } 170 171 /* 172 * GPU scratch registers helpers function. 173 */ 174 /** 175 * radeon_scratch_init - Init scratch register driver information. 176 * 177 * @rdev: radeon_device pointer 178 * 179 * Init CP scratch register driver information (r1xx-r5xx) 180 */ 181 void radeon_scratch_init(struct radeon_device *rdev) 182 { 183 int i; 184 185 /* FIXME: check this out */ 186 if (rdev->family < CHIP_R300) { 187 rdev->scratch.num_reg = 5; 188 } else { 189 rdev->scratch.num_reg = 7; 190 } 191 rdev->scratch.reg_base = RADEON_SCRATCH_REG0; 192 for (i = 0; i < rdev->scratch.num_reg; i++) { 193 rdev->scratch.free[i] = true; 194 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); 195 } 196 } 197 198 /** 199 * radeon_scratch_get - Allocate a scratch register 200 * 201 * @rdev: radeon_device pointer 202 * @reg: scratch register mmio offset 203 * 204 * Allocate a CP scratch register for use by the driver (all asics). 205 * Returns 0 on success or -EINVAL on failure. 206 */ 207 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg) 208 { 209 int i; 210 211 for (i = 0; i < rdev->scratch.num_reg; i++) { 212 if (rdev->scratch.free[i]) { 213 rdev->scratch.free[i] = false; 214 *reg = rdev->scratch.reg[i]; 215 return 0; 216 } 217 } 218 return -EINVAL; 219 } 220 221 /** 222 * radeon_scratch_free - Free a scratch register 223 * 224 * @rdev: radeon_device pointer 225 * @reg: scratch register mmio offset 226 * 227 * Free a CP scratch register allocated for use by the driver (all asics) 228 */ 229 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg) 230 { 231 int i; 232 233 for (i = 0; i < rdev->scratch.num_reg; i++) { 234 if (rdev->scratch.reg[i] == reg) { 235 rdev->scratch.free[i] = true; 236 return; 237 } 238 } 239 } 240 241 /* 242 * GPU doorbell aperture helpers function. 243 */ 244 /** 245 * radeon_doorbell_init - Init doorbell driver information. 246 * 247 * @rdev: radeon_device pointer 248 * 249 * Init doorbell driver information (CIK) 250 * Returns 0 on success, error on failure. 251 */ 252 int radeon_doorbell_init(struct radeon_device *rdev) 253 { 254 /* doorbell bar mapping */ 255 rdev->doorbell.base = pci_resource_start(rdev->pdev, 2); 256 rdev->doorbell.size = pci_resource_len(rdev->pdev, 2); 257 258 rdev->doorbell.num_doorbells = min_t(u32, rdev->doorbell.size / sizeof(u32), RADEON_MAX_DOORBELLS); 259 if (rdev->doorbell.num_doorbells == 0) 260 return -EINVAL; 261 262 rdev->doorbell.ptr = ioremap(rdev->doorbell.base, rdev->doorbell.num_doorbells * sizeof(u32)); 263 if (rdev->doorbell.ptr == NULL) { 264 return -ENOMEM; 265 } 266 DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)rdev->doorbell.base); 267 DRM_INFO("doorbell mmio size: %u\n", (unsigned)rdev->doorbell.size); 268 269 memset(&rdev->doorbell.used, 0, sizeof(rdev->doorbell.used)); 270 271 return 0; 272 } 273 274 /** 275 * radeon_doorbell_fini - Tear down doorbell driver information. 276 * 277 * @rdev: radeon_device pointer 278 * 279 * Tear down doorbell driver information (CIK) 280 */ 281 void radeon_doorbell_fini(struct radeon_device *rdev) 282 { 283 iounmap(rdev->doorbell.ptr); 284 rdev->doorbell.ptr = NULL; 285 } 286 287 /** 288 * radeon_doorbell_get - Allocate a doorbell entry 289 * 290 * @rdev: radeon_device pointer 291 * @doorbell: doorbell index 292 * 293 * Allocate a doorbell for use by the driver (all asics). 294 * Returns 0 on success or -EINVAL on failure. 295 */ 296 int radeon_doorbell_get(struct radeon_device *rdev, u32 *doorbell) 297 { 298 unsigned long offset = find_first_zero_bit(rdev->doorbell.used, rdev->doorbell.num_doorbells); 299 if (offset < rdev->doorbell.num_doorbells) { 300 __set_bit(offset, rdev->doorbell.used); 301 *doorbell = offset; 302 return 0; 303 } else { 304 return -EINVAL; 305 } 306 } 307 308 /** 309 * radeon_doorbell_free - Free a doorbell entry 310 * 311 * @rdev: radeon_device pointer 312 * @doorbell: doorbell index 313 * 314 * Free a doorbell allocated for use by the driver (all asics) 315 */ 316 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell) 317 { 318 if (doorbell < rdev->doorbell.num_doorbells) 319 __clear_bit(doorbell, rdev->doorbell.used); 320 } 321 322 /* 323 * radeon_wb_*() 324 * Writeback is the the method by which the the GPU updates special pages 325 * in memory with the status of certain GPU events (fences, ring pointers, 326 * etc.). 327 */ 328 329 /** 330 * radeon_wb_disable - Disable Writeback 331 * 332 * @rdev: radeon_device pointer 333 * 334 * Disables Writeback (all asics). Used for suspend. 335 */ 336 void radeon_wb_disable(struct radeon_device *rdev) 337 { 338 rdev->wb.enabled = false; 339 } 340 341 /** 342 * radeon_wb_fini - Disable Writeback and free memory 343 * 344 * @rdev: radeon_device pointer 345 * 346 * Disables Writeback and frees the Writeback memory (all asics). 347 * Used at driver shutdown. 348 */ 349 void radeon_wb_fini(struct radeon_device *rdev) 350 { 351 radeon_wb_disable(rdev); 352 if (rdev->wb.wb_obj) { 353 if (!radeon_bo_reserve(rdev->wb.wb_obj, false)) { 354 radeon_bo_kunmap(rdev->wb.wb_obj); 355 radeon_bo_unpin(rdev->wb.wb_obj); 356 radeon_bo_unreserve(rdev->wb.wb_obj); 357 } 358 radeon_bo_unref(&rdev->wb.wb_obj); 359 rdev->wb.wb = NULL; 360 rdev->wb.wb_obj = NULL; 361 } 362 } 363 364 /** 365 * radeon_wb_init- Init Writeback driver info and allocate memory 366 * 367 * @rdev: radeon_device pointer 368 * 369 * Disables Writeback and frees the Writeback memory (all asics). 370 * Used at driver startup. 371 * Returns 0 on success or an -error on failure. 372 */ 373 int radeon_wb_init(struct radeon_device *rdev) 374 { 375 int r; 376 377 if (rdev->wb.wb_obj == NULL) { 378 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true, 379 RADEON_GEM_DOMAIN_GTT, NULL, &rdev->wb.wb_obj); 380 if (r) { 381 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r); 382 return r; 383 } 384 r = radeon_bo_reserve(rdev->wb.wb_obj, false); 385 if (unlikely(r != 0)) { 386 radeon_wb_fini(rdev); 387 return r; 388 } 389 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT, 390 &rdev->wb.gpu_addr); 391 if (r) { 392 radeon_bo_unreserve(rdev->wb.wb_obj); 393 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r); 394 radeon_wb_fini(rdev); 395 return r; 396 } 397 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb); 398 radeon_bo_unreserve(rdev->wb.wb_obj); 399 if (r) { 400 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r); 401 radeon_wb_fini(rdev); 402 return r; 403 } 404 } 405 406 /* clear wb memory */ 407 memset((char *)rdev->wb.wb, 0, RADEON_GPU_PAGE_SIZE); 408 /* disable event_write fences */ 409 rdev->wb.use_event = false; 410 /* disabled via module param */ 411 if (radeon_no_wb == 1) { 412 rdev->wb.enabled = false; 413 } else { 414 if (rdev->flags & RADEON_IS_AGP) { 415 /* often unreliable on AGP */ 416 rdev->wb.enabled = false; 417 } else if (rdev->family < CHIP_R300) { 418 /* often unreliable on pre-r300 */ 419 rdev->wb.enabled = false; 420 } else { 421 rdev->wb.enabled = true; 422 /* event_write fences are only available on r600+ */ 423 if (rdev->family >= CHIP_R600) { 424 rdev->wb.use_event = true; 425 } 426 } 427 } 428 /* always use writeback/events on NI, APUs */ 429 if (rdev->family >= CHIP_PALM) { 430 rdev->wb.enabled = true; 431 rdev->wb.use_event = true; 432 } 433 434 dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis"); 435 436 return 0; 437 } 438 439 /** 440 * radeon_vram_location - try to find VRAM location 441 * @rdev: radeon device structure holding all necessary informations 442 * @mc: memory controller structure holding memory informations 443 * @base: base address at which to put VRAM 444 * 445 * Function will place try to place VRAM at base address provided 446 * as parameter (which is so far either PCI aperture address or 447 * for IGP TOM base address). 448 * 449 * If there is not enough space to fit the unvisible VRAM in the 32bits 450 * address space then we limit the VRAM size to the aperture. 451 * 452 * If we are using AGP and if the AGP aperture doesn't allow us to have 453 * room for all the VRAM than we restrict the VRAM to the PCI aperture 454 * size and print a warning. 455 * 456 * This function will never fails, worst case are limiting VRAM. 457 * 458 * Note: GTT start, end, size should be initialized before calling this 459 * function on AGP platform. 460 * 461 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size, 462 * this shouldn't be a problem as we are using the PCI aperture as a reference. 463 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but 464 * not IGP. 465 * 466 * Note: we use mc_vram_size as on some board we need to program the mc to 467 * cover the whole aperture even if VRAM size is inferior to aperture size 468 * Novell bug 204882 + along with lots of ubuntu ones 469 * 470 * Note: when limiting vram it's safe to overwritte real_vram_size because 471 * we are not in case where real_vram_size is inferior to mc_vram_size (ie 472 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu 473 * ones) 474 * 475 * Note: IGP TOM addr should be the same as the aperture addr, we don't 476 * explicitly check for that thought. 477 * 478 * FIXME: when reducing VRAM size align new size on power of 2. 479 */ 480 void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base) 481 { 482 uint64_t limit = (uint64_t)radeon_vram_limit << 20; 483 484 mc->vram_start = base; 485 if (mc->mc_vram_size > (rdev->mc.mc_mask - base + 1)) { 486 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); 487 mc->real_vram_size = mc->aper_size; 488 mc->mc_vram_size = mc->aper_size; 489 } 490 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 491 if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) { 492 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); 493 mc->real_vram_size = mc->aper_size; 494 mc->mc_vram_size = mc->aper_size; 495 } 496 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 497 if (limit && limit < mc->real_vram_size) 498 mc->real_vram_size = limit; 499 dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", 500 mc->mc_vram_size >> 20, mc->vram_start, 501 mc->vram_end, mc->real_vram_size >> 20); 502 } 503 504 /** 505 * radeon_gtt_location - try to find GTT location 506 * @rdev: radeon device structure holding all necessary informations 507 * @mc: memory controller structure holding memory informations 508 * 509 * Function will place try to place GTT before or after VRAM. 510 * 511 * If GTT size is bigger than space left then we ajust GTT size. 512 * Thus function will never fails. 513 * 514 * FIXME: when reducing GTT size align new size on power of 2. 515 */ 516 void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) 517 { 518 u64 size_af, size_bf; 519 520 size_af = ((rdev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align; 521 size_bf = mc->vram_start & ~mc->gtt_base_align; 522 if (size_bf > size_af) { 523 if (mc->gtt_size > size_bf) { 524 dev_warn(rdev->dev, "limiting GTT\n"); 525 mc->gtt_size = size_bf; 526 } 527 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size; 528 } else { 529 if (mc->gtt_size > size_af) { 530 dev_warn(rdev->dev, "limiting GTT\n"); 531 mc->gtt_size = size_af; 532 } 533 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align; 534 } 535 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1; 536 dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n", 537 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end); 538 } 539 540 /* 541 * GPU helpers function. 542 */ 543 /** 544 * radeon_card_posted - check if the hw has already been initialized 545 * 546 * @rdev: radeon_device pointer 547 * 548 * Check if the asic has been initialized (all asics). 549 * Used at driver startup. 550 * Returns true if initialized or false if not. 551 */ 552 bool radeon_card_posted(struct radeon_device *rdev) 553 { 554 uint32_t reg; 555 556 /* required for EFI mode on macbook2,1 which uses an r5xx asic */ 557 if (efi_enabled(EFI_BOOT) && 558 (rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) && 559 (rdev->family < CHIP_R600)) 560 return false; 561 562 if (ASIC_IS_NODCE(rdev)) 563 goto check_memsize; 564 565 /* first check CRTCs */ 566 if (ASIC_IS_DCE4(rdev)) { 567 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | 568 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); 569 if (rdev->num_crtc >= 4) { 570 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) | 571 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET); 572 } 573 if (rdev->num_crtc >= 6) { 574 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) | 575 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); 576 } 577 if (reg & EVERGREEN_CRTC_MASTER_EN) 578 return true; 579 } else if (ASIC_IS_AVIVO(rdev)) { 580 reg = RREG32(AVIVO_D1CRTC_CONTROL) | 581 RREG32(AVIVO_D2CRTC_CONTROL); 582 if (reg & AVIVO_CRTC_EN) { 583 return true; 584 } 585 } else { 586 reg = RREG32(RADEON_CRTC_GEN_CNTL) | 587 RREG32(RADEON_CRTC2_GEN_CNTL); 588 if (reg & RADEON_CRTC_EN) { 589 return true; 590 } 591 } 592 593 check_memsize: 594 /* then check MEM_SIZE, in case the crtcs are off */ 595 if (rdev->family >= CHIP_R600) 596 reg = RREG32(R600_CONFIG_MEMSIZE); 597 else 598 reg = RREG32(RADEON_CONFIG_MEMSIZE); 599 600 if (reg) 601 return true; 602 603 return false; 604 605 } 606 607 /** 608 * radeon_update_bandwidth_info - update display bandwidth params 609 * 610 * @rdev: radeon_device pointer 611 * 612 * Used when sclk/mclk are switched or display modes are set. 613 * params are used to calculate display watermarks (all asics) 614 */ 615 void radeon_update_bandwidth_info(struct radeon_device *rdev) 616 { 617 fixed20_12 a; 618 u32 sclk = rdev->pm.current_sclk; 619 u32 mclk = rdev->pm.current_mclk; 620 621 /* sclk/mclk in Mhz */ 622 a.full = dfixed_const(100); 623 rdev->pm.sclk.full = dfixed_const(sclk); 624 rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a); 625 rdev->pm.mclk.full = dfixed_const(mclk); 626 rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a); 627 628 if (rdev->flags & RADEON_IS_IGP) { 629 a.full = dfixed_const(16); 630 /* core_bandwidth = sclk(Mhz) * 16 */ 631 rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a); 632 } 633 } 634 635 /** 636 * radeon_boot_test_post_card - check and possibly initialize the hw 637 * 638 * @rdev: radeon_device pointer 639 * 640 * Check if the asic is initialized and if not, attempt to initialize 641 * it (all asics). 642 * Returns true if initialized or false if not. 643 */ 644 bool radeon_boot_test_post_card(struct radeon_device *rdev) 645 { 646 if (radeon_card_posted(rdev)) 647 return true; 648 649 if (rdev->bios) { 650 DRM_INFO("GPU not posted. posting now...\n"); 651 if (rdev->is_atom_bios) 652 atom_asic_init(rdev->mode_info.atom_context); 653 else 654 radeon_combios_asic_init(rdev->ddev); 655 return true; 656 } else { 657 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); 658 return false; 659 } 660 } 661 662 /** 663 * radeon_dummy_page_init - init dummy page used by the driver 664 * 665 * @rdev: radeon_device pointer 666 * 667 * Allocate the dummy page used by the driver (all asics). 668 * This dummy page is used by the driver as a filler for gart entries 669 * when pages are taken out of the GART 670 * Returns 0 on sucess, -ENOMEM on failure. 671 */ 672 int radeon_dummy_page_init(struct radeon_device *rdev) 673 { 674 if (rdev->dummy_page.page) 675 return 0; 676 rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO); 677 if (rdev->dummy_page.page == NULL) 678 return -ENOMEM; 679 rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page, 680 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 681 if (pci_dma_mapping_error(rdev->pdev, rdev->dummy_page.addr)) { 682 dev_err(&rdev->pdev->dev, "Failed to DMA MAP the dummy page\n"); 683 __free_page(rdev->dummy_page.page); 684 rdev->dummy_page.page = NULL; 685 return -ENOMEM; 686 } 687 return 0; 688 } 689 690 /** 691 * radeon_dummy_page_fini - free dummy page used by the driver 692 * 693 * @rdev: radeon_device pointer 694 * 695 * Frees the dummy page used by the driver (all asics). 696 */ 697 void radeon_dummy_page_fini(struct radeon_device *rdev) 698 { 699 if (rdev->dummy_page.page == NULL) 700 return; 701 pci_unmap_page(rdev->pdev, rdev->dummy_page.addr, 702 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 703 __free_page(rdev->dummy_page.page); 704 rdev->dummy_page.page = NULL; 705 } 706 707 708 /* ATOM accessor methods */ 709 /* 710 * ATOM is an interpreted byte code stored in tables in the vbios. The 711 * driver registers callbacks to access registers and the interpreter 712 * in the driver parses the tables and executes then to program specific 713 * actions (set display modes, asic init, etc.). See radeon_atombios.c, 714 * atombios.h, and atom.c 715 */ 716 717 /** 718 * cail_pll_read - read PLL register 719 * 720 * @info: atom card_info pointer 721 * @reg: PLL register offset 722 * 723 * Provides a PLL register accessor for the atom interpreter (r4xx+). 724 * Returns the value of the PLL register. 725 */ 726 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) 727 { 728 struct radeon_device *rdev = info->dev->dev_private; 729 uint32_t r; 730 731 r = rdev->pll_rreg(rdev, reg); 732 return r; 733 } 734 735 /** 736 * cail_pll_write - write PLL register 737 * 738 * @info: atom card_info pointer 739 * @reg: PLL register offset 740 * @val: value to write to the pll register 741 * 742 * Provides a PLL register accessor for the atom interpreter (r4xx+). 743 */ 744 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) 745 { 746 struct radeon_device *rdev = info->dev->dev_private; 747 748 rdev->pll_wreg(rdev, reg, val); 749 } 750 751 /** 752 * cail_mc_read - read MC (Memory Controller) register 753 * 754 * @info: atom card_info pointer 755 * @reg: MC register offset 756 * 757 * Provides an MC register accessor for the atom interpreter (r4xx+). 758 * Returns the value of the MC register. 759 */ 760 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) 761 { 762 struct radeon_device *rdev = info->dev->dev_private; 763 uint32_t r; 764 765 r = rdev->mc_rreg(rdev, reg); 766 return r; 767 } 768 769 /** 770 * cail_mc_write - write MC (Memory Controller) register 771 * 772 * @info: atom card_info pointer 773 * @reg: MC register offset 774 * @val: value to write to the pll register 775 * 776 * Provides a MC register accessor for the atom interpreter (r4xx+). 777 */ 778 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) 779 { 780 struct radeon_device *rdev = info->dev->dev_private; 781 782 rdev->mc_wreg(rdev, reg, val); 783 } 784 785 /** 786 * cail_reg_write - write MMIO register 787 * 788 * @info: atom card_info pointer 789 * @reg: MMIO register offset 790 * @val: value to write to the pll register 791 * 792 * Provides a MMIO register accessor for the atom interpreter (r4xx+). 793 */ 794 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) 795 { 796 struct radeon_device *rdev = info->dev->dev_private; 797 798 WREG32(reg*4, val); 799 } 800 801 /** 802 * cail_reg_read - read MMIO register 803 * 804 * @info: atom card_info pointer 805 * @reg: MMIO register offset 806 * 807 * Provides an MMIO register accessor for the atom interpreter (r4xx+). 808 * Returns the value of the MMIO register. 809 */ 810 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) 811 { 812 struct radeon_device *rdev = info->dev->dev_private; 813 uint32_t r; 814 815 r = RREG32(reg*4); 816 return r; 817 } 818 819 /** 820 * cail_ioreg_write - write IO register 821 * 822 * @info: atom card_info pointer 823 * @reg: IO register offset 824 * @val: value to write to the pll register 825 * 826 * Provides a IO register accessor for the atom interpreter (r4xx+). 827 */ 828 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val) 829 { 830 struct radeon_device *rdev = info->dev->dev_private; 831 832 WREG32_IO(reg*4, val); 833 } 834 835 /** 836 * cail_ioreg_read - read IO register 837 * 838 * @info: atom card_info pointer 839 * @reg: IO register offset 840 * 841 * Provides an IO register accessor for the atom interpreter (r4xx+). 842 * Returns the value of the IO register. 843 */ 844 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg) 845 { 846 struct radeon_device *rdev = info->dev->dev_private; 847 uint32_t r; 848 849 r = RREG32_IO(reg*4); 850 return r; 851 } 852 853 /** 854 * radeon_atombios_init - init the driver info and callbacks for atombios 855 * 856 * @rdev: radeon_device pointer 857 * 858 * Initializes the driver info and register access callbacks for the 859 * ATOM interpreter (r4xx+). 860 * Returns 0 on sucess, -ENOMEM on failure. 861 * Called at driver startup. 862 */ 863 int radeon_atombios_init(struct radeon_device *rdev) 864 { 865 struct card_info *atom_card_info = 866 kzalloc(sizeof(struct card_info), GFP_KERNEL); 867 868 if (!atom_card_info) 869 return -ENOMEM; 870 871 rdev->mode_info.atom_card_info = atom_card_info; 872 atom_card_info->dev = rdev->ddev; 873 atom_card_info->reg_read = cail_reg_read; 874 atom_card_info->reg_write = cail_reg_write; 875 /* needed for iio ops */ 876 if (rdev->rio_mem) { 877 atom_card_info->ioreg_read = cail_ioreg_read; 878 atom_card_info->ioreg_write = cail_ioreg_write; 879 } else { 880 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n"); 881 atom_card_info->ioreg_read = cail_reg_read; 882 atom_card_info->ioreg_write = cail_reg_write; 883 } 884 atom_card_info->mc_read = cail_mc_read; 885 atom_card_info->mc_write = cail_mc_write; 886 atom_card_info->pll_read = cail_pll_read; 887 atom_card_info->pll_write = cail_pll_write; 888 889 rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios); 890 if (!rdev->mode_info.atom_context) { 891 radeon_atombios_fini(rdev); 892 return -ENOMEM; 893 } 894 895 mutex_init(&rdev->mode_info.atom_context->mutex); 896 radeon_atom_initialize_bios_scratch_regs(rdev->ddev); 897 atom_allocate_fb_scratch(rdev->mode_info.atom_context); 898 return 0; 899 } 900 901 /** 902 * radeon_atombios_fini - free the driver info and callbacks for atombios 903 * 904 * @rdev: radeon_device pointer 905 * 906 * Frees the driver info and register access callbacks for the ATOM 907 * interpreter (r4xx+). 908 * Called at driver shutdown. 909 */ 910 void radeon_atombios_fini(struct radeon_device *rdev) 911 { 912 if (rdev->mode_info.atom_context) { 913 kfree(rdev->mode_info.atom_context->scratch); 914 } 915 kfree(rdev->mode_info.atom_context); 916 rdev->mode_info.atom_context = NULL; 917 kfree(rdev->mode_info.atom_card_info); 918 rdev->mode_info.atom_card_info = NULL; 919 } 920 921 /* COMBIOS */ 922 /* 923 * COMBIOS is the bios format prior to ATOM. It provides 924 * command tables similar to ATOM, but doesn't have a unified 925 * parser. See radeon_combios.c 926 */ 927 928 /** 929 * radeon_combios_init - init the driver info for combios 930 * 931 * @rdev: radeon_device pointer 932 * 933 * Initializes the driver info for combios (r1xx-r3xx). 934 * Returns 0 on sucess. 935 * Called at driver startup. 936 */ 937 int radeon_combios_init(struct radeon_device *rdev) 938 { 939 radeon_combios_initialize_bios_scratch_regs(rdev->ddev); 940 return 0; 941 } 942 943 /** 944 * radeon_combios_fini - free the driver info for combios 945 * 946 * @rdev: radeon_device pointer 947 * 948 * Frees the driver info for combios (r1xx-r3xx). 949 * Called at driver shutdown. 950 */ 951 void radeon_combios_fini(struct radeon_device *rdev) 952 { 953 } 954 955 /* if we get transitioned to only one device, take VGA back */ 956 /** 957 * radeon_vga_set_decode - enable/disable vga decode 958 * 959 * @cookie: radeon_device pointer 960 * @state: enable/disable vga decode 961 * 962 * Enable/disable vga decode (all asics). 963 * Returns VGA resource flags. 964 */ 965 static unsigned int radeon_vga_set_decode(void *cookie, bool state) 966 { 967 struct radeon_device *rdev = cookie; 968 radeon_vga_set_state(rdev, state); 969 if (state) 970 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | 971 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; 972 else 973 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; 974 } 975 976 /** 977 * radeon_check_pot_argument - check that argument is a power of two 978 * 979 * @arg: value to check 980 * 981 * Validates that a certain argument is a power of two (all asics). 982 * Returns true if argument is valid. 983 */ 984 static bool radeon_check_pot_argument(int arg) 985 { 986 return (arg & (arg - 1)) == 0; 987 } 988 989 /** 990 * radeon_check_arguments - validate module params 991 * 992 * @rdev: radeon_device pointer 993 * 994 * Validates certain module parameters and updates 995 * the associated values used by the driver (all asics). 996 */ 997 static void radeon_check_arguments(struct radeon_device *rdev) 998 { 999 /* vramlimit must be a power of two */ 1000 if (!radeon_check_pot_argument(radeon_vram_limit)) { 1001 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n", 1002 radeon_vram_limit); 1003 radeon_vram_limit = 0; 1004 } 1005 1006 if (radeon_gart_size == -1) { 1007 /* default to a larger gart size on newer asics */ 1008 if (rdev->family >= CHIP_RV770) 1009 radeon_gart_size = 1024; 1010 else 1011 radeon_gart_size = 512; 1012 } 1013 /* gtt size must be power of two and greater or equal to 32M */ 1014 if (radeon_gart_size < 32) { 1015 dev_warn(rdev->dev, "gart size (%d) too small\n", 1016 radeon_gart_size); 1017 if (rdev->family >= CHIP_RV770) 1018 radeon_gart_size = 1024; 1019 else 1020 radeon_gart_size = 512; 1021 } else if (!radeon_check_pot_argument(radeon_gart_size)) { 1022 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n", 1023 radeon_gart_size); 1024 if (rdev->family >= CHIP_RV770) 1025 radeon_gart_size = 1024; 1026 else 1027 radeon_gart_size = 512; 1028 } 1029 rdev->mc.gtt_size = (uint64_t)radeon_gart_size << 20; 1030 1031 /* AGP mode can only be -1, 1, 2, 4, 8 */ 1032 switch (radeon_agpmode) { 1033 case -1: 1034 case 0: 1035 case 1: 1036 case 2: 1037 case 4: 1038 case 8: 1039 break; 1040 default: 1041 dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: " 1042 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode); 1043 radeon_agpmode = 0; 1044 break; 1045 } 1046 } 1047 1048 /** 1049 * radeon_switcheroo_quirk_long_wakeup - return true if longer d3 delay is 1050 * needed for waking up. 1051 * 1052 * @pdev: pci dev pointer 1053 */ 1054 static bool radeon_switcheroo_quirk_long_wakeup(struct pci_dev *pdev) 1055 { 1056 1057 /* 6600m in a macbook pro */ 1058 if (pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE && 1059 pdev->subsystem_device == 0x00e2) { 1060 printk(KERN_INFO "radeon: quirking longer d3 wakeup delay\n"); 1061 return true; 1062 } 1063 1064 return false; 1065 } 1066 1067 /** 1068 * radeon_switcheroo_set_state - set switcheroo state 1069 * 1070 * @pdev: pci dev pointer 1071 * @state: vga switcheroo state 1072 * 1073 * Callback for the switcheroo driver. Suspends or resumes the 1074 * the asics before or after it is powered up using ACPI methods. 1075 */ 1076 static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) 1077 { 1078 struct drm_device *dev = pci_get_drvdata(pdev); 1079 1080 if (radeon_is_px() && state == VGA_SWITCHEROO_OFF) 1081 return; 1082 1083 if (state == VGA_SWITCHEROO_ON) { 1084 unsigned d3_delay = dev->pdev->d3_delay; 1085 1086 printk(KERN_INFO "radeon: switched on\n"); 1087 /* don't suspend or resume card normally */ 1088 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1089 1090 if (d3_delay < 20 && radeon_switcheroo_quirk_long_wakeup(pdev)) 1091 dev->pdev->d3_delay = 20; 1092 1093 radeon_resume_kms(dev, true, true); 1094 1095 dev->pdev->d3_delay = d3_delay; 1096 1097 dev->switch_power_state = DRM_SWITCH_POWER_ON; 1098 drm_kms_helper_poll_enable(dev); 1099 } else { 1100 printk(KERN_INFO "radeon: switched off\n"); 1101 drm_kms_helper_poll_disable(dev); 1102 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1103 radeon_suspend_kms(dev, true, true); 1104 dev->switch_power_state = DRM_SWITCH_POWER_OFF; 1105 } 1106 } 1107 1108 /** 1109 * radeon_switcheroo_can_switch - see if switcheroo state can change 1110 * 1111 * @pdev: pci dev pointer 1112 * 1113 * Callback for the switcheroo driver. Check of the switcheroo 1114 * state can be changed. 1115 * Returns true if the state can be changed, false if not. 1116 */ 1117 static bool radeon_switcheroo_can_switch(struct pci_dev *pdev) 1118 { 1119 struct drm_device *dev = pci_get_drvdata(pdev); 1120 bool can_switch; 1121 1122 spin_lock(&dev->count_lock); 1123 can_switch = (dev->open_count == 0); 1124 spin_unlock(&dev->count_lock); 1125 return can_switch; 1126 } 1127 1128 static const struct vga_switcheroo_client_ops radeon_switcheroo_ops = { 1129 .set_gpu_state = radeon_switcheroo_set_state, 1130 .reprobe = NULL, 1131 .can_switch = radeon_switcheroo_can_switch, 1132 }; 1133 1134 /** 1135 * radeon_device_init - initialize the driver 1136 * 1137 * @rdev: radeon_device pointer 1138 * @pdev: drm dev pointer 1139 * @pdev: pci dev pointer 1140 * @flags: driver flags 1141 * 1142 * Initializes the driver info and hw (all asics). 1143 * Returns 0 for success or an error on failure. 1144 * Called at driver startup. 1145 */ 1146 int radeon_device_init(struct radeon_device *rdev, 1147 struct drm_device *ddev, 1148 struct pci_dev *pdev, 1149 uint32_t flags) 1150 { 1151 int r, i; 1152 int dma_bits; 1153 bool runtime = false; 1154 1155 rdev->shutdown = false; 1156 rdev->dev = &pdev->dev; 1157 rdev->ddev = ddev; 1158 rdev->pdev = pdev; 1159 rdev->flags = flags; 1160 rdev->family = flags & RADEON_FAMILY_MASK; 1161 rdev->is_atom_bios = false; 1162 rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT; 1163 rdev->mc.gtt_size = 512 * 1024 * 1024; 1164 rdev->accel_working = false; 1165 /* set up ring ids */ 1166 for (i = 0; i < RADEON_NUM_RINGS; i++) { 1167 rdev->ring[i].idx = i; 1168 } 1169 1170 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n", 1171 radeon_family_name[rdev->family], pdev->vendor, pdev->device, 1172 pdev->subsystem_vendor, pdev->subsystem_device); 1173 1174 /* mutex initialization are all done here so we 1175 * can recall function without having locking issues */ 1176 mutex_init(&rdev->ring_lock); 1177 mutex_init(&rdev->dc_hw_i2c_mutex); 1178 atomic_set(&rdev->ih.lock, 0); 1179 mutex_init(&rdev->gem.mutex); 1180 mutex_init(&rdev->pm.mutex); 1181 mutex_init(&rdev->gpu_clock_mutex); 1182 mutex_init(&rdev->srbm_mutex); 1183 init_rwsem(&rdev->pm.mclk_lock); 1184 init_rwsem(&rdev->exclusive_lock); 1185 init_waitqueue_head(&rdev->irq.vblank_queue); 1186 r = radeon_gem_init(rdev); 1187 if (r) 1188 return r; 1189 /* initialize vm here */ 1190 mutex_init(&rdev->vm_manager.lock); 1191 /* Adjust VM size here. 1192 * Currently set to 4GB ((1 << 20) 4k pages). 1193 * Max GPUVM size for cayman and SI is 40 bits. 1194 */ 1195 rdev->vm_manager.max_pfn = 1 << 20; 1196 INIT_LIST_HEAD(&rdev->vm_manager.lru_vm); 1197 1198 /* Set asic functions */ 1199 r = radeon_asic_init(rdev); 1200 if (r) 1201 return r; 1202 radeon_check_arguments(rdev); 1203 1204 /* all of the newer IGP chips have an internal gart 1205 * However some rs4xx report as AGP, so remove that here. 1206 */ 1207 if ((rdev->family >= CHIP_RS400) && 1208 (rdev->flags & RADEON_IS_IGP)) { 1209 rdev->flags &= ~RADEON_IS_AGP; 1210 } 1211 1212 if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) { 1213 radeon_agp_disable(rdev); 1214 } 1215 1216 /* Set the internal MC address mask 1217 * This is the max address of the GPU's 1218 * internal address space. 1219 */ 1220 if (rdev->family >= CHIP_CAYMAN) 1221 rdev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ 1222 else if (rdev->family >= CHIP_CEDAR) 1223 rdev->mc.mc_mask = 0xfffffffffULL; /* 36 bit MC */ 1224 else 1225 rdev->mc.mc_mask = 0xffffffffULL; /* 32 bit MC */ 1226 1227 /* set DMA mask + need_dma32 flags. 1228 * PCIE - can handle 40-bits. 1229 * IGP - can handle 40-bits 1230 * AGP - generally dma32 is safest 1231 * PCI - dma32 for legacy pci gart, 40 bits on newer asics 1232 */ 1233 rdev->need_dma32 = false; 1234 if (rdev->flags & RADEON_IS_AGP) 1235 rdev->need_dma32 = true; 1236 if ((rdev->flags & RADEON_IS_PCI) && 1237 (rdev->family <= CHIP_RS740)) 1238 rdev->need_dma32 = true; 1239 1240 dma_bits = rdev->need_dma32 ? 32 : 40; 1241 r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits)); 1242 if (r) { 1243 rdev->need_dma32 = true; 1244 dma_bits = 32; 1245 printk(KERN_WARNING "radeon: No suitable DMA available.\n"); 1246 } 1247 r = pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits)); 1248 if (r) { 1249 pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(32)); 1250 printk(KERN_WARNING "radeon: No coherent DMA available.\n"); 1251 } 1252 1253 /* Registers mapping */ 1254 /* TODO: block userspace mapping of io register */ 1255 spin_lock_init(&rdev->mmio_idx_lock); 1256 spin_lock_init(&rdev->smc_idx_lock); 1257 spin_lock_init(&rdev->pll_idx_lock); 1258 spin_lock_init(&rdev->mc_idx_lock); 1259 spin_lock_init(&rdev->pcie_idx_lock); 1260 spin_lock_init(&rdev->pciep_idx_lock); 1261 spin_lock_init(&rdev->pif_idx_lock); 1262 spin_lock_init(&rdev->cg_idx_lock); 1263 spin_lock_init(&rdev->uvd_idx_lock); 1264 spin_lock_init(&rdev->rcu_idx_lock); 1265 spin_lock_init(&rdev->didt_idx_lock); 1266 spin_lock_init(&rdev->end_idx_lock); 1267 if (rdev->family >= CHIP_BONAIRE) { 1268 rdev->rmmio_base = pci_resource_start(rdev->pdev, 5); 1269 rdev->rmmio_size = pci_resource_len(rdev->pdev, 5); 1270 } else { 1271 rdev->rmmio_base = pci_resource_start(rdev->pdev, 2); 1272 rdev->rmmio_size = pci_resource_len(rdev->pdev, 2); 1273 } 1274 rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size); 1275 if (rdev->rmmio == NULL) { 1276 return -ENOMEM; 1277 } 1278 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base); 1279 DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size); 1280 1281 /* doorbell bar mapping */ 1282 if (rdev->family >= CHIP_BONAIRE) 1283 radeon_doorbell_init(rdev); 1284 1285 /* io port mapping */ 1286 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 1287 if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) { 1288 rdev->rio_mem_size = pci_resource_len(rdev->pdev, i); 1289 rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size); 1290 break; 1291 } 1292 } 1293 if (rdev->rio_mem == NULL) 1294 DRM_ERROR("Unable to find PCI I/O BAR\n"); 1295 1296 /* if we have > 1 VGA cards, then disable the radeon VGA resources */ 1297 /* this will fail for cards that aren't VGA class devices, just 1298 * ignore it */ 1299 vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode); 1300 1301 if (radeon_runtime_pm == 1) 1302 runtime = true; 1303 if ((radeon_runtime_pm == -1) && radeon_is_px()) 1304 runtime = true; 1305 vga_switcheroo_register_client(rdev->pdev, &radeon_switcheroo_ops, runtime); 1306 if (runtime) 1307 vga_switcheroo_init_domain_pm_ops(rdev->dev, &rdev->vga_pm_domain); 1308 1309 r = radeon_init(rdev); 1310 if (r) 1311 return r; 1312 1313 r = radeon_ib_ring_tests(rdev); 1314 if (r) 1315 DRM_ERROR("ib ring test failed (%d).\n", r); 1316 1317 r = radeon_gem_debugfs_init(rdev); 1318 if (r) { 1319 DRM_ERROR("registering gem debugfs failed (%d).\n", r); 1320 } 1321 1322 if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) { 1323 /* Acceleration not working on AGP card try again 1324 * with fallback to PCI or PCIE GART 1325 */ 1326 radeon_asic_reset(rdev); 1327 radeon_fini(rdev); 1328 radeon_agp_disable(rdev); 1329 r = radeon_init(rdev); 1330 if (r) 1331 return r; 1332 } 1333 if ((radeon_testing & 1)) { 1334 if (rdev->accel_working) 1335 radeon_test_moves(rdev); 1336 else 1337 DRM_INFO("radeon: acceleration disabled, skipping move tests\n"); 1338 } 1339 if ((radeon_testing & 2)) { 1340 if (rdev->accel_working) 1341 radeon_test_syncing(rdev); 1342 else 1343 DRM_INFO("radeon: acceleration disabled, skipping sync tests\n"); 1344 } 1345 if (radeon_benchmarking) { 1346 if (rdev->accel_working) 1347 radeon_benchmark(rdev, radeon_benchmarking); 1348 else 1349 DRM_INFO("radeon: acceleration disabled, skipping benchmarks\n"); 1350 } 1351 return 0; 1352 } 1353 1354 static void radeon_debugfs_remove_files(struct radeon_device *rdev); 1355 1356 /** 1357 * radeon_device_fini - tear down the driver 1358 * 1359 * @rdev: radeon_device pointer 1360 * 1361 * Tear down the driver info (all asics). 1362 * Called at driver shutdown. 1363 */ 1364 void radeon_device_fini(struct radeon_device *rdev) 1365 { 1366 DRM_INFO("radeon: finishing device.\n"); 1367 rdev->shutdown = true; 1368 /* evict vram memory */ 1369 radeon_bo_evict_vram(rdev); 1370 radeon_fini(rdev); 1371 vga_switcheroo_unregister_client(rdev->pdev); 1372 vga_client_register(rdev->pdev, NULL, NULL, NULL); 1373 if (rdev->rio_mem) 1374 pci_iounmap(rdev->pdev, rdev->rio_mem); 1375 rdev->rio_mem = NULL; 1376 iounmap(rdev->rmmio); 1377 rdev->rmmio = NULL; 1378 if (rdev->family >= CHIP_BONAIRE) 1379 radeon_doorbell_fini(rdev); 1380 radeon_debugfs_remove_files(rdev); 1381 } 1382 1383 1384 /* 1385 * Suspend & resume. 1386 */ 1387 /** 1388 * radeon_suspend_kms - initiate device suspend 1389 * 1390 * @pdev: drm dev pointer 1391 * @state: suspend state 1392 * 1393 * Puts the hw in the suspend state (all asics). 1394 * Returns 0 for success or an error on failure. 1395 * Called at driver suspend. 1396 */ 1397 int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon) 1398 { 1399 struct radeon_device *rdev; 1400 struct drm_crtc *crtc; 1401 struct drm_connector *connector; 1402 int i, r; 1403 bool force_completion = false; 1404 1405 if (dev == NULL || dev->dev_private == NULL) { 1406 return -ENODEV; 1407 } 1408 1409 rdev = dev->dev_private; 1410 1411 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) 1412 return 0; 1413 1414 drm_kms_helper_poll_disable(dev); 1415 1416 /* turn off display hw */ 1417 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 1418 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); 1419 } 1420 1421 /* unpin the front buffers */ 1422 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 1423 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb); 1424 struct radeon_bo *robj; 1425 1426 if (rfb == NULL || rfb->obj == NULL) { 1427 continue; 1428 } 1429 robj = gem_to_radeon_bo(rfb->obj); 1430 /* don't unpin kernel fb objects */ 1431 if (!radeon_fbdev_robj_is_fb(rdev, robj)) { 1432 r = radeon_bo_reserve(robj, false); 1433 if (r == 0) { 1434 radeon_bo_unpin(robj); 1435 radeon_bo_unreserve(robj); 1436 } 1437 } 1438 } 1439 /* evict vram memory */ 1440 radeon_bo_evict_vram(rdev); 1441 1442 mutex_lock(&rdev->ring_lock); 1443 /* wait for gpu to finish processing current batch */ 1444 for (i = 0; i < RADEON_NUM_RINGS; i++) { 1445 r = radeon_fence_wait_empty_locked(rdev, i); 1446 if (r) { 1447 /* delay GPU reset to resume */ 1448 force_completion = true; 1449 } 1450 } 1451 if (force_completion) { 1452 radeon_fence_driver_force_completion(rdev); 1453 } 1454 mutex_unlock(&rdev->ring_lock); 1455 1456 radeon_save_bios_scratch_regs(rdev); 1457 1458 radeon_pm_suspend(rdev); 1459 radeon_suspend(rdev); 1460 radeon_hpd_fini(rdev); 1461 /* evict remaining vram memory */ 1462 radeon_bo_evict_vram(rdev); 1463 1464 radeon_agp_suspend(rdev); 1465 1466 pci_save_state(dev->pdev); 1467 if (suspend) { 1468 /* Shut down the device */ 1469 pci_disable_device(dev->pdev); 1470 pci_set_power_state(dev->pdev, PCI_D3hot); 1471 } 1472 1473 if (fbcon) { 1474 console_lock(); 1475 radeon_fbdev_set_suspend(rdev, 1); 1476 console_unlock(); 1477 } 1478 return 0; 1479 } 1480 1481 /** 1482 * radeon_resume_kms - initiate device resume 1483 * 1484 * @pdev: drm dev pointer 1485 * 1486 * Bring the hw back to operating state (all asics). 1487 * Returns 0 for success or an error on failure. 1488 * Called at driver resume. 1489 */ 1490 int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon) 1491 { 1492 struct drm_connector *connector; 1493 struct radeon_device *rdev = dev->dev_private; 1494 int r; 1495 1496 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) 1497 return 0; 1498 1499 if (fbcon) { 1500 console_lock(); 1501 } 1502 if (resume) { 1503 pci_set_power_state(dev->pdev, PCI_D0); 1504 pci_restore_state(dev->pdev); 1505 if (pci_enable_device(dev->pdev)) { 1506 if (fbcon) 1507 console_unlock(); 1508 return -1; 1509 } 1510 } 1511 /* resume AGP if in use */ 1512 radeon_agp_resume(rdev); 1513 radeon_resume(rdev); 1514 1515 r = radeon_ib_ring_tests(rdev); 1516 if (r) 1517 DRM_ERROR("ib ring test failed (%d).\n", r); 1518 1519 radeon_pm_resume(rdev); 1520 radeon_restore_bios_scratch_regs(rdev); 1521 1522 if (fbcon) { 1523 radeon_fbdev_set_suspend(rdev, 0); 1524 console_unlock(); 1525 } 1526 1527 /* init dig PHYs, disp eng pll */ 1528 if (rdev->is_atom_bios) { 1529 radeon_atom_encoder_init(rdev); 1530 radeon_atom_disp_eng_pll_init(rdev); 1531 /* turn on the BL */ 1532 if (rdev->mode_info.bl_encoder) { 1533 u8 bl_level = radeon_get_backlight_level(rdev, 1534 rdev->mode_info.bl_encoder); 1535 radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder, 1536 bl_level); 1537 } 1538 } 1539 /* reset hpd state */ 1540 radeon_hpd_init(rdev); 1541 /* blat the mode back in */ 1542 drm_helper_resume_force_mode(dev); 1543 /* turn on display hw */ 1544 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 1545 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); 1546 } 1547 1548 drm_kms_helper_poll_enable(dev); 1549 return 0; 1550 } 1551 1552 /** 1553 * radeon_gpu_reset - reset the asic 1554 * 1555 * @rdev: radeon device pointer 1556 * 1557 * Attempt the reset the GPU if it has hung (all asics). 1558 * Returns 0 for success or an error on failure. 1559 */ 1560 int radeon_gpu_reset(struct radeon_device *rdev) 1561 { 1562 unsigned ring_sizes[RADEON_NUM_RINGS]; 1563 uint32_t *ring_data[RADEON_NUM_RINGS]; 1564 1565 bool saved = false; 1566 1567 int i, r; 1568 int resched; 1569 1570 down_write(&rdev->exclusive_lock); 1571 1572 if (!rdev->needs_reset) { 1573 up_write(&rdev->exclusive_lock); 1574 return 0; 1575 } 1576 1577 rdev->needs_reset = false; 1578 1579 radeon_save_bios_scratch_regs(rdev); 1580 /* block TTM */ 1581 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev); 1582 radeon_pm_suspend(rdev); 1583 radeon_suspend(rdev); 1584 1585 for (i = 0; i < RADEON_NUM_RINGS; ++i) { 1586 ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i], 1587 &ring_data[i]); 1588 if (ring_sizes[i]) { 1589 saved = true; 1590 dev_info(rdev->dev, "Saved %d dwords of commands " 1591 "on ring %d.\n", ring_sizes[i], i); 1592 } 1593 } 1594 1595 retry: 1596 r = radeon_asic_reset(rdev); 1597 if (!r) { 1598 dev_info(rdev->dev, "GPU reset succeeded, trying to resume\n"); 1599 radeon_resume(rdev); 1600 } 1601 1602 radeon_restore_bios_scratch_regs(rdev); 1603 1604 if (!r) { 1605 for (i = 0; i < RADEON_NUM_RINGS; ++i) { 1606 radeon_ring_restore(rdev, &rdev->ring[i], 1607 ring_sizes[i], ring_data[i]); 1608 ring_sizes[i] = 0; 1609 ring_data[i] = NULL; 1610 } 1611 1612 r = radeon_ib_ring_tests(rdev); 1613 if (r) { 1614 dev_err(rdev->dev, "ib ring test failed (%d).\n", r); 1615 if (saved) { 1616 saved = false; 1617 radeon_suspend(rdev); 1618 goto retry; 1619 } 1620 } 1621 } else { 1622 radeon_fence_driver_force_completion(rdev); 1623 for (i = 0; i < RADEON_NUM_RINGS; ++i) { 1624 kfree(ring_data[i]); 1625 } 1626 } 1627 1628 radeon_pm_resume(rdev); 1629 drm_helper_resume_force_mode(rdev->ddev); 1630 1631 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched); 1632 if (r) { 1633 /* bad news, how to tell it to userspace ? */ 1634 dev_info(rdev->dev, "GPU reset failed\n"); 1635 } 1636 1637 up_write(&rdev->exclusive_lock); 1638 return r; 1639 } 1640 1641 1642 /* 1643 * Debugfs 1644 */ 1645 int radeon_debugfs_add_files(struct radeon_device *rdev, 1646 struct drm_info_list *files, 1647 unsigned nfiles) 1648 { 1649 unsigned i; 1650 1651 for (i = 0; i < rdev->debugfs_count; i++) { 1652 if (rdev->debugfs[i].files == files) { 1653 /* Already registered */ 1654 return 0; 1655 } 1656 } 1657 1658 i = rdev->debugfs_count + 1; 1659 if (i > RADEON_DEBUGFS_MAX_COMPONENTS) { 1660 DRM_ERROR("Reached maximum number of debugfs components.\n"); 1661 DRM_ERROR("Report so we increase " 1662 "RADEON_DEBUGFS_MAX_COMPONENTS.\n"); 1663 return -EINVAL; 1664 } 1665 rdev->debugfs[rdev->debugfs_count].files = files; 1666 rdev->debugfs[rdev->debugfs_count].num_files = nfiles; 1667 rdev->debugfs_count = i; 1668 #if defined(CONFIG_DEBUG_FS) 1669 drm_debugfs_create_files(files, nfiles, 1670 rdev->ddev->control->debugfs_root, 1671 rdev->ddev->control); 1672 drm_debugfs_create_files(files, nfiles, 1673 rdev->ddev->primary->debugfs_root, 1674 rdev->ddev->primary); 1675 #endif 1676 return 0; 1677 } 1678 1679 static void radeon_debugfs_remove_files(struct radeon_device *rdev) 1680 { 1681 #if defined(CONFIG_DEBUG_FS) 1682 unsigned i; 1683 1684 for (i = 0; i < rdev->debugfs_count; i++) { 1685 drm_debugfs_remove_files(rdev->debugfs[i].files, 1686 rdev->debugfs[i].num_files, 1687 rdev->ddev->control); 1688 drm_debugfs_remove_files(rdev->debugfs[i].files, 1689 rdev->debugfs[i].num_files, 1690 rdev->ddev->primary); 1691 } 1692 #endif 1693 } 1694 1695 #if defined(CONFIG_DEBUG_FS) 1696 int radeon_debugfs_init(struct drm_minor *minor) 1697 { 1698 return 0; 1699 } 1700 1701 void radeon_debugfs_cleanup(struct drm_minor *minor) 1702 { 1703 } 1704 #endif 1705