1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/console.h> 29 #include <linux/slab.h> 30 #include <drm/drmP.h> 31 #include <drm/drm_crtc_helper.h> 32 #include <drm/radeon_drm.h> 33 #include <linux/vgaarb.h> 34 #include <linux/vga_switcheroo.h> 35 #include <linux/efi.h> 36 #include "radeon_reg.h" 37 #include "radeon.h" 38 #include "atom.h" 39 40 static const char radeon_family_name[][16] = { 41 "R100", 42 "RV100", 43 "RS100", 44 "RV200", 45 "RS200", 46 "R200", 47 "RV250", 48 "RS300", 49 "RV280", 50 "R300", 51 "R350", 52 "RV350", 53 "RV380", 54 "R420", 55 "R423", 56 "RV410", 57 "RS400", 58 "RS480", 59 "RS600", 60 "RS690", 61 "RS740", 62 "RV515", 63 "R520", 64 "RV530", 65 "RV560", 66 "RV570", 67 "R580", 68 "R600", 69 "RV610", 70 "RV630", 71 "RV670", 72 "RV620", 73 "RV635", 74 "RS780", 75 "RS880", 76 "RV770", 77 "RV730", 78 "RV710", 79 "RV740", 80 "CEDAR", 81 "REDWOOD", 82 "JUNIPER", 83 "CYPRESS", 84 "HEMLOCK", 85 "PALM", 86 "SUMO", 87 "SUMO2", 88 "BARTS", 89 "TURKS", 90 "CAICOS", 91 "CAYMAN", 92 "LAST", 93 }; 94 95 /* 96 * Clear GPU surface registers. 97 */ 98 void radeon_surface_init(struct radeon_device *rdev) 99 { 100 /* FIXME: check this out */ 101 if (rdev->family < CHIP_R600) { 102 int i; 103 104 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { 105 if (rdev->surface_regs[i].bo) 106 radeon_bo_get_surface_reg(rdev->surface_regs[i].bo); 107 else 108 radeon_clear_surface_reg(rdev, i); 109 } 110 /* enable surfaces */ 111 WREG32(RADEON_SURFACE_CNTL, 0); 112 } 113 } 114 115 /* 116 * GPU scratch registers helpers function. 117 */ 118 void radeon_scratch_init(struct radeon_device *rdev) 119 { 120 int i; 121 122 /* FIXME: check this out */ 123 if (rdev->family < CHIP_R300) { 124 rdev->scratch.num_reg = 5; 125 } else { 126 rdev->scratch.num_reg = 7; 127 } 128 rdev->scratch.reg_base = RADEON_SCRATCH_REG0; 129 for (i = 0; i < rdev->scratch.num_reg; i++) { 130 rdev->scratch.free[i] = true; 131 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); 132 } 133 } 134 135 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg) 136 { 137 int i; 138 139 for (i = 0; i < rdev->scratch.num_reg; i++) { 140 if (rdev->scratch.free[i]) { 141 rdev->scratch.free[i] = false; 142 *reg = rdev->scratch.reg[i]; 143 return 0; 144 } 145 } 146 return -EINVAL; 147 } 148 149 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg) 150 { 151 int i; 152 153 for (i = 0; i < rdev->scratch.num_reg; i++) { 154 if (rdev->scratch.reg[i] == reg) { 155 rdev->scratch.free[i] = true; 156 return; 157 } 158 } 159 } 160 161 void radeon_wb_disable(struct radeon_device *rdev) 162 { 163 int r; 164 165 if (rdev->wb.wb_obj) { 166 r = radeon_bo_reserve(rdev->wb.wb_obj, false); 167 if (unlikely(r != 0)) 168 return; 169 radeon_bo_kunmap(rdev->wb.wb_obj); 170 radeon_bo_unpin(rdev->wb.wb_obj); 171 radeon_bo_unreserve(rdev->wb.wb_obj); 172 } 173 rdev->wb.enabled = false; 174 } 175 176 void radeon_wb_fini(struct radeon_device *rdev) 177 { 178 radeon_wb_disable(rdev); 179 if (rdev->wb.wb_obj) { 180 radeon_bo_unref(&rdev->wb.wb_obj); 181 rdev->wb.wb = NULL; 182 rdev->wb.wb_obj = NULL; 183 } 184 } 185 186 int radeon_wb_init(struct radeon_device *rdev) 187 { 188 int r; 189 190 if (rdev->wb.wb_obj == NULL) { 191 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true, 192 RADEON_GEM_DOMAIN_GTT, &rdev->wb.wb_obj); 193 if (r) { 194 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r); 195 return r; 196 } 197 } 198 r = radeon_bo_reserve(rdev->wb.wb_obj, false); 199 if (unlikely(r != 0)) { 200 radeon_wb_fini(rdev); 201 return r; 202 } 203 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT, 204 &rdev->wb.gpu_addr); 205 if (r) { 206 radeon_bo_unreserve(rdev->wb.wb_obj); 207 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r); 208 radeon_wb_fini(rdev); 209 return r; 210 } 211 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb); 212 radeon_bo_unreserve(rdev->wb.wb_obj); 213 if (r) { 214 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r); 215 radeon_wb_fini(rdev); 216 return r; 217 } 218 219 /* clear wb memory */ 220 memset((char *)rdev->wb.wb, 0, RADEON_GPU_PAGE_SIZE); 221 /* disable event_write fences */ 222 rdev->wb.use_event = false; 223 /* disabled via module param */ 224 if (radeon_no_wb == 1) 225 rdev->wb.enabled = false; 226 else { 227 if (rdev->flags & RADEON_IS_AGP) { 228 /* often unreliable on AGP */ 229 rdev->wb.enabled = false; 230 } else if (rdev->family < CHIP_R300) { 231 /* often unreliable on pre-r300 */ 232 rdev->wb.enabled = false; 233 } else { 234 rdev->wb.enabled = true; 235 /* event_write fences are only available on r600+ */ 236 if (rdev->family >= CHIP_R600) 237 rdev->wb.use_event = true; 238 } 239 } 240 /* always use writeback/events on NI */ 241 if (ASIC_IS_DCE5(rdev)) { 242 rdev->wb.enabled = true; 243 rdev->wb.use_event = true; 244 } 245 246 dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis"); 247 248 return 0; 249 } 250 251 /** 252 * radeon_vram_location - try to find VRAM location 253 * @rdev: radeon device structure holding all necessary informations 254 * @mc: memory controller structure holding memory informations 255 * @base: base address at which to put VRAM 256 * 257 * Function will place try to place VRAM at base address provided 258 * as parameter (which is so far either PCI aperture address or 259 * for IGP TOM base address). 260 * 261 * If there is not enough space to fit the unvisible VRAM in the 32bits 262 * address space then we limit the VRAM size to the aperture. 263 * 264 * If we are using AGP and if the AGP aperture doesn't allow us to have 265 * room for all the VRAM than we restrict the VRAM to the PCI aperture 266 * size and print a warning. 267 * 268 * This function will never fails, worst case are limiting VRAM. 269 * 270 * Note: GTT start, end, size should be initialized before calling this 271 * function on AGP platform. 272 * 273 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size, 274 * this shouldn't be a problem as we are using the PCI aperture as a reference. 275 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but 276 * not IGP. 277 * 278 * Note: we use mc_vram_size as on some board we need to program the mc to 279 * cover the whole aperture even if VRAM size is inferior to aperture size 280 * Novell bug 204882 + along with lots of ubuntu ones 281 * 282 * Note: when limiting vram it's safe to overwritte real_vram_size because 283 * we are not in case where real_vram_size is inferior to mc_vram_size (ie 284 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu 285 * ones) 286 * 287 * Note: IGP TOM addr should be the same as the aperture addr, we don't 288 * explicitly check for that thought. 289 * 290 * FIXME: when reducing VRAM size align new size on power of 2. 291 */ 292 void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base) 293 { 294 mc->vram_start = base; 295 if (mc->mc_vram_size > (0xFFFFFFFF - base + 1)) { 296 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); 297 mc->real_vram_size = mc->aper_size; 298 mc->mc_vram_size = mc->aper_size; 299 } 300 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 301 if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) { 302 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); 303 mc->real_vram_size = mc->aper_size; 304 mc->mc_vram_size = mc->aper_size; 305 } 306 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 307 if (radeon_vram_limit && radeon_vram_limit < mc->real_vram_size) 308 mc->real_vram_size = radeon_vram_limit; 309 dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", 310 mc->mc_vram_size >> 20, mc->vram_start, 311 mc->vram_end, mc->real_vram_size >> 20); 312 } 313 314 /** 315 * radeon_gtt_location - try to find GTT location 316 * @rdev: radeon device structure holding all necessary informations 317 * @mc: memory controller structure holding memory informations 318 * 319 * Function will place try to place GTT before or after VRAM. 320 * 321 * If GTT size is bigger than space left then we ajust GTT size. 322 * Thus function will never fails. 323 * 324 * FIXME: when reducing GTT size align new size on power of 2. 325 */ 326 void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) 327 { 328 u64 size_af, size_bf; 329 330 size_af = ((0xFFFFFFFF - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align; 331 size_bf = mc->vram_start & ~mc->gtt_base_align; 332 if (size_bf > size_af) { 333 if (mc->gtt_size > size_bf) { 334 dev_warn(rdev->dev, "limiting GTT\n"); 335 mc->gtt_size = size_bf; 336 } 337 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size; 338 } else { 339 if (mc->gtt_size > size_af) { 340 dev_warn(rdev->dev, "limiting GTT\n"); 341 mc->gtt_size = size_af; 342 } 343 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align; 344 } 345 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1; 346 dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n", 347 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end); 348 } 349 350 /* 351 * GPU helpers function. 352 */ 353 bool radeon_card_posted(struct radeon_device *rdev) 354 { 355 uint32_t reg; 356 357 if (efi_enabled && rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) 358 return false; 359 360 /* first check CRTCs */ 361 if (ASIC_IS_DCE41(rdev)) { 362 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | 363 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); 364 if (reg & EVERGREEN_CRTC_MASTER_EN) 365 return true; 366 } else if (ASIC_IS_DCE4(rdev)) { 367 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | 368 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) | 369 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) | 370 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) | 371 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) | 372 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); 373 if (reg & EVERGREEN_CRTC_MASTER_EN) 374 return true; 375 } else if (ASIC_IS_AVIVO(rdev)) { 376 reg = RREG32(AVIVO_D1CRTC_CONTROL) | 377 RREG32(AVIVO_D2CRTC_CONTROL); 378 if (reg & AVIVO_CRTC_EN) { 379 return true; 380 } 381 } else { 382 reg = RREG32(RADEON_CRTC_GEN_CNTL) | 383 RREG32(RADEON_CRTC2_GEN_CNTL); 384 if (reg & RADEON_CRTC_EN) { 385 return true; 386 } 387 } 388 389 /* then check MEM_SIZE, in case the crtcs are off */ 390 if (rdev->family >= CHIP_R600) 391 reg = RREG32(R600_CONFIG_MEMSIZE); 392 else 393 reg = RREG32(RADEON_CONFIG_MEMSIZE); 394 395 if (reg) 396 return true; 397 398 return false; 399 400 } 401 402 void radeon_update_bandwidth_info(struct radeon_device *rdev) 403 { 404 fixed20_12 a; 405 u32 sclk = rdev->pm.current_sclk; 406 u32 mclk = rdev->pm.current_mclk; 407 408 /* sclk/mclk in Mhz */ 409 a.full = dfixed_const(100); 410 rdev->pm.sclk.full = dfixed_const(sclk); 411 rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a); 412 rdev->pm.mclk.full = dfixed_const(mclk); 413 rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a); 414 415 if (rdev->flags & RADEON_IS_IGP) { 416 a.full = dfixed_const(16); 417 /* core_bandwidth = sclk(Mhz) * 16 */ 418 rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a); 419 } 420 } 421 422 bool radeon_boot_test_post_card(struct radeon_device *rdev) 423 { 424 if (radeon_card_posted(rdev)) 425 return true; 426 427 if (rdev->bios) { 428 DRM_INFO("GPU not posted. posting now...\n"); 429 if (rdev->is_atom_bios) 430 atom_asic_init(rdev->mode_info.atom_context); 431 else 432 radeon_combios_asic_init(rdev->ddev); 433 return true; 434 } else { 435 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); 436 return false; 437 } 438 } 439 440 int radeon_dummy_page_init(struct radeon_device *rdev) 441 { 442 if (rdev->dummy_page.page) 443 return 0; 444 rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO); 445 if (rdev->dummy_page.page == NULL) 446 return -ENOMEM; 447 rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page, 448 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 449 if (pci_dma_mapping_error(rdev->pdev, rdev->dummy_page.addr)) { 450 dev_err(&rdev->pdev->dev, "Failed to DMA MAP the dummy page\n"); 451 __free_page(rdev->dummy_page.page); 452 rdev->dummy_page.page = NULL; 453 return -ENOMEM; 454 } 455 return 0; 456 } 457 458 void radeon_dummy_page_fini(struct radeon_device *rdev) 459 { 460 if (rdev->dummy_page.page == NULL) 461 return; 462 pci_unmap_page(rdev->pdev, rdev->dummy_page.addr, 463 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 464 __free_page(rdev->dummy_page.page); 465 rdev->dummy_page.page = NULL; 466 } 467 468 469 /* ATOM accessor methods */ 470 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) 471 { 472 struct radeon_device *rdev = info->dev->dev_private; 473 uint32_t r; 474 475 r = rdev->pll_rreg(rdev, reg); 476 return r; 477 } 478 479 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) 480 { 481 struct radeon_device *rdev = info->dev->dev_private; 482 483 rdev->pll_wreg(rdev, reg, val); 484 } 485 486 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) 487 { 488 struct radeon_device *rdev = info->dev->dev_private; 489 uint32_t r; 490 491 r = rdev->mc_rreg(rdev, reg); 492 return r; 493 } 494 495 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) 496 { 497 struct radeon_device *rdev = info->dev->dev_private; 498 499 rdev->mc_wreg(rdev, reg, val); 500 } 501 502 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) 503 { 504 struct radeon_device *rdev = info->dev->dev_private; 505 506 WREG32(reg*4, val); 507 } 508 509 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) 510 { 511 struct radeon_device *rdev = info->dev->dev_private; 512 uint32_t r; 513 514 r = RREG32(reg*4); 515 return r; 516 } 517 518 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val) 519 { 520 struct radeon_device *rdev = info->dev->dev_private; 521 522 WREG32_IO(reg*4, val); 523 } 524 525 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg) 526 { 527 struct radeon_device *rdev = info->dev->dev_private; 528 uint32_t r; 529 530 r = RREG32_IO(reg*4); 531 return r; 532 } 533 534 int radeon_atombios_init(struct radeon_device *rdev) 535 { 536 struct card_info *atom_card_info = 537 kzalloc(sizeof(struct card_info), GFP_KERNEL); 538 539 if (!atom_card_info) 540 return -ENOMEM; 541 542 rdev->mode_info.atom_card_info = atom_card_info; 543 atom_card_info->dev = rdev->ddev; 544 atom_card_info->reg_read = cail_reg_read; 545 atom_card_info->reg_write = cail_reg_write; 546 /* needed for iio ops */ 547 if (rdev->rio_mem) { 548 atom_card_info->ioreg_read = cail_ioreg_read; 549 atom_card_info->ioreg_write = cail_ioreg_write; 550 } else { 551 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n"); 552 atom_card_info->ioreg_read = cail_reg_read; 553 atom_card_info->ioreg_write = cail_reg_write; 554 } 555 atom_card_info->mc_read = cail_mc_read; 556 atom_card_info->mc_write = cail_mc_write; 557 atom_card_info->pll_read = cail_pll_read; 558 atom_card_info->pll_write = cail_pll_write; 559 560 rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios); 561 mutex_init(&rdev->mode_info.atom_context->mutex); 562 radeon_atom_initialize_bios_scratch_regs(rdev->ddev); 563 atom_allocate_fb_scratch(rdev->mode_info.atom_context); 564 return 0; 565 } 566 567 void radeon_atombios_fini(struct radeon_device *rdev) 568 { 569 if (rdev->mode_info.atom_context) { 570 kfree(rdev->mode_info.atom_context->scratch); 571 kfree(rdev->mode_info.atom_context); 572 } 573 kfree(rdev->mode_info.atom_card_info); 574 } 575 576 int radeon_combios_init(struct radeon_device *rdev) 577 { 578 radeon_combios_initialize_bios_scratch_regs(rdev->ddev); 579 return 0; 580 } 581 582 void radeon_combios_fini(struct radeon_device *rdev) 583 { 584 } 585 586 /* if we get transitioned to only one device, tak VGA back */ 587 static unsigned int radeon_vga_set_decode(void *cookie, bool state) 588 { 589 struct radeon_device *rdev = cookie; 590 radeon_vga_set_state(rdev, state); 591 if (state) 592 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | 593 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; 594 else 595 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; 596 } 597 598 void radeon_check_arguments(struct radeon_device *rdev) 599 { 600 /* vramlimit must be a power of two */ 601 switch (radeon_vram_limit) { 602 case 0: 603 case 4: 604 case 8: 605 case 16: 606 case 32: 607 case 64: 608 case 128: 609 case 256: 610 case 512: 611 case 1024: 612 case 2048: 613 case 4096: 614 break; 615 default: 616 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n", 617 radeon_vram_limit); 618 radeon_vram_limit = 0; 619 break; 620 } 621 radeon_vram_limit = radeon_vram_limit << 20; 622 /* gtt size must be power of two and greater or equal to 32M */ 623 switch (radeon_gart_size) { 624 case 4: 625 case 8: 626 case 16: 627 dev_warn(rdev->dev, "gart size (%d) too small forcing to 512M\n", 628 radeon_gart_size); 629 radeon_gart_size = 512; 630 break; 631 case 32: 632 case 64: 633 case 128: 634 case 256: 635 case 512: 636 case 1024: 637 case 2048: 638 case 4096: 639 break; 640 default: 641 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n", 642 radeon_gart_size); 643 radeon_gart_size = 512; 644 break; 645 } 646 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; 647 /* AGP mode can only be -1, 1, 2, 4, 8 */ 648 switch (radeon_agpmode) { 649 case -1: 650 case 0: 651 case 1: 652 case 2: 653 case 4: 654 case 8: 655 break; 656 default: 657 dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: " 658 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode); 659 radeon_agpmode = 0; 660 break; 661 } 662 } 663 664 static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) 665 { 666 struct drm_device *dev = pci_get_drvdata(pdev); 667 pm_message_t pmm = { .event = PM_EVENT_SUSPEND }; 668 if (state == VGA_SWITCHEROO_ON) { 669 printk(KERN_INFO "radeon: switched on\n"); 670 /* don't suspend or resume card normally */ 671 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 672 radeon_resume_kms(dev); 673 dev->switch_power_state = DRM_SWITCH_POWER_ON; 674 drm_kms_helper_poll_enable(dev); 675 } else { 676 printk(KERN_INFO "radeon: switched off\n"); 677 drm_kms_helper_poll_disable(dev); 678 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 679 radeon_suspend_kms(dev, pmm); 680 dev->switch_power_state = DRM_SWITCH_POWER_OFF; 681 } 682 } 683 684 static bool radeon_switcheroo_can_switch(struct pci_dev *pdev) 685 { 686 struct drm_device *dev = pci_get_drvdata(pdev); 687 bool can_switch; 688 689 spin_lock(&dev->count_lock); 690 can_switch = (dev->open_count == 0); 691 spin_unlock(&dev->count_lock); 692 return can_switch; 693 } 694 695 696 int radeon_device_init(struct radeon_device *rdev, 697 struct drm_device *ddev, 698 struct pci_dev *pdev, 699 uint32_t flags) 700 { 701 int r, i; 702 int dma_bits; 703 704 rdev->shutdown = false; 705 rdev->dev = &pdev->dev; 706 rdev->ddev = ddev; 707 rdev->pdev = pdev; 708 rdev->flags = flags; 709 rdev->family = flags & RADEON_FAMILY_MASK; 710 rdev->is_atom_bios = false; 711 rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT; 712 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; 713 rdev->gpu_lockup = false; 714 rdev->accel_working = false; 715 716 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n", 717 radeon_family_name[rdev->family], pdev->vendor, pdev->device, 718 pdev->subsystem_vendor, pdev->subsystem_device); 719 720 /* mutex initialization are all done here so we 721 * can recall function without having locking issues */ 722 radeon_mutex_init(&rdev->cs_mutex); 723 mutex_init(&rdev->ib_pool.mutex); 724 for (i = 0; i < RADEON_NUM_RINGS; ++i) 725 mutex_init(&rdev->ring[i].mutex); 726 mutex_init(&rdev->dc_hw_i2c_mutex); 727 if (rdev->family >= CHIP_R600) 728 spin_lock_init(&rdev->ih.lock); 729 mutex_init(&rdev->gem.mutex); 730 mutex_init(&rdev->pm.mutex); 731 mutex_init(&rdev->vram_mutex); 732 rwlock_init(&rdev->fence_lock); 733 rwlock_init(&rdev->semaphore_drv.lock); 734 INIT_LIST_HEAD(&rdev->gem.objects); 735 init_waitqueue_head(&rdev->irq.vblank_queue); 736 init_waitqueue_head(&rdev->irq.idle_queue); 737 INIT_LIST_HEAD(&rdev->semaphore_drv.bo); 738 /* initialize vm here */ 739 rdev->vm_manager.use_bitmap = 1; 740 rdev->vm_manager.max_pfn = 1 << 20; 741 INIT_LIST_HEAD(&rdev->vm_manager.lru_vm); 742 743 /* Set asic functions */ 744 r = radeon_asic_init(rdev); 745 if (r) 746 return r; 747 radeon_check_arguments(rdev); 748 749 /* all of the newer IGP chips have an internal gart 750 * However some rs4xx report as AGP, so remove that here. 751 */ 752 if ((rdev->family >= CHIP_RS400) && 753 (rdev->flags & RADEON_IS_IGP)) { 754 rdev->flags &= ~RADEON_IS_AGP; 755 } 756 757 if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) { 758 radeon_agp_disable(rdev); 759 } 760 761 /* set DMA mask + need_dma32 flags. 762 * PCIE - can handle 40-bits. 763 * IGP - can handle 40-bits 764 * AGP - generally dma32 is safest 765 * PCI - dma32 for legacy pci gart, 40 bits on newer asics 766 */ 767 rdev->need_dma32 = false; 768 if (rdev->flags & RADEON_IS_AGP) 769 rdev->need_dma32 = true; 770 if ((rdev->flags & RADEON_IS_PCI) && 771 (rdev->family < CHIP_RS400)) 772 rdev->need_dma32 = true; 773 774 dma_bits = rdev->need_dma32 ? 32 : 40; 775 r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits)); 776 if (r) { 777 rdev->need_dma32 = true; 778 dma_bits = 32; 779 printk(KERN_WARNING "radeon: No suitable DMA available.\n"); 780 } 781 r = pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits)); 782 if (r) { 783 pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(32)); 784 printk(KERN_WARNING "radeon: No coherent DMA available.\n"); 785 } 786 787 /* Registers mapping */ 788 /* TODO: block userspace mapping of io register */ 789 rdev->rmmio_base = pci_resource_start(rdev->pdev, 2); 790 rdev->rmmio_size = pci_resource_len(rdev->pdev, 2); 791 rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size); 792 if (rdev->rmmio == NULL) { 793 return -ENOMEM; 794 } 795 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base); 796 DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size); 797 798 /* io port mapping */ 799 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 800 if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) { 801 rdev->rio_mem_size = pci_resource_len(rdev->pdev, i); 802 rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size); 803 break; 804 } 805 } 806 if (rdev->rio_mem == NULL) 807 DRM_ERROR("Unable to find PCI I/O BAR\n"); 808 809 /* if we have > 1 VGA cards, then disable the radeon VGA resources */ 810 /* this will fail for cards that aren't VGA class devices, just 811 * ignore it */ 812 vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode); 813 vga_switcheroo_register_client(rdev->pdev, 814 radeon_switcheroo_set_state, 815 NULL, 816 radeon_switcheroo_can_switch); 817 818 r = radeon_init(rdev); 819 if (r) 820 return r; 821 822 if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) { 823 /* Acceleration not working on AGP card try again 824 * with fallback to PCI or PCIE GART 825 */ 826 radeon_asic_reset(rdev); 827 radeon_fini(rdev); 828 radeon_agp_disable(rdev); 829 r = radeon_init(rdev); 830 if (r) 831 return r; 832 } 833 if ((radeon_testing & 1)) { 834 radeon_test_moves(rdev); 835 } 836 if ((radeon_testing & 2)) { 837 radeon_test_syncing(rdev); 838 } 839 if (radeon_benchmarking) { 840 radeon_benchmark(rdev, radeon_benchmarking); 841 } 842 return 0; 843 } 844 845 static void radeon_debugfs_remove_files(struct radeon_device *rdev); 846 847 void radeon_device_fini(struct radeon_device *rdev) 848 { 849 DRM_INFO("radeon: finishing device.\n"); 850 rdev->shutdown = true; 851 /* evict vram memory */ 852 radeon_bo_evict_vram(rdev); 853 radeon_fini(rdev); 854 vga_switcheroo_unregister_client(rdev->pdev); 855 vga_client_register(rdev->pdev, NULL, NULL, NULL); 856 if (rdev->rio_mem) 857 pci_iounmap(rdev->pdev, rdev->rio_mem); 858 rdev->rio_mem = NULL; 859 iounmap(rdev->rmmio); 860 rdev->rmmio = NULL; 861 radeon_debugfs_remove_files(rdev); 862 } 863 864 865 /* 866 * Suspend & resume. 867 */ 868 int radeon_suspend_kms(struct drm_device *dev, pm_message_t state) 869 { 870 struct radeon_device *rdev; 871 struct drm_crtc *crtc; 872 struct drm_connector *connector; 873 int i, r; 874 875 if (dev == NULL || dev->dev_private == NULL) { 876 return -ENODEV; 877 } 878 if (state.event == PM_EVENT_PRETHAW) { 879 return 0; 880 } 881 rdev = dev->dev_private; 882 883 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) 884 return 0; 885 886 /* turn off display hw */ 887 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 888 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); 889 } 890 891 /* unpin the front buffers */ 892 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 893 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb); 894 struct radeon_bo *robj; 895 896 if (rfb == NULL || rfb->obj == NULL) { 897 continue; 898 } 899 robj = gem_to_radeon_bo(rfb->obj); 900 /* don't unpin kernel fb objects */ 901 if (!radeon_fbdev_robj_is_fb(rdev, robj)) { 902 r = radeon_bo_reserve(robj, false); 903 if (r == 0) { 904 radeon_bo_unpin(robj); 905 radeon_bo_unreserve(robj); 906 } 907 } 908 } 909 /* evict vram memory */ 910 radeon_bo_evict_vram(rdev); 911 /* wait for gpu to finish processing current batch */ 912 for (i = 0; i < RADEON_NUM_RINGS; i++) 913 radeon_fence_wait_last(rdev, i); 914 915 radeon_save_bios_scratch_regs(rdev); 916 917 radeon_pm_suspend(rdev); 918 radeon_suspend(rdev); 919 radeon_hpd_fini(rdev); 920 /* evict remaining vram memory */ 921 radeon_bo_evict_vram(rdev); 922 923 radeon_agp_suspend(rdev); 924 925 pci_save_state(dev->pdev); 926 if (state.event == PM_EVENT_SUSPEND) { 927 /* Shut down the device */ 928 pci_disable_device(dev->pdev); 929 pci_set_power_state(dev->pdev, PCI_D3hot); 930 } 931 console_lock(); 932 radeon_fbdev_set_suspend(rdev, 1); 933 console_unlock(); 934 return 0; 935 } 936 937 int radeon_resume_kms(struct drm_device *dev) 938 { 939 struct drm_connector *connector; 940 struct radeon_device *rdev = dev->dev_private; 941 942 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) 943 return 0; 944 945 console_lock(); 946 pci_set_power_state(dev->pdev, PCI_D0); 947 pci_restore_state(dev->pdev); 948 if (pci_enable_device(dev->pdev)) { 949 console_unlock(); 950 return -1; 951 } 952 pci_set_master(dev->pdev); 953 /* resume AGP if in use */ 954 radeon_agp_resume(rdev); 955 radeon_resume(rdev); 956 radeon_pm_resume(rdev); 957 radeon_restore_bios_scratch_regs(rdev); 958 959 radeon_fbdev_set_suspend(rdev, 0); 960 console_unlock(); 961 962 /* init dig PHYs */ 963 if (rdev->is_atom_bios) 964 radeon_atom_encoder_init(rdev); 965 /* reset hpd state */ 966 radeon_hpd_init(rdev); 967 /* blat the mode back in */ 968 drm_helper_resume_force_mode(dev); 969 /* turn on display hw */ 970 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 971 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); 972 } 973 return 0; 974 } 975 976 int radeon_gpu_reset(struct radeon_device *rdev) 977 { 978 int r; 979 int resched; 980 981 /* Prevent CS ioctl from interfering */ 982 radeon_mutex_lock(&rdev->cs_mutex); 983 984 radeon_save_bios_scratch_regs(rdev); 985 /* block TTM */ 986 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev); 987 radeon_suspend(rdev); 988 989 r = radeon_asic_reset(rdev); 990 if (!r) { 991 dev_info(rdev->dev, "GPU reset succeed\n"); 992 radeon_resume(rdev); 993 radeon_restore_bios_scratch_regs(rdev); 994 drm_helper_resume_force_mode(rdev->ddev); 995 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched); 996 } 997 998 radeon_mutex_unlock(&rdev->cs_mutex); 999 1000 if (r) { 1001 /* bad news, how to tell it to userspace ? */ 1002 dev_info(rdev->dev, "GPU reset failed\n"); 1003 } 1004 1005 return r; 1006 } 1007 1008 1009 /* 1010 * Debugfs 1011 */ 1012 int radeon_debugfs_add_files(struct radeon_device *rdev, 1013 struct drm_info_list *files, 1014 unsigned nfiles) 1015 { 1016 unsigned i; 1017 1018 for (i = 0; i < rdev->debugfs_count; i++) { 1019 if (rdev->debugfs[i].files == files) { 1020 /* Already registered */ 1021 return 0; 1022 } 1023 } 1024 1025 i = rdev->debugfs_count + 1; 1026 if (i > RADEON_DEBUGFS_MAX_COMPONENTS) { 1027 DRM_ERROR("Reached maximum number of debugfs components.\n"); 1028 DRM_ERROR("Report so we increase " 1029 "RADEON_DEBUGFS_MAX_COMPONENTS.\n"); 1030 return -EINVAL; 1031 } 1032 rdev->debugfs[rdev->debugfs_count].files = files; 1033 rdev->debugfs[rdev->debugfs_count].num_files = nfiles; 1034 rdev->debugfs_count = i; 1035 #if defined(CONFIG_DEBUG_FS) 1036 drm_debugfs_create_files(files, nfiles, 1037 rdev->ddev->control->debugfs_root, 1038 rdev->ddev->control); 1039 drm_debugfs_create_files(files, nfiles, 1040 rdev->ddev->primary->debugfs_root, 1041 rdev->ddev->primary); 1042 #endif 1043 return 0; 1044 } 1045 1046 static void radeon_debugfs_remove_files(struct radeon_device *rdev) 1047 { 1048 #if defined(CONFIG_DEBUG_FS) 1049 unsigned i; 1050 1051 for (i = 0; i < rdev->debugfs_count; i++) { 1052 drm_debugfs_remove_files(rdev->debugfs[i].files, 1053 rdev->debugfs[i].num_files, 1054 rdev->ddev->control); 1055 drm_debugfs_remove_files(rdev->debugfs[i].files, 1056 rdev->debugfs[i].num_files, 1057 rdev->ddev->primary); 1058 } 1059 #endif 1060 } 1061 1062 #if defined(CONFIG_DEBUG_FS) 1063 int radeon_debugfs_init(struct drm_minor *minor) 1064 { 1065 return 0; 1066 } 1067 1068 void radeon_debugfs_cleanup(struct drm_minor *minor) 1069 { 1070 } 1071 #endif 1072