1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/console.h> 29 #include <linux/slab.h> 30 #include <drm/drmP.h> 31 #include <drm/drm_crtc_helper.h> 32 #include <drm/radeon_drm.h> 33 #include <linux/vgaarb.h> 34 #include <linux/vga_switcheroo.h> 35 #include "radeon_reg.h" 36 #include "radeon.h" 37 #include "atom.h" 38 39 static const char radeon_family_name[][16] = { 40 "R100", 41 "RV100", 42 "RS100", 43 "RV200", 44 "RS200", 45 "R200", 46 "RV250", 47 "RS300", 48 "RV280", 49 "R300", 50 "R350", 51 "RV350", 52 "RV380", 53 "R420", 54 "R423", 55 "RV410", 56 "RS400", 57 "RS480", 58 "RS600", 59 "RS690", 60 "RS740", 61 "RV515", 62 "R520", 63 "RV530", 64 "RV560", 65 "RV570", 66 "R580", 67 "R600", 68 "RV610", 69 "RV630", 70 "RV670", 71 "RV620", 72 "RV635", 73 "RS780", 74 "RS880", 75 "RV770", 76 "RV730", 77 "RV710", 78 "RV740", 79 "CEDAR", 80 "REDWOOD", 81 "JUNIPER", 82 "CYPRESS", 83 "HEMLOCK", 84 "LAST", 85 }; 86 87 /* 88 * Clear GPU surface registers. 89 */ 90 void radeon_surface_init(struct radeon_device *rdev) 91 { 92 /* FIXME: check this out */ 93 if (rdev->family < CHIP_R600) { 94 int i; 95 96 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { 97 if (rdev->surface_regs[i].bo) 98 radeon_bo_get_surface_reg(rdev->surface_regs[i].bo); 99 else 100 radeon_clear_surface_reg(rdev, i); 101 } 102 /* enable surfaces */ 103 WREG32(RADEON_SURFACE_CNTL, 0); 104 } 105 } 106 107 /* 108 * GPU scratch registers helpers function. 109 */ 110 void radeon_scratch_init(struct radeon_device *rdev) 111 { 112 int i; 113 114 /* FIXME: check this out */ 115 if (rdev->family < CHIP_R300) { 116 rdev->scratch.num_reg = 5; 117 } else { 118 rdev->scratch.num_reg = 7; 119 } 120 for (i = 0; i < rdev->scratch.num_reg; i++) { 121 rdev->scratch.free[i] = true; 122 rdev->scratch.reg[i] = RADEON_SCRATCH_REG0 + (i * 4); 123 } 124 } 125 126 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg) 127 { 128 int i; 129 130 for (i = 0; i < rdev->scratch.num_reg; i++) { 131 if (rdev->scratch.free[i]) { 132 rdev->scratch.free[i] = false; 133 *reg = rdev->scratch.reg[i]; 134 return 0; 135 } 136 } 137 return -EINVAL; 138 } 139 140 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg) 141 { 142 int i; 143 144 for (i = 0; i < rdev->scratch.num_reg; i++) { 145 if (rdev->scratch.reg[i] == reg) { 146 rdev->scratch.free[i] = true; 147 return; 148 } 149 } 150 } 151 152 /** 153 * radeon_vram_location - try to find VRAM location 154 * @rdev: radeon device structure holding all necessary informations 155 * @mc: memory controller structure holding memory informations 156 * @base: base address at which to put VRAM 157 * 158 * Function will place try to place VRAM at base address provided 159 * as parameter (which is so far either PCI aperture address or 160 * for IGP TOM base address). 161 * 162 * If there is not enough space to fit the unvisible VRAM in the 32bits 163 * address space then we limit the VRAM size to the aperture. 164 * 165 * If we are using AGP and if the AGP aperture doesn't allow us to have 166 * room for all the VRAM than we restrict the VRAM to the PCI aperture 167 * size and print a warning. 168 * 169 * This function will never fails, worst case are limiting VRAM. 170 * 171 * Note: GTT start, end, size should be initialized before calling this 172 * function on AGP platform. 173 * 174 * Note: We don't explictly enforce VRAM start to be aligned on VRAM size, 175 * this shouldn't be a problem as we are using the PCI aperture as a reference. 176 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but 177 * not IGP. 178 * 179 * Note: we use mc_vram_size as on some board we need to program the mc to 180 * cover the whole aperture even if VRAM size is inferior to aperture size 181 * Novell bug 204882 + along with lots of ubuntu ones 182 * 183 * Note: when limiting vram it's safe to overwritte real_vram_size because 184 * we are not in case where real_vram_size is inferior to mc_vram_size (ie 185 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu 186 * ones) 187 * 188 * Note: IGP TOM addr should be the same as the aperture addr, we don't 189 * explicitly check for that thought. 190 * 191 * FIXME: when reducing VRAM size align new size on power of 2. 192 */ 193 void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base) 194 { 195 mc->vram_start = base; 196 if (mc->mc_vram_size > (0xFFFFFFFF - base + 1)) { 197 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); 198 mc->real_vram_size = mc->aper_size; 199 mc->mc_vram_size = mc->aper_size; 200 } 201 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 202 if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_end <= mc->gtt_end) { 203 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); 204 mc->real_vram_size = mc->aper_size; 205 mc->mc_vram_size = mc->aper_size; 206 } 207 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 208 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n", 209 mc->mc_vram_size >> 20, mc->vram_start, 210 mc->vram_end, mc->real_vram_size >> 20); 211 } 212 213 /** 214 * radeon_gtt_location - try to find GTT location 215 * @rdev: radeon device structure holding all necessary informations 216 * @mc: memory controller structure holding memory informations 217 * 218 * Function will place try to place GTT before or after VRAM. 219 * 220 * If GTT size is bigger than space left then we ajust GTT size. 221 * Thus function will never fails. 222 * 223 * FIXME: when reducing GTT size align new size on power of 2. 224 */ 225 void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) 226 { 227 u64 size_af, size_bf; 228 229 size_af = ((0xFFFFFFFF - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align; 230 size_bf = mc->vram_start & ~mc->gtt_base_align; 231 if (size_bf > size_af) { 232 if (mc->gtt_size > size_bf) { 233 dev_warn(rdev->dev, "limiting GTT\n"); 234 mc->gtt_size = size_bf; 235 } 236 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size; 237 } else { 238 if (mc->gtt_size > size_af) { 239 dev_warn(rdev->dev, "limiting GTT\n"); 240 mc->gtt_size = size_af; 241 } 242 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align; 243 } 244 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1; 245 dev_info(rdev->dev, "GTT: %lluM 0x%08llX - 0x%08llX\n", 246 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end); 247 } 248 249 /* 250 * GPU helpers function. 251 */ 252 bool radeon_card_posted(struct radeon_device *rdev) 253 { 254 uint32_t reg; 255 256 /* first check CRTCs */ 257 if (ASIC_IS_DCE4(rdev)) { 258 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | 259 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) | 260 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) | 261 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) | 262 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) | 263 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); 264 if (reg & EVERGREEN_CRTC_MASTER_EN) 265 return true; 266 } else if (ASIC_IS_AVIVO(rdev)) { 267 reg = RREG32(AVIVO_D1CRTC_CONTROL) | 268 RREG32(AVIVO_D2CRTC_CONTROL); 269 if (reg & AVIVO_CRTC_EN) { 270 return true; 271 } 272 } else { 273 reg = RREG32(RADEON_CRTC_GEN_CNTL) | 274 RREG32(RADEON_CRTC2_GEN_CNTL); 275 if (reg & RADEON_CRTC_EN) { 276 return true; 277 } 278 } 279 280 /* then check MEM_SIZE, in case the crtcs are off */ 281 if (rdev->family >= CHIP_R600) 282 reg = RREG32(R600_CONFIG_MEMSIZE); 283 else 284 reg = RREG32(RADEON_CONFIG_MEMSIZE); 285 286 if (reg) 287 return true; 288 289 return false; 290 291 } 292 293 void radeon_update_bandwidth_info(struct radeon_device *rdev) 294 { 295 fixed20_12 a; 296 u32 sclk, mclk; 297 298 if (rdev->flags & RADEON_IS_IGP) { 299 sclk = radeon_get_engine_clock(rdev); 300 mclk = rdev->clock.default_mclk; 301 302 a.full = dfixed_const(100); 303 rdev->pm.sclk.full = dfixed_const(sclk); 304 rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a); 305 rdev->pm.mclk.full = dfixed_const(mclk); 306 rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a); 307 308 a.full = dfixed_const(16); 309 /* core_bandwidth = sclk(Mhz) * 16 */ 310 rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a); 311 } else { 312 sclk = radeon_get_engine_clock(rdev); 313 mclk = radeon_get_memory_clock(rdev); 314 315 a.full = dfixed_const(100); 316 rdev->pm.sclk.full = dfixed_const(sclk); 317 rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a); 318 rdev->pm.mclk.full = dfixed_const(mclk); 319 rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a); 320 } 321 } 322 323 bool radeon_boot_test_post_card(struct radeon_device *rdev) 324 { 325 if (radeon_card_posted(rdev)) 326 return true; 327 328 if (rdev->bios) { 329 DRM_INFO("GPU not posted. posting now...\n"); 330 if (rdev->is_atom_bios) 331 atom_asic_init(rdev->mode_info.atom_context); 332 else 333 radeon_combios_asic_init(rdev->ddev); 334 return true; 335 } else { 336 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); 337 return false; 338 } 339 } 340 341 int radeon_dummy_page_init(struct radeon_device *rdev) 342 { 343 if (rdev->dummy_page.page) 344 return 0; 345 rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO); 346 if (rdev->dummy_page.page == NULL) 347 return -ENOMEM; 348 rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page, 349 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 350 if (pci_dma_mapping_error(rdev->pdev, rdev->dummy_page.addr)) { 351 dev_err(&rdev->pdev->dev, "Failed to DMA MAP the dummy page\n"); 352 __free_page(rdev->dummy_page.page); 353 rdev->dummy_page.page = NULL; 354 return -ENOMEM; 355 } 356 return 0; 357 } 358 359 void radeon_dummy_page_fini(struct radeon_device *rdev) 360 { 361 if (rdev->dummy_page.page == NULL) 362 return; 363 pci_unmap_page(rdev->pdev, rdev->dummy_page.addr, 364 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 365 __free_page(rdev->dummy_page.page); 366 rdev->dummy_page.page = NULL; 367 } 368 369 370 /* ATOM accessor methods */ 371 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) 372 { 373 struct radeon_device *rdev = info->dev->dev_private; 374 uint32_t r; 375 376 r = rdev->pll_rreg(rdev, reg); 377 return r; 378 } 379 380 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) 381 { 382 struct radeon_device *rdev = info->dev->dev_private; 383 384 rdev->pll_wreg(rdev, reg, val); 385 } 386 387 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) 388 { 389 struct radeon_device *rdev = info->dev->dev_private; 390 uint32_t r; 391 392 r = rdev->mc_rreg(rdev, reg); 393 return r; 394 } 395 396 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) 397 { 398 struct radeon_device *rdev = info->dev->dev_private; 399 400 rdev->mc_wreg(rdev, reg, val); 401 } 402 403 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) 404 { 405 struct radeon_device *rdev = info->dev->dev_private; 406 407 WREG32(reg*4, val); 408 } 409 410 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) 411 { 412 struct radeon_device *rdev = info->dev->dev_private; 413 uint32_t r; 414 415 r = RREG32(reg*4); 416 return r; 417 } 418 419 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val) 420 { 421 struct radeon_device *rdev = info->dev->dev_private; 422 423 WREG32_IO(reg*4, val); 424 } 425 426 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg) 427 { 428 struct radeon_device *rdev = info->dev->dev_private; 429 uint32_t r; 430 431 r = RREG32_IO(reg*4); 432 return r; 433 } 434 435 int radeon_atombios_init(struct radeon_device *rdev) 436 { 437 struct card_info *atom_card_info = 438 kzalloc(sizeof(struct card_info), GFP_KERNEL); 439 440 if (!atom_card_info) 441 return -ENOMEM; 442 443 rdev->mode_info.atom_card_info = atom_card_info; 444 atom_card_info->dev = rdev->ddev; 445 atom_card_info->reg_read = cail_reg_read; 446 atom_card_info->reg_write = cail_reg_write; 447 /* needed for iio ops */ 448 if (rdev->rio_mem) { 449 atom_card_info->ioreg_read = cail_ioreg_read; 450 atom_card_info->ioreg_write = cail_ioreg_write; 451 } else { 452 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n"); 453 atom_card_info->ioreg_read = cail_reg_read; 454 atom_card_info->ioreg_write = cail_reg_write; 455 } 456 atom_card_info->mc_read = cail_mc_read; 457 atom_card_info->mc_write = cail_mc_write; 458 atom_card_info->pll_read = cail_pll_read; 459 atom_card_info->pll_write = cail_pll_write; 460 461 rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios); 462 mutex_init(&rdev->mode_info.atom_context->mutex); 463 radeon_atom_initialize_bios_scratch_regs(rdev->ddev); 464 atom_allocate_fb_scratch(rdev->mode_info.atom_context); 465 return 0; 466 } 467 468 void radeon_atombios_fini(struct radeon_device *rdev) 469 { 470 if (rdev->mode_info.atom_context) { 471 kfree(rdev->mode_info.atom_context->scratch); 472 kfree(rdev->mode_info.atom_context); 473 } 474 kfree(rdev->mode_info.atom_card_info); 475 } 476 477 int radeon_combios_init(struct radeon_device *rdev) 478 { 479 radeon_combios_initialize_bios_scratch_regs(rdev->ddev); 480 return 0; 481 } 482 483 void radeon_combios_fini(struct radeon_device *rdev) 484 { 485 } 486 487 /* if we get transitioned to only one device, tak VGA back */ 488 static unsigned int radeon_vga_set_decode(void *cookie, bool state) 489 { 490 struct radeon_device *rdev = cookie; 491 radeon_vga_set_state(rdev, state); 492 if (state) 493 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | 494 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; 495 else 496 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; 497 } 498 499 void radeon_check_arguments(struct radeon_device *rdev) 500 { 501 /* vramlimit must be a power of two */ 502 switch (radeon_vram_limit) { 503 case 0: 504 case 4: 505 case 8: 506 case 16: 507 case 32: 508 case 64: 509 case 128: 510 case 256: 511 case 512: 512 case 1024: 513 case 2048: 514 case 4096: 515 break; 516 default: 517 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n", 518 radeon_vram_limit); 519 radeon_vram_limit = 0; 520 break; 521 } 522 radeon_vram_limit = radeon_vram_limit << 20; 523 /* gtt size must be power of two and greater or equal to 32M */ 524 switch (radeon_gart_size) { 525 case 4: 526 case 8: 527 case 16: 528 dev_warn(rdev->dev, "gart size (%d) too small forcing to 512M\n", 529 radeon_gart_size); 530 radeon_gart_size = 512; 531 break; 532 case 32: 533 case 64: 534 case 128: 535 case 256: 536 case 512: 537 case 1024: 538 case 2048: 539 case 4096: 540 break; 541 default: 542 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n", 543 radeon_gart_size); 544 radeon_gart_size = 512; 545 break; 546 } 547 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; 548 /* AGP mode can only be -1, 1, 2, 4, 8 */ 549 switch (radeon_agpmode) { 550 case -1: 551 case 0: 552 case 1: 553 case 2: 554 case 4: 555 case 8: 556 break; 557 default: 558 dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: " 559 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode); 560 radeon_agpmode = 0; 561 break; 562 } 563 } 564 565 static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) 566 { 567 struct drm_device *dev = pci_get_drvdata(pdev); 568 struct radeon_device *rdev = dev->dev_private; 569 pm_message_t pmm = { .event = PM_EVENT_SUSPEND }; 570 if (state == VGA_SWITCHEROO_ON) { 571 printk(KERN_INFO "radeon: switched on\n"); 572 /* don't suspend or resume card normally */ 573 rdev->powered_down = false; 574 radeon_resume_kms(dev); 575 drm_kms_helper_poll_enable(dev); 576 } else { 577 printk(KERN_INFO "radeon: switched off\n"); 578 drm_kms_helper_poll_disable(dev); 579 radeon_suspend_kms(dev, pmm); 580 /* don't suspend or resume card normally */ 581 rdev->powered_down = true; 582 } 583 } 584 585 static bool radeon_switcheroo_can_switch(struct pci_dev *pdev) 586 { 587 struct drm_device *dev = pci_get_drvdata(pdev); 588 bool can_switch; 589 590 spin_lock(&dev->count_lock); 591 can_switch = (dev->open_count == 0); 592 spin_unlock(&dev->count_lock); 593 return can_switch; 594 } 595 596 597 int radeon_device_init(struct radeon_device *rdev, 598 struct drm_device *ddev, 599 struct pci_dev *pdev, 600 uint32_t flags) 601 { 602 int r, i; 603 int dma_bits; 604 605 rdev->shutdown = false; 606 rdev->dev = &pdev->dev; 607 rdev->ddev = ddev; 608 rdev->pdev = pdev; 609 rdev->flags = flags; 610 rdev->family = flags & RADEON_FAMILY_MASK; 611 rdev->is_atom_bios = false; 612 rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT; 613 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; 614 rdev->gpu_lockup = false; 615 rdev->accel_working = false; 616 617 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X).\n", 618 radeon_family_name[rdev->family], pdev->vendor, pdev->device); 619 620 /* mutex initialization are all done here so we 621 * can recall function without having locking issues */ 622 mutex_init(&rdev->cs_mutex); 623 mutex_init(&rdev->ib_pool.mutex); 624 mutex_init(&rdev->cp.mutex); 625 mutex_init(&rdev->dc_hw_i2c_mutex); 626 if (rdev->family >= CHIP_R600) 627 spin_lock_init(&rdev->ih.lock); 628 mutex_init(&rdev->gem.mutex); 629 mutex_init(&rdev->pm.mutex); 630 mutex_init(&rdev->vram_mutex); 631 rwlock_init(&rdev->fence_drv.lock); 632 INIT_LIST_HEAD(&rdev->gem.objects); 633 init_waitqueue_head(&rdev->irq.vblank_queue); 634 init_waitqueue_head(&rdev->irq.idle_queue); 635 636 /* setup workqueue */ 637 rdev->wq = create_workqueue("radeon"); 638 if (rdev->wq == NULL) 639 return -ENOMEM; 640 641 /* Set asic functions */ 642 r = radeon_asic_init(rdev); 643 if (r) 644 return r; 645 radeon_check_arguments(rdev); 646 647 /* all of the newer IGP chips have an internal gart 648 * However some rs4xx report as AGP, so remove that here. 649 */ 650 if ((rdev->family >= CHIP_RS400) && 651 (rdev->flags & RADEON_IS_IGP)) { 652 rdev->flags &= ~RADEON_IS_AGP; 653 } 654 655 if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) { 656 radeon_agp_disable(rdev); 657 } 658 659 /* set DMA mask + need_dma32 flags. 660 * PCIE - can handle 40-bits. 661 * IGP - can handle 40-bits (in theory) 662 * AGP - generally dma32 is safest 663 * PCI - only dma32 664 */ 665 rdev->need_dma32 = false; 666 if (rdev->flags & RADEON_IS_AGP) 667 rdev->need_dma32 = true; 668 if (rdev->flags & RADEON_IS_PCI) 669 rdev->need_dma32 = true; 670 671 dma_bits = rdev->need_dma32 ? 32 : 40; 672 r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits)); 673 if (r) { 674 printk(KERN_WARNING "radeon: No suitable DMA available.\n"); 675 } 676 677 /* Registers mapping */ 678 /* TODO: block userspace mapping of io register */ 679 rdev->rmmio_base = pci_resource_start(rdev->pdev, 2); 680 rdev->rmmio_size = pci_resource_len(rdev->pdev, 2); 681 rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size); 682 if (rdev->rmmio == NULL) { 683 return -ENOMEM; 684 } 685 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base); 686 DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size); 687 688 /* io port mapping */ 689 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 690 if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) { 691 rdev->rio_mem_size = pci_resource_len(rdev->pdev, i); 692 rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size); 693 break; 694 } 695 } 696 if (rdev->rio_mem == NULL) 697 DRM_ERROR("Unable to find PCI I/O BAR\n"); 698 699 /* if we have > 1 VGA cards, then disable the radeon VGA resources */ 700 /* this will fail for cards that aren't VGA class devices, just 701 * ignore it */ 702 vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode); 703 vga_switcheroo_register_client(rdev->pdev, 704 radeon_switcheroo_set_state, 705 radeon_switcheroo_can_switch); 706 707 r = radeon_init(rdev); 708 if (r) 709 return r; 710 711 if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) { 712 /* Acceleration not working on AGP card try again 713 * with fallback to PCI or PCIE GART 714 */ 715 radeon_asic_reset(rdev); 716 radeon_fini(rdev); 717 radeon_agp_disable(rdev); 718 r = radeon_init(rdev); 719 if (r) 720 return r; 721 } 722 if (radeon_testing) { 723 radeon_test_moves(rdev); 724 } 725 if (radeon_benchmarking) { 726 radeon_benchmark(rdev); 727 } 728 return 0; 729 } 730 731 void radeon_device_fini(struct radeon_device *rdev) 732 { 733 DRM_INFO("radeon: finishing device.\n"); 734 rdev->shutdown = true; 735 /* evict vram memory */ 736 radeon_bo_evict_vram(rdev); 737 radeon_fini(rdev); 738 destroy_workqueue(rdev->wq); 739 vga_switcheroo_unregister_client(rdev->pdev); 740 vga_client_register(rdev->pdev, NULL, NULL, NULL); 741 if (rdev->rio_mem) 742 pci_iounmap(rdev->pdev, rdev->rio_mem); 743 rdev->rio_mem = NULL; 744 iounmap(rdev->rmmio); 745 rdev->rmmio = NULL; 746 } 747 748 749 /* 750 * Suspend & resume. 751 */ 752 int radeon_suspend_kms(struct drm_device *dev, pm_message_t state) 753 { 754 struct radeon_device *rdev; 755 struct drm_crtc *crtc; 756 struct drm_connector *connector; 757 int r; 758 759 if (dev == NULL || dev->dev_private == NULL) { 760 return -ENODEV; 761 } 762 if (state.event == PM_EVENT_PRETHAW) { 763 return 0; 764 } 765 rdev = dev->dev_private; 766 767 if (rdev->powered_down) 768 return 0; 769 770 /* turn off display hw */ 771 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 772 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); 773 } 774 775 /* unpin the front buffers */ 776 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 777 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb); 778 struct radeon_bo *robj; 779 780 if (rfb == NULL || rfb->obj == NULL) { 781 continue; 782 } 783 robj = rfb->obj->driver_private; 784 /* don't unpin kernel fb objects */ 785 if (!radeon_fbdev_robj_is_fb(rdev, robj)) { 786 r = radeon_bo_reserve(robj, false); 787 if (r == 0) { 788 radeon_bo_unpin(robj); 789 radeon_bo_unreserve(robj); 790 } 791 } 792 } 793 /* evict vram memory */ 794 radeon_bo_evict_vram(rdev); 795 /* wait for gpu to finish processing current batch */ 796 radeon_fence_wait_last(rdev); 797 798 radeon_save_bios_scratch_regs(rdev); 799 800 radeon_pm_suspend(rdev); 801 radeon_suspend(rdev); 802 radeon_hpd_fini(rdev); 803 /* evict remaining vram memory */ 804 radeon_bo_evict_vram(rdev); 805 806 radeon_agp_suspend(rdev); 807 808 pci_save_state(dev->pdev); 809 if (state.event == PM_EVENT_SUSPEND) { 810 /* Shut down the device */ 811 pci_disable_device(dev->pdev); 812 pci_set_power_state(dev->pdev, PCI_D3hot); 813 } 814 acquire_console_sem(); 815 radeon_fbdev_set_suspend(rdev, 1); 816 release_console_sem(); 817 return 0; 818 } 819 820 int radeon_resume_kms(struct drm_device *dev) 821 { 822 struct drm_connector *connector; 823 struct radeon_device *rdev = dev->dev_private; 824 825 if (rdev->powered_down) 826 return 0; 827 828 acquire_console_sem(); 829 pci_set_power_state(dev->pdev, PCI_D0); 830 pci_restore_state(dev->pdev); 831 if (pci_enable_device(dev->pdev)) { 832 release_console_sem(); 833 return -1; 834 } 835 pci_set_master(dev->pdev); 836 /* resume AGP if in use */ 837 radeon_agp_resume(rdev); 838 radeon_resume(rdev); 839 radeon_pm_resume(rdev); 840 radeon_restore_bios_scratch_regs(rdev); 841 842 /* turn on display hw */ 843 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 844 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); 845 } 846 847 radeon_fbdev_set_suspend(rdev, 0); 848 release_console_sem(); 849 850 /* reset hpd state */ 851 radeon_hpd_init(rdev); 852 /* blat the mode back in */ 853 drm_helper_resume_force_mode(dev); 854 return 0; 855 } 856 857 int radeon_gpu_reset(struct radeon_device *rdev) 858 { 859 int r; 860 861 radeon_save_bios_scratch_regs(rdev); 862 radeon_suspend(rdev); 863 864 r = radeon_asic_reset(rdev); 865 if (!r) { 866 dev_info(rdev->dev, "GPU reset succeed\n"); 867 radeon_resume(rdev); 868 radeon_restore_bios_scratch_regs(rdev); 869 drm_helper_resume_force_mode(rdev->ddev); 870 return 0; 871 } 872 /* bad news, how to tell it to userspace ? */ 873 dev_info(rdev->dev, "GPU reset failed\n"); 874 return r; 875 } 876 877 878 /* 879 * Debugfs 880 */ 881 struct radeon_debugfs { 882 struct drm_info_list *files; 883 unsigned num_files; 884 }; 885 static struct radeon_debugfs _radeon_debugfs[RADEON_DEBUGFS_MAX_NUM_FILES]; 886 static unsigned _radeon_debugfs_count = 0; 887 888 int radeon_debugfs_add_files(struct radeon_device *rdev, 889 struct drm_info_list *files, 890 unsigned nfiles) 891 { 892 unsigned i; 893 894 for (i = 0; i < _radeon_debugfs_count; i++) { 895 if (_radeon_debugfs[i].files == files) { 896 /* Already registered */ 897 return 0; 898 } 899 } 900 if ((_radeon_debugfs_count + nfiles) > RADEON_DEBUGFS_MAX_NUM_FILES) { 901 DRM_ERROR("Reached maximum number of debugfs files.\n"); 902 DRM_ERROR("Report so we increase RADEON_DEBUGFS_MAX_NUM_FILES.\n"); 903 return -EINVAL; 904 } 905 _radeon_debugfs[_radeon_debugfs_count].files = files; 906 _radeon_debugfs[_radeon_debugfs_count].num_files = nfiles; 907 _radeon_debugfs_count++; 908 #if defined(CONFIG_DEBUG_FS) 909 drm_debugfs_create_files(files, nfiles, 910 rdev->ddev->control->debugfs_root, 911 rdev->ddev->control); 912 drm_debugfs_create_files(files, nfiles, 913 rdev->ddev->primary->debugfs_root, 914 rdev->ddev->primary); 915 #endif 916 return 0; 917 } 918 919 #if defined(CONFIG_DEBUG_FS) 920 int radeon_debugfs_init(struct drm_minor *minor) 921 { 922 return 0; 923 } 924 925 void radeon_debugfs_cleanup(struct drm_minor *minor) 926 { 927 unsigned i; 928 929 for (i = 0; i < _radeon_debugfs_count; i++) { 930 drm_debugfs_remove_files(_radeon_debugfs[i].files, 931 _radeon_debugfs[i].num_files, minor); 932 } 933 } 934 #endif 935