1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/console.h> 29 #include <drm/drmP.h> 30 #include <drm/drm_crtc_helper.h> 31 #include <drm/radeon_drm.h> 32 #include "radeon_reg.h" 33 #include "radeon.h" 34 #include "radeon_asic.h" 35 #include "atom.h" 36 37 /* 38 * Clear GPU surface registers. 39 */ 40 static void radeon_surface_init(struct radeon_device *rdev) 41 { 42 /* FIXME: check this out */ 43 if (rdev->family < CHIP_R600) { 44 int i; 45 46 for (i = 0; i < 8; i++) { 47 WREG32(RADEON_SURFACE0_INFO + 48 i * (RADEON_SURFACE1_INFO - RADEON_SURFACE0_INFO), 49 0); 50 } 51 /* enable surfaces */ 52 WREG32(RADEON_SURFACE_CNTL, 0); 53 } 54 } 55 56 /* 57 * GPU scratch registers helpers function. 58 */ 59 static void radeon_scratch_init(struct radeon_device *rdev) 60 { 61 int i; 62 63 /* FIXME: check this out */ 64 if (rdev->family < CHIP_R300) { 65 rdev->scratch.num_reg = 5; 66 } else { 67 rdev->scratch.num_reg = 7; 68 } 69 for (i = 0; i < rdev->scratch.num_reg; i++) { 70 rdev->scratch.free[i] = true; 71 rdev->scratch.reg[i] = RADEON_SCRATCH_REG0 + (i * 4); 72 } 73 } 74 75 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg) 76 { 77 int i; 78 79 for (i = 0; i < rdev->scratch.num_reg; i++) { 80 if (rdev->scratch.free[i]) { 81 rdev->scratch.free[i] = false; 82 *reg = rdev->scratch.reg[i]; 83 return 0; 84 } 85 } 86 return -EINVAL; 87 } 88 89 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg) 90 { 91 int i; 92 93 for (i = 0; i < rdev->scratch.num_reg; i++) { 94 if (rdev->scratch.reg[i] == reg) { 95 rdev->scratch.free[i] = true; 96 return; 97 } 98 } 99 } 100 101 /* 102 * MC common functions 103 */ 104 int radeon_mc_setup(struct radeon_device *rdev) 105 { 106 uint32_t tmp; 107 108 /* Some chips have an "issue" with the memory controller, the 109 * location must be aligned to the size. We just align it down, 110 * too bad if we walk over the top of system memory, we don't 111 * use DMA without a remapped anyway. 112 * Affected chips are rv280, all r3xx, and all r4xx, but not IGP 113 */ 114 /* FGLRX seems to setup like this, VRAM a 0, then GART. 115 */ 116 /* 117 * Note: from R6xx the address space is 40bits but here we only 118 * use 32bits (still have to see a card which would exhaust 4G 119 * address space). 120 */ 121 if (rdev->mc.vram_location != 0xFFFFFFFFUL) { 122 /* vram location was already setup try to put gtt after 123 * if it fits */ 124 tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size; 125 tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1); 126 if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) { 127 rdev->mc.gtt_location = tmp; 128 } else { 129 if (rdev->mc.gtt_size >= rdev->mc.vram_location) { 130 printk(KERN_ERR "[drm] GTT too big to fit " 131 "before or after vram location.\n"); 132 return -EINVAL; 133 } 134 rdev->mc.gtt_location = 0; 135 } 136 } else if (rdev->mc.gtt_location != 0xFFFFFFFFUL) { 137 /* gtt location was already setup try to put vram before 138 * if it fits */ 139 if (rdev->mc.mc_vram_size < rdev->mc.gtt_location) { 140 rdev->mc.vram_location = 0; 141 } else { 142 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size; 143 tmp += (rdev->mc.mc_vram_size - 1); 144 tmp &= ~(rdev->mc.mc_vram_size - 1); 145 if ((0xFFFFFFFFUL - tmp) >= rdev->mc.mc_vram_size) { 146 rdev->mc.vram_location = tmp; 147 } else { 148 printk(KERN_ERR "[drm] vram too big to fit " 149 "before or after GTT location.\n"); 150 return -EINVAL; 151 } 152 } 153 } else { 154 rdev->mc.vram_location = 0; 155 rdev->mc.gtt_location = rdev->mc.mc_vram_size; 156 } 157 DRM_INFO("radeon: VRAM %uM\n", rdev->mc.real_vram_size >> 20); 158 DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n", 159 rdev->mc.vram_location, 160 rdev->mc.vram_location + rdev->mc.mc_vram_size - 1); 161 if (rdev->mc.real_vram_size != rdev->mc.mc_vram_size) 162 DRM_INFO("radeon: VRAM less than aperture workaround enabled\n"); 163 DRM_INFO("radeon: GTT %uM\n", rdev->mc.gtt_size >> 20); 164 DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n", 165 rdev->mc.gtt_location, 166 rdev->mc.gtt_location + rdev->mc.gtt_size - 1); 167 return 0; 168 } 169 170 171 /* 172 * GPU helpers function. 173 */ 174 static bool radeon_card_posted(struct radeon_device *rdev) 175 { 176 uint32_t reg; 177 178 /* first check CRTCs */ 179 if (ASIC_IS_AVIVO(rdev)) { 180 reg = RREG32(AVIVO_D1CRTC_CONTROL) | 181 RREG32(AVIVO_D2CRTC_CONTROL); 182 if (reg & AVIVO_CRTC_EN) { 183 return true; 184 } 185 } else { 186 reg = RREG32(RADEON_CRTC_GEN_CNTL) | 187 RREG32(RADEON_CRTC2_GEN_CNTL); 188 if (reg & RADEON_CRTC_EN) { 189 return true; 190 } 191 } 192 193 /* then check MEM_SIZE, in case the crtcs are off */ 194 if (rdev->family >= CHIP_R600) 195 reg = RREG32(R600_CONFIG_MEMSIZE); 196 else 197 reg = RREG32(RADEON_CONFIG_MEMSIZE); 198 199 if (reg) 200 return true; 201 202 return false; 203 204 } 205 206 207 /* 208 * Registers accessors functions. 209 */ 210 uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg) 211 { 212 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); 213 BUG_ON(1); 214 return 0; 215 } 216 217 void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 218 { 219 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", 220 reg, v); 221 BUG_ON(1); 222 } 223 224 void radeon_register_accessor_init(struct radeon_device *rdev) 225 { 226 rdev->mm_rreg = &r100_mm_rreg; 227 rdev->mm_wreg = &r100_mm_wreg; 228 rdev->mc_rreg = &radeon_invalid_rreg; 229 rdev->mc_wreg = &radeon_invalid_wreg; 230 rdev->pll_rreg = &radeon_invalid_rreg; 231 rdev->pll_wreg = &radeon_invalid_wreg; 232 rdev->pcie_rreg = &radeon_invalid_rreg; 233 rdev->pcie_wreg = &radeon_invalid_wreg; 234 rdev->pciep_rreg = &radeon_invalid_rreg; 235 rdev->pciep_wreg = &radeon_invalid_wreg; 236 237 /* Don't change order as we are overridding accessor. */ 238 if (rdev->family < CHIP_RV515) { 239 rdev->pcie_rreg = &rv370_pcie_rreg; 240 rdev->pcie_wreg = &rv370_pcie_wreg; 241 } 242 if (rdev->family >= CHIP_RV515) { 243 rdev->pcie_rreg = &rv515_pcie_rreg; 244 rdev->pcie_wreg = &rv515_pcie_wreg; 245 } 246 /* FIXME: not sure here */ 247 if (rdev->family <= CHIP_R580) { 248 rdev->pll_rreg = &r100_pll_rreg; 249 rdev->pll_wreg = &r100_pll_wreg; 250 } 251 if (rdev->family >= CHIP_RV515) { 252 rdev->mc_rreg = &rv515_mc_rreg; 253 rdev->mc_wreg = &rv515_mc_wreg; 254 } 255 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) { 256 rdev->mc_rreg = &rs400_mc_rreg; 257 rdev->mc_wreg = &rs400_mc_wreg; 258 } 259 if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { 260 rdev->mc_rreg = &rs690_mc_rreg; 261 rdev->mc_wreg = &rs690_mc_wreg; 262 } 263 if (rdev->family == CHIP_RS600) { 264 rdev->mc_rreg = &rs600_mc_rreg; 265 rdev->mc_wreg = &rs600_mc_wreg; 266 } 267 if (rdev->family >= CHIP_R600) { 268 rdev->pciep_rreg = &r600_pciep_rreg; 269 rdev->pciep_wreg = &r600_pciep_wreg; 270 } 271 } 272 273 274 /* 275 * ASIC 276 */ 277 int radeon_asic_init(struct radeon_device *rdev) 278 { 279 radeon_register_accessor_init(rdev); 280 switch (rdev->family) { 281 case CHIP_R100: 282 case CHIP_RV100: 283 case CHIP_RS100: 284 case CHIP_RV200: 285 case CHIP_RS200: 286 case CHIP_R200: 287 case CHIP_RV250: 288 case CHIP_RS300: 289 case CHIP_RV280: 290 rdev->asic = &r100_asic; 291 break; 292 case CHIP_R300: 293 case CHIP_R350: 294 case CHIP_RV350: 295 case CHIP_RV380: 296 rdev->asic = &r300_asic; 297 break; 298 case CHIP_R420: 299 case CHIP_R423: 300 case CHIP_RV410: 301 rdev->asic = &r420_asic; 302 break; 303 case CHIP_RS400: 304 case CHIP_RS480: 305 rdev->asic = &rs400_asic; 306 break; 307 case CHIP_RS600: 308 rdev->asic = &rs600_asic; 309 break; 310 case CHIP_RS690: 311 case CHIP_RS740: 312 rdev->asic = &rs690_asic; 313 break; 314 case CHIP_RV515: 315 rdev->asic = &rv515_asic; 316 break; 317 case CHIP_R520: 318 case CHIP_RV530: 319 case CHIP_RV560: 320 case CHIP_RV570: 321 case CHIP_R580: 322 rdev->asic = &r520_asic; 323 break; 324 case CHIP_R600: 325 case CHIP_RV610: 326 case CHIP_RV630: 327 case CHIP_RV620: 328 case CHIP_RV635: 329 case CHIP_RV670: 330 case CHIP_RS780: 331 case CHIP_RV770: 332 case CHIP_RV730: 333 case CHIP_RV710: 334 default: 335 /* FIXME: not supported yet */ 336 return -EINVAL; 337 } 338 return 0; 339 } 340 341 342 /* 343 * Wrapper around modesetting bits. 344 */ 345 int radeon_clocks_init(struct radeon_device *rdev) 346 { 347 int r; 348 349 radeon_get_clock_info(rdev->ddev); 350 r = radeon_static_clocks_init(rdev->ddev); 351 if (r) { 352 return r; 353 } 354 DRM_INFO("Clocks initialized !\n"); 355 return 0; 356 } 357 358 void radeon_clocks_fini(struct radeon_device *rdev) 359 { 360 } 361 362 /* ATOM accessor methods */ 363 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) 364 { 365 struct radeon_device *rdev = info->dev->dev_private; 366 uint32_t r; 367 368 r = rdev->pll_rreg(rdev, reg); 369 return r; 370 } 371 372 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) 373 { 374 struct radeon_device *rdev = info->dev->dev_private; 375 376 rdev->pll_wreg(rdev, reg, val); 377 } 378 379 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) 380 { 381 struct radeon_device *rdev = info->dev->dev_private; 382 uint32_t r; 383 384 r = rdev->mc_rreg(rdev, reg); 385 return r; 386 } 387 388 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) 389 { 390 struct radeon_device *rdev = info->dev->dev_private; 391 392 rdev->mc_wreg(rdev, reg, val); 393 } 394 395 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) 396 { 397 struct radeon_device *rdev = info->dev->dev_private; 398 399 WREG32(reg*4, val); 400 } 401 402 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) 403 { 404 struct radeon_device *rdev = info->dev->dev_private; 405 uint32_t r; 406 407 r = RREG32(reg*4); 408 return r; 409 } 410 411 static struct card_info atom_card_info = { 412 .dev = NULL, 413 .reg_read = cail_reg_read, 414 .reg_write = cail_reg_write, 415 .mc_read = cail_mc_read, 416 .mc_write = cail_mc_write, 417 .pll_read = cail_pll_read, 418 .pll_write = cail_pll_write, 419 }; 420 421 int radeon_atombios_init(struct radeon_device *rdev) 422 { 423 atom_card_info.dev = rdev->ddev; 424 rdev->mode_info.atom_context = atom_parse(&atom_card_info, rdev->bios); 425 radeon_atom_initialize_bios_scratch_regs(rdev->ddev); 426 return 0; 427 } 428 429 void radeon_atombios_fini(struct radeon_device *rdev) 430 { 431 kfree(rdev->mode_info.atom_context); 432 } 433 434 int radeon_combios_init(struct radeon_device *rdev) 435 { 436 radeon_combios_initialize_bios_scratch_regs(rdev->ddev); 437 return 0; 438 } 439 440 void radeon_combios_fini(struct radeon_device *rdev) 441 { 442 } 443 444 int radeon_modeset_init(struct radeon_device *rdev); 445 void radeon_modeset_fini(struct radeon_device *rdev); 446 447 448 /* 449 * Radeon device. 450 */ 451 int radeon_device_init(struct radeon_device *rdev, 452 struct drm_device *ddev, 453 struct pci_dev *pdev, 454 uint32_t flags) 455 { 456 int r, ret; 457 int dma_bits; 458 459 DRM_INFO("radeon: Initializing kernel modesetting.\n"); 460 rdev->shutdown = false; 461 rdev->ddev = ddev; 462 rdev->pdev = pdev; 463 rdev->flags = flags; 464 rdev->family = flags & RADEON_FAMILY_MASK; 465 rdev->is_atom_bios = false; 466 rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT; 467 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; 468 rdev->gpu_lockup = false; 469 /* mutex initialization are all done here so we 470 * can recall function without having locking issues */ 471 mutex_init(&rdev->cs_mutex); 472 mutex_init(&rdev->ib_pool.mutex); 473 mutex_init(&rdev->cp.mutex); 474 rwlock_init(&rdev->fence_drv.lock); 475 476 if (radeon_agpmode == -1) { 477 rdev->flags &= ~RADEON_IS_AGP; 478 if (rdev->family > CHIP_RV515 || 479 rdev->family == CHIP_RV380 || 480 rdev->family == CHIP_RV410 || 481 rdev->family == CHIP_R423) { 482 DRM_INFO("Forcing AGP to PCIE mode\n"); 483 rdev->flags |= RADEON_IS_PCIE; 484 } else { 485 DRM_INFO("Forcing AGP to PCI mode\n"); 486 rdev->flags |= RADEON_IS_PCI; 487 } 488 } 489 490 /* Set asic functions */ 491 r = radeon_asic_init(rdev); 492 if (r) { 493 return r; 494 } 495 r = radeon_init(rdev); 496 if (r) { 497 return r; 498 } 499 500 /* set DMA mask + need_dma32 flags. 501 * PCIE - can handle 40-bits. 502 * IGP - can handle 40-bits (in theory) 503 * AGP - generally dma32 is safest 504 * PCI - only dma32 505 */ 506 rdev->need_dma32 = false; 507 if (rdev->flags & RADEON_IS_AGP) 508 rdev->need_dma32 = true; 509 if (rdev->flags & RADEON_IS_PCI) 510 rdev->need_dma32 = true; 511 512 dma_bits = rdev->need_dma32 ? 32 : 40; 513 r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits)); 514 if (r) { 515 printk(KERN_WARNING "radeon: No suitable DMA available.\n"); 516 } 517 518 /* Registers mapping */ 519 /* TODO: block userspace mapping of io register */ 520 rdev->rmmio_base = drm_get_resource_start(rdev->ddev, 2); 521 rdev->rmmio_size = drm_get_resource_len(rdev->ddev, 2); 522 rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size); 523 if (rdev->rmmio == NULL) { 524 return -ENOMEM; 525 } 526 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base); 527 DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size); 528 529 /* Setup errata flags */ 530 radeon_errata(rdev); 531 /* Initialize scratch registers */ 532 radeon_scratch_init(rdev); 533 /* Initialize surface registers */ 534 radeon_surface_init(rdev); 535 536 /* TODO: disable VGA need to use VGA request */ 537 /* BIOS*/ 538 if (!radeon_get_bios(rdev)) { 539 if (ASIC_IS_AVIVO(rdev)) 540 return -EINVAL; 541 } 542 if (rdev->is_atom_bios) { 543 r = radeon_atombios_init(rdev); 544 if (r) { 545 return r; 546 } 547 } else { 548 r = radeon_combios_init(rdev); 549 if (r) { 550 return r; 551 } 552 } 553 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 554 if (radeon_gpu_reset(rdev)) { 555 /* FIXME: what do we want to do here ? */ 556 } 557 /* check if cards are posted or not */ 558 if (!radeon_card_posted(rdev) && rdev->bios) { 559 DRM_INFO("GPU not posted. posting now...\n"); 560 if (rdev->is_atom_bios) { 561 atom_asic_init(rdev->mode_info.atom_context); 562 } else { 563 radeon_combios_asic_init(rdev->ddev); 564 } 565 } 566 /* Initialize clocks */ 567 r = radeon_clocks_init(rdev); 568 if (r) { 569 return r; 570 } 571 /* Get vram informations */ 572 radeon_vram_info(rdev); 573 574 /* Add an MTRR for the VRAM */ 575 rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size, 576 MTRR_TYPE_WRCOMB, 1); 577 DRM_INFO("Detected VRAM RAM=%uM, BAR=%uM\n", 578 rdev->mc.real_vram_size >> 20, 579 (unsigned)rdev->mc.aper_size >> 20); 580 DRM_INFO("RAM width %dbits %cDR\n", 581 rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S'); 582 /* Initialize memory controller (also test AGP) */ 583 r = radeon_mc_init(rdev); 584 if (r) { 585 return r; 586 } 587 /* Fence driver */ 588 r = radeon_fence_driver_init(rdev); 589 if (r) { 590 return r; 591 } 592 r = radeon_irq_kms_init(rdev); 593 if (r) { 594 return r; 595 } 596 /* Memory manager */ 597 r = radeon_object_init(rdev); 598 if (r) { 599 return r; 600 } 601 /* Initialize GART (initialize after TTM so we can allocate 602 * memory through TTM but finalize after TTM) */ 603 r = radeon_gart_enable(rdev); 604 if (!r) { 605 r = radeon_gem_init(rdev); 606 } 607 608 /* 1M ring buffer */ 609 if (!r) { 610 r = radeon_cp_init(rdev, 1024 * 1024); 611 } 612 if (!r) { 613 r = radeon_wb_init(rdev); 614 if (r) { 615 DRM_ERROR("radeon: failled initializing WB (%d).\n", r); 616 return r; 617 } 618 } 619 if (!r) { 620 r = radeon_ib_pool_init(rdev); 621 if (r) { 622 DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r); 623 return r; 624 } 625 } 626 if (!r) { 627 r = radeon_ib_test(rdev); 628 if (r) { 629 DRM_ERROR("radeon: failled testing IB (%d).\n", r); 630 return r; 631 } 632 } 633 ret = r; 634 r = radeon_modeset_init(rdev); 635 if (r) { 636 return r; 637 } 638 if (!ret) { 639 DRM_INFO("radeon: kernel modesetting successfully initialized.\n"); 640 } 641 if (radeon_testing) { 642 radeon_test_moves(rdev); 643 } 644 if (radeon_benchmarking) { 645 radeon_benchmark(rdev); 646 } 647 return ret; 648 } 649 650 void radeon_device_fini(struct radeon_device *rdev) 651 { 652 if (rdev == NULL || rdev->rmmio == NULL) { 653 return; 654 } 655 DRM_INFO("radeon: finishing device.\n"); 656 rdev->shutdown = true; 657 /* Order matter so becarefull if you rearrange anythings */ 658 radeon_modeset_fini(rdev); 659 radeon_ib_pool_fini(rdev); 660 radeon_cp_fini(rdev); 661 radeon_wb_fini(rdev); 662 radeon_gem_fini(rdev); 663 radeon_object_fini(rdev); 664 /* mc_fini must be after object_fini */ 665 radeon_mc_fini(rdev); 666 #if __OS_HAS_AGP 667 radeon_agp_fini(rdev); 668 #endif 669 radeon_irq_kms_fini(rdev); 670 radeon_fence_driver_fini(rdev); 671 radeon_clocks_fini(rdev); 672 if (rdev->is_atom_bios) { 673 radeon_atombios_fini(rdev); 674 } else { 675 radeon_combios_fini(rdev); 676 } 677 kfree(rdev->bios); 678 rdev->bios = NULL; 679 iounmap(rdev->rmmio); 680 rdev->rmmio = NULL; 681 } 682 683 684 /* 685 * Suspend & resume. 686 */ 687 int radeon_suspend_kms(struct drm_device *dev, pm_message_t state) 688 { 689 struct radeon_device *rdev = dev->dev_private; 690 struct drm_crtc *crtc; 691 692 if (dev == NULL || rdev == NULL) { 693 return -ENODEV; 694 } 695 if (state.event == PM_EVENT_PRETHAW) { 696 return 0; 697 } 698 /* unpin the front buffers */ 699 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 700 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb); 701 struct radeon_object *robj; 702 703 if (rfb == NULL || rfb->obj == NULL) { 704 continue; 705 } 706 robj = rfb->obj->driver_private; 707 if (robj != rdev->fbdev_robj) { 708 radeon_object_unpin(robj); 709 } 710 } 711 /* evict vram memory */ 712 radeon_object_evict_vram(rdev); 713 /* wait for gpu to finish processing current batch */ 714 radeon_fence_wait_last(rdev); 715 716 radeon_cp_disable(rdev); 717 radeon_gart_disable(rdev); 718 719 /* evict remaining vram memory */ 720 radeon_object_evict_vram(rdev); 721 722 rdev->irq.sw_int = false; 723 radeon_irq_set(rdev); 724 725 pci_save_state(dev->pdev); 726 if (state.event == PM_EVENT_SUSPEND) { 727 /* Shut down the device */ 728 pci_disable_device(dev->pdev); 729 pci_set_power_state(dev->pdev, PCI_D3hot); 730 } 731 acquire_console_sem(); 732 fb_set_suspend(rdev->fbdev_info, 1); 733 release_console_sem(); 734 return 0; 735 } 736 737 int radeon_resume_kms(struct drm_device *dev) 738 { 739 struct radeon_device *rdev = dev->dev_private; 740 int r; 741 742 acquire_console_sem(); 743 pci_set_power_state(dev->pdev, PCI_D0); 744 pci_restore_state(dev->pdev); 745 if (pci_enable_device(dev->pdev)) { 746 release_console_sem(); 747 return -1; 748 } 749 pci_set_master(dev->pdev); 750 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 751 if (radeon_gpu_reset(rdev)) { 752 /* FIXME: what do we want to do here ? */ 753 } 754 /* post card */ 755 if (rdev->is_atom_bios) { 756 atom_asic_init(rdev->mode_info.atom_context); 757 } else { 758 radeon_combios_asic_init(rdev->ddev); 759 } 760 /* Initialize clocks */ 761 r = radeon_clocks_init(rdev); 762 if (r) { 763 release_console_sem(); 764 return r; 765 } 766 /* Enable IRQ */ 767 rdev->irq.sw_int = true; 768 radeon_irq_set(rdev); 769 /* Initialize GPU Memory Controller */ 770 r = radeon_mc_init(rdev); 771 if (r) { 772 goto out; 773 } 774 r = radeon_gart_enable(rdev); 775 if (r) { 776 goto out; 777 } 778 r = radeon_cp_init(rdev, rdev->cp.ring_size); 779 if (r) { 780 goto out; 781 } 782 out: 783 fb_set_suspend(rdev->fbdev_info, 0); 784 release_console_sem(); 785 786 /* blat the mode back in */ 787 drm_helper_resume_force_mode(dev); 788 return 0; 789 } 790 791 792 /* 793 * Debugfs 794 */ 795 struct radeon_debugfs { 796 struct drm_info_list *files; 797 unsigned num_files; 798 }; 799 static struct radeon_debugfs _radeon_debugfs[RADEON_DEBUGFS_MAX_NUM_FILES]; 800 static unsigned _radeon_debugfs_count = 0; 801 802 int radeon_debugfs_add_files(struct radeon_device *rdev, 803 struct drm_info_list *files, 804 unsigned nfiles) 805 { 806 unsigned i; 807 808 for (i = 0; i < _radeon_debugfs_count; i++) { 809 if (_radeon_debugfs[i].files == files) { 810 /* Already registered */ 811 return 0; 812 } 813 } 814 if ((_radeon_debugfs_count + nfiles) > RADEON_DEBUGFS_MAX_NUM_FILES) { 815 DRM_ERROR("Reached maximum number of debugfs files.\n"); 816 DRM_ERROR("Report so we increase RADEON_DEBUGFS_MAX_NUM_FILES.\n"); 817 return -EINVAL; 818 } 819 _radeon_debugfs[_radeon_debugfs_count].files = files; 820 _radeon_debugfs[_radeon_debugfs_count].num_files = nfiles; 821 _radeon_debugfs_count++; 822 #if defined(CONFIG_DEBUG_FS) 823 drm_debugfs_create_files(files, nfiles, 824 rdev->ddev->control->debugfs_root, 825 rdev->ddev->control); 826 drm_debugfs_create_files(files, nfiles, 827 rdev->ddev->primary->debugfs_root, 828 rdev->ddev->primary); 829 #endif 830 return 0; 831 } 832 833 #if defined(CONFIG_DEBUG_FS) 834 int radeon_debugfs_init(struct drm_minor *minor) 835 { 836 return 0; 837 } 838 839 void radeon_debugfs_cleanup(struct drm_minor *minor) 840 { 841 unsigned i; 842 843 for (i = 0; i < _radeon_debugfs_count; i++) { 844 drm_debugfs_remove_files(_radeon_debugfs[i].files, 845 _radeon_debugfs[i].num_files, minor); 846 } 847 } 848 #endif 849