1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/console.h> 29 #include <drm/drmP.h> 30 #include <drm/drm_crtc_helper.h> 31 #include <drm/radeon_drm.h> 32 #include <linux/vgaarb.h> 33 #include "radeon_reg.h" 34 #include "radeon.h" 35 #include "radeon_asic.h" 36 #include "atom.h" 37 38 /* 39 * Clear GPU surface registers. 40 */ 41 void radeon_surface_init(struct radeon_device *rdev) 42 { 43 /* FIXME: check this out */ 44 if (rdev->family < CHIP_R600) { 45 int i; 46 47 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { 48 if (rdev->surface_regs[i].bo) 49 radeon_bo_get_surface_reg(rdev->surface_regs[i].bo); 50 else 51 radeon_clear_surface_reg(rdev, i); 52 } 53 /* enable surfaces */ 54 WREG32(RADEON_SURFACE_CNTL, 0); 55 } 56 } 57 58 /* 59 * GPU scratch registers helpers function. 60 */ 61 void radeon_scratch_init(struct radeon_device *rdev) 62 { 63 int i; 64 65 /* FIXME: check this out */ 66 if (rdev->family < CHIP_R300) { 67 rdev->scratch.num_reg = 5; 68 } else { 69 rdev->scratch.num_reg = 7; 70 } 71 for (i = 0; i < rdev->scratch.num_reg; i++) { 72 rdev->scratch.free[i] = true; 73 rdev->scratch.reg[i] = RADEON_SCRATCH_REG0 + (i * 4); 74 } 75 } 76 77 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg) 78 { 79 int i; 80 81 for (i = 0; i < rdev->scratch.num_reg; i++) { 82 if (rdev->scratch.free[i]) { 83 rdev->scratch.free[i] = false; 84 *reg = rdev->scratch.reg[i]; 85 return 0; 86 } 87 } 88 return -EINVAL; 89 } 90 91 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg) 92 { 93 int i; 94 95 for (i = 0; i < rdev->scratch.num_reg; i++) { 96 if (rdev->scratch.reg[i] == reg) { 97 rdev->scratch.free[i] = true; 98 return; 99 } 100 } 101 } 102 103 /* 104 * MC common functions 105 */ 106 int radeon_mc_setup(struct radeon_device *rdev) 107 { 108 uint32_t tmp; 109 110 /* Some chips have an "issue" with the memory controller, the 111 * location must be aligned to the size. We just align it down, 112 * too bad if we walk over the top of system memory, we don't 113 * use DMA without a remapped anyway. 114 * Affected chips are rv280, all r3xx, and all r4xx, but not IGP 115 */ 116 /* FGLRX seems to setup like this, VRAM a 0, then GART. 117 */ 118 /* 119 * Note: from R6xx the address space is 40bits but here we only 120 * use 32bits (still have to see a card which would exhaust 4G 121 * address space). 122 */ 123 if (rdev->mc.vram_location != 0xFFFFFFFFUL) { 124 /* vram location was already setup try to put gtt after 125 * if it fits */ 126 tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size; 127 tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1); 128 if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) { 129 rdev->mc.gtt_location = tmp; 130 } else { 131 if (rdev->mc.gtt_size >= rdev->mc.vram_location) { 132 printk(KERN_ERR "[drm] GTT too big to fit " 133 "before or after vram location.\n"); 134 return -EINVAL; 135 } 136 rdev->mc.gtt_location = 0; 137 } 138 } else if (rdev->mc.gtt_location != 0xFFFFFFFFUL) { 139 /* gtt location was already setup try to put vram before 140 * if it fits */ 141 if (rdev->mc.mc_vram_size < rdev->mc.gtt_location) { 142 rdev->mc.vram_location = 0; 143 } else { 144 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size; 145 tmp += (rdev->mc.mc_vram_size - 1); 146 tmp &= ~(rdev->mc.mc_vram_size - 1); 147 if ((0xFFFFFFFFUL - tmp) >= rdev->mc.mc_vram_size) { 148 rdev->mc.vram_location = tmp; 149 } else { 150 printk(KERN_ERR "[drm] vram too big to fit " 151 "before or after GTT location.\n"); 152 return -EINVAL; 153 } 154 } 155 } else { 156 rdev->mc.vram_location = 0; 157 tmp = rdev->mc.mc_vram_size; 158 tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1); 159 rdev->mc.gtt_location = tmp; 160 } 161 rdev->mc.vram_start = rdev->mc.vram_location; 162 rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1; 163 rdev->mc.gtt_start = rdev->mc.gtt_location; 164 rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; 165 DRM_INFO("radeon: VRAM %uM\n", (unsigned)(rdev->mc.mc_vram_size >> 20)); 166 DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n", 167 (unsigned)rdev->mc.vram_location, 168 (unsigned)(rdev->mc.vram_location + rdev->mc.mc_vram_size - 1)); 169 DRM_INFO("radeon: GTT %uM\n", (unsigned)(rdev->mc.gtt_size >> 20)); 170 DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n", 171 (unsigned)rdev->mc.gtt_location, 172 (unsigned)(rdev->mc.gtt_location + rdev->mc.gtt_size - 1)); 173 return 0; 174 } 175 176 177 /* 178 * GPU helpers function. 179 */ 180 bool radeon_card_posted(struct radeon_device *rdev) 181 { 182 uint32_t reg; 183 184 /* first check CRTCs */ 185 if (ASIC_IS_AVIVO(rdev)) { 186 reg = RREG32(AVIVO_D1CRTC_CONTROL) | 187 RREG32(AVIVO_D2CRTC_CONTROL); 188 if (reg & AVIVO_CRTC_EN) { 189 return true; 190 } 191 } else { 192 reg = RREG32(RADEON_CRTC_GEN_CNTL) | 193 RREG32(RADEON_CRTC2_GEN_CNTL); 194 if (reg & RADEON_CRTC_EN) { 195 return true; 196 } 197 } 198 199 /* then check MEM_SIZE, in case the crtcs are off */ 200 if (rdev->family >= CHIP_R600) 201 reg = RREG32(R600_CONFIG_MEMSIZE); 202 else 203 reg = RREG32(RADEON_CONFIG_MEMSIZE); 204 205 if (reg) 206 return true; 207 208 return false; 209 210 } 211 212 bool radeon_boot_test_post_card(struct radeon_device *rdev) 213 { 214 if (radeon_card_posted(rdev)) 215 return true; 216 217 if (rdev->bios) { 218 DRM_INFO("GPU not posted. posting now...\n"); 219 if (rdev->is_atom_bios) 220 atom_asic_init(rdev->mode_info.atom_context); 221 else 222 radeon_combios_asic_init(rdev->ddev); 223 return true; 224 } else { 225 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); 226 return false; 227 } 228 } 229 230 int radeon_dummy_page_init(struct radeon_device *rdev) 231 { 232 rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO); 233 if (rdev->dummy_page.page == NULL) 234 return -ENOMEM; 235 rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page, 236 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 237 if (!rdev->dummy_page.addr) { 238 __free_page(rdev->dummy_page.page); 239 rdev->dummy_page.page = NULL; 240 return -ENOMEM; 241 } 242 return 0; 243 } 244 245 void radeon_dummy_page_fini(struct radeon_device *rdev) 246 { 247 if (rdev->dummy_page.page == NULL) 248 return; 249 pci_unmap_page(rdev->pdev, rdev->dummy_page.addr, 250 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 251 __free_page(rdev->dummy_page.page); 252 rdev->dummy_page.page = NULL; 253 } 254 255 256 /* 257 * Registers accessors functions. 258 */ 259 uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg) 260 { 261 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); 262 BUG_ON(1); 263 return 0; 264 } 265 266 void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 267 { 268 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", 269 reg, v); 270 BUG_ON(1); 271 } 272 273 void radeon_register_accessor_init(struct radeon_device *rdev) 274 { 275 rdev->mc_rreg = &radeon_invalid_rreg; 276 rdev->mc_wreg = &radeon_invalid_wreg; 277 rdev->pll_rreg = &radeon_invalid_rreg; 278 rdev->pll_wreg = &radeon_invalid_wreg; 279 rdev->pciep_rreg = &radeon_invalid_rreg; 280 rdev->pciep_wreg = &radeon_invalid_wreg; 281 282 /* Don't change order as we are overridding accessor. */ 283 if (rdev->family < CHIP_RV515) { 284 rdev->pcie_reg_mask = 0xff; 285 } else { 286 rdev->pcie_reg_mask = 0x7ff; 287 } 288 /* FIXME: not sure here */ 289 if (rdev->family <= CHIP_R580) { 290 rdev->pll_rreg = &r100_pll_rreg; 291 rdev->pll_wreg = &r100_pll_wreg; 292 } 293 if (rdev->family >= CHIP_R420) { 294 rdev->mc_rreg = &r420_mc_rreg; 295 rdev->mc_wreg = &r420_mc_wreg; 296 } 297 if (rdev->family >= CHIP_RV515) { 298 rdev->mc_rreg = &rv515_mc_rreg; 299 rdev->mc_wreg = &rv515_mc_wreg; 300 } 301 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) { 302 rdev->mc_rreg = &rs400_mc_rreg; 303 rdev->mc_wreg = &rs400_mc_wreg; 304 } 305 if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { 306 rdev->mc_rreg = &rs690_mc_rreg; 307 rdev->mc_wreg = &rs690_mc_wreg; 308 } 309 if (rdev->family == CHIP_RS600) { 310 rdev->mc_rreg = &rs600_mc_rreg; 311 rdev->mc_wreg = &rs600_mc_wreg; 312 } 313 if (rdev->family >= CHIP_R600) { 314 rdev->pciep_rreg = &r600_pciep_rreg; 315 rdev->pciep_wreg = &r600_pciep_wreg; 316 } 317 } 318 319 320 /* 321 * ASIC 322 */ 323 int radeon_asic_init(struct radeon_device *rdev) 324 { 325 radeon_register_accessor_init(rdev); 326 switch (rdev->family) { 327 case CHIP_R100: 328 case CHIP_RV100: 329 case CHIP_RS100: 330 case CHIP_RV200: 331 case CHIP_RS200: 332 case CHIP_R200: 333 case CHIP_RV250: 334 case CHIP_RS300: 335 case CHIP_RV280: 336 rdev->asic = &r100_asic; 337 break; 338 case CHIP_R300: 339 case CHIP_R350: 340 case CHIP_RV350: 341 case CHIP_RV380: 342 rdev->asic = &r300_asic; 343 if (rdev->flags & RADEON_IS_PCIE) { 344 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush; 345 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page; 346 } 347 break; 348 case CHIP_R420: 349 case CHIP_R423: 350 case CHIP_RV410: 351 rdev->asic = &r420_asic; 352 break; 353 case CHIP_RS400: 354 case CHIP_RS480: 355 rdev->asic = &rs400_asic; 356 break; 357 case CHIP_RS600: 358 rdev->asic = &rs600_asic; 359 break; 360 case CHIP_RS690: 361 case CHIP_RS740: 362 rdev->asic = &rs690_asic; 363 break; 364 case CHIP_RV515: 365 rdev->asic = &rv515_asic; 366 break; 367 case CHIP_R520: 368 case CHIP_RV530: 369 case CHIP_RV560: 370 case CHIP_RV570: 371 case CHIP_R580: 372 rdev->asic = &r520_asic; 373 break; 374 case CHIP_R600: 375 case CHIP_RV610: 376 case CHIP_RV630: 377 case CHIP_RV620: 378 case CHIP_RV635: 379 case CHIP_RV670: 380 case CHIP_RS780: 381 case CHIP_RS880: 382 rdev->asic = &r600_asic; 383 break; 384 case CHIP_RV770: 385 case CHIP_RV730: 386 case CHIP_RV710: 387 case CHIP_RV740: 388 rdev->asic = &rv770_asic; 389 break; 390 default: 391 /* FIXME: not supported yet */ 392 return -EINVAL; 393 } 394 return 0; 395 } 396 397 398 /* 399 * Wrapper around modesetting bits. 400 */ 401 int radeon_clocks_init(struct radeon_device *rdev) 402 { 403 int r; 404 405 r = radeon_static_clocks_init(rdev->ddev); 406 if (r) { 407 return r; 408 } 409 DRM_INFO("Clocks initialized !\n"); 410 return 0; 411 } 412 413 void radeon_clocks_fini(struct radeon_device *rdev) 414 { 415 } 416 417 /* ATOM accessor methods */ 418 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) 419 { 420 struct radeon_device *rdev = info->dev->dev_private; 421 uint32_t r; 422 423 r = rdev->pll_rreg(rdev, reg); 424 return r; 425 } 426 427 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) 428 { 429 struct radeon_device *rdev = info->dev->dev_private; 430 431 rdev->pll_wreg(rdev, reg, val); 432 } 433 434 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) 435 { 436 struct radeon_device *rdev = info->dev->dev_private; 437 uint32_t r; 438 439 r = rdev->mc_rreg(rdev, reg); 440 return r; 441 } 442 443 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) 444 { 445 struct radeon_device *rdev = info->dev->dev_private; 446 447 rdev->mc_wreg(rdev, reg, val); 448 } 449 450 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) 451 { 452 struct radeon_device *rdev = info->dev->dev_private; 453 454 WREG32(reg*4, val); 455 } 456 457 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) 458 { 459 struct radeon_device *rdev = info->dev->dev_private; 460 uint32_t r; 461 462 r = RREG32(reg*4); 463 return r; 464 } 465 466 int radeon_atombios_init(struct radeon_device *rdev) 467 { 468 struct card_info *atom_card_info = 469 kzalloc(sizeof(struct card_info), GFP_KERNEL); 470 471 if (!atom_card_info) 472 return -ENOMEM; 473 474 rdev->mode_info.atom_card_info = atom_card_info; 475 atom_card_info->dev = rdev->ddev; 476 atom_card_info->reg_read = cail_reg_read; 477 atom_card_info->reg_write = cail_reg_write; 478 atom_card_info->mc_read = cail_mc_read; 479 atom_card_info->mc_write = cail_mc_write; 480 atom_card_info->pll_read = cail_pll_read; 481 atom_card_info->pll_write = cail_pll_write; 482 483 rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios); 484 radeon_atom_initialize_bios_scratch_regs(rdev->ddev); 485 atom_allocate_fb_scratch(rdev->mode_info.atom_context); 486 return 0; 487 } 488 489 void radeon_atombios_fini(struct radeon_device *rdev) 490 { 491 if (rdev->mode_info.atom_context) { 492 kfree(rdev->mode_info.atom_context->scratch); 493 kfree(rdev->mode_info.atom_context); 494 } 495 kfree(rdev->mode_info.atom_card_info); 496 } 497 498 int radeon_combios_init(struct radeon_device *rdev) 499 { 500 radeon_combios_initialize_bios_scratch_regs(rdev->ddev); 501 return 0; 502 } 503 504 void radeon_combios_fini(struct radeon_device *rdev) 505 { 506 } 507 508 /* if we get transitioned to only one device, tak VGA back */ 509 static unsigned int radeon_vga_set_decode(void *cookie, bool state) 510 { 511 struct radeon_device *rdev = cookie; 512 radeon_vga_set_state(rdev, state); 513 if (state) 514 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | 515 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; 516 else 517 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; 518 } 519 520 void radeon_agp_disable(struct radeon_device *rdev) 521 { 522 rdev->flags &= ~RADEON_IS_AGP; 523 if (rdev->family >= CHIP_R600) { 524 DRM_INFO("Forcing AGP to PCIE mode\n"); 525 rdev->flags |= RADEON_IS_PCIE; 526 } else if (rdev->family >= CHIP_RV515 || 527 rdev->family == CHIP_RV380 || 528 rdev->family == CHIP_RV410 || 529 rdev->family == CHIP_R423) { 530 DRM_INFO("Forcing AGP to PCIE mode\n"); 531 rdev->flags |= RADEON_IS_PCIE; 532 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush; 533 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page; 534 } else { 535 DRM_INFO("Forcing AGP to PCI mode\n"); 536 rdev->flags |= RADEON_IS_PCI; 537 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush; 538 rdev->asic->gart_set_page = &r100_pci_gart_set_page; 539 } 540 } 541 542 /* 543 * Radeon device. 544 */ 545 int radeon_device_init(struct radeon_device *rdev, 546 struct drm_device *ddev, 547 struct pci_dev *pdev, 548 uint32_t flags) 549 { 550 int r; 551 int dma_bits; 552 553 DRM_INFO("radeon: Initializing kernel modesetting.\n"); 554 rdev->shutdown = false; 555 rdev->dev = &pdev->dev; 556 rdev->ddev = ddev; 557 rdev->pdev = pdev; 558 rdev->flags = flags; 559 rdev->family = flags & RADEON_FAMILY_MASK; 560 rdev->is_atom_bios = false; 561 rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT; 562 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; 563 rdev->gpu_lockup = false; 564 rdev->accel_working = false; 565 /* mutex initialization are all done here so we 566 * can recall function without having locking issues */ 567 mutex_init(&rdev->cs_mutex); 568 mutex_init(&rdev->ib_pool.mutex); 569 mutex_init(&rdev->cp.mutex); 570 if (rdev->family >= CHIP_R600) 571 spin_lock_init(&rdev->ih.lock); 572 mutex_init(&rdev->gem.mutex); 573 rwlock_init(&rdev->fence_drv.lock); 574 INIT_LIST_HEAD(&rdev->gem.objects); 575 576 /* setup workqueue */ 577 rdev->wq = create_workqueue("radeon"); 578 if (rdev->wq == NULL) 579 return -ENOMEM; 580 581 /* Set asic functions */ 582 r = radeon_asic_init(rdev); 583 if (r) { 584 return r; 585 } 586 587 if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) { 588 radeon_agp_disable(rdev); 589 } 590 591 /* set DMA mask + need_dma32 flags. 592 * PCIE - can handle 40-bits. 593 * IGP - can handle 40-bits (in theory) 594 * AGP - generally dma32 is safest 595 * PCI - only dma32 596 */ 597 rdev->need_dma32 = false; 598 if (rdev->flags & RADEON_IS_AGP) 599 rdev->need_dma32 = true; 600 if (rdev->flags & RADEON_IS_PCI) 601 rdev->need_dma32 = true; 602 603 dma_bits = rdev->need_dma32 ? 32 : 40; 604 r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits)); 605 if (r) { 606 printk(KERN_WARNING "radeon: No suitable DMA available.\n"); 607 } 608 609 /* Registers mapping */ 610 /* TODO: block userspace mapping of io register */ 611 rdev->rmmio_base = drm_get_resource_start(rdev->ddev, 2); 612 rdev->rmmio_size = drm_get_resource_len(rdev->ddev, 2); 613 rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size); 614 if (rdev->rmmio == NULL) { 615 return -ENOMEM; 616 } 617 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base); 618 DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size); 619 620 /* if we have > 1 VGA cards, then disable the radeon VGA resources */ 621 /* this will fail for cards that aren't VGA class devices, just 622 * ignore it */ 623 vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode); 624 625 r = radeon_init(rdev); 626 if (r) 627 return r; 628 629 if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) { 630 /* Acceleration not working on AGP card try again 631 * with fallback to PCI or PCIE GART 632 */ 633 radeon_gpu_reset(rdev); 634 radeon_fini(rdev); 635 radeon_agp_disable(rdev); 636 r = radeon_init(rdev); 637 if (r) 638 return r; 639 } 640 if (radeon_testing) { 641 radeon_test_moves(rdev); 642 } 643 if (radeon_benchmarking) { 644 radeon_benchmark(rdev); 645 } 646 return 0; 647 } 648 649 void radeon_device_fini(struct radeon_device *rdev) 650 { 651 DRM_INFO("radeon: finishing device.\n"); 652 rdev->shutdown = true; 653 radeon_fini(rdev); 654 destroy_workqueue(rdev->wq); 655 vga_client_register(rdev->pdev, NULL, NULL, NULL); 656 iounmap(rdev->rmmio); 657 rdev->rmmio = NULL; 658 } 659 660 661 /* 662 * Suspend & resume. 663 */ 664 int radeon_suspend_kms(struct drm_device *dev, pm_message_t state) 665 { 666 struct radeon_device *rdev = dev->dev_private; 667 struct drm_crtc *crtc; 668 int r; 669 670 if (dev == NULL || rdev == NULL) { 671 return -ENODEV; 672 } 673 if (state.event == PM_EVENT_PRETHAW) { 674 return 0; 675 } 676 /* unpin the front buffers */ 677 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 678 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb); 679 struct radeon_bo *robj; 680 681 if (rfb == NULL || rfb->obj == NULL) { 682 continue; 683 } 684 robj = rfb->obj->driver_private; 685 if (robj != rdev->fbdev_rbo) { 686 r = radeon_bo_reserve(robj, false); 687 if (unlikely(r == 0)) { 688 radeon_bo_unpin(robj); 689 radeon_bo_unreserve(robj); 690 } 691 } 692 } 693 /* evict vram memory */ 694 radeon_bo_evict_vram(rdev); 695 /* wait for gpu to finish processing current batch */ 696 radeon_fence_wait_last(rdev); 697 698 radeon_save_bios_scratch_regs(rdev); 699 700 radeon_suspend(rdev); 701 radeon_hpd_fini(rdev); 702 /* evict remaining vram memory */ 703 radeon_bo_evict_vram(rdev); 704 705 pci_save_state(dev->pdev); 706 if (state.event == PM_EVENT_SUSPEND) { 707 /* Shut down the device */ 708 pci_disable_device(dev->pdev); 709 pci_set_power_state(dev->pdev, PCI_D3hot); 710 } 711 acquire_console_sem(); 712 fb_set_suspend(rdev->fbdev_info, 1); 713 release_console_sem(); 714 return 0; 715 } 716 717 int radeon_resume_kms(struct drm_device *dev) 718 { 719 struct radeon_device *rdev = dev->dev_private; 720 721 acquire_console_sem(); 722 pci_set_power_state(dev->pdev, PCI_D0); 723 pci_restore_state(dev->pdev); 724 if (pci_enable_device(dev->pdev)) { 725 release_console_sem(); 726 return -1; 727 } 728 pci_set_master(dev->pdev); 729 /* resume AGP if in use */ 730 radeon_agp_resume(rdev); 731 radeon_resume(rdev); 732 radeon_restore_bios_scratch_regs(rdev); 733 fb_set_suspend(rdev->fbdev_info, 0); 734 release_console_sem(); 735 736 /* reset hpd state */ 737 radeon_hpd_init(rdev); 738 /* blat the mode back in */ 739 drm_helper_resume_force_mode(dev); 740 return 0; 741 } 742 743 744 /* 745 * Debugfs 746 */ 747 struct radeon_debugfs { 748 struct drm_info_list *files; 749 unsigned num_files; 750 }; 751 static struct radeon_debugfs _radeon_debugfs[RADEON_DEBUGFS_MAX_NUM_FILES]; 752 static unsigned _radeon_debugfs_count = 0; 753 754 int radeon_debugfs_add_files(struct radeon_device *rdev, 755 struct drm_info_list *files, 756 unsigned nfiles) 757 { 758 unsigned i; 759 760 for (i = 0; i < _radeon_debugfs_count; i++) { 761 if (_radeon_debugfs[i].files == files) { 762 /* Already registered */ 763 return 0; 764 } 765 } 766 if ((_radeon_debugfs_count + nfiles) > RADEON_DEBUGFS_MAX_NUM_FILES) { 767 DRM_ERROR("Reached maximum number of debugfs files.\n"); 768 DRM_ERROR("Report so we increase RADEON_DEBUGFS_MAX_NUM_FILES.\n"); 769 return -EINVAL; 770 } 771 _radeon_debugfs[_radeon_debugfs_count].files = files; 772 _radeon_debugfs[_radeon_debugfs_count].num_files = nfiles; 773 _radeon_debugfs_count++; 774 #if defined(CONFIG_DEBUG_FS) 775 drm_debugfs_create_files(files, nfiles, 776 rdev->ddev->control->debugfs_root, 777 rdev->ddev->control); 778 drm_debugfs_create_files(files, nfiles, 779 rdev->ddev->primary->debugfs_root, 780 rdev->ddev->primary); 781 #endif 782 return 0; 783 } 784 785 #if defined(CONFIG_DEBUG_FS) 786 int radeon_debugfs_init(struct drm_minor *minor) 787 { 788 return 0; 789 } 790 791 void radeon_debugfs_cleanup(struct drm_minor *minor) 792 { 793 unsigned i; 794 795 for (i = 0; i < _radeon_debugfs_count; i++) { 796 drm_debugfs_remove_files(_radeon_debugfs[i].files, 797 _radeon_debugfs[i].num_files, minor); 798 } 799 } 800 #endif 801