1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/console.h> 29 #include <drm/drmP.h> 30 #include <drm/drm_crtc_helper.h> 31 #include <drm/radeon_drm.h> 32 #include "radeon_reg.h" 33 #include "radeon.h" 34 #include "radeon_asic.h" 35 #include "atom.h" 36 37 /* 38 * Clear GPU surface registers. 39 */ 40 static void radeon_surface_init(struct radeon_device *rdev) 41 { 42 /* FIXME: check this out */ 43 if (rdev->family < CHIP_R600) { 44 int i; 45 46 for (i = 0; i < 8; i++) { 47 WREG32(RADEON_SURFACE0_INFO + 48 i * (RADEON_SURFACE1_INFO - RADEON_SURFACE0_INFO), 49 0); 50 } 51 } 52 } 53 54 /* 55 * GPU scratch registers helpers function. 56 */ 57 static void radeon_scratch_init(struct radeon_device *rdev) 58 { 59 int i; 60 61 /* FIXME: check this out */ 62 if (rdev->family < CHIP_R300) { 63 rdev->scratch.num_reg = 5; 64 } else { 65 rdev->scratch.num_reg = 7; 66 } 67 for (i = 0; i < rdev->scratch.num_reg; i++) { 68 rdev->scratch.free[i] = true; 69 rdev->scratch.reg[i] = RADEON_SCRATCH_REG0 + (i * 4); 70 } 71 } 72 73 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg) 74 { 75 int i; 76 77 for (i = 0; i < rdev->scratch.num_reg; i++) { 78 if (rdev->scratch.free[i]) { 79 rdev->scratch.free[i] = false; 80 *reg = rdev->scratch.reg[i]; 81 return 0; 82 } 83 } 84 return -EINVAL; 85 } 86 87 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg) 88 { 89 int i; 90 91 for (i = 0; i < rdev->scratch.num_reg; i++) { 92 if (rdev->scratch.reg[i] == reg) { 93 rdev->scratch.free[i] = true; 94 return; 95 } 96 } 97 } 98 99 /* 100 * MC common functions 101 */ 102 int radeon_mc_setup(struct radeon_device *rdev) 103 { 104 uint32_t tmp; 105 106 /* Some chips have an "issue" with the memory controller, the 107 * location must be aligned to the size. We just align it down, 108 * too bad if we walk over the top of system memory, we don't 109 * use DMA without a remapped anyway. 110 * Affected chips are rv280, all r3xx, and all r4xx, but not IGP 111 */ 112 /* FGLRX seems to setup like this, VRAM a 0, then GART. 113 */ 114 /* 115 * Note: from R6xx the address space is 40bits but here we only 116 * use 32bits (still have to see a card which would exhaust 4G 117 * address space). 118 */ 119 if (rdev->mc.vram_location != 0xFFFFFFFFUL) { 120 /* vram location was already setup try to put gtt after 121 * if it fits */ 122 tmp = rdev->mc.vram_location + rdev->mc.vram_size; 123 tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1); 124 if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) { 125 rdev->mc.gtt_location = tmp; 126 } else { 127 if (rdev->mc.gtt_size >= rdev->mc.vram_location) { 128 printk(KERN_ERR "[drm] GTT too big to fit " 129 "before or after vram location.\n"); 130 return -EINVAL; 131 } 132 rdev->mc.gtt_location = 0; 133 } 134 } else if (rdev->mc.gtt_location != 0xFFFFFFFFUL) { 135 /* gtt location was already setup try to put vram before 136 * if it fits */ 137 if (rdev->mc.vram_size < rdev->mc.gtt_location) { 138 rdev->mc.vram_location = 0; 139 } else { 140 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size; 141 tmp += (rdev->mc.vram_size - 1); 142 tmp &= ~(rdev->mc.vram_size - 1); 143 if ((0xFFFFFFFFUL - tmp) >= rdev->mc.vram_size) { 144 rdev->mc.vram_location = tmp; 145 } else { 146 printk(KERN_ERR "[drm] vram too big to fit " 147 "before or after GTT location.\n"); 148 return -EINVAL; 149 } 150 } 151 } else { 152 rdev->mc.vram_location = 0; 153 rdev->mc.gtt_location = rdev->mc.vram_size; 154 } 155 DRM_INFO("radeon: VRAM %uM\n", rdev->mc.vram_size >> 20); 156 DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n", 157 rdev->mc.vram_location, 158 rdev->mc.vram_location + rdev->mc.vram_size - 1); 159 DRM_INFO("radeon: GTT %uM\n", rdev->mc.gtt_size >> 20); 160 DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n", 161 rdev->mc.gtt_location, 162 rdev->mc.gtt_location + rdev->mc.gtt_size - 1); 163 return 0; 164 } 165 166 167 /* 168 * GPU helpers function. 169 */ 170 static bool radeon_card_posted(struct radeon_device *rdev) 171 { 172 uint32_t reg; 173 174 /* first check CRTCs */ 175 if (ASIC_IS_AVIVO(rdev)) { 176 reg = RREG32(AVIVO_D1CRTC_CONTROL) | 177 RREG32(AVIVO_D2CRTC_CONTROL); 178 if (reg & AVIVO_CRTC_EN) { 179 return true; 180 } 181 } else { 182 reg = RREG32(RADEON_CRTC_GEN_CNTL) | 183 RREG32(RADEON_CRTC2_GEN_CNTL); 184 if (reg & RADEON_CRTC_EN) { 185 return true; 186 } 187 } 188 189 /* then check MEM_SIZE, in case the crtcs are off */ 190 if (rdev->family >= CHIP_R600) 191 reg = RREG32(R600_CONFIG_MEMSIZE); 192 else 193 reg = RREG32(RADEON_CONFIG_MEMSIZE); 194 195 if (reg) 196 return true; 197 198 return false; 199 200 } 201 202 203 /* 204 * Registers accessors functions. 205 */ 206 uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg) 207 { 208 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); 209 BUG_ON(1); 210 return 0; 211 } 212 213 void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 214 { 215 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", 216 reg, v); 217 BUG_ON(1); 218 } 219 220 void radeon_register_accessor_init(struct radeon_device *rdev) 221 { 222 rdev->mm_rreg = &r100_mm_rreg; 223 rdev->mm_wreg = &r100_mm_wreg; 224 rdev->mc_rreg = &radeon_invalid_rreg; 225 rdev->mc_wreg = &radeon_invalid_wreg; 226 rdev->pll_rreg = &radeon_invalid_rreg; 227 rdev->pll_wreg = &radeon_invalid_wreg; 228 rdev->pcie_rreg = &radeon_invalid_rreg; 229 rdev->pcie_wreg = &radeon_invalid_wreg; 230 rdev->pciep_rreg = &radeon_invalid_rreg; 231 rdev->pciep_wreg = &radeon_invalid_wreg; 232 233 /* Don't change order as we are overridding accessor. */ 234 if (rdev->family < CHIP_RV515) { 235 rdev->pcie_rreg = &rv370_pcie_rreg; 236 rdev->pcie_wreg = &rv370_pcie_wreg; 237 } 238 if (rdev->family >= CHIP_RV515) { 239 rdev->pcie_rreg = &rv515_pcie_rreg; 240 rdev->pcie_wreg = &rv515_pcie_wreg; 241 } 242 /* FIXME: not sure here */ 243 if (rdev->family <= CHIP_R580) { 244 rdev->pll_rreg = &r100_pll_rreg; 245 rdev->pll_wreg = &r100_pll_wreg; 246 } 247 if (rdev->family >= CHIP_RV515) { 248 rdev->mc_rreg = &rv515_mc_rreg; 249 rdev->mc_wreg = &rv515_mc_wreg; 250 } 251 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) { 252 rdev->mc_rreg = &rs400_mc_rreg; 253 rdev->mc_wreg = &rs400_mc_wreg; 254 } 255 if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { 256 rdev->mc_rreg = &rs690_mc_rreg; 257 rdev->mc_wreg = &rs690_mc_wreg; 258 } 259 if (rdev->family == CHIP_RS600) { 260 rdev->mc_rreg = &rs600_mc_rreg; 261 rdev->mc_wreg = &rs600_mc_wreg; 262 } 263 if (rdev->family >= CHIP_R600) { 264 rdev->pciep_rreg = &r600_pciep_rreg; 265 rdev->pciep_wreg = &r600_pciep_wreg; 266 } 267 } 268 269 270 /* 271 * ASIC 272 */ 273 int radeon_asic_init(struct radeon_device *rdev) 274 { 275 radeon_register_accessor_init(rdev); 276 switch (rdev->family) { 277 case CHIP_R100: 278 case CHIP_RV100: 279 case CHIP_RS100: 280 case CHIP_RV200: 281 case CHIP_RS200: 282 case CHIP_R200: 283 case CHIP_RV250: 284 case CHIP_RS300: 285 case CHIP_RV280: 286 rdev->asic = &r100_asic; 287 break; 288 case CHIP_R300: 289 case CHIP_R350: 290 case CHIP_RV350: 291 case CHIP_RV380: 292 rdev->asic = &r300_asic; 293 break; 294 case CHIP_R420: 295 case CHIP_R423: 296 case CHIP_RV410: 297 rdev->asic = &r420_asic; 298 break; 299 case CHIP_RS400: 300 case CHIP_RS480: 301 rdev->asic = &rs400_asic; 302 break; 303 case CHIP_RS600: 304 rdev->asic = &rs600_asic; 305 break; 306 case CHIP_RS690: 307 case CHIP_RS740: 308 rdev->asic = &rs690_asic; 309 break; 310 case CHIP_RV515: 311 rdev->asic = &rv515_asic; 312 break; 313 case CHIP_R520: 314 case CHIP_RV530: 315 case CHIP_RV560: 316 case CHIP_RV570: 317 case CHIP_R580: 318 rdev->asic = &r520_asic; 319 break; 320 case CHIP_R600: 321 case CHIP_RV610: 322 case CHIP_RV630: 323 case CHIP_RV620: 324 case CHIP_RV635: 325 case CHIP_RV670: 326 case CHIP_RS780: 327 case CHIP_RV770: 328 case CHIP_RV730: 329 case CHIP_RV710: 330 default: 331 /* FIXME: not supported yet */ 332 return -EINVAL; 333 } 334 return 0; 335 } 336 337 338 /* 339 * Wrapper around modesetting bits. 340 */ 341 int radeon_clocks_init(struct radeon_device *rdev) 342 { 343 int r; 344 345 radeon_get_clock_info(rdev->ddev); 346 r = radeon_static_clocks_init(rdev->ddev); 347 if (r) { 348 return r; 349 } 350 DRM_INFO("Clocks initialized !\n"); 351 return 0; 352 } 353 354 void radeon_clocks_fini(struct radeon_device *rdev) 355 { 356 } 357 358 /* ATOM accessor methods */ 359 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) 360 { 361 struct radeon_device *rdev = info->dev->dev_private; 362 uint32_t r; 363 364 r = rdev->pll_rreg(rdev, reg); 365 return r; 366 } 367 368 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) 369 { 370 struct radeon_device *rdev = info->dev->dev_private; 371 372 rdev->pll_wreg(rdev, reg, val); 373 } 374 375 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) 376 { 377 struct radeon_device *rdev = info->dev->dev_private; 378 uint32_t r; 379 380 r = rdev->mc_rreg(rdev, reg); 381 return r; 382 } 383 384 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) 385 { 386 struct radeon_device *rdev = info->dev->dev_private; 387 388 rdev->mc_wreg(rdev, reg, val); 389 } 390 391 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) 392 { 393 struct radeon_device *rdev = info->dev->dev_private; 394 395 WREG32(reg*4, val); 396 } 397 398 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) 399 { 400 struct radeon_device *rdev = info->dev->dev_private; 401 uint32_t r; 402 403 r = RREG32(reg*4); 404 return r; 405 } 406 407 static struct card_info atom_card_info = { 408 .dev = NULL, 409 .reg_read = cail_reg_read, 410 .reg_write = cail_reg_write, 411 .mc_read = cail_mc_read, 412 .mc_write = cail_mc_write, 413 .pll_read = cail_pll_read, 414 .pll_write = cail_pll_write, 415 }; 416 417 int radeon_atombios_init(struct radeon_device *rdev) 418 { 419 atom_card_info.dev = rdev->ddev; 420 rdev->mode_info.atom_context = atom_parse(&atom_card_info, rdev->bios); 421 radeon_atom_initialize_bios_scratch_regs(rdev->ddev); 422 return 0; 423 } 424 425 void radeon_atombios_fini(struct radeon_device *rdev) 426 { 427 kfree(rdev->mode_info.atom_context); 428 } 429 430 int radeon_combios_init(struct radeon_device *rdev) 431 { 432 radeon_combios_initialize_bios_scratch_regs(rdev->ddev); 433 return 0; 434 } 435 436 void radeon_combios_fini(struct radeon_device *rdev) 437 { 438 } 439 440 int radeon_modeset_init(struct radeon_device *rdev); 441 void radeon_modeset_fini(struct radeon_device *rdev); 442 443 444 /* 445 * Radeon device. 446 */ 447 int radeon_device_init(struct radeon_device *rdev, 448 struct drm_device *ddev, 449 struct pci_dev *pdev, 450 uint32_t flags) 451 { 452 int r, ret; 453 454 DRM_INFO("radeon: Initializing kernel modesetting.\n"); 455 rdev->shutdown = false; 456 rdev->ddev = ddev; 457 rdev->pdev = pdev; 458 rdev->flags = flags; 459 rdev->family = flags & RADEON_FAMILY_MASK; 460 rdev->is_atom_bios = false; 461 rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT; 462 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; 463 rdev->gpu_lockup = false; 464 /* mutex initialization are all done here so we 465 * can recall function without having locking issues */ 466 mutex_init(&rdev->cs_mutex); 467 mutex_init(&rdev->ib_pool.mutex); 468 mutex_init(&rdev->cp.mutex); 469 rwlock_init(&rdev->fence_drv.lock); 470 471 if (radeon_agpmode == -1) { 472 rdev->flags &= ~RADEON_IS_AGP; 473 if (rdev->family > CHIP_RV515 || 474 rdev->family == CHIP_RV380 || 475 rdev->family == CHIP_RV410 || 476 rdev->family == CHIP_R423) { 477 DRM_INFO("Forcing AGP to PCIE mode\n"); 478 rdev->flags |= RADEON_IS_PCIE; 479 } else { 480 DRM_INFO("Forcing AGP to PCI mode\n"); 481 rdev->flags |= RADEON_IS_PCI; 482 } 483 } 484 485 /* Set asic functions */ 486 r = radeon_asic_init(rdev); 487 if (r) { 488 return r; 489 } 490 r = radeon_init(rdev); 491 if (r) { 492 return r; 493 } 494 495 /* Report DMA addressing limitation */ 496 r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(32)); 497 if (r) { 498 printk(KERN_WARNING "radeon: No suitable DMA available.\n"); 499 } 500 501 /* Registers mapping */ 502 /* TODO: block userspace mapping of io register */ 503 rdev->rmmio_base = drm_get_resource_start(rdev->ddev, 2); 504 rdev->rmmio_size = drm_get_resource_len(rdev->ddev, 2); 505 rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size); 506 if (rdev->rmmio == NULL) { 507 return -ENOMEM; 508 } 509 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base); 510 DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size); 511 512 /* Setup errata flags */ 513 radeon_errata(rdev); 514 /* Initialize scratch registers */ 515 radeon_scratch_init(rdev); 516 /* Initialize surface registers */ 517 radeon_surface_init(rdev); 518 519 /* TODO: disable VGA need to use VGA request */ 520 /* BIOS*/ 521 if (!radeon_get_bios(rdev)) { 522 if (ASIC_IS_AVIVO(rdev)) 523 return -EINVAL; 524 } 525 if (rdev->is_atom_bios) { 526 r = radeon_atombios_init(rdev); 527 if (r) { 528 return r; 529 } 530 } else { 531 r = radeon_combios_init(rdev); 532 if (r) { 533 return r; 534 } 535 } 536 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 537 if (radeon_gpu_reset(rdev)) { 538 /* FIXME: what do we want to do here ? */ 539 } 540 /* check if cards are posted or not */ 541 if (!radeon_card_posted(rdev) && rdev->bios) { 542 DRM_INFO("GPU not posted. posting now...\n"); 543 if (rdev->is_atom_bios) { 544 atom_asic_init(rdev->mode_info.atom_context); 545 } else { 546 radeon_combios_asic_init(rdev->ddev); 547 } 548 } 549 /* Get vram informations */ 550 radeon_vram_info(rdev); 551 /* Device is severly broken if aper size > vram size. 552 * for RN50/M6/M7 - Novell bug 204882 ? 553 */ 554 if (rdev->mc.vram_size < rdev->mc.aper_size) { 555 rdev->mc.aper_size = rdev->mc.vram_size; 556 } 557 /* Add an MTRR for the VRAM */ 558 rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size, 559 MTRR_TYPE_WRCOMB, 1); 560 DRM_INFO("Detected VRAM RAM=%uM, BAR=%uM\n", 561 rdev->mc.vram_size >> 20, 562 (unsigned)rdev->mc.aper_size >> 20); 563 DRM_INFO("RAM width %dbits %cDR\n", 564 rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S'); 565 /* Initialize clocks */ 566 r = radeon_clocks_init(rdev); 567 if (r) { 568 return r; 569 } 570 /* Initialize memory controller (also test AGP) */ 571 r = radeon_mc_init(rdev); 572 if (r) { 573 return r; 574 } 575 /* Fence driver */ 576 r = radeon_fence_driver_init(rdev); 577 if (r) { 578 return r; 579 } 580 r = radeon_irq_kms_init(rdev); 581 if (r) { 582 return r; 583 } 584 /* Memory manager */ 585 r = radeon_object_init(rdev); 586 if (r) { 587 return r; 588 } 589 /* Initialize GART (initialize after TTM so we can allocate 590 * memory through TTM but finalize after TTM) */ 591 r = radeon_gart_enable(rdev); 592 if (!r) { 593 r = radeon_gem_init(rdev); 594 } 595 596 /* 1M ring buffer */ 597 if (!r) { 598 r = radeon_cp_init(rdev, 1024 * 1024); 599 } 600 if (!r) { 601 r = radeon_wb_init(rdev); 602 if (r) { 603 DRM_ERROR("radeon: failled initializing WB (%d).\n", r); 604 return r; 605 } 606 } 607 if (!r) { 608 r = radeon_ib_pool_init(rdev); 609 if (r) { 610 DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r); 611 return r; 612 } 613 } 614 if (!r) { 615 r = radeon_ib_test(rdev); 616 if (r) { 617 DRM_ERROR("radeon: failled testing IB (%d).\n", r); 618 return r; 619 } 620 } 621 ret = r; 622 r = radeon_modeset_init(rdev); 623 if (r) { 624 return r; 625 } 626 if (!ret) { 627 DRM_INFO("radeon: kernel modesetting successfully initialized.\n"); 628 } 629 if (radeon_benchmarking) { 630 radeon_benchmark(rdev); 631 } 632 return ret; 633 } 634 635 void radeon_device_fini(struct radeon_device *rdev) 636 { 637 if (rdev == NULL || rdev->rmmio == NULL) { 638 return; 639 } 640 DRM_INFO("radeon: finishing device.\n"); 641 rdev->shutdown = true; 642 /* Order matter so becarefull if you rearrange anythings */ 643 radeon_modeset_fini(rdev); 644 radeon_ib_pool_fini(rdev); 645 radeon_cp_fini(rdev); 646 radeon_wb_fini(rdev); 647 radeon_gem_fini(rdev); 648 radeon_object_fini(rdev); 649 /* mc_fini must be after object_fini */ 650 radeon_mc_fini(rdev); 651 #if __OS_HAS_AGP 652 radeon_agp_fini(rdev); 653 #endif 654 radeon_irq_kms_fini(rdev); 655 radeon_fence_driver_fini(rdev); 656 radeon_clocks_fini(rdev); 657 if (rdev->is_atom_bios) { 658 radeon_atombios_fini(rdev); 659 } else { 660 radeon_combios_fini(rdev); 661 } 662 kfree(rdev->bios); 663 rdev->bios = NULL; 664 iounmap(rdev->rmmio); 665 rdev->rmmio = NULL; 666 } 667 668 669 /* 670 * Suspend & resume. 671 */ 672 int radeon_suspend_kms(struct drm_device *dev, pm_message_t state) 673 { 674 struct radeon_device *rdev = dev->dev_private; 675 struct drm_crtc *crtc; 676 677 if (dev == NULL || rdev == NULL) { 678 return -ENODEV; 679 } 680 if (state.event == PM_EVENT_PRETHAW) { 681 return 0; 682 } 683 /* unpin the front buffers */ 684 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 685 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb); 686 struct radeon_object *robj; 687 688 if (rfb == NULL || rfb->obj == NULL) { 689 continue; 690 } 691 robj = rfb->obj->driver_private; 692 if (robj != rdev->fbdev_robj) { 693 radeon_object_unpin(robj); 694 } 695 } 696 /* evict vram memory */ 697 radeon_object_evict_vram(rdev); 698 /* wait for gpu to finish processing current batch */ 699 radeon_fence_wait_last(rdev); 700 701 radeon_cp_disable(rdev); 702 radeon_gart_disable(rdev); 703 704 /* evict remaining vram memory */ 705 radeon_object_evict_vram(rdev); 706 707 rdev->irq.sw_int = false; 708 radeon_irq_set(rdev); 709 710 pci_save_state(dev->pdev); 711 if (state.event == PM_EVENT_SUSPEND) { 712 /* Shut down the device */ 713 pci_disable_device(dev->pdev); 714 pci_set_power_state(dev->pdev, PCI_D3hot); 715 } 716 acquire_console_sem(); 717 fb_set_suspend(rdev->fbdev_info, 1); 718 release_console_sem(); 719 return 0; 720 } 721 722 int radeon_resume_kms(struct drm_device *dev) 723 { 724 struct radeon_device *rdev = dev->dev_private; 725 int r; 726 727 acquire_console_sem(); 728 pci_set_power_state(dev->pdev, PCI_D0); 729 pci_restore_state(dev->pdev); 730 if (pci_enable_device(dev->pdev)) { 731 release_console_sem(); 732 return -1; 733 } 734 pci_set_master(dev->pdev); 735 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 736 if (radeon_gpu_reset(rdev)) { 737 /* FIXME: what do we want to do here ? */ 738 } 739 /* post card */ 740 if (rdev->is_atom_bios) { 741 atom_asic_init(rdev->mode_info.atom_context); 742 } else { 743 radeon_combios_asic_init(rdev->ddev); 744 } 745 /* Initialize clocks */ 746 r = radeon_clocks_init(rdev); 747 if (r) { 748 release_console_sem(); 749 return r; 750 } 751 /* Enable IRQ */ 752 rdev->irq.sw_int = true; 753 radeon_irq_set(rdev); 754 /* Initialize GPU Memory Controller */ 755 r = radeon_mc_init(rdev); 756 if (r) { 757 goto out; 758 } 759 r = radeon_gart_enable(rdev); 760 if (r) { 761 goto out; 762 } 763 r = radeon_cp_init(rdev, rdev->cp.ring_size); 764 if (r) { 765 goto out; 766 } 767 out: 768 fb_set_suspend(rdev->fbdev_info, 0); 769 release_console_sem(); 770 771 /* blat the mode back in */ 772 drm_helper_resume_force_mode(dev); 773 return 0; 774 } 775 776 777 /* 778 * Debugfs 779 */ 780 struct radeon_debugfs { 781 struct drm_info_list *files; 782 unsigned num_files; 783 }; 784 static struct radeon_debugfs _radeon_debugfs[RADEON_DEBUGFS_MAX_NUM_FILES]; 785 static unsigned _radeon_debugfs_count = 0; 786 787 int radeon_debugfs_add_files(struct radeon_device *rdev, 788 struct drm_info_list *files, 789 unsigned nfiles) 790 { 791 unsigned i; 792 793 for (i = 0; i < _radeon_debugfs_count; i++) { 794 if (_radeon_debugfs[i].files == files) { 795 /* Already registered */ 796 return 0; 797 } 798 } 799 if ((_radeon_debugfs_count + nfiles) > RADEON_DEBUGFS_MAX_NUM_FILES) { 800 DRM_ERROR("Reached maximum number of debugfs files.\n"); 801 DRM_ERROR("Report so we increase RADEON_DEBUGFS_MAX_NUM_FILES.\n"); 802 return -EINVAL; 803 } 804 _radeon_debugfs[_radeon_debugfs_count].files = files; 805 _radeon_debugfs[_radeon_debugfs_count].num_files = nfiles; 806 _radeon_debugfs_count++; 807 #if defined(CONFIG_DEBUG_FS) 808 drm_debugfs_create_files(files, nfiles, 809 rdev->ddev->control->debugfs_root, 810 rdev->ddev->control); 811 drm_debugfs_create_files(files, nfiles, 812 rdev->ddev->primary->debugfs_root, 813 rdev->ddev->primary); 814 #endif 815 return 0; 816 } 817 818 #if defined(CONFIG_DEBUG_FS) 819 int radeon_debugfs_init(struct drm_minor *minor) 820 { 821 return 0; 822 } 823 824 void radeon_debugfs_cleanup(struct drm_minor *minor) 825 { 826 unsigned i; 827 828 for (i = 0; i < _radeon_debugfs_count; i++) { 829 drm_debugfs_remove_files(_radeon_debugfs[i].files, 830 _radeon_debugfs[i].num_files, minor); 831 } 832 } 833 #endif 834