1 /* 2 * Copyright 2004 ATI Technologies Inc., Markham, Ontario 3 * Copyright 2007-8 Advanced Micro Devices, Inc. 4 * Copyright 2008 Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 */ 27 28 #include <linux/pci.h> 29 30 #include <drm/drm_device.h> 31 #include <drm/drm_edid.h> 32 #include <drm/radeon_drm.h> 33 34 #include "radeon.h" 35 #include "radeon_legacy_encoders.h" 36 #include "atom.h" 37 38 #ifdef CONFIG_PPC_PMAC 39 /* not sure which of these are needed */ 40 #include <asm/machdep.h> 41 #include <asm/pmac_feature.h> 42 #include <asm/prom.h> 43 #endif /* CONFIG_PPC_PMAC */ 44 45 /* old legacy ATI BIOS routines */ 46 47 /* COMBIOS table offsets */ 48 enum radeon_combios_table_offset { 49 /* absolute offset tables */ 50 COMBIOS_ASIC_INIT_1_TABLE, 51 COMBIOS_BIOS_SUPPORT_TABLE, 52 COMBIOS_DAC_PROGRAMMING_TABLE, 53 COMBIOS_MAX_COLOR_DEPTH_TABLE, 54 COMBIOS_CRTC_INFO_TABLE, 55 COMBIOS_PLL_INFO_TABLE, 56 COMBIOS_TV_INFO_TABLE, 57 COMBIOS_DFP_INFO_TABLE, 58 COMBIOS_HW_CONFIG_INFO_TABLE, 59 COMBIOS_MULTIMEDIA_INFO_TABLE, 60 COMBIOS_TV_STD_PATCH_TABLE, 61 COMBIOS_LCD_INFO_TABLE, 62 COMBIOS_MOBILE_INFO_TABLE, 63 COMBIOS_PLL_INIT_TABLE, 64 COMBIOS_MEM_CONFIG_TABLE, 65 COMBIOS_SAVE_MASK_TABLE, 66 COMBIOS_HARDCODED_EDID_TABLE, 67 COMBIOS_ASIC_INIT_2_TABLE, 68 COMBIOS_CONNECTOR_INFO_TABLE, 69 COMBIOS_DYN_CLK_1_TABLE, 70 COMBIOS_RESERVED_MEM_TABLE, 71 COMBIOS_EXT_TMDS_INFO_TABLE, 72 COMBIOS_MEM_CLK_INFO_TABLE, 73 COMBIOS_EXT_DAC_INFO_TABLE, 74 COMBIOS_MISC_INFO_TABLE, 75 COMBIOS_CRT_INFO_TABLE, 76 COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE, 77 COMBIOS_COMPONENT_VIDEO_INFO_TABLE, 78 COMBIOS_FAN_SPEED_INFO_TABLE, 79 COMBIOS_OVERDRIVE_INFO_TABLE, 80 COMBIOS_OEM_INFO_TABLE, 81 COMBIOS_DYN_CLK_2_TABLE, 82 COMBIOS_POWER_CONNECTOR_INFO_TABLE, 83 COMBIOS_I2C_INFO_TABLE, 84 /* relative offset tables */ 85 COMBIOS_ASIC_INIT_3_TABLE, /* offset from misc info */ 86 COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */ 87 COMBIOS_DETECTED_MEM_TABLE, /* offset from misc info */ 88 COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */ 89 COMBIOS_RAM_RESET_TABLE, /* offset from mem config */ 90 COMBIOS_POWERPLAY_INFO_TABLE, /* offset from mobile info */ 91 COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */ 92 COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */ 93 COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */ 94 COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */ 95 COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */ 96 }; 97 98 enum radeon_combios_ddc { 99 DDC_NONE_DETECTED, 100 DDC_MONID, 101 DDC_DVI, 102 DDC_VGA, 103 DDC_CRT2, 104 DDC_LCD, 105 DDC_GPIO, 106 }; 107 108 enum radeon_combios_connector { 109 CONNECTOR_NONE_LEGACY, 110 CONNECTOR_PROPRIETARY_LEGACY, 111 CONNECTOR_CRT_LEGACY, 112 CONNECTOR_DVI_I_LEGACY, 113 CONNECTOR_DVI_D_LEGACY, 114 CONNECTOR_CTV_LEGACY, 115 CONNECTOR_STV_LEGACY, 116 CONNECTOR_UNSUPPORTED_LEGACY 117 }; 118 119 static const int legacy_connector_convert[] = { 120 DRM_MODE_CONNECTOR_Unknown, 121 DRM_MODE_CONNECTOR_DVID, 122 DRM_MODE_CONNECTOR_VGA, 123 DRM_MODE_CONNECTOR_DVII, 124 DRM_MODE_CONNECTOR_DVID, 125 DRM_MODE_CONNECTOR_Composite, 126 DRM_MODE_CONNECTOR_SVIDEO, 127 DRM_MODE_CONNECTOR_Unknown, 128 }; 129 130 static uint16_t combios_get_table_offset(struct drm_device *dev, 131 enum radeon_combios_table_offset table) 132 { 133 struct radeon_device *rdev = dev->dev_private; 134 int rev, size; 135 uint16_t offset = 0, check_offset; 136 137 if (!rdev->bios) 138 return 0; 139 140 switch (table) { 141 /* absolute offset tables */ 142 case COMBIOS_ASIC_INIT_1_TABLE: 143 check_offset = 0xc; 144 break; 145 case COMBIOS_BIOS_SUPPORT_TABLE: 146 check_offset = 0x14; 147 break; 148 case COMBIOS_DAC_PROGRAMMING_TABLE: 149 check_offset = 0x2a; 150 break; 151 case COMBIOS_MAX_COLOR_DEPTH_TABLE: 152 check_offset = 0x2c; 153 break; 154 case COMBIOS_CRTC_INFO_TABLE: 155 check_offset = 0x2e; 156 break; 157 case COMBIOS_PLL_INFO_TABLE: 158 check_offset = 0x30; 159 break; 160 case COMBIOS_TV_INFO_TABLE: 161 check_offset = 0x32; 162 break; 163 case COMBIOS_DFP_INFO_TABLE: 164 check_offset = 0x34; 165 break; 166 case COMBIOS_HW_CONFIG_INFO_TABLE: 167 check_offset = 0x36; 168 break; 169 case COMBIOS_MULTIMEDIA_INFO_TABLE: 170 check_offset = 0x38; 171 break; 172 case COMBIOS_TV_STD_PATCH_TABLE: 173 check_offset = 0x3e; 174 break; 175 case COMBIOS_LCD_INFO_TABLE: 176 check_offset = 0x40; 177 break; 178 case COMBIOS_MOBILE_INFO_TABLE: 179 check_offset = 0x42; 180 break; 181 case COMBIOS_PLL_INIT_TABLE: 182 check_offset = 0x46; 183 break; 184 case COMBIOS_MEM_CONFIG_TABLE: 185 check_offset = 0x48; 186 break; 187 case COMBIOS_SAVE_MASK_TABLE: 188 check_offset = 0x4a; 189 break; 190 case COMBIOS_HARDCODED_EDID_TABLE: 191 check_offset = 0x4c; 192 break; 193 case COMBIOS_ASIC_INIT_2_TABLE: 194 check_offset = 0x4e; 195 break; 196 case COMBIOS_CONNECTOR_INFO_TABLE: 197 check_offset = 0x50; 198 break; 199 case COMBIOS_DYN_CLK_1_TABLE: 200 check_offset = 0x52; 201 break; 202 case COMBIOS_RESERVED_MEM_TABLE: 203 check_offset = 0x54; 204 break; 205 case COMBIOS_EXT_TMDS_INFO_TABLE: 206 check_offset = 0x58; 207 break; 208 case COMBIOS_MEM_CLK_INFO_TABLE: 209 check_offset = 0x5a; 210 break; 211 case COMBIOS_EXT_DAC_INFO_TABLE: 212 check_offset = 0x5c; 213 break; 214 case COMBIOS_MISC_INFO_TABLE: 215 check_offset = 0x5e; 216 break; 217 case COMBIOS_CRT_INFO_TABLE: 218 check_offset = 0x60; 219 break; 220 case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE: 221 check_offset = 0x62; 222 break; 223 case COMBIOS_COMPONENT_VIDEO_INFO_TABLE: 224 check_offset = 0x64; 225 break; 226 case COMBIOS_FAN_SPEED_INFO_TABLE: 227 check_offset = 0x66; 228 break; 229 case COMBIOS_OVERDRIVE_INFO_TABLE: 230 check_offset = 0x68; 231 break; 232 case COMBIOS_OEM_INFO_TABLE: 233 check_offset = 0x6a; 234 break; 235 case COMBIOS_DYN_CLK_2_TABLE: 236 check_offset = 0x6c; 237 break; 238 case COMBIOS_POWER_CONNECTOR_INFO_TABLE: 239 check_offset = 0x6e; 240 break; 241 case COMBIOS_I2C_INFO_TABLE: 242 check_offset = 0x70; 243 break; 244 /* relative offset tables */ 245 case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */ 246 check_offset = 247 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); 248 if (check_offset) { 249 rev = RBIOS8(check_offset); 250 if (rev > 0) { 251 check_offset = RBIOS16(check_offset + 0x3); 252 if (check_offset) 253 offset = check_offset; 254 } 255 } 256 break; 257 case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */ 258 check_offset = 259 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); 260 if (check_offset) { 261 rev = RBIOS8(check_offset); 262 if (rev > 0) { 263 check_offset = RBIOS16(check_offset + 0x5); 264 if (check_offset) 265 offset = check_offset; 266 } 267 } 268 break; 269 case COMBIOS_DETECTED_MEM_TABLE: /* offset from misc info */ 270 check_offset = 271 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); 272 if (check_offset) { 273 rev = RBIOS8(check_offset); 274 if (rev > 0) { 275 check_offset = RBIOS16(check_offset + 0x7); 276 if (check_offset) 277 offset = check_offset; 278 } 279 } 280 break; 281 case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */ 282 check_offset = 283 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); 284 if (check_offset) { 285 rev = RBIOS8(check_offset); 286 if (rev == 2) { 287 check_offset = RBIOS16(check_offset + 0x9); 288 if (check_offset) 289 offset = check_offset; 290 } 291 } 292 break; 293 case COMBIOS_RAM_RESET_TABLE: /* offset from mem config */ 294 check_offset = 295 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE); 296 if (check_offset) { 297 while (RBIOS8(check_offset++)); 298 check_offset += 2; 299 if (check_offset) 300 offset = check_offset; 301 } 302 break; 303 case COMBIOS_POWERPLAY_INFO_TABLE: /* offset from mobile info */ 304 check_offset = 305 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); 306 if (check_offset) { 307 check_offset = RBIOS16(check_offset + 0x11); 308 if (check_offset) 309 offset = check_offset; 310 } 311 break; 312 case COMBIOS_GPIO_INFO_TABLE: /* offset from mobile info */ 313 check_offset = 314 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); 315 if (check_offset) { 316 check_offset = RBIOS16(check_offset + 0x13); 317 if (check_offset) 318 offset = check_offset; 319 } 320 break; 321 case COMBIOS_LCD_DDC_INFO_TABLE: /* offset from mobile info */ 322 check_offset = 323 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); 324 if (check_offset) { 325 check_offset = RBIOS16(check_offset + 0x15); 326 if (check_offset) 327 offset = check_offset; 328 } 329 break; 330 case COMBIOS_TMDS_POWER_TABLE: /* offset from mobile info */ 331 check_offset = 332 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); 333 if (check_offset) { 334 check_offset = RBIOS16(check_offset + 0x17); 335 if (check_offset) 336 offset = check_offset; 337 } 338 break; 339 case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */ 340 check_offset = 341 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE); 342 if (check_offset) { 343 check_offset = RBIOS16(check_offset + 0x2); 344 if (check_offset) 345 offset = check_offset; 346 } 347 break; 348 case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */ 349 check_offset = 350 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE); 351 if (check_offset) { 352 check_offset = RBIOS16(check_offset + 0x4); 353 if (check_offset) 354 offset = check_offset; 355 } 356 break; 357 default: 358 check_offset = 0; 359 break; 360 } 361 362 size = RBIOS8(rdev->bios_header_start + 0x6); 363 /* check absolute offset tables */ 364 if (table < COMBIOS_ASIC_INIT_3_TABLE && check_offset && check_offset < size) 365 offset = RBIOS16(rdev->bios_header_start + check_offset); 366 367 return offset; 368 } 369 370 bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev) 371 { 372 int edid_info, size; 373 const struct drm_edid *edid; 374 unsigned char *raw; 375 edid_info = combios_get_table_offset(rdev_to_drm(rdev), COMBIOS_HARDCODED_EDID_TABLE); 376 if (!edid_info) 377 return false; 378 379 raw = rdev->bios + edid_info; 380 size = EDID_LENGTH * (raw[0x7e] + 1); 381 edid = drm_edid_alloc(raw, size); 382 383 if (!drm_edid_valid(edid)) { 384 drm_edid_free(edid); 385 return false; 386 } 387 388 rdev->mode_info.bios_hardcoded_edid = edid; 389 return true; 390 } 391 392 /* this is used for atom LCDs as well */ 393 struct edid * 394 radeon_bios_get_hardcoded_edid(struct radeon_device *rdev) 395 { 396 return drm_edid_duplicate(drm_edid_raw(rdev->mode_info.bios_hardcoded_edid)); 397 } 398 399 static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev, 400 enum radeon_combios_ddc ddc, 401 u32 clk_mask, 402 u32 data_mask) 403 { 404 struct radeon_i2c_bus_rec i2c; 405 int ddc_line = 0; 406 407 /* ddc id = mask reg 408 * DDC_NONE_DETECTED = none 409 * DDC_DVI = RADEON_GPIO_DVI_DDC 410 * DDC_VGA = RADEON_GPIO_VGA_DDC 411 * DDC_LCD = RADEON_GPIOPAD_MASK 412 * DDC_GPIO = RADEON_MDGPIO_MASK 413 * r1xx 414 * DDC_MONID = RADEON_GPIO_MONID 415 * DDC_CRT2 = RADEON_GPIO_CRT2_DDC 416 * r200 417 * DDC_MONID = RADEON_GPIO_MONID 418 * DDC_CRT2 = RADEON_GPIO_DVI_DDC 419 * r300/r350 420 * DDC_MONID = RADEON_GPIO_DVI_DDC 421 * DDC_CRT2 = RADEON_GPIO_DVI_DDC 422 * rv2xx/rv3xx 423 * DDC_MONID = RADEON_GPIO_MONID 424 * DDC_CRT2 = RADEON_GPIO_MONID 425 * rs3xx/rs4xx 426 * DDC_MONID = RADEON_GPIOPAD_MASK 427 * DDC_CRT2 = RADEON_GPIO_MONID 428 */ 429 switch (ddc) { 430 case DDC_NONE_DETECTED: 431 default: 432 ddc_line = 0; 433 break; 434 case DDC_DVI: 435 ddc_line = RADEON_GPIO_DVI_DDC; 436 break; 437 case DDC_VGA: 438 ddc_line = RADEON_GPIO_VGA_DDC; 439 break; 440 case DDC_LCD: 441 ddc_line = RADEON_GPIOPAD_MASK; 442 break; 443 case DDC_GPIO: 444 ddc_line = RADEON_MDGPIO_MASK; 445 break; 446 case DDC_MONID: 447 if (rdev->family == CHIP_RS300 || 448 rdev->family == CHIP_RS400 || 449 rdev->family == CHIP_RS480) 450 ddc_line = RADEON_GPIOPAD_MASK; 451 else if (rdev->family == CHIP_R300 || 452 rdev->family == CHIP_R350) { 453 ddc_line = RADEON_GPIO_DVI_DDC; 454 ddc = DDC_DVI; 455 } else 456 ddc_line = RADEON_GPIO_MONID; 457 break; 458 case DDC_CRT2: 459 if (rdev->family == CHIP_R200 || 460 rdev->family == CHIP_R300 || 461 rdev->family == CHIP_R350) { 462 ddc_line = RADEON_GPIO_DVI_DDC; 463 ddc = DDC_DVI; 464 } else if (rdev->family == CHIP_RS300 || 465 rdev->family == CHIP_RS400 || 466 rdev->family == CHIP_RS480) 467 ddc_line = RADEON_GPIO_MONID; 468 else if (rdev->family >= CHIP_RV350) { 469 ddc_line = RADEON_GPIO_MONID; 470 ddc = DDC_MONID; 471 } else 472 ddc_line = RADEON_GPIO_CRT2_DDC; 473 break; 474 } 475 476 if (ddc_line == RADEON_GPIOPAD_MASK) { 477 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK; 478 i2c.mask_data_reg = RADEON_GPIOPAD_MASK; 479 i2c.a_clk_reg = RADEON_GPIOPAD_A; 480 i2c.a_data_reg = RADEON_GPIOPAD_A; 481 i2c.en_clk_reg = RADEON_GPIOPAD_EN; 482 i2c.en_data_reg = RADEON_GPIOPAD_EN; 483 i2c.y_clk_reg = RADEON_GPIOPAD_Y; 484 i2c.y_data_reg = RADEON_GPIOPAD_Y; 485 } else if (ddc_line == RADEON_MDGPIO_MASK) { 486 i2c.mask_clk_reg = RADEON_MDGPIO_MASK; 487 i2c.mask_data_reg = RADEON_MDGPIO_MASK; 488 i2c.a_clk_reg = RADEON_MDGPIO_A; 489 i2c.a_data_reg = RADEON_MDGPIO_A; 490 i2c.en_clk_reg = RADEON_MDGPIO_EN; 491 i2c.en_data_reg = RADEON_MDGPIO_EN; 492 i2c.y_clk_reg = RADEON_MDGPIO_Y; 493 i2c.y_data_reg = RADEON_MDGPIO_Y; 494 } else { 495 i2c.mask_clk_reg = ddc_line; 496 i2c.mask_data_reg = ddc_line; 497 i2c.a_clk_reg = ddc_line; 498 i2c.a_data_reg = ddc_line; 499 i2c.en_clk_reg = ddc_line; 500 i2c.en_data_reg = ddc_line; 501 i2c.y_clk_reg = ddc_line; 502 i2c.y_data_reg = ddc_line; 503 } 504 505 if (clk_mask && data_mask) { 506 /* system specific masks */ 507 i2c.mask_clk_mask = clk_mask; 508 i2c.mask_data_mask = data_mask; 509 i2c.a_clk_mask = clk_mask; 510 i2c.a_data_mask = data_mask; 511 i2c.en_clk_mask = clk_mask; 512 i2c.en_data_mask = data_mask; 513 i2c.y_clk_mask = clk_mask; 514 i2c.y_data_mask = data_mask; 515 } else if ((ddc_line == RADEON_GPIOPAD_MASK) || 516 (ddc_line == RADEON_MDGPIO_MASK)) { 517 /* default gpiopad masks */ 518 i2c.mask_clk_mask = (0x20 << 8); 519 i2c.mask_data_mask = 0x80; 520 i2c.a_clk_mask = (0x20 << 8); 521 i2c.a_data_mask = 0x80; 522 i2c.en_clk_mask = (0x20 << 8); 523 i2c.en_data_mask = 0x80; 524 i2c.y_clk_mask = (0x20 << 8); 525 i2c.y_data_mask = 0x80; 526 } else { 527 /* default masks for ddc pads */ 528 i2c.mask_clk_mask = RADEON_GPIO_MASK_1; 529 i2c.mask_data_mask = RADEON_GPIO_MASK_0; 530 i2c.a_clk_mask = RADEON_GPIO_A_1; 531 i2c.a_data_mask = RADEON_GPIO_A_0; 532 i2c.en_clk_mask = RADEON_GPIO_EN_1; 533 i2c.en_data_mask = RADEON_GPIO_EN_0; 534 i2c.y_clk_mask = RADEON_GPIO_Y_1; 535 i2c.y_data_mask = RADEON_GPIO_Y_0; 536 } 537 538 switch (rdev->family) { 539 case CHIP_R100: 540 case CHIP_RV100: 541 case CHIP_RS100: 542 case CHIP_RV200: 543 case CHIP_RS200: 544 case CHIP_RS300: 545 switch (ddc_line) { 546 case RADEON_GPIO_DVI_DDC: 547 i2c.hw_capable = true; 548 break; 549 default: 550 i2c.hw_capable = false; 551 break; 552 } 553 break; 554 case CHIP_R200: 555 switch (ddc_line) { 556 case RADEON_GPIO_DVI_DDC: 557 case RADEON_GPIO_MONID: 558 i2c.hw_capable = true; 559 break; 560 default: 561 i2c.hw_capable = false; 562 break; 563 } 564 break; 565 case CHIP_RV250: 566 case CHIP_RV280: 567 switch (ddc_line) { 568 case RADEON_GPIO_VGA_DDC: 569 case RADEON_GPIO_DVI_DDC: 570 case RADEON_GPIO_CRT2_DDC: 571 i2c.hw_capable = true; 572 break; 573 default: 574 i2c.hw_capable = false; 575 break; 576 } 577 break; 578 case CHIP_R300: 579 case CHIP_R350: 580 switch (ddc_line) { 581 case RADEON_GPIO_VGA_DDC: 582 case RADEON_GPIO_DVI_DDC: 583 i2c.hw_capable = true; 584 break; 585 default: 586 i2c.hw_capable = false; 587 break; 588 } 589 break; 590 case CHIP_RV350: 591 case CHIP_RV380: 592 case CHIP_RS400: 593 case CHIP_RS480: 594 switch (ddc_line) { 595 case RADEON_GPIO_VGA_DDC: 596 case RADEON_GPIO_DVI_DDC: 597 i2c.hw_capable = true; 598 break; 599 case RADEON_GPIO_MONID: 600 /* hw i2c on RADEON_GPIO_MONID doesn't seem to work 601 * reliably on some pre-r4xx hardware; not sure why. 602 */ 603 i2c.hw_capable = false; 604 break; 605 default: 606 i2c.hw_capable = false; 607 break; 608 } 609 break; 610 default: 611 i2c.hw_capable = false; 612 break; 613 } 614 i2c.mm_i2c = false; 615 616 i2c.i2c_id = ddc; 617 i2c.hpd = RADEON_HPD_NONE; 618 619 if (ddc_line) 620 i2c.valid = true; 621 else 622 i2c.valid = false; 623 624 return i2c; 625 } 626 627 static struct radeon_i2c_bus_rec radeon_combios_get_i2c_info_from_table(struct radeon_device *rdev) 628 { 629 struct drm_device *dev = rdev_to_drm(rdev); 630 struct radeon_i2c_bus_rec i2c; 631 u16 offset; 632 u8 id, blocks, clk, data; 633 int i; 634 635 i2c.valid = false; 636 637 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE); 638 if (offset) { 639 blocks = RBIOS8(offset + 2); 640 for (i = 0; i < blocks; i++) { 641 id = RBIOS8(offset + 3 + (i * 5) + 0); 642 if (id == 136) { 643 clk = RBIOS8(offset + 3 + (i * 5) + 3); 644 data = RBIOS8(offset + 3 + (i * 5) + 4); 645 /* gpiopad */ 646 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 647 (1 << clk), (1 << data)); 648 break; 649 } 650 } 651 } 652 return i2c; 653 } 654 655 void radeon_combios_i2c_init(struct radeon_device *rdev) 656 { 657 struct drm_device *dev = rdev_to_drm(rdev); 658 struct radeon_i2c_bus_rec i2c; 659 660 /* actual hw pads 661 * r1xx/rs2xx/rs3xx 662 * 0x60, 0x64, 0x68, 0x6c, gpiopads, mm 663 * r200 664 * 0x60, 0x64, 0x68, mm 665 * r300/r350 666 * 0x60, 0x64, mm 667 * rv2xx/rv3xx/rs4xx 668 * 0x60, 0x64, 0x68, gpiopads, mm 669 */ 670 671 /* 0x60 */ 672 i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 673 rdev->i2c_bus[0] = radeon_i2c_create(dev, &i2c, "DVI_DDC"); 674 /* 0x64 */ 675 i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 676 rdev->i2c_bus[1] = radeon_i2c_create(dev, &i2c, "VGA_DDC"); 677 678 /* mm i2c */ 679 i2c.valid = true; 680 i2c.hw_capable = true; 681 i2c.mm_i2c = true; 682 i2c.i2c_id = 0xa0; 683 rdev->i2c_bus[2] = radeon_i2c_create(dev, &i2c, "MM_I2C"); 684 685 if (rdev->family == CHIP_R300 || 686 rdev->family == CHIP_R350) { 687 /* only 2 sw i2c pads */ 688 } else if (rdev->family == CHIP_RS300 || 689 rdev->family == CHIP_RS400 || 690 rdev->family == CHIP_RS480) { 691 /* 0x68 */ 692 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); 693 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID"); 694 695 /* gpiopad */ 696 i2c = radeon_combios_get_i2c_info_from_table(rdev); 697 if (i2c.valid) 698 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK"); 699 } else if ((rdev->family == CHIP_R200) || 700 (rdev->family >= CHIP_R300)) { 701 /* 0x68 */ 702 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 703 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID"); 704 } else { 705 /* 0x68 */ 706 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 707 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID"); 708 /* 0x6c */ 709 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); 710 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "CRT2_DDC"); 711 } 712 } 713 714 bool radeon_combios_get_clock_info(struct drm_device *dev) 715 { 716 struct radeon_device *rdev = dev->dev_private; 717 uint16_t pll_info; 718 struct radeon_pll *p1pll = &rdev->clock.p1pll; 719 struct radeon_pll *p2pll = &rdev->clock.p2pll; 720 struct radeon_pll *spll = &rdev->clock.spll; 721 struct radeon_pll *mpll = &rdev->clock.mpll; 722 int8_t rev; 723 uint16_t sclk, mclk; 724 725 pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE); 726 if (pll_info) { 727 rev = RBIOS8(pll_info); 728 729 /* pixel clocks */ 730 p1pll->reference_freq = RBIOS16(pll_info + 0xe); 731 p1pll->reference_div = RBIOS16(pll_info + 0x10); 732 p1pll->pll_out_min = RBIOS32(pll_info + 0x12); 733 p1pll->pll_out_max = RBIOS32(pll_info + 0x16); 734 p1pll->lcd_pll_out_min = p1pll->pll_out_min; 735 p1pll->lcd_pll_out_max = p1pll->pll_out_max; 736 737 if (rev > 9) { 738 p1pll->pll_in_min = RBIOS32(pll_info + 0x36); 739 p1pll->pll_in_max = RBIOS32(pll_info + 0x3a); 740 } else { 741 p1pll->pll_in_min = 40; 742 p1pll->pll_in_max = 500; 743 } 744 *p2pll = *p1pll; 745 746 /* system clock */ 747 spll->reference_freq = RBIOS16(pll_info + 0x1a); 748 spll->reference_div = RBIOS16(pll_info + 0x1c); 749 spll->pll_out_min = RBIOS32(pll_info + 0x1e); 750 spll->pll_out_max = RBIOS32(pll_info + 0x22); 751 752 if (rev > 10) { 753 spll->pll_in_min = RBIOS32(pll_info + 0x48); 754 spll->pll_in_max = RBIOS32(pll_info + 0x4c); 755 } else { 756 /* ??? */ 757 spll->pll_in_min = 40; 758 spll->pll_in_max = 500; 759 } 760 761 /* memory clock */ 762 mpll->reference_freq = RBIOS16(pll_info + 0x26); 763 mpll->reference_div = RBIOS16(pll_info + 0x28); 764 mpll->pll_out_min = RBIOS32(pll_info + 0x2a); 765 mpll->pll_out_max = RBIOS32(pll_info + 0x2e); 766 767 if (rev > 10) { 768 mpll->pll_in_min = RBIOS32(pll_info + 0x5a); 769 mpll->pll_in_max = RBIOS32(pll_info + 0x5e); 770 } else { 771 /* ??? */ 772 mpll->pll_in_min = 40; 773 mpll->pll_in_max = 500; 774 } 775 776 /* default sclk/mclk */ 777 sclk = RBIOS16(pll_info + 0xa); 778 mclk = RBIOS16(pll_info + 0x8); 779 if (sclk == 0) 780 sclk = 200 * 100; 781 if (mclk == 0) 782 mclk = 200 * 100; 783 784 rdev->clock.default_sclk = sclk; 785 rdev->clock.default_mclk = mclk; 786 787 if (RBIOS32(pll_info + 0x16)) 788 rdev->clock.max_pixel_clock = RBIOS32(pll_info + 0x16); 789 else 790 rdev->clock.max_pixel_clock = 35000; /* might need something asic specific */ 791 792 return true; 793 } 794 return false; 795 } 796 797 bool radeon_combios_sideport_present(struct radeon_device *rdev) 798 { 799 struct drm_device *dev = rdev_to_drm(rdev); 800 u16 igp_info; 801 802 /* sideport is AMD only */ 803 if (rdev->family == CHIP_RS400) 804 return false; 805 806 igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE); 807 808 if (igp_info) { 809 if (RBIOS16(igp_info + 0x4)) 810 return true; 811 } 812 return false; 813 } 814 815 static const uint32_t default_primarydac_adj[CHIP_LAST] = { 816 0x00000808, /* r100 */ 817 0x00000808, /* rv100 */ 818 0x00000808, /* rs100 */ 819 0x00000808, /* rv200 */ 820 0x00000808, /* rs200 */ 821 0x00000808, /* r200 */ 822 0x00000808, /* rv250 */ 823 0x00000000, /* rs300 */ 824 0x00000808, /* rv280 */ 825 0x00000808, /* r300 */ 826 0x00000808, /* r350 */ 827 0x00000808, /* rv350 */ 828 0x00000808, /* rv380 */ 829 0x00000808, /* r420 */ 830 0x00000808, /* r423 */ 831 0x00000808, /* rv410 */ 832 0x00000000, /* rs400 */ 833 0x00000000, /* rs480 */ 834 }; 835 836 static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev, 837 struct radeon_encoder_primary_dac *p_dac) 838 { 839 p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family]; 840 return; 841 } 842 843 struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct 844 radeon_encoder 845 *encoder) 846 { 847 struct drm_device *dev = encoder->base.dev; 848 struct radeon_device *rdev = dev->dev_private; 849 uint16_t dac_info; 850 uint8_t rev, bg, dac; 851 struct radeon_encoder_primary_dac *p_dac; 852 int found = 0; 853 854 p_dac = kzalloc_obj(struct radeon_encoder_primary_dac); 855 856 if (!p_dac) 857 return NULL; 858 859 /* check CRT table */ 860 dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); 861 if (dac_info) { 862 rev = RBIOS8(dac_info) & 0x3; 863 if (rev < 2) { 864 bg = RBIOS8(dac_info + 0x2) & 0xf; 865 dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf; 866 p_dac->ps2_pdac_adj = (bg << 8) | (dac); 867 } else { 868 bg = RBIOS8(dac_info + 0x2) & 0xf; 869 dac = RBIOS8(dac_info + 0x3) & 0xf; 870 p_dac->ps2_pdac_adj = (bg << 8) | (dac); 871 } 872 /* if the values are zeros, use the table */ 873 if ((dac == 0) || (bg == 0)) 874 found = 0; 875 else 876 found = 1; 877 } 878 879 /* quirks */ 880 /* Radeon 7000 (RV100) */ 881 if (((rdev->pdev->device == 0x5159) && 882 (rdev->pdev->subsystem_vendor == 0x174B) && 883 (rdev->pdev->subsystem_device == 0x7c28)) || 884 /* Radeon 9100 (R200) */ 885 ((rdev->pdev->device == 0x514D) && 886 (rdev->pdev->subsystem_vendor == 0x174B) && 887 (rdev->pdev->subsystem_device == 0x7149))) { 888 /* vbios value is bad, use the default */ 889 found = 0; 890 } 891 892 if (!found) /* fallback to defaults */ 893 radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac); 894 895 return p_dac; 896 } 897 898 enum radeon_tv_std 899 radeon_combios_get_tv_info(struct radeon_device *rdev) 900 { 901 struct drm_device *dev = rdev_to_drm(rdev); 902 uint16_t tv_info; 903 enum radeon_tv_std tv_std = TV_STD_NTSC; 904 905 tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); 906 if (tv_info) { 907 if (RBIOS8(tv_info + 6) == 'T') { 908 switch (RBIOS8(tv_info + 7) & 0xf) { 909 case 1: 910 tv_std = TV_STD_NTSC; 911 DRM_DEBUG_KMS("Default TV standard: NTSC\n"); 912 break; 913 case 2: 914 tv_std = TV_STD_PAL; 915 DRM_DEBUG_KMS("Default TV standard: PAL\n"); 916 break; 917 case 3: 918 tv_std = TV_STD_PAL_M; 919 DRM_DEBUG_KMS("Default TV standard: PAL-M\n"); 920 break; 921 case 4: 922 tv_std = TV_STD_PAL_60; 923 DRM_DEBUG_KMS("Default TV standard: PAL-60\n"); 924 break; 925 case 5: 926 tv_std = TV_STD_NTSC_J; 927 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n"); 928 break; 929 case 6: 930 tv_std = TV_STD_SCART_PAL; 931 DRM_DEBUG_KMS("Default TV standard: SCART-PAL\n"); 932 break; 933 default: 934 tv_std = TV_STD_NTSC; 935 DRM_DEBUG_KMS 936 ("Unknown TV standard; defaulting to NTSC\n"); 937 break; 938 } 939 940 switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) { 941 case 0: 942 DRM_DEBUG_KMS("29.498928713 MHz TV ref clk\n"); 943 break; 944 case 1: 945 DRM_DEBUG_KMS("28.636360000 MHz TV ref clk\n"); 946 break; 947 case 2: 948 DRM_DEBUG_KMS("14.318180000 MHz TV ref clk\n"); 949 break; 950 case 3: 951 DRM_DEBUG_KMS("27.000000000 MHz TV ref clk\n"); 952 break; 953 default: 954 break; 955 } 956 } 957 } 958 return tv_std; 959 } 960 961 static const uint32_t default_tvdac_adj[CHIP_LAST] = { 962 0x00000000, /* r100 */ 963 0x00280000, /* rv100 */ 964 0x00000000, /* rs100 */ 965 0x00880000, /* rv200 */ 966 0x00000000, /* rs200 */ 967 0x00000000, /* r200 */ 968 0x00770000, /* rv250 */ 969 0x00290000, /* rs300 */ 970 0x00560000, /* rv280 */ 971 0x00780000, /* r300 */ 972 0x00770000, /* r350 */ 973 0x00780000, /* rv350 */ 974 0x00780000, /* rv380 */ 975 0x01080000, /* r420 */ 976 0x01080000, /* r423 */ 977 0x01080000, /* rv410 */ 978 0x00780000, /* rs400 */ 979 0x00780000, /* rs480 */ 980 }; 981 982 static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev, 983 struct radeon_encoder_tv_dac *tv_dac) 984 { 985 tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family]; 986 if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250)) 987 tv_dac->ps2_tvdac_adj = 0x00880000; 988 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; 989 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; 990 return; 991 } 992 993 struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct 994 radeon_encoder 995 *encoder) 996 { 997 struct drm_device *dev = encoder->base.dev; 998 struct radeon_device *rdev = dev->dev_private; 999 uint16_t dac_info; 1000 uint8_t rev, bg, dac; 1001 struct radeon_encoder_tv_dac *tv_dac; 1002 int found = 0; 1003 1004 tv_dac = kzalloc_obj(struct radeon_encoder_tv_dac); 1005 if (!tv_dac) 1006 return NULL; 1007 1008 /* first check TV table */ 1009 dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); 1010 if (dac_info) { 1011 rev = RBIOS8(dac_info + 0x3); 1012 if (rev > 4) { 1013 bg = RBIOS8(dac_info + 0xc) & 0xf; 1014 dac = RBIOS8(dac_info + 0xd) & 0xf; 1015 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20); 1016 1017 bg = RBIOS8(dac_info + 0xe) & 0xf; 1018 dac = RBIOS8(dac_info + 0xf) & 0xf; 1019 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20); 1020 1021 bg = RBIOS8(dac_info + 0x10) & 0xf; 1022 dac = RBIOS8(dac_info + 0x11) & 0xf; 1023 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); 1024 /* if the values are all zeros, use the table */ 1025 if (tv_dac->ps2_tvdac_adj) 1026 found = 1; 1027 } else if (rev > 1) { 1028 bg = RBIOS8(dac_info + 0xc) & 0xf; 1029 dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf; 1030 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20); 1031 1032 bg = RBIOS8(dac_info + 0xd) & 0xf; 1033 dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf; 1034 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20); 1035 1036 bg = RBIOS8(dac_info + 0xe) & 0xf; 1037 dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf; 1038 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); 1039 /* if the values are all zeros, use the table */ 1040 if (tv_dac->ps2_tvdac_adj) 1041 found = 1; 1042 } 1043 tv_dac->tv_std = radeon_combios_get_tv_info(rdev); 1044 } 1045 if (!found) { 1046 /* then check CRT table */ 1047 dac_info = 1048 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); 1049 if (dac_info) { 1050 rev = RBIOS8(dac_info) & 0x3; 1051 if (rev < 2) { 1052 bg = RBIOS8(dac_info + 0x3) & 0xf; 1053 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf; 1054 tv_dac->ps2_tvdac_adj = 1055 (bg << 16) | (dac << 20); 1056 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; 1057 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; 1058 /* if the values are all zeros, use the table */ 1059 if (tv_dac->ps2_tvdac_adj) 1060 found = 1; 1061 } else { 1062 bg = RBIOS8(dac_info + 0x4) & 0xf; 1063 dac = RBIOS8(dac_info + 0x5) & 0xf; 1064 tv_dac->ps2_tvdac_adj = 1065 (bg << 16) | (dac << 20); 1066 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; 1067 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; 1068 /* if the values are all zeros, use the table */ 1069 if (tv_dac->ps2_tvdac_adj) 1070 found = 1; 1071 } 1072 } else { 1073 DRM_INFO("No TV DAC info found in BIOS\n"); 1074 } 1075 } 1076 1077 if (!found) /* fallback to defaults */ 1078 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac); 1079 1080 return tv_dac; 1081 } 1082 1083 static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct 1084 radeon_device 1085 *rdev) 1086 { 1087 struct radeon_encoder_lvds *lvds; 1088 uint32_t fp_vert_stretch, fp_horz_stretch; 1089 uint32_t ppll_div_sel, ppll_val; 1090 uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL); 1091 1092 lvds = kzalloc_obj(struct radeon_encoder_lvds); 1093 1094 if (!lvds) 1095 return NULL; 1096 1097 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH); 1098 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH); 1099 1100 /* These should be fail-safe defaults, fingers crossed */ 1101 lvds->panel_pwr_delay = 200; 1102 lvds->panel_vcc_delay = 2000; 1103 1104 lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); 1105 lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf; 1106 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf; 1107 1108 if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE) 1109 lvds->native_mode.vdisplay = 1110 ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >> 1111 RADEON_VERT_PANEL_SHIFT) + 1; 1112 else 1113 lvds->native_mode.vdisplay = 1114 (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1; 1115 1116 if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE) 1117 lvds->native_mode.hdisplay = 1118 (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >> 1119 RADEON_HORZ_PANEL_SHIFT) + 1) * 8; 1120 else 1121 lvds->native_mode.hdisplay = 1122 ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8; 1123 1124 if ((lvds->native_mode.hdisplay < 640) || 1125 (lvds->native_mode.vdisplay < 480)) { 1126 lvds->native_mode.hdisplay = 640; 1127 lvds->native_mode.vdisplay = 480; 1128 } 1129 1130 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3; 1131 ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel); 1132 if ((ppll_val & 0x000707ff) == 0x1bb) 1133 lvds->use_bios_dividers = false; 1134 else { 1135 lvds->panel_ref_divider = 1136 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff; 1137 lvds->panel_post_divider = (ppll_val >> 16) & 0x7; 1138 lvds->panel_fb_divider = ppll_val & 0x7ff; 1139 1140 if ((lvds->panel_ref_divider != 0) && 1141 (lvds->panel_fb_divider > 3)) 1142 lvds->use_bios_dividers = true; 1143 } 1144 lvds->panel_vcc_delay = 200; 1145 1146 DRM_INFO("Panel info derived from registers\n"); 1147 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay, 1148 lvds->native_mode.vdisplay); 1149 1150 return lvds; 1151 } 1152 1153 struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder 1154 *encoder) 1155 { 1156 struct drm_device *dev = encoder->base.dev; 1157 struct radeon_device *rdev = dev->dev_private; 1158 uint16_t lcd_info; 1159 uint32_t panel_setup; 1160 char stmp[30]; 1161 int tmp, i; 1162 struct radeon_encoder_lvds *lvds = NULL; 1163 1164 lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE); 1165 1166 if (lcd_info) { 1167 lvds = kzalloc_obj(struct radeon_encoder_lvds); 1168 1169 if (!lvds) 1170 return NULL; 1171 1172 for (i = 0; i < 24; i++) 1173 stmp[i] = RBIOS8(lcd_info + i + 1); 1174 stmp[24] = 0; 1175 1176 DRM_INFO("Panel ID String: %s\n", stmp); 1177 1178 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19); 1179 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b); 1180 1181 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay, 1182 lvds->native_mode.vdisplay); 1183 1184 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c); 1185 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000); 1186 1187 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24); 1188 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf; 1189 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf; 1190 1191 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e); 1192 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30); 1193 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31); 1194 if ((lvds->panel_ref_divider != 0) && 1195 (lvds->panel_fb_divider > 3)) 1196 lvds->use_bios_dividers = true; 1197 1198 panel_setup = RBIOS32(lcd_info + 0x39); 1199 lvds->lvds_gen_cntl = 0xff00; 1200 if (panel_setup & 0x1) 1201 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT; 1202 1203 if ((panel_setup >> 4) & 0x1) 1204 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE; 1205 1206 switch ((panel_setup >> 8) & 0x7) { 1207 case 0: 1208 lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM; 1209 break; 1210 case 1: 1211 lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY; 1212 break; 1213 case 2: 1214 lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY; 1215 break; 1216 default: 1217 break; 1218 } 1219 1220 if ((panel_setup >> 16) & 0x1) 1221 lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW; 1222 1223 if ((panel_setup >> 17) & 0x1) 1224 lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW; 1225 1226 if ((panel_setup >> 18) & 0x1) 1227 lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW; 1228 1229 if ((panel_setup >> 23) & 0x1) 1230 lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL; 1231 1232 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000); 1233 1234 for (i = 0; i < 32; i++) { 1235 tmp = RBIOS16(lcd_info + 64 + i * 2); 1236 if (tmp == 0) 1237 break; 1238 1239 if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) && 1240 (RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) { 1241 u32 hss = (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8; 1242 1243 if (hss > lvds->native_mode.hdisplay) 1244 hss = (10 - 1) * 8; 1245 1246 lvds->native_mode.htotal = lvds->native_mode.hdisplay + 1247 (RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8; 1248 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay + 1249 hss; 1250 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start + 1251 (RBIOS8(tmp + 23) * 8); 1252 1253 lvds->native_mode.vtotal = lvds->native_mode.vdisplay + 1254 (RBIOS16(tmp + 24) - RBIOS16(tmp + 26)); 1255 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay + 1256 ((RBIOS16(tmp + 28) & 0x7ff) - RBIOS16(tmp + 26)); 1257 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start + 1258 ((RBIOS16(tmp + 28) & 0xf800) >> 11); 1259 1260 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10; 1261 lvds->native_mode.flags = 0; 1262 /* set crtc values */ 1263 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V); 1264 1265 } 1266 } 1267 } else { 1268 DRM_INFO("No panel info found in BIOS\n"); 1269 lvds = radeon_legacy_get_lvds_info_from_regs(rdev); 1270 } 1271 1272 if (lvds) 1273 encoder->native_mode = lvds->native_mode; 1274 return lvds; 1275 } 1276 1277 static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = { 1278 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */ 1279 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */ 1280 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */ 1281 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */ 1282 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */ 1283 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */ 1284 {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */ 1285 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */ 1286 {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */ 1287 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */ 1288 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */ 1289 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */ 1290 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */ 1291 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */ 1292 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */ 1293 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */ 1294 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */ 1295 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */ 1296 }; 1297 1298 bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, 1299 struct radeon_encoder_int_tmds *tmds) 1300 { 1301 struct drm_device *dev = encoder->base.dev; 1302 struct radeon_device *rdev = dev->dev_private; 1303 int i; 1304 1305 for (i = 0; i < 4; i++) { 1306 tmds->tmds_pll[i].value = 1307 default_tmds_pll[rdev->family][i].value; 1308 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq; 1309 } 1310 1311 return true; 1312 } 1313 1314 bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, 1315 struct radeon_encoder_int_tmds *tmds) 1316 { 1317 struct drm_device *dev = encoder->base.dev; 1318 struct radeon_device *rdev = dev->dev_private; 1319 uint16_t tmds_info; 1320 int i, n; 1321 uint8_t ver; 1322 1323 tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE); 1324 1325 if (tmds_info) { 1326 ver = RBIOS8(tmds_info); 1327 DRM_DEBUG_KMS("DFP table revision: %d\n", ver); 1328 if (ver == 3) { 1329 n = RBIOS8(tmds_info + 5) + 1; 1330 if (n > 4) 1331 n = 4; 1332 for (i = 0; i < n; i++) { 1333 tmds->tmds_pll[i].value = 1334 RBIOS32(tmds_info + i * 10 + 0x08); 1335 tmds->tmds_pll[i].freq = 1336 RBIOS16(tmds_info + i * 10 + 0x10); 1337 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n", 1338 tmds->tmds_pll[i].freq, 1339 tmds->tmds_pll[i].value); 1340 } 1341 } else if (ver == 4) { 1342 int stride = 0; 1343 n = RBIOS8(tmds_info + 5) + 1; 1344 if (n > 4) 1345 n = 4; 1346 for (i = 0; i < n; i++) { 1347 tmds->tmds_pll[i].value = 1348 RBIOS32(tmds_info + stride + 0x08); 1349 tmds->tmds_pll[i].freq = 1350 RBIOS16(tmds_info + stride + 0x10); 1351 if (i == 0) 1352 stride += 10; 1353 else 1354 stride += 6; 1355 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n", 1356 tmds->tmds_pll[i].freq, 1357 tmds->tmds_pll[i].value); 1358 } 1359 } 1360 } else { 1361 DRM_INFO("No TMDS info found in BIOS\n"); 1362 return false; 1363 } 1364 return true; 1365 } 1366 1367 bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder, 1368 struct radeon_encoder_ext_tmds *tmds) 1369 { 1370 struct drm_device *dev = encoder->base.dev; 1371 struct radeon_device *rdev = dev->dev_private; 1372 struct radeon_i2c_bus_rec i2c_bus; 1373 1374 /* default for macs */ 1375 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 1376 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 1377 1378 /* XXX some macs have duallink chips */ 1379 switch (rdev->mode_info.connector_table) { 1380 case CT_POWERBOOK_EXTERNAL: 1381 case CT_MINI_EXTERNAL: 1382 default: 1383 tmds->dvo_chip = DVO_SIL164; 1384 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */ 1385 break; 1386 } 1387 1388 return true; 1389 } 1390 1391 bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder, 1392 struct radeon_encoder_ext_tmds *tmds) 1393 { 1394 struct drm_device *dev = encoder->base.dev; 1395 struct radeon_device *rdev = dev->dev_private; 1396 uint16_t offset; 1397 uint8_t ver; 1398 enum radeon_combios_ddc gpio; 1399 struct radeon_i2c_bus_rec i2c_bus; 1400 1401 tmds->i2c_bus = NULL; 1402 if (rdev->flags & RADEON_IS_IGP) { 1403 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 1404 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 1405 tmds->dvo_chip = DVO_SIL164; 1406 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */ 1407 } else { 1408 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); 1409 if (offset) { 1410 ver = RBIOS8(offset); 1411 DRM_DEBUG_KMS("External TMDS Table revision: %d\n", ver); 1412 tmds->slave_addr = RBIOS8(offset + 4 + 2); 1413 tmds->slave_addr >>= 1; /* 7 bit addressing */ 1414 gpio = RBIOS8(offset + 4 + 3); 1415 if (gpio == DDC_LCD) { 1416 /* MM i2c */ 1417 i2c_bus.valid = true; 1418 i2c_bus.hw_capable = true; 1419 i2c_bus.mm_i2c = true; 1420 i2c_bus.i2c_id = 0xa0; 1421 } else 1422 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0); 1423 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 1424 } 1425 } 1426 1427 if (!tmds->i2c_bus) { 1428 DRM_INFO("No valid Ext TMDS info found in BIOS\n"); 1429 return false; 1430 } 1431 1432 return true; 1433 } 1434 1435 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev) 1436 { 1437 struct radeon_device *rdev = dev->dev_private; 1438 struct radeon_i2c_bus_rec ddc_i2c; 1439 struct radeon_hpd hpd; 1440 1441 rdev->mode_info.connector_table = radeon_connector_table; 1442 if (rdev->mode_info.connector_table == CT_NONE) { 1443 #ifdef CONFIG_PPC_PMAC 1444 if (of_machine_is_compatible("PowerBook3,3")) { 1445 /* powerbook with VGA */ 1446 rdev->mode_info.connector_table = CT_POWERBOOK_VGA; 1447 } else if (of_machine_is_compatible("PowerBook3,4") || 1448 of_machine_is_compatible("PowerBook3,5")) { 1449 /* powerbook with internal tmds */ 1450 rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL; 1451 } else if (of_machine_is_compatible("PowerBook5,1") || 1452 of_machine_is_compatible("PowerBook5,2") || 1453 of_machine_is_compatible("PowerBook5,3") || 1454 of_machine_is_compatible("PowerBook5,4") || 1455 of_machine_is_compatible("PowerBook5,5")) { 1456 /* powerbook with external single link tmds (sil164) */ 1457 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL; 1458 } else if (of_machine_is_compatible("PowerBook5,6")) { 1459 /* powerbook with external dual or single link tmds */ 1460 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL; 1461 } else if (of_machine_is_compatible("PowerBook5,7") || 1462 of_machine_is_compatible("PowerBook5,8") || 1463 of_machine_is_compatible("PowerBook5,9")) { 1464 /* PowerBook6,2 ? */ 1465 /* powerbook with external dual link tmds (sil1178?) */ 1466 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL; 1467 } else if (of_machine_is_compatible("PowerBook4,1") || 1468 of_machine_is_compatible("PowerBook4,2") || 1469 of_machine_is_compatible("PowerBook4,3") || 1470 of_machine_is_compatible("PowerBook6,3") || 1471 of_machine_is_compatible("PowerBook6,5") || 1472 of_machine_is_compatible("PowerBook6,7")) { 1473 /* ibook */ 1474 rdev->mode_info.connector_table = CT_IBOOK; 1475 } else if (of_machine_is_compatible("PowerMac3,5")) { 1476 /* PowerMac G4 Silver radeon 7500 */ 1477 rdev->mode_info.connector_table = CT_MAC_G4_SILVER; 1478 } else if (of_machine_is_compatible("PowerMac4,4")) { 1479 /* emac */ 1480 rdev->mode_info.connector_table = CT_EMAC; 1481 } else if (of_machine_is_compatible("PowerMac10,1")) { 1482 /* mini with internal tmds */ 1483 rdev->mode_info.connector_table = CT_MINI_INTERNAL; 1484 } else if (of_machine_is_compatible("PowerMac10,2")) { 1485 /* mini with external tmds */ 1486 rdev->mode_info.connector_table = CT_MINI_EXTERNAL; 1487 } else if (of_machine_is_compatible("PowerMac12,1")) { 1488 /* PowerMac8,1 ? */ 1489 /* imac g5 isight */ 1490 rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT; 1491 } else if ((rdev->pdev->device == 0x4a48) && 1492 (rdev->pdev->subsystem_vendor == 0x1002) && 1493 (rdev->pdev->subsystem_device == 0x4a48)) { 1494 /* Mac X800 */ 1495 rdev->mode_info.connector_table = CT_MAC_X800; 1496 } else if ((of_machine_is_compatible("PowerMac7,2") || 1497 of_machine_is_compatible("PowerMac7,3")) && 1498 (rdev->pdev->device == 0x4150) && 1499 (rdev->pdev->subsystem_vendor == 0x1002) && 1500 (rdev->pdev->subsystem_device == 0x4150)) { 1501 /* Mac G5 tower 9600 */ 1502 rdev->mode_info.connector_table = CT_MAC_G5_9600; 1503 } else if ((rdev->pdev->device == 0x4c66) && 1504 (rdev->pdev->subsystem_vendor == 0x1002) && 1505 (rdev->pdev->subsystem_device == 0x4c66)) { 1506 /* SAM440ep RV250 embedded board */ 1507 rdev->mode_info.connector_table = CT_SAM440EP; 1508 } else 1509 #endif /* CONFIG_PPC_PMAC */ 1510 #ifdef CONFIG_PPC64 1511 if (ASIC_IS_RN50(rdev)) 1512 rdev->mode_info.connector_table = CT_RN50_POWER; 1513 else 1514 #endif 1515 rdev->mode_info.connector_table = CT_GENERIC; 1516 } 1517 1518 switch (rdev->mode_info.connector_table) { 1519 case CT_GENERIC: 1520 DRM_INFO("Connector Table: %d (generic)\n", 1521 rdev->mode_info.connector_table); 1522 /* these are the most common settings */ 1523 if (rdev->flags & RADEON_SINGLE_CRTC) { 1524 /* VGA - primary dac */ 1525 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1526 hpd.hpd = RADEON_HPD_NONE; 1527 radeon_add_legacy_encoder(dev, 1528 radeon_get_encoder_enum(dev, 1529 ATOM_DEVICE_CRT1_SUPPORT, 1530 1), 1531 ATOM_DEVICE_CRT1_SUPPORT); 1532 radeon_add_legacy_connector(dev, 0, 1533 ATOM_DEVICE_CRT1_SUPPORT, 1534 DRM_MODE_CONNECTOR_VGA, 1535 &ddc_i2c, 1536 CONNECTOR_OBJECT_ID_VGA, 1537 &hpd); 1538 } else if (rdev->flags & RADEON_IS_MOBILITY) { 1539 /* LVDS */ 1540 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0); 1541 hpd.hpd = RADEON_HPD_NONE; 1542 radeon_add_legacy_encoder(dev, 1543 radeon_get_encoder_enum(dev, 1544 ATOM_DEVICE_LCD1_SUPPORT, 1545 0), 1546 ATOM_DEVICE_LCD1_SUPPORT); 1547 radeon_add_legacy_connector(dev, 0, 1548 ATOM_DEVICE_LCD1_SUPPORT, 1549 DRM_MODE_CONNECTOR_LVDS, 1550 &ddc_i2c, 1551 CONNECTOR_OBJECT_ID_LVDS, 1552 &hpd); 1553 1554 /* VGA - primary dac */ 1555 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1556 hpd.hpd = RADEON_HPD_NONE; 1557 radeon_add_legacy_encoder(dev, 1558 radeon_get_encoder_enum(dev, 1559 ATOM_DEVICE_CRT1_SUPPORT, 1560 1), 1561 ATOM_DEVICE_CRT1_SUPPORT); 1562 radeon_add_legacy_connector(dev, 1, 1563 ATOM_DEVICE_CRT1_SUPPORT, 1564 DRM_MODE_CONNECTOR_VGA, 1565 &ddc_i2c, 1566 CONNECTOR_OBJECT_ID_VGA, 1567 &hpd); 1568 } else { 1569 /* DVI-I - tv dac, int tmds */ 1570 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1571 hpd.hpd = RADEON_HPD_1; 1572 radeon_add_legacy_encoder(dev, 1573 radeon_get_encoder_enum(dev, 1574 ATOM_DEVICE_DFP1_SUPPORT, 1575 0), 1576 ATOM_DEVICE_DFP1_SUPPORT); 1577 radeon_add_legacy_encoder(dev, 1578 radeon_get_encoder_enum(dev, 1579 ATOM_DEVICE_CRT2_SUPPORT, 1580 2), 1581 ATOM_DEVICE_CRT2_SUPPORT); 1582 radeon_add_legacy_connector(dev, 0, 1583 ATOM_DEVICE_DFP1_SUPPORT | 1584 ATOM_DEVICE_CRT2_SUPPORT, 1585 DRM_MODE_CONNECTOR_DVII, 1586 &ddc_i2c, 1587 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 1588 &hpd); 1589 1590 /* VGA - primary dac */ 1591 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1592 hpd.hpd = RADEON_HPD_NONE; 1593 radeon_add_legacy_encoder(dev, 1594 radeon_get_encoder_enum(dev, 1595 ATOM_DEVICE_CRT1_SUPPORT, 1596 1), 1597 ATOM_DEVICE_CRT1_SUPPORT); 1598 radeon_add_legacy_connector(dev, 1, 1599 ATOM_DEVICE_CRT1_SUPPORT, 1600 DRM_MODE_CONNECTOR_VGA, 1601 &ddc_i2c, 1602 CONNECTOR_OBJECT_ID_VGA, 1603 &hpd); 1604 } 1605 1606 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) { 1607 /* TV - tv dac */ 1608 ddc_i2c.valid = false; 1609 hpd.hpd = RADEON_HPD_NONE; 1610 radeon_add_legacy_encoder(dev, 1611 radeon_get_encoder_enum(dev, 1612 ATOM_DEVICE_TV1_SUPPORT, 1613 2), 1614 ATOM_DEVICE_TV1_SUPPORT); 1615 radeon_add_legacy_connector(dev, 2, 1616 ATOM_DEVICE_TV1_SUPPORT, 1617 DRM_MODE_CONNECTOR_SVIDEO, 1618 &ddc_i2c, 1619 CONNECTOR_OBJECT_ID_SVIDEO, 1620 &hpd); 1621 } 1622 break; 1623 case CT_IBOOK: 1624 DRM_INFO("Connector Table: %d (ibook)\n", 1625 rdev->mode_info.connector_table); 1626 /* LVDS */ 1627 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1628 hpd.hpd = RADEON_HPD_NONE; 1629 radeon_add_legacy_encoder(dev, 1630 radeon_get_encoder_enum(dev, 1631 ATOM_DEVICE_LCD1_SUPPORT, 1632 0), 1633 ATOM_DEVICE_LCD1_SUPPORT); 1634 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 1635 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 1636 CONNECTOR_OBJECT_ID_LVDS, 1637 &hpd); 1638 /* VGA - TV DAC */ 1639 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1640 hpd.hpd = RADEON_HPD_NONE; 1641 radeon_add_legacy_encoder(dev, 1642 radeon_get_encoder_enum(dev, 1643 ATOM_DEVICE_CRT2_SUPPORT, 1644 2), 1645 ATOM_DEVICE_CRT2_SUPPORT); 1646 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, 1647 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1648 CONNECTOR_OBJECT_ID_VGA, 1649 &hpd); 1650 /* TV - TV DAC */ 1651 ddc_i2c.valid = false; 1652 hpd.hpd = RADEON_HPD_NONE; 1653 radeon_add_legacy_encoder(dev, 1654 radeon_get_encoder_enum(dev, 1655 ATOM_DEVICE_TV1_SUPPORT, 1656 2), 1657 ATOM_DEVICE_TV1_SUPPORT); 1658 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1659 DRM_MODE_CONNECTOR_SVIDEO, 1660 &ddc_i2c, 1661 CONNECTOR_OBJECT_ID_SVIDEO, 1662 &hpd); 1663 break; 1664 case CT_POWERBOOK_EXTERNAL: 1665 DRM_INFO("Connector Table: %d (powerbook external tmds)\n", 1666 rdev->mode_info.connector_table); 1667 /* LVDS */ 1668 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1669 hpd.hpd = RADEON_HPD_NONE; 1670 radeon_add_legacy_encoder(dev, 1671 radeon_get_encoder_enum(dev, 1672 ATOM_DEVICE_LCD1_SUPPORT, 1673 0), 1674 ATOM_DEVICE_LCD1_SUPPORT); 1675 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 1676 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 1677 CONNECTOR_OBJECT_ID_LVDS, 1678 &hpd); 1679 /* DVI-I - primary dac, ext tmds */ 1680 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1681 hpd.hpd = RADEON_HPD_2; /* ??? */ 1682 radeon_add_legacy_encoder(dev, 1683 radeon_get_encoder_enum(dev, 1684 ATOM_DEVICE_DFP2_SUPPORT, 1685 0), 1686 ATOM_DEVICE_DFP2_SUPPORT); 1687 radeon_add_legacy_encoder(dev, 1688 radeon_get_encoder_enum(dev, 1689 ATOM_DEVICE_CRT1_SUPPORT, 1690 1), 1691 ATOM_DEVICE_CRT1_SUPPORT); 1692 /* XXX some are SL */ 1693 radeon_add_legacy_connector(dev, 1, 1694 ATOM_DEVICE_DFP2_SUPPORT | 1695 ATOM_DEVICE_CRT1_SUPPORT, 1696 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 1697 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, 1698 &hpd); 1699 /* TV - TV DAC */ 1700 ddc_i2c.valid = false; 1701 hpd.hpd = RADEON_HPD_NONE; 1702 radeon_add_legacy_encoder(dev, 1703 radeon_get_encoder_enum(dev, 1704 ATOM_DEVICE_TV1_SUPPORT, 1705 2), 1706 ATOM_DEVICE_TV1_SUPPORT); 1707 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1708 DRM_MODE_CONNECTOR_SVIDEO, 1709 &ddc_i2c, 1710 CONNECTOR_OBJECT_ID_SVIDEO, 1711 &hpd); 1712 break; 1713 case CT_POWERBOOK_INTERNAL: 1714 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n", 1715 rdev->mode_info.connector_table); 1716 /* LVDS */ 1717 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1718 hpd.hpd = RADEON_HPD_NONE; 1719 radeon_add_legacy_encoder(dev, 1720 radeon_get_encoder_enum(dev, 1721 ATOM_DEVICE_LCD1_SUPPORT, 1722 0), 1723 ATOM_DEVICE_LCD1_SUPPORT); 1724 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 1725 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 1726 CONNECTOR_OBJECT_ID_LVDS, 1727 &hpd); 1728 /* DVI-I - primary dac, int tmds */ 1729 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1730 hpd.hpd = RADEON_HPD_1; /* ??? */ 1731 radeon_add_legacy_encoder(dev, 1732 radeon_get_encoder_enum(dev, 1733 ATOM_DEVICE_DFP1_SUPPORT, 1734 0), 1735 ATOM_DEVICE_DFP1_SUPPORT); 1736 radeon_add_legacy_encoder(dev, 1737 radeon_get_encoder_enum(dev, 1738 ATOM_DEVICE_CRT1_SUPPORT, 1739 1), 1740 ATOM_DEVICE_CRT1_SUPPORT); 1741 radeon_add_legacy_connector(dev, 1, 1742 ATOM_DEVICE_DFP1_SUPPORT | 1743 ATOM_DEVICE_CRT1_SUPPORT, 1744 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 1745 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 1746 &hpd); 1747 /* TV - TV DAC */ 1748 ddc_i2c.valid = false; 1749 hpd.hpd = RADEON_HPD_NONE; 1750 radeon_add_legacy_encoder(dev, 1751 radeon_get_encoder_enum(dev, 1752 ATOM_DEVICE_TV1_SUPPORT, 1753 2), 1754 ATOM_DEVICE_TV1_SUPPORT); 1755 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1756 DRM_MODE_CONNECTOR_SVIDEO, 1757 &ddc_i2c, 1758 CONNECTOR_OBJECT_ID_SVIDEO, 1759 &hpd); 1760 break; 1761 case CT_POWERBOOK_VGA: 1762 DRM_INFO("Connector Table: %d (powerbook vga)\n", 1763 rdev->mode_info.connector_table); 1764 /* LVDS */ 1765 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1766 hpd.hpd = RADEON_HPD_NONE; 1767 radeon_add_legacy_encoder(dev, 1768 radeon_get_encoder_enum(dev, 1769 ATOM_DEVICE_LCD1_SUPPORT, 1770 0), 1771 ATOM_DEVICE_LCD1_SUPPORT); 1772 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 1773 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 1774 CONNECTOR_OBJECT_ID_LVDS, 1775 &hpd); 1776 /* VGA - primary dac */ 1777 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1778 hpd.hpd = RADEON_HPD_NONE; 1779 radeon_add_legacy_encoder(dev, 1780 radeon_get_encoder_enum(dev, 1781 ATOM_DEVICE_CRT1_SUPPORT, 1782 1), 1783 ATOM_DEVICE_CRT1_SUPPORT); 1784 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT, 1785 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1786 CONNECTOR_OBJECT_ID_VGA, 1787 &hpd); 1788 /* TV - TV DAC */ 1789 ddc_i2c.valid = false; 1790 hpd.hpd = RADEON_HPD_NONE; 1791 radeon_add_legacy_encoder(dev, 1792 radeon_get_encoder_enum(dev, 1793 ATOM_DEVICE_TV1_SUPPORT, 1794 2), 1795 ATOM_DEVICE_TV1_SUPPORT); 1796 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1797 DRM_MODE_CONNECTOR_SVIDEO, 1798 &ddc_i2c, 1799 CONNECTOR_OBJECT_ID_SVIDEO, 1800 &hpd); 1801 break; 1802 case CT_MINI_EXTERNAL: 1803 DRM_INFO("Connector Table: %d (mini external tmds)\n", 1804 rdev->mode_info.connector_table); 1805 /* DVI-I - tv dac, ext tmds */ 1806 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); 1807 hpd.hpd = RADEON_HPD_2; /* ??? */ 1808 radeon_add_legacy_encoder(dev, 1809 radeon_get_encoder_enum(dev, 1810 ATOM_DEVICE_DFP2_SUPPORT, 1811 0), 1812 ATOM_DEVICE_DFP2_SUPPORT); 1813 radeon_add_legacy_encoder(dev, 1814 radeon_get_encoder_enum(dev, 1815 ATOM_DEVICE_CRT2_SUPPORT, 1816 2), 1817 ATOM_DEVICE_CRT2_SUPPORT); 1818 /* XXX are any DL? */ 1819 radeon_add_legacy_connector(dev, 0, 1820 ATOM_DEVICE_DFP2_SUPPORT | 1821 ATOM_DEVICE_CRT2_SUPPORT, 1822 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 1823 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 1824 &hpd); 1825 /* TV - TV DAC */ 1826 ddc_i2c.valid = false; 1827 hpd.hpd = RADEON_HPD_NONE; 1828 radeon_add_legacy_encoder(dev, 1829 radeon_get_encoder_enum(dev, 1830 ATOM_DEVICE_TV1_SUPPORT, 1831 2), 1832 ATOM_DEVICE_TV1_SUPPORT); 1833 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT, 1834 DRM_MODE_CONNECTOR_SVIDEO, 1835 &ddc_i2c, 1836 CONNECTOR_OBJECT_ID_SVIDEO, 1837 &hpd); 1838 break; 1839 case CT_MINI_INTERNAL: 1840 DRM_INFO("Connector Table: %d (mini internal tmds)\n", 1841 rdev->mode_info.connector_table); 1842 /* DVI-I - tv dac, int tmds */ 1843 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); 1844 hpd.hpd = RADEON_HPD_1; /* ??? */ 1845 radeon_add_legacy_encoder(dev, 1846 radeon_get_encoder_enum(dev, 1847 ATOM_DEVICE_DFP1_SUPPORT, 1848 0), 1849 ATOM_DEVICE_DFP1_SUPPORT); 1850 radeon_add_legacy_encoder(dev, 1851 radeon_get_encoder_enum(dev, 1852 ATOM_DEVICE_CRT2_SUPPORT, 1853 2), 1854 ATOM_DEVICE_CRT2_SUPPORT); 1855 radeon_add_legacy_connector(dev, 0, 1856 ATOM_DEVICE_DFP1_SUPPORT | 1857 ATOM_DEVICE_CRT2_SUPPORT, 1858 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 1859 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 1860 &hpd); 1861 /* TV - TV DAC */ 1862 ddc_i2c.valid = false; 1863 hpd.hpd = RADEON_HPD_NONE; 1864 radeon_add_legacy_encoder(dev, 1865 radeon_get_encoder_enum(dev, 1866 ATOM_DEVICE_TV1_SUPPORT, 1867 2), 1868 ATOM_DEVICE_TV1_SUPPORT); 1869 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT, 1870 DRM_MODE_CONNECTOR_SVIDEO, 1871 &ddc_i2c, 1872 CONNECTOR_OBJECT_ID_SVIDEO, 1873 &hpd); 1874 break; 1875 case CT_IMAC_G5_ISIGHT: 1876 DRM_INFO("Connector Table: %d (imac g5 isight)\n", 1877 rdev->mode_info.connector_table); 1878 /* DVI-D - int tmds */ 1879 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 1880 hpd.hpd = RADEON_HPD_1; /* ??? */ 1881 radeon_add_legacy_encoder(dev, 1882 radeon_get_encoder_enum(dev, 1883 ATOM_DEVICE_DFP1_SUPPORT, 1884 0), 1885 ATOM_DEVICE_DFP1_SUPPORT); 1886 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT, 1887 DRM_MODE_CONNECTOR_DVID, &ddc_i2c, 1888 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D, 1889 &hpd); 1890 /* VGA - tv dac */ 1891 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1892 hpd.hpd = RADEON_HPD_NONE; 1893 radeon_add_legacy_encoder(dev, 1894 radeon_get_encoder_enum(dev, 1895 ATOM_DEVICE_CRT2_SUPPORT, 1896 2), 1897 ATOM_DEVICE_CRT2_SUPPORT); 1898 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, 1899 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1900 CONNECTOR_OBJECT_ID_VGA, 1901 &hpd); 1902 /* TV - TV DAC */ 1903 ddc_i2c.valid = false; 1904 hpd.hpd = RADEON_HPD_NONE; 1905 radeon_add_legacy_encoder(dev, 1906 radeon_get_encoder_enum(dev, 1907 ATOM_DEVICE_TV1_SUPPORT, 1908 2), 1909 ATOM_DEVICE_TV1_SUPPORT); 1910 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1911 DRM_MODE_CONNECTOR_SVIDEO, 1912 &ddc_i2c, 1913 CONNECTOR_OBJECT_ID_SVIDEO, 1914 &hpd); 1915 break; 1916 case CT_EMAC: 1917 DRM_INFO("Connector Table: %d (emac)\n", 1918 rdev->mode_info.connector_table); 1919 /* VGA - primary dac */ 1920 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1921 hpd.hpd = RADEON_HPD_NONE; 1922 radeon_add_legacy_encoder(dev, 1923 radeon_get_encoder_enum(dev, 1924 ATOM_DEVICE_CRT1_SUPPORT, 1925 1), 1926 ATOM_DEVICE_CRT1_SUPPORT); 1927 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT, 1928 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1929 CONNECTOR_OBJECT_ID_VGA, 1930 &hpd); 1931 /* VGA - tv dac */ 1932 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); 1933 hpd.hpd = RADEON_HPD_NONE; 1934 radeon_add_legacy_encoder(dev, 1935 radeon_get_encoder_enum(dev, 1936 ATOM_DEVICE_CRT2_SUPPORT, 1937 2), 1938 ATOM_DEVICE_CRT2_SUPPORT); 1939 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, 1940 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1941 CONNECTOR_OBJECT_ID_VGA, 1942 &hpd); 1943 /* TV - TV DAC */ 1944 ddc_i2c.valid = false; 1945 hpd.hpd = RADEON_HPD_NONE; 1946 radeon_add_legacy_encoder(dev, 1947 radeon_get_encoder_enum(dev, 1948 ATOM_DEVICE_TV1_SUPPORT, 1949 2), 1950 ATOM_DEVICE_TV1_SUPPORT); 1951 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1952 DRM_MODE_CONNECTOR_SVIDEO, 1953 &ddc_i2c, 1954 CONNECTOR_OBJECT_ID_SVIDEO, 1955 &hpd); 1956 break; 1957 case CT_RN50_POWER: 1958 DRM_INFO("Connector Table: %d (rn50-power)\n", 1959 rdev->mode_info.connector_table); 1960 /* VGA - primary dac */ 1961 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1962 hpd.hpd = RADEON_HPD_NONE; 1963 radeon_add_legacy_encoder(dev, 1964 radeon_get_encoder_enum(dev, 1965 ATOM_DEVICE_CRT1_SUPPORT, 1966 1), 1967 ATOM_DEVICE_CRT1_SUPPORT); 1968 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT, 1969 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1970 CONNECTOR_OBJECT_ID_VGA, 1971 &hpd); 1972 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); 1973 hpd.hpd = RADEON_HPD_NONE; 1974 radeon_add_legacy_encoder(dev, 1975 radeon_get_encoder_enum(dev, 1976 ATOM_DEVICE_CRT2_SUPPORT, 1977 2), 1978 ATOM_DEVICE_CRT2_SUPPORT); 1979 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, 1980 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1981 CONNECTOR_OBJECT_ID_VGA, 1982 &hpd); 1983 break; 1984 case CT_MAC_X800: 1985 DRM_INFO("Connector Table: %d (mac x800)\n", 1986 rdev->mode_info.connector_table); 1987 /* DVI - primary dac, internal tmds */ 1988 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1989 hpd.hpd = RADEON_HPD_1; /* ??? */ 1990 radeon_add_legacy_encoder(dev, 1991 radeon_get_encoder_enum(dev, 1992 ATOM_DEVICE_DFP1_SUPPORT, 1993 0), 1994 ATOM_DEVICE_DFP1_SUPPORT); 1995 radeon_add_legacy_encoder(dev, 1996 radeon_get_encoder_enum(dev, 1997 ATOM_DEVICE_CRT1_SUPPORT, 1998 1), 1999 ATOM_DEVICE_CRT1_SUPPORT); 2000 radeon_add_legacy_connector(dev, 0, 2001 ATOM_DEVICE_DFP1_SUPPORT | 2002 ATOM_DEVICE_CRT1_SUPPORT, 2003 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 2004 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 2005 &hpd); 2006 /* DVI - tv dac, dvo */ 2007 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 2008 hpd.hpd = RADEON_HPD_2; /* ??? */ 2009 radeon_add_legacy_encoder(dev, 2010 radeon_get_encoder_enum(dev, 2011 ATOM_DEVICE_DFP2_SUPPORT, 2012 0), 2013 ATOM_DEVICE_DFP2_SUPPORT); 2014 radeon_add_legacy_encoder(dev, 2015 radeon_get_encoder_enum(dev, 2016 ATOM_DEVICE_CRT2_SUPPORT, 2017 2), 2018 ATOM_DEVICE_CRT2_SUPPORT); 2019 radeon_add_legacy_connector(dev, 1, 2020 ATOM_DEVICE_DFP2_SUPPORT | 2021 ATOM_DEVICE_CRT2_SUPPORT, 2022 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 2023 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, 2024 &hpd); 2025 break; 2026 case CT_MAC_G5_9600: 2027 DRM_INFO("Connector Table: %d (mac g5 9600)\n", 2028 rdev->mode_info.connector_table); 2029 /* DVI - tv dac, dvo */ 2030 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 2031 hpd.hpd = RADEON_HPD_1; /* ??? */ 2032 radeon_add_legacy_encoder(dev, 2033 radeon_get_encoder_enum(dev, 2034 ATOM_DEVICE_DFP2_SUPPORT, 2035 0), 2036 ATOM_DEVICE_DFP2_SUPPORT); 2037 radeon_add_legacy_encoder(dev, 2038 radeon_get_encoder_enum(dev, 2039 ATOM_DEVICE_CRT2_SUPPORT, 2040 2), 2041 ATOM_DEVICE_CRT2_SUPPORT); 2042 radeon_add_legacy_connector(dev, 0, 2043 ATOM_DEVICE_DFP2_SUPPORT | 2044 ATOM_DEVICE_CRT2_SUPPORT, 2045 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 2046 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 2047 &hpd); 2048 /* ADC - primary dac, internal tmds */ 2049 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 2050 hpd.hpd = RADEON_HPD_2; /* ??? */ 2051 radeon_add_legacy_encoder(dev, 2052 radeon_get_encoder_enum(dev, 2053 ATOM_DEVICE_DFP1_SUPPORT, 2054 0), 2055 ATOM_DEVICE_DFP1_SUPPORT); 2056 radeon_add_legacy_encoder(dev, 2057 radeon_get_encoder_enum(dev, 2058 ATOM_DEVICE_CRT1_SUPPORT, 2059 1), 2060 ATOM_DEVICE_CRT1_SUPPORT); 2061 radeon_add_legacy_connector(dev, 1, 2062 ATOM_DEVICE_DFP1_SUPPORT | 2063 ATOM_DEVICE_CRT1_SUPPORT, 2064 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 2065 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 2066 &hpd); 2067 /* TV - TV DAC */ 2068 ddc_i2c.valid = false; 2069 hpd.hpd = RADEON_HPD_NONE; 2070 radeon_add_legacy_encoder(dev, 2071 radeon_get_encoder_enum(dev, 2072 ATOM_DEVICE_TV1_SUPPORT, 2073 2), 2074 ATOM_DEVICE_TV1_SUPPORT); 2075 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 2076 DRM_MODE_CONNECTOR_SVIDEO, 2077 &ddc_i2c, 2078 CONNECTOR_OBJECT_ID_SVIDEO, 2079 &hpd); 2080 break; 2081 case CT_SAM440EP: 2082 DRM_INFO("Connector Table: %d (SAM440ep embedded board)\n", 2083 rdev->mode_info.connector_table); 2084 /* LVDS */ 2085 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0); 2086 hpd.hpd = RADEON_HPD_NONE; 2087 radeon_add_legacy_encoder(dev, 2088 radeon_get_encoder_enum(dev, 2089 ATOM_DEVICE_LCD1_SUPPORT, 2090 0), 2091 ATOM_DEVICE_LCD1_SUPPORT); 2092 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 2093 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 2094 CONNECTOR_OBJECT_ID_LVDS, 2095 &hpd); 2096 /* DVI-I - secondary dac, int tmds */ 2097 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 2098 hpd.hpd = RADEON_HPD_1; /* ??? */ 2099 radeon_add_legacy_encoder(dev, 2100 radeon_get_encoder_enum(dev, 2101 ATOM_DEVICE_DFP1_SUPPORT, 2102 0), 2103 ATOM_DEVICE_DFP1_SUPPORT); 2104 radeon_add_legacy_encoder(dev, 2105 radeon_get_encoder_enum(dev, 2106 ATOM_DEVICE_CRT2_SUPPORT, 2107 2), 2108 ATOM_DEVICE_CRT2_SUPPORT); 2109 radeon_add_legacy_connector(dev, 1, 2110 ATOM_DEVICE_DFP1_SUPPORT | 2111 ATOM_DEVICE_CRT2_SUPPORT, 2112 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 2113 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 2114 &hpd); 2115 /* VGA - primary dac */ 2116 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 2117 hpd.hpd = RADEON_HPD_NONE; 2118 radeon_add_legacy_encoder(dev, 2119 radeon_get_encoder_enum(dev, 2120 ATOM_DEVICE_CRT1_SUPPORT, 2121 1), 2122 ATOM_DEVICE_CRT1_SUPPORT); 2123 radeon_add_legacy_connector(dev, 2, 2124 ATOM_DEVICE_CRT1_SUPPORT, 2125 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 2126 CONNECTOR_OBJECT_ID_VGA, 2127 &hpd); 2128 /* TV - TV DAC */ 2129 ddc_i2c.valid = false; 2130 hpd.hpd = RADEON_HPD_NONE; 2131 radeon_add_legacy_encoder(dev, 2132 radeon_get_encoder_enum(dev, 2133 ATOM_DEVICE_TV1_SUPPORT, 2134 2), 2135 ATOM_DEVICE_TV1_SUPPORT); 2136 radeon_add_legacy_connector(dev, 3, ATOM_DEVICE_TV1_SUPPORT, 2137 DRM_MODE_CONNECTOR_SVIDEO, 2138 &ddc_i2c, 2139 CONNECTOR_OBJECT_ID_SVIDEO, 2140 &hpd); 2141 break; 2142 case CT_MAC_G4_SILVER: 2143 DRM_INFO("Connector Table: %d (mac g4 silver)\n", 2144 rdev->mode_info.connector_table); 2145 /* DVI-I - tv dac, int tmds */ 2146 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 2147 hpd.hpd = RADEON_HPD_1; /* ??? */ 2148 radeon_add_legacy_encoder(dev, 2149 radeon_get_encoder_enum(dev, 2150 ATOM_DEVICE_DFP1_SUPPORT, 2151 0), 2152 ATOM_DEVICE_DFP1_SUPPORT); 2153 radeon_add_legacy_encoder(dev, 2154 radeon_get_encoder_enum(dev, 2155 ATOM_DEVICE_CRT2_SUPPORT, 2156 2), 2157 ATOM_DEVICE_CRT2_SUPPORT); 2158 radeon_add_legacy_connector(dev, 0, 2159 ATOM_DEVICE_DFP1_SUPPORT | 2160 ATOM_DEVICE_CRT2_SUPPORT, 2161 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 2162 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 2163 &hpd); 2164 /* VGA - primary dac */ 2165 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 2166 hpd.hpd = RADEON_HPD_NONE; 2167 radeon_add_legacy_encoder(dev, 2168 radeon_get_encoder_enum(dev, 2169 ATOM_DEVICE_CRT1_SUPPORT, 2170 1), 2171 ATOM_DEVICE_CRT1_SUPPORT); 2172 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT, 2173 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 2174 CONNECTOR_OBJECT_ID_VGA, 2175 &hpd); 2176 /* TV - TV DAC */ 2177 ddc_i2c.valid = false; 2178 hpd.hpd = RADEON_HPD_NONE; 2179 radeon_add_legacy_encoder(dev, 2180 radeon_get_encoder_enum(dev, 2181 ATOM_DEVICE_TV1_SUPPORT, 2182 2), 2183 ATOM_DEVICE_TV1_SUPPORT); 2184 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 2185 DRM_MODE_CONNECTOR_SVIDEO, 2186 &ddc_i2c, 2187 CONNECTOR_OBJECT_ID_SVIDEO, 2188 &hpd); 2189 break; 2190 default: 2191 DRM_INFO("Connector table: %d (invalid)\n", 2192 rdev->mode_info.connector_table); 2193 return false; 2194 } 2195 2196 radeon_link_encoder_connector(dev); 2197 2198 return true; 2199 } 2200 2201 static bool radeon_apply_legacy_quirks(struct drm_device *dev, 2202 int bios_index, 2203 enum radeon_combios_connector 2204 *legacy_connector, 2205 struct radeon_i2c_bus_rec *ddc_i2c, 2206 struct radeon_hpd *hpd) 2207 { 2208 struct radeon_device *rdev = dev->dev_private; 2209 2210 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs, 2211 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */ 2212 if (rdev->pdev->device == 0x515e && 2213 rdev->pdev->subsystem_vendor == 0x1014) { 2214 if (*legacy_connector == CONNECTOR_CRT_LEGACY && 2215 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC) 2216 return false; 2217 } 2218 2219 /* X300 card with extra non-existent DVI port */ 2220 if (rdev->pdev->device == 0x5B60 && 2221 rdev->pdev->subsystem_vendor == 0x17af && 2222 rdev->pdev->subsystem_device == 0x201e && bios_index == 2) { 2223 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY) 2224 return false; 2225 } 2226 2227 return true; 2228 } 2229 2230 static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev) 2231 { 2232 struct radeon_device *rdev = dev->dev_private; 2233 2234 /* Acer 5102 has non-existent TV port */ 2235 if (rdev->pdev->device == 0x5975 && 2236 rdev->pdev->subsystem_vendor == 0x1025 && 2237 rdev->pdev->subsystem_device == 0x009f) 2238 return false; 2239 2240 /* HP dc5750 has non-existent TV port */ 2241 if (rdev->pdev->device == 0x5974 && 2242 rdev->pdev->subsystem_vendor == 0x103c && 2243 rdev->pdev->subsystem_device == 0x280a) 2244 return false; 2245 2246 /* MSI S270 has non-existent TV port */ 2247 if (rdev->pdev->device == 0x5955 && 2248 rdev->pdev->subsystem_vendor == 0x1462 && 2249 rdev->pdev->subsystem_device == 0x0131) 2250 return false; 2251 2252 return true; 2253 } 2254 2255 static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d) 2256 { 2257 struct radeon_device *rdev = dev->dev_private; 2258 uint32_t ext_tmds_info; 2259 2260 if (rdev->flags & RADEON_IS_IGP) { 2261 if (is_dvi_d) 2262 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D; 2263 else 2264 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 2265 } 2266 ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); 2267 if (ext_tmds_info) { 2268 uint8_t rev = RBIOS8(ext_tmds_info); 2269 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5); 2270 if (rev >= 3) { 2271 if (is_dvi_d) 2272 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D; 2273 else 2274 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I; 2275 } else { 2276 if (flags & 1) { 2277 if (is_dvi_d) 2278 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D; 2279 else 2280 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I; 2281 } 2282 } 2283 } 2284 if (is_dvi_d) 2285 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D; 2286 else 2287 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 2288 } 2289 2290 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev) 2291 { 2292 struct radeon_device *rdev = dev->dev_private; 2293 uint32_t conn_info, entry, devices; 2294 uint16_t tmp, connector_object_id; 2295 enum radeon_combios_ddc ddc_type; 2296 enum radeon_combios_connector connector; 2297 int i = 0; 2298 struct radeon_i2c_bus_rec ddc_i2c; 2299 struct radeon_hpd hpd; 2300 2301 conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE); 2302 if (conn_info) { 2303 for (i = 0; i < 4; i++) { 2304 entry = conn_info + 2 + i * 2; 2305 2306 if (!RBIOS16(entry)) 2307 break; 2308 2309 tmp = RBIOS16(entry); 2310 2311 connector = (tmp >> 12) & 0xf; 2312 2313 ddc_type = (tmp >> 8) & 0xf; 2314 if (ddc_type == 5) 2315 ddc_i2c = radeon_combios_get_i2c_info_from_table(rdev); 2316 else 2317 ddc_i2c = combios_setup_i2c_bus(rdev, ddc_type, 0, 0); 2318 2319 switch (connector) { 2320 case CONNECTOR_PROPRIETARY_LEGACY: 2321 case CONNECTOR_DVI_I_LEGACY: 2322 case CONNECTOR_DVI_D_LEGACY: 2323 if ((tmp >> 4) & 0x1) 2324 hpd.hpd = RADEON_HPD_2; 2325 else 2326 hpd.hpd = RADEON_HPD_1; 2327 break; 2328 default: 2329 hpd.hpd = RADEON_HPD_NONE; 2330 break; 2331 } 2332 2333 if (!radeon_apply_legacy_quirks(dev, i, &connector, 2334 &ddc_i2c, &hpd)) 2335 continue; 2336 2337 switch (connector) { 2338 case CONNECTOR_PROPRIETARY_LEGACY: 2339 if ((tmp >> 4) & 0x1) 2340 devices = ATOM_DEVICE_DFP2_SUPPORT; 2341 else 2342 devices = ATOM_DEVICE_DFP1_SUPPORT; 2343 radeon_add_legacy_encoder(dev, 2344 radeon_get_encoder_enum 2345 (dev, devices, 0), 2346 devices); 2347 radeon_add_legacy_connector(dev, i, devices, 2348 legacy_connector_convert 2349 [connector], 2350 &ddc_i2c, 2351 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D, 2352 &hpd); 2353 break; 2354 case CONNECTOR_CRT_LEGACY: 2355 if (tmp & 0x1) { 2356 devices = ATOM_DEVICE_CRT2_SUPPORT; 2357 radeon_add_legacy_encoder(dev, 2358 radeon_get_encoder_enum 2359 (dev, 2360 ATOM_DEVICE_CRT2_SUPPORT, 2361 2), 2362 ATOM_DEVICE_CRT2_SUPPORT); 2363 } else { 2364 devices = ATOM_DEVICE_CRT1_SUPPORT; 2365 radeon_add_legacy_encoder(dev, 2366 radeon_get_encoder_enum 2367 (dev, 2368 ATOM_DEVICE_CRT1_SUPPORT, 2369 1), 2370 ATOM_DEVICE_CRT1_SUPPORT); 2371 } 2372 radeon_add_legacy_connector(dev, 2373 i, 2374 devices, 2375 legacy_connector_convert 2376 [connector], 2377 &ddc_i2c, 2378 CONNECTOR_OBJECT_ID_VGA, 2379 &hpd); 2380 break; 2381 case CONNECTOR_DVI_I_LEGACY: 2382 devices = 0; 2383 if (tmp & 0x1) { 2384 devices |= ATOM_DEVICE_CRT2_SUPPORT; 2385 radeon_add_legacy_encoder(dev, 2386 radeon_get_encoder_enum 2387 (dev, 2388 ATOM_DEVICE_CRT2_SUPPORT, 2389 2), 2390 ATOM_DEVICE_CRT2_SUPPORT); 2391 } else { 2392 devices |= ATOM_DEVICE_CRT1_SUPPORT; 2393 radeon_add_legacy_encoder(dev, 2394 radeon_get_encoder_enum 2395 (dev, 2396 ATOM_DEVICE_CRT1_SUPPORT, 2397 1), 2398 ATOM_DEVICE_CRT1_SUPPORT); 2399 } 2400 /* RV100 board with external TDMS bit mis-set. 2401 * Actually uses internal TMDS, clear the bit. 2402 */ 2403 if (rdev->pdev->device == 0x5159 && 2404 rdev->pdev->subsystem_vendor == 0x1014 && 2405 rdev->pdev->subsystem_device == 0x029A) { 2406 tmp &= ~(1 << 4); 2407 } 2408 if ((tmp >> 4) & 0x1) { 2409 devices |= ATOM_DEVICE_DFP2_SUPPORT; 2410 radeon_add_legacy_encoder(dev, 2411 radeon_get_encoder_enum 2412 (dev, 2413 ATOM_DEVICE_DFP2_SUPPORT, 2414 0), 2415 ATOM_DEVICE_DFP2_SUPPORT); 2416 connector_object_id = combios_check_dl_dvi(dev, 0); 2417 } else { 2418 devices |= ATOM_DEVICE_DFP1_SUPPORT; 2419 radeon_add_legacy_encoder(dev, 2420 radeon_get_encoder_enum 2421 (dev, 2422 ATOM_DEVICE_DFP1_SUPPORT, 2423 0), 2424 ATOM_DEVICE_DFP1_SUPPORT); 2425 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 2426 } 2427 radeon_add_legacy_connector(dev, 2428 i, 2429 devices, 2430 legacy_connector_convert 2431 [connector], 2432 &ddc_i2c, 2433 connector_object_id, 2434 &hpd); 2435 break; 2436 case CONNECTOR_DVI_D_LEGACY: 2437 if ((tmp >> 4) & 0x1) { 2438 devices = ATOM_DEVICE_DFP2_SUPPORT; 2439 connector_object_id = combios_check_dl_dvi(dev, 1); 2440 } else { 2441 devices = ATOM_DEVICE_DFP1_SUPPORT; 2442 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 2443 } 2444 radeon_add_legacy_encoder(dev, 2445 radeon_get_encoder_enum 2446 (dev, devices, 0), 2447 devices); 2448 radeon_add_legacy_connector(dev, i, devices, 2449 legacy_connector_convert 2450 [connector], 2451 &ddc_i2c, 2452 connector_object_id, 2453 &hpd); 2454 break; 2455 case CONNECTOR_CTV_LEGACY: 2456 case CONNECTOR_STV_LEGACY: 2457 radeon_add_legacy_encoder(dev, 2458 radeon_get_encoder_enum 2459 (dev, 2460 ATOM_DEVICE_TV1_SUPPORT, 2461 2), 2462 ATOM_DEVICE_TV1_SUPPORT); 2463 radeon_add_legacy_connector(dev, i, 2464 ATOM_DEVICE_TV1_SUPPORT, 2465 legacy_connector_convert 2466 [connector], 2467 &ddc_i2c, 2468 CONNECTOR_OBJECT_ID_SVIDEO, 2469 &hpd); 2470 break; 2471 default: 2472 DRM_ERROR("Unknown connector type: %d\n", 2473 connector); 2474 continue; 2475 } 2476 2477 } 2478 } else { 2479 uint16_t tmds_info = 2480 combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE); 2481 if (tmds_info) { 2482 DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n"); 2483 2484 radeon_add_legacy_encoder(dev, 2485 radeon_get_encoder_enum(dev, 2486 ATOM_DEVICE_CRT1_SUPPORT, 2487 1), 2488 ATOM_DEVICE_CRT1_SUPPORT); 2489 radeon_add_legacy_encoder(dev, 2490 radeon_get_encoder_enum(dev, 2491 ATOM_DEVICE_DFP1_SUPPORT, 2492 0), 2493 ATOM_DEVICE_DFP1_SUPPORT); 2494 2495 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 2496 hpd.hpd = RADEON_HPD_1; 2497 radeon_add_legacy_connector(dev, 2498 0, 2499 ATOM_DEVICE_CRT1_SUPPORT | 2500 ATOM_DEVICE_DFP1_SUPPORT, 2501 DRM_MODE_CONNECTOR_DVII, 2502 &ddc_i2c, 2503 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 2504 &hpd); 2505 } else { 2506 uint16_t crt_info = 2507 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); 2508 DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n"); 2509 if (crt_info) { 2510 radeon_add_legacy_encoder(dev, 2511 radeon_get_encoder_enum(dev, 2512 ATOM_DEVICE_CRT1_SUPPORT, 2513 1), 2514 ATOM_DEVICE_CRT1_SUPPORT); 2515 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 2516 hpd.hpd = RADEON_HPD_NONE; 2517 radeon_add_legacy_connector(dev, 2518 0, 2519 ATOM_DEVICE_CRT1_SUPPORT, 2520 DRM_MODE_CONNECTOR_VGA, 2521 &ddc_i2c, 2522 CONNECTOR_OBJECT_ID_VGA, 2523 &hpd); 2524 } else { 2525 DRM_DEBUG_KMS("No connector info found\n"); 2526 return false; 2527 } 2528 } 2529 } 2530 2531 if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) { 2532 uint16_t lcd_info = 2533 combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE); 2534 if (lcd_info) { 2535 uint16_t lcd_ddc_info = 2536 combios_get_table_offset(dev, 2537 COMBIOS_LCD_DDC_INFO_TABLE); 2538 2539 radeon_add_legacy_encoder(dev, 2540 radeon_get_encoder_enum(dev, 2541 ATOM_DEVICE_LCD1_SUPPORT, 2542 0), 2543 ATOM_DEVICE_LCD1_SUPPORT); 2544 2545 if (lcd_ddc_info) { 2546 ddc_type = RBIOS8(lcd_ddc_info + 2); 2547 switch (ddc_type) { 2548 case DDC_LCD: 2549 ddc_i2c = 2550 combios_setup_i2c_bus(rdev, 2551 DDC_LCD, 2552 RBIOS32(lcd_ddc_info + 3), 2553 RBIOS32(lcd_ddc_info + 7)); 2554 radeon_i2c_add(rdev, &ddc_i2c, "LCD"); 2555 break; 2556 case DDC_GPIO: 2557 ddc_i2c = 2558 combios_setup_i2c_bus(rdev, 2559 DDC_GPIO, 2560 RBIOS32(lcd_ddc_info + 3), 2561 RBIOS32(lcd_ddc_info + 7)); 2562 radeon_i2c_add(rdev, &ddc_i2c, "LCD"); 2563 break; 2564 default: 2565 ddc_i2c = 2566 combios_setup_i2c_bus(rdev, ddc_type, 0, 0); 2567 break; 2568 } 2569 DRM_DEBUG_KMS("LCD DDC Info Table found!\n"); 2570 } else 2571 ddc_i2c.valid = false; 2572 2573 hpd.hpd = RADEON_HPD_NONE; 2574 radeon_add_legacy_connector(dev, 2575 5, 2576 ATOM_DEVICE_LCD1_SUPPORT, 2577 DRM_MODE_CONNECTOR_LVDS, 2578 &ddc_i2c, 2579 CONNECTOR_OBJECT_ID_LVDS, 2580 &hpd); 2581 } 2582 } 2583 2584 /* check TV table */ 2585 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) { 2586 uint32_t tv_info = 2587 combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); 2588 if (tv_info) { 2589 if (RBIOS8(tv_info + 6) == 'T') { 2590 if (radeon_apply_legacy_tv_quirks(dev)) { 2591 hpd.hpd = RADEON_HPD_NONE; 2592 ddc_i2c.valid = false; 2593 radeon_add_legacy_encoder(dev, 2594 radeon_get_encoder_enum 2595 (dev, 2596 ATOM_DEVICE_TV1_SUPPORT, 2597 2), 2598 ATOM_DEVICE_TV1_SUPPORT); 2599 radeon_add_legacy_connector(dev, 6, 2600 ATOM_DEVICE_TV1_SUPPORT, 2601 DRM_MODE_CONNECTOR_SVIDEO, 2602 &ddc_i2c, 2603 CONNECTOR_OBJECT_ID_SVIDEO, 2604 &hpd); 2605 } 2606 } 2607 } 2608 } 2609 2610 radeon_link_encoder_connector(dev); 2611 2612 return true; 2613 } 2614 2615 static const char *thermal_controller_names[] = { 2616 "NONE", 2617 "lm63", 2618 "adm1032", 2619 }; 2620 2621 void radeon_combios_get_power_modes(struct radeon_device *rdev) 2622 { 2623 struct drm_device *dev = rdev_to_drm(rdev); 2624 u16 offset, misc, misc2 = 0; 2625 u8 rev, tmp; 2626 int state_index = 0; 2627 struct radeon_i2c_bus_rec i2c_bus; 2628 2629 rdev->pm.default_power_state_index = -1; 2630 2631 /* allocate 2 power states */ 2632 rdev->pm.power_state = kzalloc_objs(struct radeon_power_state, 2); 2633 if (rdev->pm.power_state) { 2634 /* allocate 1 clock mode per state */ 2635 rdev->pm.power_state[0].clock_info = 2636 kzalloc_objs(struct radeon_pm_clock_info, 1); 2637 rdev->pm.power_state[1].clock_info = 2638 kzalloc_objs(struct radeon_pm_clock_info, 1); 2639 if (!rdev->pm.power_state[0].clock_info || 2640 !rdev->pm.power_state[1].clock_info) 2641 goto pm_failed; 2642 } else 2643 goto pm_failed; 2644 2645 /* check for a thermal chip */ 2646 offset = combios_get_table_offset(dev, COMBIOS_OVERDRIVE_INFO_TABLE); 2647 if (offset) { 2648 u8 thermal_controller = 0, gpio = 0, i2c_addr = 0, clk_bit = 0, data_bit = 0; 2649 2650 rev = RBIOS8(offset); 2651 2652 if (rev == 0) { 2653 thermal_controller = RBIOS8(offset + 3); 2654 gpio = RBIOS8(offset + 4) & 0x3f; 2655 i2c_addr = RBIOS8(offset + 5); 2656 } else if (rev == 1) { 2657 thermal_controller = RBIOS8(offset + 4); 2658 gpio = RBIOS8(offset + 5) & 0x3f; 2659 i2c_addr = RBIOS8(offset + 6); 2660 } else if (rev == 2) { 2661 thermal_controller = RBIOS8(offset + 4); 2662 gpio = RBIOS8(offset + 5) & 0x3f; 2663 i2c_addr = RBIOS8(offset + 6); 2664 clk_bit = RBIOS8(offset + 0xa); 2665 data_bit = RBIOS8(offset + 0xb); 2666 } 2667 if ((thermal_controller > 0) && (thermal_controller < 3)) { 2668 DRM_INFO("Possible %s thermal controller at 0x%02x\n", 2669 thermal_controller_names[thermal_controller], 2670 i2c_addr >> 1); 2671 if (gpio == DDC_LCD) { 2672 /* MM i2c */ 2673 i2c_bus.valid = true; 2674 i2c_bus.hw_capable = true; 2675 i2c_bus.mm_i2c = true; 2676 i2c_bus.i2c_id = 0xa0; 2677 } else if (gpio == DDC_GPIO) 2678 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 1 << clk_bit, 1 << data_bit); 2679 else 2680 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0); 2681 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 2682 if (rdev->pm.i2c_bus) { 2683 struct i2c_board_info info = { }; 2684 const char *name = thermal_controller_names[thermal_controller]; 2685 info.addr = i2c_addr >> 1; 2686 strscpy(info.type, name, sizeof(info.type)); 2687 i2c_new_client_device(&rdev->pm.i2c_bus->adapter, &info); 2688 } 2689 } 2690 } else { 2691 /* boards with a thermal chip, but no overdrive table */ 2692 2693 /* Asus 9600xt has an f75375 on the monid bus */ 2694 if ((rdev->pdev->device == 0x4152) && 2695 (rdev->pdev->subsystem_vendor == 0x1043) && 2696 (rdev->pdev->subsystem_device == 0xc002)) { 2697 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 2698 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 2699 if (rdev->pm.i2c_bus) { 2700 struct i2c_board_info info = { }; 2701 const char *name = "f75375"; 2702 info.addr = 0x28; 2703 strscpy(info.type, name, sizeof(info.type)); 2704 i2c_new_client_device(&rdev->pm.i2c_bus->adapter, &info); 2705 DRM_INFO("Possible %s thermal controller at 0x%02x\n", 2706 name, info.addr); 2707 } 2708 } 2709 } 2710 2711 if (rdev->flags & RADEON_IS_MOBILITY) { 2712 offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE); 2713 if (offset) { 2714 rev = RBIOS8(offset); 2715 /* power mode 0 tends to be the only valid one */ 2716 rdev->pm.power_state[state_index].num_clock_modes = 1; 2717 rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2); 2718 rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6); 2719 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || 2720 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) 2721 goto default_mode; 2722 rdev->pm.power_state[state_index].type = 2723 POWER_STATE_TYPE_BATTERY; 2724 misc = RBIOS16(offset + 0x5 + 0x0); 2725 if (rev > 4) 2726 misc2 = RBIOS16(offset + 0x5 + 0xe); 2727 rdev->pm.power_state[state_index].misc = misc; 2728 rdev->pm.power_state[state_index].misc2 = misc2; 2729 if (misc & 0x4) { 2730 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO; 2731 if (misc & 0x8) 2732 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2733 true; 2734 else 2735 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2736 false; 2737 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true; 2738 if (rev < 6) { 2739 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg = 2740 RBIOS16(offset + 0x5 + 0xb) * 4; 2741 tmp = RBIOS8(offset + 0x5 + 0xd); 2742 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp); 2743 } else { 2744 u8 entries = RBIOS8(offset + 0x5 + 0xb); 2745 u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc); 2746 if (entries && voltage_table_offset) { 2747 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg = 2748 RBIOS16(voltage_table_offset) * 4; 2749 tmp = RBIOS8(voltage_table_offset + 0x2); 2750 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp); 2751 } else 2752 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false; 2753 } 2754 switch ((misc2 & 0x700) >> 8) { 2755 case 0: 2756 default: 2757 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0; 2758 break; 2759 case 1: 2760 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33; 2761 break; 2762 case 2: 2763 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66; 2764 break; 2765 case 3: 2766 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99; 2767 break; 2768 case 4: 2769 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132; 2770 break; 2771 } 2772 } else 2773 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; 2774 if (rev > 6) 2775 rdev->pm.power_state[state_index].pcie_lanes = 2776 RBIOS8(offset + 0x5 + 0x10); 2777 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2778 state_index++; 2779 } else { 2780 /* XXX figure out some good default low power mode for mobility cards w/out power tables */ 2781 } 2782 } else { 2783 /* XXX figure out some good default low power mode for desktop cards */ 2784 } 2785 2786 default_mode: 2787 /* add the default mode */ 2788 rdev->pm.power_state[state_index].type = 2789 POWER_STATE_TYPE_DEFAULT; 2790 rdev->pm.power_state[state_index].num_clock_modes = 1; 2791 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk; 2792 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk; 2793 rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0]; 2794 if ((state_index > 0) && 2795 (rdev->pm.power_state[0].clock_info[0].voltage.type == VOLTAGE_GPIO)) 2796 rdev->pm.power_state[state_index].clock_info[0].voltage = 2797 rdev->pm.power_state[0].clock_info[0].voltage; 2798 else 2799 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; 2800 rdev->pm.power_state[state_index].pcie_lanes = 16; 2801 rdev->pm.power_state[state_index].flags = 0; 2802 rdev->pm.default_power_state_index = state_index; 2803 rdev->pm.num_power_states = state_index + 1; 2804 2805 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; 2806 rdev->pm.current_clock_mode_index = 0; 2807 return; 2808 2809 pm_failed: 2810 rdev->pm.default_power_state_index = state_index; 2811 rdev->pm.num_power_states = 0; 2812 2813 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; 2814 rdev->pm.current_clock_mode_index = 0; 2815 } 2816 2817 void radeon_external_tmds_setup(struct drm_encoder *encoder) 2818 { 2819 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2820 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv; 2821 2822 if (!tmds) 2823 return; 2824 2825 switch (tmds->dvo_chip) { 2826 case DVO_SIL164: 2827 /* sil 164 */ 2828 radeon_i2c_put_byte(tmds->i2c_bus, 2829 tmds->slave_addr, 2830 0x08, 0x30); 2831 radeon_i2c_put_byte(tmds->i2c_bus, 2832 tmds->slave_addr, 2833 0x09, 0x00); 2834 radeon_i2c_put_byte(tmds->i2c_bus, 2835 tmds->slave_addr, 2836 0x0a, 0x90); 2837 radeon_i2c_put_byte(tmds->i2c_bus, 2838 tmds->slave_addr, 2839 0x0c, 0x89); 2840 radeon_i2c_put_byte(tmds->i2c_bus, 2841 tmds->slave_addr, 2842 0x08, 0x3b); 2843 break; 2844 case DVO_SIL1178: 2845 /* sil 1178 - untested */ 2846 /* 2847 * 0x0f, 0x44 2848 * 0x0f, 0x4c 2849 * 0x0e, 0x01 2850 * 0x0a, 0x80 2851 * 0x09, 0x30 2852 * 0x0c, 0xc9 2853 * 0x0d, 0x70 2854 * 0x08, 0x32 2855 * 0x08, 0x33 2856 */ 2857 break; 2858 default: 2859 break; 2860 } 2861 2862 } 2863 2864 bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder) 2865 { 2866 struct drm_device *dev = encoder->dev; 2867 struct radeon_device *rdev = dev->dev_private; 2868 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2869 uint16_t offset; 2870 uint8_t blocks, slave_addr, rev; 2871 uint32_t index, id; 2872 uint32_t reg, val, and_mask, or_mask; 2873 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv; 2874 2875 if (!tmds) 2876 return false; 2877 2878 if (rdev->flags & RADEON_IS_IGP) { 2879 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE); 2880 rev = RBIOS8(offset); 2881 if (offset) { 2882 rev = RBIOS8(offset); 2883 if (rev > 1) { 2884 blocks = RBIOS8(offset + 3); 2885 index = offset + 4; 2886 while (blocks > 0) { 2887 id = RBIOS16(index); 2888 index += 2; 2889 switch (id >> 13) { 2890 case 0: 2891 reg = (id & 0x1fff) * 4; 2892 val = RBIOS32(index); 2893 index += 4; 2894 WREG32(reg, val); 2895 break; 2896 case 2: 2897 reg = (id & 0x1fff) * 4; 2898 and_mask = RBIOS32(index); 2899 index += 4; 2900 or_mask = RBIOS32(index); 2901 index += 4; 2902 val = RREG32(reg); 2903 val = (val & and_mask) | or_mask; 2904 WREG32(reg, val); 2905 break; 2906 case 3: 2907 val = RBIOS16(index); 2908 index += 2; 2909 udelay(val); 2910 break; 2911 case 4: 2912 val = RBIOS16(index); 2913 index += 2; 2914 mdelay(val); 2915 break; 2916 case 6: 2917 slave_addr = id & 0xff; 2918 slave_addr >>= 1; /* 7 bit addressing */ 2919 index++; 2920 reg = RBIOS8(index); 2921 index++; 2922 val = RBIOS8(index); 2923 index++; 2924 radeon_i2c_put_byte(tmds->i2c_bus, 2925 slave_addr, 2926 reg, val); 2927 break; 2928 default: 2929 DRM_ERROR("Unknown id %d\n", id >> 13); 2930 break; 2931 } 2932 blocks--; 2933 } 2934 return true; 2935 } 2936 } 2937 } else { 2938 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); 2939 if (offset) { 2940 index = offset + 10; 2941 id = RBIOS16(index); 2942 while (id != 0xffff) { 2943 index += 2; 2944 switch (id >> 13) { 2945 case 0: 2946 reg = (id & 0x1fff) * 4; 2947 val = RBIOS32(index); 2948 WREG32(reg, val); 2949 break; 2950 case 2: 2951 reg = (id & 0x1fff) * 4; 2952 and_mask = RBIOS32(index); 2953 index += 4; 2954 or_mask = RBIOS32(index); 2955 index += 4; 2956 val = RREG32(reg); 2957 val = (val & and_mask) | or_mask; 2958 WREG32(reg, val); 2959 break; 2960 case 4: 2961 val = RBIOS16(index); 2962 index += 2; 2963 udelay(val); 2964 break; 2965 case 5: 2966 reg = id & 0x1fff; 2967 and_mask = RBIOS32(index); 2968 index += 4; 2969 or_mask = RBIOS32(index); 2970 index += 4; 2971 val = RREG32_PLL(reg); 2972 val = (val & and_mask) | or_mask; 2973 WREG32_PLL(reg, val); 2974 break; 2975 case 6: 2976 reg = id & 0x1fff; 2977 val = RBIOS8(index); 2978 index += 1; 2979 radeon_i2c_put_byte(tmds->i2c_bus, 2980 tmds->slave_addr, 2981 reg, val); 2982 break; 2983 default: 2984 DRM_ERROR("Unknown id %d\n", id >> 13); 2985 break; 2986 } 2987 id = RBIOS16(index); 2988 } 2989 return true; 2990 } 2991 } 2992 return false; 2993 } 2994 2995 static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset) 2996 { 2997 struct radeon_device *rdev = dev->dev_private; 2998 2999 if (offset) { 3000 while (RBIOS16(offset)) { 3001 uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13); 3002 uint32_t addr = (RBIOS16(offset) & 0x1fff); 3003 uint32_t val, and_mask, or_mask; 3004 uint32_t tmp; 3005 3006 offset += 2; 3007 switch (cmd) { 3008 case 0: 3009 val = RBIOS32(offset); 3010 offset += 4; 3011 WREG32(addr, val); 3012 break; 3013 case 1: 3014 val = RBIOS32(offset); 3015 offset += 4; 3016 WREG32(addr, val); 3017 break; 3018 case 2: 3019 and_mask = RBIOS32(offset); 3020 offset += 4; 3021 or_mask = RBIOS32(offset); 3022 offset += 4; 3023 tmp = RREG32(addr); 3024 tmp &= and_mask; 3025 tmp |= or_mask; 3026 WREG32(addr, tmp); 3027 break; 3028 case 3: 3029 and_mask = RBIOS32(offset); 3030 offset += 4; 3031 or_mask = RBIOS32(offset); 3032 offset += 4; 3033 tmp = RREG32(addr); 3034 tmp &= and_mask; 3035 tmp |= or_mask; 3036 WREG32(addr, tmp); 3037 break; 3038 case 4: 3039 val = RBIOS16(offset); 3040 offset += 2; 3041 udelay(val); 3042 break; 3043 case 5: 3044 val = RBIOS16(offset); 3045 offset += 2; 3046 switch (addr) { 3047 case 8: 3048 while (val--) { 3049 if (! 3050 (RREG32_PLL 3051 (RADEON_CLK_PWRMGT_CNTL) & 3052 RADEON_MC_BUSY)) 3053 break; 3054 } 3055 break; 3056 case 9: 3057 while (val--) { 3058 if ((RREG32(RADEON_MC_STATUS) & 3059 RADEON_MC_IDLE)) 3060 break; 3061 } 3062 break; 3063 default: 3064 break; 3065 } 3066 break; 3067 default: 3068 break; 3069 } 3070 } 3071 } 3072 } 3073 3074 static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset) 3075 { 3076 struct radeon_device *rdev = dev->dev_private; 3077 3078 if (offset) { 3079 while (RBIOS8(offset)) { 3080 uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6); 3081 uint8_t addr = (RBIOS8(offset) & 0x3f); 3082 uint32_t val, shift, tmp; 3083 uint32_t and_mask, or_mask; 3084 3085 offset++; 3086 switch (cmd) { 3087 case 0: 3088 val = RBIOS32(offset); 3089 offset += 4; 3090 WREG32_PLL(addr, val); 3091 break; 3092 case 1: 3093 shift = RBIOS8(offset) * 8; 3094 offset++; 3095 and_mask = RBIOS8(offset) << shift; 3096 and_mask |= ~(0xff << shift); 3097 offset++; 3098 or_mask = RBIOS8(offset) << shift; 3099 offset++; 3100 tmp = RREG32_PLL(addr); 3101 tmp &= and_mask; 3102 tmp |= or_mask; 3103 WREG32_PLL(addr, tmp); 3104 break; 3105 case 2: 3106 case 3: 3107 tmp = 1000; 3108 switch (addr) { 3109 case 1: 3110 udelay(150); 3111 break; 3112 case 2: 3113 mdelay(1); 3114 break; 3115 case 3: 3116 while (tmp--) { 3117 if (! 3118 (RREG32_PLL 3119 (RADEON_CLK_PWRMGT_CNTL) & 3120 RADEON_MC_BUSY)) 3121 break; 3122 } 3123 break; 3124 case 4: 3125 while (tmp--) { 3126 if (RREG32_PLL 3127 (RADEON_CLK_PWRMGT_CNTL) & 3128 RADEON_DLL_READY) 3129 break; 3130 } 3131 break; 3132 case 5: 3133 tmp = 3134 RREG32_PLL(RADEON_CLK_PWRMGT_CNTL); 3135 if (tmp & RADEON_CG_NO1_DEBUG_0) { 3136 #if 0 3137 uint32_t mclk_cntl = 3138 RREG32_PLL 3139 (RADEON_MCLK_CNTL); 3140 mclk_cntl &= 0xffff0000; 3141 /*mclk_cntl |= 0x00001111;*//* ??? */ 3142 WREG32_PLL(RADEON_MCLK_CNTL, 3143 mclk_cntl); 3144 mdelay(10); 3145 #endif 3146 WREG32_PLL 3147 (RADEON_CLK_PWRMGT_CNTL, 3148 tmp & 3149 ~RADEON_CG_NO1_DEBUG_0); 3150 mdelay(10); 3151 } 3152 break; 3153 default: 3154 break; 3155 } 3156 break; 3157 default: 3158 break; 3159 } 3160 } 3161 } 3162 } 3163 3164 static void combios_parse_ram_reset_table(struct drm_device *dev, 3165 uint16_t offset) 3166 { 3167 struct radeon_device *rdev = dev->dev_private; 3168 uint32_t tmp; 3169 3170 if (offset) { 3171 uint8_t val = RBIOS8(offset); 3172 while (val != 0xff) { 3173 offset++; 3174 3175 if (val == 0x0f) { 3176 uint32_t channel_complete_mask; 3177 3178 if (ASIC_IS_R300(rdev)) 3179 channel_complete_mask = 3180 R300_MEM_PWRUP_COMPLETE; 3181 else 3182 channel_complete_mask = 3183 RADEON_MEM_PWRUP_COMPLETE; 3184 tmp = 20000; 3185 while (tmp--) { 3186 if ((RREG32(RADEON_MEM_STR_CNTL) & 3187 channel_complete_mask) == 3188 channel_complete_mask) 3189 break; 3190 } 3191 } else { 3192 uint32_t or_mask = RBIOS16(offset); 3193 offset += 2; 3194 3195 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG); 3196 tmp &= RADEON_SDRAM_MODE_MASK; 3197 tmp |= or_mask; 3198 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp); 3199 3200 or_mask = val << 24; 3201 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG); 3202 tmp &= RADEON_B3MEM_RESET_MASK; 3203 tmp |= or_mask; 3204 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp); 3205 } 3206 val = RBIOS8(offset); 3207 } 3208 } 3209 } 3210 3211 static uint32_t combios_detect_ram(struct drm_device *dev, int ram, 3212 int mem_addr_mapping) 3213 { 3214 struct radeon_device *rdev = dev->dev_private; 3215 uint32_t mem_cntl; 3216 uint32_t mem_size; 3217 uint32_t addr = 0; 3218 3219 mem_cntl = RREG32(RADEON_MEM_CNTL); 3220 if (mem_cntl & RV100_HALF_MODE) 3221 ram /= 2; 3222 mem_size = ram; 3223 mem_cntl &= ~(0xff << 8); 3224 mem_cntl |= (mem_addr_mapping & 0xff) << 8; 3225 WREG32(RADEON_MEM_CNTL, mem_cntl); 3226 RREG32(RADEON_MEM_CNTL); 3227 3228 /* sdram reset ? */ 3229 3230 /* something like this???? */ 3231 while (ram--) { 3232 addr = ram * 1024 * 1024; 3233 /* write to each page */ 3234 WREG32_IDX((addr) | RADEON_MM_APER, 0xdeadbeef); 3235 /* read back and verify */ 3236 if (RREG32_IDX((addr) | RADEON_MM_APER) != 0xdeadbeef) 3237 return 0; 3238 } 3239 3240 return mem_size; 3241 } 3242 3243 static void combios_write_ram_size(struct drm_device *dev) 3244 { 3245 struct radeon_device *rdev = dev->dev_private; 3246 uint8_t rev; 3247 uint16_t offset; 3248 uint32_t mem_size = 0; 3249 uint32_t mem_cntl = 0; 3250 3251 /* should do something smarter here I guess... */ 3252 if (rdev->flags & RADEON_IS_IGP) 3253 return; 3254 3255 /* first check detected mem table */ 3256 offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE); 3257 if (offset) { 3258 rev = RBIOS8(offset); 3259 if (rev < 3) { 3260 mem_cntl = RBIOS32(offset + 1); 3261 mem_size = RBIOS16(offset + 5); 3262 if ((rdev->family < CHIP_R200) && 3263 !ASIC_IS_RN50(rdev)) 3264 WREG32(RADEON_MEM_CNTL, mem_cntl); 3265 } 3266 } 3267 3268 if (!mem_size) { 3269 offset = 3270 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE); 3271 if (offset) { 3272 rev = RBIOS8(offset - 1); 3273 if (rev < 1) { 3274 if ((rdev->family < CHIP_R200) 3275 && !ASIC_IS_RN50(rdev)) { 3276 int ram = 0; 3277 int mem_addr_mapping = 0; 3278 3279 while (RBIOS8(offset)) { 3280 ram = RBIOS8(offset); 3281 mem_addr_mapping = 3282 RBIOS8(offset + 1); 3283 if (mem_addr_mapping != 0x25) 3284 ram *= 2; 3285 mem_size = 3286 combios_detect_ram(dev, ram, 3287 mem_addr_mapping); 3288 if (mem_size) 3289 break; 3290 offset += 2; 3291 } 3292 } else 3293 mem_size = RBIOS8(offset); 3294 } else { 3295 mem_size = RBIOS8(offset); 3296 mem_size *= 2; /* convert to MB */ 3297 } 3298 } 3299 } 3300 3301 mem_size *= (1024 * 1024); /* convert to bytes */ 3302 WREG32(RADEON_CONFIG_MEMSIZE, mem_size); 3303 } 3304 3305 void radeon_combios_asic_init(struct drm_device *dev) 3306 { 3307 struct radeon_device *rdev = dev->dev_private; 3308 uint16_t table; 3309 3310 /* port hardcoded mac stuff from radeonfb */ 3311 if (rdev->bios == NULL) 3312 return; 3313 3314 /* ASIC INIT 1 */ 3315 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE); 3316 if (table) 3317 combios_parse_mmio_table(dev, table); 3318 3319 /* PLL INIT */ 3320 table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE); 3321 if (table) 3322 combios_parse_pll_table(dev, table); 3323 3324 /* ASIC INIT 2 */ 3325 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE); 3326 if (table) 3327 combios_parse_mmio_table(dev, table); 3328 3329 if (!(rdev->flags & RADEON_IS_IGP)) { 3330 /* ASIC INIT 4 */ 3331 table = 3332 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE); 3333 if (table) 3334 combios_parse_mmio_table(dev, table); 3335 3336 /* RAM RESET */ 3337 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE); 3338 if (table) 3339 combios_parse_ram_reset_table(dev, table); 3340 3341 /* ASIC INIT 3 */ 3342 table = 3343 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE); 3344 if (table) 3345 combios_parse_mmio_table(dev, table); 3346 3347 /* write CONFIG_MEMSIZE */ 3348 combios_write_ram_size(dev); 3349 } 3350 3351 /* quirk for rs4xx HP nx6125 laptop to make it resume 3352 * - it hangs on resume inside the dynclk 1 table. 3353 */ 3354 if (rdev->family == CHIP_RS480 && 3355 rdev->pdev->subsystem_vendor == 0x103c && 3356 rdev->pdev->subsystem_device == 0x308b) 3357 return; 3358 3359 /* quirk for rs4xx HP dv5000 laptop to make it resume 3360 * - it hangs on resume inside the dynclk 1 table. 3361 */ 3362 if (rdev->family == CHIP_RS480 && 3363 rdev->pdev->subsystem_vendor == 0x103c && 3364 rdev->pdev->subsystem_device == 0x30a4) 3365 return; 3366 3367 /* quirk for rs4xx Compaq Presario V5245EU laptop to make it resume 3368 * - it hangs on resume inside the dynclk 1 table. 3369 */ 3370 if (rdev->family == CHIP_RS480 && 3371 rdev->pdev->subsystem_vendor == 0x103c && 3372 rdev->pdev->subsystem_device == 0x30ae) 3373 return; 3374 3375 /* quirk for rs4xx HP Compaq dc5750 Small Form Factor to make it resume 3376 * - it hangs on resume inside the dynclk 1 table. 3377 */ 3378 if (rdev->family == CHIP_RS480 && 3379 rdev->pdev->subsystem_vendor == 0x103c && 3380 rdev->pdev->subsystem_device == 0x280a) 3381 return; 3382 /* quirk for rs4xx Toshiba Sattellite L20-183 latop to make it resume 3383 * - it hangs on resume inside the dynclk 1 table. 3384 */ 3385 if (rdev->family == CHIP_RS400 && 3386 rdev->pdev->subsystem_vendor == 0x1179 && 3387 rdev->pdev->subsystem_device == 0xff31) 3388 return; 3389 3390 /* DYN CLK 1 */ 3391 table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE); 3392 if (table) 3393 combios_parse_pll_table(dev, table); 3394 3395 } 3396 3397 void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev) 3398 { 3399 struct radeon_device *rdev = dev->dev_private; 3400 uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch; 3401 3402 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); 3403 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 3404 bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH); 3405 3406 /* let the bios control the backlight */ 3407 bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN; 3408 3409 /* tell the bios not to handle mode switching */ 3410 bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS | 3411 RADEON_ACC_MODE_CHANGE); 3412 3413 /* tell the bios a driver is loaded */ 3414 bios_7_scratch |= RADEON_DRV_LOADED; 3415 3416 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch); 3417 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 3418 WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch); 3419 } 3420 3421 void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock) 3422 { 3423 struct drm_device *dev = encoder->dev; 3424 struct radeon_device *rdev = dev->dev_private; 3425 uint32_t bios_6_scratch; 3426 3427 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 3428 3429 if (lock) 3430 bios_6_scratch |= RADEON_DRIVER_CRITICAL; 3431 else 3432 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL; 3433 3434 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 3435 } 3436 3437 void 3438 radeon_combios_connected_scratch_regs(struct drm_connector *connector, 3439 struct drm_encoder *encoder, 3440 bool connected) 3441 { 3442 struct drm_device *dev = connector->dev; 3443 struct radeon_device *rdev = dev->dev_private; 3444 struct radeon_connector *radeon_connector = 3445 to_radeon_connector(connector); 3446 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 3447 uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH); 3448 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH); 3449 3450 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) && 3451 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) { 3452 if (connected) { 3453 DRM_DEBUG_KMS("TV1 connected\n"); 3454 /* fix me */ 3455 bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO; 3456 /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */ 3457 bios_5_scratch |= RADEON_TV1_ON; 3458 bios_5_scratch |= RADEON_ACC_REQ_TV1; 3459 } else { 3460 DRM_DEBUG_KMS("TV1 disconnected\n"); 3461 bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK; 3462 bios_5_scratch &= ~RADEON_TV1_ON; 3463 bios_5_scratch &= ~RADEON_ACC_REQ_TV1; 3464 } 3465 } 3466 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) && 3467 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) { 3468 if (connected) { 3469 DRM_DEBUG_KMS("LCD1 connected\n"); 3470 bios_4_scratch |= RADEON_LCD1_ATTACHED; 3471 bios_5_scratch |= RADEON_LCD1_ON; 3472 bios_5_scratch |= RADEON_ACC_REQ_LCD1; 3473 } else { 3474 DRM_DEBUG_KMS("LCD1 disconnected\n"); 3475 bios_4_scratch &= ~RADEON_LCD1_ATTACHED; 3476 bios_5_scratch &= ~RADEON_LCD1_ON; 3477 bios_5_scratch &= ~RADEON_ACC_REQ_LCD1; 3478 } 3479 } 3480 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) && 3481 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) { 3482 if (connected) { 3483 DRM_DEBUG_KMS("CRT1 connected\n"); 3484 bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR; 3485 bios_5_scratch |= RADEON_CRT1_ON; 3486 bios_5_scratch |= RADEON_ACC_REQ_CRT1; 3487 } else { 3488 DRM_DEBUG_KMS("CRT1 disconnected\n"); 3489 bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK; 3490 bios_5_scratch &= ~RADEON_CRT1_ON; 3491 bios_5_scratch &= ~RADEON_ACC_REQ_CRT1; 3492 } 3493 } 3494 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) && 3495 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) { 3496 if (connected) { 3497 DRM_DEBUG_KMS("CRT2 connected\n"); 3498 bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR; 3499 bios_5_scratch |= RADEON_CRT2_ON; 3500 bios_5_scratch |= RADEON_ACC_REQ_CRT2; 3501 } else { 3502 DRM_DEBUG_KMS("CRT2 disconnected\n"); 3503 bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK; 3504 bios_5_scratch &= ~RADEON_CRT2_ON; 3505 bios_5_scratch &= ~RADEON_ACC_REQ_CRT2; 3506 } 3507 } 3508 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) && 3509 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) { 3510 if (connected) { 3511 DRM_DEBUG_KMS("DFP1 connected\n"); 3512 bios_4_scratch |= RADEON_DFP1_ATTACHED; 3513 bios_5_scratch |= RADEON_DFP1_ON; 3514 bios_5_scratch |= RADEON_ACC_REQ_DFP1; 3515 } else { 3516 DRM_DEBUG_KMS("DFP1 disconnected\n"); 3517 bios_4_scratch &= ~RADEON_DFP1_ATTACHED; 3518 bios_5_scratch &= ~RADEON_DFP1_ON; 3519 bios_5_scratch &= ~RADEON_ACC_REQ_DFP1; 3520 } 3521 } 3522 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) && 3523 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) { 3524 if (connected) { 3525 DRM_DEBUG_KMS("DFP2 connected\n"); 3526 bios_4_scratch |= RADEON_DFP2_ATTACHED; 3527 bios_5_scratch |= RADEON_DFP2_ON; 3528 bios_5_scratch |= RADEON_ACC_REQ_DFP2; 3529 } else { 3530 DRM_DEBUG_KMS("DFP2 disconnected\n"); 3531 bios_4_scratch &= ~RADEON_DFP2_ATTACHED; 3532 bios_5_scratch &= ~RADEON_DFP2_ON; 3533 bios_5_scratch &= ~RADEON_ACC_REQ_DFP2; 3534 } 3535 } 3536 WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch); 3537 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch); 3538 } 3539 3540 void 3541 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc) 3542 { 3543 struct drm_device *dev = encoder->dev; 3544 struct radeon_device *rdev = dev->dev_private; 3545 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 3546 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH); 3547 3548 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { 3549 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK; 3550 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT); 3551 } 3552 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { 3553 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK; 3554 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT); 3555 } 3556 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { 3557 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK; 3558 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT); 3559 } 3560 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { 3561 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK; 3562 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT); 3563 } 3564 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) { 3565 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK; 3566 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT); 3567 } 3568 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) { 3569 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK; 3570 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT); 3571 } 3572 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch); 3573 } 3574 3575 void 3576 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on) 3577 { 3578 struct drm_device *dev = encoder->dev; 3579 struct radeon_device *rdev = dev->dev_private; 3580 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 3581 uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 3582 3583 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) { 3584 if (on) 3585 bios_6_scratch |= RADEON_TV_DPMS_ON; 3586 else 3587 bios_6_scratch &= ~RADEON_TV_DPMS_ON; 3588 } 3589 if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 3590 if (on) 3591 bios_6_scratch |= RADEON_CRT_DPMS_ON; 3592 else 3593 bios_6_scratch &= ~RADEON_CRT_DPMS_ON; 3594 } 3595 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 3596 if (on) 3597 bios_6_scratch |= RADEON_LCD_DPMS_ON; 3598 else 3599 bios_6_scratch &= ~RADEON_LCD_DPMS_ON; 3600 } 3601 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 3602 if (on) 3603 bios_6_scratch |= RADEON_DFP_DPMS_ON; 3604 else 3605 bios_6_scratch &= ~RADEON_DFP_DPMS_ON; 3606 } 3607 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 3608 } 3609