1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include "drmP.h" 29 #include "radeon_reg.h" 30 #include "radeon.h" 31 #include "atom.h" 32 33 #include <linux/vga_switcheroo.h> 34 #include <linux/slab.h> 35 /* 36 * BIOS. 37 */ 38 39 /* If you boot an IGP board with a discrete card as the primary, 40 * the IGP rom is not accessible via the rom bar as the IGP rom is 41 * part of the system bios. On boot, the system bios puts a 42 * copy of the igp rom at the start of vram if a discrete card is 43 * present. 44 */ 45 static bool igp_read_bios_from_vram(struct radeon_device *rdev) 46 { 47 uint8_t __iomem *bios; 48 resource_size_t vram_base; 49 resource_size_t size = 256 * 1024; /* ??? */ 50 51 rdev->bios = NULL; 52 vram_base = drm_get_resource_start(rdev->ddev, 0); 53 bios = ioremap(vram_base, size); 54 if (!bios) { 55 return false; 56 } 57 58 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { 59 iounmap(bios); 60 return false; 61 } 62 rdev->bios = kmalloc(size, GFP_KERNEL); 63 if (rdev->bios == NULL) { 64 iounmap(bios); 65 return false; 66 } 67 memcpy_fromio(rdev->bios, bios, size); 68 iounmap(bios); 69 return true; 70 } 71 72 static bool radeon_read_bios(struct radeon_device *rdev) 73 { 74 uint8_t __iomem *bios; 75 size_t size; 76 77 rdev->bios = NULL; 78 /* XXX: some cards may return 0 for rom size? ddx has a workaround */ 79 bios = pci_map_rom(rdev->pdev, &size); 80 if (!bios) { 81 return false; 82 } 83 84 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { 85 pci_unmap_rom(rdev->pdev, bios); 86 return false; 87 } 88 rdev->bios = kmemdup(bios, size, GFP_KERNEL); 89 if (rdev->bios == NULL) { 90 pci_unmap_rom(rdev->pdev, bios); 91 return false; 92 } 93 pci_unmap_rom(rdev->pdev, bios); 94 return true; 95 } 96 97 /* ATRM is used to get the BIOS on the discrete cards in 98 * dual-gpu systems. 99 */ 100 static bool radeon_atrm_get_bios(struct radeon_device *rdev) 101 { 102 int ret; 103 int size = 64 * 1024; 104 int i; 105 106 if (!radeon_atrm_supported(rdev->pdev)) 107 return false; 108 109 rdev->bios = kmalloc(size, GFP_KERNEL); 110 if (!rdev->bios) { 111 DRM_ERROR("Unable to allocate bios\n"); 112 return false; 113 } 114 115 for (i = 0; i < size / ATRM_BIOS_PAGE; i++) { 116 ret = radeon_atrm_get_bios_chunk(rdev->bios, 117 (i * ATRM_BIOS_PAGE), 118 ATRM_BIOS_PAGE); 119 if (ret <= 0) 120 break; 121 } 122 123 if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { 124 kfree(rdev->bios); 125 return false; 126 } 127 return true; 128 } 129 static bool r700_read_disabled_bios(struct radeon_device *rdev) 130 { 131 uint32_t viph_control; 132 uint32_t bus_cntl; 133 uint32_t d1vga_control; 134 uint32_t d2vga_control; 135 uint32_t vga_render_control; 136 uint32_t rom_cntl; 137 uint32_t cg_spll_func_cntl = 0; 138 uint32_t cg_spll_status; 139 bool r; 140 141 viph_control = RREG32(RADEON_VIPH_CONTROL); 142 bus_cntl = RREG32(RADEON_BUS_CNTL); 143 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 144 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 145 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 146 rom_cntl = RREG32(R600_ROM_CNTL); 147 148 /* disable VIP */ 149 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 150 /* enable the rom */ 151 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); 152 /* Disable VGA mode */ 153 WREG32(AVIVO_D1VGA_CONTROL, 154 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 155 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 156 WREG32(AVIVO_D2VGA_CONTROL, 157 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 158 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 159 WREG32(AVIVO_VGA_RENDER_CONTROL, 160 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 161 162 if (rdev->family == CHIP_RV730) { 163 cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL); 164 165 /* enable bypass mode */ 166 WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl | 167 R600_SPLL_BYPASS_EN)); 168 169 /* wait for SPLL_CHG_STATUS to change to 1 */ 170 cg_spll_status = 0; 171 while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) 172 cg_spll_status = RREG32(R600_CG_SPLL_STATUS); 173 174 WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE)); 175 } else 176 WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE)); 177 178 r = radeon_read_bios(rdev); 179 180 /* restore regs */ 181 if (rdev->family == CHIP_RV730) { 182 WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl); 183 184 /* wait for SPLL_CHG_STATUS to change to 1 */ 185 cg_spll_status = 0; 186 while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) 187 cg_spll_status = RREG32(R600_CG_SPLL_STATUS); 188 } 189 WREG32(RADEON_VIPH_CONTROL, viph_control); 190 WREG32(RADEON_BUS_CNTL, bus_cntl); 191 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 192 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 193 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 194 WREG32(R600_ROM_CNTL, rom_cntl); 195 return r; 196 } 197 198 static bool r600_read_disabled_bios(struct radeon_device *rdev) 199 { 200 uint32_t viph_control; 201 uint32_t bus_cntl; 202 uint32_t d1vga_control; 203 uint32_t d2vga_control; 204 uint32_t vga_render_control; 205 uint32_t rom_cntl; 206 uint32_t general_pwrmgt; 207 uint32_t low_vid_lower_gpio_cntl; 208 uint32_t medium_vid_lower_gpio_cntl; 209 uint32_t high_vid_lower_gpio_cntl; 210 uint32_t ctxsw_vid_lower_gpio_cntl; 211 uint32_t lower_gpio_enable; 212 bool r; 213 214 viph_control = RREG32(RADEON_VIPH_CONTROL); 215 bus_cntl = RREG32(RADEON_BUS_CNTL); 216 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 217 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 218 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 219 rom_cntl = RREG32(R600_ROM_CNTL); 220 general_pwrmgt = RREG32(R600_GENERAL_PWRMGT); 221 low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL); 222 medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL); 223 high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL); 224 ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL); 225 lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE); 226 227 /* disable VIP */ 228 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 229 /* enable the rom */ 230 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); 231 /* Disable VGA mode */ 232 WREG32(AVIVO_D1VGA_CONTROL, 233 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 234 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 235 WREG32(AVIVO_D2VGA_CONTROL, 236 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 237 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 238 WREG32(AVIVO_VGA_RENDER_CONTROL, 239 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 240 241 WREG32(R600_ROM_CNTL, 242 ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) | 243 (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) | 244 R600_SCK_OVERWRITE)); 245 246 WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS)); 247 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, 248 (low_vid_lower_gpio_cntl & ~0x400)); 249 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, 250 (medium_vid_lower_gpio_cntl & ~0x400)); 251 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, 252 (high_vid_lower_gpio_cntl & ~0x400)); 253 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, 254 (ctxsw_vid_lower_gpio_cntl & ~0x400)); 255 WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400)); 256 257 r = radeon_read_bios(rdev); 258 259 /* restore regs */ 260 WREG32(RADEON_VIPH_CONTROL, viph_control); 261 WREG32(RADEON_BUS_CNTL, bus_cntl); 262 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 263 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 264 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 265 WREG32(R600_ROM_CNTL, rom_cntl); 266 WREG32(R600_GENERAL_PWRMGT, general_pwrmgt); 267 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl); 268 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl); 269 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl); 270 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl); 271 WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable); 272 return r; 273 } 274 275 static bool avivo_read_disabled_bios(struct radeon_device *rdev) 276 { 277 uint32_t seprom_cntl1; 278 uint32_t viph_control; 279 uint32_t bus_cntl; 280 uint32_t d1vga_control; 281 uint32_t d2vga_control; 282 uint32_t vga_render_control; 283 uint32_t gpiopad_a; 284 uint32_t gpiopad_en; 285 uint32_t gpiopad_mask; 286 bool r; 287 288 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); 289 viph_control = RREG32(RADEON_VIPH_CONTROL); 290 bus_cntl = RREG32(RADEON_BUS_CNTL); 291 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 292 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 293 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 294 gpiopad_a = RREG32(RADEON_GPIOPAD_A); 295 gpiopad_en = RREG32(RADEON_GPIOPAD_EN); 296 gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK); 297 298 WREG32(RADEON_SEPROM_CNTL1, 299 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | 300 (0xc << RADEON_SCK_PRESCALE_SHIFT))); 301 WREG32(RADEON_GPIOPAD_A, 0); 302 WREG32(RADEON_GPIOPAD_EN, 0); 303 WREG32(RADEON_GPIOPAD_MASK, 0); 304 305 /* disable VIP */ 306 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 307 308 /* enable the rom */ 309 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); 310 311 /* Disable VGA mode */ 312 WREG32(AVIVO_D1VGA_CONTROL, 313 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 314 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 315 WREG32(AVIVO_D2VGA_CONTROL, 316 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 317 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 318 WREG32(AVIVO_VGA_RENDER_CONTROL, 319 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 320 321 r = radeon_read_bios(rdev); 322 323 /* restore regs */ 324 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); 325 WREG32(RADEON_VIPH_CONTROL, viph_control); 326 WREG32(RADEON_BUS_CNTL, bus_cntl); 327 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 328 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 329 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 330 WREG32(RADEON_GPIOPAD_A, gpiopad_a); 331 WREG32(RADEON_GPIOPAD_EN, gpiopad_en); 332 WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask); 333 return r; 334 } 335 336 static bool legacy_read_disabled_bios(struct radeon_device *rdev) 337 { 338 uint32_t seprom_cntl1; 339 uint32_t viph_control; 340 uint32_t bus_cntl; 341 uint32_t crtc_gen_cntl; 342 uint32_t crtc2_gen_cntl; 343 uint32_t crtc_ext_cntl; 344 uint32_t fp2_gen_cntl; 345 bool r; 346 347 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); 348 viph_control = RREG32(RADEON_VIPH_CONTROL); 349 bus_cntl = RREG32(RADEON_BUS_CNTL); 350 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL); 351 crtc2_gen_cntl = 0; 352 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); 353 fp2_gen_cntl = 0; 354 355 if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) { 356 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); 357 } 358 359 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 360 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); 361 } 362 363 WREG32(RADEON_SEPROM_CNTL1, 364 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | 365 (0xc << RADEON_SCK_PRESCALE_SHIFT))); 366 367 /* disable VIP */ 368 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 369 370 /* enable the rom */ 371 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); 372 373 /* Turn off mem requests and CRTC for both controllers */ 374 WREG32(RADEON_CRTC_GEN_CNTL, 375 ((crtc_gen_cntl & ~RADEON_CRTC_EN) | 376 (RADEON_CRTC_DISP_REQ_EN_B | 377 RADEON_CRTC_EXT_DISP_EN))); 378 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 379 WREG32(RADEON_CRTC2_GEN_CNTL, 380 ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) | 381 RADEON_CRTC2_DISP_REQ_EN_B)); 382 } 383 /* Turn off CRTC */ 384 WREG32(RADEON_CRTC_EXT_CNTL, 385 ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) | 386 (RADEON_CRTC_SYNC_TRISTAT | 387 RADEON_CRTC_DISPLAY_DIS))); 388 389 if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) { 390 WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON)); 391 } 392 393 r = radeon_read_bios(rdev); 394 395 /* restore regs */ 396 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); 397 WREG32(RADEON_VIPH_CONTROL, viph_control); 398 WREG32(RADEON_BUS_CNTL, bus_cntl); 399 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); 400 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 401 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 402 } 403 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); 404 if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) { 405 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); 406 } 407 return r; 408 } 409 410 static bool radeon_read_disabled_bios(struct radeon_device *rdev) 411 { 412 if (rdev->flags & RADEON_IS_IGP) 413 return igp_read_bios_from_vram(rdev); 414 else if (rdev->family >= CHIP_RV770) 415 return r700_read_disabled_bios(rdev); 416 else if (rdev->family >= CHIP_R600) 417 return r600_read_disabled_bios(rdev); 418 else if (rdev->family >= CHIP_RS600) 419 return avivo_read_disabled_bios(rdev); 420 else 421 return legacy_read_disabled_bios(rdev); 422 } 423 424 425 bool radeon_get_bios(struct radeon_device *rdev) 426 { 427 bool r; 428 uint16_t tmp; 429 430 r = radeon_atrm_get_bios(rdev); 431 if (r == false) 432 r = igp_read_bios_from_vram(rdev); 433 if (r == false) 434 r = radeon_read_bios(rdev); 435 if (r == false) { 436 r = radeon_read_disabled_bios(rdev); 437 } 438 if (r == false || rdev->bios == NULL) { 439 DRM_ERROR("Unable to locate a BIOS ROM\n"); 440 rdev->bios = NULL; 441 return false; 442 } 443 if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { 444 printk("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]); 445 goto free_bios; 446 } 447 448 tmp = RBIOS16(0x18); 449 if (RBIOS8(tmp + 0x14) != 0x0) { 450 DRM_INFO("Not an x86 BIOS ROM, not using.\n"); 451 goto free_bios; 452 } 453 454 rdev->bios_header_start = RBIOS16(0x48); 455 if (!rdev->bios_header_start) { 456 goto free_bios; 457 } 458 tmp = rdev->bios_header_start + 4; 459 if (!memcmp(rdev->bios + tmp, "ATOM", 4) || 460 !memcmp(rdev->bios + tmp, "MOTA", 4)) { 461 rdev->is_atom_bios = true; 462 } else { 463 rdev->is_atom_bios = false; 464 } 465 466 DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM"); 467 return true; 468 free_bios: 469 kfree(rdev->bios); 470 rdev->bios = NULL; 471 return false; 472 } 473