1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include "drmP.h" 27 #include "radeon_drm.h" 28 #include "radeon.h" 29 30 #include "atom.h" 31 #include "atom-bits.h" 32 33 /* from radeon_encoder.c */ 34 extern uint32_t 35 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, 36 uint8_t dac); 37 extern void radeon_link_encoder_connector(struct drm_device *dev); 38 extern void 39 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum, 40 uint32_t supported_device, u16 caps); 41 42 /* from radeon_connector.c */ 43 extern void 44 radeon_add_atom_connector(struct drm_device *dev, 45 uint32_t connector_id, 46 uint32_t supported_device, 47 int connector_type, 48 struct radeon_i2c_bus_rec *i2c_bus, 49 uint32_t igp_lane_info, 50 uint16_t connector_object_id, 51 struct radeon_hpd *hpd, 52 struct radeon_router *router); 53 54 /* from radeon_legacy_encoder.c */ 55 extern void 56 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum, 57 uint32_t supported_device); 58 59 union atom_supported_devices { 60 struct _ATOM_SUPPORTED_DEVICES_INFO info; 61 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2; 62 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1; 63 }; 64 65 static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev, 66 uint8_t id) 67 { 68 struct atom_context *ctx = rdev->mode_info.atom_context; 69 ATOM_GPIO_I2C_ASSIGMENT *gpio; 70 struct radeon_i2c_bus_rec i2c; 71 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info); 72 struct _ATOM_GPIO_I2C_INFO *i2c_info; 73 uint16_t data_offset, size; 74 int i, num_indices; 75 76 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec)); 77 i2c.valid = false; 78 79 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { 80 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset); 81 82 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 83 sizeof(ATOM_GPIO_I2C_ASSIGMENT); 84 85 for (i = 0; i < num_indices; i++) { 86 gpio = &i2c_info->asGPIO_Info[i]; 87 88 /* some evergreen boards have bad data for this entry */ 89 if (ASIC_IS_DCE4(rdev)) { 90 if ((i == 7) && 91 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) && 92 (gpio->sucI2cId.ucAccess == 0)) { 93 gpio->sucI2cId.ucAccess = 0x97; 94 gpio->ucDataMaskShift = 8; 95 gpio->ucDataEnShift = 8; 96 gpio->ucDataY_Shift = 8; 97 gpio->ucDataA_Shift = 8; 98 } 99 } 100 101 /* some DCE3 boards have bad data for this entry */ 102 if (ASIC_IS_DCE3(rdev)) { 103 if ((i == 4) && 104 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) && 105 (gpio->sucI2cId.ucAccess == 0x94)) 106 gpio->sucI2cId.ucAccess = 0x14; 107 } 108 109 if (gpio->sucI2cId.ucAccess == id) { 110 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4; 111 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4; 112 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4; 113 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4; 114 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4; 115 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4; 116 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4; 117 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4; 118 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift); 119 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift); 120 i2c.en_clk_mask = (1 << gpio->ucClkEnShift); 121 i2c.en_data_mask = (1 << gpio->ucDataEnShift); 122 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift); 123 i2c.y_data_mask = (1 << gpio->ucDataY_Shift); 124 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift); 125 i2c.a_data_mask = (1 << gpio->ucDataA_Shift); 126 127 if (gpio->sucI2cId.sbfAccess.bfHW_Capable) 128 i2c.hw_capable = true; 129 else 130 i2c.hw_capable = false; 131 132 if (gpio->sucI2cId.ucAccess == 0xa0) 133 i2c.mm_i2c = true; 134 else 135 i2c.mm_i2c = false; 136 137 i2c.i2c_id = gpio->sucI2cId.ucAccess; 138 139 if (i2c.mask_clk_reg) 140 i2c.valid = true; 141 break; 142 } 143 } 144 } 145 146 return i2c; 147 } 148 149 void radeon_atombios_i2c_init(struct radeon_device *rdev) 150 { 151 struct atom_context *ctx = rdev->mode_info.atom_context; 152 ATOM_GPIO_I2C_ASSIGMENT *gpio; 153 struct radeon_i2c_bus_rec i2c; 154 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info); 155 struct _ATOM_GPIO_I2C_INFO *i2c_info; 156 uint16_t data_offset, size; 157 int i, num_indices; 158 char stmp[32]; 159 160 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec)); 161 162 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { 163 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset); 164 165 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 166 sizeof(ATOM_GPIO_I2C_ASSIGMENT); 167 168 for (i = 0; i < num_indices; i++) { 169 gpio = &i2c_info->asGPIO_Info[i]; 170 i2c.valid = false; 171 172 /* some evergreen boards have bad data for this entry */ 173 if (ASIC_IS_DCE4(rdev)) { 174 if ((i == 7) && 175 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) && 176 (gpio->sucI2cId.ucAccess == 0)) { 177 gpio->sucI2cId.ucAccess = 0x97; 178 gpio->ucDataMaskShift = 8; 179 gpio->ucDataEnShift = 8; 180 gpio->ucDataY_Shift = 8; 181 gpio->ucDataA_Shift = 8; 182 } 183 } 184 185 /* some DCE3 boards have bad data for this entry */ 186 if (ASIC_IS_DCE3(rdev)) { 187 if ((i == 4) && 188 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) && 189 (gpio->sucI2cId.ucAccess == 0x94)) 190 gpio->sucI2cId.ucAccess = 0x14; 191 } 192 193 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4; 194 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4; 195 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4; 196 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4; 197 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4; 198 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4; 199 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4; 200 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4; 201 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift); 202 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift); 203 i2c.en_clk_mask = (1 << gpio->ucClkEnShift); 204 i2c.en_data_mask = (1 << gpio->ucDataEnShift); 205 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift); 206 i2c.y_data_mask = (1 << gpio->ucDataY_Shift); 207 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift); 208 i2c.a_data_mask = (1 << gpio->ucDataA_Shift); 209 210 if (gpio->sucI2cId.sbfAccess.bfHW_Capable) 211 i2c.hw_capable = true; 212 else 213 i2c.hw_capable = false; 214 215 if (gpio->sucI2cId.ucAccess == 0xa0) 216 i2c.mm_i2c = true; 217 else 218 i2c.mm_i2c = false; 219 220 i2c.i2c_id = gpio->sucI2cId.ucAccess; 221 222 if (i2c.mask_clk_reg) { 223 i2c.valid = true; 224 sprintf(stmp, "0x%x", i2c.i2c_id); 225 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp); 226 } 227 } 228 } 229 } 230 231 static struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev, 232 u8 id) 233 { 234 struct atom_context *ctx = rdev->mode_info.atom_context; 235 struct radeon_gpio_rec gpio; 236 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT); 237 struct _ATOM_GPIO_PIN_LUT *gpio_info; 238 ATOM_GPIO_PIN_ASSIGNMENT *pin; 239 u16 data_offset, size; 240 int i, num_indices; 241 242 memset(&gpio, 0, sizeof(struct radeon_gpio_rec)); 243 gpio.valid = false; 244 245 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { 246 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset); 247 248 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 249 sizeof(ATOM_GPIO_PIN_ASSIGNMENT); 250 251 for (i = 0; i < num_indices; i++) { 252 pin = &gpio_info->asGPIO_Pin[i]; 253 if (id == pin->ucGPIO_ID) { 254 gpio.id = pin->ucGPIO_ID; 255 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4; 256 gpio.mask = (1 << pin->ucGpioPinBitShift); 257 gpio.valid = true; 258 break; 259 } 260 } 261 } 262 263 return gpio; 264 } 265 266 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev, 267 struct radeon_gpio_rec *gpio) 268 { 269 struct radeon_hpd hpd; 270 u32 reg; 271 272 memset(&hpd, 0, sizeof(struct radeon_hpd)); 273 274 if (ASIC_IS_DCE4(rdev)) 275 reg = EVERGREEN_DC_GPIO_HPD_A; 276 else 277 reg = AVIVO_DC_GPIO_HPD_A; 278 279 hpd.gpio = *gpio; 280 if (gpio->reg == reg) { 281 switch(gpio->mask) { 282 case (1 << 0): 283 hpd.hpd = RADEON_HPD_1; 284 break; 285 case (1 << 8): 286 hpd.hpd = RADEON_HPD_2; 287 break; 288 case (1 << 16): 289 hpd.hpd = RADEON_HPD_3; 290 break; 291 case (1 << 24): 292 hpd.hpd = RADEON_HPD_4; 293 break; 294 case (1 << 26): 295 hpd.hpd = RADEON_HPD_5; 296 break; 297 case (1 << 28): 298 hpd.hpd = RADEON_HPD_6; 299 break; 300 default: 301 hpd.hpd = RADEON_HPD_NONE; 302 break; 303 } 304 } else 305 hpd.hpd = RADEON_HPD_NONE; 306 return hpd; 307 } 308 309 static bool radeon_atom_apply_quirks(struct drm_device *dev, 310 uint32_t supported_device, 311 int *connector_type, 312 struct radeon_i2c_bus_rec *i2c_bus, 313 uint16_t *line_mux, 314 struct radeon_hpd *hpd) 315 { 316 317 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */ 318 if ((dev->pdev->device == 0x791e) && 319 (dev->pdev->subsystem_vendor == 0x1043) && 320 (dev->pdev->subsystem_device == 0x826d)) { 321 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) && 322 (supported_device == ATOM_DEVICE_DFP3_SUPPORT)) 323 *connector_type = DRM_MODE_CONNECTOR_DVID; 324 } 325 326 /* Asrock RS600 board lists the DVI port as HDMI */ 327 if ((dev->pdev->device == 0x7941) && 328 (dev->pdev->subsystem_vendor == 0x1849) && 329 (dev->pdev->subsystem_device == 0x7941)) { 330 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) && 331 (supported_device == ATOM_DEVICE_DFP3_SUPPORT)) 332 *connector_type = DRM_MODE_CONNECTOR_DVID; 333 } 334 335 /* MSI K9A2GM V2/V3 board has no HDMI or DVI */ 336 if ((dev->pdev->device == 0x796e) && 337 (dev->pdev->subsystem_vendor == 0x1462) && 338 (dev->pdev->subsystem_device == 0x7302)) { 339 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) || 340 (supported_device == ATOM_DEVICE_DFP3_SUPPORT)) 341 return false; 342 } 343 344 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */ 345 if ((dev->pdev->device == 0x7941) && 346 (dev->pdev->subsystem_vendor == 0x147b) && 347 (dev->pdev->subsystem_device == 0x2412)) { 348 if (*connector_type == DRM_MODE_CONNECTOR_DVII) 349 return false; 350 } 351 352 /* Falcon NW laptop lists vga ddc line for LVDS */ 353 if ((dev->pdev->device == 0x5653) && 354 (dev->pdev->subsystem_vendor == 0x1462) && 355 (dev->pdev->subsystem_device == 0x0291)) { 356 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) { 357 i2c_bus->valid = false; 358 *line_mux = 53; 359 } 360 } 361 362 /* HIS X1300 is DVI+VGA, not DVI+DVI */ 363 if ((dev->pdev->device == 0x7146) && 364 (dev->pdev->subsystem_vendor == 0x17af) && 365 (dev->pdev->subsystem_device == 0x2058)) { 366 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT) 367 return false; 368 } 369 370 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */ 371 if ((dev->pdev->device == 0x7142) && 372 (dev->pdev->subsystem_vendor == 0x1458) && 373 (dev->pdev->subsystem_device == 0x2134)) { 374 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT) 375 return false; 376 } 377 378 379 /* Funky macbooks */ 380 if ((dev->pdev->device == 0x71C5) && 381 (dev->pdev->subsystem_vendor == 0x106b) && 382 (dev->pdev->subsystem_device == 0x0080)) { 383 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) || 384 (supported_device == ATOM_DEVICE_DFP2_SUPPORT)) 385 return false; 386 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT) 387 *line_mux = 0x90; 388 } 389 390 /* mac rv630, rv730, others */ 391 if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) && 392 (*connector_type == DRM_MODE_CONNECTOR_DVII)) { 393 *connector_type = DRM_MODE_CONNECTOR_9PinDIN; 394 *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1; 395 } 396 397 /* ASUS HD 3600 XT board lists the DVI port as HDMI */ 398 if ((dev->pdev->device == 0x9598) && 399 (dev->pdev->subsystem_vendor == 0x1043) && 400 (dev->pdev->subsystem_device == 0x01da)) { 401 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { 402 *connector_type = DRM_MODE_CONNECTOR_DVII; 403 } 404 } 405 406 /* ASUS HD 3600 board lists the DVI port as HDMI */ 407 if ((dev->pdev->device == 0x9598) && 408 (dev->pdev->subsystem_vendor == 0x1043) && 409 (dev->pdev->subsystem_device == 0x01e4)) { 410 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { 411 *connector_type = DRM_MODE_CONNECTOR_DVII; 412 } 413 } 414 415 /* ASUS HD 3450 board lists the DVI port as HDMI */ 416 if ((dev->pdev->device == 0x95C5) && 417 (dev->pdev->subsystem_vendor == 0x1043) && 418 (dev->pdev->subsystem_device == 0x01e2)) { 419 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { 420 *connector_type = DRM_MODE_CONNECTOR_DVII; 421 } 422 } 423 424 /* some BIOSes seem to report DAC on HDMI - usually this is a board with 425 * HDMI + VGA reporting as HDMI 426 */ 427 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { 428 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) { 429 *connector_type = DRM_MODE_CONNECTOR_VGA; 430 *line_mux = 0; 431 } 432 } 433 434 /* Acer laptop (Acer TravelMate 5730/5730G) has an HDMI port 435 * on the laptop and a DVI port on the docking station and 436 * both share the same encoder, hpd pin, and ddc line. 437 * So while the bios table is technically correct, 438 * we drop the DVI port here since xrandr has no concept of 439 * encoders and will try and drive both connectors 440 * with different crtcs which isn't possible on the hardware 441 * side and leaves no crtcs for LVDS or VGA. 442 */ 443 if (((dev->pdev->device == 0x95c4) || (dev->pdev->device == 0x9591)) && 444 (dev->pdev->subsystem_vendor == 0x1025) && 445 (dev->pdev->subsystem_device == 0x013c)) { 446 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) && 447 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) { 448 /* actually it's a DVI-D port not DVI-I */ 449 *connector_type = DRM_MODE_CONNECTOR_DVID; 450 return false; 451 } 452 } 453 454 /* XFX Pine Group device rv730 reports no VGA DDC lines 455 * even though they are wired up to record 0x93 456 */ 457 if ((dev->pdev->device == 0x9498) && 458 (dev->pdev->subsystem_vendor == 0x1682) && 459 (dev->pdev->subsystem_device == 0x2452)) { 460 struct radeon_device *rdev = dev->dev_private; 461 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93); 462 } 463 return true; 464 } 465 466 const int supported_devices_connector_convert[] = { 467 DRM_MODE_CONNECTOR_Unknown, 468 DRM_MODE_CONNECTOR_VGA, 469 DRM_MODE_CONNECTOR_DVII, 470 DRM_MODE_CONNECTOR_DVID, 471 DRM_MODE_CONNECTOR_DVIA, 472 DRM_MODE_CONNECTOR_SVIDEO, 473 DRM_MODE_CONNECTOR_Composite, 474 DRM_MODE_CONNECTOR_LVDS, 475 DRM_MODE_CONNECTOR_Unknown, 476 DRM_MODE_CONNECTOR_Unknown, 477 DRM_MODE_CONNECTOR_HDMIA, 478 DRM_MODE_CONNECTOR_HDMIB, 479 DRM_MODE_CONNECTOR_Unknown, 480 DRM_MODE_CONNECTOR_Unknown, 481 DRM_MODE_CONNECTOR_9PinDIN, 482 DRM_MODE_CONNECTOR_DisplayPort 483 }; 484 485 const uint16_t supported_devices_connector_object_id_convert[] = { 486 CONNECTOR_OBJECT_ID_NONE, 487 CONNECTOR_OBJECT_ID_VGA, 488 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */ 489 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */ 490 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */ 491 CONNECTOR_OBJECT_ID_COMPOSITE, 492 CONNECTOR_OBJECT_ID_SVIDEO, 493 CONNECTOR_OBJECT_ID_LVDS, 494 CONNECTOR_OBJECT_ID_9PIN_DIN, 495 CONNECTOR_OBJECT_ID_9PIN_DIN, 496 CONNECTOR_OBJECT_ID_DISPLAYPORT, 497 CONNECTOR_OBJECT_ID_HDMI_TYPE_A, 498 CONNECTOR_OBJECT_ID_HDMI_TYPE_B, 499 CONNECTOR_OBJECT_ID_SVIDEO 500 }; 501 502 const int object_connector_convert[] = { 503 DRM_MODE_CONNECTOR_Unknown, 504 DRM_MODE_CONNECTOR_DVII, 505 DRM_MODE_CONNECTOR_DVII, 506 DRM_MODE_CONNECTOR_DVID, 507 DRM_MODE_CONNECTOR_DVID, 508 DRM_MODE_CONNECTOR_VGA, 509 DRM_MODE_CONNECTOR_Composite, 510 DRM_MODE_CONNECTOR_SVIDEO, 511 DRM_MODE_CONNECTOR_Unknown, 512 DRM_MODE_CONNECTOR_Unknown, 513 DRM_MODE_CONNECTOR_9PinDIN, 514 DRM_MODE_CONNECTOR_Unknown, 515 DRM_MODE_CONNECTOR_HDMIA, 516 DRM_MODE_CONNECTOR_HDMIB, 517 DRM_MODE_CONNECTOR_LVDS, 518 DRM_MODE_CONNECTOR_9PinDIN, 519 DRM_MODE_CONNECTOR_Unknown, 520 DRM_MODE_CONNECTOR_Unknown, 521 DRM_MODE_CONNECTOR_Unknown, 522 DRM_MODE_CONNECTOR_DisplayPort, 523 DRM_MODE_CONNECTOR_eDP, 524 DRM_MODE_CONNECTOR_Unknown 525 }; 526 527 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev) 528 { 529 struct radeon_device *rdev = dev->dev_private; 530 struct radeon_mode_info *mode_info = &rdev->mode_info; 531 struct atom_context *ctx = mode_info->atom_context; 532 int index = GetIndexIntoMasterTable(DATA, Object_Header); 533 u16 size, data_offset; 534 u8 frev, crev; 535 ATOM_CONNECTOR_OBJECT_TABLE *con_obj; 536 ATOM_ENCODER_OBJECT_TABLE *enc_obj; 537 ATOM_OBJECT_TABLE *router_obj; 538 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj; 539 ATOM_OBJECT_HEADER *obj_header; 540 int i, j, k, path_size, device_support; 541 int connector_type; 542 u16 igp_lane_info, conn_id, connector_object_id; 543 struct radeon_i2c_bus_rec ddc_bus; 544 struct radeon_router router; 545 struct radeon_gpio_rec gpio; 546 struct radeon_hpd hpd; 547 548 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) 549 return false; 550 551 if (crev < 2) 552 return false; 553 554 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset); 555 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *) 556 (ctx->bios + data_offset + 557 le16_to_cpu(obj_header->usDisplayPathTableOffset)); 558 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *) 559 (ctx->bios + data_offset + 560 le16_to_cpu(obj_header->usConnectorObjectTableOffset)); 561 enc_obj = (ATOM_ENCODER_OBJECT_TABLE *) 562 (ctx->bios + data_offset + 563 le16_to_cpu(obj_header->usEncoderObjectTableOffset)); 564 router_obj = (ATOM_OBJECT_TABLE *) 565 (ctx->bios + data_offset + 566 le16_to_cpu(obj_header->usRouterObjectTableOffset)); 567 device_support = le16_to_cpu(obj_header->usDeviceSupport); 568 569 path_size = 0; 570 for (i = 0; i < path_obj->ucNumOfDispPath; i++) { 571 uint8_t *addr = (uint8_t *) path_obj->asDispPath; 572 ATOM_DISPLAY_OBJECT_PATH *path; 573 addr += path_size; 574 path = (ATOM_DISPLAY_OBJECT_PATH *) addr; 575 path_size += le16_to_cpu(path->usSize); 576 577 if (device_support & le16_to_cpu(path->usDeviceTag)) { 578 uint8_t con_obj_id, con_obj_num, con_obj_type; 579 580 con_obj_id = 581 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK) 582 >> OBJECT_ID_SHIFT; 583 con_obj_num = 584 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK) 585 >> ENUM_ID_SHIFT; 586 con_obj_type = 587 (le16_to_cpu(path->usConnObjectId) & 588 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; 589 590 /* TODO CV support */ 591 if (le16_to_cpu(path->usDeviceTag) == 592 ATOM_DEVICE_CV_SUPPORT) 593 continue; 594 595 /* IGP chips */ 596 if ((rdev->flags & RADEON_IS_IGP) && 597 (con_obj_id == 598 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) { 599 uint16_t igp_offset = 0; 600 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj; 601 602 index = 603 GetIndexIntoMasterTable(DATA, 604 IntegratedSystemInfo); 605 606 if (atom_parse_data_header(ctx, index, &size, &frev, 607 &crev, &igp_offset)) { 608 609 if (crev >= 2) { 610 igp_obj = 611 (ATOM_INTEGRATED_SYSTEM_INFO_V2 612 *) (ctx->bios + igp_offset); 613 614 if (igp_obj) { 615 uint32_t slot_config, ct; 616 617 if (con_obj_num == 1) 618 slot_config = 619 igp_obj-> 620 ulDDISlot1Config; 621 else 622 slot_config = 623 igp_obj-> 624 ulDDISlot2Config; 625 626 ct = (slot_config >> 16) & 0xff; 627 connector_type = 628 object_connector_convert 629 [ct]; 630 connector_object_id = ct; 631 igp_lane_info = 632 slot_config & 0xffff; 633 } else 634 continue; 635 } else 636 continue; 637 } else { 638 igp_lane_info = 0; 639 connector_type = 640 object_connector_convert[con_obj_id]; 641 connector_object_id = con_obj_id; 642 } 643 } else { 644 igp_lane_info = 0; 645 connector_type = 646 object_connector_convert[con_obj_id]; 647 connector_object_id = con_obj_id; 648 } 649 650 if (connector_type == DRM_MODE_CONNECTOR_Unknown) 651 continue; 652 653 router.ddc_valid = false; 654 router.cd_valid = false; 655 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) { 656 uint8_t grph_obj_id, grph_obj_num, grph_obj_type; 657 658 grph_obj_id = 659 (le16_to_cpu(path->usGraphicObjIds[j]) & 660 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 661 grph_obj_num = 662 (le16_to_cpu(path->usGraphicObjIds[j]) & 663 ENUM_ID_MASK) >> ENUM_ID_SHIFT; 664 grph_obj_type = 665 (le16_to_cpu(path->usGraphicObjIds[j]) & 666 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; 667 668 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) { 669 for (k = 0; k < enc_obj->ucNumberOfObjects; k++) { 670 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID); 671 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) { 672 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *) 673 (ctx->bios + data_offset + 674 le16_to_cpu(enc_obj->asObjects[k].usRecordOffset)); 675 ATOM_ENCODER_CAP_RECORD *cap_record; 676 u16 caps = 0; 677 678 while (record->ucRecordSize > 0 && 679 record->ucRecordType > 0 && 680 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { 681 switch (record->ucRecordType) { 682 case ATOM_ENCODER_CAP_RECORD_TYPE: 683 cap_record =(ATOM_ENCODER_CAP_RECORD *) 684 record; 685 caps = le16_to_cpu(cap_record->usEncoderCap); 686 break; 687 } 688 record = (ATOM_COMMON_RECORD_HEADER *) 689 ((char *)record + record->ucRecordSize); 690 } 691 radeon_add_atom_encoder(dev, 692 encoder_obj, 693 le16_to_cpu 694 (path-> 695 usDeviceTag), 696 caps); 697 } 698 } 699 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) { 700 for (k = 0; k < router_obj->ucNumberOfObjects; k++) { 701 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID); 702 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) { 703 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *) 704 (ctx->bios + data_offset + 705 le16_to_cpu(router_obj->asObjects[k].usRecordOffset)); 706 ATOM_I2C_RECORD *i2c_record; 707 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config; 708 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path; 709 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path; 710 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table = 711 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *) 712 (ctx->bios + data_offset + 713 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset)); 714 int enum_id; 715 716 router.router_id = router_obj_id; 717 for (enum_id = 0; enum_id < router_src_dst_table->ucNumberOfDst; 718 enum_id++) { 719 if (le16_to_cpu(path->usConnObjectId) == 720 le16_to_cpu(router_src_dst_table->usDstObjectID[enum_id])) 721 break; 722 } 723 724 while (record->ucRecordSize > 0 && 725 record->ucRecordType > 0 && 726 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { 727 switch (record->ucRecordType) { 728 case ATOM_I2C_RECORD_TYPE: 729 i2c_record = 730 (ATOM_I2C_RECORD *) 731 record; 732 i2c_config = 733 (ATOM_I2C_ID_CONFIG_ACCESS *) 734 &i2c_record->sucI2cId; 735 router.i2c_info = 736 radeon_lookup_i2c_gpio(rdev, 737 i2c_config-> 738 ucAccess); 739 router.i2c_addr = i2c_record->ucI2CAddr >> 1; 740 break; 741 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE: 742 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *) 743 record; 744 router.ddc_valid = true; 745 router.ddc_mux_type = ddc_path->ucMuxType; 746 router.ddc_mux_control_pin = ddc_path->ucMuxControlPin; 747 router.ddc_mux_state = ddc_path->ucMuxState[enum_id]; 748 break; 749 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE: 750 cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *) 751 record; 752 router.cd_valid = true; 753 router.cd_mux_type = cd_path->ucMuxType; 754 router.cd_mux_control_pin = cd_path->ucMuxControlPin; 755 router.cd_mux_state = cd_path->ucMuxState[enum_id]; 756 break; 757 } 758 record = (ATOM_COMMON_RECORD_HEADER *) 759 ((char *)record + record->ucRecordSize); 760 } 761 } 762 } 763 } 764 } 765 766 /* look up gpio for ddc, hpd */ 767 ddc_bus.valid = false; 768 hpd.hpd = RADEON_HPD_NONE; 769 if ((le16_to_cpu(path->usDeviceTag) & 770 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) { 771 for (j = 0; j < con_obj->ucNumberOfObjects; j++) { 772 if (le16_to_cpu(path->usConnObjectId) == 773 le16_to_cpu(con_obj->asObjects[j]. 774 usObjectID)) { 775 ATOM_COMMON_RECORD_HEADER 776 *record = 777 (ATOM_COMMON_RECORD_HEADER 778 *) 779 (ctx->bios + data_offset + 780 le16_to_cpu(con_obj-> 781 asObjects[j]. 782 usRecordOffset)); 783 ATOM_I2C_RECORD *i2c_record; 784 ATOM_HPD_INT_RECORD *hpd_record; 785 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config; 786 787 while (record->ucRecordSize > 0 && 788 record->ucRecordType > 0 && 789 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { 790 switch (record->ucRecordType) { 791 case ATOM_I2C_RECORD_TYPE: 792 i2c_record = 793 (ATOM_I2C_RECORD *) 794 record; 795 i2c_config = 796 (ATOM_I2C_ID_CONFIG_ACCESS *) 797 &i2c_record->sucI2cId; 798 ddc_bus = radeon_lookup_i2c_gpio(rdev, 799 i2c_config-> 800 ucAccess); 801 break; 802 case ATOM_HPD_INT_RECORD_TYPE: 803 hpd_record = 804 (ATOM_HPD_INT_RECORD *) 805 record; 806 gpio = radeon_lookup_gpio(rdev, 807 hpd_record->ucHPDIntGPIOID); 808 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio); 809 hpd.plugged_state = hpd_record->ucPlugged_PinState; 810 break; 811 } 812 record = 813 (ATOM_COMMON_RECORD_HEADER 814 *) ((char *)record 815 + 816 record-> 817 ucRecordSize); 818 } 819 break; 820 } 821 } 822 } 823 824 /* needed for aux chan transactions */ 825 ddc_bus.hpd = hpd.hpd; 826 827 conn_id = le16_to_cpu(path->usConnObjectId); 828 829 if (!radeon_atom_apply_quirks 830 (dev, le16_to_cpu(path->usDeviceTag), &connector_type, 831 &ddc_bus, &conn_id, &hpd)) 832 continue; 833 834 radeon_add_atom_connector(dev, 835 conn_id, 836 le16_to_cpu(path-> 837 usDeviceTag), 838 connector_type, &ddc_bus, 839 igp_lane_info, 840 connector_object_id, 841 &hpd, 842 &router); 843 844 } 845 } 846 847 radeon_link_encoder_connector(dev); 848 849 return true; 850 } 851 852 static uint16_t atombios_get_connector_object_id(struct drm_device *dev, 853 int connector_type, 854 uint16_t devices) 855 { 856 struct radeon_device *rdev = dev->dev_private; 857 858 if (rdev->flags & RADEON_IS_IGP) { 859 return supported_devices_connector_object_id_convert 860 [connector_type]; 861 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) || 862 (connector_type == DRM_MODE_CONNECTOR_DVID)) && 863 (devices & ATOM_DEVICE_DFP2_SUPPORT)) { 864 struct radeon_mode_info *mode_info = &rdev->mode_info; 865 struct atom_context *ctx = mode_info->atom_context; 866 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info); 867 uint16_t size, data_offset; 868 uint8_t frev, crev; 869 ATOM_XTMDS_INFO *xtmds; 870 871 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) { 872 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset); 873 874 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) { 875 if (connector_type == DRM_MODE_CONNECTOR_DVII) 876 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I; 877 else 878 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D; 879 } else { 880 if (connector_type == DRM_MODE_CONNECTOR_DVII) 881 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 882 else 883 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D; 884 } 885 } else 886 return supported_devices_connector_object_id_convert 887 [connector_type]; 888 } else { 889 return supported_devices_connector_object_id_convert 890 [connector_type]; 891 } 892 } 893 894 struct bios_connector { 895 bool valid; 896 uint16_t line_mux; 897 uint16_t devices; 898 int connector_type; 899 struct radeon_i2c_bus_rec ddc_bus; 900 struct radeon_hpd hpd; 901 }; 902 903 bool radeon_get_atom_connector_info_from_supported_devices_table(struct 904 drm_device 905 *dev) 906 { 907 struct radeon_device *rdev = dev->dev_private; 908 struct radeon_mode_info *mode_info = &rdev->mode_info; 909 struct atom_context *ctx = mode_info->atom_context; 910 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo); 911 uint16_t size, data_offset; 912 uint8_t frev, crev; 913 uint16_t device_support; 914 uint8_t dac; 915 union atom_supported_devices *supported_devices; 916 int i, j, max_device; 917 struct bios_connector *bios_connectors; 918 size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE; 919 struct radeon_router router; 920 921 router.ddc_valid = false; 922 router.cd_valid = false; 923 924 bios_connectors = kzalloc(bc_size, GFP_KERNEL); 925 if (!bios_connectors) 926 return false; 927 928 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, 929 &data_offset)) { 930 kfree(bios_connectors); 931 return false; 932 } 933 934 supported_devices = 935 (union atom_supported_devices *)(ctx->bios + data_offset); 936 937 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport); 938 939 if (frev > 1) 940 max_device = ATOM_MAX_SUPPORTED_DEVICE; 941 else 942 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO; 943 944 for (i = 0; i < max_device; i++) { 945 ATOM_CONNECTOR_INFO_I2C ci = 946 supported_devices->info.asConnInfo[i]; 947 948 bios_connectors[i].valid = false; 949 950 if (!(device_support & (1 << i))) { 951 continue; 952 } 953 954 if (i == ATOM_DEVICE_CV_INDEX) { 955 DRM_DEBUG_KMS("Skipping Component Video\n"); 956 continue; 957 } 958 959 bios_connectors[i].connector_type = 960 supported_devices_connector_convert[ci.sucConnectorInfo. 961 sbfAccess. 962 bfConnectorType]; 963 964 if (bios_connectors[i].connector_type == 965 DRM_MODE_CONNECTOR_Unknown) 966 continue; 967 968 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC; 969 970 bios_connectors[i].line_mux = 971 ci.sucI2cId.ucAccess; 972 973 /* give tv unique connector ids */ 974 if (i == ATOM_DEVICE_TV1_INDEX) { 975 bios_connectors[i].ddc_bus.valid = false; 976 bios_connectors[i].line_mux = 50; 977 } else if (i == ATOM_DEVICE_TV2_INDEX) { 978 bios_connectors[i].ddc_bus.valid = false; 979 bios_connectors[i].line_mux = 51; 980 } else if (i == ATOM_DEVICE_CV_INDEX) { 981 bios_connectors[i].ddc_bus.valid = false; 982 bios_connectors[i].line_mux = 52; 983 } else 984 bios_connectors[i].ddc_bus = 985 radeon_lookup_i2c_gpio(rdev, 986 bios_connectors[i].line_mux); 987 988 if ((crev > 1) && (frev > 1)) { 989 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap; 990 switch (isb) { 991 case 0x4: 992 bios_connectors[i].hpd.hpd = RADEON_HPD_1; 993 break; 994 case 0xa: 995 bios_connectors[i].hpd.hpd = RADEON_HPD_2; 996 break; 997 default: 998 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE; 999 break; 1000 } 1001 } else { 1002 if (i == ATOM_DEVICE_DFP1_INDEX) 1003 bios_connectors[i].hpd.hpd = RADEON_HPD_1; 1004 else if (i == ATOM_DEVICE_DFP2_INDEX) 1005 bios_connectors[i].hpd.hpd = RADEON_HPD_2; 1006 else 1007 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE; 1008 } 1009 1010 /* Always set the connector type to VGA for CRT1/CRT2. if they are 1011 * shared with a DVI port, we'll pick up the DVI connector when we 1012 * merge the outputs. Some bioses incorrectly list VGA ports as DVI. 1013 */ 1014 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX) 1015 bios_connectors[i].connector_type = 1016 DRM_MODE_CONNECTOR_VGA; 1017 1018 if (!radeon_atom_apply_quirks 1019 (dev, (1 << i), &bios_connectors[i].connector_type, 1020 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux, 1021 &bios_connectors[i].hpd)) 1022 continue; 1023 1024 bios_connectors[i].valid = true; 1025 bios_connectors[i].devices = (1 << i); 1026 1027 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom) 1028 radeon_add_atom_encoder(dev, 1029 radeon_get_encoder_enum(dev, 1030 (1 << i), 1031 dac), 1032 (1 << i), 1033 0); 1034 else 1035 radeon_add_legacy_encoder(dev, 1036 radeon_get_encoder_enum(dev, 1037 (1 << i), 1038 dac), 1039 (1 << i)); 1040 } 1041 1042 /* combine shared connectors */ 1043 for (i = 0; i < max_device; i++) { 1044 if (bios_connectors[i].valid) { 1045 for (j = 0; j < max_device; j++) { 1046 if (bios_connectors[j].valid && (i != j)) { 1047 if (bios_connectors[i].line_mux == 1048 bios_connectors[j].line_mux) { 1049 /* make sure not to combine LVDS */ 1050 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1051 bios_connectors[i].line_mux = 53; 1052 bios_connectors[i].ddc_bus.valid = false; 1053 continue; 1054 } 1055 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1056 bios_connectors[j].line_mux = 53; 1057 bios_connectors[j].ddc_bus.valid = false; 1058 continue; 1059 } 1060 /* combine analog and digital for DVI-I */ 1061 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) && 1062 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) || 1063 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) && 1064 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) { 1065 bios_connectors[i].devices |= 1066 bios_connectors[j].devices; 1067 bios_connectors[i].connector_type = 1068 DRM_MODE_CONNECTOR_DVII; 1069 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) 1070 bios_connectors[i].hpd = 1071 bios_connectors[j].hpd; 1072 bios_connectors[j].valid = false; 1073 } 1074 } 1075 } 1076 } 1077 } 1078 } 1079 1080 /* add the connectors */ 1081 for (i = 0; i < max_device; i++) { 1082 if (bios_connectors[i].valid) { 1083 uint16_t connector_object_id = 1084 atombios_get_connector_object_id(dev, 1085 bios_connectors[i].connector_type, 1086 bios_connectors[i].devices); 1087 radeon_add_atom_connector(dev, 1088 bios_connectors[i].line_mux, 1089 bios_connectors[i].devices, 1090 bios_connectors[i]. 1091 connector_type, 1092 &bios_connectors[i].ddc_bus, 1093 0, 1094 connector_object_id, 1095 &bios_connectors[i].hpd, 1096 &router); 1097 } 1098 } 1099 1100 radeon_link_encoder_connector(dev); 1101 1102 kfree(bios_connectors); 1103 return true; 1104 } 1105 1106 union firmware_info { 1107 ATOM_FIRMWARE_INFO info; 1108 ATOM_FIRMWARE_INFO_V1_2 info_12; 1109 ATOM_FIRMWARE_INFO_V1_3 info_13; 1110 ATOM_FIRMWARE_INFO_V1_4 info_14; 1111 ATOM_FIRMWARE_INFO_V2_1 info_21; 1112 ATOM_FIRMWARE_INFO_V2_2 info_22; 1113 }; 1114 1115 bool radeon_atom_get_clock_info(struct drm_device *dev) 1116 { 1117 struct radeon_device *rdev = dev->dev_private; 1118 struct radeon_mode_info *mode_info = &rdev->mode_info; 1119 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); 1120 union firmware_info *firmware_info; 1121 uint8_t frev, crev; 1122 struct radeon_pll *p1pll = &rdev->clock.p1pll; 1123 struct radeon_pll *p2pll = &rdev->clock.p2pll; 1124 struct radeon_pll *dcpll = &rdev->clock.dcpll; 1125 struct radeon_pll *spll = &rdev->clock.spll; 1126 struct radeon_pll *mpll = &rdev->clock.mpll; 1127 uint16_t data_offset; 1128 1129 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1130 &frev, &crev, &data_offset)) { 1131 firmware_info = 1132 (union firmware_info *)(mode_info->atom_context->bios + 1133 data_offset); 1134 /* pixel clocks */ 1135 p1pll->reference_freq = 1136 le16_to_cpu(firmware_info->info.usReferenceClock); 1137 p1pll->reference_div = 0; 1138 1139 if (crev < 2) 1140 p1pll->pll_out_min = 1141 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output); 1142 else 1143 p1pll->pll_out_min = 1144 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output); 1145 p1pll->pll_out_max = 1146 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output); 1147 1148 if (crev >= 4) { 1149 p1pll->lcd_pll_out_min = 1150 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100; 1151 if (p1pll->lcd_pll_out_min == 0) 1152 p1pll->lcd_pll_out_min = p1pll->pll_out_min; 1153 p1pll->lcd_pll_out_max = 1154 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100; 1155 if (p1pll->lcd_pll_out_max == 0) 1156 p1pll->lcd_pll_out_max = p1pll->pll_out_max; 1157 } else { 1158 p1pll->lcd_pll_out_min = p1pll->pll_out_min; 1159 p1pll->lcd_pll_out_max = p1pll->pll_out_max; 1160 } 1161 1162 if (p1pll->pll_out_min == 0) { 1163 if (ASIC_IS_AVIVO(rdev)) 1164 p1pll->pll_out_min = 64800; 1165 else 1166 p1pll->pll_out_min = 20000; 1167 } 1168 1169 p1pll->pll_in_min = 1170 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input); 1171 p1pll->pll_in_max = 1172 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input); 1173 1174 *p2pll = *p1pll; 1175 1176 /* system clock */ 1177 if (ASIC_IS_DCE4(rdev)) 1178 spll->reference_freq = 1179 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock); 1180 else 1181 spll->reference_freq = 1182 le16_to_cpu(firmware_info->info.usReferenceClock); 1183 spll->reference_div = 0; 1184 1185 spll->pll_out_min = 1186 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output); 1187 spll->pll_out_max = 1188 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output); 1189 1190 /* ??? */ 1191 if (spll->pll_out_min == 0) { 1192 if (ASIC_IS_AVIVO(rdev)) 1193 spll->pll_out_min = 64800; 1194 else 1195 spll->pll_out_min = 20000; 1196 } 1197 1198 spll->pll_in_min = 1199 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input); 1200 spll->pll_in_max = 1201 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input); 1202 1203 /* memory clock */ 1204 if (ASIC_IS_DCE4(rdev)) 1205 mpll->reference_freq = 1206 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock); 1207 else 1208 mpll->reference_freq = 1209 le16_to_cpu(firmware_info->info.usReferenceClock); 1210 mpll->reference_div = 0; 1211 1212 mpll->pll_out_min = 1213 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output); 1214 mpll->pll_out_max = 1215 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output); 1216 1217 /* ??? */ 1218 if (mpll->pll_out_min == 0) { 1219 if (ASIC_IS_AVIVO(rdev)) 1220 mpll->pll_out_min = 64800; 1221 else 1222 mpll->pll_out_min = 20000; 1223 } 1224 1225 mpll->pll_in_min = 1226 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input); 1227 mpll->pll_in_max = 1228 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input); 1229 1230 rdev->clock.default_sclk = 1231 le32_to_cpu(firmware_info->info.ulDefaultEngineClock); 1232 rdev->clock.default_mclk = 1233 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock); 1234 1235 if (ASIC_IS_DCE4(rdev)) { 1236 rdev->clock.default_dispclk = 1237 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq); 1238 if (rdev->clock.default_dispclk == 0) { 1239 if (ASIC_IS_DCE5(rdev)) 1240 rdev->clock.default_dispclk = 54000; /* 540 Mhz */ 1241 else 1242 rdev->clock.default_dispclk = 60000; /* 600 Mhz */ 1243 } 1244 rdev->clock.dp_extclk = 1245 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq); 1246 } 1247 *dcpll = *p1pll; 1248 1249 rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock); 1250 if (rdev->clock.max_pixel_clock == 0) 1251 rdev->clock.max_pixel_clock = 40000; 1252 1253 return true; 1254 } 1255 1256 return false; 1257 } 1258 1259 union igp_info { 1260 struct _ATOM_INTEGRATED_SYSTEM_INFO info; 1261 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2; 1262 }; 1263 1264 bool radeon_atombios_sideport_present(struct radeon_device *rdev) 1265 { 1266 struct radeon_mode_info *mode_info = &rdev->mode_info; 1267 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); 1268 union igp_info *igp_info; 1269 u8 frev, crev; 1270 u16 data_offset; 1271 1272 /* sideport is AMD only */ 1273 if (rdev->family == CHIP_RS600) 1274 return false; 1275 1276 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1277 &frev, &crev, &data_offset)) { 1278 igp_info = (union igp_info *)(mode_info->atom_context->bios + 1279 data_offset); 1280 switch (crev) { 1281 case 1: 1282 if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock)) 1283 return true; 1284 break; 1285 case 2: 1286 if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock)) 1287 return true; 1288 break; 1289 default: 1290 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev); 1291 break; 1292 } 1293 } 1294 return false; 1295 } 1296 1297 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, 1298 struct radeon_encoder_int_tmds *tmds) 1299 { 1300 struct drm_device *dev = encoder->base.dev; 1301 struct radeon_device *rdev = dev->dev_private; 1302 struct radeon_mode_info *mode_info = &rdev->mode_info; 1303 int index = GetIndexIntoMasterTable(DATA, TMDS_Info); 1304 uint16_t data_offset; 1305 struct _ATOM_TMDS_INFO *tmds_info; 1306 uint8_t frev, crev; 1307 uint16_t maxfreq; 1308 int i; 1309 1310 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1311 &frev, &crev, &data_offset)) { 1312 tmds_info = 1313 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios + 1314 data_offset); 1315 1316 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency); 1317 for (i = 0; i < 4; i++) { 1318 tmds->tmds_pll[i].freq = 1319 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency); 1320 tmds->tmds_pll[i].value = 1321 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f; 1322 tmds->tmds_pll[i].value |= 1323 (tmds_info->asMiscInfo[i]. 1324 ucPLL_VCO_Gain & 0x3f) << 6; 1325 tmds->tmds_pll[i].value |= 1326 (tmds_info->asMiscInfo[i]. 1327 ucPLL_DutyCycle & 0xf) << 12; 1328 tmds->tmds_pll[i].value |= 1329 (tmds_info->asMiscInfo[i]. 1330 ucPLL_VoltageSwing & 0xf) << 16; 1331 1332 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n", 1333 tmds->tmds_pll[i].freq, 1334 tmds->tmds_pll[i].value); 1335 1336 if (maxfreq == tmds->tmds_pll[i].freq) { 1337 tmds->tmds_pll[i].freq = 0xffffffff; 1338 break; 1339 } 1340 } 1341 return true; 1342 } 1343 return false; 1344 } 1345 1346 bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev, 1347 struct radeon_atom_ss *ss, 1348 int id) 1349 { 1350 struct radeon_mode_info *mode_info = &rdev->mode_info; 1351 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info); 1352 uint16_t data_offset, size; 1353 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info; 1354 uint8_t frev, crev; 1355 int i, num_indices; 1356 1357 memset(ss, 0, sizeof(struct radeon_atom_ss)); 1358 if (atom_parse_data_header(mode_info->atom_context, index, &size, 1359 &frev, &crev, &data_offset)) { 1360 ss_info = 1361 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset); 1362 1363 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 1364 sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT); 1365 1366 for (i = 0; i < num_indices; i++) { 1367 if (ss_info->asSS_Info[i].ucSS_Id == id) { 1368 ss->percentage = 1369 le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage); 1370 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType; 1371 ss->step = ss_info->asSS_Info[i].ucSS_Step; 1372 ss->delay = ss_info->asSS_Info[i].ucSS_Delay; 1373 ss->range = ss_info->asSS_Info[i].ucSS_Range; 1374 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div; 1375 return true; 1376 } 1377 } 1378 } 1379 return false; 1380 } 1381 1382 static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev, 1383 struct radeon_atom_ss *ss, 1384 int id) 1385 { 1386 struct radeon_mode_info *mode_info = &rdev->mode_info; 1387 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); 1388 u16 data_offset, size; 1389 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 *igp_info; 1390 u8 frev, crev; 1391 u16 percentage = 0, rate = 0; 1392 1393 /* get any igp specific overrides */ 1394 if (atom_parse_data_header(mode_info->atom_context, index, &size, 1395 &frev, &crev, &data_offset)) { 1396 igp_info = (struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 *) 1397 (mode_info->atom_context->bios + data_offset); 1398 switch (id) { 1399 case ASIC_INTERNAL_SS_ON_TMDS: 1400 percentage = le16_to_cpu(igp_info->usDVISSPercentage); 1401 rate = le16_to_cpu(igp_info->usDVISSpreadRateIn10Hz); 1402 break; 1403 case ASIC_INTERNAL_SS_ON_HDMI: 1404 percentage = le16_to_cpu(igp_info->usHDMISSPercentage); 1405 rate = le16_to_cpu(igp_info->usHDMISSpreadRateIn10Hz); 1406 break; 1407 case ASIC_INTERNAL_SS_ON_LVDS: 1408 percentage = le16_to_cpu(igp_info->usLvdsSSPercentage); 1409 rate = le16_to_cpu(igp_info->usLvdsSSpreadRateIn10Hz); 1410 break; 1411 } 1412 if (percentage) 1413 ss->percentage = percentage; 1414 if (rate) 1415 ss->rate = rate; 1416 } 1417 } 1418 1419 union asic_ss_info { 1420 struct _ATOM_ASIC_INTERNAL_SS_INFO info; 1421 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2; 1422 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3; 1423 }; 1424 1425 bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev, 1426 struct radeon_atom_ss *ss, 1427 int id, u32 clock) 1428 { 1429 struct radeon_mode_info *mode_info = &rdev->mode_info; 1430 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info); 1431 uint16_t data_offset, size; 1432 union asic_ss_info *ss_info; 1433 uint8_t frev, crev; 1434 int i, num_indices; 1435 1436 memset(ss, 0, sizeof(struct radeon_atom_ss)); 1437 if (atom_parse_data_header(mode_info->atom_context, index, &size, 1438 &frev, &crev, &data_offset)) { 1439 1440 ss_info = 1441 (union asic_ss_info *)(mode_info->atom_context->bios + data_offset); 1442 1443 switch (frev) { 1444 case 1: 1445 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 1446 sizeof(ATOM_ASIC_SS_ASSIGNMENT); 1447 1448 for (i = 0; i < num_indices; i++) { 1449 if ((ss_info->info.asSpreadSpectrum[i].ucClockIndication == id) && 1450 (clock <= le32_to_cpu(ss_info->info.asSpreadSpectrum[i].ulTargetClockRange))) { 1451 ss->percentage = 1452 le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadSpectrumPercentage); 1453 ss->type = ss_info->info.asSpreadSpectrum[i].ucSpreadSpectrumMode; 1454 ss->rate = le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadRateInKhz); 1455 return true; 1456 } 1457 } 1458 break; 1459 case 2: 1460 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 1461 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2); 1462 for (i = 0; i < num_indices; i++) { 1463 if ((ss_info->info_2.asSpreadSpectrum[i].ucClockIndication == id) && 1464 (clock <= le32_to_cpu(ss_info->info_2.asSpreadSpectrum[i].ulTargetClockRange))) { 1465 ss->percentage = 1466 le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadSpectrumPercentage); 1467 ss->type = ss_info->info_2.asSpreadSpectrum[i].ucSpreadSpectrumMode; 1468 ss->rate = le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadRateIn10Hz); 1469 return true; 1470 } 1471 } 1472 break; 1473 case 3: 1474 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 1475 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3); 1476 for (i = 0; i < num_indices; i++) { 1477 if ((ss_info->info_3.asSpreadSpectrum[i].ucClockIndication == id) && 1478 (clock <= le32_to_cpu(ss_info->info_3.asSpreadSpectrum[i].ulTargetClockRange))) { 1479 ss->percentage = 1480 le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadSpectrumPercentage); 1481 ss->type = ss_info->info_3.asSpreadSpectrum[i].ucSpreadSpectrumMode; 1482 ss->rate = le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadRateIn10Hz); 1483 if (rdev->flags & RADEON_IS_IGP) 1484 radeon_atombios_get_igp_ss_overrides(rdev, ss, id); 1485 return true; 1486 } 1487 } 1488 break; 1489 default: 1490 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev); 1491 break; 1492 } 1493 1494 } 1495 return false; 1496 } 1497 1498 union lvds_info { 1499 struct _ATOM_LVDS_INFO info; 1500 struct _ATOM_LVDS_INFO_V12 info_12; 1501 }; 1502 1503 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct 1504 radeon_encoder 1505 *encoder) 1506 { 1507 struct drm_device *dev = encoder->base.dev; 1508 struct radeon_device *rdev = dev->dev_private; 1509 struct radeon_mode_info *mode_info = &rdev->mode_info; 1510 int index = GetIndexIntoMasterTable(DATA, LVDS_Info); 1511 uint16_t data_offset, misc; 1512 union lvds_info *lvds_info; 1513 uint8_t frev, crev; 1514 struct radeon_encoder_atom_dig *lvds = NULL; 1515 int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; 1516 1517 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1518 &frev, &crev, &data_offset)) { 1519 lvds_info = 1520 (union lvds_info *)(mode_info->atom_context->bios + data_offset); 1521 lvds = 1522 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); 1523 1524 if (!lvds) 1525 return NULL; 1526 1527 lvds->native_mode.clock = 1528 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10; 1529 lvds->native_mode.hdisplay = 1530 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive); 1531 lvds->native_mode.vdisplay = 1532 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive); 1533 lvds->native_mode.htotal = lvds->native_mode.hdisplay + 1534 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time); 1535 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay + 1536 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset); 1537 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start + 1538 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth); 1539 lvds->native_mode.vtotal = lvds->native_mode.vdisplay + 1540 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time); 1541 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay + 1542 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset); 1543 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start + 1544 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth); 1545 lvds->panel_pwr_delay = 1546 le16_to_cpu(lvds_info->info.usOffDelayInMs); 1547 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc; 1548 1549 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess); 1550 if (misc & ATOM_VSYNC_POLARITY) 1551 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC; 1552 if (misc & ATOM_HSYNC_POLARITY) 1553 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC; 1554 if (misc & ATOM_COMPOSITESYNC) 1555 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC; 1556 if (misc & ATOM_INTERLACE) 1557 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE; 1558 if (misc & ATOM_DOUBLE_CLOCK_MODE) 1559 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN; 1560 1561 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize); 1562 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize); 1563 1564 /* set crtc values */ 1565 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V); 1566 1567 lvds->lcd_ss_id = lvds_info->info.ucSS_Id; 1568 1569 encoder->native_mode = lvds->native_mode; 1570 1571 if (encoder_enum == 2) 1572 lvds->linkb = true; 1573 else 1574 lvds->linkb = false; 1575 1576 /* parse the lcd record table */ 1577 if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) { 1578 ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record; 1579 ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record; 1580 bool bad_record = false; 1581 u8 *record; 1582 1583 if ((frev == 1) && (crev < 2)) 1584 /* absolute */ 1585 record = (u8 *)(mode_info->atom_context->bios + 1586 le16_to_cpu(lvds_info->info.usModePatchTableOffset)); 1587 else 1588 /* relative */ 1589 record = (u8 *)(mode_info->atom_context->bios + 1590 data_offset + 1591 le16_to_cpu(lvds_info->info.usModePatchTableOffset)); 1592 while (*record != ATOM_RECORD_END_TYPE) { 1593 switch (*record) { 1594 case LCD_MODE_PATCH_RECORD_MODE_TYPE: 1595 record += sizeof(ATOM_PATCH_RECORD_MODE); 1596 break; 1597 case LCD_RTS_RECORD_TYPE: 1598 record += sizeof(ATOM_LCD_RTS_RECORD); 1599 break; 1600 case LCD_CAP_RECORD_TYPE: 1601 record += sizeof(ATOM_LCD_MODE_CONTROL_CAP); 1602 break; 1603 case LCD_FAKE_EDID_PATCH_RECORD_TYPE: 1604 fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record; 1605 if (fake_edid_record->ucFakeEDIDLength) { 1606 struct edid *edid; 1607 int edid_size = 1608 max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength); 1609 edid = kmalloc(edid_size, GFP_KERNEL); 1610 if (edid) { 1611 memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0], 1612 fake_edid_record->ucFakeEDIDLength); 1613 1614 if (drm_edid_is_valid(edid)) { 1615 rdev->mode_info.bios_hardcoded_edid = edid; 1616 rdev->mode_info.bios_hardcoded_edid_size = edid_size; 1617 } else 1618 kfree(edid); 1619 } 1620 } 1621 record += sizeof(ATOM_FAKE_EDID_PATCH_RECORD); 1622 break; 1623 case LCD_PANEL_RESOLUTION_RECORD_TYPE: 1624 panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record; 1625 lvds->native_mode.width_mm = panel_res_record->usHSize; 1626 lvds->native_mode.height_mm = panel_res_record->usVSize; 1627 record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD); 1628 break; 1629 default: 1630 DRM_ERROR("Bad LCD record %d\n", *record); 1631 bad_record = true; 1632 break; 1633 } 1634 if (bad_record) 1635 break; 1636 } 1637 } 1638 } 1639 return lvds; 1640 } 1641 1642 struct radeon_encoder_primary_dac * 1643 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder) 1644 { 1645 struct drm_device *dev = encoder->base.dev; 1646 struct radeon_device *rdev = dev->dev_private; 1647 struct radeon_mode_info *mode_info = &rdev->mode_info; 1648 int index = GetIndexIntoMasterTable(DATA, CompassionateData); 1649 uint16_t data_offset; 1650 struct _COMPASSIONATE_DATA *dac_info; 1651 uint8_t frev, crev; 1652 uint8_t bg, dac; 1653 struct radeon_encoder_primary_dac *p_dac = NULL; 1654 1655 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1656 &frev, &crev, &data_offset)) { 1657 dac_info = (struct _COMPASSIONATE_DATA *) 1658 (mode_info->atom_context->bios + data_offset); 1659 1660 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL); 1661 1662 if (!p_dac) 1663 return NULL; 1664 1665 bg = dac_info->ucDAC1_BG_Adjustment; 1666 dac = dac_info->ucDAC1_DAC_Adjustment; 1667 p_dac->ps2_pdac_adj = (bg << 8) | (dac); 1668 1669 } 1670 return p_dac; 1671 } 1672 1673 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, 1674 struct drm_display_mode *mode) 1675 { 1676 struct radeon_mode_info *mode_info = &rdev->mode_info; 1677 ATOM_ANALOG_TV_INFO *tv_info; 1678 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2; 1679 ATOM_DTD_FORMAT *dtd_timings; 1680 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info); 1681 u8 frev, crev; 1682 u16 data_offset, misc; 1683 1684 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL, 1685 &frev, &crev, &data_offset)) 1686 return false; 1687 1688 switch (crev) { 1689 case 1: 1690 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset); 1691 if (index >= MAX_SUPPORTED_TV_TIMING) 1692 return false; 1693 1694 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total); 1695 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp); 1696 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart); 1697 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) + 1698 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth); 1699 1700 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total); 1701 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp); 1702 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart); 1703 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) + 1704 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth); 1705 1706 mode->flags = 0; 1707 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess); 1708 if (misc & ATOM_VSYNC_POLARITY) 1709 mode->flags |= DRM_MODE_FLAG_NVSYNC; 1710 if (misc & ATOM_HSYNC_POLARITY) 1711 mode->flags |= DRM_MODE_FLAG_NHSYNC; 1712 if (misc & ATOM_COMPOSITESYNC) 1713 mode->flags |= DRM_MODE_FLAG_CSYNC; 1714 if (misc & ATOM_INTERLACE) 1715 mode->flags |= DRM_MODE_FLAG_INTERLACE; 1716 if (misc & ATOM_DOUBLE_CLOCK_MODE) 1717 mode->flags |= DRM_MODE_FLAG_DBLSCAN; 1718 1719 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10; 1720 1721 if (index == 1) { 1722 /* PAL timings appear to have wrong values for totals */ 1723 mode->crtc_htotal -= 1; 1724 mode->crtc_vtotal -= 1; 1725 } 1726 break; 1727 case 2: 1728 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset); 1729 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2) 1730 return false; 1731 1732 dtd_timings = &tv_info_v1_2->aModeTimings[index]; 1733 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) + 1734 le16_to_cpu(dtd_timings->usHBlanking_Time); 1735 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive); 1736 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) + 1737 le16_to_cpu(dtd_timings->usHSyncOffset); 1738 mode->crtc_hsync_end = mode->crtc_hsync_start + 1739 le16_to_cpu(dtd_timings->usHSyncWidth); 1740 1741 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) + 1742 le16_to_cpu(dtd_timings->usVBlanking_Time); 1743 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive); 1744 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) + 1745 le16_to_cpu(dtd_timings->usVSyncOffset); 1746 mode->crtc_vsync_end = mode->crtc_vsync_start + 1747 le16_to_cpu(dtd_timings->usVSyncWidth); 1748 1749 mode->flags = 0; 1750 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess); 1751 if (misc & ATOM_VSYNC_POLARITY) 1752 mode->flags |= DRM_MODE_FLAG_NVSYNC; 1753 if (misc & ATOM_HSYNC_POLARITY) 1754 mode->flags |= DRM_MODE_FLAG_NHSYNC; 1755 if (misc & ATOM_COMPOSITESYNC) 1756 mode->flags |= DRM_MODE_FLAG_CSYNC; 1757 if (misc & ATOM_INTERLACE) 1758 mode->flags |= DRM_MODE_FLAG_INTERLACE; 1759 if (misc & ATOM_DOUBLE_CLOCK_MODE) 1760 mode->flags |= DRM_MODE_FLAG_DBLSCAN; 1761 1762 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10; 1763 break; 1764 } 1765 return true; 1766 } 1767 1768 enum radeon_tv_std 1769 radeon_atombios_get_tv_info(struct radeon_device *rdev) 1770 { 1771 struct radeon_mode_info *mode_info = &rdev->mode_info; 1772 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info); 1773 uint16_t data_offset; 1774 uint8_t frev, crev; 1775 struct _ATOM_ANALOG_TV_INFO *tv_info; 1776 enum radeon_tv_std tv_std = TV_STD_NTSC; 1777 1778 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1779 &frev, &crev, &data_offset)) { 1780 1781 tv_info = (struct _ATOM_ANALOG_TV_INFO *) 1782 (mode_info->atom_context->bios + data_offset); 1783 1784 switch (tv_info->ucTV_BootUpDefaultStandard) { 1785 case ATOM_TV_NTSC: 1786 tv_std = TV_STD_NTSC; 1787 DRM_DEBUG_KMS("Default TV standard: NTSC\n"); 1788 break; 1789 case ATOM_TV_NTSCJ: 1790 tv_std = TV_STD_NTSC_J; 1791 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n"); 1792 break; 1793 case ATOM_TV_PAL: 1794 tv_std = TV_STD_PAL; 1795 DRM_DEBUG_KMS("Default TV standard: PAL\n"); 1796 break; 1797 case ATOM_TV_PALM: 1798 tv_std = TV_STD_PAL_M; 1799 DRM_DEBUG_KMS("Default TV standard: PAL-M\n"); 1800 break; 1801 case ATOM_TV_PALN: 1802 tv_std = TV_STD_PAL_N; 1803 DRM_DEBUG_KMS("Default TV standard: PAL-N\n"); 1804 break; 1805 case ATOM_TV_PALCN: 1806 tv_std = TV_STD_PAL_CN; 1807 DRM_DEBUG_KMS("Default TV standard: PAL-CN\n"); 1808 break; 1809 case ATOM_TV_PAL60: 1810 tv_std = TV_STD_PAL_60; 1811 DRM_DEBUG_KMS("Default TV standard: PAL-60\n"); 1812 break; 1813 case ATOM_TV_SECAM: 1814 tv_std = TV_STD_SECAM; 1815 DRM_DEBUG_KMS("Default TV standard: SECAM\n"); 1816 break; 1817 default: 1818 tv_std = TV_STD_NTSC; 1819 DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n"); 1820 break; 1821 } 1822 } 1823 return tv_std; 1824 } 1825 1826 struct radeon_encoder_tv_dac * 1827 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder) 1828 { 1829 struct drm_device *dev = encoder->base.dev; 1830 struct radeon_device *rdev = dev->dev_private; 1831 struct radeon_mode_info *mode_info = &rdev->mode_info; 1832 int index = GetIndexIntoMasterTable(DATA, CompassionateData); 1833 uint16_t data_offset; 1834 struct _COMPASSIONATE_DATA *dac_info; 1835 uint8_t frev, crev; 1836 uint8_t bg, dac; 1837 struct radeon_encoder_tv_dac *tv_dac = NULL; 1838 1839 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1840 &frev, &crev, &data_offset)) { 1841 1842 dac_info = (struct _COMPASSIONATE_DATA *) 1843 (mode_info->atom_context->bios + data_offset); 1844 1845 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL); 1846 1847 if (!tv_dac) 1848 return NULL; 1849 1850 bg = dac_info->ucDAC2_CRT2_BG_Adjustment; 1851 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment; 1852 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20); 1853 1854 bg = dac_info->ucDAC2_PAL_BG_Adjustment; 1855 dac = dac_info->ucDAC2_PAL_DAC_Adjustment; 1856 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20); 1857 1858 bg = dac_info->ucDAC2_NTSC_BG_Adjustment; 1859 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment; 1860 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); 1861 1862 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev); 1863 } 1864 return tv_dac; 1865 } 1866 1867 static const char *thermal_controller_names[] = { 1868 "NONE", 1869 "lm63", 1870 "adm1032", 1871 "adm1030", 1872 "max6649", 1873 "lm64", 1874 "f75375", 1875 "asc7xxx", 1876 }; 1877 1878 static const char *pp_lib_thermal_controller_names[] = { 1879 "NONE", 1880 "lm63", 1881 "adm1032", 1882 "adm1030", 1883 "max6649", 1884 "lm64", 1885 "f75375", 1886 "RV6xx", 1887 "RV770", 1888 "adt7473", 1889 "NONE", 1890 "External GPIO", 1891 "Evergreen", 1892 "emc2103", 1893 "Sumo", 1894 "Northern Islands", 1895 }; 1896 1897 union power_info { 1898 struct _ATOM_POWERPLAY_INFO info; 1899 struct _ATOM_POWERPLAY_INFO_V2 info_2; 1900 struct _ATOM_POWERPLAY_INFO_V3 info_3; 1901 struct _ATOM_PPLIB_POWERPLAYTABLE pplib; 1902 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; 1903 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; 1904 }; 1905 1906 union pplib_clock_info { 1907 struct _ATOM_PPLIB_R600_CLOCK_INFO r600; 1908 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; 1909 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; 1910 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; 1911 }; 1912 1913 union pplib_power_state { 1914 struct _ATOM_PPLIB_STATE v1; 1915 struct _ATOM_PPLIB_STATE_V2 v2; 1916 }; 1917 1918 static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev, 1919 int state_index, 1920 u32 misc, u32 misc2) 1921 { 1922 rdev->pm.power_state[state_index].misc = misc; 1923 rdev->pm.power_state[state_index].misc2 = misc2; 1924 /* order matters! */ 1925 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE) 1926 rdev->pm.power_state[state_index].type = 1927 POWER_STATE_TYPE_POWERSAVE; 1928 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE) 1929 rdev->pm.power_state[state_index].type = 1930 POWER_STATE_TYPE_BATTERY; 1931 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE) 1932 rdev->pm.power_state[state_index].type = 1933 POWER_STATE_TYPE_BATTERY; 1934 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN) 1935 rdev->pm.power_state[state_index].type = 1936 POWER_STATE_TYPE_BALANCED; 1937 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) { 1938 rdev->pm.power_state[state_index].type = 1939 POWER_STATE_TYPE_PERFORMANCE; 1940 rdev->pm.power_state[state_index].flags &= 1941 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 1942 } 1943 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE) 1944 rdev->pm.power_state[state_index].type = 1945 POWER_STATE_TYPE_BALANCED; 1946 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) { 1947 rdev->pm.power_state[state_index].type = 1948 POWER_STATE_TYPE_DEFAULT; 1949 rdev->pm.default_power_state_index = state_index; 1950 rdev->pm.power_state[state_index].default_clock_mode = 1951 &rdev->pm.power_state[state_index].clock_info[0]; 1952 } else if (state_index == 0) { 1953 rdev->pm.power_state[state_index].clock_info[0].flags |= 1954 RADEON_PM_MODE_NO_DISPLAY; 1955 } 1956 } 1957 1958 static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev) 1959 { 1960 struct radeon_mode_info *mode_info = &rdev->mode_info; 1961 u32 misc, misc2 = 0; 1962 int num_modes = 0, i; 1963 int state_index = 0; 1964 struct radeon_i2c_bus_rec i2c_bus; 1965 union power_info *power_info; 1966 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 1967 u16 data_offset; 1968 u8 frev, crev; 1969 1970 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 1971 &frev, &crev, &data_offset)) 1972 return state_index; 1973 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 1974 1975 /* add the i2c bus for thermal/fan chip */ 1976 if (power_info->info.ucOverdriveThermalController > 0) { 1977 DRM_INFO("Possible %s thermal controller at 0x%02x\n", 1978 thermal_controller_names[power_info->info.ucOverdriveThermalController], 1979 power_info->info.ucOverdriveControllerAddress >> 1); 1980 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine); 1981 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 1982 if (rdev->pm.i2c_bus) { 1983 struct i2c_board_info info = { }; 1984 const char *name = thermal_controller_names[power_info->info. 1985 ucOverdriveThermalController]; 1986 info.addr = power_info->info.ucOverdriveControllerAddress >> 1; 1987 strlcpy(info.type, name, sizeof(info.type)); 1988 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info); 1989 } 1990 } 1991 num_modes = power_info->info.ucNumOfPowerModeEntries; 1992 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK) 1993 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK; 1994 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * num_modes, GFP_KERNEL); 1995 if (!rdev->pm.power_state) 1996 return state_index; 1997 /* last mode is usually default, array is low to high */ 1998 for (i = 0; i < num_modes; i++) { 1999 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; 2000 switch (frev) { 2001 case 1: 2002 rdev->pm.power_state[state_index].clock_info = 2003 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL); 2004 if (!rdev->pm.power_state[state_index].clock_info) 2005 return state_index; 2006 rdev->pm.power_state[state_index].num_clock_modes = 1; 2007 rdev->pm.power_state[state_index].clock_info[0].mclk = 2008 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock); 2009 rdev->pm.power_state[state_index].clock_info[0].sclk = 2010 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock); 2011 /* skip invalid modes */ 2012 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || 2013 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) 2014 continue; 2015 rdev->pm.power_state[state_index].pcie_lanes = 2016 power_info->info.asPowerPlayInfo[i].ucNumPciELanes; 2017 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo); 2018 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) || 2019 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) { 2020 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2021 VOLTAGE_GPIO; 2022 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio = 2023 radeon_lookup_gpio(rdev, 2024 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex); 2025 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH) 2026 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2027 true; 2028 else 2029 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2030 false; 2031 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) { 2032 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2033 VOLTAGE_VDDC; 2034 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id = 2035 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex; 2036 } 2037 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2038 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0); 2039 state_index++; 2040 break; 2041 case 2: 2042 rdev->pm.power_state[state_index].clock_info = 2043 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL); 2044 if (!rdev->pm.power_state[state_index].clock_info) 2045 return state_index; 2046 rdev->pm.power_state[state_index].num_clock_modes = 1; 2047 rdev->pm.power_state[state_index].clock_info[0].mclk = 2048 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock); 2049 rdev->pm.power_state[state_index].clock_info[0].sclk = 2050 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock); 2051 /* skip invalid modes */ 2052 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || 2053 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) 2054 continue; 2055 rdev->pm.power_state[state_index].pcie_lanes = 2056 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes; 2057 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo); 2058 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2); 2059 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) || 2060 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) { 2061 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2062 VOLTAGE_GPIO; 2063 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio = 2064 radeon_lookup_gpio(rdev, 2065 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex); 2066 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH) 2067 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2068 true; 2069 else 2070 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2071 false; 2072 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) { 2073 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2074 VOLTAGE_VDDC; 2075 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id = 2076 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex; 2077 } 2078 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2079 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2); 2080 state_index++; 2081 break; 2082 case 3: 2083 rdev->pm.power_state[state_index].clock_info = 2084 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL); 2085 if (!rdev->pm.power_state[state_index].clock_info) 2086 return state_index; 2087 rdev->pm.power_state[state_index].num_clock_modes = 1; 2088 rdev->pm.power_state[state_index].clock_info[0].mclk = 2089 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock); 2090 rdev->pm.power_state[state_index].clock_info[0].sclk = 2091 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock); 2092 /* skip invalid modes */ 2093 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || 2094 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) 2095 continue; 2096 rdev->pm.power_state[state_index].pcie_lanes = 2097 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes; 2098 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo); 2099 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2); 2100 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) || 2101 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) { 2102 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2103 VOLTAGE_GPIO; 2104 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio = 2105 radeon_lookup_gpio(rdev, 2106 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex); 2107 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH) 2108 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2109 true; 2110 else 2111 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2112 false; 2113 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) { 2114 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2115 VOLTAGE_VDDC; 2116 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id = 2117 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex; 2118 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) { 2119 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled = 2120 true; 2121 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id = 2122 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex; 2123 } 2124 } 2125 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2126 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2); 2127 state_index++; 2128 break; 2129 } 2130 } 2131 /* last mode is usually default */ 2132 if (rdev->pm.default_power_state_index == -1) { 2133 rdev->pm.power_state[state_index - 1].type = 2134 POWER_STATE_TYPE_DEFAULT; 2135 rdev->pm.default_power_state_index = state_index - 1; 2136 rdev->pm.power_state[state_index - 1].default_clock_mode = 2137 &rdev->pm.power_state[state_index - 1].clock_info[0]; 2138 rdev->pm.power_state[state_index].flags &= 2139 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2140 rdev->pm.power_state[state_index].misc = 0; 2141 rdev->pm.power_state[state_index].misc2 = 0; 2142 } 2143 return state_index; 2144 } 2145 2146 static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev, 2147 ATOM_PPLIB_THERMALCONTROLLER *controller) 2148 { 2149 struct radeon_i2c_bus_rec i2c_bus; 2150 2151 /* add the i2c bus for thermal/fan chip */ 2152 if (controller->ucType > 0) { 2153 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) { 2154 DRM_INFO("Internal thermal controller %s fan control\n", 2155 (controller->ucFanParameters & 2156 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2157 rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX; 2158 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) { 2159 DRM_INFO("Internal thermal controller %s fan control\n", 2160 (controller->ucFanParameters & 2161 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2162 rdev->pm.int_thermal_type = THERMAL_TYPE_RV770; 2163 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) { 2164 DRM_INFO("Internal thermal controller %s fan control\n", 2165 (controller->ucFanParameters & 2166 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2167 rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN; 2168 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) { 2169 DRM_INFO("Internal thermal controller %s fan control\n", 2170 (controller->ucFanParameters & 2171 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2172 rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO; 2173 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) { 2174 DRM_INFO("Internal thermal controller %s fan control\n", 2175 (controller->ucFanParameters & 2176 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2177 rdev->pm.int_thermal_type = THERMAL_TYPE_NI; 2178 } else if ((controller->ucType == 2179 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) || 2180 (controller->ucType == 2181 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) || 2182 (controller->ucType == 2183 ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL)) { 2184 DRM_INFO("Special thermal controller config\n"); 2185 } else { 2186 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n", 2187 pp_lib_thermal_controller_names[controller->ucType], 2188 controller->ucI2cAddress >> 1, 2189 (controller->ucFanParameters & 2190 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2191 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine); 2192 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 2193 if (rdev->pm.i2c_bus) { 2194 struct i2c_board_info info = { }; 2195 const char *name = pp_lib_thermal_controller_names[controller->ucType]; 2196 info.addr = controller->ucI2cAddress >> 1; 2197 strlcpy(info.type, name, sizeof(info.type)); 2198 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info); 2199 } 2200 } 2201 } 2202 } 2203 2204 static void radeon_atombios_get_default_voltages(struct radeon_device *rdev, 2205 u16 *vddc, u16 *vddci) 2206 { 2207 struct radeon_mode_info *mode_info = &rdev->mode_info; 2208 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); 2209 u8 frev, crev; 2210 u16 data_offset; 2211 union firmware_info *firmware_info; 2212 2213 *vddc = 0; 2214 *vddci = 0; 2215 2216 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 2217 &frev, &crev, &data_offset)) { 2218 firmware_info = 2219 (union firmware_info *)(mode_info->atom_context->bios + 2220 data_offset); 2221 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage); 2222 if ((frev == 2) && (crev >= 2)) 2223 *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage); 2224 } 2225 } 2226 2227 static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev, 2228 int state_index, int mode_index, 2229 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info) 2230 { 2231 int j; 2232 u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings); 2233 u32 misc2 = le16_to_cpu(non_clock_info->usClassification); 2234 u16 vddc, vddci; 2235 2236 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci); 2237 2238 rdev->pm.power_state[state_index].misc = misc; 2239 rdev->pm.power_state[state_index].misc2 = misc2; 2240 rdev->pm.power_state[state_index].pcie_lanes = 2241 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> 2242 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; 2243 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) { 2244 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY: 2245 rdev->pm.power_state[state_index].type = 2246 POWER_STATE_TYPE_BATTERY; 2247 break; 2248 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED: 2249 rdev->pm.power_state[state_index].type = 2250 POWER_STATE_TYPE_BALANCED; 2251 break; 2252 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE: 2253 rdev->pm.power_state[state_index].type = 2254 POWER_STATE_TYPE_PERFORMANCE; 2255 break; 2256 case ATOM_PPLIB_CLASSIFICATION_UI_NONE: 2257 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE) 2258 rdev->pm.power_state[state_index].type = 2259 POWER_STATE_TYPE_PERFORMANCE; 2260 break; 2261 } 2262 rdev->pm.power_state[state_index].flags = 0; 2263 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) 2264 rdev->pm.power_state[state_index].flags |= 2265 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2266 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) { 2267 rdev->pm.power_state[state_index].type = 2268 POWER_STATE_TYPE_DEFAULT; 2269 rdev->pm.default_power_state_index = state_index; 2270 rdev->pm.power_state[state_index].default_clock_mode = 2271 &rdev->pm.power_state[state_index].clock_info[mode_index - 1]; 2272 if (ASIC_IS_DCE5(rdev) && !(rdev->flags & RADEON_IS_IGP)) { 2273 /* NI chips post without MC ucode, so default clocks are strobe mode only */ 2274 rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk; 2275 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk; 2276 rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage; 2277 rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci; 2278 } else { 2279 /* patch the table values with the default slck/mclk from firmware info */ 2280 for (j = 0; j < mode_index; j++) { 2281 rdev->pm.power_state[state_index].clock_info[j].mclk = 2282 rdev->clock.default_mclk; 2283 rdev->pm.power_state[state_index].clock_info[j].sclk = 2284 rdev->clock.default_sclk; 2285 if (vddc) 2286 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage = 2287 vddc; 2288 } 2289 } 2290 } 2291 } 2292 2293 static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev, 2294 int state_index, int mode_index, 2295 union pplib_clock_info *clock_info) 2296 { 2297 u32 sclk, mclk; 2298 2299 if (rdev->flags & RADEON_IS_IGP) { 2300 if (rdev->family >= CHIP_PALM) { 2301 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow); 2302 sclk |= clock_info->sumo.ucEngineClockHigh << 16; 2303 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2304 } else { 2305 sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow); 2306 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16; 2307 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2308 } 2309 } else if (ASIC_IS_DCE4(rdev)) { 2310 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow); 2311 sclk |= clock_info->evergreen.ucEngineClockHigh << 16; 2312 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow); 2313 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16; 2314 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk; 2315 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2316 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = 2317 VOLTAGE_SW; 2318 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = 2319 le16_to_cpu(clock_info->evergreen.usVDDC); 2320 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci = 2321 le16_to_cpu(clock_info->evergreen.usVDDCI); 2322 } else { 2323 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow); 2324 sclk |= clock_info->r600.ucEngineClockHigh << 16; 2325 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow); 2326 mclk |= clock_info->r600.ucMemoryClockHigh << 16; 2327 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk; 2328 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2329 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = 2330 VOLTAGE_SW; 2331 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = 2332 le16_to_cpu(clock_info->r600.usVDDC); 2333 } 2334 2335 /* patch up vddc if necessary */ 2336 if (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage == 0xff01) { 2337 u16 vddc; 2338 2339 if (radeon_atom_get_max_vddc(rdev, &vddc) == 0) 2340 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc; 2341 } 2342 2343 if (rdev->flags & RADEON_IS_IGP) { 2344 /* skip invalid modes */ 2345 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0) 2346 return false; 2347 } else { 2348 /* skip invalid modes */ 2349 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) || 2350 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)) 2351 return false; 2352 } 2353 return true; 2354 } 2355 2356 static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev) 2357 { 2358 struct radeon_mode_info *mode_info = &rdev->mode_info; 2359 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 2360 union pplib_power_state *power_state; 2361 int i, j; 2362 int state_index = 0, mode_index = 0; 2363 union pplib_clock_info *clock_info; 2364 bool valid; 2365 union power_info *power_info; 2366 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 2367 u16 data_offset; 2368 u8 frev, crev; 2369 2370 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 2371 &frev, &crev, &data_offset)) 2372 return state_index; 2373 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 2374 2375 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController); 2376 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * 2377 power_info->pplib.ucNumStates, GFP_KERNEL); 2378 if (!rdev->pm.power_state) 2379 return state_index; 2380 /* first mode is usually default, followed by low to high */ 2381 for (i = 0; i < power_info->pplib.ucNumStates; i++) { 2382 mode_index = 0; 2383 power_state = (union pplib_power_state *) 2384 (mode_info->atom_context->bios + data_offset + 2385 le16_to_cpu(power_info->pplib.usStateArrayOffset) + 2386 i * power_info->pplib.ucStateEntrySize); 2387 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 2388 (mode_info->atom_context->bios + data_offset + 2389 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) + 2390 (power_state->v1.ucNonClockStateIndex * 2391 power_info->pplib.ucNonClockSize)); 2392 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) * 2393 ((power_info->pplib.ucStateEntrySize - 1) ? 2394 (power_info->pplib.ucStateEntrySize - 1) : 1), 2395 GFP_KERNEL); 2396 if (!rdev->pm.power_state[i].clock_info) 2397 return state_index; 2398 if (power_info->pplib.ucStateEntrySize - 1) { 2399 for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) { 2400 clock_info = (union pplib_clock_info *) 2401 (mode_info->atom_context->bios + data_offset + 2402 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) + 2403 (power_state->v1.ucClockStateIndices[j] * 2404 power_info->pplib.ucClockInfoSize)); 2405 valid = radeon_atombios_parse_pplib_clock_info(rdev, 2406 state_index, mode_index, 2407 clock_info); 2408 if (valid) 2409 mode_index++; 2410 } 2411 } else { 2412 rdev->pm.power_state[state_index].clock_info[0].mclk = 2413 rdev->clock.default_mclk; 2414 rdev->pm.power_state[state_index].clock_info[0].sclk = 2415 rdev->clock.default_sclk; 2416 mode_index++; 2417 } 2418 rdev->pm.power_state[state_index].num_clock_modes = mode_index; 2419 if (mode_index) { 2420 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index, 2421 non_clock_info); 2422 state_index++; 2423 } 2424 } 2425 /* if multiple clock modes, mark the lowest as no display */ 2426 for (i = 0; i < state_index; i++) { 2427 if (rdev->pm.power_state[i].num_clock_modes > 1) 2428 rdev->pm.power_state[i].clock_info[0].flags |= 2429 RADEON_PM_MODE_NO_DISPLAY; 2430 } 2431 /* first mode is usually default */ 2432 if (rdev->pm.default_power_state_index == -1) { 2433 rdev->pm.power_state[0].type = 2434 POWER_STATE_TYPE_DEFAULT; 2435 rdev->pm.default_power_state_index = 0; 2436 rdev->pm.power_state[0].default_clock_mode = 2437 &rdev->pm.power_state[0].clock_info[0]; 2438 } 2439 return state_index; 2440 } 2441 2442 static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev) 2443 { 2444 struct radeon_mode_info *mode_info = &rdev->mode_info; 2445 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 2446 union pplib_power_state *power_state; 2447 int i, j, non_clock_array_index, clock_array_index; 2448 int state_index = 0, mode_index = 0; 2449 union pplib_clock_info *clock_info; 2450 struct StateArray *state_array; 2451 struct ClockInfoArray *clock_info_array; 2452 struct NonClockInfoArray *non_clock_info_array; 2453 bool valid; 2454 union power_info *power_info; 2455 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 2456 u16 data_offset; 2457 u8 frev, crev; 2458 2459 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 2460 &frev, &crev, &data_offset)) 2461 return state_index; 2462 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 2463 2464 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController); 2465 state_array = (struct StateArray *) 2466 (mode_info->atom_context->bios + data_offset + 2467 le16_to_cpu(power_info->pplib.usStateArrayOffset)); 2468 clock_info_array = (struct ClockInfoArray *) 2469 (mode_info->atom_context->bios + data_offset + 2470 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); 2471 non_clock_info_array = (struct NonClockInfoArray *) 2472 (mode_info->atom_context->bios + data_offset + 2473 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); 2474 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * 2475 state_array->ucNumEntries, GFP_KERNEL); 2476 if (!rdev->pm.power_state) 2477 return state_index; 2478 for (i = 0; i < state_array->ucNumEntries; i++) { 2479 mode_index = 0; 2480 power_state = (union pplib_power_state *)&state_array->states[i]; 2481 /* XXX this might be an inagua bug... */ 2482 non_clock_array_index = i; /* power_state->v2.nonClockInfoIndex */ 2483 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 2484 &non_clock_info_array->nonClockInfo[non_clock_array_index]; 2485 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) * 2486 (power_state->v2.ucNumDPMLevels ? 2487 power_state->v2.ucNumDPMLevels : 1), 2488 GFP_KERNEL); 2489 if (!rdev->pm.power_state[i].clock_info) 2490 return state_index; 2491 if (power_state->v2.ucNumDPMLevels) { 2492 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { 2493 clock_array_index = power_state->v2.clockInfoIndex[j]; 2494 /* XXX this might be an inagua bug... */ 2495 if (clock_array_index >= clock_info_array->ucNumEntries) 2496 continue; 2497 clock_info = (union pplib_clock_info *) 2498 &clock_info_array->clockInfo[clock_array_index]; 2499 valid = radeon_atombios_parse_pplib_clock_info(rdev, 2500 state_index, mode_index, 2501 clock_info); 2502 if (valid) 2503 mode_index++; 2504 } 2505 } else { 2506 rdev->pm.power_state[state_index].clock_info[0].mclk = 2507 rdev->clock.default_mclk; 2508 rdev->pm.power_state[state_index].clock_info[0].sclk = 2509 rdev->clock.default_sclk; 2510 mode_index++; 2511 } 2512 rdev->pm.power_state[state_index].num_clock_modes = mode_index; 2513 if (mode_index) { 2514 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index, 2515 non_clock_info); 2516 state_index++; 2517 } 2518 } 2519 /* if multiple clock modes, mark the lowest as no display */ 2520 for (i = 0; i < state_index; i++) { 2521 if (rdev->pm.power_state[i].num_clock_modes > 1) 2522 rdev->pm.power_state[i].clock_info[0].flags |= 2523 RADEON_PM_MODE_NO_DISPLAY; 2524 } 2525 /* first mode is usually default */ 2526 if (rdev->pm.default_power_state_index == -1) { 2527 rdev->pm.power_state[0].type = 2528 POWER_STATE_TYPE_DEFAULT; 2529 rdev->pm.default_power_state_index = 0; 2530 rdev->pm.power_state[0].default_clock_mode = 2531 &rdev->pm.power_state[0].clock_info[0]; 2532 } 2533 return state_index; 2534 } 2535 2536 void radeon_atombios_get_power_modes(struct radeon_device *rdev) 2537 { 2538 struct radeon_mode_info *mode_info = &rdev->mode_info; 2539 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 2540 u16 data_offset; 2541 u8 frev, crev; 2542 int state_index = 0; 2543 2544 rdev->pm.default_power_state_index = -1; 2545 2546 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 2547 &frev, &crev, &data_offset)) { 2548 switch (frev) { 2549 case 1: 2550 case 2: 2551 case 3: 2552 state_index = radeon_atombios_parse_power_table_1_3(rdev); 2553 break; 2554 case 4: 2555 case 5: 2556 state_index = radeon_atombios_parse_power_table_4_5(rdev); 2557 break; 2558 case 6: 2559 state_index = radeon_atombios_parse_power_table_6(rdev); 2560 break; 2561 default: 2562 break; 2563 } 2564 } else { 2565 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL); 2566 if (rdev->pm.power_state) { 2567 rdev->pm.power_state[0].clock_info = 2568 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL); 2569 if (rdev->pm.power_state[0].clock_info) { 2570 /* add the default mode */ 2571 rdev->pm.power_state[state_index].type = 2572 POWER_STATE_TYPE_DEFAULT; 2573 rdev->pm.power_state[state_index].num_clock_modes = 1; 2574 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk; 2575 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk; 2576 rdev->pm.power_state[state_index].default_clock_mode = 2577 &rdev->pm.power_state[state_index].clock_info[0]; 2578 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; 2579 rdev->pm.power_state[state_index].pcie_lanes = 16; 2580 rdev->pm.default_power_state_index = state_index; 2581 rdev->pm.power_state[state_index].flags = 0; 2582 state_index++; 2583 } 2584 } 2585 } 2586 2587 rdev->pm.num_power_states = state_index; 2588 2589 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; 2590 rdev->pm.current_clock_mode_index = 0; 2591 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage; 2592 } 2593 2594 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable) 2595 { 2596 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args; 2597 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating); 2598 2599 args.ucEnable = enable; 2600 2601 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2602 } 2603 2604 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev) 2605 { 2606 GET_ENGINE_CLOCK_PS_ALLOCATION args; 2607 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock); 2608 2609 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2610 return le32_to_cpu(args.ulReturnEngineClock); 2611 } 2612 2613 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev) 2614 { 2615 GET_MEMORY_CLOCK_PS_ALLOCATION args; 2616 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock); 2617 2618 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2619 return le32_to_cpu(args.ulReturnMemoryClock); 2620 } 2621 2622 void radeon_atom_set_engine_clock(struct radeon_device *rdev, 2623 uint32_t eng_clock) 2624 { 2625 SET_ENGINE_CLOCK_PS_ALLOCATION args; 2626 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock); 2627 2628 args.ulTargetEngineClock = cpu_to_le32(eng_clock); /* 10 khz */ 2629 2630 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2631 } 2632 2633 void radeon_atom_set_memory_clock(struct radeon_device *rdev, 2634 uint32_t mem_clock) 2635 { 2636 SET_MEMORY_CLOCK_PS_ALLOCATION args; 2637 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock); 2638 2639 if (rdev->flags & RADEON_IS_IGP) 2640 return; 2641 2642 args.ulTargetMemoryClock = cpu_to_le32(mem_clock); /* 10 khz */ 2643 2644 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2645 } 2646 2647 union set_voltage { 2648 struct _SET_VOLTAGE_PS_ALLOCATION alloc; 2649 struct _SET_VOLTAGE_PARAMETERS v1; 2650 struct _SET_VOLTAGE_PARAMETERS_V2 v2; 2651 }; 2652 2653 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type) 2654 { 2655 union set_voltage args; 2656 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); 2657 u8 frev, crev, volt_index = voltage_level; 2658 2659 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 2660 return; 2661 2662 /* 0xff01 is a flag rather then an actual voltage */ 2663 if (voltage_level == 0xff01) 2664 return; 2665 2666 switch (crev) { 2667 case 1: 2668 args.v1.ucVoltageType = voltage_type; 2669 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE; 2670 args.v1.ucVoltageIndex = volt_index; 2671 break; 2672 case 2: 2673 args.v2.ucVoltageType = voltage_type; 2674 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE; 2675 args.v2.usVoltageLevel = cpu_to_le16(voltage_level); 2676 break; 2677 default: 2678 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 2679 return; 2680 } 2681 2682 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2683 } 2684 2685 int radeon_atom_get_max_vddc(struct radeon_device *rdev, 2686 u16 *voltage) 2687 { 2688 union set_voltage args; 2689 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); 2690 u8 frev, crev; 2691 2692 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 2693 return -EINVAL; 2694 2695 switch (crev) { 2696 case 1: 2697 return -EINVAL; 2698 case 2: 2699 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE; 2700 args.v2.ucVoltageMode = 0; 2701 args.v2.usVoltageLevel = 0; 2702 2703 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2704 2705 *voltage = le16_to_cpu(args.v2.usVoltageLevel); 2706 break; 2707 default: 2708 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 2709 return -EINVAL; 2710 } 2711 2712 return 0; 2713 } 2714 2715 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev) 2716 { 2717 struct radeon_device *rdev = dev->dev_private; 2718 uint32_t bios_2_scratch, bios_6_scratch; 2719 2720 if (rdev->family >= CHIP_R600) { 2721 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); 2722 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); 2723 } else { 2724 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); 2725 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 2726 } 2727 2728 /* let the bios control the backlight */ 2729 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE; 2730 2731 /* tell the bios not to handle mode switching */ 2732 bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH; 2733 2734 if (rdev->family >= CHIP_R600) { 2735 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); 2736 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); 2737 } else { 2738 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); 2739 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 2740 } 2741 2742 } 2743 2744 void radeon_save_bios_scratch_regs(struct radeon_device *rdev) 2745 { 2746 uint32_t scratch_reg; 2747 int i; 2748 2749 if (rdev->family >= CHIP_R600) 2750 scratch_reg = R600_BIOS_0_SCRATCH; 2751 else 2752 scratch_reg = RADEON_BIOS_0_SCRATCH; 2753 2754 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++) 2755 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4)); 2756 } 2757 2758 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev) 2759 { 2760 uint32_t scratch_reg; 2761 int i; 2762 2763 if (rdev->family >= CHIP_R600) 2764 scratch_reg = R600_BIOS_0_SCRATCH; 2765 else 2766 scratch_reg = RADEON_BIOS_0_SCRATCH; 2767 2768 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++) 2769 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]); 2770 } 2771 2772 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock) 2773 { 2774 struct drm_device *dev = encoder->dev; 2775 struct radeon_device *rdev = dev->dev_private; 2776 uint32_t bios_6_scratch; 2777 2778 if (rdev->family >= CHIP_R600) 2779 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); 2780 else 2781 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 2782 2783 if (lock) { 2784 bios_6_scratch |= ATOM_S6_CRITICAL_STATE; 2785 bios_6_scratch &= ~ATOM_S6_ACC_MODE; 2786 } else { 2787 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE; 2788 bios_6_scratch |= ATOM_S6_ACC_MODE; 2789 } 2790 2791 if (rdev->family >= CHIP_R600) 2792 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); 2793 else 2794 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 2795 } 2796 2797 /* at some point we may want to break this out into individual functions */ 2798 void 2799 radeon_atombios_connected_scratch_regs(struct drm_connector *connector, 2800 struct drm_encoder *encoder, 2801 bool connected) 2802 { 2803 struct drm_device *dev = connector->dev; 2804 struct radeon_device *rdev = dev->dev_private; 2805 struct radeon_connector *radeon_connector = 2806 to_radeon_connector(connector); 2807 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2808 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch; 2809 2810 if (rdev->family >= CHIP_R600) { 2811 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); 2812 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH); 2813 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); 2814 } else { 2815 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); 2816 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH); 2817 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 2818 } 2819 2820 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) && 2821 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) { 2822 if (connected) { 2823 DRM_DEBUG_KMS("TV1 connected\n"); 2824 bios_3_scratch |= ATOM_S3_TV1_ACTIVE; 2825 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1; 2826 } else { 2827 DRM_DEBUG_KMS("TV1 disconnected\n"); 2828 bios_0_scratch &= ~ATOM_S0_TV1_MASK; 2829 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE; 2830 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1; 2831 } 2832 } 2833 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) && 2834 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) { 2835 if (connected) { 2836 DRM_DEBUG_KMS("CV connected\n"); 2837 bios_3_scratch |= ATOM_S3_CV_ACTIVE; 2838 bios_6_scratch |= ATOM_S6_ACC_REQ_CV; 2839 } else { 2840 DRM_DEBUG_KMS("CV disconnected\n"); 2841 bios_0_scratch &= ~ATOM_S0_CV_MASK; 2842 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE; 2843 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV; 2844 } 2845 } 2846 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) && 2847 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) { 2848 if (connected) { 2849 DRM_DEBUG_KMS("LCD1 connected\n"); 2850 bios_0_scratch |= ATOM_S0_LCD1; 2851 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE; 2852 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1; 2853 } else { 2854 DRM_DEBUG_KMS("LCD1 disconnected\n"); 2855 bios_0_scratch &= ~ATOM_S0_LCD1; 2856 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE; 2857 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1; 2858 } 2859 } 2860 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) && 2861 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) { 2862 if (connected) { 2863 DRM_DEBUG_KMS("CRT1 connected\n"); 2864 bios_0_scratch |= ATOM_S0_CRT1_COLOR; 2865 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE; 2866 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1; 2867 } else { 2868 DRM_DEBUG_KMS("CRT1 disconnected\n"); 2869 bios_0_scratch &= ~ATOM_S0_CRT1_MASK; 2870 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE; 2871 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1; 2872 } 2873 } 2874 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) && 2875 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) { 2876 if (connected) { 2877 DRM_DEBUG_KMS("CRT2 connected\n"); 2878 bios_0_scratch |= ATOM_S0_CRT2_COLOR; 2879 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE; 2880 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2; 2881 } else { 2882 DRM_DEBUG_KMS("CRT2 disconnected\n"); 2883 bios_0_scratch &= ~ATOM_S0_CRT2_MASK; 2884 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE; 2885 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2; 2886 } 2887 } 2888 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) && 2889 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) { 2890 if (connected) { 2891 DRM_DEBUG_KMS("DFP1 connected\n"); 2892 bios_0_scratch |= ATOM_S0_DFP1; 2893 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE; 2894 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1; 2895 } else { 2896 DRM_DEBUG_KMS("DFP1 disconnected\n"); 2897 bios_0_scratch &= ~ATOM_S0_DFP1; 2898 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE; 2899 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1; 2900 } 2901 } 2902 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) && 2903 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) { 2904 if (connected) { 2905 DRM_DEBUG_KMS("DFP2 connected\n"); 2906 bios_0_scratch |= ATOM_S0_DFP2; 2907 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE; 2908 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2; 2909 } else { 2910 DRM_DEBUG_KMS("DFP2 disconnected\n"); 2911 bios_0_scratch &= ~ATOM_S0_DFP2; 2912 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE; 2913 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2; 2914 } 2915 } 2916 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) && 2917 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) { 2918 if (connected) { 2919 DRM_DEBUG_KMS("DFP3 connected\n"); 2920 bios_0_scratch |= ATOM_S0_DFP3; 2921 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE; 2922 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3; 2923 } else { 2924 DRM_DEBUG_KMS("DFP3 disconnected\n"); 2925 bios_0_scratch &= ~ATOM_S0_DFP3; 2926 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE; 2927 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3; 2928 } 2929 } 2930 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) && 2931 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) { 2932 if (connected) { 2933 DRM_DEBUG_KMS("DFP4 connected\n"); 2934 bios_0_scratch |= ATOM_S0_DFP4; 2935 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE; 2936 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4; 2937 } else { 2938 DRM_DEBUG_KMS("DFP4 disconnected\n"); 2939 bios_0_scratch &= ~ATOM_S0_DFP4; 2940 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE; 2941 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4; 2942 } 2943 } 2944 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) && 2945 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) { 2946 if (connected) { 2947 DRM_DEBUG_KMS("DFP5 connected\n"); 2948 bios_0_scratch |= ATOM_S0_DFP5; 2949 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE; 2950 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5; 2951 } else { 2952 DRM_DEBUG_KMS("DFP5 disconnected\n"); 2953 bios_0_scratch &= ~ATOM_S0_DFP5; 2954 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE; 2955 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5; 2956 } 2957 } 2958 2959 if (rdev->family >= CHIP_R600) { 2960 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch); 2961 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch); 2962 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); 2963 } else { 2964 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch); 2965 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch); 2966 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 2967 } 2968 } 2969 2970 void 2971 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc) 2972 { 2973 struct drm_device *dev = encoder->dev; 2974 struct radeon_device *rdev = dev->dev_private; 2975 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2976 uint32_t bios_3_scratch; 2977 2978 if (rdev->family >= CHIP_R600) 2979 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH); 2980 else 2981 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH); 2982 2983 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { 2984 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE; 2985 bios_3_scratch |= (crtc << 18); 2986 } 2987 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) { 2988 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE; 2989 bios_3_scratch |= (crtc << 24); 2990 } 2991 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { 2992 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE; 2993 bios_3_scratch |= (crtc << 16); 2994 } 2995 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { 2996 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE; 2997 bios_3_scratch |= (crtc << 20); 2998 } 2999 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { 3000 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE; 3001 bios_3_scratch |= (crtc << 17); 3002 } 3003 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) { 3004 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE; 3005 bios_3_scratch |= (crtc << 19); 3006 } 3007 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) { 3008 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE; 3009 bios_3_scratch |= (crtc << 23); 3010 } 3011 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) { 3012 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE; 3013 bios_3_scratch |= (crtc << 25); 3014 } 3015 3016 if (rdev->family >= CHIP_R600) 3017 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch); 3018 else 3019 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch); 3020 } 3021 3022 void 3023 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on) 3024 { 3025 struct drm_device *dev = encoder->dev; 3026 struct radeon_device *rdev = dev->dev_private; 3027 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 3028 uint32_t bios_2_scratch; 3029 3030 if (rdev->family >= CHIP_R600) 3031 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); 3032 else 3033 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); 3034 3035 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { 3036 if (on) 3037 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE; 3038 else 3039 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE; 3040 } 3041 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) { 3042 if (on) 3043 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE; 3044 else 3045 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE; 3046 } 3047 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { 3048 if (on) 3049 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE; 3050 else 3051 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE; 3052 } 3053 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { 3054 if (on) 3055 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE; 3056 else 3057 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE; 3058 } 3059 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { 3060 if (on) 3061 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE; 3062 else 3063 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE; 3064 } 3065 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) { 3066 if (on) 3067 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE; 3068 else 3069 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE; 3070 } 3071 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) { 3072 if (on) 3073 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE; 3074 else 3075 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE; 3076 } 3077 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) { 3078 if (on) 3079 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE; 3080 else 3081 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE; 3082 } 3083 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) { 3084 if (on) 3085 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE; 3086 else 3087 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE; 3088 } 3089 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) { 3090 if (on) 3091 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE; 3092 else 3093 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE; 3094 } 3095 3096 if (rdev->family >= CHIP_R600) 3097 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); 3098 else 3099 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); 3100 } 3101