1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 27 #include <linux/pci.h> 28 29 #include <drm/drm_device.h> 30 #include <drm/radeon_drm.h> 31 32 #include "radeon.h" 33 34 #include "atom.h" 35 #include "atom-bits.h" 36 #include "radeon_asic.h" 37 #include "radeon_atombios.h" 38 #include "radeon_legacy_encoders.h" 39 40 union atom_supported_devices { 41 struct _ATOM_SUPPORTED_DEVICES_INFO info; 42 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2; 43 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1; 44 }; 45 46 static void radeon_lookup_i2c_gpio_quirks(struct radeon_device *rdev, 47 ATOM_GPIO_I2C_ASSIGMENT *gpio, 48 u8 index) 49 { 50 /* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */ 51 if ((rdev->family == CHIP_R420) || 52 (rdev->family == CHIP_R423) || 53 (rdev->family == CHIP_RV410)) { 54 if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) || 55 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) || 56 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) { 57 gpio->ucClkMaskShift = 0x19; 58 gpio->ucDataMaskShift = 0x18; 59 } 60 } 61 62 /* some evergreen boards have bad data for this entry */ 63 if (ASIC_IS_DCE4(rdev)) { 64 if ((index == 7) && 65 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) && 66 (gpio->sucI2cId.ucAccess == 0)) { 67 gpio->sucI2cId.ucAccess = 0x97; 68 gpio->ucDataMaskShift = 8; 69 gpio->ucDataEnShift = 8; 70 gpio->ucDataY_Shift = 8; 71 gpio->ucDataA_Shift = 8; 72 } 73 } 74 75 /* some DCE3 boards have bad data for this entry */ 76 if (ASIC_IS_DCE3(rdev)) { 77 if ((index == 4) && 78 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) && 79 (gpio->sucI2cId.ucAccess == 0x94)) 80 gpio->sucI2cId.ucAccess = 0x14; 81 } 82 } 83 84 static struct radeon_i2c_bus_rec radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio) 85 { 86 struct radeon_i2c_bus_rec i2c; 87 88 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec)); 89 90 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4; 91 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4; 92 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4; 93 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4; 94 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4; 95 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4; 96 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4; 97 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4; 98 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift); 99 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift); 100 i2c.en_clk_mask = (1 << gpio->ucClkEnShift); 101 i2c.en_data_mask = (1 << gpio->ucDataEnShift); 102 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift); 103 i2c.y_data_mask = (1 << gpio->ucDataY_Shift); 104 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift); 105 i2c.a_data_mask = (1 << gpio->ucDataA_Shift); 106 107 if (gpio->sucI2cId.sbfAccess.bfHW_Capable) 108 i2c.hw_capable = true; 109 else 110 i2c.hw_capable = false; 111 112 if (gpio->sucI2cId.ucAccess == 0xa0) 113 i2c.mm_i2c = true; 114 else 115 i2c.mm_i2c = false; 116 117 i2c.i2c_id = gpio->sucI2cId.ucAccess; 118 119 if (i2c.mask_clk_reg) 120 i2c.valid = true; 121 else 122 i2c.valid = false; 123 124 return i2c; 125 } 126 127 static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev, 128 uint8_t id) 129 { 130 struct atom_context *ctx = rdev->mode_info.atom_context; 131 ATOM_GPIO_I2C_ASSIGMENT *gpio; 132 struct radeon_i2c_bus_rec i2c; 133 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info); 134 struct _ATOM_GPIO_I2C_INFO *i2c_info; 135 uint16_t data_offset, size; 136 int i, num_indices; 137 138 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec)); 139 i2c.valid = false; 140 141 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { 142 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset); 143 144 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 145 sizeof(ATOM_GPIO_I2C_ASSIGMENT); 146 147 gpio = &i2c_info->asGPIO_Info[0]; 148 for (i = 0; i < num_indices; i++) { 149 150 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i); 151 152 if (gpio->sucI2cId.ucAccess == id) { 153 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio); 154 break; 155 } 156 gpio = (ATOM_GPIO_I2C_ASSIGMENT *) 157 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT)); 158 } 159 } 160 161 return i2c; 162 } 163 164 void radeon_atombios_i2c_init(struct radeon_device *rdev) 165 { 166 struct atom_context *ctx = rdev->mode_info.atom_context; 167 ATOM_GPIO_I2C_ASSIGMENT *gpio; 168 struct radeon_i2c_bus_rec i2c; 169 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info); 170 struct _ATOM_GPIO_I2C_INFO *i2c_info; 171 uint16_t data_offset, size; 172 int i, num_indices; 173 char stmp[32]; 174 175 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { 176 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset); 177 178 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 179 sizeof(ATOM_GPIO_I2C_ASSIGMENT); 180 181 gpio = &i2c_info->asGPIO_Info[0]; 182 for (i = 0; i < num_indices; i++) { 183 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i); 184 185 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio); 186 187 if (i2c.valid) { 188 sprintf(stmp, "0x%x", i2c.i2c_id); 189 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp); 190 } 191 gpio = (ATOM_GPIO_I2C_ASSIGMENT *) 192 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT)); 193 } 194 } 195 } 196 197 struct radeon_gpio_rec radeon_atombios_lookup_gpio(struct radeon_device *rdev, 198 u8 id) 199 { 200 struct atom_context *ctx = rdev->mode_info.atom_context; 201 struct radeon_gpio_rec gpio; 202 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT); 203 struct _ATOM_GPIO_PIN_LUT *gpio_info; 204 ATOM_GPIO_PIN_ASSIGNMENT *pin; 205 u16 data_offset, size; 206 int i, num_indices; 207 208 memset(&gpio, 0, sizeof(struct radeon_gpio_rec)); 209 gpio.valid = false; 210 211 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { 212 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset); 213 214 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 215 sizeof(ATOM_GPIO_PIN_ASSIGNMENT); 216 217 pin = gpio_info->asGPIO_Pin; 218 for (i = 0; i < num_indices; i++) { 219 if (id == pin->ucGPIO_ID) { 220 gpio.id = pin->ucGPIO_ID; 221 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4; 222 gpio.shift = pin->ucGpioPinBitShift; 223 gpio.mask = (1 << pin->ucGpioPinBitShift); 224 gpio.valid = true; 225 break; 226 } 227 pin = (ATOM_GPIO_PIN_ASSIGNMENT *) 228 ((u8 *)pin + sizeof(ATOM_GPIO_PIN_ASSIGNMENT)); 229 } 230 } 231 232 return gpio; 233 } 234 235 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev, 236 struct radeon_gpio_rec *gpio) 237 { 238 struct radeon_hpd hpd; 239 u32 reg; 240 241 memset(&hpd, 0, sizeof(struct radeon_hpd)); 242 243 if (ASIC_IS_DCE6(rdev)) 244 reg = SI_DC_GPIO_HPD_A; 245 else if (ASIC_IS_DCE4(rdev)) 246 reg = EVERGREEN_DC_GPIO_HPD_A; 247 else 248 reg = AVIVO_DC_GPIO_HPD_A; 249 250 hpd.gpio = *gpio; 251 if (gpio->reg == reg) { 252 switch(gpio->mask) { 253 case (1 << 0): 254 hpd.hpd = RADEON_HPD_1; 255 break; 256 case (1 << 8): 257 hpd.hpd = RADEON_HPD_2; 258 break; 259 case (1 << 16): 260 hpd.hpd = RADEON_HPD_3; 261 break; 262 case (1 << 24): 263 hpd.hpd = RADEON_HPD_4; 264 break; 265 case (1 << 26): 266 hpd.hpd = RADEON_HPD_5; 267 break; 268 case (1 << 28): 269 hpd.hpd = RADEON_HPD_6; 270 break; 271 default: 272 hpd.hpd = RADEON_HPD_NONE; 273 break; 274 } 275 } else 276 hpd.hpd = RADEON_HPD_NONE; 277 return hpd; 278 } 279 280 static bool radeon_atom_apply_quirks(struct drm_device *dev, 281 uint32_t supported_device, 282 int *connector_type, 283 struct radeon_i2c_bus_rec *i2c_bus, 284 uint16_t *line_mux, 285 struct radeon_hpd *hpd) 286 { 287 288 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */ 289 if ((dev->pdev->device == 0x791e) && 290 (dev->pdev->subsystem_vendor == 0x1043) && 291 (dev->pdev->subsystem_device == 0x826d)) { 292 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) && 293 (supported_device == ATOM_DEVICE_DFP3_SUPPORT)) 294 *connector_type = DRM_MODE_CONNECTOR_DVID; 295 } 296 297 /* Asrock RS600 board lists the DVI port as HDMI */ 298 if ((dev->pdev->device == 0x7941) && 299 (dev->pdev->subsystem_vendor == 0x1849) && 300 (dev->pdev->subsystem_device == 0x7941)) { 301 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) && 302 (supported_device == ATOM_DEVICE_DFP3_SUPPORT)) 303 *connector_type = DRM_MODE_CONNECTOR_DVID; 304 } 305 306 /* MSI K9A2GM V2/V3 board has no HDMI or DVI */ 307 if ((dev->pdev->device == 0x796e) && 308 (dev->pdev->subsystem_vendor == 0x1462) && 309 (dev->pdev->subsystem_device == 0x7302)) { 310 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) || 311 (supported_device == ATOM_DEVICE_DFP3_SUPPORT)) 312 return false; 313 } 314 315 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */ 316 if ((dev->pdev->device == 0x7941) && 317 (dev->pdev->subsystem_vendor == 0x147b) && 318 (dev->pdev->subsystem_device == 0x2412)) { 319 if (*connector_type == DRM_MODE_CONNECTOR_DVII) 320 return false; 321 } 322 323 /* Falcon NW laptop lists vga ddc line for LVDS */ 324 if ((dev->pdev->device == 0x5653) && 325 (dev->pdev->subsystem_vendor == 0x1462) && 326 (dev->pdev->subsystem_device == 0x0291)) { 327 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) { 328 i2c_bus->valid = false; 329 *line_mux = 53; 330 } 331 } 332 333 /* HIS X1300 is DVI+VGA, not DVI+DVI */ 334 if ((dev->pdev->device == 0x7146) && 335 (dev->pdev->subsystem_vendor == 0x17af) && 336 (dev->pdev->subsystem_device == 0x2058)) { 337 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT) 338 return false; 339 } 340 341 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */ 342 if ((dev->pdev->device == 0x7142) && 343 (dev->pdev->subsystem_vendor == 0x1458) && 344 (dev->pdev->subsystem_device == 0x2134)) { 345 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT) 346 return false; 347 } 348 349 350 /* Funky macbooks */ 351 if ((dev->pdev->device == 0x71C5) && 352 (dev->pdev->subsystem_vendor == 0x106b) && 353 (dev->pdev->subsystem_device == 0x0080)) { 354 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) || 355 (supported_device == ATOM_DEVICE_DFP2_SUPPORT)) 356 return false; 357 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT) 358 *line_mux = 0x90; 359 } 360 361 /* mac rv630, rv730, others */ 362 if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) && 363 (*connector_type == DRM_MODE_CONNECTOR_DVII)) { 364 *connector_type = DRM_MODE_CONNECTOR_9PinDIN; 365 *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1; 366 } 367 368 /* ASUS HD 3600 XT board lists the DVI port as HDMI */ 369 if ((dev->pdev->device == 0x9598) && 370 (dev->pdev->subsystem_vendor == 0x1043) && 371 (dev->pdev->subsystem_device == 0x01da)) { 372 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { 373 *connector_type = DRM_MODE_CONNECTOR_DVII; 374 } 375 } 376 377 /* ASUS HD 3600 board lists the DVI port as HDMI */ 378 if ((dev->pdev->device == 0x9598) && 379 (dev->pdev->subsystem_vendor == 0x1043) && 380 (dev->pdev->subsystem_device == 0x01e4)) { 381 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { 382 *connector_type = DRM_MODE_CONNECTOR_DVII; 383 } 384 } 385 386 /* ASUS HD 3450 board lists the DVI port as HDMI */ 387 if ((dev->pdev->device == 0x95C5) && 388 (dev->pdev->subsystem_vendor == 0x1043) && 389 (dev->pdev->subsystem_device == 0x01e2)) { 390 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { 391 *connector_type = DRM_MODE_CONNECTOR_DVII; 392 } 393 } 394 395 /* some BIOSes seem to report DAC on HDMI - usually this is a board with 396 * HDMI + VGA reporting as HDMI 397 */ 398 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { 399 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) { 400 *connector_type = DRM_MODE_CONNECTOR_VGA; 401 *line_mux = 0; 402 } 403 } 404 405 /* Acer laptop (Acer TravelMate 5730/5730G) has an HDMI port 406 * on the laptop and a DVI port on the docking station and 407 * both share the same encoder, hpd pin, and ddc line. 408 * So while the bios table is technically correct, 409 * we drop the DVI port here since xrandr has no concept of 410 * encoders and will try and drive both connectors 411 * with different crtcs which isn't possible on the hardware 412 * side and leaves no crtcs for LVDS or VGA. 413 */ 414 if (((dev->pdev->device == 0x95c4) || (dev->pdev->device == 0x9591)) && 415 (dev->pdev->subsystem_vendor == 0x1025) && 416 (dev->pdev->subsystem_device == 0x013c)) { 417 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) && 418 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) { 419 /* actually it's a DVI-D port not DVI-I */ 420 *connector_type = DRM_MODE_CONNECTOR_DVID; 421 return false; 422 } 423 } 424 425 /* XFX Pine Group device rv730 reports no VGA DDC lines 426 * even though they are wired up to record 0x93 427 */ 428 if ((dev->pdev->device == 0x9498) && 429 (dev->pdev->subsystem_vendor == 0x1682) && 430 (dev->pdev->subsystem_device == 0x2452) && 431 (i2c_bus->valid == false) && 432 !(supported_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))) { 433 struct radeon_device *rdev = dev->dev_private; 434 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93); 435 } 436 437 /* Fujitsu D3003-S2 board lists DVI-I as DVI-D and VGA */ 438 if (((dev->pdev->device == 0x9802) || 439 (dev->pdev->device == 0x9805) || 440 (dev->pdev->device == 0x9806)) && 441 (dev->pdev->subsystem_vendor == 0x1734) && 442 (dev->pdev->subsystem_device == 0x11bd)) { 443 if (*connector_type == DRM_MODE_CONNECTOR_VGA) { 444 *connector_type = DRM_MODE_CONNECTOR_DVII; 445 *line_mux = 0x3103; 446 } else if (*connector_type == DRM_MODE_CONNECTOR_DVID) { 447 *connector_type = DRM_MODE_CONNECTOR_DVII; 448 } 449 } 450 451 return true; 452 } 453 454 static const int supported_devices_connector_convert[] = { 455 DRM_MODE_CONNECTOR_Unknown, 456 DRM_MODE_CONNECTOR_VGA, 457 DRM_MODE_CONNECTOR_DVII, 458 DRM_MODE_CONNECTOR_DVID, 459 DRM_MODE_CONNECTOR_DVIA, 460 DRM_MODE_CONNECTOR_SVIDEO, 461 DRM_MODE_CONNECTOR_Composite, 462 DRM_MODE_CONNECTOR_LVDS, 463 DRM_MODE_CONNECTOR_Unknown, 464 DRM_MODE_CONNECTOR_Unknown, 465 DRM_MODE_CONNECTOR_HDMIA, 466 DRM_MODE_CONNECTOR_HDMIB, 467 DRM_MODE_CONNECTOR_Unknown, 468 DRM_MODE_CONNECTOR_Unknown, 469 DRM_MODE_CONNECTOR_9PinDIN, 470 DRM_MODE_CONNECTOR_DisplayPort 471 }; 472 473 static const uint16_t supported_devices_connector_object_id_convert[] = { 474 CONNECTOR_OBJECT_ID_NONE, 475 CONNECTOR_OBJECT_ID_VGA, 476 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */ 477 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */ 478 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */ 479 CONNECTOR_OBJECT_ID_COMPOSITE, 480 CONNECTOR_OBJECT_ID_SVIDEO, 481 CONNECTOR_OBJECT_ID_LVDS, 482 CONNECTOR_OBJECT_ID_9PIN_DIN, 483 CONNECTOR_OBJECT_ID_9PIN_DIN, 484 CONNECTOR_OBJECT_ID_DISPLAYPORT, 485 CONNECTOR_OBJECT_ID_HDMI_TYPE_A, 486 CONNECTOR_OBJECT_ID_HDMI_TYPE_B, 487 CONNECTOR_OBJECT_ID_SVIDEO 488 }; 489 490 static const int object_connector_convert[] = { 491 DRM_MODE_CONNECTOR_Unknown, 492 DRM_MODE_CONNECTOR_DVII, 493 DRM_MODE_CONNECTOR_DVII, 494 DRM_MODE_CONNECTOR_DVID, 495 DRM_MODE_CONNECTOR_DVID, 496 DRM_MODE_CONNECTOR_VGA, 497 DRM_MODE_CONNECTOR_Composite, 498 DRM_MODE_CONNECTOR_SVIDEO, 499 DRM_MODE_CONNECTOR_Unknown, 500 DRM_MODE_CONNECTOR_Unknown, 501 DRM_MODE_CONNECTOR_9PinDIN, 502 DRM_MODE_CONNECTOR_Unknown, 503 DRM_MODE_CONNECTOR_HDMIA, 504 DRM_MODE_CONNECTOR_HDMIB, 505 DRM_MODE_CONNECTOR_LVDS, 506 DRM_MODE_CONNECTOR_9PinDIN, 507 DRM_MODE_CONNECTOR_Unknown, 508 DRM_MODE_CONNECTOR_Unknown, 509 DRM_MODE_CONNECTOR_Unknown, 510 DRM_MODE_CONNECTOR_DisplayPort, 511 DRM_MODE_CONNECTOR_eDP, 512 DRM_MODE_CONNECTOR_Unknown 513 }; 514 515 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev) 516 { 517 struct radeon_device *rdev = dev->dev_private; 518 struct radeon_mode_info *mode_info = &rdev->mode_info; 519 struct atom_context *ctx = mode_info->atom_context; 520 int index = GetIndexIntoMasterTable(DATA, Object_Header); 521 u16 size, data_offset; 522 u8 frev, crev; 523 ATOM_CONNECTOR_OBJECT_TABLE *con_obj; 524 ATOM_ENCODER_OBJECT_TABLE *enc_obj; 525 ATOM_OBJECT_TABLE *router_obj; 526 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj; 527 ATOM_OBJECT_HEADER *obj_header; 528 int i, j, k, path_size, device_support; 529 int connector_type; 530 u16 igp_lane_info, conn_id, connector_object_id; 531 struct radeon_i2c_bus_rec ddc_bus; 532 struct radeon_router router; 533 struct radeon_gpio_rec gpio; 534 struct radeon_hpd hpd; 535 536 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) 537 return false; 538 539 if (crev < 2) 540 return false; 541 542 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset); 543 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *) 544 (ctx->bios + data_offset + 545 le16_to_cpu(obj_header->usDisplayPathTableOffset)); 546 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *) 547 (ctx->bios + data_offset + 548 le16_to_cpu(obj_header->usConnectorObjectTableOffset)); 549 enc_obj = (ATOM_ENCODER_OBJECT_TABLE *) 550 (ctx->bios + data_offset + 551 le16_to_cpu(obj_header->usEncoderObjectTableOffset)); 552 router_obj = (ATOM_OBJECT_TABLE *) 553 (ctx->bios + data_offset + 554 le16_to_cpu(obj_header->usRouterObjectTableOffset)); 555 device_support = le16_to_cpu(obj_header->usDeviceSupport); 556 557 path_size = 0; 558 for (i = 0; i < path_obj->ucNumOfDispPath; i++) { 559 uint8_t *addr = (uint8_t *) path_obj->asDispPath; 560 ATOM_DISPLAY_OBJECT_PATH *path; 561 addr += path_size; 562 path = (ATOM_DISPLAY_OBJECT_PATH *) addr; 563 path_size += le16_to_cpu(path->usSize); 564 565 if (device_support & le16_to_cpu(path->usDeviceTag)) { 566 uint8_t con_obj_id, con_obj_num; 567 568 con_obj_id = 569 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK) 570 >> OBJECT_ID_SHIFT; 571 con_obj_num = 572 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK) 573 >> ENUM_ID_SHIFT; 574 575 /* TODO CV support */ 576 if (le16_to_cpu(path->usDeviceTag) == 577 ATOM_DEVICE_CV_SUPPORT) 578 continue; 579 580 /* IGP chips */ 581 if ((rdev->flags & RADEON_IS_IGP) && 582 (con_obj_id == 583 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) { 584 uint16_t igp_offset = 0; 585 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj; 586 587 index = 588 GetIndexIntoMasterTable(DATA, 589 IntegratedSystemInfo); 590 591 if (atom_parse_data_header(ctx, index, &size, &frev, 592 &crev, &igp_offset)) { 593 594 if (crev >= 2) { 595 igp_obj = 596 (ATOM_INTEGRATED_SYSTEM_INFO_V2 597 *) (ctx->bios + igp_offset); 598 599 if (igp_obj) { 600 uint32_t slot_config, ct; 601 602 if (con_obj_num == 1) 603 slot_config = 604 igp_obj-> 605 ulDDISlot1Config; 606 else 607 slot_config = 608 igp_obj-> 609 ulDDISlot2Config; 610 611 ct = (slot_config >> 16) & 0xff; 612 connector_type = 613 object_connector_convert 614 [ct]; 615 connector_object_id = ct; 616 igp_lane_info = 617 slot_config & 0xffff; 618 } else 619 continue; 620 } else 621 continue; 622 } else { 623 igp_lane_info = 0; 624 connector_type = 625 object_connector_convert[con_obj_id]; 626 connector_object_id = con_obj_id; 627 } 628 } else { 629 igp_lane_info = 0; 630 connector_type = 631 object_connector_convert[con_obj_id]; 632 connector_object_id = con_obj_id; 633 } 634 635 if (connector_type == DRM_MODE_CONNECTOR_Unknown) 636 continue; 637 638 router.ddc_valid = false; 639 router.cd_valid = false; 640 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) { 641 uint8_t grph_obj_type = 642 (le16_to_cpu(path->usGraphicObjIds[j]) & 643 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; 644 645 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) { 646 for (k = 0; k < enc_obj->ucNumberOfObjects; k++) { 647 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID); 648 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) { 649 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *) 650 (ctx->bios + data_offset + 651 le16_to_cpu(enc_obj->asObjects[k].usRecordOffset)); 652 ATOM_ENCODER_CAP_RECORD *cap_record; 653 u16 caps = 0; 654 655 while (record->ucRecordSize > 0 && 656 record->ucRecordType > 0 && 657 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { 658 switch (record->ucRecordType) { 659 case ATOM_ENCODER_CAP_RECORD_TYPE: 660 cap_record =(ATOM_ENCODER_CAP_RECORD *) 661 record; 662 caps = le16_to_cpu(cap_record->usEncoderCap); 663 break; 664 } 665 record = (ATOM_COMMON_RECORD_HEADER *) 666 ((char *)record + record->ucRecordSize); 667 } 668 radeon_add_atom_encoder(dev, 669 encoder_obj, 670 le16_to_cpu 671 (path-> 672 usDeviceTag), 673 caps); 674 } 675 } 676 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) { 677 for (k = 0; k < router_obj->ucNumberOfObjects; k++) { 678 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID); 679 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) { 680 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *) 681 (ctx->bios + data_offset + 682 le16_to_cpu(router_obj->asObjects[k].usRecordOffset)); 683 ATOM_I2C_RECORD *i2c_record; 684 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config; 685 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path; 686 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path; 687 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table = 688 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *) 689 (ctx->bios + data_offset + 690 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset)); 691 u8 *num_dst_objs = (u8 *) 692 ((u8 *)router_src_dst_table + 1 + 693 (router_src_dst_table->ucNumberOfSrc * 2)); 694 u16 *dst_objs = (u16 *)(num_dst_objs + 1); 695 int enum_id; 696 697 router.router_id = router_obj_id; 698 for (enum_id = 0; enum_id < (*num_dst_objs); enum_id++) { 699 if (le16_to_cpu(path->usConnObjectId) == 700 le16_to_cpu(dst_objs[enum_id])) 701 break; 702 } 703 704 while (record->ucRecordSize > 0 && 705 record->ucRecordType > 0 && 706 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { 707 switch (record->ucRecordType) { 708 case ATOM_I2C_RECORD_TYPE: 709 i2c_record = 710 (ATOM_I2C_RECORD *) 711 record; 712 i2c_config = 713 (ATOM_I2C_ID_CONFIG_ACCESS *) 714 &i2c_record->sucI2cId; 715 router.i2c_info = 716 radeon_lookup_i2c_gpio(rdev, 717 i2c_config-> 718 ucAccess); 719 router.i2c_addr = i2c_record->ucI2CAddr >> 1; 720 break; 721 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE: 722 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *) 723 record; 724 router.ddc_valid = true; 725 router.ddc_mux_type = ddc_path->ucMuxType; 726 router.ddc_mux_control_pin = ddc_path->ucMuxControlPin; 727 router.ddc_mux_state = ddc_path->ucMuxState[enum_id]; 728 break; 729 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE: 730 cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *) 731 record; 732 router.cd_valid = true; 733 router.cd_mux_type = cd_path->ucMuxType; 734 router.cd_mux_control_pin = cd_path->ucMuxControlPin; 735 router.cd_mux_state = cd_path->ucMuxState[enum_id]; 736 break; 737 } 738 record = (ATOM_COMMON_RECORD_HEADER *) 739 ((char *)record + record->ucRecordSize); 740 } 741 } 742 } 743 } 744 } 745 746 /* look up gpio for ddc, hpd */ 747 ddc_bus.valid = false; 748 hpd.hpd = RADEON_HPD_NONE; 749 if ((le16_to_cpu(path->usDeviceTag) & 750 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) { 751 for (j = 0; j < con_obj->ucNumberOfObjects; j++) { 752 if (le16_to_cpu(path->usConnObjectId) == 753 le16_to_cpu(con_obj->asObjects[j]. 754 usObjectID)) { 755 ATOM_COMMON_RECORD_HEADER 756 *record = 757 (ATOM_COMMON_RECORD_HEADER 758 *) 759 (ctx->bios + data_offset + 760 le16_to_cpu(con_obj-> 761 asObjects[j]. 762 usRecordOffset)); 763 ATOM_I2C_RECORD *i2c_record; 764 ATOM_HPD_INT_RECORD *hpd_record; 765 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config; 766 767 while (record->ucRecordSize > 0 && 768 record->ucRecordType > 0 && 769 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { 770 switch (record->ucRecordType) { 771 case ATOM_I2C_RECORD_TYPE: 772 i2c_record = 773 (ATOM_I2C_RECORD *) 774 record; 775 i2c_config = 776 (ATOM_I2C_ID_CONFIG_ACCESS *) 777 &i2c_record->sucI2cId; 778 ddc_bus = radeon_lookup_i2c_gpio(rdev, 779 i2c_config-> 780 ucAccess); 781 break; 782 case ATOM_HPD_INT_RECORD_TYPE: 783 hpd_record = 784 (ATOM_HPD_INT_RECORD *) 785 record; 786 gpio = radeon_atombios_lookup_gpio(rdev, 787 hpd_record->ucHPDIntGPIOID); 788 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio); 789 hpd.plugged_state = hpd_record->ucPlugged_PinState; 790 break; 791 } 792 record = 793 (ATOM_COMMON_RECORD_HEADER 794 *) ((char *)record 795 + 796 record-> 797 ucRecordSize); 798 } 799 break; 800 } 801 } 802 } 803 804 /* needed for aux chan transactions */ 805 ddc_bus.hpd = hpd.hpd; 806 807 conn_id = le16_to_cpu(path->usConnObjectId); 808 809 if (!radeon_atom_apply_quirks 810 (dev, le16_to_cpu(path->usDeviceTag), &connector_type, 811 &ddc_bus, &conn_id, &hpd)) 812 continue; 813 814 radeon_add_atom_connector(dev, 815 conn_id, 816 le16_to_cpu(path-> 817 usDeviceTag), 818 connector_type, &ddc_bus, 819 igp_lane_info, 820 connector_object_id, 821 &hpd, 822 &router); 823 824 } 825 } 826 827 radeon_link_encoder_connector(dev); 828 829 radeon_setup_mst_connector(dev); 830 return true; 831 } 832 833 static uint16_t atombios_get_connector_object_id(struct drm_device *dev, 834 int connector_type, 835 uint16_t devices) 836 { 837 struct radeon_device *rdev = dev->dev_private; 838 839 if (rdev->flags & RADEON_IS_IGP) { 840 return supported_devices_connector_object_id_convert 841 [connector_type]; 842 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) || 843 (connector_type == DRM_MODE_CONNECTOR_DVID)) && 844 (devices & ATOM_DEVICE_DFP2_SUPPORT)) { 845 struct radeon_mode_info *mode_info = &rdev->mode_info; 846 struct atom_context *ctx = mode_info->atom_context; 847 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info); 848 uint16_t size, data_offset; 849 uint8_t frev, crev; 850 ATOM_XTMDS_INFO *xtmds; 851 852 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) { 853 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset); 854 855 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) { 856 if (connector_type == DRM_MODE_CONNECTOR_DVII) 857 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I; 858 else 859 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D; 860 } else { 861 if (connector_type == DRM_MODE_CONNECTOR_DVII) 862 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 863 else 864 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D; 865 } 866 } else 867 return supported_devices_connector_object_id_convert 868 [connector_type]; 869 } else { 870 return supported_devices_connector_object_id_convert 871 [connector_type]; 872 } 873 } 874 875 struct bios_connector { 876 bool valid; 877 uint16_t line_mux; 878 uint16_t devices; 879 int connector_type; 880 struct radeon_i2c_bus_rec ddc_bus; 881 struct radeon_hpd hpd; 882 }; 883 884 bool radeon_get_atom_connector_info_from_supported_devices_table(struct 885 drm_device 886 *dev) 887 { 888 struct radeon_device *rdev = dev->dev_private; 889 struct radeon_mode_info *mode_info = &rdev->mode_info; 890 struct atom_context *ctx = mode_info->atom_context; 891 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo); 892 uint16_t size, data_offset; 893 uint8_t frev, crev; 894 uint16_t device_support; 895 uint8_t dac; 896 union atom_supported_devices *supported_devices; 897 int i, j, max_device; 898 struct bios_connector *bios_connectors; 899 size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE; 900 struct radeon_router router; 901 902 router.ddc_valid = false; 903 router.cd_valid = false; 904 905 bios_connectors = kzalloc(bc_size, GFP_KERNEL); 906 if (!bios_connectors) 907 return false; 908 909 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, 910 &data_offset)) { 911 kfree(bios_connectors); 912 return false; 913 } 914 915 supported_devices = 916 (union atom_supported_devices *)(ctx->bios + data_offset); 917 918 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport); 919 920 if (frev > 1) 921 max_device = ATOM_MAX_SUPPORTED_DEVICE; 922 else 923 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO; 924 925 for (i = 0; i < max_device; i++) { 926 ATOM_CONNECTOR_INFO_I2C ci = 927 supported_devices->info.asConnInfo[i]; 928 929 bios_connectors[i].valid = false; 930 931 if (!(device_support & (1 << i))) { 932 continue; 933 } 934 935 if (i == ATOM_DEVICE_CV_INDEX) { 936 DRM_DEBUG_KMS("Skipping Component Video\n"); 937 continue; 938 } 939 940 bios_connectors[i].connector_type = 941 supported_devices_connector_convert[ci.sucConnectorInfo. 942 sbfAccess. 943 bfConnectorType]; 944 945 if (bios_connectors[i].connector_type == 946 DRM_MODE_CONNECTOR_Unknown) 947 continue; 948 949 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC; 950 951 bios_connectors[i].line_mux = 952 ci.sucI2cId.ucAccess; 953 954 /* give tv unique connector ids */ 955 if (i == ATOM_DEVICE_TV1_INDEX) { 956 bios_connectors[i].ddc_bus.valid = false; 957 bios_connectors[i].line_mux = 50; 958 } else if (i == ATOM_DEVICE_TV2_INDEX) { 959 bios_connectors[i].ddc_bus.valid = false; 960 bios_connectors[i].line_mux = 51; 961 } else if (i == ATOM_DEVICE_CV_INDEX) { 962 bios_connectors[i].ddc_bus.valid = false; 963 bios_connectors[i].line_mux = 52; 964 } else 965 bios_connectors[i].ddc_bus = 966 radeon_lookup_i2c_gpio(rdev, 967 bios_connectors[i].line_mux); 968 969 if ((crev > 1) && (frev > 1)) { 970 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap; 971 switch (isb) { 972 case 0x4: 973 bios_connectors[i].hpd.hpd = RADEON_HPD_1; 974 break; 975 case 0xa: 976 bios_connectors[i].hpd.hpd = RADEON_HPD_2; 977 break; 978 default: 979 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE; 980 break; 981 } 982 } else { 983 if (i == ATOM_DEVICE_DFP1_INDEX) 984 bios_connectors[i].hpd.hpd = RADEON_HPD_1; 985 else if (i == ATOM_DEVICE_DFP2_INDEX) 986 bios_connectors[i].hpd.hpd = RADEON_HPD_2; 987 else 988 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE; 989 } 990 991 /* Always set the connector type to VGA for CRT1/CRT2. if they are 992 * shared with a DVI port, we'll pick up the DVI connector when we 993 * merge the outputs. Some bioses incorrectly list VGA ports as DVI. 994 */ 995 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX) 996 bios_connectors[i].connector_type = 997 DRM_MODE_CONNECTOR_VGA; 998 999 if (!radeon_atom_apply_quirks 1000 (dev, (1 << i), &bios_connectors[i].connector_type, 1001 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux, 1002 &bios_connectors[i].hpd)) 1003 continue; 1004 1005 bios_connectors[i].valid = true; 1006 bios_connectors[i].devices = (1 << i); 1007 1008 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom) 1009 radeon_add_atom_encoder(dev, 1010 radeon_get_encoder_enum(dev, 1011 (1 << i), 1012 dac), 1013 (1 << i), 1014 0); 1015 else 1016 radeon_add_legacy_encoder(dev, 1017 radeon_get_encoder_enum(dev, 1018 (1 << i), 1019 dac), 1020 (1 << i)); 1021 } 1022 1023 /* combine shared connectors */ 1024 for (i = 0; i < max_device; i++) { 1025 if (bios_connectors[i].valid) { 1026 for (j = 0; j < max_device; j++) { 1027 if (bios_connectors[j].valid && (i != j)) { 1028 if (bios_connectors[i].line_mux == 1029 bios_connectors[j].line_mux) { 1030 /* make sure not to combine LVDS */ 1031 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1032 bios_connectors[i].line_mux = 53; 1033 bios_connectors[i].ddc_bus.valid = false; 1034 continue; 1035 } 1036 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1037 bios_connectors[j].line_mux = 53; 1038 bios_connectors[j].ddc_bus.valid = false; 1039 continue; 1040 } 1041 /* combine analog and digital for DVI-I */ 1042 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) && 1043 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) || 1044 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) && 1045 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) { 1046 bios_connectors[i].devices |= 1047 bios_connectors[j].devices; 1048 bios_connectors[i].connector_type = 1049 DRM_MODE_CONNECTOR_DVII; 1050 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) 1051 bios_connectors[i].hpd = 1052 bios_connectors[j].hpd; 1053 bios_connectors[j].valid = false; 1054 } 1055 } 1056 } 1057 } 1058 } 1059 } 1060 1061 /* add the connectors */ 1062 for (i = 0; i < max_device; i++) { 1063 if (bios_connectors[i].valid) { 1064 uint16_t connector_object_id = 1065 atombios_get_connector_object_id(dev, 1066 bios_connectors[i].connector_type, 1067 bios_connectors[i].devices); 1068 radeon_add_atom_connector(dev, 1069 bios_connectors[i].line_mux, 1070 bios_connectors[i].devices, 1071 bios_connectors[i]. 1072 connector_type, 1073 &bios_connectors[i].ddc_bus, 1074 0, 1075 connector_object_id, 1076 &bios_connectors[i].hpd, 1077 &router); 1078 } 1079 } 1080 1081 radeon_link_encoder_connector(dev); 1082 1083 kfree(bios_connectors); 1084 return true; 1085 } 1086 1087 union firmware_info { 1088 ATOM_FIRMWARE_INFO info; 1089 ATOM_FIRMWARE_INFO_V1_2 info_12; 1090 ATOM_FIRMWARE_INFO_V1_3 info_13; 1091 ATOM_FIRMWARE_INFO_V1_4 info_14; 1092 ATOM_FIRMWARE_INFO_V2_1 info_21; 1093 ATOM_FIRMWARE_INFO_V2_2 info_22; 1094 }; 1095 1096 union igp_info { 1097 struct _ATOM_INTEGRATED_SYSTEM_INFO info; 1098 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2; 1099 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6; 1100 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7; 1101 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8; 1102 }; 1103 1104 static void radeon_atombios_get_dentist_vco_freq(struct radeon_device *rdev) 1105 { 1106 struct radeon_mode_info *mode_info = &rdev->mode_info; 1107 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); 1108 union igp_info *igp_info; 1109 u8 frev, crev; 1110 u16 data_offset; 1111 1112 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1113 &frev, &crev, &data_offset)) { 1114 igp_info = (union igp_info *)(mode_info->atom_context->bios + 1115 data_offset); 1116 rdev->clock.vco_freq = 1117 le32_to_cpu(igp_info->info_6.ulDentistVCOFreq); 1118 } 1119 } 1120 1121 bool radeon_atom_get_clock_info(struct drm_device *dev) 1122 { 1123 struct radeon_device *rdev = dev->dev_private; 1124 struct radeon_mode_info *mode_info = &rdev->mode_info; 1125 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); 1126 union firmware_info *firmware_info; 1127 uint8_t frev, crev; 1128 struct radeon_pll *p1pll = &rdev->clock.p1pll; 1129 struct radeon_pll *p2pll = &rdev->clock.p2pll; 1130 struct radeon_pll *dcpll = &rdev->clock.dcpll; 1131 struct radeon_pll *spll = &rdev->clock.spll; 1132 struct radeon_pll *mpll = &rdev->clock.mpll; 1133 uint16_t data_offset; 1134 1135 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1136 &frev, &crev, &data_offset)) { 1137 firmware_info = 1138 (union firmware_info *)(mode_info->atom_context->bios + 1139 data_offset); 1140 /* pixel clocks */ 1141 p1pll->reference_freq = 1142 le16_to_cpu(firmware_info->info.usReferenceClock); 1143 p1pll->reference_div = 0; 1144 1145 if ((frev < 2) && (crev < 2)) 1146 p1pll->pll_out_min = 1147 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output); 1148 else 1149 p1pll->pll_out_min = 1150 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output); 1151 p1pll->pll_out_max = 1152 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output); 1153 1154 if (((frev < 2) && (crev >= 4)) || (frev >= 2)) { 1155 p1pll->lcd_pll_out_min = 1156 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100; 1157 if (p1pll->lcd_pll_out_min == 0) 1158 p1pll->lcd_pll_out_min = p1pll->pll_out_min; 1159 p1pll->lcd_pll_out_max = 1160 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100; 1161 if (p1pll->lcd_pll_out_max == 0) 1162 p1pll->lcd_pll_out_max = p1pll->pll_out_max; 1163 } else { 1164 p1pll->lcd_pll_out_min = p1pll->pll_out_min; 1165 p1pll->lcd_pll_out_max = p1pll->pll_out_max; 1166 } 1167 1168 if (p1pll->pll_out_min == 0) { 1169 if (ASIC_IS_AVIVO(rdev)) 1170 p1pll->pll_out_min = 64800; 1171 else 1172 p1pll->pll_out_min = 20000; 1173 } 1174 1175 p1pll->pll_in_min = 1176 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input); 1177 p1pll->pll_in_max = 1178 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input); 1179 1180 *p2pll = *p1pll; 1181 1182 /* system clock */ 1183 if (ASIC_IS_DCE4(rdev)) 1184 spll->reference_freq = 1185 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock); 1186 else 1187 spll->reference_freq = 1188 le16_to_cpu(firmware_info->info.usReferenceClock); 1189 spll->reference_div = 0; 1190 1191 spll->pll_out_min = 1192 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output); 1193 spll->pll_out_max = 1194 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output); 1195 1196 /* ??? */ 1197 if (spll->pll_out_min == 0) { 1198 if (ASIC_IS_AVIVO(rdev)) 1199 spll->pll_out_min = 64800; 1200 else 1201 spll->pll_out_min = 20000; 1202 } 1203 1204 spll->pll_in_min = 1205 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input); 1206 spll->pll_in_max = 1207 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input); 1208 1209 /* memory clock */ 1210 if (ASIC_IS_DCE4(rdev)) 1211 mpll->reference_freq = 1212 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock); 1213 else 1214 mpll->reference_freq = 1215 le16_to_cpu(firmware_info->info.usReferenceClock); 1216 mpll->reference_div = 0; 1217 1218 mpll->pll_out_min = 1219 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output); 1220 mpll->pll_out_max = 1221 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output); 1222 1223 /* ??? */ 1224 if (mpll->pll_out_min == 0) { 1225 if (ASIC_IS_AVIVO(rdev)) 1226 mpll->pll_out_min = 64800; 1227 else 1228 mpll->pll_out_min = 20000; 1229 } 1230 1231 mpll->pll_in_min = 1232 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input); 1233 mpll->pll_in_max = 1234 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input); 1235 1236 rdev->clock.default_sclk = 1237 le32_to_cpu(firmware_info->info.ulDefaultEngineClock); 1238 rdev->clock.default_mclk = 1239 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock); 1240 1241 if (ASIC_IS_DCE4(rdev)) { 1242 rdev->clock.default_dispclk = 1243 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq); 1244 if (rdev->clock.default_dispclk == 0) { 1245 if (ASIC_IS_DCE6(rdev)) 1246 rdev->clock.default_dispclk = 60000; /* 600 Mhz */ 1247 else if (ASIC_IS_DCE5(rdev)) 1248 rdev->clock.default_dispclk = 54000; /* 540 Mhz */ 1249 else 1250 rdev->clock.default_dispclk = 60000; /* 600 Mhz */ 1251 } 1252 /* set a reasonable default for DP */ 1253 if (ASIC_IS_DCE6(rdev) && (rdev->clock.default_dispclk < 53900)) { 1254 DRM_INFO("Changing default dispclk from %dMhz to 600Mhz\n", 1255 rdev->clock.default_dispclk / 100); 1256 rdev->clock.default_dispclk = 60000; 1257 } 1258 rdev->clock.dp_extclk = 1259 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq); 1260 rdev->clock.current_dispclk = rdev->clock.default_dispclk; 1261 } 1262 *dcpll = *p1pll; 1263 1264 rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock); 1265 if (rdev->clock.max_pixel_clock == 0) 1266 rdev->clock.max_pixel_clock = 40000; 1267 1268 /* not technically a clock, but... */ 1269 rdev->mode_info.firmware_flags = 1270 le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess); 1271 1272 if (ASIC_IS_DCE8(rdev)) 1273 rdev->clock.vco_freq = 1274 le32_to_cpu(firmware_info->info_22.ulGPUPLL_OutputFreq); 1275 else if (ASIC_IS_DCE5(rdev)) 1276 rdev->clock.vco_freq = rdev->clock.current_dispclk; 1277 else if (ASIC_IS_DCE41(rdev)) 1278 radeon_atombios_get_dentist_vco_freq(rdev); 1279 else 1280 rdev->clock.vco_freq = rdev->clock.current_dispclk; 1281 1282 if (rdev->clock.vco_freq == 0) 1283 rdev->clock.vco_freq = 360000; /* 3.6 GHz */ 1284 1285 return true; 1286 } 1287 1288 return false; 1289 } 1290 1291 bool radeon_atombios_sideport_present(struct radeon_device *rdev) 1292 { 1293 struct radeon_mode_info *mode_info = &rdev->mode_info; 1294 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); 1295 union igp_info *igp_info; 1296 u8 frev, crev; 1297 u16 data_offset; 1298 1299 /* sideport is AMD only */ 1300 if (rdev->family == CHIP_RS600) 1301 return false; 1302 1303 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1304 &frev, &crev, &data_offset)) { 1305 igp_info = (union igp_info *)(mode_info->atom_context->bios + 1306 data_offset); 1307 switch (crev) { 1308 case 1: 1309 if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock)) 1310 return true; 1311 break; 1312 case 2: 1313 if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock)) 1314 return true; 1315 break; 1316 default: 1317 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev); 1318 break; 1319 } 1320 } 1321 return false; 1322 } 1323 1324 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, 1325 struct radeon_encoder_int_tmds *tmds) 1326 { 1327 struct drm_device *dev = encoder->base.dev; 1328 struct radeon_device *rdev = dev->dev_private; 1329 struct radeon_mode_info *mode_info = &rdev->mode_info; 1330 int index = GetIndexIntoMasterTable(DATA, TMDS_Info); 1331 uint16_t data_offset; 1332 struct _ATOM_TMDS_INFO *tmds_info; 1333 uint8_t frev, crev; 1334 uint16_t maxfreq; 1335 int i; 1336 1337 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1338 &frev, &crev, &data_offset)) { 1339 tmds_info = 1340 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios + 1341 data_offset); 1342 1343 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency); 1344 for (i = 0; i < 4; i++) { 1345 tmds->tmds_pll[i].freq = 1346 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency); 1347 tmds->tmds_pll[i].value = 1348 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f; 1349 tmds->tmds_pll[i].value |= 1350 (tmds_info->asMiscInfo[i]. 1351 ucPLL_VCO_Gain & 0x3f) << 6; 1352 tmds->tmds_pll[i].value |= 1353 (tmds_info->asMiscInfo[i]. 1354 ucPLL_DutyCycle & 0xf) << 12; 1355 tmds->tmds_pll[i].value |= 1356 (tmds_info->asMiscInfo[i]. 1357 ucPLL_VoltageSwing & 0xf) << 16; 1358 1359 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n", 1360 tmds->tmds_pll[i].freq, 1361 tmds->tmds_pll[i].value); 1362 1363 if (maxfreq == tmds->tmds_pll[i].freq) { 1364 tmds->tmds_pll[i].freq = 0xffffffff; 1365 break; 1366 } 1367 } 1368 return true; 1369 } 1370 return false; 1371 } 1372 1373 bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev, 1374 struct radeon_atom_ss *ss, 1375 int id) 1376 { 1377 struct radeon_mode_info *mode_info = &rdev->mode_info; 1378 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info); 1379 uint16_t data_offset, size; 1380 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info; 1381 struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT *ss_assign; 1382 uint8_t frev, crev; 1383 int i, num_indices; 1384 1385 memset(ss, 0, sizeof(struct radeon_atom_ss)); 1386 if (atom_parse_data_header(mode_info->atom_context, index, &size, 1387 &frev, &crev, &data_offset)) { 1388 ss_info = 1389 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset); 1390 1391 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 1392 sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT); 1393 ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT*) 1394 ((u8 *)&ss_info->asSS_Info[0]); 1395 for (i = 0; i < num_indices; i++) { 1396 if (ss_assign->ucSS_Id == id) { 1397 ss->percentage = 1398 le16_to_cpu(ss_assign->usSpreadSpectrumPercentage); 1399 ss->type = ss_assign->ucSpreadSpectrumType; 1400 ss->step = ss_assign->ucSS_Step; 1401 ss->delay = ss_assign->ucSS_Delay; 1402 ss->range = ss_assign->ucSS_Range; 1403 ss->refdiv = ss_assign->ucRecommendedRef_Div; 1404 return true; 1405 } 1406 ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT*) 1407 ((u8 *)ss_assign + sizeof(struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT)); 1408 } 1409 } 1410 return false; 1411 } 1412 1413 static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev, 1414 struct radeon_atom_ss *ss, 1415 int id) 1416 { 1417 struct radeon_mode_info *mode_info = &rdev->mode_info; 1418 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); 1419 u16 data_offset, size; 1420 union igp_info *igp_info; 1421 u8 frev, crev; 1422 u16 percentage = 0, rate = 0; 1423 1424 /* get any igp specific overrides */ 1425 if (atom_parse_data_header(mode_info->atom_context, index, &size, 1426 &frev, &crev, &data_offset)) { 1427 igp_info = (union igp_info *) 1428 (mode_info->atom_context->bios + data_offset); 1429 switch (crev) { 1430 case 6: 1431 switch (id) { 1432 case ASIC_INTERNAL_SS_ON_TMDS: 1433 percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage); 1434 rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz); 1435 break; 1436 case ASIC_INTERNAL_SS_ON_HDMI: 1437 percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage); 1438 rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz); 1439 break; 1440 case ASIC_INTERNAL_SS_ON_LVDS: 1441 percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage); 1442 rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz); 1443 break; 1444 } 1445 break; 1446 case 7: 1447 switch (id) { 1448 case ASIC_INTERNAL_SS_ON_TMDS: 1449 percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage); 1450 rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz); 1451 break; 1452 case ASIC_INTERNAL_SS_ON_HDMI: 1453 percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage); 1454 rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz); 1455 break; 1456 case ASIC_INTERNAL_SS_ON_LVDS: 1457 percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage); 1458 rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz); 1459 break; 1460 } 1461 break; 1462 case 8: 1463 switch (id) { 1464 case ASIC_INTERNAL_SS_ON_TMDS: 1465 percentage = le16_to_cpu(igp_info->info_8.usDVISSPercentage); 1466 rate = le16_to_cpu(igp_info->info_8.usDVISSpreadRateIn10Hz); 1467 break; 1468 case ASIC_INTERNAL_SS_ON_HDMI: 1469 percentage = le16_to_cpu(igp_info->info_8.usHDMISSPercentage); 1470 rate = le16_to_cpu(igp_info->info_8.usHDMISSpreadRateIn10Hz); 1471 break; 1472 case ASIC_INTERNAL_SS_ON_LVDS: 1473 percentage = le16_to_cpu(igp_info->info_8.usLvdsSSPercentage); 1474 rate = le16_to_cpu(igp_info->info_8.usLvdsSSpreadRateIn10Hz); 1475 break; 1476 } 1477 break; 1478 default: 1479 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev); 1480 break; 1481 } 1482 if (percentage) 1483 ss->percentage = percentage; 1484 if (rate) 1485 ss->rate = rate; 1486 } 1487 } 1488 1489 union asic_ss_info { 1490 struct _ATOM_ASIC_INTERNAL_SS_INFO info; 1491 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2; 1492 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3; 1493 }; 1494 1495 union asic_ss_assignment { 1496 struct _ATOM_ASIC_SS_ASSIGNMENT v1; 1497 struct _ATOM_ASIC_SS_ASSIGNMENT_V2 v2; 1498 struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3; 1499 }; 1500 1501 bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev, 1502 struct radeon_atom_ss *ss, 1503 int id, u32 clock) 1504 { 1505 struct radeon_mode_info *mode_info = &rdev->mode_info; 1506 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info); 1507 uint16_t data_offset, size; 1508 union asic_ss_info *ss_info; 1509 union asic_ss_assignment *ss_assign; 1510 uint8_t frev, crev; 1511 int i, num_indices; 1512 1513 if (id == ASIC_INTERNAL_MEMORY_SS) { 1514 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT)) 1515 return false; 1516 } 1517 if (id == ASIC_INTERNAL_ENGINE_SS) { 1518 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT)) 1519 return false; 1520 } 1521 1522 memset(ss, 0, sizeof(struct radeon_atom_ss)); 1523 if (atom_parse_data_header(mode_info->atom_context, index, &size, 1524 &frev, &crev, &data_offset)) { 1525 1526 ss_info = 1527 (union asic_ss_info *)(mode_info->atom_context->bios + data_offset); 1528 1529 switch (frev) { 1530 case 1: 1531 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 1532 sizeof(ATOM_ASIC_SS_ASSIGNMENT); 1533 1534 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info.asSpreadSpectrum[0]); 1535 for (i = 0; i < num_indices; i++) { 1536 if ((ss_assign->v1.ucClockIndication == id) && 1537 (clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) { 1538 ss->percentage = 1539 le16_to_cpu(ss_assign->v1.usSpreadSpectrumPercentage); 1540 ss->type = ss_assign->v1.ucSpreadSpectrumMode; 1541 ss->rate = le16_to_cpu(ss_assign->v1.usSpreadRateInKhz); 1542 ss->percentage_divider = 100; 1543 return true; 1544 } 1545 ss_assign = (union asic_ss_assignment *) 1546 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT)); 1547 } 1548 break; 1549 case 2: 1550 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 1551 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2); 1552 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_2.asSpreadSpectrum[0]); 1553 for (i = 0; i < num_indices; i++) { 1554 if ((ss_assign->v2.ucClockIndication == id) && 1555 (clock <= le32_to_cpu(ss_assign->v2.ulTargetClockRange))) { 1556 ss->percentage = 1557 le16_to_cpu(ss_assign->v2.usSpreadSpectrumPercentage); 1558 ss->type = ss_assign->v2.ucSpreadSpectrumMode; 1559 ss->rate = le16_to_cpu(ss_assign->v2.usSpreadRateIn10Hz); 1560 ss->percentage_divider = 100; 1561 if ((crev == 2) && 1562 ((id == ASIC_INTERNAL_ENGINE_SS) || 1563 (id == ASIC_INTERNAL_MEMORY_SS))) 1564 ss->rate /= 100; 1565 return true; 1566 } 1567 ss_assign = (union asic_ss_assignment *) 1568 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2)); 1569 } 1570 break; 1571 case 3: 1572 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 1573 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3); 1574 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_3.asSpreadSpectrum[0]); 1575 for (i = 0; i < num_indices; i++) { 1576 if ((ss_assign->v3.ucClockIndication == id) && 1577 (clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) { 1578 ss->percentage = 1579 le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage); 1580 ss->type = ss_assign->v3.ucSpreadSpectrumMode; 1581 ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz); 1582 if (ss_assign->v3.ucSpreadSpectrumMode & 1583 SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK) 1584 ss->percentage_divider = 1000; 1585 else 1586 ss->percentage_divider = 100; 1587 if ((id == ASIC_INTERNAL_ENGINE_SS) || 1588 (id == ASIC_INTERNAL_MEMORY_SS)) 1589 ss->rate /= 100; 1590 if (rdev->flags & RADEON_IS_IGP) 1591 radeon_atombios_get_igp_ss_overrides(rdev, ss, id); 1592 return true; 1593 } 1594 ss_assign = (union asic_ss_assignment *) 1595 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3)); 1596 } 1597 break; 1598 default: 1599 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev); 1600 break; 1601 } 1602 1603 } 1604 return false; 1605 } 1606 1607 union lvds_info { 1608 struct _ATOM_LVDS_INFO info; 1609 struct _ATOM_LVDS_INFO_V12 info_12; 1610 }; 1611 1612 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct 1613 radeon_encoder 1614 *encoder) 1615 { 1616 struct drm_device *dev = encoder->base.dev; 1617 struct radeon_device *rdev = dev->dev_private; 1618 struct radeon_mode_info *mode_info = &rdev->mode_info; 1619 int index = GetIndexIntoMasterTable(DATA, LVDS_Info); 1620 uint16_t data_offset, misc; 1621 union lvds_info *lvds_info; 1622 uint8_t frev, crev; 1623 struct radeon_encoder_atom_dig *lvds = NULL; 1624 int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; 1625 1626 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1627 &frev, &crev, &data_offset)) { 1628 lvds_info = 1629 (union lvds_info *)(mode_info->atom_context->bios + data_offset); 1630 lvds = 1631 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); 1632 1633 if (!lvds) 1634 return NULL; 1635 1636 lvds->native_mode.clock = 1637 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10; 1638 lvds->native_mode.hdisplay = 1639 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive); 1640 lvds->native_mode.vdisplay = 1641 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive); 1642 lvds->native_mode.htotal = lvds->native_mode.hdisplay + 1643 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time); 1644 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay + 1645 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset); 1646 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start + 1647 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth); 1648 lvds->native_mode.vtotal = lvds->native_mode.vdisplay + 1649 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time); 1650 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay + 1651 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset); 1652 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start + 1653 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth); 1654 lvds->panel_pwr_delay = 1655 le16_to_cpu(lvds_info->info.usOffDelayInMs); 1656 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc; 1657 1658 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess); 1659 if (misc & ATOM_VSYNC_POLARITY) 1660 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC; 1661 if (misc & ATOM_HSYNC_POLARITY) 1662 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC; 1663 if (misc & ATOM_COMPOSITESYNC) 1664 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC; 1665 if (misc & ATOM_INTERLACE) 1666 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE; 1667 if (misc & ATOM_DOUBLE_CLOCK_MODE) 1668 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN; 1669 1670 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize); 1671 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize); 1672 1673 /* set crtc values */ 1674 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V); 1675 1676 lvds->lcd_ss_id = lvds_info->info.ucSS_Id; 1677 1678 encoder->native_mode = lvds->native_mode; 1679 1680 if (encoder_enum == 2) 1681 lvds->linkb = true; 1682 else 1683 lvds->linkb = false; 1684 1685 /* parse the lcd record table */ 1686 if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) { 1687 ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record; 1688 ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record; 1689 bool bad_record = false; 1690 u8 *record; 1691 1692 if ((frev == 1) && (crev < 2)) 1693 /* absolute */ 1694 record = (u8 *)(mode_info->atom_context->bios + 1695 le16_to_cpu(lvds_info->info.usModePatchTableOffset)); 1696 else 1697 /* relative */ 1698 record = (u8 *)(mode_info->atom_context->bios + 1699 data_offset + 1700 le16_to_cpu(lvds_info->info.usModePatchTableOffset)); 1701 while (*record != ATOM_RECORD_END_TYPE) { 1702 switch (*record) { 1703 case LCD_MODE_PATCH_RECORD_MODE_TYPE: 1704 record += sizeof(ATOM_PATCH_RECORD_MODE); 1705 break; 1706 case LCD_RTS_RECORD_TYPE: 1707 record += sizeof(ATOM_LCD_RTS_RECORD); 1708 break; 1709 case LCD_CAP_RECORD_TYPE: 1710 record += sizeof(ATOM_LCD_MODE_CONTROL_CAP); 1711 break; 1712 case LCD_FAKE_EDID_PATCH_RECORD_TYPE: 1713 fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record; 1714 if (fake_edid_record->ucFakeEDIDLength) { 1715 struct edid *edid; 1716 int edid_size = 1717 max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength); 1718 edid = kmalloc(edid_size, GFP_KERNEL); 1719 if (edid) { 1720 memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0], 1721 fake_edid_record->ucFakeEDIDLength); 1722 1723 if (drm_edid_is_valid(edid)) { 1724 rdev->mode_info.bios_hardcoded_edid = edid; 1725 rdev->mode_info.bios_hardcoded_edid_size = edid_size; 1726 } else 1727 kfree(edid); 1728 } 1729 } 1730 record += fake_edid_record->ucFakeEDIDLength ? 1731 fake_edid_record->ucFakeEDIDLength + 2 : 1732 sizeof(ATOM_FAKE_EDID_PATCH_RECORD); 1733 break; 1734 case LCD_PANEL_RESOLUTION_RECORD_TYPE: 1735 panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record; 1736 lvds->native_mode.width_mm = panel_res_record->usHSize; 1737 lvds->native_mode.height_mm = panel_res_record->usVSize; 1738 record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD); 1739 break; 1740 default: 1741 DRM_ERROR("Bad LCD record %d\n", *record); 1742 bad_record = true; 1743 break; 1744 } 1745 if (bad_record) 1746 break; 1747 } 1748 } 1749 } 1750 return lvds; 1751 } 1752 1753 struct radeon_encoder_primary_dac * 1754 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder) 1755 { 1756 struct drm_device *dev = encoder->base.dev; 1757 struct radeon_device *rdev = dev->dev_private; 1758 struct radeon_mode_info *mode_info = &rdev->mode_info; 1759 int index = GetIndexIntoMasterTable(DATA, CompassionateData); 1760 uint16_t data_offset; 1761 struct _COMPASSIONATE_DATA *dac_info; 1762 uint8_t frev, crev; 1763 uint8_t bg, dac; 1764 struct radeon_encoder_primary_dac *p_dac = NULL; 1765 1766 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1767 &frev, &crev, &data_offset)) { 1768 dac_info = (struct _COMPASSIONATE_DATA *) 1769 (mode_info->atom_context->bios + data_offset); 1770 1771 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL); 1772 1773 if (!p_dac) 1774 return NULL; 1775 1776 bg = dac_info->ucDAC1_BG_Adjustment; 1777 dac = dac_info->ucDAC1_DAC_Adjustment; 1778 p_dac->ps2_pdac_adj = (bg << 8) | (dac); 1779 1780 } 1781 return p_dac; 1782 } 1783 1784 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, 1785 struct drm_display_mode *mode) 1786 { 1787 struct radeon_mode_info *mode_info = &rdev->mode_info; 1788 ATOM_ANALOG_TV_INFO *tv_info; 1789 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2; 1790 ATOM_DTD_FORMAT *dtd_timings; 1791 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info); 1792 u8 frev, crev; 1793 u16 data_offset, misc; 1794 1795 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL, 1796 &frev, &crev, &data_offset)) 1797 return false; 1798 1799 switch (crev) { 1800 case 1: 1801 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset); 1802 if (index >= MAX_SUPPORTED_TV_TIMING) 1803 return false; 1804 1805 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total); 1806 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp); 1807 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart); 1808 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) + 1809 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth); 1810 1811 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total); 1812 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp); 1813 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart); 1814 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) + 1815 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth); 1816 1817 mode->flags = 0; 1818 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess); 1819 if (misc & ATOM_VSYNC_POLARITY) 1820 mode->flags |= DRM_MODE_FLAG_NVSYNC; 1821 if (misc & ATOM_HSYNC_POLARITY) 1822 mode->flags |= DRM_MODE_FLAG_NHSYNC; 1823 if (misc & ATOM_COMPOSITESYNC) 1824 mode->flags |= DRM_MODE_FLAG_CSYNC; 1825 if (misc & ATOM_INTERLACE) 1826 mode->flags |= DRM_MODE_FLAG_INTERLACE; 1827 if (misc & ATOM_DOUBLE_CLOCK_MODE) 1828 mode->flags |= DRM_MODE_FLAG_DBLSCAN; 1829 1830 mode->crtc_clock = mode->clock = 1831 le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10; 1832 1833 if (index == 1) { 1834 /* PAL timings appear to have wrong values for totals */ 1835 mode->crtc_htotal -= 1; 1836 mode->crtc_vtotal -= 1; 1837 } 1838 break; 1839 case 2: 1840 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset); 1841 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2) 1842 return false; 1843 1844 dtd_timings = &tv_info_v1_2->aModeTimings[index]; 1845 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) + 1846 le16_to_cpu(dtd_timings->usHBlanking_Time); 1847 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive); 1848 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) + 1849 le16_to_cpu(dtd_timings->usHSyncOffset); 1850 mode->crtc_hsync_end = mode->crtc_hsync_start + 1851 le16_to_cpu(dtd_timings->usHSyncWidth); 1852 1853 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) + 1854 le16_to_cpu(dtd_timings->usVBlanking_Time); 1855 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive); 1856 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) + 1857 le16_to_cpu(dtd_timings->usVSyncOffset); 1858 mode->crtc_vsync_end = mode->crtc_vsync_start + 1859 le16_to_cpu(dtd_timings->usVSyncWidth); 1860 1861 mode->flags = 0; 1862 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess); 1863 if (misc & ATOM_VSYNC_POLARITY) 1864 mode->flags |= DRM_MODE_FLAG_NVSYNC; 1865 if (misc & ATOM_HSYNC_POLARITY) 1866 mode->flags |= DRM_MODE_FLAG_NHSYNC; 1867 if (misc & ATOM_COMPOSITESYNC) 1868 mode->flags |= DRM_MODE_FLAG_CSYNC; 1869 if (misc & ATOM_INTERLACE) 1870 mode->flags |= DRM_MODE_FLAG_INTERLACE; 1871 if (misc & ATOM_DOUBLE_CLOCK_MODE) 1872 mode->flags |= DRM_MODE_FLAG_DBLSCAN; 1873 1874 mode->crtc_clock = mode->clock = 1875 le16_to_cpu(dtd_timings->usPixClk) * 10; 1876 break; 1877 } 1878 return true; 1879 } 1880 1881 enum radeon_tv_std 1882 radeon_atombios_get_tv_info(struct radeon_device *rdev) 1883 { 1884 struct radeon_mode_info *mode_info = &rdev->mode_info; 1885 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info); 1886 uint16_t data_offset; 1887 uint8_t frev, crev; 1888 struct _ATOM_ANALOG_TV_INFO *tv_info; 1889 enum radeon_tv_std tv_std = TV_STD_NTSC; 1890 1891 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1892 &frev, &crev, &data_offset)) { 1893 1894 tv_info = (struct _ATOM_ANALOG_TV_INFO *) 1895 (mode_info->atom_context->bios + data_offset); 1896 1897 switch (tv_info->ucTV_BootUpDefaultStandard) { 1898 case ATOM_TV_NTSC: 1899 tv_std = TV_STD_NTSC; 1900 DRM_DEBUG_KMS("Default TV standard: NTSC\n"); 1901 break; 1902 case ATOM_TV_NTSCJ: 1903 tv_std = TV_STD_NTSC_J; 1904 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n"); 1905 break; 1906 case ATOM_TV_PAL: 1907 tv_std = TV_STD_PAL; 1908 DRM_DEBUG_KMS("Default TV standard: PAL\n"); 1909 break; 1910 case ATOM_TV_PALM: 1911 tv_std = TV_STD_PAL_M; 1912 DRM_DEBUG_KMS("Default TV standard: PAL-M\n"); 1913 break; 1914 case ATOM_TV_PALN: 1915 tv_std = TV_STD_PAL_N; 1916 DRM_DEBUG_KMS("Default TV standard: PAL-N\n"); 1917 break; 1918 case ATOM_TV_PALCN: 1919 tv_std = TV_STD_PAL_CN; 1920 DRM_DEBUG_KMS("Default TV standard: PAL-CN\n"); 1921 break; 1922 case ATOM_TV_PAL60: 1923 tv_std = TV_STD_PAL_60; 1924 DRM_DEBUG_KMS("Default TV standard: PAL-60\n"); 1925 break; 1926 case ATOM_TV_SECAM: 1927 tv_std = TV_STD_SECAM; 1928 DRM_DEBUG_KMS("Default TV standard: SECAM\n"); 1929 break; 1930 default: 1931 tv_std = TV_STD_NTSC; 1932 DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n"); 1933 break; 1934 } 1935 } 1936 return tv_std; 1937 } 1938 1939 struct radeon_encoder_tv_dac * 1940 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder) 1941 { 1942 struct drm_device *dev = encoder->base.dev; 1943 struct radeon_device *rdev = dev->dev_private; 1944 struct radeon_mode_info *mode_info = &rdev->mode_info; 1945 int index = GetIndexIntoMasterTable(DATA, CompassionateData); 1946 uint16_t data_offset; 1947 struct _COMPASSIONATE_DATA *dac_info; 1948 uint8_t frev, crev; 1949 uint8_t bg, dac; 1950 struct radeon_encoder_tv_dac *tv_dac = NULL; 1951 1952 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1953 &frev, &crev, &data_offset)) { 1954 1955 dac_info = (struct _COMPASSIONATE_DATA *) 1956 (mode_info->atom_context->bios + data_offset); 1957 1958 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL); 1959 1960 if (!tv_dac) 1961 return NULL; 1962 1963 bg = dac_info->ucDAC2_CRT2_BG_Adjustment; 1964 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment; 1965 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20); 1966 1967 bg = dac_info->ucDAC2_PAL_BG_Adjustment; 1968 dac = dac_info->ucDAC2_PAL_DAC_Adjustment; 1969 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20); 1970 1971 bg = dac_info->ucDAC2_NTSC_BG_Adjustment; 1972 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment; 1973 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); 1974 1975 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev); 1976 } 1977 return tv_dac; 1978 } 1979 1980 static const char *thermal_controller_names[] = { 1981 "NONE", 1982 "lm63", 1983 "adm1032", 1984 "adm1030", 1985 "max6649", 1986 "lm63", /* lm64 */ 1987 "f75375", 1988 "asc7xxx", 1989 }; 1990 1991 static const char *pp_lib_thermal_controller_names[] = { 1992 "NONE", 1993 "lm63", 1994 "adm1032", 1995 "adm1030", 1996 "max6649", 1997 "lm63", /* lm64 */ 1998 "f75375", 1999 "RV6xx", 2000 "RV770", 2001 "adt7473", 2002 "NONE", 2003 "External GPIO", 2004 "Evergreen", 2005 "emc2103", 2006 "Sumo", 2007 "Northern Islands", 2008 "Southern Islands", 2009 "lm96163", 2010 "Sea Islands", 2011 }; 2012 2013 union power_info { 2014 struct _ATOM_POWERPLAY_INFO info; 2015 struct _ATOM_POWERPLAY_INFO_V2 info_2; 2016 struct _ATOM_POWERPLAY_INFO_V3 info_3; 2017 struct _ATOM_PPLIB_POWERPLAYTABLE pplib; 2018 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; 2019 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; 2020 }; 2021 2022 union pplib_clock_info { 2023 struct _ATOM_PPLIB_R600_CLOCK_INFO r600; 2024 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; 2025 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; 2026 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; 2027 struct _ATOM_PPLIB_SI_CLOCK_INFO si; 2028 struct _ATOM_PPLIB_CI_CLOCK_INFO ci; 2029 }; 2030 2031 union pplib_power_state { 2032 struct _ATOM_PPLIB_STATE v1; 2033 struct _ATOM_PPLIB_STATE_V2 v2; 2034 }; 2035 2036 static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev, 2037 int state_index, 2038 u32 misc, u32 misc2) 2039 { 2040 rdev->pm.power_state[state_index].misc = misc; 2041 rdev->pm.power_state[state_index].misc2 = misc2; 2042 /* order matters! */ 2043 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE) 2044 rdev->pm.power_state[state_index].type = 2045 POWER_STATE_TYPE_POWERSAVE; 2046 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE) 2047 rdev->pm.power_state[state_index].type = 2048 POWER_STATE_TYPE_BATTERY; 2049 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE) 2050 rdev->pm.power_state[state_index].type = 2051 POWER_STATE_TYPE_BATTERY; 2052 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN) 2053 rdev->pm.power_state[state_index].type = 2054 POWER_STATE_TYPE_BALANCED; 2055 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) { 2056 rdev->pm.power_state[state_index].type = 2057 POWER_STATE_TYPE_PERFORMANCE; 2058 rdev->pm.power_state[state_index].flags &= 2059 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2060 } 2061 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE) 2062 rdev->pm.power_state[state_index].type = 2063 POWER_STATE_TYPE_BALANCED; 2064 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) { 2065 rdev->pm.power_state[state_index].type = 2066 POWER_STATE_TYPE_DEFAULT; 2067 rdev->pm.default_power_state_index = state_index; 2068 rdev->pm.power_state[state_index].default_clock_mode = 2069 &rdev->pm.power_state[state_index].clock_info[0]; 2070 } else if (state_index == 0) { 2071 rdev->pm.power_state[state_index].clock_info[0].flags |= 2072 RADEON_PM_MODE_NO_DISPLAY; 2073 } 2074 } 2075 2076 static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev) 2077 { 2078 struct radeon_mode_info *mode_info = &rdev->mode_info; 2079 u32 misc, misc2 = 0; 2080 int num_modes = 0, i; 2081 int state_index = 0; 2082 struct radeon_i2c_bus_rec i2c_bus; 2083 union power_info *power_info; 2084 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 2085 u16 data_offset; 2086 u8 frev, crev; 2087 2088 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 2089 &frev, &crev, &data_offset)) 2090 return state_index; 2091 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 2092 2093 /* add the i2c bus for thermal/fan chip */ 2094 if ((power_info->info.ucOverdriveThermalController > 0) && 2095 (power_info->info.ucOverdriveThermalController < ARRAY_SIZE(thermal_controller_names))) { 2096 DRM_INFO("Possible %s thermal controller at 0x%02x\n", 2097 thermal_controller_names[power_info->info.ucOverdriveThermalController], 2098 power_info->info.ucOverdriveControllerAddress >> 1); 2099 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine); 2100 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 2101 if (rdev->pm.i2c_bus) { 2102 struct i2c_board_info info = { }; 2103 const char *name = thermal_controller_names[power_info->info. 2104 ucOverdriveThermalController]; 2105 info.addr = power_info->info.ucOverdriveControllerAddress >> 1; 2106 strlcpy(info.type, name, sizeof(info.type)); 2107 i2c_new_client_device(&rdev->pm.i2c_bus->adapter, &info); 2108 } 2109 } 2110 num_modes = power_info->info.ucNumOfPowerModeEntries; 2111 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK) 2112 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK; 2113 if (num_modes == 0) 2114 return state_index; 2115 rdev->pm.power_state = kcalloc(num_modes, 2116 sizeof(struct radeon_power_state), 2117 GFP_KERNEL); 2118 if (!rdev->pm.power_state) 2119 return state_index; 2120 /* last mode is usually default, array is low to high */ 2121 for (i = 0; i < num_modes; i++) { 2122 rdev->pm.power_state[state_index].clock_info = 2123 kcalloc(1, sizeof(struct radeon_pm_clock_info), 2124 GFP_KERNEL); 2125 if (!rdev->pm.power_state[state_index].clock_info) 2126 return state_index; 2127 rdev->pm.power_state[state_index].num_clock_modes = 1; 2128 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; 2129 switch (frev) { 2130 case 1: 2131 rdev->pm.power_state[state_index].clock_info[0].mclk = 2132 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock); 2133 rdev->pm.power_state[state_index].clock_info[0].sclk = 2134 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock); 2135 /* skip invalid modes */ 2136 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || 2137 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) 2138 continue; 2139 rdev->pm.power_state[state_index].pcie_lanes = 2140 power_info->info.asPowerPlayInfo[i].ucNumPciELanes; 2141 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo); 2142 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) || 2143 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) { 2144 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2145 VOLTAGE_GPIO; 2146 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio = 2147 radeon_atombios_lookup_gpio(rdev, 2148 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex); 2149 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH) 2150 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2151 true; 2152 else 2153 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2154 false; 2155 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) { 2156 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2157 VOLTAGE_VDDC; 2158 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id = 2159 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex; 2160 } 2161 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2162 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0); 2163 state_index++; 2164 break; 2165 case 2: 2166 rdev->pm.power_state[state_index].clock_info[0].mclk = 2167 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock); 2168 rdev->pm.power_state[state_index].clock_info[0].sclk = 2169 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock); 2170 /* skip invalid modes */ 2171 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || 2172 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) 2173 continue; 2174 rdev->pm.power_state[state_index].pcie_lanes = 2175 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes; 2176 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo); 2177 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2); 2178 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) || 2179 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) { 2180 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2181 VOLTAGE_GPIO; 2182 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio = 2183 radeon_atombios_lookup_gpio(rdev, 2184 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex); 2185 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH) 2186 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2187 true; 2188 else 2189 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2190 false; 2191 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) { 2192 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2193 VOLTAGE_VDDC; 2194 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id = 2195 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex; 2196 } 2197 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2198 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2); 2199 state_index++; 2200 break; 2201 case 3: 2202 rdev->pm.power_state[state_index].clock_info[0].mclk = 2203 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock); 2204 rdev->pm.power_state[state_index].clock_info[0].sclk = 2205 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock); 2206 /* skip invalid modes */ 2207 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || 2208 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) 2209 continue; 2210 rdev->pm.power_state[state_index].pcie_lanes = 2211 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes; 2212 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo); 2213 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2); 2214 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) || 2215 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) { 2216 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2217 VOLTAGE_GPIO; 2218 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio = 2219 radeon_atombios_lookup_gpio(rdev, 2220 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex); 2221 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH) 2222 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2223 true; 2224 else 2225 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2226 false; 2227 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) { 2228 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2229 VOLTAGE_VDDC; 2230 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id = 2231 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex; 2232 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) { 2233 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled = 2234 true; 2235 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id = 2236 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex; 2237 } 2238 } 2239 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2240 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2); 2241 state_index++; 2242 break; 2243 } 2244 } 2245 /* last mode is usually default */ 2246 if (rdev->pm.default_power_state_index == -1) { 2247 rdev->pm.power_state[state_index - 1].type = 2248 POWER_STATE_TYPE_DEFAULT; 2249 rdev->pm.default_power_state_index = state_index - 1; 2250 rdev->pm.power_state[state_index - 1].default_clock_mode = 2251 &rdev->pm.power_state[state_index - 1].clock_info[0]; 2252 rdev->pm.power_state[state_index].flags &= 2253 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2254 rdev->pm.power_state[state_index].misc = 0; 2255 rdev->pm.power_state[state_index].misc2 = 0; 2256 } 2257 return state_index; 2258 } 2259 2260 static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev, 2261 ATOM_PPLIB_THERMALCONTROLLER *controller) 2262 { 2263 struct radeon_i2c_bus_rec i2c_bus; 2264 2265 /* add the i2c bus for thermal/fan chip */ 2266 if (controller->ucType > 0) { 2267 if (controller->ucFanParameters & ATOM_PP_FANPARAMETERS_NOFAN) 2268 rdev->pm.no_fan = true; 2269 rdev->pm.fan_pulses_per_revolution = 2270 controller->ucFanParameters & ATOM_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK; 2271 if (rdev->pm.fan_pulses_per_revolution) { 2272 rdev->pm.fan_min_rpm = controller->ucFanMinRPM; 2273 rdev->pm.fan_max_rpm = controller->ucFanMaxRPM; 2274 } 2275 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) { 2276 DRM_INFO("Internal thermal controller %s fan control\n", 2277 (controller->ucFanParameters & 2278 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2279 rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX; 2280 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) { 2281 DRM_INFO("Internal thermal controller %s fan control\n", 2282 (controller->ucFanParameters & 2283 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2284 rdev->pm.int_thermal_type = THERMAL_TYPE_RV770; 2285 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) { 2286 DRM_INFO("Internal thermal controller %s fan control\n", 2287 (controller->ucFanParameters & 2288 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2289 rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN; 2290 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) { 2291 DRM_INFO("Internal thermal controller %s fan control\n", 2292 (controller->ucFanParameters & 2293 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2294 rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO; 2295 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) { 2296 DRM_INFO("Internal thermal controller %s fan control\n", 2297 (controller->ucFanParameters & 2298 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2299 rdev->pm.int_thermal_type = THERMAL_TYPE_NI; 2300 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SISLANDS) { 2301 DRM_INFO("Internal thermal controller %s fan control\n", 2302 (controller->ucFanParameters & 2303 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2304 rdev->pm.int_thermal_type = THERMAL_TYPE_SI; 2305 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_CISLANDS) { 2306 DRM_INFO("Internal thermal controller %s fan control\n", 2307 (controller->ucFanParameters & 2308 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2309 rdev->pm.int_thermal_type = THERMAL_TYPE_CI; 2310 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_KAVERI) { 2311 DRM_INFO("Internal thermal controller %s fan control\n", 2312 (controller->ucFanParameters & 2313 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2314 rdev->pm.int_thermal_type = THERMAL_TYPE_KV; 2315 } else if (controller->ucType == 2316 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) { 2317 DRM_INFO("External GPIO thermal controller %s fan control\n", 2318 (controller->ucFanParameters & 2319 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2320 rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL_GPIO; 2321 } else if (controller->ucType == 2322 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) { 2323 DRM_INFO("ADT7473 with internal thermal controller %s fan control\n", 2324 (controller->ucFanParameters & 2325 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2326 rdev->pm.int_thermal_type = THERMAL_TYPE_ADT7473_WITH_INTERNAL; 2327 } else if (controller->ucType == 2328 ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL) { 2329 DRM_INFO("EMC2103 with internal thermal controller %s fan control\n", 2330 (controller->ucFanParameters & 2331 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2332 rdev->pm.int_thermal_type = THERMAL_TYPE_EMC2103_WITH_INTERNAL; 2333 } else if (controller->ucType < ARRAY_SIZE(pp_lib_thermal_controller_names)) { 2334 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n", 2335 pp_lib_thermal_controller_names[controller->ucType], 2336 controller->ucI2cAddress >> 1, 2337 (controller->ucFanParameters & 2338 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2339 rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL; 2340 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine); 2341 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 2342 if (rdev->pm.i2c_bus) { 2343 struct i2c_board_info info = { }; 2344 const char *name = pp_lib_thermal_controller_names[controller->ucType]; 2345 info.addr = controller->ucI2cAddress >> 1; 2346 strlcpy(info.type, name, sizeof(info.type)); 2347 i2c_new_client_device(&rdev->pm.i2c_bus->adapter, &info); 2348 } 2349 } else { 2350 DRM_INFO("Unknown thermal controller type %d at 0x%02x %s fan control\n", 2351 controller->ucType, 2352 controller->ucI2cAddress >> 1, 2353 (controller->ucFanParameters & 2354 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2355 } 2356 } 2357 } 2358 2359 void radeon_atombios_get_default_voltages(struct radeon_device *rdev, 2360 u16 *vddc, u16 *vddci, u16 *mvdd) 2361 { 2362 struct radeon_mode_info *mode_info = &rdev->mode_info; 2363 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); 2364 u8 frev, crev; 2365 u16 data_offset; 2366 union firmware_info *firmware_info; 2367 2368 *vddc = 0; 2369 *vddci = 0; 2370 *mvdd = 0; 2371 2372 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 2373 &frev, &crev, &data_offset)) { 2374 firmware_info = 2375 (union firmware_info *)(mode_info->atom_context->bios + 2376 data_offset); 2377 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage); 2378 if ((frev == 2) && (crev >= 2)) { 2379 *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage); 2380 *mvdd = le16_to_cpu(firmware_info->info_22.usBootUpMVDDCVoltage); 2381 } 2382 } 2383 } 2384 2385 static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev, 2386 int state_index, int mode_index, 2387 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info) 2388 { 2389 int j; 2390 u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings); 2391 u32 misc2 = le16_to_cpu(non_clock_info->usClassification); 2392 u16 vddc, vddci, mvdd; 2393 2394 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd); 2395 2396 rdev->pm.power_state[state_index].misc = misc; 2397 rdev->pm.power_state[state_index].misc2 = misc2; 2398 rdev->pm.power_state[state_index].pcie_lanes = 2399 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> 2400 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; 2401 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) { 2402 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY: 2403 rdev->pm.power_state[state_index].type = 2404 POWER_STATE_TYPE_BATTERY; 2405 break; 2406 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED: 2407 rdev->pm.power_state[state_index].type = 2408 POWER_STATE_TYPE_BALANCED; 2409 break; 2410 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE: 2411 rdev->pm.power_state[state_index].type = 2412 POWER_STATE_TYPE_PERFORMANCE; 2413 break; 2414 case ATOM_PPLIB_CLASSIFICATION_UI_NONE: 2415 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE) 2416 rdev->pm.power_state[state_index].type = 2417 POWER_STATE_TYPE_PERFORMANCE; 2418 break; 2419 } 2420 rdev->pm.power_state[state_index].flags = 0; 2421 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) 2422 rdev->pm.power_state[state_index].flags |= 2423 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2424 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) { 2425 rdev->pm.power_state[state_index].type = 2426 POWER_STATE_TYPE_DEFAULT; 2427 rdev->pm.default_power_state_index = state_index; 2428 rdev->pm.power_state[state_index].default_clock_mode = 2429 &rdev->pm.power_state[state_index].clock_info[mode_index - 1]; 2430 if ((rdev->family >= CHIP_BARTS) && !(rdev->flags & RADEON_IS_IGP)) { 2431 /* NI chips post without MC ucode, so default clocks are strobe mode only */ 2432 rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk; 2433 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk; 2434 rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage; 2435 rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci; 2436 } else { 2437 u16 max_vddci = 0; 2438 2439 if (ASIC_IS_DCE4(rdev)) 2440 radeon_atom_get_max_voltage(rdev, 2441 SET_VOLTAGE_TYPE_ASIC_VDDCI, 2442 &max_vddci); 2443 /* patch the table values with the default sclk/mclk from firmware info */ 2444 for (j = 0; j < mode_index; j++) { 2445 rdev->pm.power_state[state_index].clock_info[j].mclk = 2446 rdev->clock.default_mclk; 2447 rdev->pm.power_state[state_index].clock_info[j].sclk = 2448 rdev->clock.default_sclk; 2449 if (vddc) 2450 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage = 2451 vddc; 2452 if (max_vddci) 2453 rdev->pm.power_state[state_index].clock_info[j].voltage.vddci = 2454 max_vddci; 2455 } 2456 } 2457 } 2458 } 2459 2460 static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev, 2461 int state_index, int mode_index, 2462 union pplib_clock_info *clock_info) 2463 { 2464 u32 sclk, mclk; 2465 u16 vddc; 2466 2467 if (rdev->flags & RADEON_IS_IGP) { 2468 if (rdev->family >= CHIP_PALM) { 2469 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow); 2470 sclk |= clock_info->sumo.ucEngineClockHigh << 16; 2471 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2472 } else { 2473 sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow); 2474 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16; 2475 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2476 } 2477 } else if (rdev->family >= CHIP_BONAIRE) { 2478 sclk = le16_to_cpu(clock_info->ci.usEngineClockLow); 2479 sclk |= clock_info->ci.ucEngineClockHigh << 16; 2480 mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow); 2481 mclk |= clock_info->ci.ucMemoryClockHigh << 16; 2482 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk; 2483 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2484 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = 2485 VOLTAGE_NONE; 2486 } else if (rdev->family >= CHIP_TAHITI) { 2487 sclk = le16_to_cpu(clock_info->si.usEngineClockLow); 2488 sclk |= clock_info->si.ucEngineClockHigh << 16; 2489 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); 2490 mclk |= clock_info->si.ucMemoryClockHigh << 16; 2491 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk; 2492 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2493 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = 2494 VOLTAGE_SW; 2495 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = 2496 le16_to_cpu(clock_info->si.usVDDC); 2497 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci = 2498 le16_to_cpu(clock_info->si.usVDDCI); 2499 } else if (rdev->family >= CHIP_CEDAR) { 2500 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow); 2501 sclk |= clock_info->evergreen.ucEngineClockHigh << 16; 2502 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow); 2503 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16; 2504 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk; 2505 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2506 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = 2507 VOLTAGE_SW; 2508 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = 2509 le16_to_cpu(clock_info->evergreen.usVDDC); 2510 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci = 2511 le16_to_cpu(clock_info->evergreen.usVDDCI); 2512 } else { 2513 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow); 2514 sclk |= clock_info->r600.ucEngineClockHigh << 16; 2515 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow); 2516 mclk |= clock_info->r600.ucMemoryClockHigh << 16; 2517 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk; 2518 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2519 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = 2520 VOLTAGE_SW; 2521 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = 2522 le16_to_cpu(clock_info->r600.usVDDC); 2523 } 2524 2525 /* patch up vddc if necessary */ 2526 switch (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage) { 2527 case ATOM_VIRTUAL_VOLTAGE_ID0: 2528 case ATOM_VIRTUAL_VOLTAGE_ID1: 2529 case ATOM_VIRTUAL_VOLTAGE_ID2: 2530 case ATOM_VIRTUAL_VOLTAGE_ID3: 2531 case ATOM_VIRTUAL_VOLTAGE_ID4: 2532 case ATOM_VIRTUAL_VOLTAGE_ID5: 2533 case ATOM_VIRTUAL_VOLTAGE_ID6: 2534 case ATOM_VIRTUAL_VOLTAGE_ID7: 2535 if (radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC, 2536 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage, 2537 &vddc) == 0) 2538 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc; 2539 break; 2540 default: 2541 break; 2542 } 2543 2544 if (rdev->flags & RADEON_IS_IGP) { 2545 /* skip invalid modes */ 2546 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0) 2547 return false; 2548 } else { 2549 /* skip invalid modes */ 2550 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) || 2551 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)) 2552 return false; 2553 } 2554 return true; 2555 } 2556 2557 static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev) 2558 { 2559 struct radeon_mode_info *mode_info = &rdev->mode_info; 2560 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 2561 union pplib_power_state *power_state; 2562 int i, j; 2563 int state_index = 0, mode_index = 0; 2564 union pplib_clock_info *clock_info; 2565 bool valid; 2566 union power_info *power_info; 2567 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 2568 u16 data_offset; 2569 u8 frev, crev; 2570 2571 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 2572 &frev, &crev, &data_offset)) 2573 return state_index; 2574 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 2575 2576 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController); 2577 if (power_info->pplib.ucNumStates == 0) 2578 return state_index; 2579 rdev->pm.power_state = kcalloc(power_info->pplib.ucNumStates, 2580 sizeof(struct radeon_power_state), 2581 GFP_KERNEL); 2582 if (!rdev->pm.power_state) 2583 return state_index; 2584 /* first mode is usually default, followed by low to high */ 2585 for (i = 0; i < power_info->pplib.ucNumStates; i++) { 2586 mode_index = 0; 2587 power_state = (union pplib_power_state *) 2588 (mode_info->atom_context->bios + data_offset + 2589 le16_to_cpu(power_info->pplib.usStateArrayOffset) + 2590 i * power_info->pplib.ucStateEntrySize); 2591 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 2592 (mode_info->atom_context->bios + data_offset + 2593 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) + 2594 (power_state->v1.ucNonClockStateIndex * 2595 power_info->pplib.ucNonClockSize)); 2596 rdev->pm.power_state[i].clock_info = 2597 kcalloc((power_info->pplib.ucStateEntrySize - 1) ? 2598 (power_info->pplib.ucStateEntrySize - 1) : 1, 2599 sizeof(struct radeon_pm_clock_info), 2600 GFP_KERNEL); 2601 if (!rdev->pm.power_state[i].clock_info) 2602 return state_index; 2603 if (power_info->pplib.ucStateEntrySize - 1) { 2604 for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) { 2605 clock_info = (union pplib_clock_info *) 2606 (mode_info->atom_context->bios + data_offset + 2607 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) + 2608 (power_state->v1.ucClockStateIndices[j] * 2609 power_info->pplib.ucClockInfoSize)); 2610 valid = radeon_atombios_parse_pplib_clock_info(rdev, 2611 state_index, mode_index, 2612 clock_info); 2613 if (valid) 2614 mode_index++; 2615 } 2616 } else { 2617 rdev->pm.power_state[state_index].clock_info[0].mclk = 2618 rdev->clock.default_mclk; 2619 rdev->pm.power_state[state_index].clock_info[0].sclk = 2620 rdev->clock.default_sclk; 2621 mode_index++; 2622 } 2623 rdev->pm.power_state[state_index].num_clock_modes = mode_index; 2624 if (mode_index) { 2625 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index, 2626 non_clock_info); 2627 state_index++; 2628 } 2629 } 2630 /* if multiple clock modes, mark the lowest as no display */ 2631 for (i = 0; i < state_index; i++) { 2632 if (rdev->pm.power_state[i].num_clock_modes > 1) 2633 rdev->pm.power_state[i].clock_info[0].flags |= 2634 RADEON_PM_MODE_NO_DISPLAY; 2635 } 2636 /* first mode is usually default */ 2637 if (rdev->pm.default_power_state_index == -1) { 2638 rdev->pm.power_state[0].type = 2639 POWER_STATE_TYPE_DEFAULT; 2640 rdev->pm.default_power_state_index = 0; 2641 rdev->pm.power_state[0].default_clock_mode = 2642 &rdev->pm.power_state[0].clock_info[0]; 2643 } 2644 return state_index; 2645 } 2646 2647 static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev) 2648 { 2649 struct radeon_mode_info *mode_info = &rdev->mode_info; 2650 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 2651 union pplib_power_state *power_state; 2652 int i, j, non_clock_array_index, clock_array_index; 2653 int state_index = 0, mode_index = 0; 2654 union pplib_clock_info *clock_info; 2655 struct _StateArray *state_array; 2656 struct _ClockInfoArray *clock_info_array; 2657 struct _NonClockInfoArray *non_clock_info_array; 2658 bool valid; 2659 union power_info *power_info; 2660 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 2661 u16 data_offset; 2662 u8 frev, crev; 2663 u8 *power_state_offset; 2664 2665 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 2666 &frev, &crev, &data_offset)) 2667 return state_index; 2668 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 2669 2670 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController); 2671 state_array = (struct _StateArray *) 2672 (mode_info->atom_context->bios + data_offset + 2673 le16_to_cpu(power_info->pplib.usStateArrayOffset)); 2674 clock_info_array = (struct _ClockInfoArray *) 2675 (mode_info->atom_context->bios + data_offset + 2676 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); 2677 non_clock_info_array = (struct _NonClockInfoArray *) 2678 (mode_info->atom_context->bios + data_offset + 2679 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); 2680 if (state_array->ucNumEntries == 0) 2681 return state_index; 2682 rdev->pm.power_state = kcalloc(state_array->ucNumEntries, 2683 sizeof(struct radeon_power_state), 2684 GFP_KERNEL); 2685 if (!rdev->pm.power_state) 2686 return state_index; 2687 power_state_offset = (u8 *)state_array->states; 2688 for (i = 0; i < state_array->ucNumEntries; i++) { 2689 mode_index = 0; 2690 power_state = (union pplib_power_state *)power_state_offset; 2691 non_clock_array_index = power_state->v2.nonClockInfoIndex; 2692 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 2693 &non_clock_info_array->nonClockInfo[non_clock_array_index]; 2694 rdev->pm.power_state[i].clock_info = 2695 kcalloc(power_state->v2.ucNumDPMLevels ? 2696 power_state->v2.ucNumDPMLevels : 1, 2697 sizeof(struct radeon_pm_clock_info), 2698 GFP_KERNEL); 2699 if (!rdev->pm.power_state[i].clock_info) 2700 return state_index; 2701 if (power_state->v2.ucNumDPMLevels) { 2702 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { 2703 clock_array_index = power_state->v2.clockInfoIndex[j]; 2704 clock_info = (union pplib_clock_info *) 2705 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; 2706 valid = radeon_atombios_parse_pplib_clock_info(rdev, 2707 state_index, mode_index, 2708 clock_info); 2709 if (valid) 2710 mode_index++; 2711 } 2712 } else { 2713 rdev->pm.power_state[state_index].clock_info[0].mclk = 2714 rdev->clock.default_mclk; 2715 rdev->pm.power_state[state_index].clock_info[0].sclk = 2716 rdev->clock.default_sclk; 2717 mode_index++; 2718 } 2719 rdev->pm.power_state[state_index].num_clock_modes = mode_index; 2720 if (mode_index) { 2721 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index, 2722 non_clock_info); 2723 state_index++; 2724 } 2725 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; 2726 } 2727 /* if multiple clock modes, mark the lowest as no display */ 2728 for (i = 0; i < state_index; i++) { 2729 if (rdev->pm.power_state[i].num_clock_modes > 1) 2730 rdev->pm.power_state[i].clock_info[0].flags |= 2731 RADEON_PM_MODE_NO_DISPLAY; 2732 } 2733 /* first mode is usually default */ 2734 if (rdev->pm.default_power_state_index == -1) { 2735 rdev->pm.power_state[0].type = 2736 POWER_STATE_TYPE_DEFAULT; 2737 rdev->pm.default_power_state_index = 0; 2738 rdev->pm.power_state[0].default_clock_mode = 2739 &rdev->pm.power_state[0].clock_info[0]; 2740 } 2741 return state_index; 2742 } 2743 2744 void radeon_atombios_get_power_modes(struct radeon_device *rdev) 2745 { 2746 struct radeon_mode_info *mode_info = &rdev->mode_info; 2747 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 2748 u16 data_offset; 2749 u8 frev, crev; 2750 int state_index = 0; 2751 2752 rdev->pm.default_power_state_index = -1; 2753 2754 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 2755 &frev, &crev, &data_offset)) { 2756 switch (frev) { 2757 case 1: 2758 case 2: 2759 case 3: 2760 state_index = radeon_atombios_parse_power_table_1_3(rdev); 2761 break; 2762 case 4: 2763 case 5: 2764 state_index = radeon_atombios_parse_power_table_4_5(rdev); 2765 break; 2766 case 6: 2767 state_index = radeon_atombios_parse_power_table_6(rdev); 2768 break; 2769 default: 2770 break; 2771 } 2772 } 2773 2774 if (state_index == 0) { 2775 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL); 2776 if (rdev->pm.power_state) { 2777 rdev->pm.power_state[0].clock_info = 2778 kcalloc(1, 2779 sizeof(struct radeon_pm_clock_info), 2780 GFP_KERNEL); 2781 if (rdev->pm.power_state[0].clock_info) { 2782 /* add the default mode */ 2783 rdev->pm.power_state[state_index].type = 2784 POWER_STATE_TYPE_DEFAULT; 2785 rdev->pm.power_state[state_index].num_clock_modes = 1; 2786 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk; 2787 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk; 2788 rdev->pm.power_state[state_index].default_clock_mode = 2789 &rdev->pm.power_state[state_index].clock_info[0]; 2790 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; 2791 rdev->pm.power_state[state_index].pcie_lanes = 16; 2792 rdev->pm.default_power_state_index = state_index; 2793 rdev->pm.power_state[state_index].flags = 0; 2794 state_index++; 2795 } 2796 } 2797 } 2798 2799 rdev->pm.num_power_states = state_index; 2800 2801 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; 2802 rdev->pm.current_clock_mode_index = 0; 2803 if (rdev->pm.default_power_state_index >= 0) 2804 rdev->pm.current_vddc = 2805 rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage; 2806 else 2807 rdev->pm.current_vddc = 0; 2808 } 2809 2810 union get_clock_dividers { 2811 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1; 2812 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2; 2813 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3; 2814 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4; 2815 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5; 2816 struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in; 2817 struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out; 2818 }; 2819 2820 int radeon_atom_get_clock_dividers(struct radeon_device *rdev, 2821 u8 clock_type, 2822 u32 clock, 2823 bool strobe_mode, 2824 struct atom_clock_dividers *dividers) 2825 { 2826 union get_clock_dividers args; 2827 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL); 2828 u8 frev, crev; 2829 2830 memset(&args, 0, sizeof(args)); 2831 memset(dividers, 0, sizeof(struct atom_clock_dividers)); 2832 2833 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 2834 return -EINVAL; 2835 2836 switch (crev) { 2837 case 1: 2838 /* r4xx, r5xx */ 2839 args.v1.ucAction = clock_type; 2840 args.v1.ulClock = cpu_to_le32(clock); /* 10 khz */ 2841 2842 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2843 2844 dividers->post_div = args.v1.ucPostDiv; 2845 dividers->fb_div = args.v1.ucFbDiv; 2846 dividers->enable_post_div = true; 2847 break; 2848 case 2: 2849 case 3: 2850 case 5: 2851 /* r6xx, r7xx, evergreen, ni, si */ 2852 if (rdev->family <= CHIP_RV770) { 2853 args.v2.ucAction = clock_type; 2854 args.v2.ulClock = cpu_to_le32(clock); /* 10 khz */ 2855 2856 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2857 2858 dividers->post_div = args.v2.ucPostDiv; 2859 dividers->fb_div = le16_to_cpu(args.v2.usFbDiv); 2860 dividers->ref_div = args.v2.ucAction; 2861 if (rdev->family == CHIP_RV770) { 2862 dividers->enable_post_div = (le32_to_cpu(args.v2.ulClock) & (1 << 24)) ? 2863 true : false; 2864 dividers->vco_mode = (le32_to_cpu(args.v2.ulClock) & (1 << 25)) ? 1 : 0; 2865 } else 2866 dividers->enable_post_div = (dividers->fb_div & 1) ? true : false; 2867 } else { 2868 if (clock_type == COMPUTE_ENGINE_PLL_PARAM) { 2869 args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock); 2870 2871 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2872 2873 dividers->post_div = args.v3.ucPostDiv; 2874 dividers->enable_post_div = (args.v3.ucCntlFlag & 2875 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false; 2876 dividers->enable_dithen = (args.v3.ucCntlFlag & 2877 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true; 2878 dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv); 2879 dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac); 2880 dividers->ref_div = args.v3.ucRefDiv; 2881 dividers->vco_mode = (args.v3.ucCntlFlag & 2882 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0; 2883 } else { 2884 /* for SI we use ComputeMemoryClockParam for memory plls */ 2885 if (rdev->family >= CHIP_TAHITI) 2886 return -EINVAL; 2887 args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock); 2888 if (strobe_mode) 2889 args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN; 2890 2891 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2892 2893 dividers->post_div = args.v5.ucPostDiv; 2894 dividers->enable_post_div = (args.v5.ucCntlFlag & 2895 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false; 2896 dividers->enable_dithen = (args.v5.ucCntlFlag & 2897 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true; 2898 dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv); 2899 dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac); 2900 dividers->ref_div = args.v5.ucRefDiv; 2901 dividers->vco_mode = (args.v5.ucCntlFlag & 2902 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0; 2903 } 2904 } 2905 break; 2906 case 4: 2907 /* fusion */ 2908 args.v4.ulClock = cpu_to_le32(clock); /* 10 khz */ 2909 2910 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2911 2912 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv; 2913 dividers->real_clock = le32_to_cpu(args.v4.ulClock); 2914 break; 2915 case 6: 2916 /* CI */ 2917 /* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, COMPUTE_GPUCLK_INPUT_FLAG_SCLK */ 2918 args.v6_in.ulClock.ulComputeClockFlag = clock_type; 2919 args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */ 2920 2921 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2922 2923 dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv); 2924 dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac); 2925 dividers->ref_div = args.v6_out.ucPllRefDiv; 2926 dividers->post_div = args.v6_out.ucPllPostDiv; 2927 dividers->flags = args.v6_out.ucPllCntlFlag; 2928 dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock); 2929 dividers->post_divider = args.v6_out.ulClock.ucPostDiv; 2930 break; 2931 default: 2932 return -EINVAL; 2933 } 2934 return 0; 2935 } 2936 2937 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev, 2938 u32 clock, 2939 bool strobe_mode, 2940 struct atom_mpll_param *mpll_param) 2941 { 2942 COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 args; 2943 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam); 2944 u8 frev, crev; 2945 2946 memset(&args, 0, sizeof(args)); 2947 memset(mpll_param, 0, sizeof(struct atom_mpll_param)); 2948 2949 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 2950 return -EINVAL; 2951 2952 switch (frev) { 2953 case 2: 2954 switch (crev) { 2955 case 1: 2956 /* SI */ 2957 args.ulClock = cpu_to_le32(clock); /* 10 khz */ 2958 args.ucInputFlag = 0; 2959 if (strobe_mode) 2960 args.ucInputFlag |= MPLL_INPUT_FLAG_STROBE_MODE_EN; 2961 2962 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2963 2964 mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac); 2965 mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv); 2966 mpll_param->post_div = args.ucPostDiv; 2967 mpll_param->dll_speed = args.ucDllSpeed; 2968 mpll_param->bwcntl = args.ucBWCntl; 2969 mpll_param->vco_mode = 2970 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK); 2971 mpll_param->yclk_sel = 2972 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0; 2973 mpll_param->qdr = 2974 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_QDR_ENABLE) ? 1 : 0; 2975 mpll_param->half_rate = 2976 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_AD_HALF_RATE) ? 1 : 0; 2977 break; 2978 default: 2979 return -EINVAL; 2980 } 2981 break; 2982 default: 2983 return -EINVAL; 2984 } 2985 return 0; 2986 } 2987 2988 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable) 2989 { 2990 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args; 2991 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating); 2992 2993 args.ucEnable = enable; 2994 2995 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2996 } 2997 2998 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev) 2999 { 3000 GET_ENGINE_CLOCK_PS_ALLOCATION args; 3001 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock); 3002 3003 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3004 return le32_to_cpu(args.ulReturnEngineClock); 3005 } 3006 3007 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev) 3008 { 3009 GET_MEMORY_CLOCK_PS_ALLOCATION args; 3010 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock); 3011 3012 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3013 return le32_to_cpu(args.ulReturnMemoryClock); 3014 } 3015 3016 void radeon_atom_set_engine_clock(struct radeon_device *rdev, 3017 uint32_t eng_clock) 3018 { 3019 SET_ENGINE_CLOCK_PS_ALLOCATION args; 3020 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock); 3021 3022 args.ulTargetEngineClock = cpu_to_le32(eng_clock); /* 10 khz */ 3023 3024 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3025 } 3026 3027 void radeon_atom_set_memory_clock(struct radeon_device *rdev, 3028 uint32_t mem_clock) 3029 { 3030 SET_MEMORY_CLOCK_PS_ALLOCATION args; 3031 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock); 3032 3033 if (rdev->flags & RADEON_IS_IGP) 3034 return; 3035 3036 args.ulTargetMemoryClock = cpu_to_le32(mem_clock); /* 10 khz */ 3037 3038 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3039 } 3040 3041 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev, 3042 u32 eng_clock, u32 mem_clock) 3043 { 3044 SET_ENGINE_CLOCK_PS_ALLOCATION args; 3045 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings); 3046 u32 tmp; 3047 3048 memset(&args, 0, sizeof(args)); 3049 3050 tmp = eng_clock & SET_CLOCK_FREQ_MASK; 3051 tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24); 3052 3053 args.ulTargetEngineClock = cpu_to_le32(tmp); 3054 if (mem_clock) 3055 args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK); 3056 3057 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3058 } 3059 3060 void radeon_atom_update_memory_dll(struct radeon_device *rdev, 3061 u32 mem_clock) 3062 { 3063 u32 args; 3064 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings); 3065 3066 args = cpu_to_le32(mem_clock); /* 10 khz */ 3067 3068 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3069 } 3070 3071 void radeon_atom_set_ac_timing(struct radeon_device *rdev, 3072 u32 mem_clock) 3073 { 3074 SET_MEMORY_CLOCK_PS_ALLOCATION args; 3075 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings); 3076 u32 tmp = mem_clock | (COMPUTE_MEMORY_PLL_PARAM << 24); 3077 3078 args.ulTargetMemoryClock = cpu_to_le32(tmp); /* 10 khz */ 3079 3080 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3081 } 3082 3083 union set_voltage { 3084 struct _SET_VOLTAGE_PS_ALLOCATION alloc; 3085 struct _SET_VOLTAGE_PARAMETERS v1; 3086 struct _SET_VOLTAGE_PARAMETERS_V2 v2; 3087 struct _SET_VOLTAGE_PARAMETERS_V1_3 v3; 3088 }; 3089 3090 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type) 3091 { 3092 union set_voltage args; 3093 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); 3094 u8 frev, crev, volt_index = voltage_level; 3095 3096 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 3097 return; 3098 3099 /* 0xff01 is a flag rather then an actual voltage */ 3100 if (voltage_level == 0xff01) 3101 return; 3102 3103 switch (crev) { 3104 case 1: 3105 args.v1.ucVoltageType = voltage_type; 3106 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE; 3107 args.v1.ucVoltageIndex = volt_index; 3108 break; 3109 case 2: 3110 args.v2.ucVoltageType = voltage_type; 3111 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE; 3112 args.v2.usVoltageLevel = cpu_to_le16(voltage_level); 3113 break; 3114 case 3: 3115 args.v3.ucVoltageType = voltage_type; 3116 args.v3.ucVoltageMode = ATOM_SET_VOLTAGE; 3117 args.v3.usVoltageLevel = cpu_to_le16(voltage_level); 3118 break; 3119 default: 3120 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3121 return; 3122 } 3123 3124 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3125 } 3126 3127 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 3128 u16 voltage_id, u16 *voltage) 3129 { 3130 union set_voltage args; 3131 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); 3132 u8 frev, crev; 3133 3134 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 3135 return -EINVAL; 3136 3137 switch (crev) { 3138 case 1: 3139 return -EINVAL; 3140 case 2: 3141 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE; 3142 args.v2.ucVoltageMode = 0; 3143 args.v2.usVoltageLevel = 0; 3144 3145 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3146 3147 *voltage = le16_to_cpu(args.v2.usVoltageLevel); 3148 break; 3149 case 3: 3150 args.v3.ucVoltageType = voltage_type; 3151 args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL; 3152 args.v3.usVoltageLevel = cpu_to_le16(voltage_id); 3153 3154 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3155 3156 *voltage = le16_to_cpu(args.v3.usVoltageLevel); 3157 break; 3158 default: 3159 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3160 return -EINVAL; 3161 } 3162 3163 return 0; 3164 } 3165 3166 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev, 3167 u16 *voltage, 3168 u16 leakage_idx) 3169 { 3170 return radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC, leakage_idx, voltage); 3171 } 3172 3173 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev, 3174 u16 *leakage_id) 3175 { 3176 union set_voltage args; 3177 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); 3178 u8 frev, crev; 3179 3180 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 3181 return -EINVAL; 3182 3183 switch (crev) { 3184 case 3: 3185 case 4: 3186 args.v3.ucVoltageType = 0; 3187 args.v3.ucVoltageMode = ATOM_GET_LEAKAGE_ID; 3188 args.v3.usVoltageLevel = 0; 3189 3190 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3191 3192 *leakage_id = le16_to_cpu(args.v3.usVoltageLevel); 3193 break; 3194 default: 3195 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3196 return -EINVAL; 3197 } 3198 3199 return 0; 3200 } 3201 3202 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev, 3203 u16 *vddc, u16 *vddci, 3204 u16 virtual_voltage_id, 3205 u16 vbios_voltage_id) 3206 { 3207 int index = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo); 3208 u8 frev, crev; 3209 u16 data_offset, size; 3210 int i, j; 3211 ATOM_ASIC_PROFILING_INFO_V2_1 *profile; 3212 u16 *leakage_bin, *vddc_id_buf, *vddc_buf, *vddci_id_buf, *vddci_buf; 3213 3214 *vddc = 0; 3215 *vddci = 0; 3216 3217 if (!atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3218 &frev, &crev, &data_offset)) 3219 return -EINVAL; 3220 3221 profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *) 3222 (rdev->mode_info.atom_context->bios + data_offset); 3223 3224 switch (frev) { 3225 case 1: 3226 return -EINVAL; 3227 case 2: 3228 switch (crev) { 3229 case 1: 3230 if (size < sizeof(ATOM_ASIC_PROFILING_INFO_V2_1)) 3231 return -EINVAL; 3232 leakage_bin = (u16 *) 3233 (rdev->mode_info.atom_context->bios + data_offset + 3234 le16_to_cpu(profile->usLeakageBinArrayOffset)); 3235 vddc_id_buf = (u16 *) 3236 (rdev->mode_info.atom_context->bios + data_offset + 3237 le16_to_cpu(profile->usElbVDDC_IdArrayOffset)); 3238 vddc_buf = (u16 *) 3239 (rdev->mode_info.atom_context->bios + data_offset + 3240 le16_to_cpu(profile->usElbVDDC_LevelArrayOffset)); 3241 vddci_id_buf = (u16 *) 3242 (rdev->mode_info.atom_context->bios + data_offset + 3243 le16_to_cpu(profile->usElbVDDCI_IdArrayOffset)); 3244 vddci_buf = (u16 *) 3245 (rdev->mode_info.atom_context->bios + data_offset + 3246 le16_to_cpu(profile->usElbVDDCI_LevelArrayOffset)); 3247 3248 if (profile->ucElbVDDC_Num > 0) { 3249 for (i = 0; i < profile->ucElbVDDC_Num; i++) { 3250 if (vddc_id_buf[i] == virtual_voltage_id) { 3251 for (j = 0; j < profile->ucLeakageBinNum; j++) { 3252 if (vbios_voltage_id <= leakage_bin[j]) { 3253 *vddc = vddc_buf[j * profile->ucElbVDDC_Num + i]; 3254 break; 3255 } 3256 } 3257 break; 3258 } 3259 } 3260 } 3261 if (profile->ucElbVDDCI_Num > 0) { 3262 for (i = 0; i < profile->ucElbVDDCI_Num; i++) { 3263 if (vddci_id_buf[i] == virtual_voltage_id) { 3264 for (j = 0; j < profile->ucLeakageBinNum; j++) { 3265 if (vbios_voltage_id <= leakage_bin[j]) { 3266 *vddci = vddci_buf[j * profile->ucElbVDDCI_Num + i]; 3267 break; 3268 } 3269 } 3270 break; 3271 } 3272 } 3273 } 3274 break; 3275 default: 3276 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3277 return -EINVAL; 3278 } 3279 break; 3280 default: 3281 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3282 return -EINVAL; 3283 } 3284 3285 return 0; 3286 } 3287 3288 union get_voltage_info { 3289 struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 in; 3290 struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 evv_out; 3291 }; 3292 3293 int radeon_atom_get_voltage_evv(struct radeon_device *rdev, 3294 u16 virtual_voltage_id, 3295 u16 *voltage) 3296 { 3297 int index = GetIndexIntoMasterTable(COMMAND, GetVoltageInfo); 3298 u32 entry_id; 3299 u32 count = rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; 3300 union get_voltage_info args; 3301 3302 for (entry_id = 0; entry_id < count; entry_id++) { 3303 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v == 3304 virtual_voltage_id) 3305 break; 3306 } 3307 3308 if (entry_id >= count) 3309 return -EINVAL; 3310 3311 args.in.ucVoltageType = VOLTAGE_TYPE_VDDC; 3312 args.in.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE; 3313 args.in.usVoltageLevel = cpu_to_le16(virtual_voltage_id); 3314 args.in.ulSCLKFreq = 3315 cpu_to_le32(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk); 3316 3317 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3318 3319 *voltage = le16_to_cpu(args.evv_out.usVoltageLevel); 3320 3321 return 0; 3322 } 3323 3324 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev, 3325 u16 voltage_level, u8 voltage_type, 3326 u32 *gpio_value, u32 *gpio_mask) 3327 { 3328 union set_voltage args; 3329 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); 3330 u8 frev, crev; 3331 3332 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 3333 return -EINVAL; 3334 3335 switch (crev) { 3336 case 1: 3337 return -EINVAL; 3338 case 2: 3339 args.v2.ucVoltageType = voltage_type; 3340 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK; 3341 args.v2.usVoltageLevel = cpu_to_le16(voltage_level); 3342 3343 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3344 3345 *gpio_mask = le32_to_cpu(*(u32 *)&args.v2); 3346 3347 args.v2.ucVoltageType = voltage_type; 3348 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL; 3349 args.v2.usVoltageLevel = cpu_to_le16(voltage_level); 3350 3351 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3352 3353 *gpio_value = le32_to_cpu(*(u32 *)&args.v2); 3354 break; 3355 default: 3356 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3357 return -EINVAL; 3358 } 3359 3360 return 0; 3361 } 3362 3363 union voltage_object_info { 3364 struct _ATOM_VOLTAGE_OBJECT_INFO v1; 3365 struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2; 3366 struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3; 3367 }; 3368 3369 union voltage_object { 3370 struct _ATOM_VOLTAGE_OBJECT v1; 3371 struct _ATOM_VOLTAGE_OBJECT_V2 v2; 3372 union _ATOM_VOLTAGE_OBJECT_V3 v3; 3373 }; 3374 3375 static ATOM_VOLTAGE_OBJECT *atom_lookup_voltage_object_v1(ATOM_VOLTAGE_OBJECT_INFO *v1, 3376 u8 voltage_type) 3377 { 3378 u32 size = le16_to_cpu(v1->sHeader.usStructureSize); 3379 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO, asVoltageObj[0]); 3380 u8 *start = (u8 *)v1; 3381 3382 while (offset < size) { 3383 ATOM_VOLTAGE_OBJECT *vo = (ATOM_VOLTAGE_OBJECT *)(start + offset); 3384 if (vo->ucVoltageType == voltage_type) 3385 return vo; 3386 offset += offsetof(ATOM_VOLTAGE_OBJECT, asFormula.ucVIDAdjustEntries) + 3387 vo->asFormula.ucNumOfVoltageEntries; 3388 } 3389 return NULL; 3390 } 3391 3392 static ATOM_VOLTAGE_OBJECT_V2 *atom_lookup_voltage_object_v2(ATOM_VOLTAGE_OBJECT_INFO_V2 *v2, 3393 u8 voltage_type) 3394 { 3395 u32 size = le16_to_cpu(v2->sHeader.usStructureSize); 3396 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V2, asVoltageObj[0]); 3397 u8 *start = (u8*)v2; 3398 3399 while (offset < size) { 3400 ATOM_VOLTAGE_OBJECT_V2 *vo = (ATOM_VOLTAGE_OBJECT_V2 *)(start + offset); 3401 if (vo->ucVoltageType == voltage_type) 3402 return vo; 3403 offset += offsetof(ATOM_VOLTAGE_OBJECT_V2, asFormula.asVIDAdjustEntries) + 3404 (vo->asFormula.ucNumOfVoltageEntries * sizeof(VOLTAGE_LUT_ENTRY)); 3405 } 3406 return NULL; 3407 } 3408 3409 static ATOM_VOLTAGE_OBJECT_V3 *atom_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *v3, 3410 u8 voltage_type, u8 voltage_mode) 3411 { 3412 u32 size = le16_to_cpu(v3->sHeader.usStructureSize); 3413 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]); 3414 u8 *start = (u8*)v3; 3415 3416 while (offset < size) { 3417 ATOM_VOLTAGE_OBJECT_V3 *vo = (ATOM_VOLTAGE_OBJECT_V3 *)(start + offset); 3418 if ((vo->asGpioVoltageObj.sHeader.ucVoltageType == voltage_type) && 3419 (vo->asGpioVoltageObj.sHeader.ucVoltageMode == voltage_mode)) 3420 return vo; 3421 offset += le16_to_cpu(vo->asGpioVoltageObj.sHeader.usSize); 3422 } 3423 return NULL; 3424 } 3425 3426 bool 3427 radeon_atom_is_voltage_gpio(struct radeon_device *rdev, 3428 u8 voltage_type, u8 voltage_mode) 3429 { 3430 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); 3431 u8 frev, crev; 3432 u16 data_offset, size; 3433 union voltage_object_info *voltage_info; 3434 union voltage_object *voltage_object = NULL; 3435 3436 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3437 &frev, &crev, &data_offset)) { 3438 voltage_info = (union voltage_object_info *) 3439 (rdev->mode_info.atom_context->bios + data_offset); 3440 3441 switch (frev) { 3442 case 1: 3443 case 2: 3444 switch (crev) { 3445 case 1: 3446 voltage_object = (union voltage_object *) 3447 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type); 3448 if (voltage_object && 3449 (voltage_object->v1.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO)) 3450 return true; 3451 break; 3452 case 2: 3453 voltage_object = (union voltage_object *) 3454 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type); 3455 if (voltage_object && 3456 (voltage_object->v2.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO)) 3457 return true; 3458 break; 3459 default: 3460 DRM_ERROR("unknown voltage object table\n"); 3461 return false; 3462 } 3463 break; 3464 case 3: 3465 switch (crev) { 3466 case 1: 3467 if (atom_lookup_voltage_object_v3(&voltage_info->v3, 3468 voltage_type, voltage_mode)) 3469 return true; 3470 break; 3471 default: 3472 DRM_ERROR("unknown voltage object table\n"); 3473 return false; 3474 } 3475 break; 3476 default: 3477 DRM_ERROR("unknown voltage object table\n"); 3478 return false; 3479 } 3480 3481 } 3482 return false; 3483 } 3484 3485 int radeon_atom_get_svi2_info(struct radeon_device *rdev, 3486 u8 voltage_type, 3487 u8 *svd_gpio_id, u8 *svc_gpio_id) 3488 { 3489 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); 3490 u8 frev, crev; 3491 u16 data_offset, size; 3492 union voltage_object_info *voltage_info; 3493 union voltage_object *voltage_object = NULL; 3494 3495 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3496 &frev, &crev, &data_offset)) { 3497 voltage_info = (union voltage_object_info *) 3498 (rdev->mode_info.atom_context->bios + data_offset); 3499 3500 switch (frev) { 3501 case 3: 3502 switch (crev) { 3503 case 1: 3504 voltage_object = (union voltage_object *) 3505 atom_lookup_voltage_object_v3(&voltage_info->v3, 3506 voltage_type, 3507 VOLTAGE_OBJ_SVID2); 3508 if (voltage_object) { 3509 *svd_gpio_id = voltage_object->v3.asSVID2Obj.ucSVDGpioId; 3510 *svc_gpio_id = voltage_object->v3.asSVID2Obj.ucSVCGpioId; 3511 } else { 3512 return -EINVAL; 3513 } 3514 break; 3515 default: 3516 DRM_ERROR("unknown voltage object table\n"); 3517 return -EINVAL; 3518 } 3519 break; 3520 default: 3521 DRM_ERROR("unknown voltage object table\n"); 3522 return -EINVAL; 3523 } 3524 3525 } 3526 return 0; 3527 } 3528 3529 int radeon_atom_get_max_voltage(struct radeon_device *rdev, 3530 u8 voltage_type, u16 *max_voltage) 3531 { 3532 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); 3533 u8 frev, crev; 3534 u16 data_offset, size; 3535 union voltage_object_info *voltage_info; 3536 union voltage_object *voltage_object = NULL; 3537 3538 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3539 &frev, &crev, &data_offset)) { 3540 voltage_info = (union voltage_object_info *) 3541 (rdev->mode_info.atom_context->bios + data_offset); 3542 3543 switch (crev) { 3544 case 1: 3545 voltage_object = (union voltage_object *) 3546 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type); 3547 if (voltage_object) { 3548 ATOM_VOLTAGE_FORMULA *formula = 3549 &voltage_object->v1.asFormula; 3550 if (formula->ucFlag & 1) 3551 *max_voltage = 3552 le16_to_cpu(formula->usVoltageBaseLevel) + 3553 formula->ucNumOfVoltageEntries / 2 * 3554 le16_to_cpu(formula->usVoltageStep); 3555 else 3556 *max_voltage = 3557 le16_to_cpu(formula->usVoltageBaseLevel) + 3558 (formula->ucNumOfVoltageEntries - 1) * 3559 le16_to_cpu(formula->usVoltageStep); 3560 return 0; 3561 } 3562 break; 3563 case 2: 3564 voltage_object = (union voltage_object *) 3565 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type); 3566 if (voltage_object) { 3567 ATOM_VOLTAGE_FORMULA_V2 *formula = 3568 &voltage_object->v2.asFormula; 3569 if (formula->ucNumOfVoltageEntries) { 3570 VOLTAGE_LUT_ENTRY *lut = (VOLTAGE_LUT_ENTRY *) 3571 ((u8 *)&formula->asVIDAdjustEntries[0] + 3572 (sizeof(VOLTAGE_LUT_ENTRY) * (formula->ucNumOfVoltageEntries - 1))); 3573 *max_voltage = 3574 le16_to_cpu(lut->usVoltageValue); 3575 return 0; 3576 } 3577 } 3578 break; 3579 default: 3580 DRM_ERROR("unknown voltage object table\n"); 3581 return -EINVAL; 3582 } 3583 3584 } 3585 return -EINVAL; 3586 } 3587 3588 int radeon_atom_get_min_voltage(struct radeon_device *rdev, 3589 u8 voltage_type, u16 *min_voltage) 3590 { 3591 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); 3592 u8 frev, crev; 3593 u16 data_offset, size; 3594 union voltage_object_info *voltage_info; 3595 union voltage_object *voltage_object = NULL; 3596 3597 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3598 &frev, &crev, &data_offset)) { 3599 voltage_info = (union voltage_object_info *) 3600 (rdev->mode_info.atom_context->bios + data_offset); 3601 3602 switch (crev) { 3603 case 1: 3604 voltage_object = (union voltage_object *) 3605 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type); 3606 if (voltage_object) { 3607 ATOM_VOLTAGE_FORMULA *formula = 3608 &voltage_object->v1.asFormula; 3609 *min_voltage = 3610 le16_to_cpu(formula->usVoltageBaseLevel); 3611 return 0; 3612 } 3613 break; 3614 case 2: 3615 voltage_object = (union voltage_object *) 3616 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type); 3617 if (voltage_object) { 3618 ATOM_VOLTAGE_FORMULA_V2 *formula = 3619 &voltage_object->v2.asFormula; 3620 if (formula->ucNumOfVoltageEntries) { 3621 *min_voltage = 3622 le16_to_cpu(formula->asVIDAdjustEntries[ 3623 0 3624 ].usVoltageValue); 3625 return 0; 3626 } 3627 } 3628 break; 3629 default: 3630 DRM_ERROR("unknown voltage object table\n"); 3631 return -EINVAL; 3632 } 3633 3634 } 3635 return -EINVAL; 3636 } 3637 3638 int radeon_atom_get_voltage_step(struct radeon_device *rdev, 3639 u8 voltage_type, u16 *voltage_step) 3640 { 3641 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); 3642 u8 frev, crev; 3643 u16 data_offset, size; 3644 union voltage_object_info *voltage_info; 3645 union voltage_object *voltage_object = NULL; 3646 3647 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3648 &frev, &crev, &data_offset)) { 3649 voltage_info = (union voltage_object_info *) 3650 (rdev->mode_info.atom_context->bios + data_offset); 3651 3652 switch (crev) { 3653 case 1: 3654 voltage_object = (union voltage_object *) 3655 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type); 3656 if (voltage_object) { 3657 ATOM_VOLTAGE_FORMULA *formula = 3658 &voltage_object->v1.asFormula; 3659 if (formula->ucFlag & 1) 3660 *voltage_step = 3661 (le16_to_cpu(formula->usVoltageStep) + 1) / 2; 3662 else 3663 *voltage_step = 3664 le16_to_cpu(formula->usVoltageStep); 3665 return 0; 3666 } 3667 break; 3668 case 2: 3669 return -EINVAL; 3670 default: 3671 DRM_ERROR("unknown voltage object table\n"); 3672 return -EINVAL; 3673 } 3674 3675 } 3676 return -EINVAL; 3677 } 3678 3679 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev, 3680 u8 voltage_type, 3681 u16 nominal_voltage, 3682 u16 *true_voltage) 3683 { 3684 u16 min_voltage, max_voltage, voltage_step; 3685 3686 if (radeon_atom_get_max_voltage(rdev, voltage_type, &max_voltage)) 3687 return -EINVAL; 3688 if (radeon_atom_get_min_voltage(rdev, voltage_type, &min_voltage)) 3689 return -EINVAL; 3690 if (radeon_atom_get_voltage_step(rdev, voltage_type, &voltage_step)) 3691 return -EINVAL; 3692 3693 if (nominal_voltage <= min_voltage) 3694 *true_voltage = min_voltage; 3695 else if (nominal_voltage >= max_voltage) 3696 *true_voltage = max_voltage; 3697 else 3698 *true_voltage = min_voltage + 3699 ((nominal_voltage - min_voltage) / voltage_step) * 3700 voltage_step; 3701 3702 return 0; 3703 } 3704 3705 int radeon_atom_get_voltage_table(struct radeon_device *rdev, 3706 u8 voltage_type, u8 voltage_mode, 3707 struct atom_voltage_table *voltage_table) 3708 { 3709 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); 3710 u8 frev, crev; 3711 u16 data_offset, size; 3712 int i, ret; 3713 union voltage_object_info *voltage_info; 3714 union voltage_object *voltage_object = NULL; 3715 3716 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3717 &frev, &crev, &data_offset)) { 3718 voltage_info = (union voltage_object_info *) 3719 (rdev->mode_info.atom_context->bios + data_offset); 3720 3721 switch (frev) { 3722 case 1: 3723 case 2: 3724 switch (crev) { 3725 case 1: 3726 DRM_ERROR("old table version %d, %d\n", frev, crev); 3727 return -EINVAL; 3728 case 2: 3729 voltage_object = (union voltage_object *) 3730 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type); 3731 if (voltage_object) { 3732 ATOM_VOLTAGE_FORMULA_V2 *formula = 3733 &voltage_object->v2.asFormula; 3734 VOLTAGE_LUT_ENTRY *lut; 3735 if (formula->ucNumOfVoltageEntries > MAX_VOLTAGE_ENTRIES) 3736 return -EINVAL; 3737 lut = &formula->asVIDAdjustEntries[0]; 3738 for (i = 0; i < formula->ucNumOfVoltageEntries; i++) { 3739 voltage_table->entries[i].value = 3740 le16_to_cpu(lut->usVoltageValue); 3741 ret = radeon_atom_get_voltage_gpio_settings(rdev, 3742 voltage_table->entries[i].value, 3743 voltage_type, 3744 &voltage_table->entries[i].smio_low, 3745 &voltage_table->mask_low); 3746 if (ret) 3747 return ret; 3748 lut = (VOLTAGE_LUT_ENTRY *) 3749 ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY)); 3750 } 3751 voltage_table->count = formula->ucNumOfVoltageEntries; 3752 return 0; 3753 } 3754 break; 3755 default: 3756 DRM_ERROR("unknown voltage object table\n"); 3757 return -EINVAL; 3758 } 3759 break; 3760 case 3: 3761 switch (crev) { 3762 case 1: 3763 voltage_object = (union voltage_object *) 3764 atom_lookup_voltage_object_v3(&voltage_info->v3, 3765 voltage_type, voltage_mode); 3766 if (voltage_object) { 3767 ATOM_GPIO_VOLTAGE_OBJECT_V3 *gpio = 3768 &voltage_object->v3.asGpioVoltageObj; 3769 VOLTAGE_LUT_ENTRY_V2 *lut; 3770 if (gpio->ucGpioEntryNum > MAX_VOLTAGE_ENTRIES) 3771 return -EINVAL; 3772 lut = &gpio->asVolGpioLut[0]; 3773 for (i = 0; i < gpio->ucGpioEntryNum; i++) { 3774 voltage_table->entries[i].value = 3775 le16_to_cpu(lut->usVoltageValue); 3776 voltage_table->entries[i].smio_low = 3777 le32_to_cpu(lut->ulVoltageId); 3778 lut = (VOLTAGE_LUT_ENTRY_V2 *) 3779 ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY_V2)); 3780 } 3781 voltage_table->mask_low = le32_to_cpu(gpio->ulGpioMaskVal); 3782 voltage_table->count = gpio->ucGpioEntryNum; 3783 voltage_table->phase_delay = gpio->ucPhaseDelay; 3784 return 0; 3785 } 3786 break; 3787 default: 3788 DRM_ERROR("unknown voltage object table\n"); 3789 return -EINVAL; 3790 } 3791 break; 3792 default: 3793 DRM_ERROR("unknown voltage object table\n"); 3794 return -EINVAL; 3795 } 3796 } 3797 return -EINVAL; 3798 } 3799 3800 union vram_info { 3801 struct _ATOM_VRAM_INFO_V3 v1_3; 3802 struct _ATOM_VRAM_INFO_V4 v1_4; 3803 struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1; 3804 }; 3805 3806 int radeon_atom_get_memory_info(struct radeon_device *rdev, 3807 u8 module_index, struct atom_memory_info *mem_info) 3808 { 3809 int index = GetIndexIntoMasterTable(DATA, VRAM_Info); 3810 u8 frev, crev, i; 3811 u16 data_offset, size; 3812 union vram_info *vram_info; 3813 3814 memset(mem_info, 0, sizeof(struct atom_memory_info)); 3815 3816 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3817 &frev, &crev, &data_offset)) { 3818 vram_info = (union vram_info *) 3819 (rdev->mode_info.atom_context->bios + data_offset); 3820 switch (frev) { 3821 case 1: 3822 switch (crev) { 3823 case 3: 3824 /* r6xx */ 3825 if (module_index < vram_info->v1_3.ucNumOfVRAMModule) { 3826 ATOM_VRAM_MODULE_V3 *vram_module = 3827 (ATOM_VRAM_MODULE_V3 *)vram_info->v1_3.aVramInfo; 3828 3829 for (i = 0; i < module_index; i++) { 3830 if (le16_to_cpu(vram_module->usSize) == 0) 3831 return -EINVAL; 3832 vram_module = (ATOM_VRAM_MODULE_V3 *) 3833 ((u8 *)vram_module + le16_to_cpu(vram_module->usSize)); 3834 } 3835 mem_info->mem_vendor = vram_module->asMemory.ucMemoryVenderID & 0xf; 3836 mem_info->mem_type = vram_module->asMemory.ucMemoryType & 0xf0; 3837 } else 3838 return -EINVAL; 3839 break; 3840 case 4: 3841 /* r7xx, evergreen */ 3842 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) { 3843 ATOM_VRAM_MODULE_V4 *vram_module = 3844 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo; 3845 3846 for (i = 0; i < module_index; i++) { 3847 if (le16_to_cpu(vram_module->usModuleSize) == 0) 3848 return -EINVAL; 3849 vram_module = (ATOM_VRAM_MODULE_V4 *) 3850 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize)); 3851 } 3852 mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf; 3853 mem_info->mem_type = vram_module->ucMemoryType & 0xf0; 3854 } else 3855 return -EINVAL; 3856 break; 3857 default: 3858 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3859 return -EINVAL; 3860 } 3861 break; 3862 case 2: 3863 switch (crev) { 3864 case 1: 3865 /* ni */ 3866 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) { 3867 ATOM_VRAM_MODULE_V7 *vram_module = 3868 (ATOM_VRAM_MODULE_V7 *)vram_info->v2_1.aVramInfo; 3869 3870 for (i = 0; i < module_index; i++) { 3871 if (le16_to_cpu(vram_module->usModuleSize) == 0) 3872 return -EINVAL; 3873 vram_module = (ATOM_VRAM_MODULE_V7 *) 3874 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize)); 3875 } 3876 mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf; 3877 mem_info->mem_type = vram_module->ucMemoryType & 0xf0; 3878 } else 3879 return -EINVAL; 3880 break; 3881 default: 3882 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3883 return -EINVAL; 3884 } 3885 break; 3886 default: 3887 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3888 return -EINVAL; 3889 } 3890 return 0; 3891 } 3892 return -EINVAL; 3893 } 3894 3895 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev, 3896 bool gddr5, u8 module_index, 3897 struct atom_memory_clock_range_table *mclk_range_table) 3898 { 3899 int index = GetIndexIntoMasterTable(DATA, VRAM_Info); 3900 u8 frev, crev, i; 3901 u16 data_offset, size; 3902 union vram_info *vram_info; 3903 u32 mem_timing_size = gddr5 ? 3904 sizeof(ATOM_MEMORY_TIMING_FORMAT_V2) : sizeof(ATOM_MEMORY_TIMING_FORMAT); 3905 3906 memset(mclk_range_table, 0, sizeof(struct atom_memory_clock_range_table)); 3907 3908 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3909 &frev, &crev, &data_offset)) { 3910 vram_info = (union vram_info *) 3911 (rdev->mode_info.atom_context->bios + data_offset); 3912 switch (frev) { 3913 case 1: 3914 switch (crev) { 3915 case 3: 3916 DRM_ERROR("old table version %d, %d\n", frev, crev); 3917 return -EINVAL; 3918 case 4: 3919 /* r7xx, evergreen */ 3920 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) { 3921 ATOM_VRAM_MODULE_V4 *vram_module = 3922 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo; 3923 ATOM_MEMORY_TIMING_FORMAT *format; 3924 3925 for (i = 0; i < module_index; i++) { 3926 if (le16_to_cpu(vram_module->usModuleSize) == 0) 3927 return -EINVAL; 3928 vram_module = (ATOM_VRAM_MODULE_V4 *) 3929 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize)); 3930 } 3931 mclk_range_table->num_entries = (u8) 3932 ((le16_to_cpu(vram_module->usModuleSize) - offsetof(ATOM_VRAM_MODULE_V4, asMemTiming)) / 3933 mem_timing_size); 3934 format = &vram_module->asMemTiming[0]; 3935 for (i = 0; i < mclk_range_table->num_entries; i++) { 3936 mclk_range_table->mclk[i] = le32_to_cpu(format->ulClkRange); 3937 format = (ATOM_MEMORY_TIMING_FORMAT *) 3938 ((u8 *)format + mem_timing_size); 3939 } 3940 } else 3941 return -EINVAL; 3942 break; 3943 default: 3944 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3945 return -EINVAL; 3946 } 3947 break; 3948 case 2: 3949 DRM_ERROR("new table version %d, %d\n", frev, crev); 3950 return -EINVAL; 3951 default: 3952 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3953 return -EINVAL; 3954 } 3955 return 0; 3956 } 3957 return -EINVAL; 3958 } 3959 3960 #define MEM_ID_MASK 0xff000000 3961 #define MEM_ID_SHIFT 24 3962 #define CLOCK_RANGE_MASK 0x00ffffff 3963 #define CLOCK_RANGE_SHIFT 0 3964 #define LOW_NIBBLE_MASK 0xf 3965 #define DATA_EQU_PREV 0 3966 #define DATA_FROM_TABLE 4 3967 3968 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev, 3969 u8 module_index, 3970 struct atom_mc_reg_table *reg_table) 3971 { 3972 int index = GetIndexIntoMasterTable(DATA, VRAM_Info); 3973 u8 frev, crev, num_entries, t_mem_id, num_ranges = 0; 3974 u32 i = 0, j; 3975 u16 data_offset, size; 3976 union vram_info *vram_info; 3977 3978 memset(reg_table, 0, sizeof(struct atom_mc_reg_table)); 3979 3980 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3981 &frev, &crev, &data_offset)) { 3982 vram_info = (union vram_info *) 3983 (rdev->mode_info.atom_context->bios + data_offset); 3984 switch (frev) { 3985 case 1: 3986 DRM_ERROR("old table version %d, %d\n", frev, crev); 3987 return -EINVAL; 3988 case 2: 3989 switch (crev) { 3990 case 1: 3991 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) { 3992 ATOM_INIT_REG_BLOCK *reg_block = 3993 (ATOM_INIT_REG_BLOCK *) 3994 ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset)); 3995 ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data = 3996 (ATOM_MEMORY_SETTING_DATA_BLOCK *) 3997 ((u8 *)reg_block + (2 * sizeof(u16)) + 3998 le16_to_cpu(reg_block->usRegIndexTblSize)); 3999 ATOM_INIT_REG_INDEX_FORMAT *format = ®_block->asRegIndexBuf[0]; 4000 num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) / 4001 sizeof(ATOM_INIT_REG_INDEX_FORMAT)) - 1; 4002 if (num_entries > VBIOS_MC_REGISTER_ARRAY_SIZE) 4003 return -EINVAL; 4004 while (i < num_entries) { 4005 if (format->ucPreRegDataLength & ACCESS_PLACEHOLDER) 4006 break; 4007 reg_table->mc_reg_address[i].s1 = 4008 (u16)(le16_to_cpu(format->usRegIndex)); 4009 reg_table->mc_reg_address[i].pre_reg_data = 4010 (u8)(format->ucPreRegDataLength); 4011 i++; 4012 format = (ATOM_INIT_REG_INDEX_FORMAT *) 4013 ((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT)); 4014 } 4015 reg_table->last = i; 4016 while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) && 4017 (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) { 4018 t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK) 4019 >> MEM_ID_SHIFT); 4020 if (module_index == t_mem_id) { 4021 reg_table->mc_reg_table_entry[num_ranges].mclk_max = 4022 (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK) 4023 >> CLOCK_RANGE_SHIFT); 4024 for (i = 0, j = 1; i < reg_table->last; i++) { 4025 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) { 4026 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] = 4027 (u32)le32_to_cpu(*((u32 *)reg_data + j)); 4028 j++; 4029 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) { 4030 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] = 4031 reg_table->mc_reg_table_entry[num_ranges].mc_data[i - 1]; 4032 } 4033 } 4034 num_ranges++; 4035 } 4036 reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *) 4037 ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize)); 4038 } 4039 if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) 4040 return -EINVAL; 4041 reg_table->num_entries = num_ranges; 4042 } else 4043 return -EINVAL; 4044 break; 4045 default: 4046 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 4047 return -EINVAL; 4048 } 4049 break; 4050 default: 4051 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 4052 return -EINVAL; 4053 } 4054 return 0; 4055 } 4056 return -EINVAL; 4057 } 4058 4059 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev) 4060 { 4061 struct radeon_device *rdev = dev->dev_private; 4062 uint32_t bios_2_scratch, bios_6_scratch; 4063 4064 if (rdev->family >= CHIP_R600) { 4065 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); 4066 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); 4067 } else { 4068 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); 4069 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 4070 } 4071 4072 /* let the bios control the backlight */ 4073 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE; 4074 4075 /* tell the bios not to handle mode switching */ 4076 bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH; 4077 4078 /* clear the vbios dpms state */ 4079 if (ASIC_IS_DCE4(rdev)) 4080 bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE; 4081 4082 if (rdev->family >= CHIP_R600) { 4083 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); 4084 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); 4085 } else { 4086 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); 4087 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 4088 } 4089 4090 } 4091 4092 void radeon_save_bios_scratch_regs(struct radeon_device *rdev) 4093 { 4094 uint32_t scratch_reg; 4095 int i; 4096 4097 if (rdev->family >= CHIP_R600) 4098 scratch_reg = R600_BIOS_0_SCRATCH; 4099 else 4100 scratch_reg = RADEON_BIOS_0_SCRATCH; 4101 4102 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++) 4103 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4)); 4104 } 4105 4106 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev) 4107 { 4108 uint32_t scratch_reg; 4109 int i; 4110 4111 if (rdev->family >= CHIP_R600) 4112 scratch_reg = R600_BIOS_0_SCRATCH; 4113 else 4114 scratch_reg = RADEON_BIOS_0_SCRATCH; 4115 4116 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++) 4117 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]); 4118 } 4119 4120 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock) 4121 { 4122 struct drm_device *dev = encoder->dev; 4123 struct radeon_device *rdev = dev->dev_private; 4124 uint32_t bios_6_scratch; 4125 4126 if (rdev->family >= CHIP_R600) 4127 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); 4128 else 4129 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 4130 4131 if (lock) { 4132 bios_6_scratch |= ATOM_S6_CRITICAL_STATE; 4133 bios_6_scratch &= ~ATOM_S6_ACC_MODE; 4134 } else { 4135 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE; 4136 bios_6_scratch |= ATOM_S6_ACC_MODE; 4137 } 4138 4139 if (rdev->family >= CHIP_R600) 4140 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); 4141 else 4142 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 4143 } 4144 4145 /* at some point we may want to break this out into individual functions */ 4146 void 4147 radeon_atombios_connected_scratch_regs(struct drm_connector *connector, 4148 struct drm_encoder *encoder, 4149 bool connected) 4150 { 4151 struct drm_device *dev = connector->dev; 4152 struct radeon_device *rdev = dev->dev_private; 4153 struct radeon_connector *radeon_connector = 4154 to_radeon_connector(connector); 4155 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 4156 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch; 4157 4158 if (rdev->family >= CHIP_R600) { 4159 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); 4160 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH); 4161 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); 4162 } else { 4163 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); 4164 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH); 4165 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 4166 } 4167 4168 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) && 4169 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) { 4170 if (connected) { 4171 DRM_DEBUG_KMS("TV1 connected\n"); 4172 bios_3_scratch |= ATOM_S3_TV1_ACTIVE; 4173 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1; 4174 } else { 4175 DRM_DEBUG_KMS("TV1 disconnected\n"); 4176 bios_0_scratch &= ~ATOM_S0_TV1_MASK; 4177 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE; 4178 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1; 4179 } 4180 } 4181 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) && 4182 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) { 4183 if (connected) { 4184 DRM_DEBUG_KMS("CV connected\n"); 4185 bios_3_scratch |= ATOM_S3_CV_ACTIVE; 4186 bios_6_scratch |= ATOM_S6_ACC_REQ_CV; 4187 } else { 4188 DRM_DEBUG_KMS("CV disconnected\n"); 4189 bios_0_scratch &= ~ATOM_S0_CV_MASK; 4190 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE; 4191 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV; 4192 } 4193 } 4194 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) && 4195 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) { 4196 if (connected) { 4197 DRM_DEBUG_KMS("LCD1 connected\n"); 4198 bios_0_scratch |= ATOM_S0_LCD1; 4199 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE; 4200 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1; 4201 } else { 4202 DRM_DEBUG_KMS("LCD1 disconnected\n"); 4203 bios_0_scratch &= ~ATOM_S0_LCD1; 4204 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE; 4205 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1; 4206 } 4207 } 4208 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) && 4209 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) { 4210 if (connected) { 4211 DRM_DEBUG_KMS("CRT1 connected\n"); 4212 bios_0_scratch |= ATOM_S0_CRT1_COLOR; 4213 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE; 4214 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1; 4215 } else { 4216 DRM_DEBUG_KMS("CRT1 disconnected\n"); 4217 bios_0_scratch &= ~ATOM_S0_CRT1_MASK; 4218 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE; 4219 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1; 4220 } 4221 } 4222 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) && 4223 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) { 4224 if (connected) { 4225 DRM_DEBUG_KMS("CRT2 connected\n"); 4226 bios_0_scratch |= ATOM_S0_CRT2_COLOR; 4227 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE; 4228 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2; 4229 } else { 4230 DRM_DEBUG_KMS("CRT2 disconnected\n"); 4231 bios_0_scratch &= ~ATOM_S0_CRT2_MASK; 4232 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE; 4233 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2; 4234 } 4235 } 4236 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) && 4237 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) { 4238 if (connected) { 4239 DRM_DEBUG_KMS("DFP1 connected\n"); 4240 bios_0_scratch |= ATOM_S0_DFP1; 4241 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE; 4242 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1; 4243 } else { 4244 DRM_DEBUG_KMS("DFP1 disconnected\n"); 4245 bios_0_scratch &= ~ATOM_S0_DFP1; 4246 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE; 4247 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1; 4248 } 4249 } 4250 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) && 4251 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) { 4252 if (connected) { 4253 DRM_DEBUG_KMS("DFP2 connected\n"); 4254 bios_0_scratch |= ATOM_S0_DFP2; 4255 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE; 4256 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2; 4257 } else { 4258 DRM_DEBUG_KMS("DFP2 disconnected\n"); 4259 bios_0_scratch &= ~ATOM_S0_DFP2; 4260 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE; 4261 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2; 4262 } 4263 } 4264 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) && 4265 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) { 4266 if (connected) { 4267 DRM_DEBUG_KMS("DFP3 connected\n"); 4268 bios_0_scratch |= ATOM_S0_DFP3; 4269 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE; 4270 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3; 4271 } else { 4272 DRM_DEBUG_KMS("DFP3 disconnected\n"); 4273 bios_0_scratch &= ~ATOM_S0_DFP3; 4274 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE; 4275 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3; 4276 } 4277 } 4278 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) && 4279 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) { 4280 if (connected) { 4281 DRM_DEBUG_KMS("DFP4 connected\n"); 4282 bios_0_scratch |= ATOM_S0_DFP4; 4283 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE; 4284 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4; 4285 } else { 4286 DRM_DEBUG_KMS("DFP4 disconnected\n"); 4287 bios_0_scratch &= ~ATOM_S0_DFP4; 4288 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE; 4289 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4; 4290 } 4291 } 4292 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) && 4293 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) { 4294 if (connected) { 4295 DRM_DEBUG_KMS("DFP5 connected\n"); 4296 bios_0_scratch |= ATOM_S0_DFP5; 4297 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE; 4298 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5; 4299 } else { 4300 DRM_DEBUG_KMS("DFP5 disconnected\n"); 4301 bios_0_scratch &= ~ATOM_S0_DFP5; 4302 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE; 4303 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5; 4304 } 4305 } 4306 if ((radeon_encoder->devices & ATOM_DEVICE_DFP6_SUPPORT) && 4307 (radeon_connector->devices & ATOM_DEVICE_DFP6_SUPPORT)) { 4308 if (connected) { 4309 DRM_DEBUG_KMS("DFP6 connected\n"); 4310 bios_0_scratch |= ATOM_S0_DFP6; 4311 bios_3_scratch |= ATOM_S3_DFP6_ACTIVE; 4312 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP6; 4313 } else { 4314 DRM_DEBUG_KMS("DFP6 disconnected\n"); 4315 bios_0_scratch &= ~ATOM_S0_DFP6; 4316 bios_3_scratch &= ~ATOM_S3_DFP6_ACTIVE; 4317 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP6; 4318 } 4319 } 4320 4321 if (rdev->family >= CHIP_R600) { 4322 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch); 4323 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch); 4324 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); 4325 } else { 4326 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch); 4327 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch); 4328 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 4329 } 4330 } 4331 4332 void 4333 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc) 4334 { 4335 struct drm_device *dev = encoder->dev; 4336 struct radeon_device *rdev = dev->dev_private; 4337 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 4338 uint32_t bios_3_scratch; 4339 4340 if (ASIC_IS_DCE4(rdev)) 4341 return; 4342 4343 if (rdev->family >= CHIP_R600) 4344 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH); 4345 else 4346 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH); 4347 4348 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { 4349 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE; 4350 bios_3_scratch |= (crtc << 18); 4351 } 4352 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) { 4353 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE; 4354 bios_3_scratch |= (crtc << 24); 4355 } 4356 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { 4357 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE; 4358 bios_3_scratch |= (crtc << 16); 4359 } 4360 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { 4361 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE; 4362 bios_3_scratch |= (crtc << 20); 4363 } 4364 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { 4365 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE; 4366 bios_3_scratch |= (crtc << 17); 4367 } 4368 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) { 4369 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE; 4370 bios_3_scratch |= (crtc << 19); 4371 } 4372 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) { 4373 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE; 4374 bios_3_scratch |= (crtc << 23); 4375 } 4376 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) { 4377 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE; 4378 bios_3_scratch |= (crtc << 25); 4379 } 4380 4381 if (rdev->family >= CHIP_R600) 4382 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch); 4383 else 4384 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch); 4385 } 4386 4387 void 4388 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on) 4389 { 4390 struct drm_device *dev = encoder->dev; 4391 struct radeon_device *rdev = dev->dev_private; 4392 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 4393 uint32_t bios_2_scratch; 4394 4395 if (ASIC_IS_DCE4(rdev)) 4396 return; 4397 4398 if (rdev->family >= CHIP_R600) 4399 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); 4400 else 4401 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); 4402 4403 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { 4404 if (on) 4405 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE; 4406 else 4407 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE; 4408 } 4409 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) { 4410 if (on) 4411 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE; 4412 else 4413 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE; 4414 } 4415 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { 4416 if (on) 4417 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE; 4418 else 4419 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE; 4420 } 4421 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { 4422 if (on) 4423 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE; 4424 else 4425 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE; 4426 } 4427 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { 4428 if (on) 4429 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE; 4430 else 4431 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE; 4432 } 4433 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) { 4434 if (on) 4435 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE; 4436 else 4437 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE; 4438 } 4439 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) { 4440 if (on) 4441 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE; 4442 else 4443 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE; 4444 } 4445 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) { 4446 if (on) 4447 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE; 4448 else 4449 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE; 4450 } 4451 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) { 4452 if (on) 4453 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE; 4454 else 4455 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE; 4456 } 4457 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) { 4458 if (on) 4459 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE; 4460 else 4461 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE; 4462 } 4463 4464 if (rdev->family >= CHIP_R600) 4465 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); 4466 else 4467 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); 4468 } 4469