1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __RADEON_ASIC_H__ 29 #define __RADEON_ASIC_H__ 30 31 /* 32 * common functions 33 */ 34 uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev); 35 void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); 36 uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev); 37 void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); 38 39 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev); 40 void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); 41 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev); 42 void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock); 43 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); 44 45 /* 46 * r100,rv100,rs100,rv200,rs200 47 */ 48 struct r100_mc_save { 49 u32 GENMO_WT; 50 u32 CRTC_EXT_CNTL; 51 u32 CRTC_GEN_CNTL; 52 u32 CRTC2_GEN_CNTL; 53 u32 CUR_OFFSET; 54 u32 CUR2_OFFSET; 55 }; 56 int r100_init(struct radeon_device *rdev); 57 void r100_fini(struct radeon_device *rdev); 58 int r100_suspend(struct radeon_device *rdev); 59 int r100_resume(struct radeon_device *rdev); 60 void r100_vga_set_state(struct radeon_device *rdev, bool state); 61 bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 62 int r100_asic_reset(struct radeon_device *rdev); 63 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc); 64 void r100_pci_gart_tlb_flush(struct radeon_device *rdev); 65 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); 66 void r100_ring_start(struct radeon_device *rdev); 67 int r100_irq_set(struct radeon_device *rdev); 68 int r100_irq_process(struct radeon_device *rdev); 69 void r100_fence_ring_emit(struct radeon_device *rdev, 70 struct radeon_fence *fence); 71 void r100_semaphore_ring_emit(struct radeon_device *rdev, 72 struct radeon_ring *cp, 73 struct radeon_semaphore *semaphore, 74 bool emit_wait); 75 int r100_cs_parse(struct radeon_cs_parser *p); 76 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 77 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg); 78 int r100_copy_blit(struct radeon_device *rdev, 79 uint64_t src_offset, 80 uint64_t dst_offset, 81 unsigned num_gpu_pages, 82 struct radeon_fence *fence); 83 int r100_set_surface_reg(struct radeon_device *rdev, int reg, 84 uint32_t tiling_flags, uint32_t pitch, 85 uint32_t offset, uint32_t obj_size); 86 void r100_clear_surface_reg(struct radeon_device *rdev, int reg); 87 void r100_bandwidth_update(struct radeon_device *rdev); 88 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 89 int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 90 void r100_hpd_init(struct radeon_device *rdev); 91 void r100_hpd_fini(struct radeon_device *rdev); 92 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 93 void r100_hpd_set_polarity(struct radeon_device *rdev, 94 enum radeon_hpd_id hpd); 95 int r100_debugfs_rbbm_init(struct radeon_device *rdev); 96 int r100_debugfs_cp_init(struct radeon_device *rdev); 97 void r100_cp_disable(struct radeon_device *rdev); 98 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); 99 void r100_cp_fini(struct radeon_device *rdev); 100 int r100_pci_gart_init(struct radeon_device *rdev); 101 void r100_pci_gart_fini(struct radeon_device *rdev); 102 int r100_pci_gart_enable(struct radeon_device *rdev); 103 void r100_pci_gart_disable(struct radeon_device *rdev); 104 int r100_debugfs_mc_info_init(struct radeon_device *rdev); 105 int r100_gui_wait_for_idle(struct radeon_device *rdev); 106 void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, 107 struct radeon_ring *cp); 108 bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, 109 struct r100_gpu_lockup *lockup, 110 struct radeon_ring *cp); 111 void r100_ib_fini(struct radeon_device *rdev); 112 int r100_ib_test(struct radeon_device *rdev); 113 void r100_irq_disable(struct radeon_device *rdev); 114 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save); 115 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save); 116 void r100_vram_init_sizes(struct radeon_device *rdev); 117 int r100_cp_reset(struct radeon_device *rdev); 118 void r100_vga_render_disable(struct radeon_device *rdev); 119 void r100_restore_sanity(struct radeon_device *rdev); 120 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, 121 struct radeon_cs_packet *pkt, 122 struct radeon_bo *robj); 123 int r100_cs_parse_packet0(struct radeon_cs_parser *p, 124 struct radeon_cs_packet *pkt, 125 const unsigned *auth, unsigned n, 126 radeon_packet0_check_t check); 127 int r100_cs_packet_parse(struct radeon_cs_parser *p, 128 struct radeon_cs_packet *pkt, 129 unsigned idx); 130 void r100_enable_bm(struct radeon_device *rdev); 131 void r100_set_common_regs(struct radeon_device *rdev); 132 void r100_bm_disable(struct radeon_device *rdev); 133 extern bool r100_gui_idle(struct radeon_device *rdev); 134 extern void r100_pm_misc(struct radeon_device *rdev); 135 extern void r100_pm_prepare(struct radeon_device *rdev); 136 extern void r100_pm_finish(struct radeon_device *rdev); 137 extern void r100_pm_init_profile(struct radeon_device *rdev); 138 extern void r100_pm_get_dynpm_state(struct radeon_device *rdev); 139 extern void r100_pre_page_flip(struct radeon_device *rdev, int crtc); 140 extern u32 r100_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); 141 extern void r100_post_page_flip(struct radeon_device *rdev, int crtc); 142 143 /* 144 * r200,rv250,rs300,rv280 145 */ 146 extern int r200_copy_dma(struct radeon_device *rdev, 147 uint64_t src_offset, 148 uint64_t dst_offset, 149 unsigned num_gpu_pages, 150 struct radeon_fence *fence); 151 void r200_set_safe_registers(struct radeon_device *rdev); 152 153 /* 154 * r300,r350,rv350,rv380 155 */ 156 extern int r300_init(struct radeon_device *rdev); 157 extern void r300_fini(struct radeon_device *rdev); 158 extern int r300_suspend(struct radeon_device *rdev); 159 extern int r300_resume(struct radeon_device *rdev); 160 extern bool r300_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 161 extern int r300_asic_reset(struct radeon_device *rdev); 162 extern void r300_ring_start(struct radeon_device *rdev); 163 extern void r300_fence_ring_emit(struct radeon_device *rdev, 164 struct radeon_fence *fence); 165 extern int r300_cs_parse(struct radeon_cs_parser *p); 166 extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev); 167 extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); 168 extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes); 169 extern int rv370_get_pcie_lanes(struct radeon_device *rdev); 170 extern void r300_set_reg_safe(struct radeon_device *rdev); 171 extern void r300_mc_program(struct radeon_device *rdev); 172 extern void r300_mc_init(struct radeon_device *rdev); 173 extern void r300_clock_startup(struct radeon_device *rdev); 174 extern int r300_mc_wait_for_idle(struct radeon_device *rdev); 175 extern int rv370_pcie_gart_init(struct radeon_device *rdev); 176 extern void rv370_pcie_gart_fini(struct radeon_device *rdev); 177 extern int rv370_pcie_gart_enable(struct radeon_device *rdev); 178 extern void rv370_pcie_gart_disable(struct radeon_device *rdev); 179 180 /* 181 * r420,r423,rv410 182 */ 183 extern int r420_init(struct radeon_device *rdev); 184 extern void r420_fini(struct radeon_device *rdev); 185 extern int r420_suspend(struct radeon_device *rdev); 186 extern int r420_resume(struct radeon_device *rdev); 187 extern void r420_pm_init_profile(struct radeon_device *rdev); 188 extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); 189 extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); 190 extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev); 191 extern void r420_pipes_init(struct radeon_device *rdev); 192 193 /* 194 * rs400,rs480 195 */ 196 extern int rs400_init(struct radeon_device *rdev); 197 extern void rs400_fini(struct radeon_device *rdev); 198 extern int rs400_suspend(struct radeon_device *rdev); 199 extern int rs400_resume(struct radeon_device *rdev); 200 void rs400_gart_tlb_flush(struct radeon_device *rdev); 201 int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); 202 uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg); 203 void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 204 int rs400_gart_init(struct radeon_device *rdev); 205 int rs400_gart_enable(struct radeon_device *rdev); 206 void rs400_gart_adjust_size(struct radeon_device *rdev); 207 void rs400_gart_disable(struct radeon_device *rdev); 208 void rs400_gart_fini(struct radeon_device *rdev); 209 210 /* 211 * rs600. 212 */ 213 extern int rs600_asic_reset(struct radeon_device *rdev); 214 extern int rs600_init(struct radeon_device *rdev); 215 extern void rs600_fini(struct radeon_device *rdev); 216 extern int rs600_suspend(struct radeon_device *rdev); 217 extern int rs600_resume(struct radeon_device *rdev); 218 int rs600_irq_set(struct radeon_device *rdev); 219 int rs600_irq_process(struct radeon_device *rdev); 220 void rs600_irq_disable(struct radeon_device *rdev); 221 u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc); 222 void rs600_gart_tlb_flush(struct radeon_device *rdev); 223 int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); 224 uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg); 225 void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 226 void rs600_bandwidth_update(struct radeon_device *rdev); 227 void rs600_hpd_init(struct radeon_device *rdev); 228 void rs600_hpd_fini(struct radeon_device *rdev); 229 bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 230 void rs600_hpd_set_polarity(struct radeon_device *rdev, 231 enum radeon_hpd_id hpd); 232 extern void rs600_pm_misc(struct radeon_device *rdev); 233 extern void rs600_pm_prepare(struct radeon_device *rdev); 234 extern void rs600_pm_finish(struct radeon_device *rdev); 235 extern void rs600_pre_page_flip(struct radeon_device *rdev, int crtc); 236 extern u32 rs600_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); 237 extern void rs600_post_page_flip(struct radeon_device *rdev, int crtc); 238 void rs600_set_safe_registers(struct radeon_device *rdev); 239 240 241 /* 242 * rs690,rs740 243 */ 244 int rs690_init(struct radeon_device *rdev); 245 void rs690_fini(struct radeon_device *rdev); 246 int rs690_resume(struct radeon_device *rdev); 247 int rs690_suspend(struct radeon_device *rdev); 248 uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg); 249 void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 250 void rs690_bandwidth_update(struct radeon_device *rdev); 251 void rs690_line_buffer_adjust(struct radeon_device *rdev, 252 struct drm_display_mode *mode1, 253 struct drm_display_mode *mode2); 254 255 /* 256 * rv515 257 */ 258 struct rv515_mc_save { 259 u32 d1vga_control; 260 u32 d2vga_control; 261 u32 vga_render_control; 262 u32 vga_hdp_control; 263 u32 d1crtc_control; 264 u32 d2crtc_control; 265 }; 266 int rv515_init(struct radeon_device *rdev); 267 void rv515_fini(struct radeon_device *rdev); 268 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg); 269 void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 270 void rv515_ring_start(struct radeon_device *rdev); 271 void rv515_bandwidth_update(struct radeon_device *rdev); 272 int rv515_resume(struct radeon_device *rdev); 273 int rv515_suspend(struct radeon_device *rdev); 274 void rv515_bandwidth_avivo_update(struct radeon_device *rdev); 275 void rv515_vga_render_disable(struct radeon_device *rdev); 276 void rv515_set_safe_registers(struct radeon_device *rdev); 277 void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save); 278 void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save); 279 void rv515_clock_startup(struct radeon_device *rdev); 280 void rv515_debugfs(struct radeon_device *rdev); 281 282 283 /* 284 * r520,rv530,rv560,rv570,r580 285 */ 286 int r520_init(struct radeon_device *rdev); 287 int r520_resume(struct radeon_device *rdev); 288 289 /* 290 * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880 291 */ 292 int r600_init(struct radeon_device *rdev); 293 void r600_fini(struct radeon_device *rdev); 294 int r600_suspend(struct radeon_device *rdev); 295 int r600_resume(struct radeon_device *rdev); 296 void r600_vga_set_state(struct radeon_device *rdev, bool state); 297 int r600_wb_init(struct radeon_device *rdev); 298 void r600_wb_fini(struct radeon_device *rdev); 299 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); 300 uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg); 301 void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 302 int r600_cs_parse(struct radeon_cs_parser *p); 303 void r600_fence_ring_emit(struct radeon_device *rdev, 304 struct radeon_fence *fence); 305 void r600_semaphore_ring_emit(struct radeon_device *rdev, 306 struct radeon_ring *cp, 307 struct radeon_semaphore *semaphore, 308 bool emit_wait); 309 bool r600_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 310 int r600_asic_reset(struct radeon_device *rdev); 311 int r600_set_surface_reg(struct radeon_device *rdev, int reg, 312 uint32_t tiling_flags, uint32_t pitch, 313 uint32_t offset, uint32_t obj_size); 314 void r600_clear_surface_reg(struct radeon_device *rdev, int reg); 315 int r600_ib_test(struct radeon_device *rdev, int ring); 316 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 317 int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 318 int r600_copy_blit(struct radeon_device *rdev, 319 uint64_t src_offset, uint64_t dst_offset, 320 unsigned num_gpu_pages, struct radeon_fence *fence); 321 void r600_hpd_init(struct radeon_device *rdev); 322 void r600_hpd_fini(struct radeon_device *rdev); 323 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 324 void r600_hpd_set_polarity(struct radeon_device *rdev, 325 enum radeon_hpd_id hpd); 326 extern void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo); 327 extern bool r600_gui_idle(struct radeon_device *rdev); 328 extern void r600_pm_misc(struct radeon_device *rdev); 329 extern void r600_pm_init_profile(struct radeon_device *rdev); 330 extern void rs780_pm_init_profile(struct radeon_device *rdev); 331 extern void r600_pm_get_dynpm_state(struct radeon_device *rdev); 332 extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes); 333 extern int r600_get_pcie_lanes(struct radeon_device *rdev); 334 bool r600_card_posted(struct radeon_device *rdev); 335 void r600_cp_stop(struct radeon_device *rdev); 336 int r600_cp_start(struct radeon_device *rdev); 337 void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size); 338 int r600_cp_resume(struct radeon_device *rdev); 339 void r600_cp_fini(struct radeon_device *rdev); 340 int r600_count_pipe_bits(uint32_t val); 341 int r600_mc_wait_for_idle(struct radeon_device *rdev); 342 int r600_pcie_gart_init(struct radeon_device *rdev); 343 void r600_scratch_init(struct radeon_device *rdev); 344 int r600_blit_init(struct radeon_device *rdev); 345 void r600_blit_fini(struct radeon_device *rdev); 346 int r600_init_microcode(struct radeon_device *rdev); 347 /* r600 irq */ 348 int r600_irq_process(struct radeon_device *rdev); 349 int r600_irq_init(struct radeon_device *rdev); 350 void r600_irq_fini(struct radeon_device *rdev); 351 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size); 352 int r600_irq_set(struct radeon_device *rdev); 353 void r600_irq_suspend(struct radeon_device *rdev); 354 void r600_disable_interrupts(struct radeon_device *rdev); 355 void r600_rlc_stop(struct radeon_device *rdev); 356 /* r600 audio */ 357 int r600_audio_init(struct radeon_device *rdev); 358 int r600_audio_tmds_index(struct drm_encoder *encoder); 359 void r600_audio_set_clock(struct drm_encoder *encoder, int clock); 360 int r600_audio_channels(struct radeon_device *rdev); 361 int r600_audio_bits_per_sample(struct radeon_device *rdev); 362 int r600_audio_rate(struct radeon_device *rdev); 363 uint8_t r600_audio_status_bits(struct radeon_device *rdev); 364 uint8_t r600_audio_category_code(struct radeon_device *rdev); 365 void r600_audio_schedule_polling(struct radeon_device *rdev); 366 void r600_audio_enable_polling(struct drm_encoder *encoder); 367 void r600_audio_disable_polling(struct drm_encoder *encoder); 368 void r600_audio_fini(struct radeon_device *rdev); 369 void r600_hdmi_init(struct drm_encoder *encoder); 370 int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder); 371 void r600_hdmi_update_audio_settings(struct drm_encoder *encoder); 372 /* r600 blit */ 373 int r600_blit_prepare_copy(struct radeon_device *rdev, unsigned num_gpu_pages); 374 void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence); 375 void r600_kms_blit_copy(struct radeon_device *rdev, 376 u64 src_gpu_addr, u64 dst_gpu_addr, 377 unsigned num_gpu_pages); 378 379 /* 380 * rv770,rv730,rv710,rv740 381 */ 382 int rv770_init(struct radeon_device *rdev); 383 void rv770_fini(struct radeon_device *rdev); 384 int rv770_suspend(struct radeon_device *rdev); 385 int rv770_resume(struct radeon_device *rdev); 386 void rv770_pm_misc(struct radeon_device *rdev); 387 u32 rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); 388 void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); 389 void r700_cp_stop(struct radeon_device *rdev); 390 void r700_cp_fini(struct radeon_device *rdev); 391 392 /* 393 * evergreen 394 */ 395 struct evergreen_mc_save { 396 u32 vga_control[6]; 397 u32 vga_render_control; 398 u32 vga_hdp_control; 399 u32 crtc_control[6]; 400 }; 401 void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev); 402 int evergreen_init(struct radeon_device *rdev); 403 void evergreen_fini(struct radeon_device *rdev); 404 int evergreen_suspend(struct radeon_device *rdev); 405 int evergreen_resume(struct radeon_device *rdev); 406 bool evergreen_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 407 int evergreen_asic_reset(struct radeon_device *rdev); 408 void evergreen_bandwidth_update(struct radeon_device *rdev); 409 void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 410 void evergreen_hpd_init(struct radeon_device *rdev); 411 void evergreen_hpd_fini(struct radeon_device *rdev); 412 bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 413 void evergreen_hpd_set_polarity(struct radeon_device *rdev, 414 enum radeon_hpd_id hpd); 415 u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc); 416 int evergreen_irq_set(struct radeon_device *rdev); 417 int evergreen_irq_process(struct radeon_device *rdev); 418 extern int evergreen_cs_parse(struct radeon_cs_parser *p); 419 extern void evergreen_pm_misc(struct radeon_device *rdev); 420 extern void evergreen_pm_prepare(struct radeon_device *rdev); 421 extern void evergreen_pm_finish(struct radeon_device *rdev); 422 extern void sumo_pm_init_profile(struct radeon_device *rdev); 423 extern void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc); 424 extern u32 evergreen_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); 425 extern void evergreen_post_page_flip(struct radeon_device *rdev, int crtc); 426 void evergreen_disable_interrupt_state(struct radeon_device *rdev); 427 int evergreen_blit_init(struct radeon_device *rdev); 428 429 /* 430 * cayman 431 */ 432 void cayman_fence_ring_emit(struct radeon_device *rdev, 433 struct radeon_fence *fence); 434 void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev); 435 int cayman_init(struct radeon_device *rdev); 436 void cayman_fini(struct radeon_device *rdev); 437 int cayman_suspend(struct radeon_device *rdev); 438 int cayman_resume(struct radeon_device *rdev); 439 bool cayman_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 440 int cayman_asic_reset(struct radeon_device *rdev); 441 void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 442 int cayman_vm_init(struct radeon_device *rdev); 443 void cayman_vm_fini(struct radeon_device *rdev); 444 int cayman_vm_bind(struct radeon_device *rdev, struct radeon_vm *vm, int id); 445 void cayman_vm_unbind(struct radeon_device *rdev, struct radeon_vm *vm); 446 void cayman_vm_tlb_flush(struct radeon_device *rdev, struct radeon_vm *vm); 447 uint32_t cayman_vm_page_flags(struct radeon_device *rdev, 448 struct radeon_vm *vm, 449 uint32_t flags); 450 void cayman_vm_set_page(struct radeon_device *rdev, struct radeon_vm *vm, 451 unsigned pfn, uint64_t addr, uint32_t flags); 452 int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); 453 454 #endif 455