1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __RADEON_ASIC_H__ 29 #define __RADEON_ASIC_H__ 30 31 /* 32 * common functions 33 */ 34 uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev); 35 void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); 36 uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev); 37 void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); 38 39 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev); 40 void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); 41 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev); 42 void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock); 43 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); 44 45 void atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level); 46 u8 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder); 47 void radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level); 48 u8 radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder); 49 50 /* 51 * r100,rv100,rs100,rv200,rs200 52 */ 53 struct r100_mc_save { 54 u32 GENMO_WT; 55 u32 CRTC_EXT_CNTL; 56 u32 CRTC_GEN_CNTL; 57 u32 CRTC2_GEN_CNTL; 58 u32 CUR_OFFSET; 59 u32 CUR2_OFFSET; 60 }; 61 int r100_init(struct radeon_device *rdev); 62 void r100_fini(struct radeon_device *rdev); 63 int r100_suspend(struct radeon_device *rdev); 64 int r100_resume(struct radeon_device *rdev); 65 void r100_vga_set_state(struct radeon_device *rdev, bool state); 66 bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 67 int r100_asic_reset(struct radeon_device *rdev, bool hard); 68 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc); 69 void r100_pci_gart_tlb_flush(struct radeon_device *rdev); 70 uint64_t r100_pci_gart_get_page_entry(uint64_t addr, uint32_t flags); 71 void r100_pci_gart_set_page(struct radeon_device *rdev, unsigned i, 72 uint64_t entry); 73 void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); 74 int r100_irq_set(struct radeon_device *rdev); 75 int r100_irq_process(struct radeon_device *rdev); 76 void r100_fence_ring_emit(struct radeon_device *rdev, 77 struct radeon_fence *fence); 78 bool r100_semaphore_ring_emit(struct radeon_device *rdev, 79 struct radeon_ring *cp, 80 struct radeon_semaphore *semaphore, 81 bool emit_wait); 82 int r100_cs_parse(struct radeon_cs_parser *p); 83 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 84 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg); 85 struct radeon_fence *r100_copy_blit(struct radeon_device *rdev, 86 uint64_t src_offset, 87 uint64_t dst_offset, 88 unsigned num_gpu_pages, 89 struct dma_resv *resv); 90 int r100_set_surface_reg(struct radeon_device *rdev, int reg, 91 uint32_t tiling_flags, uint32_t pitch, 92 uint32_t offset, uint32_t obj_size); 93 void r100_clear_surface_reg(struct radeon_device *rdev, int reg); 94 void r100_bandwidth_update(struct radeon_device *rdev); 95 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 96 int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 97 void r100_hpd_init(struct radeon_device *rdev); 98 void r100_hpd_fini(struct radeon_device *rdev); 99 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 100 void r100_hpd_set_polarity(struct radeon_device *rdev, 101 enum radeon_hpd_id hpd); 102 void r100_debugfs_rbbm_init(struct radeon_device *rdev); 103 void r100_debugfs_cp_init(struct radeon_device *rdev); 104 void r100_cp_disable(struct radeon_device *rdev); 105 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); 106 void r100_cp_fini(struct radeon_device *rdev); 107 int r100_pci_gart_init(struct radeon_device *rdev); 108 void r100_pci_gart_fini(struct radeon_device *rdev); 109 int r100_pci_gart_enable(struct radeon_device *rdev); 110 void r100_pci_gart_disable(struct radeon_device *rdev); 111 void r100_debugfs_mc_info_init(struct radeon_device *rdev); 112 int r100_gui_wait_for_idle(struct radeon_device *rdev); 113 int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 114 void r100_irq_disable(struct radeon_device *rdev); 115 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save); 116 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save); 117 void r100_vram_init_sizes(struct radeon_device *rdev); 118 int r100_cp_reset(struct radeon_device *rdev); 119 void r100_vga_render_disable(struct radeon_device *rdev); 120 void r100_restore_sanity(struct radeon_device *rdev); 121 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, 122 struct radeon_cs_packet *pkt, 123 struct radeon_bo *robj); 124 int r100_cs_parse_packet0(struct radeon_cs_parser *p, 125 struct radeon_cs_packet *pkt, 126 const unsigned *auth, unsigned n, 127 radeon_packet0_check_t check); 128 int r100_cs_packet_parse(struct radeon_cs_parser *p, 129 struct radeon_cs_packet *pkt, 130 unsigned idx); 131 void r100_enable_bm(struct radeon_device *rdev); 132 void r100_set_common_regs(struct radeon_device *rdev); 133 void r100_bm_disable(struct radeon_device *rdev); 134 extern bool r100_gui_idle(struct radeon_device *rdev); 135 extern void r100_pm_misc(struct radeon_device *rdev); 136 extern void r100_pm_prepare(struct radeon_device *rdev); 137 extern void r100_pm_finish(struct radeon_device *rdev); 138 extern void r100_pm_init_profile(struct radeon_device *rdev); 139 extern void r100_pm_get_dynpm_state(struct radeon_device *rdev); 140 extern void r100_page_flip(struct radeon_device *rdev, int crtc, 141 u64 crtc_base, bool async); 142 extern bool r100_page_flip_pending(struct radeon_device *rdev, int crtc); 143 extern void r100_wait_for_vblank(struct radeon_device *rdev, int crtc); 144 extern int r100_mc_wait_for_idle(struct radeon_device *rdev); 145 146 u32 r100_gfx_get_rptr(struct radeon_device *rdev, 147 struct radeon_ring *ring); 148 u32 r100_gfx_get_wptr(struct radeon_device *rdev, 149 struct radeon_ring *ring); 150 void r100_gfx_set_wptr(struct radeon_device *rdev, 151 struct radeon_ring *ring); 152 153 /* 154 * r200,rv250,rs300,rv280 155 */ 156 struct radeon_fence *r200_copy_dma(struct radeon_device *rdev, 157 uint64_t src_offset, 158 uint64_t dst_offset, 159 unsigned num_gpu_pages, 160 struct dma_resv *resv); 161 void r200_set_safe_registers(struct radeon_device *rdev); 162 163 /* 164 * r300,r350,rv350,rv380 165 */ 166 extern int r300_init(struct radeon_device *rdev); 167 extern void r300_fini(struct radeon_device *rdev); 168 extern int r300_suspend(struct radeon_device *rdev); 169 extern int r300_resume(struct radeon_device *rdev); 170 extern int r300_asic_reset(struct radeon_device *rdev, bool hard); 171 extern void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); 172 extern void r300_fence_ring_emit(struct radeon_device *rdev, 173 struct radeon_fence *fence); 174 extern int r300_cs_parse(struct radeon_cs_parser *p); 175 extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev); 176 extern uint64_t rv370_pcie_gart_get_page_entry(uint64_t addr, uint32_t flags); 177 extern void rv370_pcie_gart_set_page(struct radeon_device *rdev, unsigned i, 178 uint64_t entry); 179 extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes); 180 extern int rv370_get_pcie_lanes(struct radeon_device *rdev); 181 extern void r300_set_reg_safe(struct radeon_device *rdev); 182 extern void r300_mc_program(struct radeon_device *rdev); 183 extern void r300_mc_init(struct radeon_device *rdev); 184 extern void r300_clock_startup(struct radeon_device *rdev); 185 extern int r300_mc_wait_for_idle(struct radeon_device *rdev); 186 extern int rv370_pcie_gart_init(struct radeon_device *rdev); 187 extern void rv370_pcie_gart_fini(struct radeon_device *rdev); 188 extern int rv370_pcie_gart_enable(struct radeon_device *rdev); 189 extern void rv370_pcie_gart_disable(struct radeon_device *rdev); 190 191 /* 192 * r420,r423,rv410 193 */ 194 extern int r420_init(struct radeon_device *rdev); 195 extern void r420_fini(struct radeon_device *rdev); 196 extern int r420_suspend(struct radeon_device *rdev); 197 extern int r420_resume(struct radeon_device *rdev); 198 extern void r420_pm_init_profile(struct radeon_device *rdev); 199 extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); 200 extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); 201 extern void r420_debugfs_pipes_info_init(struct radeon_device *rdev); 202 extern void r420_pipes_init(struct radeon_device *rdev); 203 204 /* 205 * rs400,rs480 206 */ 207 extern int rs400_init(struct radeon_device *rdev); 208 extern void rs400_fini(struct radeon_device *rdev); 209 extern int rs400_suspend(struct radeon_device *rdev); 210 extern int rs400_resume(struct radeon_device *rdev); 211 void rs400_gart_tlb_flush(struct radeon_device *rdev); 212 uint64_t rs400_gart_get_page_entry(uint64_t addr, uint32_t flags); 213 void rs400_gart_set_page(struct radeon_device *rdev, unsigned i, 214 uint64_t entry); 215 uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg); 216 void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 217 int rs400_gart_init(struct radeon_device *rdev); 218 int rs400_gart_enable(struct radeon_device *rdev); 219 void rs400_gart_adjust_size(struct radeon_device *rdev); 220 void rs400_gart_disable(struct radeon_device *rdev); 221 void rs400_gart_fini(struct radeon_device *rdev); 222 extern int rs400_mc_wait_for_idle(struct radeon_device *rdev); 223 224 /* 225 * rs600. 226 */ 227 extern int rs600_asic_reset(struct radeon_device *rdev, bool hard); 228 extern int rs600_init(struct radeon_device *rdev); 229 extern void rs600_fini(struct radeon_device *rdev); 230 extern int rs600_suspend(struct radeon_device *rdev); 231 extern int rs600_resume(struct radeon_device *rdev); 232 int rs600_irq_set(struct radeon_device *rdev); 233 int rs600_irq_process(struct radeon_device *rdev); 234 void rs600_irq_disable(struct radeon_device *rdev); 235 u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc); 236 void rs600_gart_tlb_flush(struct radeon_device *rdev); 237 uint64_t rs600_gart_get_page_entry(uint64_t addr, uint32_t flags); 238 void rs600_gart_set_page(struct radeon_device *rdev, unsigned i, 239 uint64_t entry); 240 uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg); 241 void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 242 void rs600_bandwidth_update(struct radeon_device *rdev); 243 void rs600_hpd_init(struct radeon_device *rdev); 244 void rs600_hpd_fini(struct radeon_device *rdev); 245 bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 246 void rs600_hpd_set_polarity(struct radeon_device *rdev, 247 enum radeon_hpd_id hpd); 248 extern void rs600_pm_misc(struct radeon_device *rdev); 249 extern void rs600_pm_prepare(struct radeon_device *rdev); 250 extern void rs600_pm_finish(struct radeon_device *rdev); 251 extern void rs600_page_flip(struct radeon_device *rdev, int crtc, 252 u64 crtc_base, bool async); 253 extern bool rs600_page_flip_pending(struct radeon_device *rdev, int crtc); 254 void rs600_set_safe_registers(struct radeon_device *rdev); 255 extern void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc); 256 extern int rs600_mc_wait_for_idle(struct radeon_device *rdev); 257 258 /* 259 * rs690,rs740 260 */ 261 int rs690_init(struct radeon_device *rdev); 262 void rs690_fini(struct radeon_device *rdev); 263 int rs690_resume(struct radeon_device *rdev); 264 int rs690_suspend(struct radeon_device *rdev); 265 uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg); 266 void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 267 void rs690_bandwidth_update(struct radeon_device *rdev); 268 void rs690_line_buffer_adjust(struct radeon_device *rdev, 269 struct drm_display_mode *mode1, 270 struct drm_display_mode *mode2); 271 extern int rs690_mc_wait_for_idle(struct radeon_device *rdev); 272 273 /* 274 * rv515 275 */ 276 struct rv515_mc_save { 277 u32 vga_render_control; 278 u32 vga_hdp_control; 279 bool crtc_enabled[2]; 280 }; 281 282 int rv515_init(struct radeon_device *rdev); 283 void rv515_fini(struct radeon_device *rdev); 284 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg); 285 void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 286 void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); 287 void rv515_bandwidth_update(struct radeon_device *rdev); 288 int rv515_resume(struct radeon_device *rdev); 289 int rv515_suspend(struct radeon_device *rdev); 290 void rv515_bandwidth_avivo_update(struct radeon_device *rdev); 291 void rv515_vga_render_disable(struct radeon_device *rdev); 292 void rv515_set_safe_registers(struct radeon_device *rdev); 293 void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save); 294 void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save); 295 void rv515_clock_startup(struct radeon_device *rdev); 296 void rv515_debugfs(struct radeon_device *rdev); 297 int rv515_mc_wait_for_idle(struct radeon_device *rdev); 298 299 /* 300 * r520,rv530,rv560,rv570,r580 301 */ 302 int r520_init(struct radeon_device *rdev); 303 int r520_resume(struct radeon_device *rdev); 304 int r520_mc_wait_for_idle(struct radeon_device *rdev); 305 306 /* 307 * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880 308 */ 309 int r600_init(struct radeon_device *rdev); 310 void r600_fini(struct radeon_device *rdev); 311 int r600_suspend(struct radeon_device *rdev); 312 int r600_resume(struct radeon_device *rdev); 313 void r600_vga_set_state(struct radeon_device *rdev, bool state); 314 int r600_wb_init(struct radeon_device *rdev); 315 void r600_wb_fini(struct radeon_device *rdev); 316 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); 317 uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg); 318 void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 319 int r600_cs_parse(struct radeon_cs_parser *p); 320 int r600_dma_cs_parse(struct radeon_cs_parser *p); 321 void r600_fence_ring_emit(struct radeon_device *rdev, 322 struct radeon_fence *fence); 323 bool r600_semaphore_ring_emit(struct radeon_device *rdev, 324 struct radeon_ring *cp, 325 struct radeon_semaphore *semaphore, 326 bool emit_wait); 327 void r600_dma_fence_ring_emit(struct radeon_device *rdev, 328 struct radeon_fence *fence); 329 bool r600_dma_semaphore_ring_emit(struct radeon_device *rdev, 330 struct radeon_ring *ring, 331 struct radeon_semaphore *semaphore, 332 bool emit_wait); 333 void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 334 bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 335 bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 336 int r600_asic_reset(struct radeon_device *rdev, bool hard); 337 int r600_set_surface_reg(struct radeon_device *rdev, int reg, 338 uint32_t tiling_flags, uint32_t pitch, 339 uint32_t offset, uint32_t obj_size); 340 void r600_clear_surface_reg(struct radeon_device *rdev, int reg); 341 int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 342 int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 343 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 344 int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 345 int r600_dma_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 346 struct radeon_fence *r600_copy_cpdma(struct radeon_device *rdev, 347 uint64_t src_offset, uint64_t dst_offset, 348 unsigned num_gpu_pages, 349 struct dma_resv *resv); 350 struct radeon_fence *r600_copy_dma(struct radeon_device *rdev, 351 uint64_t src_offset, uint64_t dst_offset, 352 unsigned num_gpu_pages, 353 struct dma_resv *resv); 354 void r600_hpd_init(struct radeon_device *rdev); 355 void r600_hpd_fini(struct radeon_device *rdev); 356 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 357 void r600_hpd_set_polarity(struct radeon_device *rdev, 358 enum radeon_hpd_id hpd); 359 extern void r600_mmio_hdp_flush(struct radeon_device *rdev); 360 extern bool r600_gui_idle(struct radeon_device *rdev); 361 extern void r600_pm_misc(struct radeon_device *rdev); 362 extern void r600_pm_init_profile(struct radeon_device *rdev); 363 extern void rs780_pm_init_profile(struct radeon_device *rdev); 364 extern uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg); 365 extern void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 366 extern void r600_pm_get_dynpm_state(struct radeon_device *rdev); 367 extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes); 368 extern int r600_get_pcie_lanes(struct radeon_device *rdev); 369 bool r600_card_posted(struct radeon_device *rdev); 370 void r600_cp_stop(struct radeon_device *rdev); 371 int r600_cp_start(struct radeon_device *rdev); 372 void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size); 373 int r600_cp_resume(struct radeon_device *rdev); 374 void r600_cp_fini(struct radeon_device *rdev); 375 int r600_count_pipe_bits(uint32_t val); 376 int r600_mc_wait_for_idle(struct radeon_device *rdev); 377 int r600_pcie_gart_init(struct radeon_device *rdev); 378 void r600_scratch_init(struct radeon_device *rdev); 379 int r600_init_microcode(struct radeon_device *rdev); 380 u32 r600_gfx_get_rptr(struct radeon_device *rdev, 381 struct radeon_ring *ring); 382 u32 r600_gfx_get_wptr(struct radeon_device *rdev, 383 struct radeon_ring *ring); 384 void r600_gfx_set_wptr(struct radeon_device *rdev, 385 struct radeon_ring *ring); 386 int r600_get_allowed_info_register(struct radeon_device *rdev, 387 u32 reg, u32 *val); 388 /* r600 irq */ 389 int r600_irq_process(struct radeon_device *rdev); 390 int r600_irq_init(struct radeon_device *rdev); 391 void r600_irq_fini(struct radeon_device *rdev); 392 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size); 393 int r600_irq_set(struct radeon_device *rdev); 394 void r600_irq_suspend(struct radeon_device *rdev); 395 void r600_disable_interrupts(struct radeon_device *rdev); 396 void r600_rlc_stop(struct radeon_device *rdev); 397 /* r600 audio */ 398 void r600_audio_fini(struct radeon_device *rdev); 399 void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock); 400 void r600_hdmi_update_avi_infoframe(struct drm_encoder *encoder, void *buffer, 401 size_t size); 402 void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock); 403 void r600_hdmi_audio_workaround(struct drm_encoder *encoder); 404 int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder); 405 void r600_hdmi_update_audio_settings(struct drm_encoder *encoder); 406 u32 r600_get_xclk(struct radeon_device *rdev); 407 uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev); 408 int rv6xx_get_temp(struct radeon_device *rdev); 409 int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); 410 int r600_dpm_pre_set_power_state(struct radeon_device *rdev); 411 void r600_dpm_post_set_power_state(struct radeon_device *rdev); 412 int r600_dpm_late_enable(struct radeon_device *rdev); 413 /* r600 dma */ 414 uint32_t r600_dma_get_rptr(struct radeon_device *rdev, 415 struct radeon_ring *ring); 416 uint32_t r600_dma_get_wptr(struct radeon_device *rdev, 417 struct radeon_ring *ring); 418 void r600_dma_set_wptr(struct radeon_device *rdev, 419 struct radeon_ring *ring); 420 /* rv6xx dpm */ 421 int rv6xx_dpm_init(struct radeon_device *rdev); 422 int rv6xx_dpm_enable(struct radeon_device *rdev); 423 void rv6xx_dpm_disable(struct radeon_device *rdev); 424 int rv6xx_dpm_set_power_state(struct radeon_device *rdev); 425 void rv6xx_setup_asic(struct radeon_device *rdev); 426 void rv6xx_dpm_display_configuration_changed(struct radeon_device *rdev); 427 void rv6xx_dpm_fini(struct radeon_device *rdev); 428 u32 rv6xx_dpm_get_sclk(struct radeon_device *rdev, bool low); 429 u32 rv6xx_dpm_get_mclk(struct radeon_device *rdev, bool low); 430 void rv6xx_dpm_print_power_state(struct radeon_device *rdev, 431 struct radeon_ps *ps); 432 void rv6xx_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 433 struct seq_file *m); 434 int rv6xx_dpm_force_performance_level(struct radeon_device *rdev, 435 enum radeon_dpm_forced_level level); 436 u32 rv6xx_dpm_get_current_sclk(struct radeon_device *rdev); 437 u32 rv6xx_dpm_get_current_mclk(struct radeon_device *rdev); 438 /* rs780 dpm */ 439 int rs780_dpm_init(struct radeon_device *rdev); 440 int rs780_dpm_enable(struct radeon_device *rdev); 441 void rs780_dpm_disable(struct radeon_device *rdev); 442 int rs780_dpm_set_power_state(struct radeon_device *rdev); 443 void rs780_dpm_setup_asic(struct radeon_device *rdev); 444 void rs780_dpm_display_configuration_changed(struct radeon_device *rdev); 445 void rs780_dpm_fini(struct radeon_device *rdev); 446 u32 rs780_dpm_get_sclk(struct radeon_device *rdev, bool low); 447 u32 rs780_dpm_get_mclk(struct radeon_device *rdev, bool low); 448 void rs780_dpm_print_power_state(struct radeon_device *rdev, 449 struct radeon_ps *ps); 450 void rs780_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 451 struct seq_file *m); 452 int rs780_dpm_force_performance_level(struct radeon_device *rdev, 453 enum radeon_dpm_forced_level level); 454 u32 rs780_dpm_get_current_sclk(struct radeon_device *rdev); 455 u32 rs780_dpm_get_current_mclk(struct radeon_device *rdev); 456 457 /* 458 * rv770,rv730,rv710,rv740 459 */ 460 int rv770_init(struct radeon_device *rdev); 461 void rv770_fini(struct radeon_device *rdev); 462 int rv770_suspend(struct radeon_device *rdev); 463 int rv770_resume(struct radeon_device *rdev); 464 void rv770_pm_misc(struct radeon_device *rdev); 465 void rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base, 466 bool async); 467 bool rv770_page_flip_pending(struct radeon_device *rdev, int crtc); 468 void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); 469 void r700_cp_stop(struct radeon_device *rdev); 470 void r700_cp_fini(struct radeon_device *rdev); 471 struct radeon_fence *rv770_copy_dma(struct radeon_device *rdev, 472 uint64_t src_offset, uint64_t dst_offset, 473 unsigned num_gpu_pages, 474 struct dma_resv *resv); 475 u32 rv770_get_xclk(struct radeon_device *rdev); 476 int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); 477 int rv770_get_temp(struct radeon_device *rdev); 478 /* rv7xx pm */ 479 int rv770_dpm_init(struct radeon_device *rdev); 480 int rv770_dpm_enable(struct radeon_device *rdev); 481 int rv770_dpm_late_enable(struct radeon_device *rdev); 482 void rv770_dpm_disable(struct radeon_device *rdev); 483 int rv770_dpm_set_power_state(struct radeon_device *rdev); 484 void rv770_dpm_setup_asic(struct radeon_device *rdev); 485 void rv770_dpm_display_configuration_changed(struct radeon_device *rdev); 486 void rv770_dpm_fini(struct radeon_device *rdev); 487 u32 rv770_dpm_get_sclk(struct radeon_device *rdev, bool low); 488 u32 rv770_dpm_get_mclk(struct radeon_device *rdev, bool low); 489 void rv770_dpm_print_power_state(struct radeon_device *rdev, 490 struct radeon_ps *ps); 491 void rv770_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 492 struct seq_file *m); 493 int rv770_dpm_force_performance_level(struct radeon_device *rdev, 494 enum radeon_dpm_forced_level level); 495 bool rv770_dpm_vblank_too_short(struct radeon_device *rdev); 496 u32 rv770_dpm_get_current_sclk(struct radeon_device *rdev); 497 u32 rv770_dpm_get_current_mclk(struct radeon_device *rdev); 498 499 /* 500 * evergreen 501 */ 502 struct evergreen_mc_save { 503 u32 vga_render_control; 504 u32 vga_hdp_control; 505 bool crtc_enabled[RADEON_MAX_CRTCS]; 506 }; 507 508 void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev); 509 int evergreen_init(struct radeon_device *rdev); 510 void evergreen_fini(struct radeon_device *rdev); 511 int evergreen_suspend(struct radeon_device *rdev); 512 int evergreen_resume(struct radeon_device *rdev); 513 bool evergreen_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 514 bool evergreen_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 515 int evergreen_asic_reset(struct radeon_device *rdev, bool hard); 516 void evergreen_bandwidth_update(struct radeon_device *rdev); 517 void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 518 void evergreen_hpd_init(struct radeon_device *rdev); 519 void evergreen_hpd_fini(struct radeon_device *rdev); 520 bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 521 void evergreen_hpd_set_polarity(struct radeon_device *rdev, 522 enum radeon_hpd_id hpd); 523 u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc); 524 int evergreen_irq_set(struct radeon_device *rdev); 525 int evergreen_irq_process(struct radeon_device *rdev); 526 extern int evergreen_cs_parse(struct radeon_cs_parser *p); 527 extern int evergreen_dma_cs_parse(struct radeon_cs_parser *p); 528 extern void evergreen_pm_misc(struct radeon_device *rdev); 529 extern void evergreen_pm_prepare(struct radeon_device *rdev); 530 extern void evergreen_pm_finish(struct radeon_device *rdev); 531 extern void sumo_pm_init_profile(struct radeon_device *rdev); 532 extern void btc_pm_init_profile(struct radeon_device *rdev); 533 int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); 534 int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); 535 extern void evergreen_page_flip(struct radeon_device *rdev, int crtc, 536 u64 crtc_base, bool async); 537 extern bool evergreen_page_flip_pending(struct radeon_device *rdev, int crtc); 538 extern void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc); 539 void evergreen_disable_interrupt_state(struct radeon_device *rdev); 540 int evergreen_mc_wait_for_idle(struct radeon_device *rdev); 541 void evergreen_dma_fence_ring_emit(struct radeon_device *rdev, 542 struct radeon_fence *fence); 543 void evergreen_dma_ring_ib_execute(struct radeon_device *rdev, 544 struct radeon_ib *ib); 545 struct radeon_fence *evergreen_copy_dma(struct radeon_device *rdev, 546 uint64_t src_offset, uint64_t dst_offset, 547 unsigned num_gpu_pages, 548 struct dma_resv *resv); 549 int evergreen_get_temp(struct radeon_device *rdev); 550 int evergreen_get_allowed_info_register(struct radeon_device *rdev, 551 u32 reg, u32 *val); 552 int sumo_get_temp(struct radeon_device *rdev); 553 int tn_get_temp(struct radeon_device *rdev); 554 int cypress_dpm_init(struct radeon_device *rdev); 555 void cypress_dpm_setup_asic(struct radeon_device *rdev); 556 int cypress_dpm_enable(struct radeon_device *rdev); 557 void cypress_dpm_disable(struct radeon_device *rdev); 558 int cypress_dpm_set_power_state(struct radeon_device *rdev); 559 void cypress_dpm_display_configuration_changed(struct radeon_device *rdev); 560 void cypress_dpm_fini(struct radeon_device *rdev); 561 bool cypress_dpm_vblank_too_short(struct radeon_device *rdev); 562 int btc_dpm_init(struct radeon_device *rdev); 563 void btc_dpm_setup_asic(struct radeon_device *rdev); 564 int btc_dpm_enable(struct radeon_device *rdev); 565 void btc_dpm_disable(struct radeon_device *rdev); 566 int btc_dpm_pre_set_power_state(struct radeon_device *rdev); 567 int btc_dpm_set_power_state(struct radeon_device *rdev); 568 void btc_dpm_post_set_power_state(struct radeon_device *rdev); 569 void btc_dpm_fini(struct radeon_device *rdev); 570 u32 btc_dpm_get_sclk(struct radeon_device *rdev, bool low); 571 u32 btc_dpm_get_mclk(struct radeon_device *rdev, bool low); 572 bool btc_dpm_vblank_too_short(struct radeon_device *rdev); 573 void btc_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 574 struct seq_file *m); 575 u32 btc_dpm_get_current_sclk(struct radeon_device *rdev); 576 u32 btc_dpm_get_current_mclk(struct radeon_device *rdev); 577 int sumo_dpm_init(struct radeon_device *rdev); 578 int sumo_dpm_enable(struct radeon_device *rdev); 579 int sumo_dpm_late_enable(struct radeon_device *rdev); 580 void sumo_dpm_disable(struct radeon_device *rdev); 581 int sumo_dpm_pre_set_power_state(struct radeon_device *rdev); 582 int sumo_dpm_set_power_state(struct radeon_device *rdev); 583 void sumo_dpm_post_set_power_state(struct radeon_device *rdev); 584 void sumo_dpm_setup_asic(struct radeon_device *rdev); 585 void sumo_dpm_display_configuration_changed(struct radeon_device *rdev); 586 void sumo_dpm_fini(struct radeon_device *rdev); 587 u32 sumo_dpm_get_sclk(struct radeon_device *rdev, bool low); 588 u32 sumo_dpm_get_mclk(struct radeon_device *rdev, bool low); 589 void sumo_dpm_print_power_state(struct radeon_device *rdev, 590 struct radeon_ps *ps); 591 void sumo_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 592 struct seq_file *m); 593 int sumo_dpm_force_performance_level(struct radeon_device *rdev, 594 enum radeon_dpm_forced_level level); 595 u32 sumo_dpm_get_current_sclk(struct radeon_device *rdev); 596 u32 sumo_dpm_get_current_mclk(struct radeon_device *rdev); 597 u16 sumo_dpm_get_current_vddc(struct radeon_device *rdev); 598 599 /* 600 * cayman 601 */ 602 void cayman_fence_ring_emit(struct radeon_device *rdev, 603 struct radeon_fence *fence); 604 void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev); 605 int cayman_init(struct radeon_device *rdev); 606 void cayman_fini(struct radeon_device *rdev); 607 int cayman_suspend(struct radeon_device *rdev); 608 int cayman_resume(struct radeon_device *rdev); 609 int cayman_asic_reset(struct radeon_device *rdev, bool hard); 610 void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 611 int cayman_vm_init(struct radeon_device *rdev); 612 void cayman_vm_fini(struct radeon_device *rdev); 613 void cayman_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, 614 unsigned vm_id, uint64_t pd_addr); 615 uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags); 616 int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); 617 int evergreen_dma_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); 618 void cayman_dma_ring_ib_execute(struct radeon_device *rdev, 619 struct radeon_ib *ib); 620 bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 621 bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 622 623 void cayman_dma_vm_copy_pages(struct radeon_device *rdev, 624 struct radeon_ib *ib, 625 uint64_t pe, uint64_t src, 626 unsigned count); 627 void cayman_dma_vm_write_pages(struct radeon_device *rdev, 628 struct radeon_ib *ib, 629 uint64_t pe, 630 uint64_t addr, unsigned count, 631 uint32_t incr, uint32_t flags); 632 void cayman_dma_vm_set_pages(struct radeon_device *rdev, 633 struct radeon_ib *ib, 634 uint64_t pe, 635 uint64_t addr, unsigned count, 636 uint32_t incr, uint32_t flags); 637 void cayman_dma_vm_pad_ib(struct radeon_ib *ib); 638 639 void cayman_dma_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, 640 unsigned vm_id, uint64_t pd_addr); 641 642 u32 cayman_gfx_get_rptr(struct radeon_device *rdev, 643 struct radeon_ring *ring); 644 u32 cayman_gfx_get_wptr(struct radeon_device *rdev, 645 struct radeon_ring *ring); 646 void cayman_gfx_set_wptr(struct radeon_device *rdev, 647 struct radeon_ring *ring); 648 uint32_t cayman_dma_get_rptr(struct radeon_device *rdev, 649 struct radeon_ring *ring); 650 uint32_t cayman_dma_get_wptr(struct radeon_device *rdev, 651 struct radeon_ring *ring); 652 void cayman_dma_set_wptr(struct radeon_device *rdev, 653 struct radeon_ring *ring); 654 int cayman_get_allowed_info_register(struct radeon_device *rdev, 655 u32 reg, u32 *val); 656 657 int ni_dpm_init(struct radeon_device *rdev); 658 void ni_dpm_setup_asic(struct radeon_device *rdev); 659 int ni_dpm_enable(struct radeon_device *rdev); 660 void ni_dpm_disable(struct radeon_device *rdev); 661 int ni_dpm_pre_set_power_state(struct radeon_device *rdev); 662 int ni_dpm_set_power_state(struct radeon_device *rdev); 663 void ni_dpm_post_set_power_state(struct radeon_device *rdev); 664 void ni_dpm_fini(struct radeon_device *rdev); 665 u32 ni_dpm_get_sclk(struct radeon_device *rdev, bool low); 666 u32 ni_dpm_get_mclk(struct radeon_device *rdev, bool low); 667 void ni_dpm_print_power_state(struct radeon_device *rdev, 668 struct radeon_ps *ps); 669 void ni_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 670 struct seq_file *m); 671 int ni_dpm_force_performance_level(struct radeon_device *rdev, 672 enum radeon_dpm_forced_level level); 673 bool ni_dpm_vblank_too_short(struct radeon_device *rdev); 674 u32 ni_dpm_get_current_sclk(struct radeon_device *rdev); 675 u32 ni_dpm_get_current_mclk(struct radeon_device *rdev); 676 int trinity_dpm_init(struct radeon_device *rdev); 677 int trinity_dpm_enable(struct radeon_device *rdev); 678 int trinity_dpm_late_enable(struct radeon_device *rdev); 679 void trinity_dpm_disable(struct radeon_device *rdev); 680 int trinity_dpm_pre_set_power_state(struct radeon_device *rdev); 681 int trinity_dpm_set_power_state(struct radeon_device *rdev); 682 void trinity_dpm_post_set_power_state(struct radeon_device *rdev); 683 void trinity_dpm_setup_asic(struct radeon_device *rdev); 684 void trinity_dpm_display_configuration_changed(struct radeon_device *rdev); 685 void trinity_dpm_fini(struct radeon_device *rdev); 686 u32 trinity_dpm_get_sclk(struct radeon_device *rdev, bool low); 687 u32 trinity_dpm_get_mclk(struct radeon_device *rdev, bool low); 688 void trinity_dpm_print_power_state(struct radeon_device *rdev, 689 struct radeon_ps *ps); 690 void trinity_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 691 struct seq_file *m); 692 int trinity_dpm_force_performance_level(struct radeon_device *rdev, 693 enum radeon_dpm_forced_level level); 694 void trinity_dpm_enable_bapm(struct radeon_device *rdev, bool enable); 695 u32 trinity_dpm_get_current_sclk(struct radeon_device *rdev); 696 u32 trinity_dpm_get_current_mclk(struct radeon_device *rdev); 697 int tn_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk); 698 699 /* DCE6 - SI */ 700 void dce6_bandwidth_update(struct radeon_device *rdev); 701 void dce6_audio_fini(struct radeon_device *rdev); 702 703 /* 704 * si 705 */ 706 void si_fence_ring_emit(struct radeon_device *rdev, 707 struct radeon_fence *fence); 708 void si_pcie_gart_tlb_flush(struct radeon_device *rdev); 709 int si_init(struct radeon_device *rdev); 710 void si_fini(struct radeon_device *rdev); 711 int si_suspend(struct radeon_device *rdev); 712 int si_resume(struct radeon_device *rdev); 713 bool si_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 714 bool si_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 715 int si_asic_reset(struct radeon_device *rdev, bool hard); 716 void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 717 int si_irq_set(struct radeon_device *rdev); 718 int si_irq_process(struct radeon_device *rdev); 719 int si_vm_init(struct radeon_device *rdev); 720 void si_vm_fini(struct radeon_device *rdev); 721 void si_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, 722 unsigned vm_id, uint64_t pd_addr); 723 int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); 724 struct radeon_fence *si_copy_dma(struct radeon_device *rdev, 725 uint64_t src_offset, uint64_t dst_offset, 726 unsigned num_gpu_pages, 727 struct dma_resv *resv); 728 729 void si_dma_vm_copy_pages(struct radeon_device *rdev, 730 struct radeon_ib *ib, 731 uint64_t pe, uint64_t src, 732 unsigned count); 733 void si_dma_vm_write_pages(struct radeon_device *rdev, 734 struct radeon_ib *ib, 735 uint64_t pe, 736 uint64_t addr, unsigned count, 737 uint32_t incr, uint32_t flags); 738 void si_dma_vm_set_pages(struct radeon_device *rdev, 739 struct radeon_ib *ib, 740 uint64_t pe, 741 uint64_t addr, unsigned count, 742 uint32_t incr, uint32_t flags); 743 744 void si_dma_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, 745 unsigned vm_id, uint64_t pd_addr); 746 u32 si_get_xclk(struct radeon_device *rdev); 747 uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev); 748 int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); 749 int si_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk); 750 int si_get_temp(struct radeon_device *rdev); 751 int si_get_allowed_info_register(struct radeon_device *rdev, 752 u32 reg, u32 *val); 753 int si_dpm_init(struct radeon_device *rdev); 754 void si_dpm_setup_asic(struct radeon_device *rdev); 755 int si_dpm_enable(struct radeon_device *rdev); 756 int si_dpm_late_enable(struct radeon_device *rdev); 757 void si_dpm_disable(struct radeon_device *rdev); 758 int si_dpm_pre_set_power_state(struct radeon_device *rdev); 759 int si_dpm_set_power_state(struct radeon_device *rdev); 760 void si_dpm_post_set_power_state(struct radeon_device *rdev); 761 void si_dpm_fini(struct radeon_device *rdev); 762 void si_dpm_display_configuration_changed(struct radeon_device *rdev); 763 void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 764 struct seq_file *m); 765 int si_dpm_force_performance_level(struct radeon_device *rdev, 766 enum radeon_dpm_forced_level level); 767 int si_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev, 768 u32 *speed); 769 int si_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev, 770 u32 speed); 771 u32 si_fan_ctrl_get_mode(struct radeon_device *rdev); 772 void si_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode); 773 u32 si_dpm_get_current_sclk(struct radeon_device *rdev); 774 u32 si_dpm_get_current_mclk(struct radeon_device *rdev); 775 776 /* DCE8 - CIK */ 777 void dce8_bandwidth_update(struct radeon_device *rdev); 778 779 /* 780 * cik 781 */ 782 uint64_t cik_get_gpu_clock_counter(struct radeon_device *rdev); 783 u32 cik_get_xclk(struct radeon_device *rdev); 784 uint32_t cik_pciep_rreg(struct radeon_device *rdev, uint32_t reg); 785 void cik_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 786 int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); 787 int cik_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk); 788 void cik_sdma_fence_ring_emit(struct radeon_device *rdev, 789 struct radeon_fence *fence); 790 bool cik_sdma_semaphore_ring_emit(struct radeon_device *rdev, 791 struct radeon_ring *ring, 792 struct radeon_semaphore *semaphore, 793 bool emit_wait); 794 void cik_sdma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 795 struct radeon_fence *cik_copy_dma(struct radeon_device *rdev, 796 uint64_t src_offset, uint64_t dst_offset, 797 unsigned num_gpu_pages, 798 struct dma_resv *resv); 799 struct radeon_fence *cik_copy_cpdma(struct radeon_device *rdev, 800 uint64_t src_offset, uint64_t dst_offset, 801 unsigned num_gpu_pages, 802 struct dma_resv *resv); 803 int cik_sdma_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); 804 int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 805 bool cik_sdma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 806 void cik_fence_gfx_ring_emit(struct radeon_device *rdev, 807 struct radeon_fence *fence); 808 void cik_fence_compute_ring_emit(struct radeon_device *rdev, 809 struct radeon_fence *fence); 810 bool cik_semaphore_ring_emit(struct radeon_device *rdev, 811 struct radeon_ring *cp, 812 struct radeon_semaphore *semaphore, 813 bool emit_wait); 814 void cik_pcie_gart_tlb_flush(struct radeon_device *rdev); 815 int cik_init(struct radeon_device *rdev); 816 void cik_fini(struct radeon_device *rdev); 817 int cik_suspend(struct radeon_device *rdev); 818 int cik_resume(struct radeon_device *rdev); 819 bool cik_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 820 int cik_asic_reset(struct radeon_device *rdev, bool hard); 821 void cik_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 822 int cik_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); 823 int cik_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 824 int cik_irq_set(struct radeon_device *rdev); 825 int cik_irq_process(struct radeon_device *rdev); 826 int cik_vm_init(struct radeon_device *rdev); 827 void cik_vm_fini(struct radeon_device *rdev); 828 void cik_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, 829 unsigned vm_id, uint64_t pd_addr); 830 831 void cik_sdma_vm_copy_pages(struct radeon_device *rdev, 832 struct radeon_ib *ib, 833 uint64_t pe, uint64_t src, 834 unsigned count); 835 void cik_sdma_vm_write_pages(struct radeon_device *rdev, 836 struct radeon_ib *ib, 837 uint64_t pe, 838 uint64_t addr, unsigned count, 839 uint32_t incr, uint32_t flags); 840 void cik_sdma_vm_set_pages(struct radeon_device *rdev, 841 struct radeon_ib *ib, 842 uint64_t pe, 843 uint64_t addr, unsigned count, 844 uint32_t incr, uint32_t flags); 845 void cik_sdma_vm_pad_ib(struct radeon_ib *ib); 846 847 void cik_dma_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, 848 unsigned vm_id, uint64_t pd_addr); 849 int cik_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); 850 u32 cik_gfx_get_rptr(struct radeon_device *rdev, 851 struct radeon_ring *ring); 852 u32 cik_gfx_get_wptr(struct radeon_device *rdev, 853 struct radeon_ring *ring); 854 void cik_gfx_set_wptr(struct radeon_device *rdev, 855 struct radeon_ring *ring); 856 u32 cik_compute_get_rptr(struct radeon_device *rdev, 857 struct radeon_ring *ring); 858 u32 cik_compute_get_wptr(struct radeon_device *rdev, 859 struct radeon_ring *ring); 860 void cik_compute_set_wptr(struct radeon_device *rdev, 861 struct radeon_ring *ring); 862 u32 cik_sdma_get_rptr(struct radeon_device *rdev, 863 struct radeon_ring *ring); 864 u32 cik_sdma_get_wptr(struct radeon_device *rdev, 865 struct radeon_ring *ring); 866 void cik_sdma_set_wptr(struct radeon_device *rdev, 867 struct radeon_ring *ring); 868 int ci_get_temp(struct radeon_device *rdev); 869 int kv_get_temp(struct radeon_device *rdev); 870 int cik_get_allowed_info_register(struct radeon_device *rdev, 871 u32 reg, u32 *val); 872 873 int ci_dpm_init(struct radeon_device *rdev); 874 int ci_dpm_enable(struct radeon_device *rdev); 875 int ci_dpm_late_enable(struct radeon_device *rdev); 876 void ci_dpm_disable(struct radeon_device *rdev); 877 int ci_dpm_pre_set_power_state(struct radeon_device *rdev); 878 int ci_dpm_set_power_state(struct radeon_device *rdev); 879 void ci_dpm_post_set_power_state(struct radeon_device *rdev); 880 void ci_dpm_setup_asic(struct radeon_device *rdev); 881 void ci_dpm_display_configuration_changed(struct radeon_device *rdev); 882 void ci_dpm_fini(struct radeon_device *rdev); 883 u32 ci_dpm_get_sclk(struct radeon_device *rdev, bool low); 884 u32 ci_dpm_get_mclk(struct radeon_device *rdev, bool low); 885 void ci_dpm_print_power_state(struct radeon_device *rdev, 886 struct radeon_ps *ps); 887 void ci_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 888 struct seq_file *m); 889 int ci_dpm_force_performance_level(struct radeon_device *rdev, 890 enum radeon_dpm_forced_level level); 891 bool ci_dpm_vblank_too_short(struct radeon_device *rdev); 892 void ci_dpm_powergate_uvd(struct radeon_device *rdev, bool gate); 893 u32 ci_dpm_get_current_sclk(struct radeon_device *rdev); 894 u32 ci_dpm_get_current_mclk(struct radeon_device *rdev); 895 896 int ci_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev, 897 u32 *speed); 898 int ci_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev, 899 u32 speed); 900 u32 ci_fan_ctrl_get_mode(struct radeon_device *rdev); 901 void ci_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode); 902 903 int kv_dpm_init(struct radeon_device *rdev); 904 int kv_dpm_enable(struct radeon_device *rdev); 905 int kv_dpm_late_enable(struct radeon_device *rdev); 906 void kv_dpm_disable(struct radeon_device *rdev); 907 int kv_dpm_pre_set_power_state(struct radeon_device *rdev); 908 int kv_dpm_set_power_state(struct radeon_device *rdev); 909 void kv_dpm_post_set_power_state(struct radeon_device *rdev); 910 void kv_dpm_setup_asic(struct radeon_device *rdev); 911 void kv_dpm_display_configuration_changed(struct radeon_device *rdev); 912 void kv_dpm_fini(struct radeon_device *rdev); 913 u32 kv_dpm_get_sclk(struct radeon_device *rdev, bool low); 914 u32 kv_dpm_get_mclk(struct radeon_device *rdev, bool low); 915 void kv_dpm_print_power_state(struct radeon_device *rdev, 916 struct radeon_ps *ps); 917 void kv_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 918 struct seq_file *m); 919 int kv_dpm_force_performance_level(struct radeon_device *rdev, 920 enum radeon_dpm_forced_level level); 921 void kv_dpm_powergate_uvd(struct radeon_device *rdev, bool gate); 922 void kv_dpm_enable_bapm(struct radeon_device *rdev, bool enable); 923 u32 kv_dpm_get_current_sclk(struct radeon_device *rdev); 924 u32 kv_dpm_get_current_mclk(struct radeon_device *rdev); 925 926 /* uvd v1.0 */ 927 uint32_t uvd_v1_0_get_rptr(struct radeon_device *rdev, 928 struct radeon_ring *ring); 929 uint32_t uvd_v1_0_get_wptr(struct radeon_device *rdev, 930 struct radeon_ring *ring); 931 void uvd_v1_0_set_wptr(struct radeon_device *rdev, 932 struct radeon_ring *ring); 933 int uvd_v1_0_resume(struct radeon_device *rdev); 934 935 int uvd_v1_0_init(struct radeon_device *rdev); 936 void uvd_v1_0_fini(struct radeon_device *rdev); 937 int uvd_v1_0_start(struct radeon_device *rdev); 938 void uvd_v1_0_stop(struct radeon_device *rdev); 939 940 int uvd_v1_0_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); 941 void uvd_v1_0_fence_emit(struct radeon_device *rdev, 942 struct radeon_fence *fence); 943 int uvd_v1_0_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 944 bool uvd_v1_0_semaphore_emit(struct radeon_device *rdev, 945 struct radeon_ring *ring, 946 struct radeon_semaphore *semaphore, 947 bool emit_wait); 948 void uvd_v1_0_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 949 950 /* uvd v2.2 */ 951 int uvd_v2_2_resume(struct radeon_device *rdev); 952 void uvd_v2_2_fence_emit(struct radeon_device *rdev, 953 struct radeon_fence *fence); 954 bool uvd_v2_2_semaphore_emit(struct radeon_device *rdev, 955 struct radeon_ring *ring, 956 struct radeon_semaphore *semaphore, 957 bool emit_wait); 958 959 /* uvd v3.1 */ 960 bool uvd_v3_1_semaphore_emit(struct radeon_device *rdev, 961 struct radeon_ring *ring, 962 struct radeon_semaphore *semaphore, 963 bool emit_wait); 964 965 /* uvd v4.2 */ 966 int uvd_v4_2_resume(struct radeon_device *rdev); 967 968 /* vce v1.0 */ 969 uint32_t vce_v1_0_get_rptr(struct radeon_device *rdev, 970 struct radeon_ring *ring); 971 uint32_t vce_v1_0_get_wptr(struct radeon_device *rdev, 972 struct radeon_ring *ring); 973 void vce_v1_0_set_wptr(struct radeon_device *rdev, 974 struct radeon_ring *ring); 975 int vce_v1_0_load_fw(struct radeon_device *rdev, uint32_t *data); 976 unsigned vce_v1_0_bo_size(struct radeon_device *rdev); 977 int vce_v1_0_resume(struct radeon_device *rdev); 978 int vce_v1_0_init(struct radeon_device *rdev); 979 int vce_v1_0_start(struct radeon_device *rdev); 980 981 /* vce v2.0 */ 982 unsigned vce_v2_0_bo_size(struct radeon_device *rdev); 983 int vce_v2_0_resume(struct radeon_device *rdev); 984 985 #endif 986