1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include <linux/console.h> 30 #include <drm/drmP.h> 31 #include <drm/drm_crtc_helper.h> 32 #include <drm/radeon_drm.h> 33 #include <linux/vgaarb.h> 34 #include <linux/vga_switcheroo.h> 35 #include "radeon_reg.h" 36 #include "radeon.h" 37 #include "radeon_asic.h" 38 #include "atom.h" 39 40 /* 41 * Registers accessors functions. 42 */ 43 /** 44 * radeon_invalid_rreg - dummy reg read function 45 * 46 * @rdev: radeon device pointer 47 * @reg: offset of register 48 * 49 * Dummy register read function. Used for register blocks 50 * that certain asics don't have (all asics). 51 * Returns the value in the register. 52 */ 53 static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg) 54 { 55 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); 56 BUG_ON(1); 57 return 0; 58 } 59 60 /** 61 * radeon_invalid_wreg - dummy reg write function 62 * 63 * @rdev: radeon device pointer 64 * @reg: offset of register 65 * @v: value to write to the register 66 * 67 * Dummy register read function. Used for register blocks 68 * that certain asics don't have (all asics). 69 */ 70 static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 71 { 72 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", 73 reg, v); 74 BUG_ON(1); 75 } 76 77 /** 78 * radeon_register_accessor_init - sets up the register accessor callbacks 79 * 80 * @rdev: radeon device pointer 81 * 82 * Sets up the register accessor callbacks for various register 83 * apertures. Not all asics have all apertures (all asics). 84 */ 85 static void radeon_register_accessor_init(struct radeon_device *rdev) 86 { 87 rdev->mc_rreg = &radeon_invalid_rreg; 88 rdev->mc_wreg = &radeon_invalid_wreg; 89 rdev->pll_rreg = &radeon_invalid_rreg; 90 rdev->pll_wreg = &radeon_invalid_wreg; 91 rdev->pciep_rreg = &radeon_invalid_rreg; 92 rdev->pciep_wreg = &radeon_invalid_wreg; 93 94 /* Don't change order as we are overridding accessor. */ 95 if (rdev->family < CHIP_RV515) { 96 rdev->pcie_reg_mask = 0xff; 97 } else { 98 rdev->pcie_reg_mask = 0x7ff; 99 } 100 /* FIXME: not sure here */ 101 if (rdev->family <= CHIP_R580) { 102 rdev->pll_rreg = &r100_pll_rreg; 103 rdev->pll_wreg = &r100_pll_wreg; 104 } 105 if (rdev->family >= CHIP_R420) { 106 rdev->mc_rreg = &r420_mc_rreg; 107 rdev->mc_wreg = &r420_mc_wreg; 108 } 109 if (rdev->family >= CHIP_RV515) { 110 rdev->mc_rreg = &rv515_mc_rreg; 111 rdev->mc_wreg = &rv515_mc_wreg; 112 } 113 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) { 114 rdev->mc_rreg = &rs400_mc_rreg; 115 rdev->mc_wreg = &rs400_mc_wreg; 116 } 117 if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { 118 rdev->mc_rreg = &rs690_mc_rreg; 119 rdev->mc_wreg = &rs690_mc_wreg; 120 } 121 if (rdev->family == CHIP_RS600) { 122 rdev->mc_rreg = &rs600_mc_rreg; 123 rdev->mc_wreg = &rs600_mc_wreg; 124 } 125 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) { 126 rdev->mc_rreg = &rs780_mc_rreg; 127 rdev->mc_wreg = &rs780_mc_wreg; 128 } 129 130 if (rdev->family >= CHIP_BONAIRE) { 131 rdev->pciep_rreg = &cik_pciep_rreg; 132 rdev->pciep_wreg = &cik_pciep_wreg; 133 } else if (rdev->family >= CHIP_R600) { 134 rdev->pciep_rreg = &r600_pciep_rreg; 135 rdev->pciep_wreg = &r600_pciep_wreg; 136 } 137 } 138 139 140 /* helper to disable agp */ 141 /** 142 * radeon_agp_disable - AGP disable helper function 143 * 144 * @rdev: radeon device pointer 145 * 146 * Removes AGP flags and changes the gart callbacks on AGP 147 * cards when using the internal gart rather than AGP (all asics). 148 */ 149 void radeon_agp_disable(struct radeon_device *rdev) 150 { 151 rdev->flags &= ~RADEON_IS_AGP; 152 if (rdev->family >= CHIP_R600) { 153 DRM_INFO("Forcing AGP to PCIE mode\n"); 154 rdev->flags |= RADEON_IS_PCIE; 155 } else if (rdev->family >= CHIP_RV515 || 156 rdev->family == CHIP_RV380 || 157 rdev->family == CHIP_RV410 || 158 rdev->family == CHIP_R423) { 159 DRM_INFO("Forcing AGP to PCIE mode\n"); 160 rdev->flags |= RADEON_IS_PCIE; 161 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush; 162 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page; 163 } else { 164 DRM_INFO("Forcing AGP to PCI mode\n"); 165 rdev->flags |= RADEON_IS_PCI; 166 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush; 167 rdev->asic->gart.set_page = &r100_pci_gart_set_page; 168 } 169 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; 170 } 171 172 /* 173 * ASIC 174 */ 175 static struct radeon_asic r100_asic = { 176 .init = &r100_init, 177 .fini = &r100_fini, 178 .suspend = &r100_suspend, 179 .resume = &r100_resume, 180 .vga_set_state = &r100_vga_set_state, 181 .asic_reset = &r100_asic_reset, 182 .ioctl_wait_idle = NULL, 183 .gui_idle = &r100_gui_idle, 184 .mc_wait_for_idle = &r100_mc_wait_for_idle, 185 .gart = { 186 .tlb_flush = &r100_pci_gart_tlb_flush, 187 .set_page = &r100_pci_gart_set_page, 188 }, 189 .ring = { 190 [RADEON_RING_TYPE_GFX_INDEX] = { 191 .ib_execute = &r100_ring_ib_execute, 192 .emit_fence = &r100_fence_ring_emit, 193 .emit_semaphore = &r100_semaphore_ring_emit, 194 .cs_parse = &r100_cs_parse, 195 .ring_start = &r100_ring_start, 196 .ring_test = &r100_ring_test, 197 .ib_test = &r100_ib_test, 198 .is_lockup = &r100_gpu_is_lockup, 199 .get_rptr = &radeon_ring_generic_get_rptr, 200 .get_wptr = &radeon_ring_generic_get_wptr, 201 .set_wptr = &radeon_ring_generic_set_wptr, 202 } 203 }, 204 .irq = { 205 .set = &r100_irq_set, 206 .process = &r100_irq_process, 207 }, 208 .display = { 209 .bandwidth_update = &r100_bandwidth_update, 210 .get_vblank_counter = &r100_get_vblank_counter, 211 .wait_for_vblank = &r100_wait_for_vblank, 212 .set_backlight_level = &radeon_legacy_set_backlight_level, 213 .get_backlight_level = &radeon_legacy_get_backlight_level, 214 }, 215 .copy = { 216 .blit = &r100_copy_blit, 217 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 218 .dma = NULL, 219 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 220 .copy = &r100_copy_blit, 221 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 222 }, 223 .surface = { 224 .set_reg = r100_set_surface_reg, 225 .clear_reg = r100_clear_surface_reg, 226 }, 227 .hpd = { 228 .init = &r100_hpd_init, 229 .fini = &r100_hpd_fini, 230 .sense = &r100_hpd_sense, 231 .set_polarity = &r100_hpd_set_polarity, 232 }, 233 .pm = { 234 .misc = &r100_pm_misc, 235 .prepare = &r100_pm_prepare, 236 .finish = &r100_pm_finish, 237 .init_profile = &r100_pm_init_profile, 238 .get_dynpm_state = &r100_pm_get_dynpm_state, 239 .get_engine_clock = &radeon_legacy_get_engine_clock, 240 .set_engine_clock = &radeon_legacy_set_engine_clock, 241 .get_memory_clock = &radeon_legacy_get_memory_clock, 242 .set_memory_clock = NULL, 243 .get_pcie_lanes = NULL, 244 .set_pcie_lanes = NULL, 245 .set_clock_gating = &radeon_legacy_set_clock_gating, 246 }, 247 .pflip = { 248 .pre_page_flip = &r100_pre_page_flip, 249 .page_flip = &r100_page_flip, 250 .post_page_flip = &r100_post_page_flip, 251 }, 252 }; 253 254 static struct radeon_asic r200_asic = { 255 .init = &r100_init, 256 .fini = &r100_fini, 257 .suspend = &r100_suspend, 258 .resume = &r100_resume, 259 .vga_set_state = &r100_vga_set_state, 260 .asic_reset = &r100_asic_reset, 261 .ioctl_wait_idle = NULL, 262 .gui_idle = &r100_gui_idle, 263 .mc_wait_for_idle = &r100_mc_wait_for_idle, 264 .gart = { 265 .tlb_flush = &r100_pci_gart_tlb_flush, 266 .set_page = &r100_pci_gart_set_page, 267 }, 268 .ring = { 269 [RADEON_RING_TYPE_GFX_INDEX] = { 270 .ib_execute = &r100_ring_ib_execute, 271 .emit_fence = &r100_fence_ring_emit, 272 .emit_semaphore = &r100_semaphore_ring_emit, 273 .cs_parse = &r100_cs_parse, 274 .ring_start = &r100_ring_start, 275 .ring_test = &r100_ring_test, 276 .ib_test = &r100_ib_test, 277 .is_lockup = &r100_gpu_is_lockup, 278 .get_rptr = &radeon_ring_generic_get_rptr, 279 .get_wptr = &radeon_ring_generic_get_wptr, 280 .set_wptr = &radeon_ring_generic_set_wptr, 281 } 282 }, 283 .irq = { 284 .set = &r100_irq_set, 285 .process = &r100_irq_process, 286 }, 287 .display = { 288 .bandwidth_update = &r100_bandwidth_update, 289 .get_vblank_counter = &r100_get_vblank_counter, 290 .wait_for_vblank = &r100_wait_for_vblank, 291 .set_backlight_level = &radeon_legacy_set_backlight_level, 292 .get_backlight_level = &radeon_legacy_get_backlight_level, 293 }, 294 .copy = { 295 .blit = &r100_copy_blit, 296 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 297 .dma = &r200_copy_dma, 298 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 299 .copy = &r100_copy_blit, 300 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 301 }, 302 .surface = { 303 .set_reg = r100_set_surface_reg, 304 .clear_reg = r100_clear_surface_reg, 305 }, 306 .hpd = { 307 .init = &r100_hpd_init, 308 .fini = &r100_hpd_fini, 309 .sense = &r100_hpd_sense, 310 .set_polarity = &r100_hpd_set_polarity, 311 }, 312 .pm = { 313 .misc = &r100_pm_misc, 314 .prepare = &r100_pm_prepare, 315 .finish = &r100_pm_finish, 316 .init_profile = &r100_pm_init_profile, 317 .get_dynpm_state = &r100_pm_get_dynpm_state, 318 .get_engine_clock = &radeon_legacy_get_engine_clock, 319 .set_engine_clock = &radeon_legacy_set_engine_clock, 320 .get_memory_clock = &radeon_legacy_get_memory_clock, 321 .set_memory_clock = NULL, 322 .get_pcie_lanes = NULL, 323 .set_pcie_lanes = NULL, 324 .set_clock_gating = &radeon_legacy_set_clock_gating, 325 }, 326 .pflip = { 327 .pre_page_flip = &r100_pre_page_flip, 328 .page_flip = &r100_page_flip, 329 .post_page_flip = &r100_post_page_flip, 330 }, 331 }; 332 333 static struct radeon_asic r300_asic = { 334 .init = &r300_init, 335 .fini = &r300_fini, 336 .suspend = &r300_suspend, 337 .resume = &r300_resume, 338 .vga_set_state = &r100_vga_set_state, 339 .asic_reset = &r300_asic_reset, 340 .ioctl_wait_idle = NULL, 341 .gui_idle = &r100_gui_idle, 342 .mc_wait_for_idle = &r300_mc_wait_for_idle, 343 .gart = { 344 .tlb_flush = &r100_pci_gart_tlb_flush, 345 .set_page = &r100_pci_gart_set_page, 346 }, 347 .ring = { 348 [RADEON_RING_TYPE_GFX_INDEX] = { 349 .ib_execute = &r100_ring_ib_execute, 350 .emit_fence = &r300_fence_ring_emit, 351 .emit_semaphore = &r100_semaphore_ring_emit, 352 .cs_parse = &r300_cs_parse, 353 .ring_start = &r300_ring_start, 354 .ring_test = &r100_ring_test, 355 .ib_test = &r100_ib_test, 356 .is_lockup = &r100_gpu_is_lockup, 357 .get_rptr = &radeon_ring_generic_get_rptr, 358 .get_wptr = &radeon_ring_generic_get_wptr, 359 .set_wptr = &radeon_ring_generic_set_wptr, 360 } 361 }, 362 .irq = { 363 .set = &r100_irq_set, 364 .process = &r100_irq_process, 365 }, 366 .display = { 367 .bandwidth_update = &r100_bandwidth_update, 368 .get_vblank_counter = &r100_get_vblank_counter, 369 .wait_for_vblank = &r100_wait_for_vblank, 370 .set_backlight_level = &radeon_legacy_set_backlight_level, 371 .get_backlight_level = &radeon_legacy_get_backlight_level, 372 }, 373 .copy = { 374 .blit = &r100_copy_blit, 375 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 376 .dma = &r200_copy_dma, 377 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 378 .copy = &r100_copy_blit, 379 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 380 }, 381 .surface = { 382 .set_reg = r100_set_surface_reg, 383 .clear_reg = r100_clear_surface_reg, 384 }, 385 .hpd = { 386 .init = &r100_hpd_init, 387 .fini = &r100_hpd_fini, 388 .sense = &r100_hpd_sense, 389 .set_polarity = &r100_hpd_set_polarity, 390 }, 391 .pm = { 392 .misc = &r100_pm_misc, 393 .prepare = &r100_pm_prepare, 394 .finish = &r100_pm_finish, 395 .init_profile = &r100_pm_init_profile, 396 .get_dynpm_state = &r100_pm_get_dynpm_state, 397 .get_engine_clock = &radeon_legacy_get_engine_clock, 398 .set_engine_clock = &radeon_legacy_set_engine_clock, 399 .get_memory_clock = &radeon_legacy_get_memory_clock, 400 .set_memory_clock = NULL, 401 .get_pcie_lanes = &rv370_get_pcie_lanes, 402 .set_pcie_lanes = &rv370_set_pcie_lanes, 403 .set_clock_gating = &radeon_legacy_set_clock_gating, 404 }, 405 .pflip = { 406 .pre_page_flip = &r100_pre_page_flip, 407 .page_flip = &r100_page_flip, 408 .post_page_flip = &r100_post_page_flip, 409 }, 410 }; 411 412 static struct radeon_asic r300_asic_pcie = { 413 .init = &r300_init, 414 .fini = &r300_fini, 415 .suspend = &r300_suspend, 416 .resume = &r300_resume, 417 .vga_set_state = &r100_vga_set_state, 418 .asic_reset = &r300_asic_reset, 419 .ioctl_wait_idle = NULL, 420 .gui_idle = &r100_gui_idle, 421 .mc_wait_for_idle = &r300_mc_wait_for_idle, 422 .gart = { 423 .tlb_flush = &rv370_pcie_gart_tlb_flush, 424 .set_page = &rv370_pcie_gart_set_page, 425 }, 426 .ring = { 427 [RADEON_RING_TYPE_GFX_INDEX] = { 428 .ib_execute = &r100_ring_ib_execute, 429 .emit_fence = &r300_fence_ring_emit, 430 .emit_semaphore = &r100_semaphore_ring_emit, 431 .cs_parse = &r300_cs_parse, 432 .ring_start = &r300_ring_start, 433 .ring_test = &r100_ring_test, 434 .ib_test = &r100_ib_test, 435 .is_lockup = &r100_gpu_is_lockup, 436 .get_rptr = &radeon_ring_generic_get_rptr, 437 .get_wptr = &radeon_ring_generic_get_wptr, 438 .set_wptr = &radeon_ring_generic_set_wptr, 439 } 440 }, 441 .irq = { 442 .set = &r100_irq_set, 443 .process = &r100_irq_process, 444 }, 445 .display = { 446 .bandwidth_update = &r100_bandwidth_update, 447 .get_vblank_counter = &r100_get_vblank_counter, 448 .wait_for_vblank = &r100_wait_for_vblank, 449 .set_backlight_level = &radeon_legacy_set_backlight_level, 450 .get_backlight_level = &radeon_legacy_get_backlight_level, 451 }, 452 .copy = { 453 .blit = &r100_copy_blit, 454 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 455 .dma = &r200_copy_dma, 456 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 457 .copy = &r100_copy_blit, 458 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 459 }, 460 .surface = { 461 .set_reg = r100_set_surface_reg, 462 .clear_reg = r100_clear_surface_reg, 463 }, 464 .hpd = { 465 .init = &r100_hpd_init, 466 .fini = &r100_hpd_fini, 467 .sense = &r100_hpd_sense, 468 .set_polarity = &r100_hpd_set_polarity, 469 }, 470 .pm = { 471 .misc = &r100_pm_misc, 472 .prepare = &r100_pm_prepare, 473 .finish = &r100_pm_finish, 474 .init_profile = &r100_pm_init_profile, 475 .get_dynpm_state = &r100_pm_get_dynpm_state, 476 .get_engine_clock = &radeon_legacy_get_engine_clock, 477 .set_engine_clock = &radeon_legacy_set_engine_clock, 478 .get_memory_clock = &radeon_legacy_get_memory_clock, 479 .set_memory_clock = NULL, 480 .get_pcie_lanes = &rv370_get_pcie_lanes, 481 .set_pcie_lanes = &rv370_set_pcie_lanes, 482 .set_clock_gating = &radeon_legacy_set_clock_gating, 483 }, 484 .pflip = { 485 .pre_page_flip = &r100_pre_page_flip, 486 .page_flip = &r100_page_flip, 487 .post_page_flip = &r100_post_page_flip, 488 }, 489 }; 490 491 static struct radeon_asic r420_asic = { 492 .init = &r420_init, 493 .fini = &r420_fini, 494 .suspend = &r420_suspend, 495 .resume = &r420_resume, 496 .vga_set_state = &r100_vga_set_state, 497 .asic_reset = &r300_asic_reset, 498 .ioctl_wait_idle = NULL, 499 .gui_idle = &r100_gui_idle, 500 .mc_wait_for_idle = &r300_mc_wait_for_idle, 501 .gart = { 502 .tlb_flush = &rv370_pcie_gart_tlb_flush, 503 .set_page = &rv370_pcie_gart_set_page, 504 }, 505 .ring = { 506 [RADEON_RING_TYPE_GFX_INDEX] = { 507 .ib_execute = &r100_ring_ib_execute, 508 .emit_fence = &r300_fence_ring_emit, 509 .emit_semaphore = &r100_semaphore_ring_emit, 510 .cs_parse = &r300_cs_parse, 511 .ring_start = &r300_ring_start, 512 .ring_test = &r100_ring_test, 513 .ib_test = &r100_ib_test, 514 .is_lockup = &r100_gpu_is_lockup, 515 .get_rptr = &radeon_ring_generic_get_rptr, 516 .get_wptr = &radeon_ring_generic_get_wptr, 517 .set_wptr = &radeon_ring_generic_set_wptr, 518 } 519 }, 520 .irq = { 521 .set = &r100_irq_set, 522 .process = &r100_irq_process, 523 }, 524 .display = { 525 .bandwidth_update = &r100_bandwidth_update, 526 .get_vblank_counter = &r100_get_vblank_counter, 527 .wait_for_vblank = &r100_wait_for_vblank, 528 .set_backlight_level = &atombios_set_backlight_level, 529 .get_backlight_level = &atombios_get_backlight_level, 530 }, 531 .copy = { 532 .blit = &r100_copy_blit, 533 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 534 .dma = &r200_copy_dma, 535 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 536 .copy = &r100_copy_blit, 537 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 538 }, 539 .surface = { 540 .set_reg = r100_set_surface_reg, 541 .clear_reg = r100_clear_surface_reg, 542 }, 543 .hpd = { 544 .init = &r100_hpd_init, 545 .fini = &r100_hpd_fini, 546 .sense = &r100_hpd_sense, 547 .set_polarity = &r100_hpd_set_polarity, 548 }, 549 .pm = { 550 .misc = &r100_pm_misc, 551 .prepare = &r100_pm_prepare, 552 .finish = &r100_pm_finish, 553 .init_profile = &r420_pm_init_profile, 554 .get_dynpm_state = &r100_pm_get_dynpm_state, 555 .get_engine_clock = &radeon_atom_get_engine_clock, 556 .set_engine_clock = &radeon_atom_set_engine_clock, 557 .get_memory_clock = &radeon_atom_get_memory_clock, 558 .set_memory_clock = &radeon_atom_set_memory_clock, 559 .get_pcie_lanes = &rv370_get_pcie_lanes, 560 .set_pcie_lanes = &rv370_set_pcie_lanes, 561 .set_clock_gating = &radeon_atom_set_clock_gating, 562 }, 563 .pflip = { 564 .pre_page_flip = &r100_pre_page_flip, 565 .page_flip = &r100_page_flip, 566 .post_page_flip = &r100_post_page_flip, 567 }, 568 }; 569 570 static struct radeon_asic rs400_asic = { 571 .init = &rs400_init, 572 .fini = &rs400_fini, 573 .suspend = &rs400_suspend, 574 .resume = &rs400_resume, 575 .vga_set_state = &r100_vga_set_state, 576 .asic_reset = &r300_asic_reset, 577 .ioctl_wait_idle = NULL, 578 .gui_idle = &r100_gui_idle, 579 .mc_wait_for_idle = &rs400_mc_wait_for_idle, 580 .gart = { 581 .tlb_flush = &rs400_gart_tlb_flush, 582 .set_page = &rs400_gart_set_page, 583 }, 584 .ring = { 585 [RADEON_RING_TYPE_GFX_INDEX] = { 586 .ib_execute = &r100_ring_ib_execute, 587 .emit_fence = &r300_fence_ring_emit, 588 .emit_semaphore = &r100_semaphore_ring_emit, 589 .cs_parse = &r300_cs_parse, 590 .ring_start = &r300_ring_start, 591 .ring_test = &r100_ring_test, 592 .ib_test = &r100_ib_test, 593 .is_lockup = &r100_gpu_is_lockup, 594 .get_rptr = &radeon_ring_generic_get_rptr, 595 .get_wptr = &radeon_ring_generic_get_wptr, 596 .set_wptr = &radeon_ring_generic_set_wptr, 597 } 598 }, 599 .irq = { 600 .set = &r100_irq_set, 601 .process = &r100_irq_process, 602 }, 603 .display = { 604 .bandwidth_update = &r100_bandwidth_update, 605 .get_vblank_counter = &r100_get_vblank_counter, 606 .wait_for_vblank = &r100_wait_for_vblank, 607 .set_backlight_level = &radeon_legacy_set_backlight_level, 608 .get_backlight_level = &radeon_legacy_get_backlight_level, 609 }, 610 .copy = { 611 .blit = &r100_copy_blit, 612 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 613 .dma = &r200_copy_dma, 614 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 615 .copy = &r100_copy_blit, 616 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 617 }, 618 .surface = { 619 .set_reg = r100_set_surface_reg, 620 .clear_reg = r100_clear_surface_reg, 621 }, 622 .hpd = { 623 .init = &r100_hpd_init, 624 .fini = &r100_hpd_fini, 625 .sense = &r100_hpd_sense, 626 .set_polarity = &r100_hpd_set_polarity, 627 }, 628 .pm = { 629 .misc = &r100_pm_misc, 630 .prepare = &r100_pm_prepare, 631 .finish = &r100_pm_finish, 632 .init_profile = &r100_pm_init_profile, 633 .get_dynpm_state = &r100_pm_get_dynpm_state, 634 .get_engine_clock = &radeon_legacy_get_engine_clock, 635 .set_engine_clock = &radeon_legacy_set_engine_clock, 636 .get_memory_clock = &radeon_legacy_get_memory_clock, 637 .set_memory_clock = NULL, 638 .get_pcie_lanes = NULL, 639 .set_pcie_lanes = NULL, 640 .set_clock_gating = &radeon_legacy_set_clock_gating, 641 }, 642 .pflip = { 643 .pre_page_flip = &r100_pre_page_flip, 644 .page_flip = &r100_page_flip, 645 .post_page_flip = &r100_post_page_flip, 646 }, 647 }; 648 649 static struct radeon_asic rs600_asic = { 650 .init = &rs600_init, 651 .fini = &rs600_fini, 652 .suspend = &rs600_suspend, 653 .resume = &rs600_resume, 654 .vga_set_state = &r100_vga_set_state, 655 .asic_reset = &rs600_asic_reset, 656 .ioctl_wait_idle = NULL, 657 .gui_idle = &r100_gui_idle, 658 .mc_wait_for_idle = &rs600_mc_wait_for_idle, 659 .gart = { 660 .tlb_flush = &rs600_gart_tlb_flush, 661 .set_page = &rs600_gart_set_page, 662 }, 663 .ring = { 664 [RADEON_RING_TYPE_GFX_INDEX] = { 665 .ib_execute = &r100_ring_ib_execute, 666 .emit_fence = &r300_fence_ring_emit, 667 .emit_semaphore = &r100_semaphore_ring_emit, 668 .cs_parse = &r300_cs_parse, 669 .ring_start = &r300_ring_start, 670 .ring_test = &r100_ring_test, 671 .ib_test = &r100_ib_test, 672 .is_lockup = &r100_gpu_is_lockup, 673 .get_rptr = &radeon_ring_generic_get_rptr, 674 .get_wptr = &radeon_ring_generic_get_wptr, 675 .set_wptr = &radeon_ring_generic_set_wptr, 676 } 677 }, 678 .irq = { 679 .set = &rs600_irq_set, 680 .process = &rs600_irq_process, 681 }, 682 .display = { 683 .bandwidth_update = &rs600_bandwidth_update, 684 .get_vblank_counter = &rs600_get_vblank_counter, 685 .wait_for_vblank = &avivo_wait_for_vblank, 686 .set_backlight_level = &atombios_set_backlight_level, 687 .get_backlight_level = &atombios_get_backlight_level, 688 .hdmi_enable = &r600_hdmi_enable, 689 .hdmi_setmode = &r600_hdmi_setmode, 690 }, 691 .copy = { 692 .blit = &r100_copy_blit, 693 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 694 .dma = &r200_copy_dma, 695 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 696 .copy = &r100_copy_blit, 697 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 698 }, 699 .surface = { 700 .set_reg = r100_set_surface_reg, 701 .clear_reg = r100_clear_surface_reg, 702 }, 703 .hpd = { 704 .init = &rs600_hpd_init, 705 .fini = &rs600_hpd_fini, 706 .sense = &rs600_hpd_sense, 707 .set_polarity = &rs600_hpd_set_polarity, 708 }, 709 .pm = { 710 .misc = &rs600_pm_misc, 711 .prepare = &rs600_pm_prepare, 712 .finish = &rs600_pm_finish, 713 .init_profile = &r420_pm_init_profile, 714 .get_dynpm_state = &r100_pm_get_dynpm_state, 715 .get_engine_clock = &radeon_atom_get_engine_clock, 716 .set_engine_clock = &radeon_atom_set_engine_clock, 717 .get_memory_clock = &radeon_atom_get_memory_clock, 718 .set_memory_clock = &radeon_atom_set_memory_clock, 719 .get_pcie_lanes = NULL, 720 .set_pcie_lanes = NULL, 721 .set_clock_gating = &radeon_atom_set_clock_gating, 722 }, 723 .pflip = { 724 .pre_page_flip = &rs600_pre_page_flip, 725 .page_flip = &rs600_page_flip, 726 .post_page_flip = &rs600_post_page_flip, 727 }, 728 }; 729 730 static struct radeon_asic rs690_asic = { 731 .init = &rs690_init, 732 .fini = &rs690_fini, 733 .suspend = &rs690_suspend, 734 .resume = &rs690_resume, 735 .vga_set_state = &r100_vga_set_state, 736 .asic_reset = &rs600_asic_reset, 737 .ioctl_wait_idle = NULL, 738 .gui_idle = &r100_gui_idle, 739 .mc_wait_for_idle = &rs690_mc_wait_for_idle, 740 .gart = { 741 .tlb_flush = &rs400_gart_tlb_flush, 742 .set_page = &rs400_gart_set_page, 743 }, 744 .ring = { 745 [RADEON_RING_TYPE_GFX_INDEX] = { 746 .ib_execute = &r100_ring_ib_execute, 747 .emit_fence = &r300_fence_ring_emit, 748 .emit_semaphore = &r100_semaphore_ring_emit, 749 .cs_parse = &r300_cs_parse, 750 .ring_start = &r300_ring_start, 751 .ring_test = &r100_ring_test, 752 .ib_test = &r100_ib_test, 753 .is_lockup = &r100_gpu_is_lockup, 754 .get_rptr = &radeon_ring_generic_get_rptr, 755 .get_wptr = &radeon_ring_generic_get_wptr, 756 .set_wptr = &radeon_ring_generic_set_wptr, 757 } 758 }, 759 .irq = { 760 .set = &rs600_irq_set, 761 .process = &rs600_irq_process, 762 }, 763 .display = { 764 .get_vblank_counter = &rs600_get_vblank_counter, 765 .bandwidth_update = &rs690_bandwidth_update, 766 .wait_for_vblank = &avivo_wait_for_vblank, 767 .set_backlight_level = &atombios_set_backlight_level, 768 .get_backlight_level = &atombios_get_backlight_level, 769 .hdmi_enable = &r600_hdmi_enable, 770 .hdmi_setmode = &r600_hdmi_setmode, 771 }, 772 .copy = { 773 .blit = &r100_copy_blit, 774 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 775 .dma = &r200_copy_dma, 776 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 777 .copy = &r200_copy_dma, 778 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 779 }, 780 .surface = { 781 .set_reg = r100_set_surface_reg, 782 .clear_reg = r100_clear_surface_reg, 783 }, 784 .hpd = { 785 .init = &rs600_hpd_init, 786 .fini = &rs600_hpd_fini, 787 .sense = &rs600_hpd_sense, 788 .set_polarity = &rs600_hpd_set_polarity, 789 }, 790 .pm = { 791 .misc = &rs600_pm_misc, 792 .prepare = &rs600_pm_prepare, 793 .finish = &rs600_pm_finish, 794 .init_profile = &r420_pm_init_profile, 795 .get_dynpm_state = &r100_pm_get_dynpm_state, 796 .get_engine_clock = &radeon_atom_get_engine_clock, 797 .set_engine_clock = &radeon_atom_set_engine_clock, 798 .get_memory_clock = &radeon_atom_get_memory_clock, 799 .set_memory_clock = &radeon_atom_set_memory_clock, 800 .get_pcie_lanes = NULL, 801 .set_pcie_lanes = NULL, 802 .set_clock_gating = &radeon_atom_set_clock_gating, 803 }, 804 .pflip = { 805 .pre_page_flip = &rs600_pre_page_flip, 806 .page_flip = &rs600_page_flip, 807 .post_page_flip = &rs600_post_page_flip, 808 }, 809 }; 810 811 static struct radeon_asic rv515_asic = { 812 .init = &rv515_init, 813 .fini = &rv515_fini, 814 .suspend = &rv515_suspend, 815 .resume = &rv515_resume, 816 .vga_set_state = &r100_vga_set_state, 817 .asic_reset = &rs600_asic_reset, 818 .ioctl_wait_idle = NULL, 819 .gui_idle = &r100_gui_idle, 820 .mc_wait_for_idle = &rv515_mc_wait_for_idle, 821 .gart = { 822 .tlb_flush = &rv370_pcie_gart_tlb_flush, 823 .set_page = &rv370_pcie_gart_set_page, 824 }, 825 .ring = { 826 [RADEON_RING_TYPE_GFX_INDEX] = { 827 .ib_execute = &r100_ring_ib_execute, 828 .emit_fence = &r300_fence_ring_emit, 829 .emit_semaphore = &r100_semaphore_ring_emit, 830 .cs_parse = &r300_cs_parse, 831 .ring_start = &rv515_ring_start, 832 .ring_test = &r100_ring_test, 833 .ib_test = &r100_ib_test, 834 .is_lockup = &r100_gpu_is_lockup, 835 .get_rptr = &radeon_ring_generic_get_rptr, 836 .get_wptr = &radeon_ring_generic_get_wptr, 837 .set_wptr = &radeon_ring_generic_set_wptr, 838 } 839 }, 840 .irq = { 841 .set = &rs600_irq_set, 842 .process = &rs600_irq_process, 843 }, 844 .display = { 845 .get_vblank_counter = &rs600_get_vblank_counter, 846 .bandwidth_update = &rv515_bandwidth_update, 847 .wait_for_vblank = &avivo_wait_for_vblank, 848 .set_backlight_level = &atombios_set_backlight_level, 849 .get_backlight_level = &atombios_get_backlight_level, 850 }, 851 .copy = { 852 .blit = &r100_copy_blit, 853 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 854 .dma = &r200_copy_dma, 855 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 856 .copy = &r100_copy_blit, 857 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 858 }, 859 .surface = { 860 .set_reg = r100_set_surface_reg, 861 .clear_reg = r100_clear_surface_reg, 862 }, 863 .hpd = { 864 .init = &rs600_hpd_init, 865 .fini = &rs600_hpd_fini, 866 .sense = &rs600_hpd_sense, 867 .set_polarity = &rs600_hpd_set_polarity, 868 }, 869 .pm = { 870 .misc = &rs600_pm_misc, 871 .prepare = &rs600_pm_prepare, 872 .finish = &rs600_pm_finish, 873 .init_profile = &r420_pm_init_profile, 874 .get_dynpm_state = &r100_pm_get_dynpm_state, 875 .get_engine_clock = &radeon_atom_get_engine_clock, 876 .set_engine_clock = &radeon_atom_set_engine_clock, 877 .get_memory_clock = &radeon_atom_get_memory_clock, 878 .set_memory_clock = &radeon_atom_set_memory_clock, 879 .get_pcie_lanes = &rv370_get_pcie_lanes, 880 .set_pcie_lanes = &rv370_set_pcie_lanes, 881 .set_clock_gating = &radeon_atom_set_clock_gating, 882 }, 883 .pflip = { 884 .pre_page_flip = &rs600_pre_page_flip, 885 .page_flip = &rs600_page_flip, 886 .post_page_flip = &rs600_post_page_flip, 887 }, 888 }; 889 890 static struct radeon_asic r520_asic = { 891 .init = &r520_init, 892 .fini = &rv515_fini, 893 .suspend = &rv515_suspend, 894 .resume = &r520_resume, 895 .vga_set_state = &r100_vga_set_state, 896 .asic_reset = &rs600_asic_reset, 897 .ioctl_wait_idle = NULL, 898 .gui_idle = &r100_gui_idle, 899 .mc_wait_for_idle = &r520_mc_wait_for_idle, 900 .gart = { 901 .tlb_flush = &rv370_pcie_gart_tlb_flush, 902 .set_page = &rv370_pcie_gart_set_page, 903 }, 904 .ring = { 905 [RADEON_RING_TYPE_GFX_INDEX] = { 906 .ib_execute = &r100_ring_ib_execute, 907 .emit_fence = &r300_fence_ring_emit, 908 .emit_semaphore = &r100_semaphore_ring_emit, 909 .cs_parse = &r300_cs_parse, 910 .ring_start = &rv515_ring_start, 911 .ring_test = &r100_ring_test, 912 .ib_test = &r100_ib_test, 913 .is_lockup = &r100_gpu_is_lockup, 914 .get_rptr = &radeon_ring_generic_get_rptr, 915 .get_wptr = &radeon_ring_generic_get_wptr, 916 .set_wptr = &radeon_ring_generic_set_wptr, 917 } 918 }, 919 .irq = { 920 .set = &rs600_irq_set, 921 .process = &rs600_irq_process, 922 }, 923 .display = { 924 .bandwidth_update = &rv515_bandwidth_update, 925 .get_vblank_counter = &rs600_get_vblank_counter, 926 .wait_for_vblank = &avivo_wait_for_vblank, 927 .set_backlight_level = &atombios_set_backlight_level, 928 .get_backlight_level = &atombios_get_backlight_level, 929 }, 930 .copy = { 931 .blit = &r100_copy_blit, 932 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 933 .dma = &r200_copy_dma, 934 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 935 .copy = &r100_copy_blit, 936 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 937 }, 938 .surface = { 939 .set_reg = r100_set_surface_reg, 940 .clear_reg = r100_clear_surface_reg, 941 }, 942 .hpd = { 943 .init = &rs600_hpd_init, 944 .fini = &rs600_hpd_fini, 945 .sense = &rs600_hpd_sense, 946 .set_polarity = &rs600_hpd_set_polarity, 947 }, 948 .pm = { 949 .misc = &rs600_pm_misc, 950 .prepare = &rs600_pm_prepare, 951 .finish = &rs600_pm_finish, 952 .init_profile = &r420_pm_init_profile, 953 .get_dynpm_state = &r100_pm_get_dynpm_state, 954 .get_engine_clock = &radeon_atom_get_engine_clock, 955 .set_engine_clock = &radeon_atom_set_engine_clock, 956 .get_memory_clock = &radeon_atom_get_memory_clock, 957 .set_memory_clock = &radeon_atom_set_memory_clock, 958 .get_pcie_lanes = &rv370_get_pcie_lanes, 959 .set_pcie_lanes = &rv370_set_pcie_lanes, 960 .set_clock_gating = &radeon_atom_set_clock_gating, 961 }, 962 .pflip = { 963 .pre_page_flip = &rs600_pre_page_flip, 964 .page_flip = &rs600_page_flip, 965 .post_page_flip = &rs600_post_page_flip, 966 }, 967 }; 968 969 static struct radeon_asic r600_asic = { 970 .init = &r600_init, 971 .fini = &r600_fini, 972 .suspend = &r600_suspend, 973 .resume = &r600_resume, 974 .vga_set_state = &r600_vga_set_state, 975 .asic_reset = &r600_asic_reset, 976 .ioctl_wait_idle = r600_ioctl_wait_idle, 977 .gui_idle = &r600_gui_idle, 978 .mc_wait_for_idle = &r600_mc_wait_for_idle, 979 .get_xclk = &r600_get_xclk, 980 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 981 .gart = { 982 .tlb_flush = &r600_pcie_gart_tlb_flush, 983 .set_page = &rs600_gart_set_page, 984 }, 985 .ring = { 986 [RADEON_RING_TYPE_GFX_INDEX] = { 987 .ib_execute = &r600_ring_ib_execute, 988 .emit_fence = &r600_fence_ring_emit, 989 .emit_semaphore = &r600_semaphore_ring_emit, 990 .cs_parse = &r600_cs_parse, 991 .ring_test = &r600_ring_test, 992 .ib_test = &r600_ib_test, 993 .is_lockup = &r600_gfx_is_lockup, 994 .get_rptr = &radeon_ring_generic_get_rptr, 995 .get_wptr = &radeon_ring_generic_get_wptr, 996 .set_wptr = &radeon_ring_generic_set_wptr, 997 }, 998 [R600_RING_TYPE_DMA_INDEX] = { 999 .ib_execute = &r600_dma_ring_ib_execute, 1000 .emit_fence = &r600_dma_fence_ring_emit, 1001 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1002 .cs_parse = &r600_dma_cs_parse, 1003 .ring_test = &r600_dma_ring_test, 1004 .ib_test = &r600_dma_ib_test, 1005 .is_lockup = &r600_dma_is_lockup, 1006 .get_rptr = &radeon_ring_generic_get_rptr, 1007 .get_wptr = &radeon_ring_generic_get_wptr, 1008 .set_wptr = &radeon_ring_generic_set_wptr, 1009 } 1010 }, 1011 .irq = { 1012 .set = &r600_irq_set, 1013 .process = &r600_irq_process, 1014 }, 1015 .display = { 1016 .bandwidth_update = &rv515_bandwidth_update, 1017 .get_vblank_counter = &rs600_get_vblank_counter, 1018 .wait_for_vblank = &avivo_wait_for_vblank, 1019 .set_backlight_level = &atombios_set_backlight_level, 1020 .get_backlight_level = &atombios_get_backlight_level, 1021 .hdmi_enable = &r600_hdmi_enable, 1022 .hdmi_setmode = &r600_hdmi_setmode, 1023 }, 1024 .copy = { 1025 .blit = &r600_copy_blit, 1026 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1027 .dma = &r600_copy_dma, 1028 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1029 .copy = &r600_copy_dma, 1030 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1031 }, 1032 .surface = { 1033 .set_reg = r600_set_surface_reg, 1034 .clear_reg = r600_clear_surface_reg, 1035 }, 1036 .hpd = { 1037 .init = &r600_hpd_init, 1038 .fini = &r600_hpd_fini, 1039 .sense = &r600_hpd_sense, 1040 .set_polarity = &r600_hpd_set_polarity, 1041 }, 1042 .pm = { 1043 .misc = &r600_pm_misc, 1044 .prepare = &rs600_pm_prepare, 1045 .finish = &rs600_pm_finish, 1046 .init_profile = &r600_pm_init_profile, 1047 .get_dynpm_state = &r600_pm_get_dynpm_state, 1048 .get_engine_clock = &radeon_atom_get_engine_clock, 1049 .set_engine_clock = &radeon_atom_set_engine_clock, 1050 .get_memory_clock = &radeon_atom_get_memory_clock, 1051 .set_memory_clock = &radeon_atom_set_memory_clock, 1052 .get_pcie_lanes = &r600_get_pcie_lanes, 1053 .set_pcie_lanes = &r600_set_pcie_lanes, 1054 .set_clock_gating = NULL, 1055 .get_temperature = &rv6xx_get_temp, 1056 }, 1057 .pflip = { 1058 .pre_page_flip = &rs600_pre_page_flip, 1059 .page_flip = &rs600_page_flip, 1060 .post_page_flip = &rs600_post_page_flip, 1061 }, 1062 }; 1063 1064 static struct radeon_asic rv6xx_asic = { 1065 .init = &r600_init, 1066 .fini = &r600_fini, 1067 .suspend = &r600_suspend, 1068 .resume = &r600_resume, 1069 .vga_set_state = &r600_vga_set_state, 1070 .asic_reset = &r600_asic_reset, 1071 .ioctl_wait_idle = r600_ioctl_wait_idle, 1072 .gui_idle = &r600_gui_idle, 1073 .mc_wait_for_idle = &r600_mc_wait_for_idle, 1074 .get_xclk = &r600_get_xclk, 1075 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1076 .gart = { 1077 .tlb_flush = &r600_pcie_gart_tlb_flush, 1078 .set_page = &rs600_gart_set_page, 1079 }, 1080 .ring = { 1081 [RADEON_RING_TYPE_GFX_INDEX] = { 1082 .ib_execute = &r600_ring_ib_execute, 1083 .emit_fence = &r600_fence_ring_emit, 1084 .emit_semaphore = &r600_semaphore_ring_emit, 1085 .cs_parse = &r600_cs_parse, 1086 .ring_test = &r600_ring_test, 1087 .ib_test = &r600_ib_test, 1088 .is_lockup = &r600_gfx_is_lockup, 1089 .get_rptr = &radeon_ring_generic_get_rptr, 1090 .get_wptr = &radeon_ring_generic_get_wptr, 1091 .set_wptr = &radeon_ring_generic_set_wptr, 1092 }, 1093 [R600_RING_TYPE_DMA_INDEX] = { 1094 .ib_execute = &r600_dma_ring_ib_execute, 1095 .emit_fence = &r600_dma_fence_ring_emit, 1096 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1097 .cs_parse = &r600_dma_cs_parse, 1098 .ring_test = &r600_dma_ring_test, 1099 .ib_test = &r600_dma_ib_test, 1100 .is_lockup = &r600_dma_is_lockup, 1101 .get_rptr = &radeon_ring_generic_get_rptr, 1102 .get_wptr = &radeon_ring_generic_get_wptr, 1103 .set_wptr = &radeon_ring_generic_set_wptr, 1104 } 1105 }, 1106 .irq = { 1107 .set = &r600_irq_set, 1108 .process = &r600_irq_process, 1109 }, 1110 .display = { 1111 .bandwidth_update = &rv515_bandwidth_update, 1112 .get_vblank_counter = &rs600_get_vblank_counter, 1113 .wait_for_vblank = &avivo_wait_for_vblank, 1114 .set_backlight_level = &atombios_set_backlight_level, 1115 .get_backlight_level = &atombios_get_backlight_level, 1116 }, 1117 .copy = { 1118 .blit = &r600_copy_blit, 1119 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1120 .dma = &r600_copy_dma, 1121 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1122 .copy = &r600_copy_dma, 1123 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1124 }, 1125 .surface = { 1126 .set_reg = r600_set_surface_reg, 1127 .clear_reg = r600_clear_surface_reg, 1128 }, 1129 .hpd = { 1130 .init = &r600_hpd_init, 1131 .fini = &r600_hpd_fini, 1132 .sense = &r600_hpd_sense, 1133 .set_polarity = &r600_hpd_set_polarity, 1134 }, 1135 .pm = { 1136 .misc = &r600_pm_misc, 1137 .prepare = &rs600_pm_prepare, 1138 .finish = &rs600_pm_finish, 1139 .init_profile = &r600_pm_init_profile, 1140 .get_dynpm_state = &r600_pm_get_dynpm_state, 1141 .get_engine_clock = &radeon_atom_get_engine_clock, 1142 .set_engine_clock = &radeon_atom_set_engine_clock, 1143 .get_memory_clock = &radeon_atom_get_memory_clock, 1144 .set_memory_clock = &radeon_atom_set_memory_clock, 1145 .get_pcie_lanes = &r600_get_pcie_lanes, 1146 .set_pcie_lanes = &r600_set_pcie_lanes, 1147 .set_clock_gating = NULL, 1148 .get_temperature = &rv6xx_get_temp, 1149 }, 1150 .dpm = { 1151 .init = &rv6xx_dpm_init, 1152 .setup_asic = &rv6xx_setup_asic, 1153 .enable = &rv6xx_dpm_enable, 1154 .disable = &rv6xx_dpm_disable, 1155 .pre_set_power_state = &r600_dpm_pre_set_power_state, 1156 .set_power_state = &rv6xx_dpm_set_power_state, 1157 .post_set_power_state = &r600_dpm_post_set_power_state, 1158 .display_configuration_changed = &rv6xx_dpm_display_configuration_changed, 1159 .fini = &rv6xx_dpm_fini, 1160 .get_sclk = &rv6xx_dpm_get_sclk, 1161 .get_mclk = &rv6xx_dpm_get_mclk, 1162 .print_power_state = &rv6xx_dpm_print_power_state, 1163 .debugfs_print_current_performance_level = &rv6xx_dpm_debugfs_print_current_performance_level, 1164 }, 1165 .pflip = { 1166 .pre_page_flip = &rs600_pre_page_flip, 1167 .page_flip = &rs600_page_flip, 1168 .post_page_flip = &rs600_post_page_flip, 1169 }, 1170 }; 1171 1172 static struct radeon_asic rs780_asic = { 1173 .init = &r600_init, 1174 .fini = &r600_fini, 1175 .suspend = &r600_suspend, 1176 .resume = &r600_resume, 1177 .vga_set_state = &r600_vga_set_state, 1178 .asic_reset = &r600_asic_reset, 1179 .ioctl_wait_idle = r600_ioctl_wait_idle, 1180 .gui_idle = &r600_gui_idle, 1181 .mc_wait_for_idle = &r600_mc_wait_for_idle, 1182 .get_xclk = &r600_get_xclk, 1183 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1184 .gart = { 1185 .tlb_flush = &r600_pcie_gart_tlb_flush, 1186 .set_page = &rs600_gart_set_page, 1187 }, 1188 .ring = { 1189 [RADEON_RING_TYPE_GFX_INDEX] = { 1190 .ib_execute = &r600_ring_ib_execute, 1191 .emit_fence = &r600_fence_ring_emit, 1192 .emit_semaphore = &r600_semaphore_ring_emit, 1193 .cs_parse = &r600_cs_parse, 1194 .ring_test = &r600_ring_test, 1195 .ib_test = &r600_ib_test, 1196 .is_lockup = &r600_gfx_is_lockup, 1197 .get_rptr = &radeon_ring_generic_get_rptr, 1198 .get_wptr = &radeon_ring_generic_get_wptr, 1199 .set_wptr = &radeon_ring_generic_set_wptr, 1200 }, 1201 [R600_RING_TYPE_DMA_INDEX] = { 1202 .ib_execute = &r600_dma_ring_ib_execute, 1203 .emit_fence = &r600_dma_fence_ring_emit, 1204 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1205 .cs_parse = &r600_dma_cs_parse, 1206 .ring_test = &r600_dma_ring_test, 1207 .ib_test = &r600_dma_ib_test, 1208 .is_lockup = &r600_dma_is_lockup, 1209 .get_rptr = &radeon_ring_generic_get_rptr, 1210 .get_wptr = &radeon_ring_generic_get_wptr, 1211 .set_wptr = &radeon_ring_generic_set_wptr, 1212 } 1213 }, 1214 .irq = { 1215 .set = &r600_irq_set, 1216 .process = &r600_irq_process, 1217 }, 1218 .display = { 1219 .bandwidth_update = &rs690_bandwidth_update, 1220 .get_vblank_counter = &rs600_get_vblank_counter, 1221 .wait_for_vblank = &avivo_wait_for_vblank, 1222 .set_backlight_level = &atombios_set_backlight_level, 1223 .get_backlight_level = &atombios_get_backlight_level, 1224 .hdmi_enable = &r600_hdmi_enable, 1225 .hdmi_setmode = &r600_hdmi_setmode, 1226 }, 1227 .copy = { 1228 .blit = &r600_copy_blit, 1229 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1230 .dma = &r600_copy_dma, 1231 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1232 .copy = &r600_copy_dma, 1233 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1234 }, 1235 .surface = { 1236 .set_reg = r600_set_surface_reg, 1237 .clear_reg = r600_clear_surface_reg, 1238 }, 1239 .hpd = { 1240 .init = &r600_hpd_init, 1241 .fini = &r600_hpd_fini, 1242 .sense = &r600_hpd_sense, 1243 .set_polarity = &r600_hpd_set_polarity, 1244 }, 1245 .pm = { 1246 .misc = &r600_pm_misc, 1247 .prepare = &rs600_pm_prepare, 1248 .finish = &rs600_pm_finish, 1249 .init_profile = &rs780_pm_init_profile, 1250 .get_dynpm_state = &r600_pm_get_dynpm_state, 1251 .get_engine_clock = &radeon_atom_get_engine_clock, 1252 .set_engine_clock = &radeon_atom_set_engine_clock, 1253 .get_memory_clock = NULL, 1254 .set_memory_clock = NULL, 1255 .get_pcie_lanes = NULL, 1256 .set_pcie_lanes = NULL, 1257 .set_clock_gating = NULL, 1258 .get_temperature = &rv6xx_get_temp, 1259 }, 1260 .dpm = { 1261 .init = &rs780_dpm_init, 1262 .setup_asic = &rs780_dpm_setup_asic, 1263 .enable = &rs780_dpm_enable, 1264 .disable = &rs780_dpm_disable, 1265 .pre_set_power_state = &r600_dpm_pre_set_power_state, 1266 .set_power_state = &rs780_dpm_set_power_state, 1267 .post_set_power_state = &r600_dpm_post_set_power_state, 1268 .display_configuration_changed = &rs780_dpm_display_configuration_changed, 1269 .fini = &rs780_dpm_fini, 1270 .get_sclk = &rs780_dpm_get_sclk, 1271 .get_mclk = &rs780_dpm_get_mclk, 1272 .print_power_state = &rs780_dpm_print_power_state, 1273 }, 1274 .pflip = { 1275 .pre_page_flip = &rs600_pre_page_flip, 1276 .page_flip = &rs600_page_flip, 1277 .post_page_flip = &rs600_post_page_flip, 1278 }, 1279 }; 1280 1281 static struct radeon_asic rv770_asic = { 1282 .init = &rv770_init, 1283 .fini = &rv770_fini, 1284 .suspend = &rv770_suspend, 1285 .resume = &rv770_resume, 1286 .asic_reset = &r600_asic_reset, 1287 .vga_set_state = &r600_vga_set_state, 1288 .ioctl_wait_idle = r600_ioctl_wait_idle, 1289 .gui_idle = &r600_gui_idle, 1290 .mc_wait_for_idle = &r600_mc_wait_for_idle, 1291 .get_xclk = &rv770_get_xclk, 1292 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1293 .gart = { 1294 .tlb_flush = &r600_pcie_gart_tlb_flush, 1295 .set_page = &rs600_gart_set_page, 1296 }, 1297 .ring = { 1298 [RADEON_RING_TYPE_GFX_INDEX] = { 1299 .ib_execute = &r600_ring_ib_execute, 1300 .emit_fence = &r600_fence_ring_emit, 1301 .emit_semaphore = &r600_semaphore_ring_emit, 1302 .cs_parse = &r600_cs_parse, 1303 .ring_test = &r600_ring_test, 1304 .ib_test = &r600_ib_test, 1305 .is_lockup = &r600_gfx_is_lockup, 1306 .get_rptr = &radeon_ring_generic_get_rptr, 1307 .get_wptr = &radeon_ring_generic_get_wptr, 1308 .set_wptr = &radeon_ring_generic_set_wptr, 1309 }, 1310 [R600_RING_TYPE_DMA_INDEX] = { 1311 .ib_execute = &r600_dma_ring_ib_execute, 1312 .emit_fence = &r600_dma_fence_ring_emit, 1313 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1314 .cs_parse = &r600_dma_cs_parse, 1315 .ring_test = &r600_dma_ring_test, 1316 .ib_test = &r600_dma_ib_test, 1317 .is_lockup = &r600_dma_is_lockup, 1318 .get_rptr = &radeon_ring_generic_get_rptr, 1319 .get_wptr = &radeon_ring_generic_get_wptr, 1320 .set_wptr = &radeon_ring_generic_set_wptr, 1321 }, 1322 [R600_RING_TYPE_UVD_INDEX] = { 1323 .ib_execute = &r600_uvd_ib_execute, 1324 .emit_fence = &r600_uvd_fence_emit, 1325 .emit_semaphore = &r600_uvd_semaphore_emit, 1326 .cs_parse = &radeon_uvd_cs_parse, 1327 .ring_test = &r600_uvd_ring_test, 1328 .ib_test = &r600_uvd_ib_test, 1329 .is_lockup = &radeon_ring_test_lockup, 1330 .get_rptr = &radeon_ring_generic_get_rptr, 1331 .get_wptr = &radeon_ring_generic_get_wptr, 1332 .set_wptr = &radeon_ring_generic_set_wptr, 1333 } 1334 }, 1335 .irq = { 1336 .set = &r600_irq_set, 1337 .process = &r600_irq_process, 1338 }, 1339 .display = { 1340 .bandwidth_update = &rv515_bandwidth_update, 1341 .get_vblank_counter = &rs600_get_vblank_counter, 1342 .wait_for_vblank = &avivo_wait_for_vblank, 1343 .set_backlight_level = &atombios_set_backlight_level, 1344 .get_backlight_level = &atombios_get_backlight_level, 1345 .hdmi_enable = &r600_hdmi_enable, 1346 .hdmi_setmode = &r600_hdmi_setmode, 1347 }, 1348 .copy = { 1349 .blit = &r600_copy_blit, 1350 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1351 .dma = &rv770_copy_dma, 1352 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1353 .copy = &rv770_copy_dma, 1354 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1355 }, 1356 .surface = { 1357 .set_reg = r600_set_surface_reg, 1358 .clear_reg = r600_clear_surface_reg, 1359 }, 1360 .hpd = { 1361 .init = &r600_hpd_init, 1362 .fini = &r600_hpd_fini, 1363 .sense = &r600_hpd_sense, 1364 .set_polarity = &r600_hpd_set_polarity, 1365 }, 1366 .pm = { 1367 .misc = &rv770_pm_misc, 1368 .prepare = &rs600_pm_prepare, 1369 .finish = &rs600_pm_finish, 1370 .init_profile = &r600_pm_init_profile, 1371 .get_dynpm_state = &r600_pm_get_dynpm_state, 1372 .get_engine_clock = &radeon_atom_get_engine_clock, 1373 .set_engine_clock = &radeon_atom_set_engine_clock, 1374 .get_memory_clock = &radeon_atom_get_memory_clock, 1375 .set_memory_clock = &radeon_atom_set_memory_clock, 1376 .get_pcie_lanes = &r600_get_pcie_lanes, 1377 .set_pcie_lanes = &r600_set_pcie_lanes, 1378 .set_clock_gating = &radeon_atom_set_clock_gating, 1379 .set_uvd_clocks = &rv770_set_uvd_clocks, 1380 .get_temperature = &rv770_get_temp, 1381 }, 1382 .dpm = { 1383 .init = &rv770_dpm_init, 1384 .setup_asic = &rv770_dpm_setup_asic, 1385 .enable = &rv770_dpm_enable, 1386 .disable = &rv770_dpm_disable, 1387 .pre_set_power_state = &r600_dpm_pre_set_power_state, 1388 .set_power_state = &rv770_dpm_set_power_state, 1389 .post_set_power_state = &r600_dpm_post_set_power_state, 1390 .display_configuration_changed = &rv770_dpm_display_configuration_changed, 1391 .fini = &rv770_dpm_fini, 1392 .get_sclk = &rv770_dpm_get_sclk, 1393 .get_mclk = &rv770_dpm_get_mclk, 1394 .print_power_state = &rv770_dpm_print_power_state, 1395 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level, 1396 .force_performance_level = &rv770_dpm_force_performance_level, 1397 .vblank_too_short = &rv770_dpm_vblank_too_short, 1398 }, 1399 .pflip = { 1400 .pre_page_flip = &rs600_pre_page_flip, 1401 .page_flip = &rv770_page_flip, 1402 .post_page_flip = &rs600_post_page_flip, 1403 }, 1404 }; 1405 1406 static struct radeon_asic evergreen_asic = { 1407 .init = &evergreen_init, 1408 .fini = &evergreen_fini, 1409 .suspend = &evergreen_suspend, 1410 .resume = &evergreen_resume, 1411 .asic_reset = &evergreen_asic_reset, 1412 .vga_set_state = &r600_vga_set_state, 1413 .ioctl_wait_idle = r600_ioctl_wait_idle, 1414 .gui_idle = &r600_gui_idle, 1415 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1416 .get_xclk = &rv770_get_xclk, 1417 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1418 .gart = { 1419 .tlb_flush = &evergreen_pcie_gart_tlb_flush, 1420 .set_page = &rs600_gart_set_page, 1421 }, 1422 .ring = { 1423 [RADEON_RING_TYPE_GFX_INDEX] = { 1424 .ib_execute = &evergreen_ring_ib_execute, 1425 .emit_fence = &r600_fence_ring_emit, 1426 .emit_semaphore = &r600_semaphore_ring_emit, 1427 .cs_parse = &evergreen_cs_parse, 1428 .ring_test = &r600_ring_test, 1429 .ib_test = &r600_ib_test, 1430 .is_lockup = &evergreen_gfx_is_lockup, 1431 .get_rptr = &radeon_ring_generic_get_rptr, 1432 .get_wptr = &radeon_ring_generic_get_wptr, 1433 .set_wptr = &radeon_ring_generic_set_wptr, 1434 }, 1435 [R600_RING_TYPE_DMA_INDEX] = { 1436 .ib_execute = &evergreen_dma_ring_ib_execute, 1437 .emit_fence = &evergreen_dma_fence_ring_emit, 1438 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1439 .cs_parse = &evergreen_dma_cs_parse, 1440 .ring_test = &r600_dma_ring_test, 1441 .ib_test = &r600_dma_ib_test, 1442 .is_lockup = &evergreen_dma_is_lockup, 1443 .get_rptr = &radeon_ring_generic_get_rptr, 1444 .get_wptr = &radeon_ring_generic_get_wptr, 1445 .set_wptr = &radeon_ring_generic_set_wptr, 1446 }, 1447 [R600_RING_TYPE_UVD_INDEX] = { 1448 .ib_execute = &r600_uvd_ib_execute, 1449 .emit_fence = &r600_uvd_fence_emit, 1450 .emit_semaphore = &r600_uvd_semaphore_emit, 1451 .cs_parse = &radeon_uvd_cs_parse, 1452 .ring_test = &r600_uvd_ring_test, 1453 .ib_test = &r600_uvd_ib_test, 1454 .is_lockup = &radeon_ring_test_lockup, 1455 .get_rptr = &radeon_ring_generic_get_rptr, 1456 .get_wptr = &radeon_ring_generic_get_wptr, 1457 .set_wptr = &radeon_ring_generic_set_wptr, 1458 } 1459 }, 1460 .irq = { 1461 .set = &evergreen_irq_set, 1462 .process = &evergreen_irq_process, 1463 }, 1464 .display = { 1465 .bandwidth_update = &evergreen_bandwidth_update, 1466 .get_vblank_counter = &evergreen_get_vblank_counter, 1467 .wait_for_vblank = &dce4_wait_for_vblank, 1468 .set_backlight_level = &atombios_set_backlight_level, 1469 .get_backlight_level = &atombios_get_backlight_level, 1470 .hdmi_enable = &evergreen_hdmi_enable, 1471 .hdmi_setmode = &evergreen_hdmi_setmode, 1472 }, 1473 .copy = { 1474 .blit = &r600_copy_blit, 1475 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1476 .dma = &evergreen_copy_dma, 1477 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1478 .copy = &evergreen_copy_dma, 1479 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1480 }, 1481 .surface = { 1482 .set_reg = r600_set_surface_reg, 1483 .clear_reg = r600_clear_surface_reg, 1484 }, 1485 .hpd = { 1486 .init = &evergreen_hpd_init, 1487 .fini = &evergreen_hpd_fini, 1488 .sense = &evergreen_hpd_sense, 1489 .set_polarity = &evergreen_hpd_set_polarity, 1490 }, 1491 .pm = { 1492 .misc = &evergreen_pm_misc, 1493 .prepare = &evergreen_pm_prepare, 1494 .finish = &evergreen_pm_finish, 1495 .init_profile = &r600_pm_init_profile, 1496 .get_dynpm_state = &r600_pm_get_dynpm_state, 1497 .get_engine_clock = &radeon_atom_get_engine_clock, 1498 .set_engine_clock = &radeon_atom_set_engine_clock, 1499 .get_memory_clock = &radeon_atom_get_memory_clock, 1500 .set_memory_clock = &radeon_atom_set_memory_clock, 1501 .get_pcie_lanes = &r600_get_pcie_lanes, 1502 .set_pcie_lanes = &r600_set_pcie_lanes, 1503 .set_clock_gating = NULL, 1504 .set_uvd_clocks = &evergreen_set_uvd_clocks, 1505 .get_temperature = &evergreen_get_temp, 1506 }, 1507 .dpm = { 1508 .init = &cypress_dpm_init, 1509 .setup_asic = &cypress_dpm_setup_asic, 1510 .enable = &cypress_dpm_enable, 1511 .disable = &cypress_dpm_disable, 1512 .pre_set_power_state = &r600_dpm_pre_set_power_state, 1513 .set_power_state = &cypress_dpm_set_power_state, 1514 .post_set_power_state = &r600_dpm_post_set_power_state, 1515 .display_configuration_changed = &cypress_dpm_display_configuration_changed, 1516 .fini = &cypress_dpm_fini, 1517 .get_sclk = &rv770_dpm_get_sclk, 1518 .get_mclk = &rv770_dpm_get_mclk, 1519 .print_power_state = &rv770_dpm_print_power_state, 1520 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level, 1521 .force_performance_level = &rv770_dpm_force_performance_level, 1522 .vblank_too_short = &cypress_dpm_vblank_too_short, 1523 }, 1524 .pflip = { 1525 .pre_page_flip = &evergreen_pre_page_flip, 1526 .page_flip = &evergreen_page_flip, 1527 .post_page_flip = &evergreen_post_page_flip, 1528 }, 1529 }; 1530 1531 static struct radeon_asic sumo_asic = { 1532 .init = &evergreen_init, 1533 .fini = &evergreen_fini, 1534 .suspend = &evergreen_suspend, 1535 .resume = &evergreen_resume, 1536 .asic_reset = &evergreen_asic_reset, 1537 .vga_set_state = &r600_vga_set_state, 1538 .ioctl_wait_idle = r600_ioctl_wait_idle, 1539 .gui_idle = &r600_gui_idle, 1540 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1541 .get_xclk = &r600_get_xclk, 1542 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1543 .gart = { 1544 .tlb_flush = &evergreen_pcie_gart_tlb_flush, 1545 .set_page = &rs600_gart_set_page, 1546 }, 1547 .ring = { 1548 [RADEON_RING_TYPE_GFX_INDEX] = { 1549 .ib_execute = &evergreen_ring_ib_execute, 1550 .emit_fence = &r600_fence_ring_emit, 1551 .emit_semaphore = &r600_semaphore_ring_emit, 1552 .cs_parse = &evergreen_cs_parse, 1553 .ring_test = &r600_ring_test, 1554 .ib_test = &r600_ib_test, 1555 .is_lockup = &evergreen_gfx_is_lockup, 1556 .get_rptr = &radeon_ring_generic_get_rptr, 1557 .get_wptr = &radeon_ring_generic_get_wptr, 1558 .set_wptr = &radeon_ring_generic_set_wptr, 1559 }, 1560 [R600_RING_TYPE_DMA_INDEX] = { 1561 .ib_execute = &evergreen_dma_ring_ib_execute, 1562 .emit_fence = &evergreen_dma_fence_ring_emit, 1563 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1564 .cs_parse = &evergreen_dma_cs_parse, 1565 .ring_test = &r600_dma_ring_test, 1566 .ib_test = &r600_dma_ib_test, 1567 .is_lockup = &evergreen_dma_is_lockup, 1568 .get_rptr = &radeon_ring_generic_get_rptr, 1569 .get_wptr = &radeon_ring_generic_get_wptr, 1570 .set_wptr = &radeon_ring_generic_set_wptr, 1571 }, 1572 [R600_RING_TYPE_UVD_INDEX] = { 1573 .ib_execute = &r600_uvd_ib_execute, 1574 .emit_fence = &r600_uvd_fence_emit, 1575 .emit_semaphore = &r600_uvd_semaphore_emit, 1576 .cs_parse = &radeon_uvd_cs_parse, 1577 .ring_test = &r600_uvd_ring_test, 1578 .ib_test = &r600_uvd_ib_test, 1579 .is_lockup = &radeon_ring_test_lockup, 1580 .get_rptr = &radeon_ring_generic_get_rptr, 1581 .get_wptr = &radeon_ring_generic_get_wptr, 1582 .set_wptr = &radeon_ring_generic_set_wptr, 1583 } 1584 }, 1585 .irq = { 1586 .set = &evergreen_irq_set, 1587 .process = &evergreen_irq_process, 1588 }, 1589 .display = { 1590 .bandwidth_update = &evergreen_bandwidth_update, 1591 .get_vblank_counter = &evergreen_get_vblank_counter, 1592 .wait_for_vblank = &dce4_wait_for_vblank, 1593 .set_backlight_level = &atombios_set_backlight_level, 1594 .get_backlight_level = &atombios_get_backlight_level, 1595 .hdmi_enable = &evergreen_hdmi_enable, 1596 .hdmi_setmode = &evergreen_hdmi_setmode, 1597 }, 1598 .copy = { 1599 .blit = &r600_copy_blit, 1600 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1601 .dma = &evergreen_copy_dma, 1602 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1603 .copy = &evergreen_copy_dma, 1604 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1605 }, 1606 .surface = { 1607 .set_reg = r600_set_surface_reg, 1608 .clear_reg = r600_clear_surface_reg, 1609 }, 1610 .hpd = { 1611 .init = &evergreen_hpd_init, 1612 .fini = &evergreen_hpd_fini, 1613 .sense = &evergreen_hpd_sense, 1614 .set_polarity = &evergreen_hpd_set_polarity, 1615 }, 1616 .pm = { 1617 .misc = &evergreen_pm_misc, 1618 .prepare = &evergreen_pm_prepare, 1619 .finish = &evergreen_pm_finish, 1620 .init_profile = &sumo_pm_init_profile, 1621 .get_dynpm_state = &r600_pm_get_dynpm_state, 1622 .get_engine_clock = &radeon_atom_get_engine_clock, 1623 .set_engine_clock = &radeon_atom_set_engine_clock, 1624 .get_memory_clock = NULL, 1625 .set_memory_clock = NULL, 1626 .get_pcie_lanes = NULL, 1627 .set_pcie_lanes = NULL, 1628 .set_clock_gating = NULL, 1629 .set_uvd_clocks = &sumo_set_uvd_clocks, 1630 .get_temperature = &sumo_get_temp, 1631 }, 1632 .dpm = { 1633 .init = &sumo_dpm_init, 1634 .setup_asic = &sumo_dpm_setup_asic, 1635 .enable = &sumo_dpm_enable, 1636 .disable = &sumo_dpm_disable, 1637 .pre_set_power_state = &sumo_dpm_pre_set_power_state, 1638 .set_power_state = &sumo_dpm_set_power_state, 1639 .post_set_power_state = &sumo_dpm_post_set_power_state, 1640 .display_configuration_changed = &sumo_dpm_display_configuration_changed, 1641 .fini = &sumo_dpm_fini, 1642 .get_sclk = &sumo_dpm_get_sclk, 1643 .get_mclk = &sumo_dpm_get_mclk, 1644 .print_power_state = &sumo_dpm_print_power_state, 1645 .debugfs_print_current_performance_level = &sumo_dpm_debugfs_print_current_performance_level, 1646 .force_performance_level = &sumo_dpm_force_performance_level, 1647 }, 1648 .pflip = { 1649 .pre_page_flip = &evergreen_pre_page_flip, 1650 .page_flip = &evergreen_page_flip, 1651 .post_page_flip = &evergreen_post_page_flip, 1652 }, 1653 }; 1654 1655 static struct radeon_asic btc_asic = { 1656 .init = &evergreen_init, 1657 .fini = &evergreen_fini, 1658 .suspend = &evergreen_suspend, 1659 .resume = &evergreen_resume, 1660 .asic_reset = &evergreen_asic_reset, 1661 .vga_set_state = &r600_vga_set_state, 1662 .ioctl_wait_idle = r600_ioctl_wait_idle, 1663 .gui_idle = &r600_gui_idle, 1664 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1665 .get_xclk = &rv770_get_xclk, 1666 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1667 .gart = { 1668 .tlb_flush = &evergreen_pcie_gart_tlb_flush, 1669 .set_page = &rs600_gart_set_page, 1670 }, 1671 .ring = { 1672 [RADEON_RING_TYPE_GFX_INDEX] = { 1673 .ib_execute = &evergreen_ring_ib_execute, 1674 .emit_fence = &r600_fence_ring_emit, 1675 .emit_semaphore = &r600_semaphore_ring_emit, 1676 .cs_parse = &evergreen_cs_parse, 1677 .ring_test = &r600_ring_test, 1678 .ib_test = &r600_ib_test, 1679 .is_lockup = &evergreen_gfx_is_lockup, 1680 .get_rptr = &radeon_ring_generic_get_rptr, 1681 .get_wptr = &radeon_ring_generic_get_wptr, 1682 .set_wptr = &radeon_ring_generic_set_wptr, 1683 }, 1684 [R600_RING_TYPE_DMA_INDEX] = { 1685 .ib_execute = &evergreen_dma_ring_ib_execute, 1686 .emit_fence = &evergreen_dma_fence_ring_emit, 1687 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1688 .cs_parse = &evergreen_dma_cs_parse, 1689 .ring_test = &r600_dma_ring_test, 1690 .ib_test = &r600_dma_ib_test, 1691 .is_lockup = &evergreen_dma_is_lockup, 1692 .get_rptr = &radeon_ring_generic_get_rptr, 1693 .get_wptr = &radeon_ring_generic_get_wptr, 1694 .set_wptr = &radeon_ring_generic_set_wptr, 1695 }, 1696 [R600_RING_TYPE_UVD_INDEX] = { 1697 .ib_execute = &r600_uvd_ib_execute, 1698 .emit_fence = &r600_uvd_fence_emit, 1699 .emit_semaphore = &r600_uvd_semaphore_emit, 1700 .cs_parse = &radeon_uvd_cs_parse, 1701 .ring_test = &r600_uvd_ring_test, 1702 .ib_test = &r600_uvd_ib_test, 1703 .is_lockup = &radeon_ring_test_lockup, 1704 .get_rptr = &radeon_ring_generic_get_rptr, 1705 .get_wptr = &radeon_ring_generic_get_wptr, 1706 .set_wptr = &radeon_ring_generic_set_wptr, 1707 } 1708 }, 1709 .irq = { 1710 .set = &evergreen_irq_set, 1711 .process = &evergreen_irq_process, 1712 }, 1713 .display = { 1714 .bandwidth_update = &evergreen_bandwidth_update, 1715 .get_vblank_counter = &evergreen_get_vblank_counter, 1716 .wait_for_vblank = &dce4_wait_for_vblank, 1717 .set_backlight_level = &atombios_set_backlight_level, 1718 .get_backlight_level = &atombios_get_backlight_level, 1719 .hdmi_enable = &evergreen_hdmi_enable, 1720 .hdmi_setmode = &evergreen_hdmi_setmode, 1721 }, 1722 .copy = { 1723 .blit = &r600_copy_blit, 1724 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1725 .dma = &evergreen_copy_dma, 1726 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1727 .copy = &evergreen_copy_dma, 1728 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1729 }, 1730 .surface = { 1731 .set_reg = r600_set_surface_reg, 1732 .clear_reg = r600_clear_surface_reg, 1733 }, 1734 .hpd = { 1735 .init = &evergreen_hpd_init, 1736 .fini = &evergreen_hpd_fini, 1737 .sense = &evergreen_hpd_sense, 1738 .set_polarity = &evergreen_hpd_set_polarity, 1739 }, 1740 .pm = { 1741 .misc = &evergreen_pm_misc, 1742 .prepare = &evergreen_pm_prepare, 1743 .finish = &evergreen_pm_finish, 1744 .init_profile = &btc_pm_init_profile, 1745 .get_dynpm_state = &r600_pm_get_dynpm_state, 1746 .get_engine_clock = &radeon_atom_get_engine_clock, 1747 .set_engine_clock = &radeon_atom_set_engine_clock, 1748 .get_memory_clock = &radeon_atom_get_memory_clock, 1749 .set_memory_clock = &radeon_atom_set_memory_clock, 1750 .get_pcie_lanes = &r600_get_pcie_lanes, 1751 .set_pcie_lanes = &r600_set_pcie_lanes, 1752 .set_clock_gating = NULL, 1753 .set_uvd_clocks = &evergreen_set_uvd_clocks, 1754 .get_temperature = &evergreen_get_temp, 1755 }, 1756 .dpm = { 1757 .init = &btc_dpm_init, 1758 .setup_asic = &btc_dpm_setup_asic, 1759 .enable = &btc_dpm_enable, 1760 .disable = &btc_dpm_disable, 1761 .pre_set_power_state = &btc_dpm_pre_set_power_state, 1762 .set_power_state = &btc_dpm_set_power_state, 1763 .post_set_power_state = &btc_dpm_post_set_power_state, 1764 .display_configuration_changed = &cypress_dpm_display_configuration_changed, 1765 .fini = &btc_dpm_fini, 1766 .get_sclk = &btc_dpm_get_sclk, 1767 .get_mclk = &btc_dpm_get_mclk, 1768 .print_power_state = &rv770_dpm_print_power_state, 1769 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level, 1770 .force_performance_level = &rv770_dpm_force_performance_level, 1771 .vblank_too_short = &btc_dpm_vblank_too_short, 1772 }, 1773 .pflip = { 1774 .pre_page_flip = &evergreen_pre_page_flip, 1775 .page_flip = &evergreen_page_flip, 1776 .post_page_flip = &evergreen_post_page_flip, 1777 }, 1778 }; 1779 1780 static struct radeon_asic cayman_asic = { 1781 .init = &cayman_init, 1782 .fini = &cayman_fini, 1783 .suspend = &cayman_suspend, 1784 .resume = &cayman_resume, 1785 .asic_reset = &cayman_asic_reset, 1786 .vga_set_state = &r600_vga_set_state, 1787 .ioctl_wait_idle = r600_ioctl_wait_idle, 1788 .gui_idle = &r600_gui_idle, 1789 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1790 .get_xclk = &rv770_get_xclk, 1791 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1792 .gart = { 1793 .tlb_flush = &cayman_pcie_gart_tlb_flush, 1794 .set_page = &rs600_gart_set_page, 1795 }, 1796 .vm = { 1797 .init = &cayman_vm_init, 1798 .fini = &cayman_vm_fini, 1799 .pt_ring_index = R600_RING_TYPE_DMA_INDEX, 1800 .set_page = &cayman_vm_set_page, 1801 }, 1802 .ring = { 1803 [RADEON_RING_TYPE_GFX_INDEX] = { 1804 .ib_execute = &cayman_ring_ib_execute, 1805 .ib_parse = &evergreen_ib_parse, 1806 .emit_fence = &cayman_fence_ring_emit, 1807 .emit_semaphore = &r600_semaphore_ring_emit, 1808 .cs_parse = &evergreen_cs_parse, 1809 .ring_test = &r600_ring_test, 1810 .ib_test = &r600_ib_test, 1811 .is_lockup = &cayman_gfx_is_lockup, 1812 .vm_flush = &cayman_vm_flush, 1813 .get_rptr = &radeon_ring_generic_get_rptr, 1814 .get_wptr = &radeon_ring_generic_get_wptr, 1815 .set_wptr = &radeon_ring_generic_set_wptr, 1816 }, 1817 [CAYMAN_RING_TYPE_CP1_INDEX] = { 1818 .ib_execute = &cayman_ring_ib_execute, 1819 .ib_parse = &evergreen_ib_parse, 1820 .emit_fence = &cayman_fence_ring_emit, 1821 .emit_semaphore = &r600_semaphore_ring_emit, 1822 .cs_parse = &evergreen_cs_parse, 1823 .ring_test = &r600_ring_test, 1824 .ib_test = &r600_ib_test, 1825 .is_lockup = &cayman_gfx_is_lockup, 1826 .vm_flush = &cayman_vm_flush, 1827 .get_rptr = &radeon_ring_generic_get_rptr, 1828 .get_wptr = &radeon_ring_generic_get_wptr, 1829 .set_wptr = &radeon_ring_generic_set_wptr, 1830 }, 1831 [CAYMAN_RING_TYPE_CP2_INDEX] = { 1832 .ib_execute = &cayman_ring_ib_execute, 1833 .ib_parse = &evergreen_ib_parse, 1834 .emit_fence = &cayman_fence_ring_emit, 1835 .emit_semaphore = &r600_semaphore_ring_emit, 1836 .cs_parse = &evergreen_cs_parse, 1837 .ring_test = &r600_ring_test, 1838 .ib_test = &r600_ib_test, 1839 .is_lockup = &cayman_gfx_is_lockup, 1840 .vm_flush = &cayman_vm_flush, 1841 .get_rptr = &radeon_ring_generic_get_rptr, 1842 .get_wptr = &radeon_ring_generic_get_wptr, 1843 .set_wptr = &radeon_ring_generic_set_wptr, 1844 }, 1845 [R600_RING_TYPE_DMA_INDEX] = { 1846 .ib_execute = &cayman_dma_ring_ib_execute, 1847 .ib_parse = &evergreen_dma_ib_parse, 1848 .emit_fence = &evergreen_dma_fence_ring_emit, 1849 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1850 .cs_parse = &evergreen_dma_cs_parse, 1851 .ring_test = &r600_dma_ring_test, 1852 .ib_test = &r600_dma_ib_test, 1853 .is_lockup = &cayman_dma_is_lockup, 1854 .vm_flush = &cayman_dma_vm_flush, 1855 .get_rptr = &radeon_ring_generic_get_rptr, 1856 .get_wptr = &radeon_ring_generic_get_wptr, 1857 .set_wptr = &radeon_ring_generic_set_wptr, 1858 }, 1859 [CAYMAN_RING_TYPE_DMA1_INDEX] = { 1860 .ib_execute = &cayman_dma_ring_ib_execute, 1861 .ib_parse = &evergreen_dma_ib_parse, 1862 .emit_fence = &evergreen_dma_fence_ring_emit, 1863 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1864 .cs_parse = &evergreen_dma_cs_parse, 1865 .ring_test = &r600_dma_ring_test, 1866 .ib_test = &r600_dma_ib_test, 1867 .is_lockup = &cayman_dma_is_lockup, 1868 .vm_flush = &cayman_dma_vm_flush, 1869 .get_rptr = &radeon_ring_generic_get_rptr, 1870 .get_wptr = &radeon_ring_generic_get_wptr, 1871 .set_wptr = &radeon_ring_generic_set_wptr, 1872 }, 1873 [R600_RING_TYPE_UVD_INDEX] = { 1874 .ib_execute = &r600_uvd_ib_execute, 1875 .emit_fence = &r600_uvd_fence_emit, 1876 .emit_semaphore = &cayman_uvd_semaphore_emit, 1877 .cs_parse = &radeon_uvd_cs_parse, 1878 .ring_test = &r600_uvd_ring_test, 1879 .ib_test = &r600_uvd_ib_test, 1880 .is_lockup = &radeon_ring_test_lockup, 1881 .get_rptr = &radeon_ring_generic_get_rptr, 1882 .get_wptr = &radeon_ring_generic_get_wptr, 1883 .set_wptr = &radeon_ring_generic_set_wptr, 1884 } 1885 }, 1886 .irq = { 1887 .set = &evergreen_irq_set, 1888 .process = &evergreen_irq_process, 1889 }, 1890 .display = { 1891 .bandwidth_update = &evergreen_bandwidth_update, 1892 .get_vblank_counter = &evergreen_get_vblank_counter, 1893 .wait_for_vblank = &dce4_wait_for_vblank, 1894 .set_backlight_level = &atombios_set_backlight_level, 1895 .get_backlight_level = &atombios_get_backlight_level, 1896 .hdmi_enable = &evergreen_hdmi_enable, 1897 .hdmi_setmode = &evergreen_hdmi_setmode, 1898 }, 1899 .copy = { 1900 .blit = &r600_copy_blit, 1901 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1902 .dma = &evergreen_copy_dma, 1903 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1904 .copy = &evergreen_copy_dma, 1905 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1906 }, 1907 .surface = { 1908 .set_reg = r600_set_surface_reg, 1909 .clear_reg = r600_clear_surface_reg, 1910 }, 1911 .hpd = { 1912 .init = &evergreen_hpd_init, 1913 .fini = &evergreen_hpd_fini, 1914 .sense = &evergreen_hpd_sense, 1915 .set_polarity = &evergreen_hpd_set_polarity, 1916 }, 1917 .pm = { 1918 .misc = &evergreen_pm_misc, 1919 .prepare = &evergreen_pm_prepare, 1920 .finish = &evergreen_pm_finish, 1921 .init_profile = &btc_pm_init_profile, 1922 .get_dynpm_state = &r600_pm_get_dynpm_state, 1923 .get_engine_clock = &radeon_atom_get_engine_clock, 1924 .set_engine_clock = &radeon_atom_set_engine_clock, 1925 .get_memory_clock = &radeon_atom_get_memory_clock, 1926 .set_memory_clock = &radeon_atom_set_memory_clock, 1927 .get_pcie_lanes = &r600_get_pcie_lanes, 1928 .set_pcie_lanes = &r600_set_pcie_lanes, 1929 .set_clock_gating = NULL, 1930 .set_uvd_clocks = &evergreen_set_uvd_clocks, 1931 .get_temperature = &evergreen_get_temp, 1932 }, 1933 .dpm = { 1934 .init = &ni_dpm_init, 1935 .setup_asic = &ni_dpm_setup_asic, 1936 .enable = &ni_dpm_enable, 1937 .disable = &ni_dpm_disable, 1938 .pre_set_power_state = &ni_dpm_pre_set_power_state, 1939 .set_power_state = &ni_dpm_set_power_state, 1940 .post_set_power_state = &ni_dpm_post_set_power_state, 1941 .display_configuration_changed = &cypress_dpm_display_configuration_changed, 1942 .fini = &ni_dpm_fini, 1943 .get_sclk = &ni_dpm_get_sclk, 1944 .get_mclk = &ni_dpm_get_mclk, 1945 .print_power_state = &ni_dpm_print_power_state, 1946 .debugfs_print_current_performance_level = &ni_dpm_debugfs_print_current_performance_level, 1947 .force_performance_level = &ni_dpm_force_performance_level, 1948 .vblank_too_short = &ni_dpm_vblank_too_short, 1949 }, 1950 .pflip = { 1951 .pre_page_flip = &evergreen_pre_page_flip, 1952 .page_flip = &evergreen_page_flip, 1953 .post_page_flip = &evergreen_post_page_flip, 1954 }, 1955 }; 1956 1957 static struct radeon_asic trinity_asic = { 1958 .init = &cayman_init, 1959 .fini = &cayman_fini, 1960 .suspend = &cayman_suspend, 1961 .resume = &cayman_resume, 1962 .asic_reset = &cayman_asic_reset, 1963 .vga_set_state = &r600_vga_set_state, 1964 .ioctl_wait_idle = r600_ioctl_wait_idle, 1965 .gui_idle = &r600_gui_idle, 1966 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1967 .get_xclk = &r600_get_xclk, 1968 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1969 .gart = { 1970 .tlb_flush = &cayman_pcie_gart_tlb_flush, 1971 .set_page = &rs600_gart_set_page, 1972 }, 1973 .vm = { 1974 .init = &cayman_vm_init, 1975 .fini = &cayman_vm_fini, 1976 .pt_ring_index = R600_RING_TYPE_DMA_INDEX, 1977 .set_page = &cayman_vm_set_page, 1978 }, 1979 .ring = { 1980 [RADEON_RING_TYPE_GFX_INDEX] = { 1981 .ib_execute = &cayman_ring_ib_execute, 1982 .ib_parse = &evergreen_ib_parse, 1983 .emit_fence = &cayman_fence_ring_emit, 1984 .emit_semaphore = &r600_semaphore_ring_emit, 1985 .cs_parse = &evergreen_cs_parse, 1986 .ring_test = &r600_ring_test, 1987 .ib_test = &r600_ib_test, 1988 .is_lockup = &cayman_gfx_is_lockup, 1989 .vm_flush = &cayman_vm_flush, 1990 .get_rptr = &radeon_ring_generic_get_rptr, 1991 .get_wptr = &radeon_ring_generic_get_wptr, 1992 .set_wptr = &radeon_ring_generic_set_wptr, 1993 }, 1994 [CAYMAN_RING_TYPE_CP1_INDEX] = { 1995 .ib_execute = &cayman_ring_ib_execute, 1996 .ib_parse = &evergreen_ib_parse, 1997 .emit_fence = &cayman_fence_ring_emit, 1998 .emit_semaphore = &r600_semaphore_ring_emit, 1999 .cs_parse = &evergreen_cs_parse, 2000 .ring_test = &r600_ring_test, 2001 .ib_test = &r600_ib_test, 2002 .is_lockup = &cayman_gfx_is_lockup, 2003 .vm_flush = &cayman_vm_flush, 2004 .get_rptr = &radeon_ring_generic_get_rptr, 2005 .get_wptr = &radeon_ring_generic_get_wptr, 2006 .set_wptr = &radeon_ring_generic_set_wptr, 2007 }, 2008 [CAYMAN_RING_TYPE_CP2_INDEX] = { 2009 .ib_execute = &cayman_ring_ib_execute, 2010 .ib_parse = &evergreen_ib_parse, 2011 .emit_fence = &cayman_fence_ring_emit, 2012 .emit_semaphore = &r600_semaphore_ring_emit, 2013 .cs_parse = &evergreen_cs_parse, 2014 .ring_test = &r600_ring_test, 2015 .ib_test = &r600_ib_test, 2016 .is_lockup = &cayman_gfx_is_lockup, 2017 .vm_flush = &cayman_vm_flush, 2018 .get_rptr = &radeon_ring_generic_get_rptr, 2019 .get_wptr = &radeon_ring_generic_get_wptr, 2020 .set_wptr = &radeon_ring_generic_set_wptr, 2021 }, 2022 [R600_RING_TYPE_DMA_INDEX] = { 2023 .ib_execute = &cayman_dma_ring_ib_execute, 2024 .ib_parse = &evergreen_dma_ib_parse, 2025 .emit_fence = &evergreen_dma_fence_ring_emit, 2026 .emit_semaphore = &r600_dma_semaphore_ring_emit, 2027 .cs_parse = &evergreen_dma_cs_parse, 2028 .ring_test = &r600_dma_ring_test, 2029 .ib_test = &r600_dma_ib_test, 2030 .is_lockup = &cayman_dma_is_lockup, 2031 .vm_flush = &cayman_dma_vm_flush, 2032 .get_rptr = &radeon_ring_generic_get_rptr, 2033 .get_wptr = &radeon_ring_generic_get_wptr, 2034 .set_wptr = &radeon_ring_generic_set_wptr, 2035 }, 2036 [CAYMAN_RING_TYPE_DMA1_INDEX] = { 2037 .ib_execute = &cayman_dma_ring_ib_execute, 2038 .ib_parse = &evergreen_dma_ib_parse, 2039 .emit_fence = &evergreen_dma_fence_ring_emit, 2040 .emit_semaphore = &r600_dma_semaphore_ring_emit, 2041 .cs_parse = &evergreen_dma_cs_parse, 2042 .ring_test = &r600_dma_ring_test, 2043 .ib_test = &r600_dma_ib_test, 2044 .is_lockup = &cayman_dma_is_lockup, 2045 .vm_flush = &cayman_dma_vm_flush, 2046 .get_rptr = &radeon_ring_generic_get_rptr, 2047 .get_wptr = &radeon_ring_generic_get_wptr, 2048 .set_wptr = &radeon_ring_generic_set_wptr, 2049 }, 2050 [R600_RING_TYPE_UVD_INDEX] = { 2051 .ib_execute = &r600_uvd_ib_execute, 2052 .emit_fence = &r600_uvd_fence_emit, 2053 .emit_semaphore = &cayman_uvd_semaphore_emit, 2054 .cs_parse = &radeon_uvd_cs_parse, 2055 .ring_test = &r600_uvd_ring_test, 2056 .ib_test = &r600_uvd_ib_test, 2057 .is_lockup = &radeon_ring_test_lockup, 2058 .get_rptr = &radeon_ring_generic_get_rptr, 2059 .get_wptr = &radeon_ring_generic_get_wptr, 2060 .set_wptr = &radeon_ring_generic_set_wptr, 2061 } 2062 }, 2063 .irq = { 2064 .set = &evergreen_irq_set, 2065 .process = &evergreen_irq_process, 2066 }, 2067 .display = { 2068 .bandwidth_update = &dce6_bandwidth_update, 2069 .get_vblank_counter = &evergreen_get_vblank_counter, 2070 .wait_for_vblank = &dce4_wait_for_vblank, 2071 .set_backlight_level = &atombios_set_backlight_level, 2072 .get_backlight_level = &atombios_get_backlight_level, 2073 }, 2074 .copy = { 2075 .blit = &r600_copy_blit, 2076 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 2077 .dma = &evergreen_copy_dma, 2078 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 2079 .copy = &evergreen_copy_dma, 2080 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 2081 }, 2082 .surface = { 2083 .set_reg = r600_set_surface_reg, 2084 .clear_reg = r600_clear_surface_reg, 2085 }, 2086 .hpd = { 2087 .init = &evergreen_hpd_init, 2088 .fini = &evergreen_hpd_fini, 2089 .sense = &evergreen_hpd_sense, 2090 .set_polarity = &evergreen_hpd_set_polarity, 2091 }, 2092 .pm = { 2093 .misc = &evergreen_pm_misc, 2094 .prepare = &evergreen_pm_prepare, 2095 .finish = &evergreen_pm_finish, 2096 .init_profile = &sumo_pm_init_profile, 2097 .get_dynpm_state = &r600_pm_get_dynpm_state, 2098 .get_engine_clock = &radeon_atom_get_engine_clock, 2099 .set_engine_clock = &radeon_atom_set_engine_clock, 2100 .get_memory_clock = NULL, 2101 .set_memory_clock = NULL, 2102 .get_pcie_lanes = NULL, 2103 .set_pcie_lanes = NULL, 2104 .set_clock_gating = NULL, 2105 .set_uvd_clocks = &sumo_set_uvd_clocks, 2106 .get_temperature = &tn_get_temp, 2107 }, 2108 .dpm = { 2109 .init = &trinity_dpm_init, 2110 .setup_asic = &trinity_dpm_setup_asic, 2111 .enable = &trinity_dpm_enable, 2112 .disable = &trinity_dpm_disable, 2113 .pre_set_power_state = &trinity_dpm_pre_set_power_state, 2114 .set_power_state = &trinity_dpm_set_power_state, 2115 .post_set_power_state = &trinity_dpm_post_set_power_state, 2116 .display_configuration_changed = &trinity_dpm_display_configuration_changed, 2117 .fini = &trinity_dpm_fini, 2118 .get_sclk = &trinity_dpm_get_sclk, 2119 .get_mclk = &trinity_dpm_get_mclk, 2120 .print_power_state = &trinity_dpm_print_power_state, 2121 .debugfs_print_current_performance_level = &trinity_dpm_debugfs_print_current_performance_level, 2122 .force_performance_level = &trinity_dpm_force_performance_level, 2123 }, 2124 .pflip = { 2125 .pre_page_flip = &evergreen_pre_page_flip, 2126 .page_flip = &evergreen_page_flip, 2127 .post_page_flip = &evergreen_post_page_flip, 2128 }, 2129 }; 2130 2131 static struct radeon_asic si_asic = { 2132 .init = &si_init, 2133 .fini = &si_fini, 2134 .suspend = &si_suspend, 2135 .resume = &si_resume, 2136 .asic_reset = &si_asic_reset, 2137 .vga_set_state = &r600_vga_set_state, 2138 .ioctl_wait_idle = r600_ioctl_wait_idle, 2139 .gui_idle = &r600_gui_idle, 2140 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 2141 .get_xclk = &si_get_xclk, 2142 .get_gpu_clock_counter = &si_get_gpu_clock_counter, 2143 .gart = { 2144 .tlb_flush = &si_pcie_gart_tlb_flush, 2145 .set_page = &rs600_gart_set_page, 2146 }, 2147 .vm = { 2148 .init = &si_vm_init, 2149 .fini = &si_vm_fini, 2150 .pt_ring_index = R600_RING_TYPE_DMA_INDEX, 2151 .set_page = &si_vm_set_page, 2152 }, 2153 .ring = { 2154 [RADEON_RING_TYPE_GFX_INDEX] = { 2155 .ib_execute = &si_ring_ib_execute, 2156 .ib_parse = &si_ib_parse, 2157 .emit_fence = &si_fence_ring_emit, 2158 .emit_semaphore = &r600_semaphore_ring_emit, 2159 .cs_parse = NULL, 2160 .ring_test = &r600_ring_test, 2161 .ib_test = &r600_ib_test, 2162 .is_lockup = &si_gfx_is_lockup, 2163 .vm_flush = &si_vm_flush, 2164 .get_rptr = &radeon_ring_generic_get_rptr, 2165 .get_wptr = &radeon_ring_generic_get_wptr, 2166 .set_wptr = &radeon_ring_generic_set_wptr, 2167 }, 2168 [CAYMAN_RING_TYPE_CP1_INDEX] = { 2169 .ib_execute = &si_ring_ib_execute, 2170 .ib_parse = &si_ib_parse, 2171 .emit_fence = &si_fence_ring_emit, 2172 .emit_semaphore = &r600_semaphore_ring_emit, 2173 .cs_parse = NULL, 2174 .ring_test = &r600_ring_test, 2175 .ib_test = &r600_ib_test, 2176 .is_lockup = &si_gfx_is_lockup, 2177 .vm_flush = &si_vm_flush, 2178 .get_rptr = &radeon_ring_generic_get_rptr, 2179 .get_wptr = &radeon_ring_generic_get_wptr, 2180 .set_wptr = &radeon_ring_generic_set_wptr, 2181 }, 2182 [CAYMAN_RING_TYPE_CP2_INDEX] = { 2183 .ib_execute = &si_ring_ib_execute, 2184 .ib_parse = &si_ib_parse, 2185 .emit_fence = &si_fence_ring_emit, 2186 .emit_semaphore = &r600_semaphore_ring_emit, 2187 .cs_parse = NULL, 2188 .ring_test = &r600_ring_test, 2189 .ib_test = &r600_ib_test, 2190 .is_lockup = &si_gfx_is_lockup, 2191 .vm_flush = &si_vm_flush, 2192 .get_rptr = &radeon_ring_generic_get_rptr, 2193 .get_wptr = &radeon_ring_generic_get_wptr, 2194 .set_wptr = &radeon_ring_generic_set_wptr, 2195 }, 2196 [R600_RING_TYPE_DMA_INDEX] = { 2197 .ib_execute = &cayman_dma_ring_ib_execute, 2198 .ib_parse = &evergreen_dma_ib_parse, 2199 .emit_fence = &evergreen_dma_fence_ring_emit, 2200 .emit_semaphore = &r600_dma_semaphore_ring_emit, 2201 .cs_parse = NULL, 2202 .ring_test = &r600_dma_ring_test, 2203 .ib_test = &r600_dma_ib_test, 2204 .is_lockup = &si_dma_is_lockup, 2205 .vm_flush = &si_dma_vm_flush, 2206 .get_rptr = &radeon_ring_generic_get_rptr, 2207 .get_wptr = &radeon_ring_generic_get_wptr, 2208 .set_wptr = &radeon_ring_generic_set_wptr, 2209 }, 2210 [CAYMAN_RING_TYPE_DMA1_INDEX] = { 2211 .ib_execute = &cayman_dma_ring_ib_execute, 2212 .ib_parse = &evergreen_dma_ib_parse, 2213 .emit_fence = &evergreen_dma_fence_ring_emit, 2214 .emit_semaphore = &r600_dma_semaphore_ring_emit, 2215 .cs_parse = NULL, 2216 .ring_test = &r600_dma_ring_test, 2217 .ib_test = &r600_dma_ib_test, 2218 .is_lockup = &si_dma_is_lockup, 2219 .vm_flush = &si_dma_vm_flush, 2220 .get_rptr = &radeon_ring_generic_get_rptr, 2221 .get_wptr = &radeon_ring_generic_get_wptr, 2222 .set_wptr = &radeon_ring_generic_set_wptr, 2223 }, 2224 [R600_RING_TYPE_UVD_INDEX] = { 2225 .ib_execute = &r600_uvd_ib_execute, 2226 .emit_fence = &r600_uvd_fence_emit, 2227 .emit_semaphore = &cayman_uvd_semaphore_emit, 2228 .cs_parse = &radeon_uvd_cs_parse, 2229 .ring_test = &r600_uvd_ring_test, 2230 .ib_test = &r600_uvd_ib_test, 2231 .is_lockup = &radeon_ring_test_lockup, 2232 .get_rptr = &radeon_ring_generic_get_rptr, 2233 .get_wptr = &radeon_ring_generic_get_wptr, 2234 .set_wptr = &radeon_ring_generic_set_wptr, 2235 } 2236 }, 2237 .irq = { 2238 .set = &si_irq_set, 2239 .process = &si_irq_process, 2240 }, 2241 .display = { 2242 .bandwidth_update = &dce6_bandwidth_update, 2243 .get_vblank_counter = &evergreen_get_vblank_counter, 2244 .wait_for_vblank = &dce4_wait_for_vblank, 2245 .set_backlight_level = &atombios_set_backlight_level, 2246 .get_backlight_level = &atombios_get_backlight_level, 2247 }, 2248 .copy = { 2249 .blit = NULL, 2250 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 2251 .dma = &si_copy_dma, 2252 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 2253 .copy = &si_copy_dma, 2254 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 2255 }, 2256 .surface = { 2257 .set_reg = r600_set_surface_reg, 2258 .clear_reg = r600_clear_surface_reg, 2259 }, 2260 .hpd = { 2261 .init = &evergreen_hpd_init, 2262 .fini = &evergreen_hpd_fini, 2263 .sense = &evergreen_hpd_sense, 2264 .set_polarity = &evergreen_hpd_set_polarity, 2265 }, 2266 .pm = { 2267 .misc = &evergreen_pm_misc, 2268 .prepare = &evergreen_pm_prepare, 2269 .finish = &evergreen_pm_finish, 2270 .init_profile = &sumo_pm_init_profile, 2271 .get_dynpm_state = &r600_pm_get_dynpm_state, 2272 .get_engine_clock = &radeon_atom_get_engine_clock, 2273 .set_engine_clock = &radeon_atom_set_engine_clock, 2274 .get_memory_clock = &radeon_atom_get_memory_clock, 2275 .set_memory_clock = &radeon_atom_set_memory_clock, 2276 .get_pcie_lanes = &r600_get_pcie_lanes, 2277 .set_pcie_lanes = &r600_set_pcie_lanes, 2278 .set_clock_gating = NULL, 2279 .set_uvd_clocks = &si_set_uvd_clocks, 2280 .get_temperature = &si_get_temp, 2281 }, 2282 .dpm = { 2283 .init = &si_dpm_init, 2284 .setup_asic = &si_dpm_setup_asic, 2285 .enable = &si_dpm_enable, 2286 .disable = &si_dpm_disable, 2287 .pre_set_power_state = &si_dpm_pre_set_power_state, 2288 .set_power_state = &si_dpm_set_power_state, 2289 .post_set_power_state = &si_dpm_post_set_power_state, 2290 .display_configuration_changed = &si_dpm_display_configuration_changed, 2291 .fini = &si_dpm_fini, 2292 .get_sclk = &ni_dpm_get_sclk, 2293 .get_mclk = &ni_dpm_get_mclk, 2294 .print_power_state = &ni_dpm_print_power_state, 2295 .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level, 2296 .force_performance_level = &si_dpm_force_performance_level, 2297 .vblank_too_short = &ni_dpm_vblank_too_short, 2298 }, 2299 .pflip = { 2300 .pre_page_flip = &evergreen_pre_page_flip, 2301 .page_flip = &evergreen_page_flip, 2302 .post_page_flip = &evergreen_post_page_flip, 2303 }, 2304 }; 2305 2306 static struct radeon_asic ci_asic = { 2307 .init = &cik_init, 2308 .fini = &cik_fini, 2309 .suspend = &cik_suspend, 2310 .resume = &cik_resume, 2311 .asic_reset = &cik_asic_reset, 2312 .vga_set_state = &r600_vga_set_state, 2313 .ioctl_wait_idle = NULL, 2314 .gui_idle = &r600_gui_idle, 2315 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 2316 .get_xclk = &cik_get_xclk, 2317 .get_gpu_clock_counter = &cik_get_gpu_clock_counter, 2318 .gart = { 2319 .tlb_flush = &cik_pcie_gart_tlb_flush, 2320 .set_page = &rs600_gart_set_page, 2321 }, 2322 .vm = { 2323 .init = &cik_vm_init, 2324 .fini = &cik_vm_fini, 2325 .pt_ring_index = R600_RING_TYPE_DMA_INDEX, 2326 .set_page = &cik_vm_set_page, 2327 }, 2328 .ring = { 2329 [RADEON_RING_TYPE_GFX_INDEX] = { 2330 .ib_execute = &cik_ring_ib_execute, 2331 .ib_parse = &cik_ib_parse, 2332 .emit_fence = &cik_fence_gfx_ring_emit, 2333 .emit_semaphore = &cik_semaphore_ring_emit, 2334 .cs_parse = NULL, 2335 .ring_test = &cik_ring_test, 2336 .ib_test = &cik_ib_test, 2337 .is_lockup = &cik_gfx_is_lockup, 2338 .vm_flush = &cik_vm_flush, 2339 .get_rptr = &radeon_ring_generic_get_rptr, 2340 .get_wptr = &radeon_ring_generic_get_wptr, 2341 .set_wptr = &radeon_ring_generic_set_wptr, 2342 }, 2343 [CAYMAN_RING_TYPE_CP1_INDEX] = { 2344 .ib_execute = &cik_ring_ib_execute, 2345 .ib_parse = &cik_ib_parse, 2346 .emit_fence = &cik_fence_compute_ring_emit, 2347 .emit_semaphore = &cik_semaphore_ring_emit, 2348 .cs_parse = NULL, 2349 .ring_test = &cik_ring_test, 2350 .ib_test = &cik_ib_test, 2351 .is_lockup = &cik_gfx_is_lockup, 2352 .vm_flush = &cik_vm_flush, 2353 .get_rptr = &cik_compute_ring_get_rptr, 2354 .get_wptr = &cik_compute_ring_get_wptr, 2355 .set_wptr = &cik_compute_ring_set_wptr, 2356 }, 2357 [CAYMAN_RING_TYPE_CP2_INDEX] = { 2358 .ib_execute = &cik_ring_ib_execute, 2359 .ib_parse = &cik_ib_parse, 2360 .emit_fence = &cik_fence_compute_ring_emit, 2361 .emit_semaphore = &cik_semaphore_ring_emit, 2362 .cs_parse = NULL, 2363 .ring_test = &cik_ring_test, 2364 .ib_test = &cik_ib_test, 2365 .is_lockup = &cik_gfx_is_lockup, 2366 .vm_flush = &cik_vm_flush, 2367 .get_rptr = &cik_compute_ring_get_rptr, 2368 .get_wptr = &cik_compute_ring_get_wptr, 2369 .set_wptr = &cik_compute_ring_set_wptr, 2370 }, 2371 [R600_RING_TYPE_DMA_INDEX] = { 2372 .ib_execute = &cik_sdma_ring_ib_execute, 2373 .ib_parse = &cik_ib_parse, 2374 .emit_fence = &cik_sdma_fence_ring_emit, 2375 .emit_semaphore = &cik_sdma_semaphore_ring_emit, 2376 .cs_parse = NULL, 2377 .ring_test = &cik_sdma_ring_test, 2378 .ib_test = &cik_sdma_ib_test, 2379 .is_lockup = &cik_sdma_is_lockup, 2380 .vm_flush = &cik_dma_vm_flush, 2381 .get_rptr = &radeon_ring_generic_get_rptr, 2382 .get_wptr = &radeon_ring_generic_get_wptr, 2383 .set_wptr = &radeon_ring_generic_set_wptr, 2384 }, 2385 [CAYMAN_RING_TYPE_DMA1_INDEX] = { 2386 .ib_execute = &cik_sdma_ring_ib_execute, 2387 .ib_parse = &cik_ib_parse, 2388 .emit_fence = &cik_sdma_fence_ring_emit, 2389 .emit_semaphore = &cik_sdma_semaphore_ring_emit, 2390 .cs_parse = NULL, 2391 .ring_test = &cik_sdma_ring_test, 2392 .ib_test = &cik_sdma_ib_test, 2393 .is_lockup = &cik_sdma_is_lockup, 2394 .vm_flush = &cik_dma_vm_flush, 2395 .get_rptr = &radeon_ring_generic_get_rptr, 2396 .get_wptr = &radeon_ring_generic_get_wptr, 2397 .set_wptr = &radeon_ring_generic_set_wptr, 2398 }, 2399 [R600_RING_TYPE_UVD_INDEX] = { 2400 .ib_execute = &r600_uvd_ib_execute, 2401 .emit_fence = &r600_uvd_fence_emit, 2402 .emit_semaphore = &cayman_uvd_semaphore_emit, 2403 .cs_parse = &radeon_uvd_cs_parse, 2404 .ring_test = &r600_uvd_ring_test, 2405 .ib_test = &r600_uvd_ib_test, 2406 .is_lockup = &radeon_ring_test_lockup, 2407 .get_rptr = &radeon_ring_generic_get_rptr, 2408 .get_wptr = &radeon_ring_generic_get_wptr, 2409 .set_wptr = &radeon_ring_generic_set_wptr, 2410 } 2411 }, 2412 .irq = { 2413 .set = &cik_irq_set, 2414 .process = &cik_irq_process, 2415 }, 2416 .display = { 2417 .bandwidth_update = &dce8_bandwidth_update, 2418 .get_vblank_counter = &evergreen_get_vblank_counter, 2419 .wait_for_vblank = &dce4_wait_for_vblank, 2420 }, 2421 .copy = { 2422 .blit = NULL, 2423 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 2424 .dma = &cik_copy_dma, 2425 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 2426 .copy = &cik_copy_dma, 2427 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 2428 }, 2429 .surface = { 2430 .set_reg = r600_set_surface_reg, 2431 .clear_reg = r600_clear_surface_reg, 2432 }, 2433 .hpd = { 2434 .init = &evergreen_hpd_init, 2435 .fini = &evergreen_hpd_fini, 2436 .sense = &evergreen_hpd_sense, 2437 .set_polarity = &evergreen_hpd_set_polarity, 2438 }, 2439 .pm = { 2440 .misc = &evergreen_pm_misc, 2441 .prepare = &evergreen_pm_prepare, 2442 .finish = &evergreen_pm_finish, 2443 .init_profile = &sumo_pm_init_profile, 2444 .get_dynpm_state = &r600_pm_get_dynpm_state, 2445 .get_engine_clock = &radeon_atom_get_engine_clock, 2446 .set_engine_clock = &radeon_atom_set_engine_clock, 2447 .get_memory_clock = &radeon_atom_get_memory_clock, 2448 .set_memory_clock = &radeon_atom_set_memory_clock, 2449 .get_pcie_lanes = NULL, 2450 .set_pcie_lanes = NULL, 2451 .set_clock_gating = NULL, 2452 .set_uvd_clocks = &cik_set_uvd_clocks, 2453 }, 2454 .pflip = { 2455 .pre_page_flip = &evergreen_pre_page_flip, 2456 .page_flip = &evergreen_page_flip, 2457 .post_page_flip = &evergreen_post_page_flip, 2458 }, 2459 }; 2460 2461 static struct radeon_asic kv_asic = { 2462 .init = &cik_init, 2463 .fini = &cik_fini, 2464 .suspend = &cik_suspend, 2465 .resume = &cik_resume, 2466 .asic_reset = &cik_asic_reset, 2467 .vga_set_state = &r600_vga_set_state, 2468 .ioctl_wait_idle = NULL, 2469 .gui_idle = &r600_gui_idle, 2470 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 2471 .get_xclk = &cik_get_xclk, 2472 .get_gpu_clock_counter = &cik_get_gpu_clock_counter, 2473 .gart = { 2474 .tlb_flush = &cik_pcie_gart_tlb_flush, 2475 .set_page = &rs600_gart_set_page, 2476 }, 2477 .vm = { 2478 .init = &cik_vm_init, 2479 .fini = &cik_vm_fini, 2480 .pt_ring_index = R600_RING_TYPE_DMA_INDEX, 2481 .set_page = &cik_vm_set_page, 2482 }, 2483 .ring = { 2484 [RADEON_RING_TYPE_GFX_INDEX] = { 2485 .ib_execute = &cik_ring_ib_execute, 2486 .ib_parse = &cik_ib_parse, 2487 .emit_fence = &cik_fence_gfx_ring_emit, 2488 .emit_semaphore = &cik_semaphore_ring_emit, 2489 .cs_parse = NULL, 2490 .ring_test = &cik_ring_test, 2491 .ib_test = &cik_ib_test, 2492 .is_lockup = &cik_gfx_is_lockup, 2493 .vm_flush = &cik_vm_flush, 2494 .get_rptr = &radeon_ring_generic_get_rptr, 2495 .get_wptr = &radeon_ring_generic_get_wptr, 2496 .set_wptr = &radeon_ring_generic_set_wptr, 2497 }, 2498 [CAYMAN_RING_TYPE_CP1_INDEX] = { 2499 .ib_execute = &cik_ring_ib_execute, 2500 .ib_parse = &cik_ib_parse, 2501 .emit_fence = &cik_fence_compute_ring_emit, 2502 .emit_semaphore = &cik_semaphore_ring_emit, 2503 .cs_parse = NULL, 2504 .ring_test = &cik_ring_test, 2505 .ib_test = &cik_ib_test, 2506 .is_lockup = &cik_gfx_is_lockup, 2507 .vm_flush = &cik_vm_flush, 2508 .get_rptr = &cik_compute_ring_get_rptr, 2509 .get_wptr = &cik_compute_ring_get_wptr, 2510 .set_wptr = &cik_compute_ring_set_wptr, 2511 }, 2512 [CAYMAN_RING_TYPE_CP2_INDEX] = { 2513 .ib_execute = &cik_ring_ib_execute, 2514 .ib_parse = &cik_ib_parse, 2515 .emit_fence = &cik_fence_compute_ring_emit, 2516 .emit_semaphore = &cik_semaphore_ring_emit, 2517 .cs_parse = NULL, 2518 .ring_test = &cik_ring_test, 2519 .ib_test = &cik_ib_test, 2520 .is_lockup = &cik_gfx_is_lockup, 2521 .vm_flush = &cik_vm_flush, 2522 .get_rptr = &cik_compute_ring_get_rptr, 2523 .get_wptr = &cik_compute_ring_get_wptr, 2524 .set_wptr = &cik_compute_ring_set_wptr, 2525 }, 2526 [R600_RING_TYPE_DMA_INDEX] = { 2527 .ib_execute = &cik_sdma_ring_ib_execute, 2528 .ib_parse = &cik_ib_parse, 2529 .emit_fence = &cik_sdma_fence_ring_emit, 2530 .emit_semaphore = &cik_sdma_semaphore_ring_emit, 2531 .cs_parse = NULL, 2532 .ring_test = &cik_sdma_ring_test, 2533 .ib_test = &cik_sdma_ib_test, 2534 .is_lockup = &cik_sdma_is_lockup, 2535 .vm_flush = &cik_dma_vm_flush, 2536 .get_rptr = &radeon_ring_generic_get_rptr, 2537 .get_wptr = &radeon_ring_generic_get_wptr, 2538 .set_wptr = &radeon_ring_generic_set_wptr, 2539 }, 2540 [CAYMAN_RING_TYPE_DMA1_INDEX] = { 2541 .ib_execute = &cik_sdma_ring_ib_execute, 2542 .ib_parse = &cik_ib_parse, 2543 .emit_fence = &cik_sdma_fence_ring_emit, 2544 .emit_semaphore = &cik_sdma_semaphore_ring_emit, 2545 .cs_parse = NULL, 2546 .ring_test = &cik_sdma_ring_test, 2547 .ib_test = &cik_sdma_ib_test, 2548 .is_lockup = &cik_sdma_is_lockup, 2549 .vm_flush = &cik_dma_vm_flush, 2550 .get_rptr = &radeon_ring_generic_get_rptr, 2551 .get_wptr = &radeon_ring_generic_get_wptr, 2552 .set_wptr = &radeon_ring_generic_set_wptr, 2553 }, 2554 [R600_RING_TYPE_UVD_INDEX] = { 2555 .ib_execute = &r600_uvd_ib_execute, 2556 .emit_fence = &r600_uvd_fence_emit, 2557 .emit_semaphore = &cayman_uvd_semaphore_emit, 2558 .cs_parse = &radeon_uvd_cs_parse, 2559 .ring_test = &r600_uvd_ring_test, 2560 .ib_test = &r600_uvd_ib_test, 2561 .is_lockup = &radeon_ring_test_lockup, 2562 .get_rptr = &radeon_ring_generic_get_rptr, 2563 .get_wptr = &radeon_ring_generic_get_wptr, 2564 .set_wptr = &radeon_ring_generic_set_wptr, 2565 } 2566 }, 2567 .irq = { 2568 .set = &cik_irq_set, 2569 .process = &cik_irq_process, 2570 }, 2571 .display = { 2572 .bandwidth_update = &dce8_bandwidth_update, 2573 .get_vblank_counter = &evergreen_get_vblank_counter, 2574 .wait_for_vblank = &dce4_wait_for_vblank, 2575 }, 2576 .copy = { 2577 .blit = NULL, 2578 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 2579 .dma = &cik_copy_dma, 2580 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 2581 .copy = &cik_copy_dma, 2582 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 2583 }, 2584 .surface = { 2585 .set_reg = r600_set_surface_reg, 2586 .clear_reg = r600_clear_surface_reg, 2587 }, 2588 .hpd = { 2589 .init = &evergreen_hpd_init, 2590 .fini = &evergreen_hpd_fini, 2591 .sense = &evergreen_hpd_sense, 2592 .set_polarity = &evergreen_hpd_set_polarity, 2593 }, 2594 .pm = { 2595 .misc = &evergreen_pm_misc, 2596 .prepare = &evergreen_pm_prepare, 2597 .finish = &evergreen_pm_finish, 2598 .init_profile = &sumo_pm_init_profile, 2599 .get_dynpm_state = &r600_pm_get_dynpm_state, 2600 .get_engine_clock = &radeon_atom_get_engine_clock, 2601 .set_engine_clock = &radeon_atom_set_engine_clock, 2602 .get_memory_clock = &radeon_atom_get_memory_clock, 2603 .set_memory_clock = &radeon_atom_set_memory_clock, 2604 .get_pcie_lanes = NULL, 2605 .set_pcie_lanes = NULL, 2606 .set_clock_gating = NULL, 2607 .set_uvd_clocks = &cik_set_uvd_clocks, 2608 }, 2609 .pflip = { 2610 .pre_page_flip = &evergreen_pre_page_flip, 2611 .page_flip = &evergreen_page_flip, 2612 .post_page_flip = &evergreen_post_page_flip, 2613 }, 2614 }; 2615 2616 /** 2617 * radeon_asic_init - register asic specific callbacks 2618 * 2619 * @rdev: radeon device pointer 2620 * 2621 * Registers the appropriate asic specific callbacks for each 2622 * chip family. Also sets other asics specific info like the number 2623 * of crtcs and the register aperture accessors (all asics). 2624 * Returns 0 for success. 2625 */ 2626 int radeon_asic_init(struct radeon_device *rdev) 2627 { 2628 radeon_register_accessor_init(rdev); 2629 2630 /* set the number of crtcs */ 2631 if (rdev->flags & RADEON_SINGLE_CRTC) 2632 rdev->num_crtc = 1; 2633 else 2634 rdev->num_crtc = 2; 2635 2636 rdev->has_uvd = false; 2637 2638 switch (rdev->family) { 2639 case CHIP_R100: 2640 case CHIP_RV100: 2641 case CHIP_RS100: 2642 case CHIP_RV200: 2643 case CHIP_RS200: 2644 rdev->asic = &r100_asic; 2645 break; 2646 case CHIP_R200: 2647 case CHIP_RV250: 2648 case CHIP_RS300: 2649 case CHIP_RV280: 2650 rdev->asic = &r200_asic; 2651 break; 2652 case CHIP_R300: 2653 case CHIP_R350: 2654 case CHIP_RV350: 2655 case CHIP_RV380: 2656 if (rdev->flags & RADEON_IS_PCIE) 2657 rdev->asic = &r300_asic_pcie; 2658 else 2659 rdev->asic = &r300_asic; 2660 break; 2661 case CHIP_R420: 2662 case CHIP_R423: 2663 case CHIP_RV410: 2664 rdev->asic = &r420_asic; 2665 /* handle macs */ 2666 if (rdev->bios == NULL) { 2667 rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock; 2668 rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock; 2669 rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock; 2670 rdev->asic->pm.set_memory_clock = NULL; 2671 rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level; 2672 } 2673 break; 2674 case CHIP_RS400: 2675 case CHIP_RS480: 2676 rdev->asic = &rs400_asic; 2677 break; 2678 case CHIP_RS600: 2679 rdev->asic = &rs600_asic; 2680 break; 2681 case CHIP_RS690: 2682 case CHIP_RS740: 2683 rdev->asic = &rs690_asic; 2684 break; 2685 case CHIP_RV515: 2686 rdev->asic = &rv515_asic; 2687 break; 2688 case CHIP_R520: 2689 case CHIP_RV530: 2690 case CHIP_RV560: 2691 case CHIP_RV570: 2692 case CHIP_R580: 2693 rdev->asic = &r520_asic; 2694 break; 2695 case CHIP_R600: 2696 rdev->asic = &r600_asic; 2697 break; 2698 case CHIP_RV610: 2699 case CHIP_RV630: 2700 case CHIP_RV620: 2701 case CHIP_RV635: 2702 case CHIP_RV670: 2703 rdev->asic = &rv6xx_asic; 2704 rdev->has_uvd = true; 2705 break; 2706 case CHIP_RS780: 2707 case CHIP_RS880: 2708 rdev->asic = &rs780_asic; 2709 rdev->has_uvd = true; 2710 break; 2711 case CHIP_RV770: 2712 case CHIP_RV730: 2713 case CHIP_RV710: 2714 case CHIP_RV740: 2715 rdev->asic = &rv770_asic; 2716 rdev->has_uvd = true; 2717 break; 2718 case CHIP_CEDAR: 2719 case CHIP_REDWOOD: 2720 case CHIP_JUNIPER: 2721 case CHIP_CYPRESS: 2722 case CHIP_HEMLOCK: 2723 /* set num crtcs */ 2724 if (rdev->family == CHIP_CEDAR) 2725 rdev->num_crtc = 4; 2726 else 2727 rdev->num_crtc = 6; 2728 rdev->asic = &evergreen_asic; 2729 rdev->has_uvd = true; 2730 break; 2731 case CHIP_PALM: 2732 case CHIP_SUMO: 2733 case CHIP_SUMO2: 2734 rdev->asic = &sumo_asic; 2735 rdev->has_uvd = true; 2736 break; 2737 case CHIP_BARTS: 2738 case CHIP_TURKS: 2739 case CHIP_CAICOS: 2740 /* set num crtcs */ 2741 if (rdev->family == CHIP_CAICOS) 2742 rdev->num_crtc = 4; 2743 else 2744 rdev->num_crtc = 6; 2745 rdev->asic = &btc_asic; 2746 rdev->has_uvd = true; 2747 break; 2748 case CHIP_CAYMAN: 2749 rdev->asic = &cayman_asic; 2750 /* set num crtcs */ 2751 rdev->num_crtc = 6; 2752 rdev->has_uvd = true; 2753 break; 2754 case CHIP_ARUBA: 2755 rdev->asic = &trinity_asic; 2756 /* set num crtcs */ 2757 rdev->num_crtc = 4; 2758 rdev->has_uvd = true; 2759 break; 2760 case CHIP_TAHITI: 2761 case CHIP_PITCAIRN: 2762 case CHIP_VERDE: 2763 case CHIP_OLAND: 2764 case CHIP_HAINAN: 2765 rdev->asic = &si_asic; 2766 /* set num crtcs */ 2767 if (rdev->family == CHIP_HAINAN) 2768 rdev->num_crtc = 0; 2769 else if (rdev->family == CHIP_OLAND) 2770 rdev->num_crtc = 2; 2771 else 2772 rdev->num_crtc = 6; 2773 if (rdev->family == CHIP_HAINAN) 2774 rdev->has_uvd = false; 2775 else 2776 rdev->has_uvd = true; 2777 break; 2778 case CHIP_BONAIRE: 2779 rdev->asic = &ci_asic; 2780 rdev->num_crtc = 6; 2781 break; 2782 case CHIP_KAVERI: 2783 case CHIP_KABINI: 2784 rdev->asic = &kv_asic; 2785 /* set num crtcs */ 2786 if (rdev->family == CHIP_KAVERI) 2787 rdev->num_crtc = 4; 2788 else 2789 rdev->num_crtc = 2; 2790 break; 2791 default: 2792 /* FIXME: not supported yet */ 2793 return -EINVAL; 2794 } 2795 2796 if (rdev->flags & RADEON_IS_IGP) { 2797 rdev->asic->pm.get_memory_clock = NULL; 2798 rdev->asic->pm.set_memory_clock = NULL; 2799 } 2800 2801 return 0; 2802 } 2803 2804