xref: /linux/drivers/gpu/drm/radeon/radeon_asic.c (revision b889fcf63cb62e7fdb7816565e28f44dbe4a76a5)
1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 
29 #include <linux/console.h>
30 #include <drm/drmP.h>
31 #include <drm/drm_crtc_helper.h>
32 #include <drm/radeon_drm.h>
33 #include <linux/vgaarb.h>
34 #include <linux/vga_switcheroo.h>
35 #include "radeon_reg.h"
36 #include "radeon.h"
37 #include "radeon_asic.h"
38 #include "atom.h"
39 
40 /*
41  * Registers accessors functions.
42  */
43 /**
44  * radeon_invalid_rreg - dummy reg read function
45  *
46  * @rdev: radeon device pointer
47  * @reg: offset of register
48  *
49  * Dummy register read function.  Used for register blocks
50  * that certain asics don't have (all asics).
51  * Returns the value in the register.
52  */
53 static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
54 {
55 	DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
56 	BUG_ON(1);
57 	return 0;
58 }
59 
60 /**
61  * radeon_invalid_wreg - dummy reg write function
62  *
63  * @rdev: radeon device pointer
64  * @reg: offset of register
65  * @v: value to write to the register
66  *
67  * Dummy register read function.  Used for register blocks
68  * that certain asics don't have (all asics).
69  */
70 static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
71 {
72 	DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
73 		  reg, v);
74 	BUG_ON(1);
75 }
76 
77 /**
78  * radeon_register_accessor_init - sets up the register accessor callbacks
79  *
80  * @rdev: radeon device pointer
81  *
82  * Sets up the register accessor callbacks for various register
83  * apertures.  Not all asics have all apertures (all asics).
84  */
85 static void radeon_register_accessor_init(struct radeon_device *rdev)
86 {
87 	rdev->mc_rreg = &radeon_invalid_rreg;
88 	rdev->mc_wreg = &radeon_invalid_wreg;
89 	rdev->pll_rreg = &radeon_invalid_rreg;
90 	rdev->pll_wreg = &radeon_invalid_wreg;
91 	rdev->pciep_rreg = &radeon_invalid_rreg;
92 	rdev->pciep_wreg = &radeon_invalid_wreg;
93 
94 	/* Don't change order as we are overridding accessor. */
95 	if (rdev->family < CHIP_RV515) {
96 		rdev->pcie_reg_mask = 0xff;
97 	} else {
98 		rdev->pcie_reg_mask = 0x7ff;
99 	}
100 	/* FIXME: not sure here */
101 	if (rdev->family <= CHIP_R580) {
102 		rdev->pll_rreg = &r100_pll_rreg;
103 		rdev->pll_wreg = &r100_pll_wreg;
104 	}
105 	if (rdev->family >= CHIP_R420) {
106 		rdev->mc_rreg = &r420_mc_rreg;
107 		rdev->mc_wreg = &r420_mc_wreg;
108 	}
109 	if (rdev->family >= CHIP_RV515) {
110 		rdev->mc_rreg = &rv515_mc_rreg;
111 		rdev->mc_wreg = &rv515_mc_wreg;
112 	}
113 	if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
114 		rdev->mc_rreg = &rs400_mc_rreg;
115 		rdev->mc_wreg = &rs400_mc_wreg;
116 	}
117 	if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
118 		rdev->mc_rreg = &rs690_mc_rreg;
119 		rdev->mc_wreg = &rs690_mc_wreg;
120 	}
121 	if (rdev->family == CHIP_RS600) {
122 		rdev->mc_rreg = &rs600_mc_rreg;
123 		rdev->mc_wreg = &rs600_mc_wreg;
124 	}
125 	if (rdev->family >= CHIP_R600) {
126 		rdev->pciep_rreg = &r600_pciep_rreg;
127 		rdev->pciep_wreg = &r600_pciep_wreg;
128 	}
129 }
130 
131 
132 /* helper to disable agp */
133 /**
134  * radeon_agp_disable - AGP disable helper function
135  *
136  * @rdev: radeon device pointer
137  *
138  * Removes AGP flags and changes the gart callbacks on AGP
139  * cards when using the internal gart rather than AGP (all asics).
140  */
141 void radeon_agp_disable(struct radeon_device *rdev)
142 {
143 	rdev->flags &= ~RADEON_IS_AGP;
144 	if (rdev->family >= CHIP_R600) {
145 		DRM_INFO("Forcing AGP to PCIE mode\n");
146 		rdev->flags |= RADEON_IS_PCIE;
147 	} else if (rdev->family >= CHIP_RV515 ||
148 			rdev->family == CHIP_RV380 ||
149 			rdev->family == CHIP_RV410 ||
150 			rdev->family == CHIP_R423) {
151 		DRM_INFO("Forcing AGP to PCIE mode\n");
152 		rdev->flags |= RADEON_IS_PCIE;
153 		rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
154 		rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
155 	} else {
156 		DRM_INFO("Forcing AGP to PCI mode\n");
157 		rdev->flags |= RADEON_IS_PCI;
158 		rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
159 		rdev->asic->gart.set_page = &r100_pci_gart_set_page;
160 	}
161 	rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
162 }
163 
164 /*
165  * ASIC
166  */
167 static struct radeon_asic r100_asic = {
168 	.init = &r100_init,
169 	.fini = &r100_fini,
170 	.suspend = &r100_suspend,
171 	.resume = &r100_resume,
172 	.vga_set_state = &r100_vga_set_state,
173 	.asic_reset = &r100_asic_reset,
174 	.ioctl_wait_idle = NULL,
175 	.gui_idle = &r100_gui_idle,
176 	.mc_wait_for_idle = &r100_mc_wait_for_idle,
177 	.gart = {
178 		.tlb_flush = &r100_pci_gart_tlb_flush,
179 		.set_page = &r100_pci_gart_set_page,
180 	},
181 	.ring = {
182 		[RADEON_RING_TYPE_GFX_INDEX] = {
183 			.ib_execute = &r100_ring_ib_execute,
184 			.emit_fence = &r100_fence_ring_emit,
185 			.emit_semaphore = &r100_semaphore_ring_emit,
186 			.cs_parse = &r100_cs_parse,
187 			.ring_start = &r100_ring_start,
188 			.ring_test = &r100_ring_test,
189 			.ib_test = &r100_ib_test,
190 			.is_lockup = &r100_gpu_is_lockup,
191 		}
192 	},
193 	.irq = {
194 		.set = &r100_irq_set,
195 		.process = &r100_irq_process,
196 	},
197 	.display = {
198 		.bandwidth_update = &r100_bandwidth_update,
199 		.get_vblank_counter = &r100_get_vblank_counter,
200 		.wait_for_vblank = &r100_wait_for_vblank,
201 		.set_backlight_level = &radeon_legacy_set_backlight_level,
202 		.get_backlight_level = &radeon_legacy_get_backlight_level,
203 	},
204 	.copy = {
205 		.blit = &r100_copy_blit,
206 		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
207 		.dma = NULL,
208 		.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
209 		.copy = &r100_copy_blit,
210 		.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
211 	},
212 	.surface = {
213 		.set_reg = r100_set_surface_reg,
214 		.clear_reg = r100_clear_surface_reg,
215 	},
216 	.hpd = {
217 		.init = &r100_hpd_init,
218 		.fini = &r100_hpd_fini,
219 		.sense = &r100_hpd_sense,
220 		.set_polarity = &r100_hpd_set_polarity,
221 	},
222 	.pm = {
223 		.misc = &r100_pm_misc,
224 		.prepare = &r100_pm_prepare,
225 		.finish = &r100_pm_finish,
226 		.init_profile = &r100_pm_init_profile,
227 		.get_dynpm_state = &r100_pm_get_dynpm_state,
228 		.get_engine_clock = &radeon_legacy_get_engine_clock,
229 		.set_engine_clock = &radeon_legacy_set_engine_clock,
230 		.get_memory_clock = &radeon_legacy_get_memory_clock,
231 		.set_memory_clock = NULL,
232 		.get_pcie_lanes = NULL,
233 		.set_pcie_lanes = NULL,
234 		.set_clock_gating = &radeon_legacy_set_clock_gating,
235 	},
236 	.pflip = {
237 		.pre_page_flip = &r100_pre_page_flip,
238 		.page_flip = &r100_page_flip,
239 		.post_page_flip = &r100_post_page_flip,
240 	},
241 };
242 
243 static struct radeon_asic r200_asic = {
244 	.init = &r100_init,
245 	.fini = &r100_fini,
246 	.suspend = &r100_suspend,
247 	.resume = &r100_resume,
248 	.vga_set_state = &r100_vga_set_state,
249 	.asic_reset = &r100_asic_reset,
250 	.ioctl_wait_idle = NULL,
251 	.gui_idle = &r100_gui_idle,
252 	.mc_wait_for_idle = &r100_mc_wait_for_idle,
253 	.gart = {
254 		.tlb_flush = &r100_pci_gart_tlb_flush,
255 		.set_page = &r100_pci_gart_set_page,
256 	},
257 	.ring = {
258 		[RADEON_RING_TYPE_GFX_INDEX] = {
259 			.ib_execute = &r100_ring_ib_execute,
260 			.emit_fence = &r100_fence_ring_emit,
261 			.emit_semaphore = &r100_semaphore_ring_emit,
262 			.cs_parse = &r100_cs_parse,
263 			.ring_start = &r100_ring_start,
264 			.ring_test = &r100_ring_test,
265 			.ib_test = &r100_ib_test,
266 			.is_lockup = &r100_gpu_is_lockup,
267 		}
268 	},
269 	.irq = {
270 		.set = &r100_irq_set,
271 		.process = &r100_irq_process,
272 	},
273 	.display = {
274 		.bandwidth_update = &r100_bandwidth_update,
275 		.get_vblank_counter = &r100_get_vblank_counter,
276 		.wait_for_vblank = &r100_wait_for_vblank,
277 		.set_backlight_level = &radeon_legacy_set_backlight_level,
278 		.get_backlight_level = &radeon_legacy_get_backlight_level,
279 	},
280 	.copy = {
281 		.blit = &r100_copy_blit,
282 		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
283 		.dma = &r200_copy_dma,
284 		.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
285 		.copy = &r100_copy_blit,
286 		.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
287 	},
288 	.surface = {
289 		.set_reg = r100_set_surface_reg,
290 		.clear_reg = r100_clear_surface_reg,
291 	},
292 	.hpd = {
293 		.init = &r100_hpd_init,
294 		.fini = &r100_hpd_fini,
295 		.sense = &r100_hpd_sense,
296 		.set_polarity = &r100_hpd_set_polarity,
297 	},
298 	.pm = {
299 		.misc = &r100_pm_misc,
300 		.prepare = &r100_pm_prepare,
301 		.finish = &r100_pm_finish,
302 		.init_profile = &r100_pm_init_profile,
303 		.get_dynpm_state = &r100_pm_get_dynpm_state,
304 		.get_engine_clock = &radeon_legacy_get_engine_clock,
305 		.set_engine_clock = &radeon_legacy_set_engine_clock,
306 		.get_memory_clock = &radeon_legacy_get_memory_clock,
307 		.set_memory_clock = NULL,
308 		.get_pcie_lanes = NULL,
309 		.set_pcie_lanes = NULL,
310 		.set_clock_gating = &radeon_legacy_set_clock_gating,
311 	},
312 	.pflip = {
313 		.pre_page_flip = &r100_pre_page_flip,
314 		.page_flip = &r100_page_flip,
315 		.post_page_flip = &r100_post_page_flip,
316 	},
317 };
318 
319 static struct radeon_asic r300_asic = {
320 	.init = &r300_init,
321 	.fini = &r300_fini,
322 	.suspend = &r300_suspend,
323 	.resume = &r300_resume,
324 	.vga_set_state = &r100_vga_set_state,
325 	.asic_reset = &r300_asic_reset,
326 	.ioctl_wait_idle = NULL,
327 	.gui_idle = &r100_gui_idle,
328 	.mc_wait_for_idle = &r300_mc_wait_for_idle,
329 	.gart = {
330 		.tlb_flush = &r100_pci_gart_tlb_flush,
331 		.set_page = &r100_pci_gart_set_page,
332 	},
333 	.ring = {
334 		[RADEON_RING_TYPE_GFX_INDEX] = {
335 			.ib_execute = &r100_ring_ib_execute,
336 			.emit_fence = &r300_fence_ring_emit,
337 			.emit_semaphore = &r100_semaphore_ring_emit,
338 			.cs_parse = &r300_cs_parse,
339 			.ring_start = &r300_ring_start,
340 			.ring_test = &r100_ring_test,
341 			.ib_test = &r100_ib_test,
342 			.is_lockup = &r100_gpu_is_lockup,
343 		}
344 	},
345 	.irq = {
346 		.set = &r100_irq_set,
347 		.process = &r100_irq_process,
348 	},
349 	.display = {
350 		.bandwidth_update = &r100_bandwidth_update,
351 		.get_vblank_counter = &r100_get_vblank_counter,
352 		.wait_for_vblank = &r100_wait_for_vblank,
353 		.set_backlight_level = &radeon_legacy_set_backlight_level,
354 		.get_backlight_level = &radeon_legacy_get_backlight_level,
355 	},
356 	.copy = {
357 		.blit = &r100_copy_blit,
358 		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
359 		.dma = &r200_copy_dma,
360 		.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
361 		.copy = &r100_copy_blit,
362 		.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
363 	},
364 	.surface = {
365 		.set_reg = r100_set_surface_reg,
366 		.clear_reg = r100_clear_surface_reg,
367 	},
368 	.hpd = {
369 		.init = &r100_hpd_init,
370 		.fini = &r100_hpd_fini,
371 		.sense = &r100_hpd_sense,
372 		.set_polarity = &r100_hpd_set_polarity,
373 	},
374 	.pm = {
375 		.misc = &r100_pm_misc,
376 		.prepare = &r100_pm_prepare,
377 		.finish = &r100_pm_finish,
378 		.init_profile = &r100_pm_init_profile,
379 		.get_dynpm_state = &r100_pm_get_dynpm_state,
380 		.get_engine_clock = &radeon_legacy_get_engine_clock,
381 		.set_engine_clock = &radeon_legacy_set_engine_clock,
382 		.get_memory_clock = &radeon_legacy_get_memory_clock,
383 		.set_memory_clock = NULL,
384 		.get_pcie_lanes = &rv370_get_pcie_lanes,
385 		.set_pcie_lanes = &rv370_set_pcie_lanes,
386 		.set_clock_gating = &radeon_legacy_set_clock_gating,
387 	},
388 	.pflip = {
389 		.pre_page_flip = &r100_pre_page_flip,
390 		.page_flip = &r100_page_flip,
391 		.post_page_flip = &r100_post_page_flip,
392 	},
393 };
394 
395 static struct radeon_asic r300_asic_pcie = {
396 	.init = &r300_init,
397 	.fini = &r300_fini,
398 	.suspend = &r300_suspend,
399 	.resume = &r300_resume,
400 	.vga_set_state = &r100_vga_set_state,
401 	.asic_reset = &r300_asic_reset,
402 	.ioctl_wait_idle = NULL,
403 	.gui_idle = &r100_gui_idle,
404 	.mc_wait_for_idle = &r300_mc_wait_for_idle,
405 	.gart = {
406 		.tlb_flush = &rv370_pcie_gart_tlb_flush,
407 		.set_page = &rv370_pcie_gart_set_page,
408 	},
409 	.ring = {
410 		[RADEON_RING_TYPE_GFX_INDEX] = {
411 			.ib_execute = &r100_ring_ib_execute,
412 			.emit_fence = &r300_fence_ring_emit,
413 			.emit_semaphore = &r100_semaphore_ring_emit,
414 			.cs_parse = &r300_cs_parse,
415 			.ring_start = &r300_ring_start,
416 			.ring_test = &r100_ring_test,
417 			.ib_test = &r100_ib_test,
418 			.is_lockup = &r100_gpu_is_lockup,
419 		}
420 	},
421 	.irq = {
422 		.set = &r100_irq_set,
423 		.process = &r100_irq_process,
424 	},
425 	.display = {
426 		.bandwidth_update = &r100_bandwidth_update,
427 		.get_vblank_counter = &r100_get_vblank_counter,
428 		.wait_for_vblank = &r100_wait_for_vblank,
429 		.set_backlight_level = &radeon_legacy_set_backlight_level,
430 		.get_backlight_level = &radeon_legacy_get_backlight_level,
431 	},
432 	.copy = {
433 		.blit = &r100_copy_blit,
434 		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
435 		.dma = &r200_copy_dma,
436 		.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
437 		.copy = &r100_copy_blit,
438 		.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
439 	},
440 	.surface = {
441 		.set_reg = r100_set_surface_reg,
442 		.clear_reg = r100_clear_surface_reg,
443 	},
444 	.hpd = {
445 		.init = &r100_hpd_init,
446 		.fini = &r100_hpd_fini,
447 		.sense = &r100_hpd_sense,
448 		.set_polarity = &r100_hpd_set_polarity,
449 	},
450 	.pm = {
451 		.misc = &r100_pm_misc,
452 		.prepare = &r100_pm_prepare,
453 		.finish = &r100_pm_finish,
454 		.init_profile = &r100_pm_init_profile,
455 		.get_dynpm_state = &r100_pm_get_dynpm_state,
456 		.get_engine_clock = &radeon_legacy_get_engine_clock,
457 		.set_engine_clock = &radeon_legacy_set_engine_clock,
458 		.get_memory_clock = &radeon_legacy_get_memory_clock,
459 		.set_memory_clock = NULL,
460 		.get_pcie_lanes = &rv370_get_pcie_lanes,
461 		.set_pcie_lanes = &rv370_set_pcie_lanes,
462 		.set_clock_gating = &radeon_legacy_set_clock_gating,
463 	},
464 	.pflip = {
465 		.pre_page_flip = &r100_pre_page_flip,
466 		.page_flip = &r100_page_flip,
467 		.post_page_flip = &r100_post_page_flip,
468 	},
469 };
470 
471 static struct radeon_asic r420_asic = {
472 	.init = &r420_init,
473 	.fini = &r420_fini,
474 	.suspend = &r420_suspend,
475 	.resume = &r420_resume,
476 	.vga_set_state = &r100_vga_set_state,
477 	.asic_reset = &r300_asic_reset,
478 	.ioctl_wait_idle = NULL,
479 	.gui_idle = &r100_gui_idle,
480 	.mc_wait_for_idle = &r300_mc_wait_for_idle,
481 	.gart = {
482 		.tlb_flush = &rv370_pcie_gart_tlb_flush,
483 		.set_page = &rv370_pcie_gart_set_page,
484 	},
485 	.ring = {
486 		[RADEON_RING_TYPE_GFX_INDEX] = {
487 			.ib_execute = &r100_ring_ib_execute,
488 			.emit_fence = &r300_fence_ring_emit,
489 			.emit_semaphore = &r100_semaphore_ring_emit,
490 			.cs_parse = &r300_cs_parse,
491 			.ring_start = &r300_ring_start,
492 			.ring_test = &r100_ring_test,
493 			.ib_test = &r100_ib_test,
494 			.is_lockup = &r100_gpu_is_lockup,
495 		}
496 	},
497 	.irq = {
498 		.set = &r100_irq_set,
499 		.process = &r100_irq_process,
500 	},
501 	.display = {
502 		.bandwidth_update = &r100_bandwidth_update,
503 		.get_vblank_counter = &r100_get_vblank_counter,
504 		.wait_for_vblank = &r100_wait_for_vblank,
505 		.set_backlight_level = &atombios_set_backlight_level,
506 		.get_backlight_level = &atombios_get_backlight_level,
507 	},
508 	.copy = {
509 		.blit = &r100_copy_blit,
510 		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
511 		.dma = &r200_copy_dma,
512 		.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
513 		.copy = &r100_copy_blit,
514 		.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
515 	},
516 	.surface = {
517 		.set_reg = r100_set_surface_reg,
518 		.clear_reg = r100_clear_surface_reg,
519 	},
520 	.hpd = {
521 		.init = &r100_hpd_init,
522 		.fini = &r100_hpd_fini,
523 		.sense = &r100_hpd_sense,
524 		.set_polarity = &r100_hpd_set_polarity,
525 	},
526 	.pm = {
527 		.misc = &r100_pm_misc,
528 		.prepare = &r100_pm_prepare,
529 		.finish = &r100_pm_finish,
530 		.init_profile = &r420_pm_init_profile,
531 		.get_dynpm_state = &r100_pm_get_dynpm_state,
532 		.get_engine_clock = &radeon_atom_get_engine_clock,
533 		.set_engine_clock = &radeon_atom_set_engine_clock,
534 		.get_memory_clock = &radeon_atom_get_memory_clock,
535 		.set_memory_clock = &radeon_atom_set_memory_clock,
536 		.get_pcie_lanes = &rv370_get_pcie_lanes,
537 		.set_pcie_lanes = &rv370_set_pcie_lanes,
538 		.set_clock_gating = &radeon_atom_set_clock_gating,
539 	},
540 	.pflip = {
541 		.pre_page_flip = &r100_pre_page_flip,
542 		.page_flip = &r100_page_flip,
543 		.post_page_flip = &r100_post_page_flip,
544 	},
545 };
546 
547 static struct radeon_asic rs400_asic = {
548 	.init = &rs400_init,
549 	.fini = &rs400_fini,
550 	.suspend = &rs400_suspend,
551 	.resume = &rs400_resume,
552 	.vga_set_state = &r100_vga_set_state,
553 	.asic_reset = &r300_asic_reset,
554 	.ioctl_wait_idle = NULL,
555 	.gui_idle = &r100_gui_idle,
556 	.mc_wait_for_idle = &rs400_mc_wait_for_idle,
557 	.gart = {
558 		.tlb_flush = &rs400_gart_tlb_flush,
559 		.set_page = &rs400_gart_set_page,
560 	},
561 	.ring = {
562 		[RADEON_RING_TYPE_GFX_INDEX] = {
563 			.ib_execute = &r100_ring_ib_execute,
564 			.emit_fence = &r300_fence_ring_emit,
565 			.emit_semaphore = &r100_semaphore_ring_emit,
566 			.cs_parse = &r300_cs_parse,
567 			.ring_start = &r300_ring_start,
568 			.ring_test = &r100_ring_test,
569 			.ib_test = &r100_ib_test,
570 			.is_lockup = &r100_gpu_is_lockup,
571 		}
572 	},
573 	.irq = {
574 		.set = &r100_irq_set,
575 		.process = &r100_irq_process,
576 	},
577 	.display = {
578 		.bandwidth_update = &r100_bandwidth_update,
579 		.get_vblank_counter = &r100_get_vblank_counter,
580 		.wait_for_vblank = &r100_wait_for_vblank,
581 		.set_backlight_level = &radeon_legacy_set_backlight_level,
582 		.get_backlight_level = &radeon_legacy_get_backlight_level,
583 	},
584 	.copy = {
585 		.blit = &r100_copy_blit,
586 		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
587 		.dma = &r200_copy_dma,
588 		.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
589 		.copy = &r100_copy_blit,
590 		.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
591 	},
592 	.surface = {
593 		.set_reg = r100_set_surface_reg,
594 		.clear_reg = r100_clear_surface_reg,
595 	},
596 	.hpd = {
597 		.init = &r100_hpd_init,
598 		.fini = &r100_hpd_fini,
599 		.sense = &r100_hpd_sense,
600 		.set_polarity = &r100_hpd_set_polarity,
601 	},
602 	.pm = {
603 		.misc = &r100_pm_misc,
604 		.prepare = &r100_pm_prepare,
605 		.finish = &r100_pm_finish,
606 		.init_profile = &r100_pm_init_profile,
607 		.get_dynpm_state = &r100_pm_get_dynpm_state,
608 		.get_engine_clock = &radeon_legacy_get_engine_clock,
609 		.set_engine_clock = &radeon_legacy_set_engine_clock,
610 		.get_memory_clock = &radeon_legacy_get_memory_clock,
611 		.set_memory_clock = NULL,
612 		.get_pcie_lanes = NULL,
613 		.set_pcie_lanes = NULL,
614 		.set_clock_gating = &radeon_legacy_set_clock_gating,
615 	},
616 	.pflip = {
617 		.pre_page_flip = &r100_pre_page_flip,
618 		.page_flip = &r100_page_flip,
619 		.post_page_flip = &r100_post_page_flip,
620 	},
621 };
622 
623 static struct radeon_asic rs600_asic = {
624 	.init = &rs600_init,
625 	.fini = &rs600_fini,
626 	.suspend = &rs600_suspend,
627 	.resume = &rs600_resume,
628 	.vga_set_state = &r100_vga_set_state,
629 	.asic_reset = &rs600_asic_reset,
630 	.ioctl_wait_idle = NULL,
631 	.gui_idle = &r100_gui_idle,
632 	.mc_wait_for_idle = &rs600_mc_wait_for_idle,
633 	.gart = {
634 		.tlb_flush = &rs600_gart_tlb_flush,
635 		.set_page = &rs600_gart_set_page,
636 	},
637 	.ring = {
638 		[RADEON_RING_TYPE_GFX_INDEX] = {
639 			.ib_execute = &r100_ring_ib_execute,
640 			.emit_fence = &r300_fence_ring_emit,
641 			.emit_semaphore = &r100_semaphore_ring_emit,
642 			.cs_parse = &r300_cs_parse,
643 			.ring_start = &r300_ring_start,
644 			.ring_test = &r100_ring_test,
645 			.ib_test = &r100_ib_test,
646 			.is_lockup = &r100_gpu_is_lockup,
647 		}
648 	},
649 	.irq = {
650 		.set = &rs600_irq_set,
651 		.process = &rs600_irq_process,
652 	},
653 	.display = {
654 		.bandwidth_update = &rs600_bandwidth_update,
655 		.get_vblank_counter = &rs600_get_vblank_counter,
656 		.wait_for_vblank = &avivo_wait_for_vblank,
657 		.set_backlight_level = &atombios_set_backlight_level,
658 		.get_backlight_level = &atombios_get_backlight_level,
659 	},
660 	.copy = {
661 		.blit = &r100_copy_blit,
662 		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
663 		.dma = &r200_copy_dma,
664 		.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
665 		.copy = &r100_copy_blit,
666 		.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
667 	},
668 	.surface = {
669 		.set_reg = r100_set_surface_reg,
670 		.clear_reg = r100_clear_surface_reg,
671 	},
672 	.hpd = {
673 		.init = &rs600_hpd_init,
674 		.fini = &rs600_hpd_fini,
675 		.sense = &rs600_hpd_sense,
676 		.set_polarity = &rs600_hpd_set_polarity,
677 	},
678 	.pm = {
679 		.misc = &rs600_pm_misc,
680 		.prepare = &rs600_pm_prepare,
681 		.finish = &rs600_pm_finish,
682 		.init_profile = &r420_pm_init_profile,
683 		.get_dynpm_state = &r100_pm_get_dynpm_state,
684 		.get_engine_clock = &radeon_atom_get_engine_clock,
685 		.set_engine_clock = &radeon_atom_set_engine_clock,
686 		.get_memory_clock = &radeon_atom_get_memory_clock,
687 		.set_memory_clock = &radeon_atom_set_memory_clock,
688 		.get_pcie_lanes = NULL,
689 		.set_pcie_lanes = NULL,
690 		.set_clock_gating = &radeon_atom_set_clock_gating,
691 	},
692 	.pflip = {
693 		.pre_page_flip = &rs600_pre_page_flip,
694 		.page_flip = &rs600_page_flip,
695 		.post_page_flip = &rs600_post_page_flip,
696 	},
697 };
698 
699 static struct radeon_asic rs690_asic = {
700 	.init = &rs690_init,
701 	.fini = &rs690_fini,
702 	.suspend = &rs690_suspend,
703 	.resume = &rs690_resume,
704 	.vga_set_state = &r100_vga_set_state,
705 	.asic_reset = &rs600_asic_reset,
706 	.ioctl_wait_idle = NULL,
707 	.gui_idle = &r100_gui_idle,
708 	.mc_wait_for_idle = &rs690_mc_wait_for_idle,
709 	.gart = {
710 		.tlb_flush = &rs400_gart_tlb_flush,
711 		.set_page = &rs400_gart_set_page,
712 	},
713 	.ring = {
714 		[RADEON_RING_TYPE_GFX_INDEX] = {
715 			.ib_execute = &r100_ring_ib_execute,
716 			.emit_fence = &r300_fence_ring_emit,
717 			.emit_semaphore = &r100_semaphore_ring_emit,
718 			.cs_parse = &r300_cs_parse,
719 			.ring_start = &r300_ring_start,
720 			.ring_test = &r100_ring_test,
721 			.ib_test = &r100_ib_test,
722 			.is_lockup = &r100_gpu_is_lockup,
723 		}
724 	},
725 	.irq = {
726 		.set = &rs600_irq_set,
727 		.process = &rs600_irq_process,
728 	},
729 	.display = {
730 		.get_vblank_counter = &rs600_get_vblank_counter,
731 		.bandwidth_update = &rs690_bandwidth_update,
732 		.wait_for_vblank = &avivo_wait_for_vblank,
733 		.set_backlight_level = &atombios_set_backlight_level,
734 		.get_backlight_level = &atombios_get_backlight_level,
735 	},
736 	.copy = {
737 		.blit = &r100_copy_blit,
738 		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
739 		.dma = &r200_copy_dma,
740 		.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
741 		.copy = &r200_copy_dma,
742 		.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
743 	},
744 	.surface = {
745 		.set_reg = r100_set_surface_reg,
746 		.clear_reg = r100_clear_surface_reg,
747 	},
748 	.hpd = {
749 		.init = &rs600_hpd_init,
750 		.fini = &rs600_hpd_fini,
751 		.sense = &rs600_hpd_sense,
752 		.set_polarity = &rs600_hpd_set_polarity,
753 	},
754 	.pm = {
755 		.misc = &rs600_pm_misc,
756 		.prepare = &rs600_pm_prepare,
757 		.finish = &rs600_pm_finish,
758 		.init_profile = &r420_pm_init_profile,
759 		.get_dynpm_state = &r100_pm_get_dynpm_state,
760 		.get_engine_clock = &radeon_atom_get_engine_clock,
761 		.set_engine_clock = &radeon_atom_set_engine_clock,
762 		.get_memory_clock = &radeon_atom_get_memory_clock,
763 		.set_memory_clock = &radeon_atom_set_memory_clock,
764 		.get_pcie_lanes = NULL,
765 		.set_pcie_lanes = NULL,
766 		.set_clock_gating = &radeon_atom_set_clock_gating,
767 	},
768 	.pflip = {
769 		.pre_page_flip = &rs600_pre_page_flip,
770 		.page_flip = &rs600_page_flip,
771 		.post_page_flip = &rs600_post_page_flip,
772 	},
773 };
774 
775 static struct radeon_asic rv515_asic = {
776 	.init = &rv515_init,
777 	.fini = &rv515_fini,
778 	.suspend = &rv515_suspend,
779 	.resume = &rv515_resume,
780 	.vga_set_state = &r100_vga_set_state,
781 	.asic_reset = &rs600_asic_reset,
782 	.ioctl_wait_idle = NULL,
783 	.gui_idle = &r100_gui_idle,
784 	.mc_wait_for_idle = &rv515_mc_wait_for_idle,
785 	.gart = {
786 		.tlb_flush = &rv370_pcie_gart_tlb_flush,
787 		.set_page = &rv370_pcie_gart_set_page,
788 	},
789 	.ring = {
790 		[RADEON_RING_TYPE_GFX_INDEX] = {
791 			.ib_execute = &r100_ring_ib_execute,
792 			.emit_fence = &r300_fence_ring_emit,
793 			.emit_semaphore = &r100_semaphore_ring_emit,
794 			.cs_parse = &r300_cs_parse,
795 			.ring_start = &rv515_ring_start,
796 			.ring_test = &r100_ring_test,
797 			.ib_test = &r100_ib_test,
798 			.is_lockup = &r100_gpu_is_lockup,
799 		}
800 	},
801 	.irq = {
802 		.set = &rs600_irq_set,
803 		.process = &rs600_irq_process,
804 	},
805 	.display = {
806 		.get_vblank_counter = &rs600_get_vblank_counter,
807 		.bandwidth_update = &rv515_bandwidth_update,
808 		.wait_for_vblank = &avivo_wait_for_vblank,
809 		.set_backlight_level = &atombios_set_backlight_level,
810 		.get_backlight_level = &atombios_get_backlight_level,
811 	},
812 	.copy = {
813 		.blit = &r100_copy_blit,
814 		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
815 		.dma = &r200_copy_dma,
816 		.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
817 		.copy = &r100_copy_blit,
818 		.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
819 	},
820 	.surface = {
821 		.set_reg = r100_set_surface_reg,
822 		.clear_reg = r100_clear_surface_reg,
823 	},
824 	.hpd = {
825 		.init = &rs600_hpd_init,
826 		.fini = &rs600_hpd_fini,
827 		.sense = &rs600_hpd_sense,
828 		.set_polarity = &rs600_hpd_set_polarity,
829 	},
830 	.pm = {
831 		.misc = &rs600_pm_misc,
832 		.prepare = &rs600_pm_prepare,
833 		.finish = &rs600_pm_finish,
834 		.init_profile = &r420_pm_init_profile,
835 		.get_dynpm_state = &r100_pm_get_dynpm_state,
836 		.get_engine_clock = &radeon_atom_get_engine_clock,
837 		.set_engine_clock = &radeon_atom_set_engine_clock,
838 		.get_memory_clock = &radeon_atom_get_memory_clock,
839 		.set_memory_clock = &radeon_atom_set_memory_clock,
840 		.get_pcie_lanes = &rv370_get_pcie_lanes,
841 		.set_pcie_lanes = &rv370_set_pcie_lanes,
842 		.set_clock_gating = &radeon_atom_set_clock_gating,
843 	},
844 	.pflip = {
845 		.pre_page_flip = &rs600_pre_page_flip,
846 		.page_flip = &rs600_page_flip,
847 		.post_page_flip = &rs600_post_page_flip,
848 	},
849 };
850 
851 static struct radeon_asic r520_asic = {
852 	.init = &r520_init,
853 	.fini = &rv515_fini,
854 	.suspend = &rv515_suspend,
855 	.resume = &r520_resume,
856 	.vga_set_state = &r100_vga_set_state,
857 	.asic_reset = &rs600_asic_reset,
858 	.ioctl_wait_idle = NULL,
859 	.gui_idle = &r100_gui_idle,
860 	.mc_wait_for_idle = &r520_mc_wait_for_idle,
861 	.gart = {
862 		.tlb_flush = &rv370_pcie_gart_tlb_flush,
863 		.set_page = &rv370_pcie_gart_set_page,
864 	},
865 	.ring = {
866 		[RADEON_RING_TYPE_GFX_INDEX] = {
867 			.ib_execute = &r100_ring_ib_execute,
868 			.emit_fence = &r300_fence_ring_emit,
869 			.emit_semaphore = &r100_semaphore_ring_emit,
870 			.cs_parse = &r300_cs_parse,
871 			.ring_start = &rv515_ring_start,
872 			.ring_test = &r100_ring_test,
873 			.ib_test = &r100_ib_test,
874 			.is_lockup = &r100_gpu_is_lockup,
875 		}
876 	},
877 	.irq = {
878 		.set = &rs600_irq_set,
879 		.process = &rs600_irq_process,
880 	},
881 	.display = {
882 		.bandwidth_update = &rv515_bandwidth_update,
883 		.get_vblank_counter = &rs600_get_vblank_counter,
884 		.wait_for_vblank = &avivo_wait_for_vblank,
885 		.set_backlight_level = &atombios_set_backlight_level,
886 		.get_backlight_level = &atombios_get_backlight_level,
887 	},
888 	.copy = {
889 		.blit = &r100_copy_blit,
890 		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
891 		.dma = &r200_copy_dma,
892 		.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
893 		.copy = &r100_copy_blit,
894 		.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
895 	},
896 	.surface = {
897 		.set_reg = r100_set_surface_reg,
898 		.clear_reg = r100_clear_surface_reg,
899 	},
900 	.hpd = {
901 		.init = &rs600_hpd_init,
902 		.fini = &rs600_hpd_fini,
903 		.sense = &rs600_hpd_sense,
904 		.set_polarity = &rs600_hpd_set_polarity,
905 	},
906 	.pm = {
907 		.misc = &rs600_pm_misc,
908 		.prepare = &rs600_pm_prepare,
909 		.finish = &rs600_pm_finish,
910 		.init_profile = &r420_pm_init_profile,
911 		.get_dynpm_state = &r100_pm_get_dynpm_state,
912 		.get_engine_clock = &radeon_atom_get_engine_clock,
913 		.set_engine_clock = &radeon_atom_set_engine_clock,
914 		.get_memory_clock = &radeon_atom_get_memory_clock,
915 		.set_memory_clock = &radeon_atom_set_memory_clock,
916 		.get_pcie_lanes = &rv370_get_pcie_lanes,
917 		.set_pcie_lanes = &rv370_set_pcie_lanes,
918 		.set_clock_gating = &radeon_atom_set_clock_gating,
919 	},
920 	.pflip = {
921 		.pre_page_flip = &rs600_pre_page_flip,
922 		.page_flip = &rs600_page_flip,
923 		.post_page_flip = &rs600_post_page_flip,
924 	},
925 };
926 
927 static struct radeon_asic r600_asic = {
928 	.init = &r600_init,
929 	.fini = &r600_fini,
930 	.suspend = &r600_suspend,
931 	.resume = &r600_resume,
932 	.vga_set_state = &r600_vga_set_state,
933 	.asic_reset = &r600_asic_reset,
934 	.ioctl_wait_idle = r600_ioctl_wait_idle,
935 	.gui_idle = &r600_gui_idle,
936 	.mc_wait_for_idle = &r600_mc_wait_for_idle,
937 	.gart = {
938 		.tlb_flush = &r600_pcie_gart_tlb_flush,
939 		.set_page = &rs600_gart_set_page,
940 	},
941 	.ring = {
942 		[RADEON_RING_TYPE_GFX_INDEX] = {
943 			.ib_execute = &r600_ring_ib_execute,
944 			.emit_fence = &r600_fence_ring_emit,
945 			.emit_semaphore = &r600_semaphore_ring_emit,
946 			.cs_parse = &r600_cs_parse,
947 			.ring_test = &r600_ring_test,
948 			.ib_test = &r600_ib_test,
949 			.is_lockup = &r600_gpu_is_lockup,
950 		},
951 		[R600_RING_TYPE_DMA_INDEX] = {
952 			.ib_execute = &r600_dma_ring_ib_execute,
953 			.emit_fence = &r600_dma_fence_ring_emit,
954 			.emit_semaphore = &r600_dma_semaphore_ring_emit,
955 			.cs_parse = &r600_dma_cs_parse,
956 			.ring_test = &r600_dma_ring_test,
957 			.ib_test = &r600_dma_ib_test,
958 			.is_lockup = &r600_dma_is_lockup,
959 		}
960 	},
961 	.irq = {
962 		.set = &r600_irq_set,
963 		.process = &r600_irq_process,
964 	},
965 	.display = {
966 		.bandwidth_update = &rv515_bandwidth_update,
967 		.get_vblank_counter = &rs600_get_vblank_counter,
968 		.wait_for_vblank = &avivo_wait_for_vblank,
969 		.set_backlight_level = &atombios_set_backlight_level,
970 		.get_backlight_level = &atombios_get_backlight_level,
971 	},
972 	.copy = {
973 		.blit = &r600_copy_blit,
974 		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
975 		.dma = &r600_copy_dma,
976 		.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
977 		.copy = &r600_copy_dma,
978 		.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
979 	},
980 	.surface = {
981 		.set_reg = r600_set_surface_reg,
982 		.clear_reg = r600_clear_surface_reg,
983 	},
984 	.hpd = {
985 		.init = &r600_hpd_init,
986 		.fini = &r600_hpd_fini,
987 		.sense = &r600_hpd_sense,
988 		.set_polarity = &r600_hpd_set_polarity,
989 	},
990 	.pm = {
991 		.misc = &r600_pm_misc,
992 		.prepare = &rs600_pm_prepare,
993 		.finish = &rs600_pm_finish,
994 		.init_profile = &r600_pm_init_profile,
995 		.get_dynpm_state = &r600_pm_get_dynpm_state,
996 		.get_engine_clock = &radeon_atom_get_engine_clock,
997 		.set_engine_clock = &radeon_atom_set_engine_clock,
998 		.get_memory_clock = &radeon_atom_get_memory_clock,
999 		.set_memory_clock = &radeon_atom_set_memory_clock,
1000 		.get_pcie_lanes = &r600_get_pcie_lanes,
1001 		.set_pcie_lanes = &r600_set_pcie_lanes,
1002 		.set_clock_gating = NULL,
1003 	},
1004 	.pflip = {
1005 		.pre_page_flip = &rs600_pre_page_flip,
1006 		.page_flip = &rs600_page_flip,
1007 		.post_page_flip = &rs600_post_page_flip,
1008 	},
1009 };
1010 
1011 static struct radeon_asic rs780_asic = {
1012 	.init = &r600_init,
1013 	.fini = &r600_fini,
1014 	.suspend = &r600_suspend,
1015 	.resume = &r600_resume,
1016 	.vga_set_state = &r600_vga_set_state,
1017 	.asic_reset = &r600_asic_reset,
1018 	.ioctl_wait_idle = r600_ioctl_wait_idle,
1019 	.gui_idle = &r600_gui_idle,
1020 	.mc_wait_for_idle = &r600_mc_wait_for_idle,
1021 	.gart = {
1022 		.tlb_flush = &r600_pcie_gart_tlb_flush,
1023 		.set_page = &rs600_gart_set_page,
1024 	},
1025 	.ring = {
1026 		[RADEON_RING_TYPE_GFX_INDEX] = {
1027 			.ib_execute = &r600_ring_ib_execute,
1028 			.emit_fence = &r600_fence_ring_emit,
1029 			.emit_semaphore = &r600_semaphore_ring_emit,
1030 			.cs_parse = &r600_cs_parse,
1031 			.ring_test = &r600_ring_test,
1032 			.ib_test = &r600_ib_test,
1033 			.is_lockup = &r600_gpu_is_lockup,
1034 		},
1035 		[R600_RING_TYPE_DMA_INDEX] = {
1036 			.ib_execute = &r600_dma_ring_ib_execute,
1037 			.emit_fence = &r600_dma_fence_ring_emit,
1038 			.emit_semaphore = &r600_dma_semaphore_ring_emit,
1039 			.cs_parse = &r600_dma_cs_parse,
1040 			.ring_test = &r600_dma_ring_test,
1041 			.ib_test = &r600_dma_ib_test,
1042 			.is_lockup = &r600_dma_is_lockup,
1043 		}
1044 	},
1045 	.irq = {
1046 		.set = &r600_irq_set,
1047 		.process = &r600_irq_process,
1048 	},
1049 	.display = {
1050 		.bandwidth_update = &rs690_bandwidth_update,
1051 		.get_vblank_counter = &rs600_get_vblank_counter,
1052 		.wait_for_vblank = &avivo_wait_for_vblank,
1053 		.set_backlight_level = &atombios_set_backlight_level,
1054 		.get_backlight_level = &atombios_get_backlight_level,
1055 	},
1056 	.copy = {
1057 		.blit = &r600_copy_blit,
1058 		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1059 		.dma = &r600_copy_dma,
1060 		.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1061 		.copy = &r600_copy_dma,
1062 		.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1063 	},
1064 	.surface = {
1065 		.set_reg = r600_set_surface_reg,
1066 		.clear_reg = r600_clear_surface_reg,
1067 	},
1068 	.hpd = {
1069 		.init = &r600_hpd_init,
1070 		.fini = &r600_hpd_fini,
1071 		.sense = &r600_hpd_sense,
1072 		.set_polarity = &r600_hpd_set_polarity,
1073 	},
1074 	.pm = {
1075 		.misc = &r600_pm_misc,
1076 		.prepare = &rs600_pm_prepare,
1077 		.finish = &rs600_pm_finish,
1078 		.init_profile = &rs780_pm_init_profile,
1079 		.get_dynpm_state = &r600_pm_get_dynpm_state,
1080 		.get_engine_clock = &radeon_atom_get_engine_clock,
1081 		.set_engine_clock = &radeon_atom_set_engine_clock,
1082 		.get_memory_clock = NULL,
1083 		.set_memory_clock = NULL,
1084 		.get_pcie_lanes = NULL,
1085 		.set_pcie_lanes = NULL,
1086 		.set_clock_gating = NULL,
1087 	},
1088 	.pflip = {
1089 		.pre_page_flip = &rs600_pre_page_flip,
1090 		.page_flip = &rs600_page_flip,
1091 		.post_page_flip = &rs600_post_page_flip,
1092 	},
1093 };
1094 
1095 static struct radeon_asic rv770_asic = {
1096 	.init = &rv770_init,
1097 	.fini = &rv770_fini,
1098 	.suspend = &rv770_suspend,
1099 	.resume = &rv770_resume,
1100 	.asic_reset = &r600_asic_reset,
1101 	.vga_set_state = &r600_vga_set_state,
1102 	.ioctl_wait_idle = r600_ioctl_wait_idle,
1103 	.gui_idle = &r600_gui_idle,
1104 	.mc_wait_for_idle = &r600_mc_wait_for_idle,
1105 	.gart = {
1106 		.tlb_flush = &r600_pcie_gart_tlb_flush,
1107 		.set_page = &rs600_gart_set_page,
1108 	},
1109 	.ring = {
1110 		[RADEON_RING_TYPE_GFX_INDEX] = {
1111 			.ib_execute = &r600_ring_ib_execute,
1112 			.emit_fence = &r600_fence_ring_emit,
1113 			.emit_semaphore = &r600_semaphore_ring_emit,
1114 			.cs_parse = &r600_cs_parse,
1115 			.ring_test = &r600_ring_test,
1116 			.ib_test = &r600_ib_test,
1117 			.is_lockup = &r600_gpu_is_lockup,
1118 		},
1119 		[R600_RING_TYPE_DMA_INDEX] = {
1120 			.ib_execute = &r600_dma_ring_ib_execute,
1121 			.emit_fence = &r600_dma_fence_ring_emit,
1122 			.emit_semaphore = &r600_dma_semaphore_ring_emit,
1123 			.cs_parse = &r600_dma_cs_parse,
1124 			.ring_test = &r600_dma_ring_test,
1125 			.ib_test = &r600_dma_ib_test,
1126 			.is_lockup = &r600_dma_is_lockup,
1127 		}
1128 	},
1129 	.irq = {
1130 		.set = &r600_irq_set,
1131 		.process = &r600_irq_process,
1132 	},
1133 	.display = {
1134 		.bandwidth_update = &rv515_bandwidth_update,
1135 		.get_vblank_counter = &rs600_get_vblank_counter,
1136 		.wait_for_vblank = &avivo_wait_for_vblank,
1137 		.set_backlight_level = &atombios_set_backlight_level,
1138 		.get_backlight_level = &atombios_get_backlight_level,
1139 	},
1140 	.copy = {
1141 		.blit = &r600_copy_blit,
1142 		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1143 		.dma = &r600_copy_dma,
1144 		.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1145 		.copy = &r600_copy_dma,
1146 		.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1147 	},
1148 	.surface = {
1149 		.set_reg = r600_set_surface_reg,
1150 		.clear_reg = r600_clear_surface_reg,
1151 	},
1152 	.hpd = {
1153 		.init = &r600_hpd_init,
1154 		.fini = &r600_hpd_fini,
1155 		.sense = &r600_hpd_sense,
1156 		.set_polarity = &r600_hpd_set_polarity,
1157 	},
1158 	.pm = {
1159 		.misc = &rv770_pm_misc,
1160 		.prepare = &rs600_pm_prepare,
1161 		.finish = &rs600_pm_finish,
1162 		.init_profile = &r600_pm_init_profile,
1163 		.get_dynpm_state = &r600_pm_get_dynpm_state,
1164 		.get_engine_clock = &radeon_atom_get_engine_clock,
1165 		.set_engine_clock = &radeon_atom_set_engine_clock,
1166 		.get_memory_clock = &radeon_atom_get_memory_clock,
1167 		.set_memory_clock = &radeon_atom_set_memory_clock,
1168 		.get_pcie_lanes = &r600_get_pcie_lanes,
1169 		.set_pcie_lanes = &r600_set_pcie_lanes,
1170 		.set_clock_gating = &radeon_atom_set_clock_gating,
1171 	},
1172 	.pflip = {
1173 		.pre_page_flip = &rs600_pre_page_flip,
1174 		.page_flip = &rv770_page_flip,
1175 		.post_page_flip = &rs600_post_page_flip,
1176 	},
1177 };
1178 
1179 static struct radeon_asic evergreen_asic = {
1180 	.init = &evergreen_init,
1181 	.fini = &evergreen_fini,
1182 	.suspend = &evergreen_suspend,
1183 	.resume = &evergreen_resume,
1184 	.asic_reset = &evergreen_asic_reset,
1185 	.vga_set_state = &r600_vga_set_state,
1186 	.ioctl_wait_idle = r600_ioctl_wait_idle,
1187 	.gui_idle = &r600_gui_idle,
1188 	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1189 	.gart = {
1190 		.tlb_flush = &evergreen_pcie_gart_tlb_flush,
1191 		.set_page = &rs600_gart_set_page,
1192 	},
1193 	.ring = {
1194 		[RADEON_RING_TYPE_GFX_INDEX] = {
1195 			.ib_execute = &evergreen_ring_ib_execute,
1196 			.emit_fence = &r600_fence_ring_emit,
1197 			.emit_semaphore = &r600_semaphore_ring_emit,
1198 			.cs_parse = &evergreen_cs_parse,
1199 			.ring_test = &r600_ring_test,
1200 			.ib_test = &r600_ib_test,
1201 			.is_lockup = &evergreen_gpu_is_lockup,
1202 		},
1203 		[R600_RING_TYPE_DMA_INDEX] = {
1204 			.ib_execute = &evergreen_dma_ring_ib_execute,
1205 			.emit_fence = &evergreen_dma_fence_ring_emit,
1206 			.emit_semaphore = &r600_dma_semaphore_ring_emit,
1207 			.cs_parse = &evergreen_dma_cs_parse,
1208 			.ring_test = &r600_dma_ring_test,
1209 			.ib_test = &r600_dma_ib_test,
1210 			.is_lockup = &r600_dma_is_lockup,
1211 		}
1212 	},
1213 	.irq = {
1214 		.set = &evergreen_irq_set,
1215 		.process = &evergreen_irq_process,
1216 	},
1217 	.display = {
1218 		.bandwidth_update = &evergreen_bandwidth_update,
1219 		.get_vblank_counter = &evergreen_get_vblank_counter,
1220 		.wait_for_vblank = &dce4_wait_for_vblank,
1221 		.set_backlight_level = &atombios_set_backlight_level,
1222 		.get_backlight_level = &atombios_get_backlight_level,
1223 	},
1224 	.copy = {
1225 		.blit = &r600_copy_blit,
1226 		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1227 		.dma = &evergreen_copy_dma,
1228 		.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1229 		.copy = &evergreen_copy_dma,
1230 		.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1231 	},
1232 	.surface = {
1233 		.set_reg = r600_set_surface_reg,
1234 		.clear_reg = r600_clear_surface_reg,
1235 	},
1236 	.hpd = {
1237 		.init = &evergreen_hpd_init,
1238 		.fini = &evergreen_hpd_fini,
1239 		.sense = &evergreen_hpd_sense,
1240 		.set_polarity = &evergreen_hpd_set_polarity,
1241 	},
1242 	.pm = {
1243 		.misc = &evergreen_pm_misc,
1244 		.prepare = &evergreen_pm_prepare,
1245 		.finish = &evergreen_pm_finish,
1246 		.init_profile = &r600_pm_init_profile,
1247 		.get_dynpm_state = &r600_pm_get_dynpm_state,
1248 		.get_engine_clock = &radeon_atom_get_engine_clock,
1249 		.set_engine_clock = &radeon_atom_set_engine_clock,
1250 		.get_memory_clock = &radeon_atom_get_memory_clock,
1251 		.set_memory_clock = &radeon_atom_set_memory_clock,
1252 		.get_pcie_lanes = &r600_get_pcie_lanes,
1253 		.set_pcie_lanes = &r600_set_pcie_lanes,
1254 		.set_clock_gating = NULL,
1255 	},
1256 	.pflip = {
1257 		.pre_page_flip = &evergreen_pre_page_flip,
1258 		.page_flip = &evergreen_page_flip,
1259 		.post_page_flip = &evergreen_post_page_flip,
1260 	},
1261 };
1262 
1263 static struct radeon_asic sumo_asic = {
1264 	.init = &evergreen_init,
1265 	.fini = &evergreen_fini,
1266 	.suspend = &evergreen_suspend,
1267 	.resume = &evergreen_resume,
1268 	.asic_reset = &evergreen_asic_reset,
1269 	.vga_set_state = &r600_vga_set_state,
1270 	.ioctl_wait_idle = r600_ioctl_wait_idle,
1271 	.gui_idle = &r600_gui_idle,
1272 	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1273 	.gart = {
1274 		.tlb_flush = &evergreen_pcie_gart_tlb_flush,
1275 		.set_page = &rs600_gart_set_page,
1276 	},
1277 	.ring = {
1278 		[RADEON_RING_TYPE_GFX_INDEX] = {
1279 			.ib_execute = &evergreen_ring_ib_execute,
1280 			.emit_fence = &r600_fence_ring_emit,
1281 			.emit_semaphore = &r600_semaphore_ring_emit,
1282 			.cs_parse = &evergreen_cs_parse,
1283 			.ring_test = &r600_ring_test,
1284 			.ib_test = &r600_ib_test,
1285 			.is_lockup = &evergreen_gpu_is_lockup,
1286 		},
1287 		[R600_RING_TYPE_DMA_INDEX] = {
1288 			.ib_execute = &evergreen_dma_ring_ib_execute,
1289 			.emit_fence = &evergreen_dma_fence_ring_emit,
1290 			.emit_semaphore = &r600_dma_semaphore_ring_emit,
1291 			.cs_parse = &evergreen_dma_cs_parse,
1292 			.ring_test = &r600_dma_ring_test,
1293 			.ib_test = &r600_dma_ib_test,
1294 			.is_lockup = &r600_dma_is_lockup,
1295 		}
1296 	},
1297 	.irq = {
1298 		.set = &evergreen_irq_set,
1299 		.process = &evergreen_irq_process,
1300 	},
1301 	.display = {
1302 		.bandwidth_update = &evergreen_bandwidth_update,
1303 		.get_vblank_counter = &evergreen_get_vblank_counter,
1304 		.wait_for_vblank = &dce4_wait_for_vblank,
1305 		.set_backlight_level = &atombios_set_backlight_level,
1306 		.get_backlight_level = &atombios_get_backlight_level,
1307 	},
1308 	.copy = {
1309 		.blit = &r600_copy_blit,
1310 		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1311 		.dma = &evergreen_copy_dma,
1312 		.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1313 		.copy = &evergreen_copy_dma,
1314 		.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1315 	},
1316 	.surface = {
1317 		.set_reg = r600_set_surface_reg,
1318 		.clear_reg = r600_clear_surface_reg,
1319 	},
1320 	.hpd = {
1321 		.init = &evergreen_hpd_init,
1322 		.fini = &evergreen_hpd_fini,
1323 		.sense = &evergreen_hpd_sense,
1324 		.set_polarity = &evergreen_hpd_set_polarity,
1325 	},
1326 	.pm = {
1327 		.misc = &evergreen_pm_misc,
1328 		.prepare = &evergreen_pm_prepare,
1329 		.finish = &evergreen_pm_finish,
1330 		.init_profile = &sumo_pm_init_profile,
1331 		.get_dynpm_state = &r600_pm_get_dynpm_state,
1332 		.get_engine_clock = &radeon_atom_get_engine_clock,
1333 		.set_engine_clock = &radeon_atom_set_engine_clock,
1334 		.get_memory_clock = NULL,
1335 		.set_memory_clock = NULL,
1336 		.get_pcie_lanes = NULL,
1337 		.set_pcie_lanes = NULL,
1338 		.set_clock_gating = NULL,
1339 	},
1340 	.pflip = {
1341 		.pre_page_flip = &evergreen_pre_page_flip,
1342 		.page_flip = &evergreen_page_flip,
1343 		.post_page_flip = &evergreen_post_page_flip,
1344 	},
1345 };
1346 
1347 static struct radeon_asic btc_asic = {
1348 	.init = &evergreen_init,
1349 	.fini = &evergreen_fini,
1350 	.suspend = &evergreen_suspend,
1351 	.resume = &evergreen_resume,
1352 	.asic_reset = &evergreen_asic_reset,
1353 	.vga_set_state = &r600_vga_set_state,
1354 	.ioctl_wait_idle = r600_ioctl_wait_idle,
1355 	.gui_idle = &r600_gui_idle,
1356 	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1357 	.gart = {
1358 		.tlb_flush = &evergreen_pcie_gart_tlb_flush,
1359 		.set_page = &rs600_gart_set_page,
1360 	},
1361 	.ring = {
1362 		[RADEON_RING_TYPE_GFX_INDEX] = {
1363 			.ib_execute = &evergreen_ring_ib_execute,
1364 			.emit_fence = &r600_fence_ring_emit,
1365 			.emit_semaphore = &r600_semaphore_ring_emit,
1366 			.cs_parse = &evergreen_cs_parse,
1367 			.ring_test = &r600_ring_test,
1368 			.ib_test = &r600_ib_test,
1369 			.is_lockup = &evergreen_gpu_is_lockup,
1370 		},
1371 		[R600_RING_TYPE_DMA_INDEX] = {
1372 			.ib_execute = &evergreen_dma_ring_ib_execute,
1373 			.emit_fence = &evergreen_dma_fence_ring_emit,
1374 			.emit_semaphore = &r600_dma_semaphore_ring_emit,
1375 			.cs_parse = &evergreen_dma_cs_parse,
1376 			.ring_test = &r600_dma_ring_test,
1377 			.ib_test = &r600_dma_ib_test,
1378 			.is_lockup = &r600_dma_is_lockup,
1379 		}
1380 	},
1381 	.irq = {
1382 		.set = &evergreen_irq_set,
1383 		.process = &evergreen_irq_process,
1384 	},
1385 	.display = {
1386 		.bandwidth_update = &evergreen_bandwidth_update,
1387 		.get_vblank_counter = &evergreen_get_vblank_counter,
1388 		.wait_for_vblank = &dce4_wait_for_vblank,
1389 		.set_backlight_level = &atombios_set_backlight_level,
1390 		.get_backlight_level = &atombios_get_backlight_level,
1391 	},
1392 	.copy = {
1393 		.blit = &r600_copy_blit,
1394 		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1395 		.dma = &evergreen_copy_dma,
1396 		.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1397 		.copy = &evergreen_copy_dma,
1398 		.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1399 	},
1400 	.surface = {
1401 		.set_reg = r600_set_surface_reg,
1402 		.clear_reg = r600_clear_surface_reg,
1403 	},
1404 	.hpd = {
1405 		.init = &evergreen_hpd_init,
1406 		.fini = &evergreen_hpd_fini,
1407 		.sense = &evergreen_hpd_sense,
1408 		.set_polarity = &evergreen_hpd_set_polarity,
1409 	},
1410 	.pm = {
1411 		.misc = &evergreen_pm_misc,
1412 		.prepare = &evergreen_pm_prepare,
1413 		.finish = &evergreen_pm_finish,
1414 		.init_profile = &btc_pm_init_profile,
1415 		.get_dynpm_state = &r600_pm_get_dynpm_state,
1416 		.get_engine_clock = &radeon_atom_get_engine_clock,
1417 		.set_engine_clock = &radeon_atom_set_engine_clock,
1418 		.get_memory_clock = &radeon_atom_get_memory_clock,
1419 		.set_memory_clock = &radeon_atom_set_memory_clock,
1420 		.get_pcie_lanes = NULL,
1421 		.set_pcie_lanes = NULL,
1422 		.set_clock_gating = NULL,
1423 	},
1424 	.pflip = {
1425 		.pre_page_flip = &evergreen_pre_page_flip,
1426 		.page_flip = &evergreen_page_flip,
1427 		.post_page_flip = &evergreen_post_page_flip,
1428 	},
1429 };
1430 
1431 static struct radeon_asic cayman_asic = {
1432 	.init = &cayman_init,
1433 	.fini = &cayman_fini,
1434 	.suspend = &cayman_suspend,
1435 	.resume = &cayman_resume,
1436 	.asic_reset = &cayman_asic_reset,
1437 	.vga_set_state = &r600_vga_set_state,
1438 	.ioctl_wait_idle = r600_ioctl_wait_idle,
1439 	.gui_idle = &r600_gui_idle,
1440 	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1441 	.gart = {
1442 		.tlb_flush = &cayman_pcie_gart_tlb_flush,
1443 		.set_page = &rs600_gart_set_page,
1444 	},
1445 	.vm = {
1446 		.init = &cayman_vm_init,
1447 		.fini = &cayman_vm_fini,
1448 		.pt_ring_index = R600_RING_TYPE_DMA_INDEX,
1449 		.set_page = &cayman_vm_set_page,
1450 	},
1451 	.ring = {
1452 		[RADEON_RING_TYPE_GFX_INDEX] = {
1453 			.ib_execute = &cayman_ring_ib_execute,
1454 			.ib_parse = &evergreen_ib_parse,
1455 			.emit_fence = &cayman_fence_ring_emit,
1456 			.emit_semaphore = &r600_semaphore_ring_emit,
1457 			.cs_parse = &evergreen_cs_parse,
1458 			.ring_test = &r600_ring_test,
1459 			.ib_test = &r600_ib_test,
1460 			.is_lockup = &evergreen_gpu_is_lockup,
1461 			.vm_flush = &cayman_vm_flush,
1462 		},
1463 		[CAYMAN_RING_TYPE_CP1_INDEX] = {
1464 			.ib_execute = &cayman_ring_ib_execute,
1465 			.ib_parse = &evergreen_ib_parse,
1466 			.emit_fence = &cayman_fence_ring_emit,
1467 			.emit_semaphore = &r600_semaphore_ring_emit,
1468 			.cs_parse = &evergreen_cs_parse,
1469 			.ring_test = &r600_ring_test,
1470 			.ib_test = &r600_ib_test,
1471 			.is_lockup = &evergreen_gpu_is_lockup,
1472 			.vm_flush = &cayman_vm_flush,
1473 		},
1474 		[CAYMAN_RING_TYPE_CP2_INDEX] = {
1475 			.ib_execute = &cayman_ring_ib_execute,
1476 			.ib_parse = &evergreen_ib_parse,
1477 			.emit_fence = &cayman_fence_ring_emit,
1478 			.emit_semaphore = &r600_semaphore_ring_emit,
1479 			.cs_parse = &evergreen_cs_parse,
1480 			.ring_test = &r600_ring_test,
1481 			.ib_test = &r600_ib_test,
1482 			.is_lockup = &evergreen_gpu_is_lockup,
1483 			.vm_flush = &cayman_vm_flush,
1484 		},
1485 		[R600_RING_TYPE_DMA_INDEX] = {
1486 			.ib_execute = &cayman_dma_ring_ib_execute,
1487 			.ib_parse = &evergreen_dma_ib_parse,
1488 			.emit_fence = &evergreen_dma_fence_ring_emit,
1489 			.emit_semaphore = &r600_dma_semaphore_ring_emit,
1490 			.cs_parse = &evergreen_dma_cs_parse,
1491 			.ring_test = &r600_dma_ring_test,
1492 			.ib_test = &r600_dma_ib_test,
1493 			.is_lockup = &cayman_dma_is_lockup,
1494 			.vm_flush = &cayman_dma_vm_flush,
1495 		},
1496 		[CAYMAN_RING_TYPE_DMA1_INDEX] = {
1497 			.ib_execute = &cayman_dma_ring_ib_execute,
1498 			.ib_parse = &evergreen_dma_ib_parse,
1499 			.emit_fence = &evergreen_dma_fence_ring_emit,
1500 			.emit_semaphore = &r600_dma_semaphore_ring_emit,
1501 			.cs_parse = &evergreen_dma_cs_parse,
1502 			.ring_test = &r600_dma_ring_test,
1503 			.ib_test = &r600_dma_ib_test,
1504 			.is_lockup = &cayman_dma_is_lockup,
1505 			.vm_flush = &cayman_dma_vm_flush,
1506 		}
1507 	},
1508 	.irq = {
1509 		.set = &evergreen_irq_set,
1510 		.process = &evergreen_irq_process,
1511 	},
1512 	.display = {
1513 		.bandwidth_update = &evergreen_bandwidth_update,
1514 		.get_vblank_counter = &evergreen_get_vblank_counter,
1515 		.wait_for_vblank = &dce4_wait_for_vblank,
1516 		.set_backlight_level = &atombios_set_backlight_level,
1517 		.get_backlight_level = &atombios_get_backlight_level,
1518 	},
1519 	.copy = {
1520 		.blit = &r600_copy_blit,
1521 		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1522 		.dma = &evergreen_copy_dma,
1523 		.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1524 		.copy = &evergreen_copy_dma,
1525 		.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1526 	},
1527 	.surface = {
1528 		.set_reg = r600_set_surface_reg,
1529 		.clear_reg = r600_clear_surface_reg,
1530 	},
1531 	.hpd = {
1532 		.init = &evergreen_hpd_init,
1533 		.fini = &evergreen_hpd_fini,
1534 		.sense = &evergreen_hpd_sense,
1535 		.set_polarity = &evergreen_hpd_set_polarity,
1536 	},
1537 	.pm = {
1538 		.misc = &evergreen_pm_misc,
1539 		.prepare = &evergreen_pm_prepare,
1540 		.finish = &evergreen_pm_finish,
1541 		.init_profile = &btc_pm_init_profile,
1542 		.get_dynpm_state = &r600_pm_get_dynpm_state,
1543 		.get_engine_clock = &radeon_atom_get_engine_clock,
1544 		.set_engine_clock = &radeon_atom_set_engine_clock,
1545 		.get_memory_clock = &radeon_atom_get_memory_clock,
1546 		.set_memory_clock = &radeon_atom_set_memory_clock,
1547 		.get_pcie_lanes = NULL,
1548 		.set_pcie_lanes = NULL,
1549 		.set_clock_gating = NULL,
1550 	},
1551 	.pflip = {
1552 		.pre_page_flip = &evergreen_pre_page_flip,
1553 		.page_flip = &evergreen_page_flip,
1554 		.post_page_flip = &evergreen_post_page_flip,
1555 	},
1556 };
1557 
1558 static struct radeon_asic trinity_asic = {
1559 	.init = &cayman_init,
1560 	.fini = &cayman_fini,
1561 	.suspend = &cayman_suspend,
1562 	.resume = &cayman_resume,
1563 	.asic_reset = &cayman_asic_reset,
1564 	.vga_set_state = &r600_vga_set_state,
1565 	.ioctl_wait_idle = r600_ioctl_wait_idle,
1566 	.gui_idle = &r600_gui_idle,
1567 	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1568 	.gart = {
1569 		.tlb_flush = &cayman_pcie_gart_tlb_flush,
1570 		.set_page = &rs600_gart_set_page,
1571 	},
1572 	.vm = {
1573 		.init = &cayman_vm_init,
1574 		.fini = &cayman_vm_fini,
1575 		.pt_ring_index = R600_RING_TYPE_DMA_INDEX,
1576 		.set_page = &cayman_vm_set_page,
1577 	},
1578 	.ring = {
1579 		[RADEON_RING_TYPE_GFX_INDEX] = {
1580 			.ib_execute = &cayman_ring_ib_execute,
1581 			.ib_parse = &evergreen_ib_parse,
1582 			.emit_fence = &cayman_fence_ring_emit,
1583 			.emit_semaphore = &r600_semaphore_ring_emit,
1584 			.cs_parse = &evergreen_cs_parse,
1585 			.ring_test = &r600_ring_test,
1586 			.ib_test = &r600_ib_test,
1587 			.is_lockup = &evergreen_gpu_is_lockup,
1588 			.vm_flush = &cayman_vm_flush,
1589 		},
1590 		[CAYMAN_RING_TYPE_CP1_INDEX] = {
1591 			.ib_execute = &cayman_ring_ib_execute,
1592 			.ib_parse = &evergreen_ib_parse,
1593 			.emit_fence = &cayman_fence_ring_emit,
1594 			.emit_semaphore = &r600_semaphore_ring_emit,
1595 			.cs_parse = &evergreen_cs_parse,
1596 			.ring_test = &r600_ring_test,
1597 			.ib_test = &r600_ib_test,
1598 			.is_lockup = &evergreen_gpu_is_lockup,
1599 			.vm_flush = &cayman_vm_flush,
1600 		},
1601 		[CAYMAN_RING_TYPE_CP2_INDEX] = {
1602 			.ib_execute = &cayman_ring_ib_execute,
1603 			.ib_parse = &evergreen_ib_parse,
1604 			.emit_fence = &cayman_fence_ring_emit,
1605 			.emit_semaphore = &r600_semaphore_ring_emit,
1606 			.cs_parse = &evergreen_cs_parse,
1607 			.ring_test = &r600_ring_test,
1608 			.ib_test = &r600_ib_test,
1609 			.is_lockup = &evergreen_gpu_is_lockup,
1610 			.vm_flush = &cayman_vm_flush,
1611 		},
1612 		[R600_RING_TYPE_DMA_INDEX] = {
1613 			.ib_execute = &cayman_dma_ring_ib_execute,
1614 			.ib_parse = &evergreen_dma_ib_parse,
1615 			.emit_fence = &evergreen_dma_fence_ring_emit,
1616 			.emit_semaphore = &r600_dma_semaphore_ring_emit,
1617 			.cs_parse = &evergreen_dma_cs_parse,
1618 			.ring_test = &r600_dma_ring_test,
1619 			.ib_test = &r600_dma_ib_test,
1620 			.is_lockup = &cayman_dma_is_lockup,
1621 			.vm_flush = &cayman_dma_vm_flush,
1622 		},
1623 		[CAYMAN_RING_TYPE_DMA1_INDEX] = {
1624 			.ib_execute = &cayman_dma_ring_ib_execute,
1625 			.ib_parse = &evergreen_dma_ib_parse,
1626 			.emit_fence = &evergreen_dma_fence_ring_emit,
1627 			.emit_semaphore = &r600_dma_semaphore_ring_emit,
1628 			.cs_parse = &evergreen_dma_cs_parse,
1629 			.ring_test = &r600_dma_ring_test,
1630 			.ib_test = &r600_dma_ib_test,
1631 			.is_lockup = &cayman_dma_is_lockup,
1632 			.vm_flush = &cayman_dma_vm_flush,
1633 		}
1634 	},
1635 	.irq = {
1636 		.set = &evergreen_irq_set,
1637 		.process = &evergreen_irq_process,
1638 	},
1639 	.display = {
1640 		.bandwidth_update = &dce6_bandwidth_update,
1641 		.get_vblank_counter = &evergreen_get_vblank_counter,
1642 		.wait_for_vblank = &dce4_wait_for_vblank,
1643 		.set_backlight_level = &atombios_set_backlight_level,
1644 		.get_backlight_level = &atombios_get_backlight_level,
1645 	},
1646 	.copy = {
1647 		.blit = &r600_copy_blit,
1648 		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1649 		.dma = &evergreen_copy_dma,
1650 		.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1651 		.copy = &evergreen_copy_dma,
1652 		.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1653 	},
1654 	.surface = {
1655 		.set_reg = r600_set_surface_reg,
1656 		.clear_reg = r600_clear_surface_reg,
1657 	},
1658 	.hpd = {
1659 		.init = &evergreen_hpd_init,
1660 		.fini = &evergreen_hpd_fini,
1661 		.sense = &evergreen_hpd_sense,
1662 		.set_polarity = &evergreen_hpd_set_polarity,
1663 	},
1664 	.pm = {
1665 		.misc = &evergreen_pm_misc,
1666 		.prepare = &evergreen_pm_prepare,
1667 		.finish = &evergreen_pm_finish,
1668 		.init_profile = &sumo_pm_init_profile,
1669 		.get_dynpm_state = &r600_pm_get_dynpm_state,
1670 		.get_engine_clock = &radeon_atom_get_engine_clock,
1671 		.set_engine_clock = &radeon_atom_set_engine_clock,
1672 		.get_memory_clock = NULL,
1673 		.set_memory_clock = NULL,
1674 		.get_pcie_lanes = NULL,
1675 		.set_pcie_lanes = NULL,
1676 		.set_clock_gating = NULL,
1677 	},
1678 	.pflip = {
1679 		.pre_page_flip = &evergreen_pre_page_flip,
1680 		.page_flip = &evergreen_page_flip,
1681 		.post_page_flip = &evergreen_post_page_flip,
1682 	},
1683 };
1684 
1685 static struct radeon_asic si_asic = {
1686 	.init = &si_init,
1687 	.fini = &si_fini,
1688 	.suspend = &si_suspend,
1689 	.resume = &si_resume,
1690 	.asic_reset = &si_asic_reset,
1691 	.vga_set_state = &r600_vga_set_state,
1692 	.ioctl_wait_idle = r600_ioctl_wait_idle,
1693 	.gui_idle = &r600_gui_idle,
1694 	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1695 	.gart = {
1696 		.tlb_flush = &si_pcie_gart_tlb_flush,
1697 		.set_page = &rs600_gart_set_page,
1698 	},
1699 	.vm = {
1700 		.init = &si_vm_init,
1701 		.fini = &si_vm_fini,
1702 		.pt_ring_index = R600_RING_TYPE_DMA_INDEX,
1703 		.set_page = &si_vm_set_page,
1704 	},
1705 	.ring = {
1706 		[RADEON_RING_TYPE_GFX_INDEX] = {
1707 			.ib_execute = &si_ring_ib_execute,
1708 			.ib_parse = &si_ib_parse,
1709 			.emit_fence = &si_fence_ring_emit,
1710 			.emit_semaphore = &r600_semaphore_ring_emit,
1711 			.cs_parse = NULL,
1712 			.ring_test = &r600_ring_test,
1713 			.ib_test = &r600_ib_test,
1714 			.is_lockup = &si_gpu_is_lockup,
1715 			.vm_flush = &si_vm_flush,
1716 		},
1717 		[CAYMAN_RING_TYPE_CP1_INDEX] = {
1718 			.ib_execute = &si_ring_ib_execute,
1719 			.ib_parse = &si_ib_parse,
1720 			.emit_fence = &si_fence_ring_emit,
1721 			.emit_semaphore = &r600_semaphore_ring_emit,
1722 			.cs_parse = NULL,
1723 			.ring_test = &r600_ring_test,
1724 			.ib_test = &r600_ib_test,
1725 			.is_lockup = &si_gpu_is_lockup,
1726 			.vm_flush = &si_vm_flush,
1727 		},
1728 		[CAYMAN_RING_TYPE_CP2_INDEX] = {
1729 			.ib_execute = &si_ring_ib_execute,
1730 			.ib_parse = &si_ib_parse,
1731 			.emit_fence = &si_fence_ring_emit,
1732 			.emit_semaphore = &r600_semaphore_ring_emit,
1733 			.cs_parse = NULL,
1734 			.ring_test = &r600_ring_test,
1735 			.ib_test = &r600_ib_test,
1736 			.is_lockup = &si_gpu_is_lockup,
1737 			.vm_flush = &si_vm_flush,
1738 		},
1739 		[R600_RING_TYPE_DMA_INDEX] = {
1740 			.ib_execute = &cayman_dma_ring_ib_execute,
1741 			.ib_parse = &evergreen_dma_ib_parse,
1742 			.emit_fence = &evergreen_dma_fence_ring_emit,
1743 			.emit_semaphore = &r600_dma_semaphore_ring_emit,
1744 			.cs_parse = NULL,
1745 			.ring_test = &r600_dma_ring_test,
1746 			.ib_test = &r600_dma_ib_test,
1747 			.is_lockup = &cayman_dma_is_lockup,
1748 			.vm_flush = &si_dma_vm_flush,
1749 		},
1750 		[CAYMAN_RING_TYPE_DMA1_INDEX] = {
1751 			.ib_execute = &cayman_dma_ring_ib_execute,
1752 			.ib_parse = &evergreen_dma_ib_parse,
1753 			.emit_fence = &evergreen_dma_fence_ring_emit,
1754 			.emit_semaphore = &r600_dma_semaphore_ring_emit,
1755 			.cs_parse = NULL,
1756 			.ring_test = &r600_dma_ring_test,
1757 			.ib_test = &r600_dma_ib_test,
1758 			.is_lockup = &cayman_dma_is_lockup,
1759 			.vm_flush = &si_dma_vm_flush,
1760 		}
1761 	},
1762 	.irq = {
1763 		.set = &si_irq_set,
1764 		.process = &si_irq_process,
1765 	},
1766 	.display = {
1767 		.bandwidth_update = &dce6_bandwidth_update,
1768 		.get_vblank_counter = &evergreen_get_vblank_counter,
1769 		.wait_for_vblank = &dce4_wait_for_vblank,
1770 		.set_backlight_level = &atombios_set_backlight_level,
1771 		.get_backlight_level = &atombios_get_backlight_level,
1772 	},
1773 	.copy = {
1774 		.blit = NULL,
1775 		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1776 		.dma = &si_copy_dma,
1777 		.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1778 		.copy = &si_copy_dma,
1779 		.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1780 	},
1781 	.surface = {
1782 		.set_reg = r600_set_surface_reg,
1783 		.clear_reg = r600_clear_surface_reg,
1784 	},
1785 	.hpd = {
1786 		.init = &evergreen_hpd_init,
1787 		.fini = &evergreen_hpd_fini,
1788 		.sense = &evergreen_hpd_sense,
1789 		.set_polarity = &evergreen_hpd_set_polarity,
1790 	},
1791 	.pm = {
1792 		.misc = &evergreen_pm_misc,
1793 		.prepare = &evergreen_pm_prepare,
1794 		.finish = &evergreen_pm_finish,
1795 		.init_profile = &sumo_pm_init_profile,
1796 		.get_dynpm_state = &r600_pm_get_dynpm_state,
1797 		.get_engine_clock = &radeon_atom_get_engine_clock,
1798 		.set_engine_clock = &radeon_atom_set_engine_clock,
1799 		.get_memory_clock = &radeon_atom_get_memory_clock,
1800 		.set_memory_clock = &radeon_atom_set_memory_clock,
1801 		.get_pcie_lanes = NULL,
1802 		.set_pcie_lanes = NULL,
1803 		.set_clock_gating = NULL,
1804 	},
1805 	.pflip = {
1806 		.pre_page_flip = &evergreen_pre_page_flip,
1807 		.page_flip = &evergreen_page_flip,
1808 		.post_page_flip = &evergreen_post_page_flip,
1809 	},
1810 };
1811 
1812 /**
1813  * radeon_asic_init - register asic specific callbacks
1814  *
1815  * @rdev: radeon device pointer
1816  *
1817  * Registers the appropriate asic specific callbacks for each
1818  * chip family.  Also sets other asics specific info like the number
1819  * of crtcs and the register aperture accessors (all asics).
1820  * Returns 0 for success.
1821  */
1822 int radeon_asic_init(struct radeon_device *rdev)
1823 {
1824 	radeon_register_accessor_init(rdev);
1825 
1826 	/* set the number of crtcs */
1827 	if (rdev->flags & RADEON_SINGLE_CRTC)
1828 		rdev->num_crtc = 1;
1829 	else
1830 		rdev->num_crtc = 2;
1831 
1832 	switch (rdev->family) {
1833 	case CHIP_R100:
1834 	case CHIP_RV100:
1835 	case CHIP_RS100:
1836 	case CHIP_RV200:
1837 	case CHIP_RS200:
1838 		rdev->asic = &r100_asic;
1839 		break;
1840 	case CHIP_R200:
1841 	case CHIP_RV250:
1842 	case CHIP_RS300:
1843 	case CHIP_RV280:
1844 		rdev->asic = &r200_asic;
1845 		break;
1846 	case CHIP_R300:
1847 	case CHIP_R350:
1848 	case CHIP_RV350:
1849 	case CHIP_RV380:
1850 		if (rdev->flags & RADEON_IS_PCIE)
1851 			rdev->asic = &r300_asic_pcie;
1852 		else
1853 			rdev->asic = &r300_asic;
1854 		break;
1855 	case CHIP_R420:
1856 	case CHIP_R423:
1857 	case CHIP_RV410:
1858 		rdev->asic = &r420_asic;
1859 		/* handle macs */
1860 		if (rdev->bios == NULL) {
1861 			rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock;
1862 			rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock;
1863 			rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock;
1864 			rdev->asic->pm.set_memory_clock = NULL;
1865 			rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level;
1866 		}
1867 		break;
1868 	case CHIP_RS400:
1869 	case CHIP_RS480:
1870 		rdev->asic = &rs400_asic;
1871 		break;
1872 	case CHIP_RS600:
1873 		rdev->asic = &rs600_asic;
1874 		break;
1875 	case CHIP_RS690:
1876 	case CHIP_RS740:
1877 		rdev->asic = &rs690_asic;
1878 		break;
1879 	case CHIP_RV515:
1880 		rdev->asic = &rv515_asic;
1881 		break;
1882 	case CHIP_R520:
1883 	case CHIP_RV530:
1884 	case CHIP_RV560:
1885 	case CHIP_RV570:
1886 	case CHIP_R580:
1887 		rdev->asic = &r520_asic;
1888 		break;
1889 	case CHIP_R600:
1890 	case CHIP_RV610:
1891 	case CHIP_RV630:
1892 	case CHIP_RV620:
1893 	case CHIP_RV635:
1894 	case CHIP_RV670:
1895 		rdev->asic = &r600_asic;
1896 		break;
1897 	case CHIP_RS780:
1898 	case CHIP_RS880:
1899 		rdev->asic = &rs780_asic;
1900 		break;
1901 	case CHIP_RV770:
1902 	case CHIP_RV730:
1903 	case CHIP_RV710:
1904 	case CHIP_RV740:
1905 		rdev->asic = &rv770_asic;
1906 		break;
1907 	case CHIP_CEDAR:
1908 	case CHIP_REDWOOD:
1909 	case CHIP_JUNIPER:
1910 	case CHIP_CYPRESS:
1911 	case CHIP_HEMLOCK:
1912 		/* set num crtcs */
1913 		if (rdev->family == CHIP_CEDAR)
1914 			rdev->num_crtc = 4;
1915 		else
1916 			rdev->num_crtc = 6;
1917 		rdev->asic = &evergreen_asic;
1918 		break;
1919 	case CHIP_PALM:
1920 	case CHIP_SUMO:
1921 	case CHIP_SUMO2:
1922 		rdev->asic = &sumo_asic;
1923 		break;
1924 	case CHIP_BARTS:
1925 	case CHIP_TURKS:
1926 	case CHIP_CAICOS:
1927 		/* set num crtcs */
1928 		if (rdev->family == CHIP_CAICOS)
1929 			rdev->num_crtc = 4;
1930 		else
1931 			rdev->num_crtc = 6;
1932 		rdev->asic = &btc_asic;
1933 		break;
1934 	case CHIP_CAYMAN:
1935 		rdev->asic = &cayman_asic;
1936 		/* set num crtcs */
1937 		rdev->num_crtc = 6;
1938 		break;
1939 	case CHIP_ARUBA:
1940 		rdev->asic = &trinity_asic;
1941 		/* set num crtcs */
1942 		rdev->num_crtc = 4;
1943 		break;
1944 	case CHIP_TAHITI:
1945 	case CHIP_PITCAIRN:
1946 	case CHIP_VERDE:
1947 		rdev->asic = &si_asic;
1948 		/* set num crtcs */
1949 		rdev->num_crtc = 6;
1950 		break;
1951 	default:
1952 		/* FIXME: not supported yet */
1953 		return -EINVAL;
1954 	}
1955 
1956 	if (rdev->flags & RADEON_IS_IGP) {
1957 		rdev->asic->pm.get_memory_clock = NULL;
1958 		rdev->asic->pm.set_memory_clock = NULL;
1959 	}
1960 
1961 	return 0;
1962 }
1963 
1964