1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include <linux/console.h> 30 #include <drm/drmP.h> 31 #include <drm/drm_crtc_helper.h> 32 #include <drm/radeon_drm.h> 33 #include <linux/vgaarb.h> 34 #include <linux/vga_switcheroo.h> 35 #include "radeon_reg.h" 36 #include "radeon.h" 37 #include "radeon_asic.h" 38 #include "atom.h" 39 40 /* 41 * Registers accessors functions. 42 */ 43 static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg) 44 { 45 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); 46 BUG_ON(1); 47 return 0; 48 } 49 50 static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 51 { 52 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", 53 reg, v); 54 BUG_ON(1); 55 } 56 57 static void radeon_register_accessor_init(struct radeon_device *rdev) 58 { 59 rdev->mc_rreg = &radeon_invalid_rreg; 60 rdev->mc_wreg = &radeon_invalid_wreg; 61 rdev->pll_rreg = &radeon_invalid_rreg; 62 rdev->pll_wreg = &radeon_invalid_wreg; 63 rdev->pciep_rreg = &radeon_invalid_rreg; 64 rdev->pciep_wreg = &radeon_invalid_wreg; 65 66 /* Don't change order as we are overridding accessor. */ 67 if (rdev->family < CHIP_RV515) { 68 rdev->pcie_reg_mask = 0xff; 69 } else { 70 rdev->pcie_reg_mask = 0x7ff; 71 } 72 /* FIXME: not sure here */ 73 if (rdev->family <= CHIP_R580) { 74 rdev->pll_rreg = &r100_pll_rreg; 75 rdev->pll_wreg = &r100_pll_wreg; 76 } 77 if (rdev->family >= CHIP_R420) { 78 rdev->mc_rreg = &r420_mc_rreg; 79 rdev->mc_wreg = &r420_mc_wreg; 80 } 81 if (rdev->family >= CHIP_RV515) { 82 rdev->mc_rreg = &rv515_mc_rreg; 83 rdev->mc_wreg = &rv515_mc_wreg; 84 } 85 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) { 86 rdev->mc_rreg = &rs400_mc_rreg; 87 rdev->mc_wreg = &rs400_mc_wreg; 88 } 89 if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { 90 rdev->mc_rreg = &rs690_mc_rreg; 91 rdev->mc_wreg = &rs690_mc_wreg; 92 } 93 if (rdev->family == CHIP_RS600) { 94 rdev->mc_rreg = &rs600_mc_rreg; 95 rdev->mc_wreg = &rs600_mc_wreg; 96 } 97 if (rdev->family >= CHIP_R600) { 98 rdev->pciep_rreg = &r600_pciep_rreg; 99 rdev->pciep_wreg = &r600_pciep_wreg; 100 } 101 } 102 103 104 /* helper to disable agp */ 105 void radeon_agp_disable(struct radeon_device *rdev) 106 { 107 rdev->flags &= ~RADEON_IS_AGP; 108 if (rdev->family >= CHIP_R600) { 109 DRM_INFO("Forcing AGP to PCIE mode\n"); 110 rdev->flags |= RADEON_IS_PCIE; 111 } else if (rdev->family >= CHIP_RV515 || 112 rdev->family == CHIP_RV380 || 113 rdev->family == CHIP_RV410 || 114 rdev->family == CHIP_R423) { 115 DRM_INFO("Forcing AGP to PCIE mode\n"); 116 rdev->flags |= RADEON_IS_PCIE; 117 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush; 118 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page; 119 } else { 120 DRM_INFO("Forcing AGP to PCI mode\n"); 121 rdev->flags |= RADEON_IS_PCI; 122 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush; 123 rdev->asic->gart_set_page = &r100_pci_gart_set_page; 124 } 125 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; 126 } 127 128 /* 129 * ASIC 130 */ 131 static struct radeon_asic r100_asic = { 132 .init = &r100_init, 133 .fini = &r100_fini, 134 .suspend = &r100_suspend, 135 .resume = &r100_resume, 136 .vga_set_state = &r100_vga_set_state, 137 .gpu_is_lockup = &r100_gpu_is_lockup, 138 .asic_reset = &r100_asic_reset, 139 .gart_tlb_flush = &r100_pci_gart_tlb_flush, 140 .gart_set_page = &r100_pci_gart_set_page, 141 .ring_start = &r100_ring_start, 142 .ring_test = &r100_ring_test, 143 .ring = { 144 [RADEON_RING_TYPE_GFX_INDEX] = { 145 .ib_execute = &r100_ring_ib_execute, 146 .emit_fence = &r100_fence_ring_emit, 147 .emit_semaphore = &r100_semaphore_ring_emit, 148 } 149 }, 150 .irq_set = &r100_irq_set, 151 .irq_process = &r100_irq_process, 152 .get_vblank_counter = &r100_get_vblank_counter, 153 .cs_parse = &r100_cs_parse, 154 .copy_blit = &r100_copy_blit, 155 .copy_dma = NULL, 156 .copy = &r100_copy_blit, 157 .get_engine_clock = &radeon_legacy_get_engine_clock, 158 .set_engine_clock = &radeon_legacy_set_engine_clock, 159 .get_memory_clock = &radeon_legacy_get_memory_clock, 160 .set_memory_clock = NULL, 161 .get_pcie_lanes = NULL, 162 .set_pcie_lanes = NULL, 163 .set_clock_gating = &radeon_legacy_set_clock_gating, 164 .set_surface_reg = r100_set_surface_reg, 165 .clear_surface_reg = r100_clear_surface_reg, 166 .bandwidth_update = &r100_bandwidth_update, 167 .hpd_init = &r100_hpd_init, 168 .hpd_fini = &r100_hpd_fini, 169 .hpd_sense = &r100_hpd_sense, 170 .hpd_set_polarity = &r100_hpd_set_polarity, 171 .ioctl_wait_idle = NULL, 172 .gui_idle = &r100_gui_idle, 173 .pm_misc = &r100_pm_misc, 174 .pm_prepare = &r100_pm_prepare, 175 .pm_finish = &r100_pm_finish, 176 .pm_init_profile = &r100_pm_init_profile, 177 .pm_get_dynpm_state = &r100_pm_get_dynpm_state, 178 .pre_page_flip = &r100_pre_page_flip, 179 .page_flip = &r100_page_flip, 180 .post_page_flip = &r100_post_page_flip, 181 }; 182 183 static struct radeon_asic r200_asic = { 184 .init = &r100_init, 185 .fini = &r100_fini, 186 .suspend = &r100_suspend, 187 .resume = &r100_resume, 188 .vga_set_state = &r100_vga_set_state, 189 .gpu_is_lockup = &r100_gpu_is_lockup, 190 .asic_reset = &r100_asic_reset, 191 .gart_tlb_flush = &r100_pci_gart_tlb_flush, 192 .gart_set_page = &r100_pci_gart_set_page, 193 .ring_start = &r100_ring_start, 194 .ring_test = &r100_ring_test, 195 .ring = { 196 [RADEON_RING_TYPE_GFX_INDEX] = { 197 .ib_execute = &r100_ring_ib_execute, 198 .emit_fence = &r100_fence_ring_emit, 199 .emit_semaphore = &r100_semaphore_ring_emit, 200 } 201 }, 202 .irq_set = &r100_irq_set, 203 .irq_process = &r100_irq_process, 204 .get_vblank_counter = &r100_get_vblank_counter, 205 .cs_parse = &r100_cs_parse, 206 .copy_blit = &r100_copy_blit, 207 .copy_dma = &r200_copy_dma, 208 .copy = &r100_copy_blit, 209 .get_engine_clock = &radeon_legacy_get_engine_clock, 210 .set_engine_clock = &radeon_legacy_set_engine_clock, 211 .get_memory_clock = &radeon_legacy_get_memory_clock, 212 .set_memory_clock = NULL, 213 .set_pcie_lanes = NULL, 214 .set_clock_gating = &radeon_legacy_set_clock_gating, 215 .set_surface_reg = r100_set_surface_reg, 216 .clear_surface_reg = r100_clear_surface_reg, 217 .bandwidth_update = &r100_bandwidth_update, 218 .hpd_init = &r100_hpd_init, 219 .hpd_fini = &r100_hpd_fini, 220 .hpd_sense = &r100_hpd_sense, 221 .hpd_set_polarity = &r100_hpd_set_polarity, 222 .ioctl_wait_idle = NULL, 223 .gui_idle = &r100_gui_idle, 224 .pm_misc = &r100_pm_misc, 225 .pm_prepare = &r100_pm_prepare, 226 .pm_finish = &r100_pm_finish, 227 .pm_init_profile = &r100_pm_init_profile, 228 .pm_get_dynpm_state = &r100_pm_get_dynpm_state, 229 .pre_page_flip = &r100_pre_page_flip, 230 .page_flip = &r100_page_flip, 231 .post_page_flip = &r100_post_page_flip, 232 }; 233 234 static struct radeon_asic r300_asic = { 235 .init = &r300_init, 236 .fini = &r300_fini, 237 .suspend = &r300_suspend, 238 .resume = &r300_resume, 239 .vga_set_state = &r100_vga_set_state, 240 .gpu_is_lockup = &r300_gpu_is_lockup, 241 .asic_reset = &r300_asic_reset, 242 .gart_tlb_flush = &r100_pci_gart_tlb_flush, 243 .gart_set_page = &r100_pci_gart_set_page, 244 .ring_start = &r300_ring_start, 245 .ring_test = &r100_ring_test, 246 .ring = { 247 [RADEON_RING_TYPE_GFX_INDEX] = { 248 .ib_execute = &r100_ring_ib_execute, 249 .emit_fence = &r300_fence_ring_emit, 250 .emit_semaphore = &r100_semaphore_ring_emit, 251 } 252 }, 253 .irq_set = &r100_irq_set, 254 .irq_process = &r100_irq_process, 255 .get_vblank_counter = &r100_get_vblank_counter, 256 .cs_parse = &r300_cs_parse, 257 .copy_blit = &r100_copy_blit, 258 .copy_dma = &r200_copy_dma, 259 .copy = &r100_copy_blit, 260 .get_engine_clock = &radeon_legacy_get_engine_clock, 261 .set_engine_clock = &radeon_legacy_set_engine_clock, 262 .get_memory_clock = &radeon_legacy_get_memory_clock, 263 .set_memory_clock = NULL, 264 .get_pcie_lanes = &rv370_get_pcie_lanes, 265 .set_pcie_lanes = &rv370_set_pcie_lanes, 266 .set_clock_gating = &radeon_legacy_set_clock_gating, 267 .set_surface_reg = r100_set_surface_reg, 268 .clear_surface_reg = r100_clear_surface_reg, 269 .bandwidth_update = &r100_bandwidth_update, 270 .hpd_init = &r100_hpd_init, 271 .hpd_fini = &r100_hpd_fini, 272 .hpd_sense = &r100_hpd_sense, 273 .hpd_set_polarity = &r100_hpd_set_polarity, 274 .ioctl_wait_idle = NULL, 275 .gui_idle = &r100_gui_idle, 276 .pm_misc = &r100_pm_misc, 277 .pm_prepare = &r100_pm_prepare, 278 .pm_finish = &r100_pm_finish, 279 .pm_init_profile = &r100_pm_init_profile, 280 .pm_get_dynpm_state = &r100_pm_get_dynpm_state, 281 .pre_page_flip = &r100_pre_page_flip, 282 .page_flip = &r100_page_flip, 283 .post_page_flip = &r100_post_page_flip, 284 }; 285 286 static struct radeon_asic r300_asic_pcie = { 287 .init = &r300_init, 288 .fini = &r300_fini, 289 .suspend = &r300_suspend, 290 .resume = &r300_resume, 291 .vga_set_state = &r100_vga_set_state, 292 .gpu_is_lockup = &r300_gpu_is_lockup, 293 .asic_reset = &r300_asic_reset, 294 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, 295 .gart_set_page = &rv370_pcie_gart_set_page, 296 .ring_start = &r300_ring_start, 297 .ring_test = &r100_ring_test, 298 .ring = { 299 [RADEON_RING_TYPE_GFX_INDEX] = { 300 .ib_execute = &r100_ring_ib_execute, 301 .emit_fence = &r300_fence_ring_emit, 302 .emit_semaphore = &r100_semaphore_ring_emit, 303 } 304 }, 305 .irq_set = &r100_irq_set, 306 .irq_process = &r100_irq_process, 307 .get_vblank_counter = &r100_get_vblank_counter, 308 .cs_parse = &r300_cs_parse, 309 .copy_blit = &r100_copy_blit, 310 .copy_dma = &r200_copy_dma, 311 .copy = &r100_copy_blit, 312 .get_engine_clock = &radeon_legacy_get_engine_clock, 313 .set_engine_clock = &radeon_legacy_set_engine_clock, 314 .get_memory_clock = &radeon_legacy_get_memory_clock, 315 .set_memory_clock = NULL, 316 .set_pcie_lanes = &rv370_set_pcie_lanes, 317 .set_clock_gating = &radeon_legacy_set_clock_gating, 318 .set_surface_reg = r100_set_surface_reg, 319 .clear_surface_reg = r100_clear_surface_reg, 320 .bandwidth_update = &r100_bandwidth_update, 321 .hpd_init = &r100_hpd_init, 322 .hpd_fini = &r100_hpd_fini, 323 .hpd_sense = &r100_hpd_sense, 324 .hpd_set_polarity = &r100_hpd_set_polarity, 325 .ioctl_wait_idle = NULL, 326 .gui_idle = &r100_gui_idle, 327 .pm_misc = &r100_pm_misc, 328 .pm_prepare = &r100_pm_prepare, 329 .pm_finish = &r100_pm_finish, 330 .pm_init_profile = &r100_pm_init_profile, 331 .pm_get_dynpm_state = &r100_pm_get_dynpm_state, 332 .pre_page_flip = &r100_pre_page_flip, 333 .page_flip = &r100_page_flip, 334 .post_page_flip = &r100_post_page_flip, 335 }; 336 337 static struct radeon_asic r420_asic = { 338 .init = &r420_init, 339 .fini = &r420_fini, 340 .suspend = &r420_suspend, 341 .resume = &r420_resume, 342 .vga_set_state = &r100_vga_set_state, 343 .gpu_is_lockup = &r300_gpu_is_lockup, 344 .asic_reset = &r300_asic_reset, 345 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, 346 .gart_set_page = &rv370_pcie_gart_set_page, 347 .ring_start = &r300_ring_start, 348 .ring_test = &r100_ring_test, 349 .ring = { 350 [RADEON_RING_TYPE_GFX_INDEX] = { 351 .ib_execute = &r100_ring_ib_execute, 352 .emit_fence = &r300_fence_ring_emit, 353 .emit_semaphore = &r100_semaphore_ring_emit, 354 } 355 }, 356 .irq_set = &r100_irq_set, 357 .irq_process = &r100_irq_process, 358 .get_vblank_counter = &r100_get_vblank_counter, 359 .cs_parse = &r300_cs_parse, 360 .copy_blit = &r100_copy_blit, 361 .copy_dma = &r200_copy_dma, 362 .copy = &r100_copy_blit, 363 .get_engine_clock = &radeon_atom_get_engine_clock, 364 .set_engine_clock = &radeon_atom_set_engine_clock, 365 .get_memory_clock = &radeon_atom_get_memory_clock, 366 .set_memory_clock = &radeon_atom_set_memory_clock, 367 .get_pcie_lanes = &rv370_get_pcie_lanes, 368 .set_pcie_lanes = &rv370_set_pcie_lanes, 369 .set_clock_gating = &radeon_atom_set_clock_gating, 370 .set_surface_reg = r100_set_surface_reg, 371 .clear_surface_reg = r100_clear_surface_reg, 372 .bandwidth_update = &r100_bandwidth_update, 373 .hpd_init = &r100_hpd_init, 374 .hpd_fini = &r100_hpd_fini, 375 .hpd_sense = &r100_hpd_sense, 376 .hpd_set_polarity = &r100_hpd_set_polarity, 377 .ioctl_wait_idle = NULL, 378 .gui_idle = &r100_gui_idle, 379 .pm_misc = &r100_pm_misc, 380 .pm_prepare = &r100_pm_prepare, 381 .pm_finish = &r100_pm_finish, 382 .pm_init_profile = &r420_pm_init_profile, 383 .pm_get_dynpm_state = &r100_pm_get_dynpm_state, 384 .pre_page_flip = &r100_pre_page_flip, 385 .page_flip = &r100_page_flip, 386 .post_page_flip = &r100_post_page_flip, 387 }; 388 389 static struct radeon_asic rs400_asic = { 390 .init = &rs400_init, 391 .fini = &rs400_fini, 392 .suspend = &rs400_suspend, 393 .resume = &rs400_resume, 394 .vga_set_state = &r100_vga_set_state, 395 .gpu_is_lockup = &r300_gpu_is_lockup, 396 .asic_reset = &r300_asic_reset, 397 .gart_tlb_flush = &rs400_gart_tlb_flush, 398 .gart_set_page = &rs400_gart_set_page, 399 .ring_start = &r300_ring_start, 400 .ring_test = &r100_ring_test, 401 .ring = { 402 [RADEON_RING_TYPE_GFX_INDEX] = { 403 .ib_execute = &r100_ring_ib_execute, 404 .emit_fence = &r300_fence_ring_emit, 405 .emit_semaphore = &r100_semaphore_ring_emit, 406 } 407 }, 408 .irq_set = &r100_irq_set, 409 .irq_process = &r100_irq_process, 410 .get_vblank_counter = &r100_get_vblank_counter, 411 .cs_parse = &r300_cs_parse, 412 .copy_blit = &r100_copy_blit, 413 .copy_dma = &r200_copy_dma, 414 .copy = &r100_copy_blit, 415 .get_engine_clock = &radeon_legacy_get_engine_clock, 416 .set_engine_clock = &radeon_legacy_set_engine_clock, 417 .get_memory_clock = &radeon_legacy_get_memory_clock, 418 .set_memory_clock = NULL, 419 .get_pcie_lanes = NULL, 420 .set_pcie_lanes = NULL, 421 .set_clock_gating = &radeon_legacy_set_clock_gating, 422 .set_surface_reg = r100_set_surface_reg, 423 .clear_surface_reg = r100_clear_surface_reg, 424 .bandwidth_update = &r100_bandwidth_update, 425 .hpd_init = &r100_hpd_init, 426 .hpd_fini = &r100_hpd_fini, 427 .hpd_sense = &r100_hpd_sense, 428 .hpd_set_polarity = &r100_hpd_set_polarity, 429 .ioctl_wait_idle = NULL, 430 .gui_idle = &r100_gui_idle, 431 .pm_misc = &r100_pm_misc, 432 .pm_prepare = &r100_pm_prepare, 433 .pm_finish = &r100_pm_finish, 434 .pm_init_profile = &r100_pm_init_profile, 435 .pm_get_dynpm_state = &r100_pm_get_dynpm_state, 436 .pre_page_flip = &r100_pre_page_flip, 437 .page_flip = &r100_page_flip, 438 .post_page_flip = &r100_post_page_flip, 439 }; 440 441 static struct radeon_asic rs600_asic = { 442 .init = &rs600_init, 443 .fini = &rs600_fini, 444 .suspend = &rs600_suspend, 445 .resume = &rs600_resume, 446 .vga_set_state = &r100_vga_set_state, 447 .gpu_is_lockup = &r300_gpu_is_lockup, 448 .asic_reset = &rs600_asic_reset, 449 .gart_tlb_flush = &rs600_gart_tlb_flush, 450 .gart_set_page = &rs600_gart_set_page, 451 .ring_start = &r300_ring_start, 452 .ring_test = &r100_ring_test, 453 .ring = { 454 [RADEON_RING_TYPE_GFX_INDEX] = { 455 .ib_execute = &r100_ring_ib_execute, 456 .emit_fence = &r300_fence_ring_emit, 457 .emit_semaphore = &r100_semaphore_ring_emit, 458 } 459 }, 460 .irq_set = &rs600_irq_set, 461 .irq_process = &rs600_irq_process, 462 .get_vblank_counter = &rs600_get_vblank_counter, 463 .cs_parse = &r300_cs_parse, 464 .copy_blit = &r100_copy_blit, 465 .copy_dma = &r200_copy_dma, 466 .copy = &r100_copy_blit, 467 .get_engine_clock = &radeon_atom_get_engine_clock, 468 .set_engine_clock = &radeon_atom_set_engine_clock, 469 .get_memory_clock = &radeon_atom_get_memory_clock, 470 .set_memory_clock = &radeon_atom_set_memory_clock, 471 .get_pcie_lanes = NULL, 472 .set_pcie_lanes = NULL, 473 .set_clock_gating = &radeon_atom_set_clock_gating, 474 .set_surface_reg = r100_set_surface_reg, 475 .clear_surface_reg = r100_clear_surface_reg, 476 .bandwidth_update = &rs600_bandwidth_update, 477 .hpd_init = &rs600_hpd_init, 478 .hpd_fini = &rs600_hpd_fini, 479 .hpd_sense = &rs600_hpd_sense, 480 .hpd_set_polarity = &rs600_hpd_set_polarity, 481 .ioctl_wait_idle = NULL, 482 .gui_idle = &r100_gui_idle, 483 .pm_misc = &rs600_pm_misc, 484 .pm_prepare = &rs600_pm_prepare, 485 .pm_finish = &rs600_pm_finish, 486 .pm_init_profile = &r420_pm_init_profile, 487 .pm_get_dynpm_state = &r100_pm_get_dynpm_state, 488 .pre_page_flip = &rs600_pre_page_flip, 489 .page_flip = &rs600_page_flip, 490 .post_page_flip = &rs600_post_page_flip, 491 }; 492 493 static struct radeon_asic rs690_asic = { 494 .init = &rs690_init, 495 .fini = &rs690_fini, 496 .suspend = &rs690_suspend, 497 .resume = &rs690_resume, 498 .vga_set_state = &r100_vga_set_state, 499 .gpu_is_lockup = &r300_gpu_is_lockup, 500 .asic_reset = &rs600_asic_reset, 501 .gart_tlb_flush = &rs400_gart_tlb_flush, 502 .gart_set_page = &rs400_gart_set_page, 503 .ring_start = &r300_ring_start, 504 .ring_test = &r100_ring_test, 505 .ring = { 506 [RADEON_RING_TYPE_GFX_INDEX] = { 507 .ib_execute = &r100_ring_ib_execute, 508 .emit_fence = &r300_fence_ring_emit, 509 .emit_semaphore = &r100_semaphore_ring_emit, 510 } 511 }, 512 .irq_set = &rs600_irq_set, 513 .irq_process = &rs600_irq_process, 514 .get_vblank_counter = &rs600_get_vblank_counter, 515 .cs_parse = &r300_cs_parse, 516 .copy_blit = &r100_copy_blit, 517 .copy_dma = &r200_copy_dma, 518 .copy = &r200_copy_dma, 519 .get_engine_clock = &radeon_atom_get_engine_clock, 520 .set_engine_clock = &radeon_atom_set_engine_clock, 521 .get_memory_clock = &radeon_atom_get_memory_clock, 522 .set_memory_clock = &radeon_atom_set_memory_clock, 523 .get_pcie_lanes = NULL, 524 .set_pcie_lanes = NULL, 525 .set_clock_gating = &radeon_atom_set_clock_gating, 526 .set_surface_reg = r100_set_surface_reg, 527 .clear_surface_reg = r100_clear_surface_reg, 528 .bandwidth_update = &rs690_bandwidth_update, 529 .hpd_init = &rs600_hpd_init, 530 .hpd_fini = &rs600_hpd_fini, 531 .hpd_sense = &rs600_hpd_sense, 532 .hpd_set_polarity = &rs600_hpd_set_polarity, 533 .ioctl_wait_idle = NULL, 534 .gui_idle = &r100_gui_idle, 535 .pm_misc = &rs600_pm_misc, 536 .pm_prepare = &rs600_pm_prepare, 537 .pm_finish = &rs600_pm_finish, 538 .pm_init_profile = &r420_pm_init_profile, 539 .pm_get_dynpm_state = &r100_pm_get_dynpm_state, 540 .pre_page_flip = &rs600_pre_page_flip, 541 .page_flip = &rs600_page_flip, 542 .post_page_flip = &rs600_post_page_flip, 543 }; 544 545 static struct radeon_asic rv515_asic = { 546 .init = &rv515_init, 547 .fini = &rv515_fini, 548 .suspend = &rv515_suspend, 549 .resume = &rv515_resume, 550 .vga_set_state = &r100_vga_set_state, 551 .gpu_is_lockup = &r300_gpu_is_lockup, 552 .asic_reset = &rs600_asic_reset, 553 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, 554 .gart_set_page = &rv370_pcie_gart_set_page, 555 .ring_start = &rv515_ring_start, 556 .ring_test = &r100_ring_test, 557 .ring = { 558 [RADEON_RING_TYPE_GFX_INDEX] = { 559 .ib_execute = &r100_ring_ib_execute, 560 .emit_fence = &r300_fence_ring_emit, 561 .emit_semaphore = &r100_semaphore_ring_emit, 562 } 563 }, 564 .irq_set = &rs600_irq_set, 565 .irq_process = &rs600_irq_process, 566 .get_vblank_counter = &rs600_get_vblank_counter, 567 .cs_parse = &r300_cs_parse, 568 .copy_blit = &r100_copy_blit, 569 .copy_dma = &r200_copy_dma, 570 .copy = &r100_copy_blit, 571 .get_engine_clock = &radeon_atom_get_engine_clock, 572 .set_engine_clock = &radeon_atom_set_engine_clock, 573 .get_memory_clock = &radeon_atom_get_memory_clock, 574 .set_memory_clock = &radeon_atom_set_memory_clock, 575 .get_pcie_lanes = &rv370_get_pcie_lanes, 576 .set_pcie_lanes = &rv370_set_pcie_lanes, 577 .set_clock_gating = &radeon_atom_set_clock_gating, 578 .set_surface_reg = r100_set_surface_reg, 579 .clear_surface_reg = r100_clear_surface_reg, 580 .bandwidth_update = &rv515_bandwidth_update, 581 .hpd_init = &rs600_hpd_init, 582 .hpd_fini = &rs600_hpd_fini, 583 .hpd_sense = &rs600_hpd_sense, 584 .hpd_set_polarity = &rs600_hpd_set_polarity, 585 .ioctl_wait_idle = NULL, 586 .gui_idle = &r100_gui_idle, 587 .pm_misc = &rs600_pm_misc, 588 .pm_prepare = &rs600_pm_prepare, 589 .pm_finish = &rs600_pm_finish, 590 .pm_init_profile = &r420_pm_init_profile, 591 .pm_get_dynpm_state = &r100_pm_get_dynpm_state, 592 .pre_page_flip = &rs600_pre_page_flip, 593 .page_flip = &rs600_page_flip, 594 .post_page_flip = &rs600_post_page_flip, 595 }; 596 597 static struct radeon_asic r520_asic = { 598 .init = &r520_init, 599 .fini = &rv515_fini, 600 .suspend = &rv515_suspend, 601 .resume = &r520_resume, 602 .vga_set_state = &r100_vga_set_state, 603 .gpu_is_lockup = &r300_gpu_is_lockup, 604 .asic_reset = &rs600_asic_reset, 605 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, 606 .gart_set_page = &rv370_pcie_gart_set_page, 607 .ring_start = &rv515_ring_start, 608 .ring_test = &r100_ring_test, 609 .ring = { 610 [RADEON_RING_TYPE_GFX_INDEX] = { 611 .ib_execute = &r100_ring_ib_execute, 612 .emit_fence = &r300_fence_ring_emit, 613 .emit_semaphore = &r100_semaphore_ring_emit, 614 } 615 }, 616 .irq_set = &rs600_irq_set, 617 .irq_process = &rs600_irq_process, 618 .get_vblank_counter = &rs600_get_vblank_counter, 619 .cs_parse = &r300_cs_parse, 620 .copy_blit = &r100_copy_blit, 621 .copy_dma = &r200_copy_dma, 622 .copy = &r100_copy_blit, 623 .get_engine_clock = &radeon_atom_get_engine_clock, 624 .set_engine_clock = &radeon_atom_set_engine_clock, 625 .get_memory_clock = &radeon_atom_get_memory_clock, 626 .set_memory_clock = &radeon_atom_set_memory_clock, 627 .get_pcie_lanes = &rv370_get_pcie_lanes, 628 .set_pcie_lanes = &rv370_set_pcie_lanes, 629 .set_clock_gating = &radeon_atom_set_clock_gating, 630 .set_surface_reg = r100_set_surface_reg, 631 .clear_surface_reg = r100_clear_surface_reg, 632 .bandwidth_update = &rv515_bandwidth_update, 633 .hpd_init = &rs600_hpd_init, 634 .hpd_fini = &rs600_hpd_fini, 635 .hpd_sense = &rs600_hpd_sense, 636 .hpd_set_polarity = &rs600_hpd_set_polarity, 637 .ioctl_wait_idle = NULL, 638 .gui_idle = &r100_gui_idle, 639 .pm_misc = &rs600_pm_misc, 640 .pm_prepare = &rs600_pm_prepare, 641 .pm_finish = &rs600_pm_finish, 642 .pm_init_profile = &r420_pm_init_profile, 643 .pm_get_dynpm_state = &r100_pm_get_dynpm_state, 644 .pre_page_flip = &rs600_pre_page_flip, 645 .page_flip = &rs600_page_flip, 646 .post_page_flip = &rs600_post_page_flip, 647 }; 648 649 static struct radeon_asic r600_asic = { 650 .init = &r600_init, 651 .fini = &r600_fini, 652 .suspend = &r600_suspend, 653 .resume = &r600_resume, 654 .vga_set_state = &r600_vga_set_state, 655 .gpu_is_lockup = &r600_gpu_is_lockup, 656 .asic_reset = &r600_asic_reset, 657 .gart_tlb_flush = &r600_pcie_gart_tlb_flush, 658 .gart_set_page = &rs600_gart_set_page, 659 .ring_test = &r600_ring_test, 660 .ring = { 661 [RADEON_RING_TYPE_GFX_INDEX] = { 662 .ib_execute = &r600_ring_ib_execute, 663 .emit_fence = &r600_fence_ring_emit, 664 .emit_semaphore = &r600_semaphore_ring_emit, 665 } 666 }, 667 .irq_set = &r600_irq_set, 668 .irq_process = &r600_irq_process, 669 .get_vblank_counter = &rs600_get_vblank_counter, 670 .cs_parse = &r600_cs_parse, 671 .copy_blit = &r600_copy_blit, 672 .copy_dma = NULL, 673 .copy = &r600_copy_blit, 674 .get_engine_clock = &radeon_atom_get_engine_clock, 675 .set_engine_clock = &radeon_atom_set_engine_clock, 676 .get_memory_clock = &radeon_atom_get_memory_clock, 677 .set_memory_clock = &radeon_atom_set_memory_clock, 678 .get_pcie_lanes = &r600_get_pcie_lanes, 679 .set_pcie_lanes = &r600_set_pcie_lanes, 680 .set_clock_gating = NULL, 681 .set_surface_reg = r600_set_surface_reg, 682 .clear_surface_reg = r600_clear_surface_reg, 683 .bandwidth_update = &rv515_bandwidth_update, 684 .hpd_init = &r600_hpd_init, 685 .hpd_fini = &r600_hpd_fini, 686 .hpd_sense = &r600_hpd_sense, 687 .hpd_set_polarity = &r600_hpd_set_polarity, 688 .ioctl_wait_idle = r600_ioctl_wait_idle, 689 .gui_idle = &r600_gui_idle, 690 .pm_misc = &r600_pm_misc, 691 .pm_prepare = &rs600_pm_prepare, 692 .pm_finish = &rs600_pm_finish, 693 .pm_init_profile = &r600_pm_init_profile, 694 .pm_get_dynpm_state = &r600_pm_get_dynpm_state, 695 .pre_page_flip = &rs600_pre_page_flip, 696 .page_flip = &rs600_page_flip, 697 .post_page_flip = &rs600_post_page_flip, 698 }; 699 700 static struct radeon_asic rs780_asic = { 701 .init = &r600_init, 702 .fini = &r600_fini, 703 .suspend = &r600_suspend, 704 .resume = &r600_resume, 705 .gpu_is_lockup = &r600_gpu_is_lockup, 706 .vga_set_state = &r600_vga_set_state, 707 .asic_reset = &r600_asic_reset, 708 .gart_tlb_flush = &r600_pcie_gart_tlb_flush, 709 .gart_set_page = &rs600_gart_set_page, 710 .ring_test = &r600_ring_test, 711 .ring = { 712 [RADEON_RING_TYPE_GFX_INDEX] = { 713 .ib_execute = &r600_ring_ib_execute, 714 .emit_fence = &r600_fence_ring_emit, 715 .emit_semaphore = &r600_semaphore_ring_emit, 716 } 717 }, 718 .irq_set = &r600_irq_set, 719 .irq_process = &r600_irq_process, 720 .get_vblank_counter = &rs600_get_vblank_counter, 721 .cs_parse = &r600_cs_parse, 722 .copy_blit = &r600_copy_blit, 723 .copy_dma = NULL, 724 .copy = &r600_copy_blit, 725 .get_engine_clock = &radeon_atom_get_engine_clock, 726 .set_engine_clock = &radeon_atom_set_engine_clock, 727 .get_memory_clock = NULL, 728 .set_memory_clock = NULL, 729 .get_pcie_lanes = NULL, 730 .set_pcie_lanes = NULL, 731 .set_clock_gating = NULL, 732 .set_surface_reg = r600_set_surface_reg, 733 .clear_surface_reg = r600_clear_surface_reg, 734 .bandwidth_update = &rs690_bandwidth_update, 735 .hpd_init = &r600_hpd_init, 736 .hpd_fini = &r600_hpd_fini, 737 .hpd_sense = &r600_hpd_sense, 738 .hpd_set_polarity = &r600_hpd_set_polarity, 739 .ioctl_wait_idle = r600_ioctl_wait_idle, 740 .gui_idle = &r600_gui_idle, 741 .pm_misc = &r600_pm_misc, 742 .pm_prepare = &rs600_pm_prepare, 743 .pm_finish = &rs600_pm_finish, 744 .pm_init_profile = &rs780_pm_init_profile, 745 .pm_get_dynpm_state = &r600_pm_get_dynpm_state, 746 .pre_page_flip = &rs600_pre_page_flip, 747 .page_flip = &rs600_page_flip, 748 .post_page_flip = &rs600_post_page_flip, 749 }; 750 751 static struct radeon_asic rv770_asic = { 752 .init = &rv770_init, 753 .fini = &rv770_fini, 754 .suspend = &rv770_suspend, 755 .resume = &rv770_resume, 756 .asic_reset = &r600_asic_reset, 757 .gpu_is_lockup = &r600_gpu_is_lockup, 758 .vga_set_state = &r600_vga_set_state, 759 .gart_tlb_flush = &r600_pcie_gart_tlb_flush, 760 .gart_set_page = &rs600_gart_set_page, 761 .ring_test = &r600_ring_test, 762 .ring = { 763 [RADEON_RING_TYPE_GFX_INDEX] = { 764 .ib_execute = &r600_ring_ib_execute, 765 .emit_fence = &r600_fence_ring_emit, 766 .emit_semaphore = &r600_semaphore_ring_emit, 767 } 768 }, 769 .irq_set = &r600_irq_set, 770 .irq_process = &r600_irq_process, 771 .get_vblank_counter = &rs600_get_vblank_counter, 772 .cs_parse = &r600_cs_parse, 773 .copy_blit = &r600_copy_blit, 774 .copy_dma = NULL, 775 .copy = &r600_copy_blit, 776 .get_engine_clock = &radeon_atom_get_engine_clock, 777 .set_engine_clock = &radeon_atom_set_engine_clock, 778 .get_memory_clock = &radeon_atom_get_memory_clock, 779 .set_memory_clock = &radeon_atom_set_memory_clock, 780 .get_pcie_lanes = &r600_get_pcie_lanes, 781 .set_pcie_lanes = &r600_set_pcie_lanes, 782 .set_clock_gating = &radeon_atom_set_clock_gating, 783 .set_surface_reg = r600_set_surface_reg, 784 .clear_surface_reg = r600_clear_surface_reg, 785 .bandwidth_update = &rv515_bandwidth_update, 786 .hpd_init = &r600_hpd_init, 787 .hpd_fini = &r600_hpd_fini, 788 .hpd_sense = &r600_hpd_sense, 789 .hpd_set_polarity = &r600_hpd_set_polarity, 790 .ioctl_wait_idle = r600_ioctl_wait_idle, 791 .gui_idle = &r600_gui_idle, 792 .pm_misc = &rv770_pm_misc, 793 .pm_prepare = &rs600_pm_prepare, 794 .pm_finish = &rs600_pm_finish, 795 .pm_init_profile = &r600_pm_init_profile, 796 .pm_get_dynpm_state = &r600_pm_get_dynpm_state, 797 .pre_page_flip = &rs600_pre_page_flip, 798 .page_flip = &rv770_page_flip, 799 .post_page_flip = &rs600_post_page_flip, 800 }; 801 802 static struct radeon_asic evergreen_asic = { 803 .init = &evergreen_init, 804 .fini = &evergreen_fini, 805 .suspend = &evergreen_suspend, 806 .resume = &evergreen_resume, 807 .gpu_is_lockup = &evergreen_gpu_is_lockup, 808 .asic_reset = &evergreen_asic_reset, 809 .vga_set_state = &r600_vga_set_state, 810 .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush, 811 .gart_set_page = &rs600_gart_set_page, 812 .ring_test = &r600_ring_test, 813 .ring = { 814 [RADEON_RING_TYPE_GFX_INDEX] = { 815 .ib_execute = &evergreen_ring_ib_execute, 816 .emit_fence = &r600_fence_ring_emit, 817 .emit_semaphore = &r600_semaphore_ring_emit, 818 } 819 }, 820 .irq_set = &evergreen_irq_set, 821 .irq_process = &evergreen_irq_process, 822 .get_vblank_counter = &evergreen_get_vblank_counter, 823 .cs_parse = &evergreen_cs_parse, 824 .copy_blit = &r600_copy_blit, 825 .copy_dma = NULL, 826 .copy = &r600_copy_blit, 827 .get_engine_clock = &radeon_atom_get_engine_clock, 828 .set_engine_clock = &radeon_atom_set_engine_clock, 829 .get_memory_clock = &radeon_atom_get_memory_clock, 830 .set_memory_clock = &radeon_atom_set_memory_clock, 831 .get_pcie_lanes = &r600_get_pcie_lanes, 832 .set_pcie_lanes = &r600_set_pcie_lanes, 833 .set_clock_gating = NULL, 834 .set_surface_reg = r600_set_surface_reg, 835 .clear_surface_reg = r600_clear_surface_reg, 836 .bandwidth_update = &evergreen_bandwidth_update, 837 .hpd_init = &evergreen_hpd_init, 838 .hpd_fini = &evergreen_hpd_fini, 839 .hpd_sense = &evergreen_hpd_sense, 840 .hpd_set_polarity = &evergreen_hpd_set_polarity, 841 .ioctl_wait_idle = r600_ioctl_wait_idle, 842 .gui_idle = &r600_gui_idle, 843 .pm_misc = &evergreen_pm_misc, 844 .pm_prepare = &evergreen_pm_prepare, 845 .pm_finish = &evergreen_pm_finish, 846 .pm_init_profile = &r600_pm_init_profile, 847 .pm_get_dynpm_state = &r600_pm_get_dynpm_state, 848 .pre_page_flip = &evergreen_pre_page_flip, 849 .page_flip = &evergreen_page_flip, 850 .post_page_flip = &evergreen_post_page_flip, 851 }; 852 853 static struct radeon_asic sumo_asic = { 854 .init = &evergreen_init, 855 .fini = &evergreen_fini, 856 .suspend = &evergreen_suspend, 857 .resume = &evergreen_resume, 858 .gpu_is_lockup = &evergreen_gpu_is_lockup, 859 .asic_reset = &evergreen_asic_reset, 860 .vga_set_state = &r600_vga_set_state, 861 .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush, 862 .gart_set_page = &rs600_gart_set_page, 863 .ring_test = &r600_ring_test, 864 .ring = { 865 [RADEON_RING_TYPE_GFX_INDEX] = { 866 .ib_execute = &evergreen_ring_ib_execute, 867 .emit_fence = &r600_fence_ring_emit, 868 .emit_semaphore = &r600_semaphore_ring_emit, 869 } 870 }, 871 .irq_set = &evergreen_irq_set, 872 .irq_process = &evergreen_irq_process, 873 .get_vblank_counter = &evergreen_get_vblank_counter, 874 .cs_parse = &evergreen_cs_parse, 875 .copy_blit = &r600_copy_blit, 876 .copy_dma = NULL, 877 .copy = &r600_copy_blit, 878 .get_engine_clock = &radeon_atom_get_engine_clock, 879 .set_engine_clock = &radeon_atom_set_engine_clock, 880 .get_memory_clock = NULL, 881 .set_memory_clock = NULL, 882 .get_pcie_lanes = NULL, 883 .set_pcie_lanes = NULL, 884 .set_clock_gating = NULL, 885 .set_surface_reg = r600_set_surface_reg, 886 .clear_surface_reg = r600_clear_surface_reg, 887 .bandwidth_update = &evergreen_bandwidth_update, 888 .hpd_init = &evergreen_hpd_init, 889 .hpd_fini = &evergreen_hpd_fini, 890 .hpd_sense = &evergreen_hpd_sense, 891 .hpd_set_polarity = &evergreen_hpd_set_polarity, 892 .ioctl_wait_idle = r600_ioctl_wait_idle, 893 .gui_idle = &r600_gui_idle, 894 .pm_misc = &evergreen_pm_misc, 895 .pm_prepare = &evergreen_pm_prepare, 896 .pm_finish = &evergreen_pm_finish, 897 .pm_init_profile = &sumo_pm_init_profile, 898 .pm_get_dynpm_state = &r600_pm_get_dynpm_state, 899 .pre_page_flip = &evergreen_pre_page_flip, 900 .page_flip = &evergreen_page_flip, 901 .post_page_flip = &evergreen_post_page_flip, 902 }; 903 904 static struct radeon_asic btc_asic = { 905 .init = &evergreen_init, 906 .fini = &evergreen_fini, 907 .suspend = &evergreen_suspend, 908 .resume = &evergreen_resume, 909 .gpu_is_lockup = &evergreen_gpu_is_lockup, 910 .asic_reset = &evergreen_asic_reset, 911 .vga_set_state = &r600_vga_set_state, 912 .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush, 913 .gart_set_page = &rs600_gart_set_page, 914 .ring_test = &r600_ring_test, 915 .ring = { 916 [RADEON_RING_TYPE_GFX_INDEX] = { 917 .ib_execute = &evergreen_ring_ib_execute, 918 .emit_fence = &r600_fence_ring_emit, 919 .emit_semaphore = &r600_semaphore_ring_emit, 920 } 921 }, 922 .irq_set = &evergreen_irq_set, 923 .irq_process = &evergreen_irq_process, 924 .get_vblank_counter = &evergreen_get_vblank_counter, 925 .cs_parse = &evergreen_cs_parse, 926 .copy_blit = &r600_copy_blit, 927 .copy_dma = NULL, 928 .copy = &r600_copy_blit, 929 .get_engine_clock = &radeon_atom_get_engine_clock, 930 .set_engine_clock = &radeon_atom_set_engine_clock, 931 .get_memory_clock = &radeon_atom_get_memory_clock, 932 .set_memory_clock = &radeon_atom_set_memory_clock, 933 .get_pcie_lanes = NULL, 934 .set_pcie_lanes = NULL, 935 .set_clock_gating = NULL, 936 .set_surface_reg = r600_set_surface_reg, 937 .clear_surface_reg = r600_clear_surface_reg, 938 .bandwidth_update = &evergreen_bandwidth_update, 939 .hpd_init = &evergreen_hpd_init, 940 .hpd_fini = &evergreen_hpd_fini, 941 .hpd_sense = &evergreen_hpd_sense, 942 .hpd_set_polarity = &evergreen_hpd_set_polarity, 943 .ioctl_wait_idle = r600_ioctl_wait_idle, 944 .gui_idle = &r600_gui_idle, 945 .pm_misc = &evergreen_pm_misc, 946 .pm_prepare = &evergreen_pm_prepare, 947 .pm_finish = &evergreen_pm_finish, 948 .pm_init_profile = &r600_pm_init_profile, 949 .pm_get_dynpm_state = &r600_pm_get_dynpm_state, 950 .pre_page_flip = &evergreen_pre_page_flip, 951 .page_flip = &evergreen_page_flip, 952 .post_page_flip = &evergreen_post_page_flip, 953 }; 954 955 static const struct radeon_vm_funcs cayman_vm_funcs = { 956 .init = &cayman_vm_init, 957 .fini = &cayman_vm_fini, 958 .bind = &cayman_vm_bind, 959 .unbind = &cayman_vm_unbind, 960 .tlb_flush = &cayman_vm_tlb_flush, 961 .page_flags = &cayman_vm_page_flags, 962 .set_page = &cayman_vm_set_page, 963 }; 964 965 static struct radeon_asic cayman_asic = { 966 .init = &cayman_init, 967 .fini = &cayman_fini, 968 .suspend = &cayman_suspend, 969 .resume = &cayman_resume, 970 .gpu_is_lockup = &cayman_gpu_is_lockup, 971 .asic_reset = &cayman_asic_reset, 972 .vga_set_state = &r600_vga_set_state, 973 .gart_tlb_flush = &cayman_pcie_gart_tlb_flush, 974 .gart_set_page = &rs600_gart_set_page, 975 .ring_test = &r600_ring_test, 976 .ring = { 977 [RADEON_RING_TYPE_GFX_INDEX] = { 978 .ib_execute = &cayman_ring_ib_execute, 979 .ib_parse = &evergreen_ib_parse, 980 .emit_fence = &cayman_fence_ring_emit, 981 .emit_semaphore = &r600_semaphore_ring_emit, 982 }, 983 [CAYMAN_RING_TYPE_CP1_INDEX] = { 984 .ib_execute = &cayman_ring_ib_execute, 985 .ib_parse = &evergreen_ib_parse, 986 .emit_fence = &cayman_fence_ring_emit, 987 .emit_semaphore = &r600_semaphore_ring_emit, 988 }, 989 [CAYMAN_RING_TYPE_CP2_INDEX] = { 990 .ib_execute = &cayman_ring_ib_execute, 991 .ib_parse = &evergreen_ib_parse, 992 .emit_fence = &cayman_fence_ring_emit, 993 .emit_semaphore = &r600_semaphore_ring_emit, 994 } 995 }, 996 .irq_set = &evergreen_irq_set, 997 .irq_process = &evergreen_irq_process, 998 .get_vblank_counter = &evergreen_get_vblank_counter, 999 .cs_parse = &evergreen_cs_parse, 1000 .copy_blit = &r600_copy_blit, 1001 .copy_dma = NULL, 1002 .copy = &r600_copy_blit, 1003 .get_engine_clock = &radeon_atom_get_engine_clock, 1004 .set_engine_clock = &radeon_atom_set_engine_clock, 1005 .get_memory_clock = &radeon_atom_get_memory_clock, 1006 .set_memory_clock = &radeon_atom_set_memory_clock, 1007 .get_pcie_lanes = NULL, 1008 .set_pcie_lanes = NULL, 1009 .set_clock_gating = NULL, 1010 .set_surface_reg = r600_set_surface_reg, 1011 .clear_surface_reg = r600_clear_surface_reg, 1012 .bandwidth_update = &evergreen_bandwidth_update, 1013 .hpd_init = &evergreen_hpd_init, 1014 .hpd_fini = &evergreen_hpd_fini, 1015 .hpd_sense = &evergreen_hpd_sense, 1016 .hpd_set_polarity = &evergreen_hpd_set_polarity, 1017 .ioctl_wait_idle = r600_ioctl_wait_idle, 1018 .gui_idle = &r600_gui_idle, 1019 .pm_misc = &evergreen_pm_misc, 1020 .pm_prepare = &evergreen_pm_prepare, 1021 .pm_finish = &evergreen_pm_finish, 1022 .pm_init_profile = &r600_pm_init_profile, 1023 .pm_get_dynpm_state = &r600_pm_get_dynpm_state, 1024 .pre_page_flip = &evergreen_pre_page_flip, 1025 .page_flip = &evergreen_page_flip, 1026 .post_page_flip = &evergreen_post_page_flip, 1027 }; 1028 1029 int radeon_asic_init(struct radeon_device *rdev) 1030 { 1031 radeon_register_accessor_init(rdev); 1032 1033 /* set the number of crtcs */ 1034 if (rdev->flags & RADEON_SINGLE_CRTC) 1035 rdev->num_crtc = 1; 1036 else 1037 rdev->num_crtc = 2; 1038 1039 /* set the ring used for bo copies */ 1040 rdev->copy_ring = RADEON_RING_TYPE_GFX_INDEX; 1041 1042 switch (rdev->family) { 1043 case CHIP_R100: 1044 case CHIP_RV100: 1045 case CHIP_RS100: 1046 case CHIP_RV200: 1047 case CHIP_RS200: 1048 rdev->asic = &r100_asic; 1049 break; 1050 case CHIP_R200: 1051 case CHIP_RV250: 1052 case CHIP_RS300: 1053 case CHIP_RV280: 1054 rdev->asic = &r200_asic; 1055 break; 1056 case CHIP_R300: 1057 case CHIP_R350: 1058 case CHIP_RV350: 1059 case CHIP_RV380: 1060 if (rdev->flags & RADEON_IS_PCIE) 1061 rdev->asic = &r300_asic_pcie; 1062 else 1063 rdev->asic = &r300_asic; 1064 break; 1065 case CHIP_R420: 1066 case CHIP_R423: 1067 case CHIP_RV410: 1068 rdev->asic = &r420_asic; 1069 /* handle macs */ 1070 if (rdev->bios == NULL) { 1071 rdev->asic->get_engine_clock = &radeon_legacy_get_engine_clock; 1072 rdev->asic->set_engine_clock = &radeon_legacy_set_engine_clock; 1073 rdev->asic->get_memory_clock = &radeon_legacy_get_memory_clock; 1074 rdev->asic->set_memory_clock = NULL; 1075 } 1076 break; 1077 case CHIP_RS400: 1078 case CHIP_RS480: 1079 rdev->asic = &rs400_asic; 1080 break; 1081 case CHIP_RS600: 1082 rdev->asic = &rs600_asic; 1083 break; 1084 case CHIP_RS690: 1085 case CHIP_RS740: 1086 rdev->asic = &rs690_asic; 1087 break; 1088 case CHIP_RV515: 1089 rdev->asic = &rv515_asic; 1090 break; 1091 case CHIP_R520: 1092 case CHIP_RV530: 1093 case CHIP_RV560: 1094 case CHIP_RV570: 1095 case CHIP_R580: 1096 rdev->asic = &r520_asic; 1097 break; 1098 case CHIP_R600: 1099 case CHIP_RV610: 1100 case CHIP_RV630: 1101 case CHIP_RV620: 1102 case CHIP_RV635: 1103 case CHIP_RV670: 1104 rdev->asic = &r600_asic; 1105 break; 1106 case CHIP_RS780: 1107 case CHIP_RS880: 1108 rdev->asic = &rs780_asic; 1109 break; 1110 case CHIP_RV770: 1111 case CHIP_RV730: 1112 case CHIP_RV710: 1113 case CHIP_RV740: 1114 rdev->asic = &rv770_asic; 1115 break; 1116 case CHIP_CEDAR: 1117 case CHIP_REDWOOD: 1118 case CHIP_JUNIPER: 1119 case CHIP_CYPRESS: 1120 case CHIP_HEMLOCK: 1121 /* set num crtcs */ 1122 if (rdev->family == CHIP_CEDAR) 1123 rdev->num_crtc = 4; 1124 else 1125 rdev->num_crtc = 6; 1126 rdev->asic = &evergreen_asic; 1127 break; 1128 case CHIP_PALM: 1129 case CHIP_SUMO: 1130 case CHIP_SUMO2: 1131 rdev->asic = &sumo_asic; 1132 break; 1133 case CHIP_BARTS: 1134 case CHIP_TURKS: 1135 case CHIP_CAICOS: 1136 /* set num crtcs */ 1137 if (rdev->family == CHIP_CAICOS) 1138 rdev->num_crtc = 4; 1139 else 1140 rdev->num_crtc = 6; 1141 rdev->asic = &btc_asic; 1142 break; 1143 case CHIP_CAYMAN: 1144 rdev->asic = &cayman_asic; 1145 /* set num crtcs */ 1146 rdev->num_crtc = 6; 1147 rdev->vm_manager.funcs = &cayman_vm_funcs; 1148 break; 1149 default: 1150 /* FIXME: not supported yet */ 1151 return -EINVAL; 1152 } 1153 1154 if (rdev->flags & RADEON_IS_IGP) { 1155 rdev->asic->get_memory_clock = NULL; 1156 rdev->asic->set_memory_clock = NULL; 1157 } 1158 1159 return 0; 1160 } 1161 1162