1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include <linux/console.h> 30 #include <drm/drmP.h> 31 #include <drm/drm_crtc_helper.h> 32 #include <drm/radeon_drm.h> 33 #include <linux/vgaarb.h> 34 #include <linux/vga_switcheroo.h> 35 #include "radeon_reg.h" 36 #include "radeon.h" 37 #include "radeon_asic.h" 38 #include "atom.h" 39 40 /* 41 * Registers accessors functions. 42 */ 43 static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg) 44 { 45 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); 46 BUG_ON(1); 47 return 0; 48 } 49 50 static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 51 { 52 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", 53 reg, v); 54 BUG_ON(1); 55 } 56 57 static void radeon_register_accessor_init(struct radeon_device *rdev) 58 { 59 rdev->mc_rreg = &radeon_invalid_rreg; 60 rdev->mc_wreg = &radeon_invalid_wreg; 61 rdev->pll_rreg = &radeon_invalid_rreg; 62 rdev->pll_wreg = &radeon_invalid_wreg; 63 rdev->pciep_rreg = &radeon_invalid_rreg; 64 rdev->pciep_wreg = &radeon_invalid_wreg; 65 66 /* Don't change order as we are overridding accessor. */ 67 if (rdev->family < CHIP_RV515) { 68 rdev->pcie_reg_mask = 0xff; 69 } else { 70 rdev->pcie_reg_mask = 0x7ff; 71 } 72 /* FIXME: not sure here */ 73 if (rdev->family <= CHIP_R580) { 74 rdev->pll_rreg = &r100_pll_rreg; 75 rdev->pll_wreg = &r100_pll_wreg; 76 } 77 if (rdev->family >= CHIP_R420) { 78 rdev->mc_rreg = &r420_mc_rreg; 79 rdev->mc_wreg = &r420_mc_wreg; 80 } 81 if (rdev->family >= CHIP_RV515) { 82 rdev->mc_rreg = &rv515_mc_rreg; 83 rdev->mc_wreg = &rv515_mc_wreg; 84 } 85 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) { 86 rdev->mc_rreg = &rs400_mc_rreg; 87 rdev->mc_wreg = &rs400_mc_wreg; 88 } 89 if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { 90 rdev->mc_rreg = &rs690_mc_rreg; 91 rdev->mc_wreg = &rs690_mc_wreg; 92 } 93 if (rdev->family == CHIP_RS600) { 94 rdev->mc_rreg = &rs600_mc_rreg; 95 rdev->mc_wreg = &rs600_mc_wreg; 96 } 97 if ((rdev->family >= CHIP_R600) && (rdev->family <= CHIP_RV740)) { 98 rdev->pciep_rreg = &r600_pciep_rreg; 99 rdev->pciep_wreg = &r600_pciep_wreg; 100 } 101 } 102 103 104 /* helper to disable agp */ 105 void radeon_agp_disable(struct radeon_device *rdev) 106 { 107 rdev->flags &= ~RADEON_IS_AGP; 108 if (rdev->family >= CHIP_R600) { 109 DRM_INFO("Forcing AGP to PCIE mode\n"); 110 rdev->flags |= RADEON_IS_PCIE; 111 } else if (rdev->family >= CHIP_RV515 || 112 rdev->family == CHIP_RV380 || 113 rdev->family == CHIP_RV410 || 114 rdev->family == CHIP_R423) { 115 DRM_INFO("Forcing AGP to PCIE mode\n"); 116 rdev->flags |= RADEON_IS_PCIE; 117 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush; 118 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page; 119 } else { 120 DRM_INFO("Forcing AGP to PCI mode\n"); 121 rdev->flags |= RADEON_IS_PCI; 122 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush; 123 rdev->asic->gart_set_page = &r100_pci_gart_set_page; 124 } 125 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; 126 } 127 128 /* 129 * ASIC 130 */ 131 static struct radeon_asic r100_asic = { 132 .init = &r100_init, 133 .fini = &r100_fini, 134 .suspend = &r100_suspend, 135 .resume = &r100_resume, 136 .vga_set_state = &r100_vga_set_state, 137 .gpu_reset = &r100_gpu_reset, 138 .gart_tlb_flush = &r100_pci_gart_tlb_flush, 139 .gart_set_page = &r100_pci_gart_set_page, 140 .cp_commit = &r100_cp_commit, 141 .ring_start = &r100_ring_start, 142 .ring_test = &r100_ring_test, 143 .ring_ib_execute = &r100_ring_ib_execute, 144 .irq_set = &r100_irq_set, 145 .irq_process = &r100_irq_process, 146 .get_vblank_counter = &r100_get_vblank_counter, 147 .fence_ring_emit = &r100_fence_ring_emit, 148 .cs_parse = &r100_cs_parse, 149 .copy_blit = &r100_copy_blit, 150 .copy_dma = NULL, 151 .copy = &r100_copy_blit, 152 .get_engine_clock = &radeon_legacy_get_engine_clock, 153 .set_engine_clock = &radeon_legacy_set_engine_clock, 154 .get_memory_clock = &radeon_legacy_get_memory_clock, 155 .set_memory_clock = NULL, 156 .get_pcie_lanes = NULL, 157 .set_pcie_lanes = NULL, 158 .set_clock_gating = &radeon_legacy_set_clock_gating, 159 .set_surface_reg = r100_set_surface_reg, 160 .clear_surface_reg = r100_clear_surface_reg, 161 .bandwidth_update = &r100_bandwidth_update, 162 .hpd_init = &r100_hpd_init, 163 .hpd_fini = &r100_hpd_fini, 164 .hpd_sense = &r100_hpd_sense, 165 .hpd_set_polarity = &r100_hpd_set_polarity, 166 .ioctl_wait_idle = NULL, 167 }; 168 169 static struct radeon_asic r200_asic = { 170 .init = &r100_init, 171 .fini = &r100_fini, 172 .suspend = &r100_suspend, 173 .resume = &r100_resume, 174 .vga_set_state = &r100_vga_set_state, 175 .gpu_reset = &r100_gpu_reset, 176 .gart_tlb_flush = &r100_pci_gart_tlb_flush, 177 .gart_set_page = &r100_pci_gart_set_page, 178 .cp_commit = &r100_cp_commit, 179 .ring_start = &r100_ring_start, 180 .ring_test = &r100_ring_test, 181 .ring_ib_execute = &r100_ring_ib_execute, 182 .irq_set = &r100_irq_set, 183 .irq_process = &r100_irq_process, 184 .get_vblank_counter = &r100_get_vblank_counter, 185 .fence_ring_emit = &r100_fence_ring_emit, 186 .cs_parse = &r100_cs_parse, 187 .copy_blit = &r100_copy_blit, 188 .copy_dma = &r200_copy_dma, 189 .copy = &r100_copy_blit, 190 .get_engine_clock = &radeon_legacy_get_engine_clock, 191 .set_engine_clock = &radeon_legacy_set_engine_clock, 192 .get_memory_clock = &radeon_legacy_get_memory_clock, 193 .set_memory_clock = NULL, 194 .set_pcie_lanes = NULL, 195 .set_clock_gating = &radeon_legacy_set_clock_gating, 196 .set_surface_reg = r100_set_surface_reg, 197 .clear_surface_reg = r100_clear_surface_reg, 198 .bandwidth_update = &r100_bandwidth_update, 199 .hpd_init = &r100_hpd_init, 200 .hpd_fini = &r100_hpd_fini, 201 .hpd_sense = &r100_hpd_sense, 202 .hpd_set_polarity = &r100_hpd_set_polarity, 203 .ioctl_wait_idle = NULL, 204 }; 205 206 static struct radeon_asic r300_asic = { 207 .init = &r300_init, 208 .fini = &r300_fini, 209 .suspend = &r300_suspend, 210 .resume = &r300_resume, 211 .vga_set_state = &r100_vga_set_state, 212 .gpu_reset = &r300_gpu_reset, 213 .gart_tlb_flush = &r100_pci_gart_tlb_flush, 214 .gart_set_page = &r100_pci_gart_set_page, 215 .cp_commit = &r100_cp_commit, 216 .ring_start = &r300_ring_start, 217 .ring_test = &r100_ring_test, 218 .ring_ib_execute = &r100_ring_ib_execute, 219 .irq_set = &r100_irq_set, 220 .irq_process = &r100_irq_process, 221 .get_vblank_counter = &r100_get_vblank_counter, 222 .fence_ring_emit = &r300_fence_ring_emit, 223 .cs_parse = &r300_cs_parse, 224 .copy_blit = &r100_copy_blit, 225 .copy_dma = &r200_copy_dma, 226 .copy = &r100_copy_blit, 227 .get_engine_clock = &radeon_legacy_get_engine_clock, 228 .set_engine_clock = &radeon_legacy_set_engine_clock, 229 .get_memory_clock = &radeon_legacy_get_memory_clock, 230 .set_memory_clock = NULL, 231 .get_pcie_lanes = &rv370_get_pcie_lanes, 232 .set_pcie_lanes = &rv370_set_pcie_lanes, 233 .set_clock_gating = &radeon_legacy_set_clock_gating, 234 .set_surface_reg = r100_set_surface_reg, 235 .clear_surface_reg = r100_clear_surface_reg, 236 .bandwidth_update = &r100_bandwidth_update, 237 .hpd_init = &r100_hpd_init, 238 .hpd_fini = &r100_hpd_fini, 239 .hpd_sense = &r100_hpd_sense, 240 .hpd_set_polarity = &r100_hpd_set_polarity, 241 .ioctl_wait_idle = NULL, 242 }; 243 244 static struct radeon_asic r300_asic_pcie = { 245 .init = &r300_init, 246 .fini = &r300_fini, 247 .suspend = &r300_suspend, 248 .resume = &r300_resume, 249 .vga_set_state = &r100_vga_set_state, 250 .gpu_reset = &r300_gpu_reset, 251 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, 252 .gart_set_page = &rv370_pcie_gart_set_page, 253 .cp_commit = &r100_cp_commit, 254 .ring_start = &r300_ring_start, 255 .ring_test = &r100_ring_test, 256 .ring_ib_execute = &r100_ring_ib_execute, 257 .irq_set = &r100_irq_set, 258 .irq_process = &r100_irq_process, 259 .get_vblank_counter = &r100_get_vblank_counter, 260 .fence_ring_emit = &r300_fence_ring_emit, 261 .cs_parse = &r300_cs_parse, 262 .copy_blit = &r100_copy_blit, 263 .copy_dma = &r200_copy_dma, 264 .copy = &r100_copy_blit, 265 .get_engine_clock = &radeon_legacy_get_engine_clock, 266 .set_engine_clock = &radeon_legacy_set_engine_clock, 267 .get_memory_clock = &radeon_legacy_get_memory_clock, 268 .set_memory_clock = NULL, 269 .set_pcie_lanes = &rv370_set_pcie_lanes, 270 .set_clock_gating = &radeon_legacy_set_clock_gating, 271 .set_surface_reg = r100_set_surface_reg, 272 .clear_surface_reg = r100_clear_surface_reg, 273 .bandwidth_update = &r100_bandwidth_update, 274 .hpd_init = &r100_hpd_init, 275 .hpd_fini = &r100_hpd_fini, 276 .hpd_sense = &r100_hpd_sense, 277 .hpd_set_polarity = &r100_hpd_set_polarity, 278 .ioctl_wait_idle = NULL, 279 }; 280 281 static struct radeon_asic r420_asic = { 282 .init = &r420_init, 283 .fini = &r420_fini, 284 .suspend = &r420_suspend, 285 .resume = &r420_resume, 286 .vga_set_state = &r100_vga_set_state, 287 .gpu_reset = &r300_gpu_reset, 288 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, 289 .gart_set_page = &rv370_pcie_gart_set_page, 290 .cp_commit = &r100_cp_commit, 291 .ring_start = &r300_ring_start, 292 .ring_test = &r100_ring_test, 293 .ring_ib_execute = &r100_ring_ib_execute, 294 .irq_set = &r100_irq_set, 295 .irq_process = &r100_irq_process, 296 .get_vblank_counter = &r100_get_vblank_counter, 297 .fence_ring_emit = &r300_fence_ring_emit, 298 .cs_parse = &r300_cs_parse, 299 .copy_blit = &r100_copy_blit, 300 .copy_dma = &r200_copy_dma, 301 .copy = &r100_copy_blit, 302 .get_engine_clock = &radeon_atom_get_engine_clock, 303 .set_engine_clock = &radeon_atom_set_engine_clock, 304 .get_memory_clock = &radeon_atom_get_memory_clock, 305 .set_memory_clock = &radeon_atom_set_memory_clock, 306 .get_pcie_lanes = &rv370_get_pcie_lanes, 307 .set_pcie_lanes = &rv370_set_pcie_lanes, 308 .set_clock_gating = &radeon_atom_set_clock_gating, 309 .set_surface_reg = r100_set_surface_reg, 310 .clear_surface_reg = r100_clear_surface_reg, 311 .bandwidth_update = &r100_bandwidth_update, 312 .hpd_init = &r100_hpd_init, 313 .hpd_fini = &r100_hpd_fini, 314 .hpd_sense = &r100_hpd_sense, 315 .hpd_set_polarity = &r100_hpd_set_polarity, 316 .ioctl_wait_idle = NULL, 317 }; 318 319 static struct radeon_asic rs400_asic = { 320 .init = &rs400_init, 321 .fini = &rs400_fini, 322 .suspend = &rs400_suspend, 323 .resume = &rs400_resume, 324 .vga_set_state = &r100_vga_set_state, 325 .gpu_reset = &r300_gpu_reset, 326 .gart_tlb_flush = &rs400_gart_tlb_flush, 327 .gart_set_page = &rs400_gart_set_page, 328 .cp_commit = &r100_cp_commit, 329 .ring_start = &r300_ring_start, 330 .ring_test = &r100_ring_test, 331 .ring_ib_execute = &r100_ring_ib_execute, 332 .irq_set = &r100_irq_set, 333 .irq_process = &r100_irq_process, 334 .get_vblank_counter = &r100_get_vblank_counter, 335 .fence_ring_emit = &r300_fence_ring_emit, 336 .cs_parse = &r300_cs_parse, 337 .copy_blit = &r100_copy_blit, 338 .copy_dma = &r200_copy_dma, 339 .copy = &r100_copy_blit, 340 .get_engine_clock = &radeon_legacy_get_engine_clock, 341 .set_engine_clock = &radeon_legacy_set_engine_clock, 342 .get_memory_clock = &radeon_legacy_get_memory_clock, 343 .set_memory_clock = NULL, 344 .get_pcie_lanes = NULL, 345 .set_pcie_lanes = NULL, 346 .set_clock_gating = &radeon_legacy_set_clock_gating, 347 .set_surface_reg = r100_set_surface_reg, 348 .clear_surface_reg = r100_clear_surface_reg, 349 .bandwidth_update = &r100_bandwidth_update, 350 .hpd_init = &r100_hpd_init, 351 .hpd_fini = &r100_hpd_fini, 352 .hpd_sense = &r100_hpd_sense, 353 .hpd_set_polarity = &r100_hpd_set_polarity, 354 .ioctl_wait_idle = NULL, 355 }; 356 357 static struct radeon_asic rs600_asic = { 358 .init = &rs600_init, 359 .fini = &rs600_fini, 360 .suspend = &rs600_suspend, 361 .resume = &rs600_resume, 362 .vga_set_state = &r100_vga_set_state, 363 .gpu_reset = &r300_gpu_reset, 364 .gart_tlb_flush = &rs600_gart_tlb_flush, 365 .gart_set_page = &rs600_gart_set_page, 366 .cp_commit = &r100_cp_commit, 367 .ring_start = &r300_ring_start, 368 .ring_test = &r100_ring_test, 369 .ring_ib_execute = &r100_ring_ib_execute, 370 .irq_set = &rs600_irq_set, 371 .irq_process = &rs600_irq_process, 372 .get_vblank_counter = &rs600_get_vblank_counter, 373 .fence_ring_emit = &r300_fence_ring_emit, 374 .cs_parse = &r300_cs_parse, 375 .copy_blit = &r100_copy_blit, 376 .copy_dma = &r200_copy_dma, 377 .copy = &r100_copy_blit, 378 .get_engine_clock = &radeon_atom_get_engine_clock, 379 .set_engine_clock = &radeon_atom_set_engine_clock, 380 .get_memory_clock = &radeon_atom_get_memory_clock, 381 .set_memory_clock = &radeon_atom_set_memory_clock, 382 .get_pcie_lanes = NULL, 383 .set_pcie_lanes = NULL, 384 .set_clock_gating = &radeon_atom_set_clock_gating, 385 .set_surface_reg = r100_set_surface_reg, 386 .clear_surface_reg = r100_clear_surface_reg, 387 .bandwidth_update = &rs600_bandwidth_update, 388 .hpd_init = &rs600_hpd_init, 389 .hpd_fini = &rs600_hpd_fini, 390 .hpd_sense = &rs600_hpd_sense, 391 .hpd_set_polarity = &rs600_hpd_set_polarity, 392 .ioctl_wait_idle = NULL, 393 }; 394 395 static struct radeon_asic rs690_asic = { 396 .init = &rs690_init, 397 .fini = &rs690_fini, 398 .suspend = &rs690_suspend, 399 .resume = &rs690_resume, 400 .vga_set_state = &r100_vga_set_state, 401 .gpu_reset = &r300_gpu_reset, 402 .gart_tlb_flush = &rs400_gart_tlb_flush, 403 .gart_set_page = &rs400_gart_set_page, 404 .cp_commit = &r100_cp_commit, 405 .ring_start = &r300_ring_start, 406 .ring_test = &r100_ring_test, 407 .ring_ib_execute = &r100_ring_ib_execute, 408 .irq_set = &rs600_irq_set, 409 .irq_process = &rs600_irq_process, 410 .get_vblank_counter = &rs600_get_vblank_counter, 411 .fence_ring_emit = &r300_fence_ring_emit, 412 .cs_parse = &r300_cs_parse, 413 .copy_blit = &r100_copy_blit, 414 .copy_dma = &r200_copy_dma, 415 .copy = &r200_copy_dma, 416 .get_engine_clock = &radeon_atom_get_engine_clock, 417 .set_engine_clock = &radeon_atom_set_engine_clock, 418 .get_memory_clock = &radeon_atom_get_memory_clock, 419 .set_memory_clock = &radeon_atom_set_memory_clock, 420 .get_pcie_lanes = NULL, 421 .set_pcie_lanes = NULL, 422 .set_clock_gating = &radeon_atom_set_clock_gating, 423 .set_surface_reg = r100_set_surface_reg, 424 .clear_surface_reg = r100_clear_surface_reg, 425 .bandwidth_update = &rs690_bandwidth_update, 426 .hpd_init = &rs600_hpd_init, 427 .hpd_fini = &rs600_hpd_fini, 428 .hpd_sense = &rs600_hpd_sense, 429 .hpd_set_polarity = &rs600_hpd_set_polarity, 430 .ioctl_wait_idle = NULL, 431 }; 432 433 static struct radeon_asic rv515_asic = { 434 .init = &rv515_init, 435 .fini = &rv515_fini, 436 .suspend = &rv515_suspend, 437 .resume = &rv515_resume, 438 .vga_set_state = &r100_vga_set_state, 439 .gpu_reset = &rv515_gpu_reset, 440 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, 441 .gart_set_page = &rv370_pcie_gart_set_page, 442 .cp_commit = &r100_cp_commit, 443 .ring_start = &rv515_ring_start, 444 .ring_test = &r100_ring_test, 445 .ring_ib_execute = &r100_ring_ib_execute, 446 .irq_set = &rs600_irq_set, 447 .irq_process = &rs600_irq_process, 448 .get_vblank_counter = &rs600_get_vblank_counter, 449 .fence_ring_emit = &r300_fence_ring_emit, 450 .cs_parse = &r300_cs_parse, 451 .copy_blit = &r100_copy_blit, 452 .copy_dma = &r200_copy_dma, 453 .copy = &r100_copy_blit, 454 .get_engine_clock = &radeon_atom_get_engine_clock, 455 .set_engine_clock = &radeon_atom_set_engine_clock, 456 .get_memory_clock = &radeon_atom_get_memory_clock, 457 .set_memory_clock = &radeon_atom_set_memory_clock, 458 .get_pcie_lanes = &rv370_get_pcie_lanes, 459 .set_pcie_lanes = &rv370_set_pcie_lanes, 460 .set_clock_gating = &radeon_atom_set_clock_gating, 461 .set_surface_reg = r100_set_surface_reg, 462 .clear_surface_reg = r100_clear_surface_reg, 463 .bandwidth_update = &rv515_bandwidth_update, 464 .hpd_init = &rs600_hpd_init, 465 .hpd_fini = &rs600_hpd_fini, 466 .hpd_sense = &rs600_hpd_sense, 467 .hpd_set_polarity = &rs600_hpd_set_polarity, 468 .ioctl_wait_idle = NULL, 469 }; 470 471 static struct radeon_asic r520_asic = { 472 .init = &r520_init, 473 .fini = &rv515_fini, 474 .suspend = &rv515_suspend, 475 .resume = &r520_resume, 476 .vga_set_state = &r100_vga_set_state, 477 .gpu_reset = &rv515_gpu_reset, 478 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, 479 .gart_set_page = &rv370_pcie_gart_set_page, 480 .cp_commit = &r100_cp_commit, 481 .ring_start = &rv515_ring_start, 482 .ring_test = &r100_ring_test, 483 .ring_ib_execute = &r100_ring_ib_execute, 484 .irq_set = &rs600_irq_set, 485 .irq_process = &rs600_irq_process, 486 .get_vblank_counter = &rs600_get_vblank_counter, 487 .fence_ring_emit = &r300_fence_ring_emit, 488 .cs_parse = &r300_cs_parse, 489 .copy_blit = &r100_copy_blit, 490 .copy_dma = &r200_copy_dma, 491 .copy = &r100_copy_blit, 492 .get_engine_clock = &radeon_atom_get_engine_clock, 493 .set_engine_clock = &radeon_atom_set_engine_clock, 494 .get_memory_clock = &radeon_atom_get_memory_clock, 495 .set_memory_clock = &radeon_atom_set_memory_clock, 496 .get_pcie_lanes = &rv370_get_pcie_lanes, 497 .set_pcie_lanes = &rv370_set_pcie_lanes, 498 .set_clock_gating = &radeon_atom_set_clock_gating, 499 .set_surface_reg = r100_set_surface_reg, 500 .clear_surface_reg = r100_clear_surface_reg, 501 .bandwidth_update = &rv515_bandwidth_update, 502 .hpd_init = &rs600_hpd_init, 503 .hpd_fini = &rs600_hpd_fini, 504 .hpd_sense = &rs600_hpd_sense, 505 .hpd_set_polarity = &rs600_hpd_set_polarity, 506 .ioctl_wait_idle = NULL, 507 }; 508 509 static struct radeon_asic r600_asic = { 510 .init = &r600_init, 511 .fini = &r600_fini, 512 .suspend = &r600_suspend, 513 .resume = &r600_resume, 514 .cp_commit = &r600_cp_commit, 515 .vga_set_state = &r600_vga_set_state, 516 .gpu_reset = &r600_gpu_reset, 517 .gart_tlb_flush = &r600_pcie_gart_tlb_flush, 518 .gart_set_page = &rs600_gart_set_page, 519 .ring_test = &r600_ring_test, 520 .ring_ib_execute = &r600_ring_ib_execute, 521 .irq_set = &r600_irq_set, 522 .irq_process = &r600_irq_process, 523 .get_vblank_counter = &rs600_get_vblank_counter, 524 .fence_ring_emit = &r600_fence_ring_emit, 525 .cs_parse = &r600_cs_parse, 526 .copy_blit = &r600_copy_blit, 527 .copy_dma = &r600_copy_blit, 528 .copy = &r600_copy_blit, 529 .get_engine_clock = &radeon_atom_get_engine_clock, 530 .set_engine_clock = &radeon_atom_set_engine_clock, 531 .get_memory_clock = &radeon_atom_get_memory_clock, 532 .set_memory_clock = &radeon_atom_set_memory_clock, 533 .get_pcie_lanes = &rv370_get_pcie_lanes, 534 .set_pcie_lanes = NULL, 535 .set_clock_gating = NULL, 536 .set_surface_reg = r600_set_surface_reg, 537 .clear_surface_reg = r600_clear_surface_reg, 538 .bandwidth_update = &rv515_bandwidth_update, 539 .hpd_init = &r600_hpd_init, 540 .hpd_fini = &r600_hpd_fini, 541 .hpd_sense = &r600_hpd_sense, 542 .hpd_set_polarity = &r600_hpd_set_polarity, 543 .ioctl_wait_idle = r600_ioctl_wait_idle, 544 }; 545 546 static struct radeon_asic rv770_asic = { 547 .init = &rv770_init, 548 .fini = &rv770_fini, 549 .suspend = &rv770_suspend, 550 .resume = &rv770_resume, 551 .cp_commit = &r600_cp_commit, 552 .gpu_reset = &rv770_gpu_reset, 553 .vga_set_state = &r600_vga_set_state, 554 .gart_tlb_flush = &r600_pcie_gart_tlb_flush, 555 .gart_set_page = &rs600_gart_set_page, 556 .ring_test = &r600_ring_test, 557 .ring_ib_execute = &r600_ring_ib_execute, 558 .irq_set = &r600_irq_set, 559 .irq_process = &r600_irq_process, 560 .get_vblank_counter = &rs600_get_vblank_counter, 561 .fence_ring_emit = &r600_fence_ring_emit, 562 .cs_parse = &r600_cs_parse, 563 .copy_blit = &r600_copy_blit, 564 .copy_dma = &r600_copy_blit, 565 .copy = &r600_copy_blit, 566 .get_engine_clock = &radeon_atom_get_engine_clock, 567 .set_engine_clock = &radeon_atom_set_engine_clock, 568 .get_memory_clock = &radeon_atom_get_memory_clock, 569 .set_memory_clock = &radeon_atom_set_memory_clock, 570 .get_pcie_lanes = &rv370_get_pcie_lanes, 571 .set_pcie_lanes = NULL, 572 .set_clock_gating = &radeon_atom_set_clock_gating, 573 .set_surface_reg = r600_set_surface_reg, 574 .clear_surface_reg = r600_clear_surface_reg, 575 .bandwidth_update = &rv515_bandwidth_update, 576 .hpd_init = &r600_hpd_init, 577 .hpd_fini = &r600_hpd_fini, 578 .hpd_sense = &r600_hpd_sense, 579 .hpd_set_polarity = &r600_hpd_set_polarity, 580 .ioctl_wait_idle = r600_ioctl_wait_idle, 581 }; 582 583 static struct radeon_asic evergreen_asic = { 584 .init = &evergreen_init, 585 .fini = &evergreen_fini, 586 .suspend = &evergreen_suspend, 587 .resume = &evergreen_resume, 588 .cp_commit = NULL, 589 .gpu_reset = &evergreen_gpu_reset, 590 .vga_set_state = &r600_vga_set_state, 591 .gart_tlb_flush = &r600_pcie_gart_tlb_flush, 592 .gart_set_page = &rs600_gart_set_page, 593 .ring_test = NULL, 594 .ring_ib_execute = NULL, 595 .irq_set = NULL, 596 .irq_process = NULL, 597 .get_vblank_counter = NULL, 598 .fence_ring_emit = NULL, 599 .cs_parse = NULL, 600 .copy_blit = NULL, 601 .copy_dma = NULL, 602 .copy = NULL, 603 .get_engine_clock = &radeon_atom_get_engine_clock, 604 .set_engine_clock = &radeon_atom_set_engine_clock, 605 .get_memory_clock = &radeon_atom_get_memory_clock, 606 .set_memory_clock = &radeon_atom_set_memory_clock, 607 .set_pcie_lanes = NULL, 608 .set_clock_gating = NULL, 609 .set_surface_reg = r600_set_surface_reg, 610 .clear_surface_reg = r600_clear_surface_reg, 611 .bandwidth_update = &evergreen_bandwidth_update, 612 .hpd_init = &evergreen_hpd_init, 613 .hpd_fini = &evergreen_hpd_fini, 614 .hpd_sense = &evergreen_hpd_sense, 615 .hpd_set_polarity = &evergreen_hpd_set_polarity, 616 }; 617 618 int radeon_asic_init(struct radeon_device *rdev) 619 { 620 radeon_register_accessor_init(rdev); 621 switch (rdev->family) { 622 case CHIP_R100: 623 case CHIP_RV100: 624 case CHIP_RS100: 625 case CHIP_RV200: 626 case CHIP_RS200: 627 rdev->asic = &r100_asic; 628 break; 629 case CHIP_R200: 630 case CHIP_RV250: 631 case CHIP_RS300: 632 case CHIP_RV280: 633 rdev->asic = &r200_asic; 634 break; 635 case CHIP_R300: 636 case CHIP_R350: 637 case CHIP_RV350: 638 case CHIP_RV380: 639 if (rdev->flags & RADEON_IS_PCIE) 640 rdev->asic = &r300_asic_pcie; 641 else 642 rdev->asic = &r300_asic; 643 break; 644 case CHIP_R420: 645 case CHIP_R423: 646 case CHIP_RV410: 647 rdev->asic = &r420_asic; 648 break; 649 case CHIP_RS400: 650 case CHIP_RS480: 651 rdev->asic = &rs400_asic; 652 break; 653 case CHIP_RS600: 654 rdev->asic = &rs600_asic; 655 break; 656 case CHIP_RS690: 657 case CHIP_RS740: 658 rdev->asic = &rs690_asic; 659 break; 660 case CHIP_RV515: 661 rdev->asic = &rv515_asic; 662 break; 663 case CHIP_R520: 664 case CHIP_RV530: 665 case CHIP_RV560: 666 case CHIP_RV570: 667 case CHIP_R580: 668 rdev->asic = &r520_asic; 669 break; 670 case CHIP_R600: 671 case CHIP_RV610: 672 case CHIP_RV630: 673 case CHIP_RV620: 674 case CHIP_RV635: 675 case CHIP_RV670: 676 case CHIP_RS780: 677 case CHIP_RS880: 678 rdev->asic = &r600_asic; 679 break; 680 case CHIP_RV770: 681 case CHIP_RV730: 682 case CHIP_RV710: 683 case CHIP_RV740: 684 rdev->asic = &rv770_asic; 685 break; 686 case CHIP_CEDAR: 687 case CHIP_REDWOOD: 688 case CHIP_JUNIPER: 689 case CHIP_CYPRESS: 690 case CHIP_HEMLOCK: 691 rdev->asic = &evergreen_asic; 692 break; 693 default: 694 /* FIXME: not supported yet */ 695 return -EINVAL; 696 } 697 698 if (rdev->flags & RADEON_IS_IGP) { 699 rdev->asic->get_memory_clock = NULL; 700 rdev->asic->set_memory_clock = NULL; 701 } 702 703 /* set the number of crtcs */ 704 if (rdev->flags & RADEON_SINGLE_CRTC) 705 rdev->num_crtc = 1; 706 else { 707 if (ASIC_IS_DCE4(rdev)) 708 rdev->num_crtc = 6; 709 else 710 rdev->num_crtc = 2; 711 } 712 713 return 0; 714 } 715 716 /* 717 * Wrapper around modesetting bits. Move to radeon_clocks.c? 718 */ 719 int radeon_clocks_init(struct radeon_device *rdev) 720 { 721 int r; 722 723 r = radeon_static_clocks_init(rdev->ddev); 724 if (r) { 725 return r; 726 } 727 DRM_INFO("Clocks initialized !\n"); 728 return 0; 729 } 730 731 void radeon_clocks_fini(struct radeon_device *rdev) 732 { 733 } 734