1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include <linux/console.h> 30 #include <drm/drmP.h> 31 #include <drm/drm_crtc_helper.h> 32 #include <drm/radeon_drm.h> 33 #include <linux/vgaarb.h> 34 #include <linux/vga_switcheroo.h> 35 #include "radeon_reg.h" 36 #include "radeon.h" 37 #include "radeon_asic.h" 38 #include "atom.h" 39 40 /* 41 * Registers accessors functions. 42 */ 43 /** 44 * radeon_invalid_rreg - dummy reg read function 45 * 46 * @rdev: radeon device pointer 47 * @reg: offset of register 48 * 49 * Dummy register read function. Used for register blocks 50 * that certain asics don't have (all asics). 51 * Returns the value in the register. 52 */ 53 static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg) 54 { 55 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); 56 BUG_ON(1); 57 return 0; 58 } 59 60 /** 61 * radeon_invalid_wreg - dummy reg write function 62 * 63 * @rdev: radeon device pointer 64 * @reg: offset of register 65 * @v: value to write to the register 66 * 67 * Dummy register read function. Used for register blocks 68 * that certain asics don't have (all asics). 69 */ 70 static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 71 { 72 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", 73 reg, v); 74 BUG_ON(1); 75 } 76 77 /** 78 * radeon_register_accessor_init - sets up the register accessor callbacks 79 * 80 * @rdev: radeon device pointer 81 * 82 * Sets up the register accessor callbacks for various register 83 * apertures. Not all asics have all apertures (all asics). 84 */ 85 static void radeon_register_accessor_init(struct radeon_device *rdev) 86 { 87 rdev->mc_rreg = &radeon_invalid_rreg; 88 rdev->mc_wreg = &radeon_invalid_wreg; 89 rdev->pll_rreg = &radeon_invalid_rreg; 90 rdev->pll_wreg = &radeon_invalid_wreg; 91 rdev->pciep_rreg = &radeon_invalid_rreg; 92 rdev->pciep_wreg = &radeon_invalid_wreg; 93 94 /* Don't change order as we are overridding accessor. */ 95 if (rdev->family < CHIP_RV515) { 96 rdev->pcie_reg_mask = 0xff; 97 } else { 98 rdev->pcie_reg_mask = 0x7ff; 99 } 100 /* FIXME: not sure here */ 101 if (rdev->family <= CHIP_R580) { 102 rdev->pll_rreg = &r100_pll_rreg; 103 rdev->pll_wreg = &r100_pll_wreg; 104 } 105 if (rdev->family >= CHIP_R420) { 106 rdev->mc_rreg = &r420_mc_rreg; 107 rdev->mc_wreg = &r420_mc_wreg; 108 } 109 if (rdev->family >= CHIP_RV515) { 110 rdev->mc_rreg = &rv515_mc_rreg; 111 rdev->mc_wreg = &rv515_mc_wreg; 112 } 113 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) { 114 rdev->mc_rreg = &rs400_mc_rreg; 115 rdev->mc_wreg = &rs400_mc_wreg; 116 } 117 if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { 118 rdev->mc_rreg = &rs690_mc_rreg; 119 rdev->mc_wreg = &rs690_mc_wreg; 120 } 121 if (rdev->family == CHIP_RS600) { 122 rdev->mc_rreg = &rs600_mc_rreg; 123 rdev->mc_wreg = &rs600_mc_wreg; 124 } 125 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) { 126 rdev->mc_rreg = &rs780_mc_rreg; 127 rdev->mc_wreg = &rs780_mc_wreg; 128 } 129 130 if (rdev->family >= CHIP_BONAIRE) { 131 rdev->pciep_rreg = &cik_pciep_rreg; 132 rdev->pciep_wreg = &cik_pciep_wreg; 133 } else if (rdev->family >= CHIP_R600) { 134 rdev->pciep_rreg = &r600_pciep_rreg; 135 rdev->pciep_wreg = &r600_pciep_wreg; 136 } 137 } 138 139 140 /* helper to disable agp */ 141 /** 142 * radeon_agp_disable - AGP disable helper function 143 * 144 * @rdev: radeon device pointer 145 * 146 * Removes AGP flags and changes the gart callbacks on AGP 147 * cards when using the internal gart rather than AGP (all asics). 148 */ 149 void radeon_agp_disable(struct radeon_device *rdev) 150 { 151 rdev->flags &= ~RADEON_IS_AGP; 152 if (rdev->family >= CHIP_R600) { 153 DRM_INFO("Forcing AGP to PCIE mode\n"); 154 rdev->flags |= RADEON_IS_PCIE; 155 } else if (rdev->family >= CHIP_RV515 || 156 rdev->family == CHIP_RV380 || 157 rdev->family == CHIP_RV410 || 158 rdev->family == CHIP_R423) { 159 DRM_INFO("Forcing AGP to PCIE mode\n"); 160 rdev->flags |= RADEON_IS_PCIE; 161 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush; 162 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page; 163 } else { 164 DRM_INFO("Forcing AGP to PCI mode\n"); 165 rdev->flags |= RADEON_IS_PCI; 166 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush; 167 rdev->asic->gart.set_page = &r100_pci_gart_set_page; 168 } 169 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; 170 } 171 172 /* 173 * ASIC 174 */ 175 176 static struct radeon_asic_ring r100_gfx_ring = { 177 .ib_execute = &r100_ring_ib_execute, 178 .emit_fence = &r100_fence_ring_emit, 179 .emit_semaphore = &r100_semaphore_ring_emit, 180 .cs_parse = &r100_cs_parse, 181 .ring_start = &r100_ring_start, 182 .ring_test = &r100_ring_test, 183 .ib_test = &r100_ib_test, 184 .is_lockup = &r100_gpu_is_lockup, 185 .get_rptr = &r100_gfx_get_rptr, 186 .get_wptr = &r100_gfx_get_wptr, 187 .set_wptr = &r100_gfx_set_wptr, 188 }; 189 190 static struct radeon_asic r100_asic = { 191 .init = &r100_init, 192 .fini = &r100_fini, 193 .suspend = &r100_suspend, 194 .resume = &r100_resume, 195 .vga_set_state = &r100_vga_set_state, 196 .asic_reset = &r100_asic_reset, 197 .mmio_hdp_flush = NULL, 198 .gui_idle = &r100_gui_idle, 199 .mc_wait_for_idle = &r100_mc_wait_for_idle, 200 .gart = { 201 .tlb_flush = &r100_pci_gart_tlb_flush, 202 .set_page = &r100_pci_gart_set_page, 203 }, 204 .ring = { 205 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring 206 }, 207 .irq = { 208 .set = &r100_irq_set, 209 .process = &r100_irq_process, 210 }, 211 .display = { 212 .bandwidth_update = &r100_bandwidth_update, 213 .get_vblank_counter = &r100_get_vblank_counter, 214 .wait_for_vblank = &r100_wait_for_vblank, 215 .set_backlight_level = &radeon_legacy_set_backlight_level, 216 .get_backlight_level = &radeon_legacy_get_backlight_level, 217 }, 218 .copy = { 219 .blit = &r100_copy_blit, 220 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 221 .dma = NULL, 222 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 223 .copy = &r100_copy_blit, 224 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 225 }, 226 .surface = { 227 .set_reg = r100_set_surface_reg, 228 .clear_reg = r100_clear_surface_reg, 229 }, 230 .hpd = { 231 .init = &r100_hpd_init, 232 .fini = &r100_hpd_fini, 233 .sense = &r100_hpd_sense, 234 .set_polarity = &r100_hpd_set_polarity, 235 }, 236 .pm = { 237 .misc = &r100_pm_misc, 238 .prepare = &r100_pm_prepare, 239 .finish = &r100_pm_finish, 240 .init_profile = &r100_pm_init_profile, 241 .get_dynpm_state = &r100_pm_get_dynpm_state, 242 .get_engine_clock = &radeon_legacy_get_engine_clock, 243 .set_engine_clock = &radeon_legacy_set_engine_clock, 244 .get_memory_clock = &radeon_legacy_get_memory_clock, 245 .set_memory_clock = NULL, 246 .get_pcie_lanes = NULL, 247 .set_pcie_lanes = NULL, 248 .set_clock_gating = &radeon_legacy_set_clock_gating, 249 }, 250 .pflip = { 251 .page_flip = &r100_page_flip, 252 .page_flip_pending = &r100_page_flip_pending, 253 }, 254 }; 255 256 static struct radeon_asic r200_asic = { 257 .init = &r100_init, 258 .fini = &r100_fini, 259 .suspend = &r100_suspend, 260 .resume = &r100_resume, 261 .vga_set_state = &r100_vga_set_state, 262 .asic_reset = &r100_asic_reset, 263 .mmio_hdp_flush = NULL, 264 .gui_idle = &r100_gui_idle, 265 .mc_wait_for_idle = &r100_mc_wait_for_idle, 266 .gart = { 267 .tlb_flush = &r100_pci_gart_tlb_flush, 268 .set_page = &r100_pci_gart_set_page, 269 }, 270 .ring = { 271 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring 272 }, 273 .irq = { 274 .set = &r100_irq_set, 275 .process = &r100_irq_process, 276 }, 277 .display = { 278 .bandwidth_update = &r100_bandwidth_update, 279 .get_vblank_counter = &r100_get_vblank_counter, 280 .wait_for_vblank = &r100_wait_for_vblank, 281 .set_backlight_level = &radeon_legacy_set_backlight_level, 282 .get_backlight_level = &radeon_legacy_get_backlight_level, 283 }, 284 .copy = { 285 .blit = &r100_copy_blit, 286 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 287 .dma = &r200_copy_dma, 288 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 289 .copy = &r100_copy_blit, 290 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 291 }, 292 .surface = { 293 .set_reg = r100_set_surface_reg, 294 .clear_reg = r100_clear_surface_reg, 295 }, 296 .hpd = { 297 .init = &r100_hpd_init, 298 .fini = &r100_hpd_fini, 299 .sense = &r100_hpd_sense, 300 .set_polarity = &r100_hpd_set_polarity, 301 }, 302 .pm = { 303 .misc = &r100_pm_misc, 304 .prepare = &r100_pm_prepare, 305 .finish = &r100_pm_finish, 306 .init_profile = &r100_pm_init_profile, 307 .get_dynpm_state = &r100_pm_get_dynpm_state, 308 .get_engine_clock = &radeon_legacy_get_engine_clock, 309 .set_engine_clock = &radeon_legacy_set_engine_clock, 310 .get_memory_clock = &radeon_legacy_get_memory_clock, 311 .set_memory_clock = NULL, 312 .get_pcie_lanes = NULL, 313 .set_pcie_lanes = NULL, 314 .set_clock_gating = &radeon_legacy_set_clock_gating, 315 }, 316 .pflip = { 317 .page_flip = &r100_page_flip, 318 .page_flip_pending = &r100_page_flip_pending, 319 }, 320 }; 321 322 static struct radeon_asic_ring r300_gfx_ring = { 323 .ib_execute = &r100_ring_ib_execute, 324 .emit_fence = &r300_fence_ring_emit, 325 .emit_semaphore = &r100_semaphore_ring_emit, 326 .cs_parse = &r300_cs_parse, 327 .ring_start = &r300_ring_start, 328 .ring_test = &r100_ring_test, 329 .ib_test = &r100_ib_test, 330 .is_lockup = &r100_gpu_is_lockup, 331 .get_rptr = &r100_gfx_get_rptr, 332 .get_wptr = &r100_gfx_get_wptr, 333 .set_wptr = &r100_gfx_set_wptr, 334 }; 335 336 static struct radeon_asic r300_asic = { 337 .init = &r300_init, 338 .fini = &r300_fini, 339 .suspend = &r300_suspend, 340 .resume = &r300_resume, 341 .vga_set_state = &r100_vga_set_state, 342 .asic_reset = &r300_asic_reset, 343 .mmio_hdp_flush = NULL, 344 .gui_idle = &r100_gui_idle, 345 .mc_wait_for_idle = &r300_mc_wait_for_idle, 346 .gart = { 347 .tlb_flush = &r100_pci_gart_tlb_flush, 348 .set_page = &r100_pci_gart_set_page, 349 }, 350 .ring = { 351 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 352 }, 353 .irq = { 354 .set = &r100_irq_set, 355 .process = &r100_irq_process, 356 }, 357 .display = { 358 .bandwidth_update = &r100_bandwidth_update, 359 .get_vblank_counter = &r100_get_vblank_counter, 360 .wait_for_vblank = &r100_wait_for_vblank, 361 .set_backlight_level = &radeon_legacy_set_backlight_level, 362 .get_backlight_level = &radeon_legacy_get_backlight_level, 363 }, 364 .copy = { 365 .blit = &r100_copy_blit, 366 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 367 .dma = &r200_copy_dma, 368 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 369 .copy = &r100_copy_blit, 370 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 371 }, 372 .surface = { 373 .set_reg = r100_set_surface_reg, 374 .clear_reg = r100_clear_surface_reg, 375 }, 376 .hpd = { 377 .init = &r100_hpd_init, 378 .fini = &r100_hpd_fini, 379 .sense = &r100_hpd_sense, 380 .set_polarity = &r100_hpd_set_polarity, 381 }, 382 .pm = { 383 .misc = &r100_pm_misc, 384 .prepare = &r100_pm_prepare, 385 .finish = &r100_pm_finish, 386 .init_profile = &r100_pm_init_profile, 387 .get_dynpm_state = &r100_pm_get_dynpm_state, 388 .get_engine_clock = &radeon_legacy_get_engine_clock, 389 .set_engine_clock = &radeon_legacy_set_engine_clock, 390 .get_memory_clock = &radeon_legacy_get_memory_clock, 391 .set_memory_clock = NULL, 392 .get_pcie_lanes = &rv370_get_pcie_lanes, 393 .set_pcie_lanes = &rv370_set_pcie_lanes, 394 .set_clock_gating = &radeon_legacy_set_clock_gating, 395 }, 396 .pflip = { 397 .page_flip = &r100_page_flip, 398 .page_flip_pending = &r100_page_flip_pending, 399 }, 400 }; 401 402 static struct radeon_asic r300_asic_pcie = { 403 .init = &r300_init, 404 .fini = &r300_fini, 405 .suspend = &r300_suspend, 406 .resume = &r300_resume, 407 .vga_set_state = &r100_vga_set_state, 408 .asic_reset = &r300_asic_reset, 409 .mmio_hdp_flush = NULL, 410 .gui_idle = &r100_gui_idle, 411 .mc_wait_for_idle = &r300_mc_wait_for_idle, 412 .gart = { 413 .tlb_flush = &rv370_pcie_gart_tlb_flush, 414 .set_page = &rv370_pcie_gart_set_page, 415 }, 416 .ring = { 417 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 418 }, 419 .irq = { 420 .set = &r100_irq_set, 421 .process = &r100_irq_process, 422 }, 423 .display = { 424 .bandwidth_update = &r100_bandwidth_update, 425 .get_vblank_counter = &r100_get_vblank_counter, 426 .wait_for_vblank = &r100_wait_for_vblank, 427 .set_backlight_level = &radeon_legacy_set_backlight_level, 428 .get_backlight_level = &radeon_legacy_get_backlight_level, 429 }, 430 .copy = { 431 .blit = &r100_copy_blit, 432 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 433 .dma = &r200_copy_dma, 434 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 435 .copy = &r100_copy_blit, 436 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 437 }, 438 .surface = { 439 .set_reg = r100_set_surface_reg, 440 .clear_reg = r100_clear_surface_reg, 441 }, 442 .hpd = { 443 .init = &r100_hpd_init, 444 .fini = &r100_hpd_fini, 445 .sense = &r100_hpd_sense, 446 .set_polarity = &r100_hpd_set_polarity, 447 }, 448 .pm = { 449 .misc = &r100_pm_misc, 450 .prepare = &r100_pm_prepare, 451 .finish = &r100_pm_finish, 452 .init_profile = &r100_pm_init_profile, 453 .get_dynpm_state = &r100_pm_get_dynpm_state, 454 .get_engine_clock = &radeon_legacy_get_engine_clock, 455 .set_engine_clock = &radeon_legacy_set_engine_clock, 456 .get_memory_clock = &radeon_legacy_get_memory_clock, 457 .set_memory_clock = NULL, 458 .get_pcie_lanes = &rv370_get_pcie_lanes, 459 .set_pcie_lanes = &rv370_set_pcie_lanes, 460 .set_clock_gating = &radeon_legacy_set_clock_gating, 461 }, 462 .pflip = { 463 .page_flip = &r100_page_flip, 464 .page_flip_pending = &r100_page_flip_pending, 465 }, 466 }; 467 468 static struct radeon_asic r420_asic = { 469 .init = &r420_init, 470 .fini = &r420_fini, 471 .suspend = &r420_suspend, 472 .resume = &r420_resume, 473 .vga_set_state = &r100_vga_set_state, 474 .asic_reset = &r300_asic_reset, 475 .mmio_hdp_flush = NULL, 476 .gui_idle = &r100_gui_idle, 477 .mc_wait_for_idle = &r300_mc_wait_for_idle, 478 .gart = { 479 .tlb_flush = &rv370_pcie_gart_tlb_flush, 480 .set_page = &rv370_pcie_gart_set_page, 481 }, 482 .ring = { 483 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 484 }, 485 .irq = { 486 .set = &r100_irq_set, 487 .process = &r100_irq_process, 488 }, 489 .display = { 490 .bandwidth_update = &r100_bandwidth_update, 491 .get_vblank_counter = &r100_get_vblank_counter, 492 .wait_for_vblank = &r100_wait_for_vblank, 493 .set_backlight_level = &atombios_set_backlight_level, 494 .get_backlight_level = &atombios_get_backlight_level, 495 }, 496 .copy = { 497 .blit = &r100_copy_blit, 498 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 499 .dma = &r200_copy_dma, 500 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 501 .copy = &r100_copy_blit, 502 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 503 }, 504 .surface = { 505 .set_reg = r100_set_surface_reg, 506 .clear_reg = r100_clear_surface_reg, 507 }, 508 .hpd = { 509 .init = &r100_hpd_init, 510 .fini = &r100_hpd_fini, 511 .sense = &r100_hpd_sense, 512 .set_polarity = &r100_hpd_set_polarity, 513 }, 514 .pm = { 515 .misc = &r100_pm_misc, 516 .prepare = &r100_pm_prepare, 517 .finish = &r100_pm_finish, 518 .init_profile = &r420_pm_init_profile, 519 .get_dynpm_state = &r100_pm_get_dynpm_state, 520 .get_engine_clock = &radeon_atom_get_engine_clock, 521 .set_engine_clock = &radeon_atom_set_engine_clock, 522 .get_memory_clock = &radeon_atom_get_memory_clock, 523 .set_memory_clock = &radeon_atom_set_memory_clock, 524 .get_pcie_lanes = &rv370_get_pcie_lanes, 525 .set_pcie_lanes = &rv370_set_pcie_lanes, 526 .set_clock_gating = &radeon_atom_set_clock_gating, 527 }, 528 .pflip = { 529 .page_flip = &r100_page_flip, 530 .page_flip_pending = &r100_page_flip_pending, 531 }, 532 }; 533 534 static struct radeon_asic rs400_asic = { 535 .init = &rs400_init, 536 .fini = &rs400_fini, 537 .suspend = &rs400_suspend, 538 .resume = &rs400_resume, 539 .vga_set_state = &r100_vga_set_state, 540 .asic_reset = &r300_asic_reset, 541 .mmio_hdp_flush = NULL, 542 .gui_idle = &r100_gui_idle, 543 .mc_wait_for_idle = &rs400_mc_wait_for_idle, 544 .gart = { 545 .tlb_flush = &rs400_gart_tlb_flush, 546 .set_page = &rs400_gart_set_page, 547 }, 548 .ring = { 549 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 550 }, 551 .irq = { 552 .set = &r100_irq_set, 553 .process = &r100_irq_process, 554 }, 555 .display = { 556 .bandwidth_update = &r100_bandwidth_update, 557 .get_vblank_counter = &r100_get_vblank_counter, 558 .wait_for_vblank = &r100_wait_for_vblank, 559 .set_backlight_level = &radeon_legacy_set_backlight_level, 560 .get_backlight_level = &radeon_legacy_get_backlight_level, 561 }, 562 .copy = { 563 .blit = &r100_copy_blit, 564 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 565 .dma = &r200_copy_dma, 566 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 567 .copy = &r100_copy_blit, 568 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 569 }, 570 .surface = { 571 .set_reg = r100_set_surface_reg, 572 .clear_reg = r100_clear_surface_reg, 573 }, 574 .hpd = { 575 .init = &r100_hpd_init, 576 .fini = &r100_hpd_fini, 577 .sense = &r100_hpd_sense, 578 .set_polarity = &r100_hpd_set_polarity, 579 }, 580 .pm = { 581 .misc = &r100_pm_misc, 582 .prepare = &r100_pm_prepare, 583 .finish = &r100_pm_finish, 584 .init_profile = &r100_pm_init_profile, 585 .get_dynpm_state = &r100_pm_get_dynpm_state, 586 .get_engine_clock = &radeon_legacy_get_engine_clock, 587 .set_engine_clock = &radeon_legacy_set_engine_clock, 588 .get_memory_clock = &radeon_legacy_get_memory_clock, 589 .set_memory_clock = NULL, 590 .get_pcie_lanes = NULL, 591 .set_pcie_lanes = NULL, 592 .set_clock_gating = &radeon_legacy_set_clock_gating, 593 }, 594 .pflip = { 595 .page_flip = &r100_page_flip, 596 .page_flip_pending = &r100_page_flip_pending, 597 }, 598 }; 599 600 static struct radeon_asic rs600_asic = { 601 .init = &rs600_init, 602 .fini = &rs600_fini, 603 .suspend = &rs600_suspend, 604 .resume = &rs600_resume, 605 .vga_set_state = &r100_vga_set_state, 606 .asic_reset = &rs600_asic_reset, 607 .mmio_hdp_flush = NULL, 608 .gui_idle = &r100_gui_idle, 609 .mc_wait_for_idle = &rs600_mc_wait_for_idle, 610 .gart = { 611 .tlb_flush = &rs600_gart_tlb_flush, 612 .set_page = &rs600_gart_set_page, 613 }, 614 .ring = { 615 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 616 }, 617 .irq = { 618 .set = &rs600_irq_set, 619 .process = &rs600_irq_process, 620 }, 621 .display = { 622 .bandwidth_update = &rs600_bandwidth_update, 623 .get_vblank_counter = &rs600_get_vblank_counter, 624 .wait_for_vblank = &avivo_wait_for_vblank, 625 .set_backlight_level = &atombios_set_backlight_level, 626 .get_backlight_level = &atombios_get_backlight_level, 627 .hdmi_enable = &r600_hdmi_enable, 628 .hdmi_setmode = &r600_hdmi_setmode, 629 }, 630 .copy = { 631 .blit = &r100_copy_blit, 632 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 633 .dma = &r200_copy_dma, 634 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 635 .copy = &r100_copy_blit, 636 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 637 }, 638 .surface = { 639 .set_reg = r100_set_surface_reg, 640 .clear_reg = r100_clear_surface_reg, 641 }, 642 .hpd = { 643 .init = &rs600_hpd_init, 644 .fini = &rs600_hpd_fini, 645 .sense = &rs600_hpd_sense, 646 .set_polarity = &rs600_hpd_set_polarity, 647 }, 648 .pm = { 649 .misc = &rs600_pm_misc, 650 .prepare = &rs600_pm_prepare, 651 .finish = &rs600_pm_finish, 652 .init_profile = &r420_pm_init_profile, 653 .get_dynpm_state = &r100_pm_get_dynpm_state, 654 .get_engine_clock = &radeon_atom_get_engine_clock, 655 .set_engine_clock = &radeon_atom_set_engine_clock, 656 .get_memory_clock = &radeon_atom_get_memory_clock, 657 .set_memory_clock = &radeon_atom_set_memory_clock, 658 .get_pcie_lanes = NULL, 659 .set_pcie_lanes = NULL, 660 .set_clock_gating = &radeon_atom_set_clock_gating, 661 }, 662 .pflip = { 663 .page_flip = &rs600_page_flip, 664 .page_flip_pending = &rs600_page_flip_pending, 665 }, 666 }; 667 668 static struct radeon_asic rs690_asic = { 669 .init = &rs690_init, 670 .fini = &rs690_fini, 671 .suspend = &rs690_suspend, 672 .resume = &rs690_resume, 673 .vga_set_state = &r100_vga_set_state, 674 .asic_reset = &rs600_asic_reset, 675 .mmio_hdp_flush = NULL, 676 .gui_idle = &r100_gui_idle, 677 .mc_wait_for_idle = &rs690_mc_wait_for_idle, 678 .gart = { 679 .tlb_flush = &rs400_gart_tlb_flush, 680 .set_page = &rs400_gart_set_page, 681 }, 682 .ring = { 683 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 684 }, 685 .irq = { 686 .set = &rs600_irq_set, 687 .process = &rs600_irq_process, 688 }, 689 .display = { 690 .get_vblank_counter = &rs600_get_vblank_counter, 691 .bandwidth_update = &rs690_bandwidth_update, 692 .wait_for_vblank = &avivo_wait_for_vblank, 693 .set_backlight_level = &atombios_set_backlight_level, 694 .get_backlight_level = &atombios_get_backlight_level, 695 .hdmi_enable = &r600_hdmi_enable, 696 .hdmi_setmode = &r600_hdmi_setmode, 697 }, 698 .copy = { 699 .blit = &r100_copy_blit, 700 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 701 .dma = &r200_copy_dma, 702 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 703 .copy = &r200_copy_dma, 704 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 705 }, 706 .surface = { 707 .set_reg = r100_set_surface_reg, 708 .clear_reg = r100_clear_surface_reg, 709 }, 710 .hpd = { 711 .init = &rs600_hpd_init, 712 .fini = &rs600_hpd_fini, 713 .sense = &rs600_hpd_sense, 714 .set_polarity = &rs600_hpd_set_polarity, 715 }, 716 .pm = { 717 .misc = &rs600_pm_misc, 718 .prepare = &rs600_pm_prepare, 719 .finish = &rs600_pm_finish, 720 .init_profile = &r420_pm_init_profile, 721 .get_dynpm_state = &r100_pm_get_dynpm_state, 722 .get_engine_clock = &radeon_atom_get_engine_clock, 723 .set_engine_clock = &radeon_atom_set_engine_clock, 724 .get_memory_clock = &radeon_atom_get_memory_clock, 725 .set_memory_clock = &radeon_atom_set_memory_clock, 726 .get_pcie_lanes = NULL, 727 .set_pcie_lanes = NULL, 728 .set_clock_gating = &radeon_atom_set_clock_gating, 729 }, 730 .pflip = { 731 .page_flip = &rs600_page_flip, 732 .page_flip_pending = &rs600_page_flip_pending, 733 }, 734 }; 735 736 static struct radeon_asic rv515_asic = { 737 .init = &rv515_init, 738 .fini = &rv515_fini, 739 .suspend = &rv515_suspend, 740 .resume = &rv515_resume, 741 .vga_set_state = &r100_vga_set_state, 742 .asic_reset = &rs600_asic_reset, 743 .mmio_hdp_flush = NULL, 744 .gui_idle = &r100_gui_idle, 745 .mc_wait_for_idle = &rv515_mc_wait_for_idle, 746 .gart = { 747 .tlb_flush = &rv370_pcie_gart_tlb_flush, 748 .set_page = &rv370_pcie_gart_set_page, 749 }, 750 .ring = { 751 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 752 }, 753 .irq = { 754 .set = &rs600_irq_set, 755 .process = &rs600_irq_process, 756 }, 757 .display = { 758 .get_vblank_counter = &rs600_get_vblank_counter, 759 .bandwidth_update = &rv515_bandwidth_update, 760 .wait_for_vblank = &avivo_wait_for_vblank, 761 .set_backlight_level = &atombios_set_backlight_level, 762 .get_backlight_level = &atombios_get_backlight_level, 763 }, 764 .copy = { 765 .blit = &r100_copy_blit, 766 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 767 .dma = &r200_copy_dma, 768 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 769 .copy = &r100_copy_blit, 770 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 771 }, 772 .surface = { 773 .set_reg = r100_set_surface_reg, 774 .clear_reg = r100_clear_surface_reg, 775 }, 776 .hpd = { 777 .init = &rs600_hpd_init, 778 .fini = &rs600_hpd_fini, 779 .sense = &rs600_hpd_sense, 780 .set_polarity = &rs600_hpd_set_polarity, 781 }, 782 .pm = { 783 .misc = &rs600_pm_misc, 784 .prepare = &rs600_pm_prepare, 785 .finish = &rs600_pm_finish, 786 .init_profile = &r420_pm_init_profile, 787 .get_dynpm_state = &r100_pm_get_dynpm_state, 788 .get_engine_clock = &radeon_atom_get_engine_clock, 789 .set_engine_clock = &radeon_atom_set_engine_clock, 790 .get_memory_clock = &radeon_atom_get_memory_clock, 791 .set_memory_clock = &radeon_atom_set_memory_clock, 792 .get_pcie_lanes = &rv370_get_pcie_lanes, 793 .set_pcie_lanes = &rv370_set_pcie_lanes, 794 .set_clock_gating = &radeon_atom_set_clock_gating, 795 }, 796 .pflip = { 797 .page_flip = &rs600_page_flip, 798 .page_flip_pending = &rs600_page_flip_pending, 799 }, 800 }; 801 802 static struct radeon_asic r520_asic = { 803 .init = &r520_init, 804 .fini = &rv515_fini, 805 .suspend = &rv515_suspend, 806 .resume = &r520_resume, 807 .vga_set_state = &r100_vga_set_state, 808 .asic_reset = &rs600_asic_reset, 809 .mmio_hdp_flush = NULL, 810 .gui_idle = &r100_gui_idle, 811 .mc_wait_for_idle = &r520_mc_wait_for_idle, 812 .gart = { 813 .tlb_flush = &rv370_pcie_gart_tlb_flush, 814 .set_page = &rv370_pcie_gart_set_page, 815 }, 816 .ring = { 817 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 818 }, 819 .irq = { 820 .set = &rs600_irq_set, 821 .process = &rs600_irq_process, 822 }, 823 .display = { 824 .bandwidth_update = &rv515_bandwidth_update, 825 .get_vblank_counter = &rs600_get_vblank_counter, 826 .wait_for_vblank = &avivo_wait_for_vblank, 827 .set_backlight_level = &atombios_set_backlight_level, 828 .get_backlight_level = &atombios_get_backlight_level, 829 }, 830 .copy = { 831 .blit = &r100_copy_blit, 832 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 833 .dma = &r200_copy_dma, 834 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 835 .copy = &r100_copy_blit, 836 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 837 }, 838 .surface = { 839 .set_reg = r100_set_surface_reg, 840 .clear_reg = r100_clear_surface_reg, 841 }, 842 .hpd = { 843 .init = &rs600_hpd_init, 844 .fini = &rs600_hpd_fini, 845 .sense = &rs600_hpd_sense, 846 .set_polarity = &rs600_hpd_set_polarity, 847 }, 848 .pm = { 849 .misc = &rs600_pm_misc, 850 .prepare = &rs600_pm_prepare, 851 .finish = &rs600_pm_finish, 852 .init_profile = &r420_pm_init_profile, 853 .get_dynpm_state = &r100_pm_get_dynpm_state, 854 .get_engine_clock = &radeon_atom_get_engine_clock, 855 .set_engine_clock = &radeon_atom_set_engine_clock, 856 .get_memory_clock = &radeon_atom_get_memory_clock, 857 .set_memory_clock = &radeon_atom_set_memory_clock, 858 .get_pcie_lanes = &rv370_get_pcie_lanes, 859 .set_pcie_lanes = &rv370_set_pcie_lanes, 860 .set_clock_gating = &radeon_atom_set_clock_gating, 861 }, 862 .pflip = { 863 .page_flip = &rs600_page_flip, 864 .page_flip_pending = &rs600_page_flip_pending, 865 }, 866 }; 867 868 static struct radeon_asic_ring r600_gfx_ring = { 869 .ib_execute = &r600_ring_ib_execute, 870 .emit_fence = &r600_fence_ring_emit, 871 .emit_semaphore = &r600_semaphore_ring_emit, 872 .cs_parse = &r600_cs_parse, 873 .ring_test = &r600_ring_test, 874 .ib_test = &r600_ib_test, 875 .is_lockup = &r600_gfx_is_lockup, 876 .get_rptr = &r600_gfx_get_rptr, 877 .get_wptr = &r600_gfx_get_wptr, 878 .set_wptr = &r600_gfx_set_wptr, 879 }; 880 881 static struct radeon_asic_ring r600_dma_ring = { 882 .ib_execute = &r600_dma_ring_ib_execute, 883 .emit_fence = &r600_dma_fence_ring_emit, 884 .emit_semaphore = &r600_dma_semaphore_ring_emit, 885 .cs_parse = &r600_dma_cs_parse, 886 .ring_test = &r600_dma_ring_test, 887 .ib_test = &r600_dma_ib_test, 888 .is_lockup = &r600_dma_is_lockup, 889 .get_rptr = &r600_dma_get_rptr, 890 .get_wptr = &r600_dma_get_wptr, 891 .set_wptr = &r600_dma_set_wptr, 892 }; 893 894 static struct radeon_asic r600_asic = { 895 .init = &r600_init, 896 .fini = &r600_fini, 897 .suspend = &r600_suspend, 898 .resume = &r600_resume, 899 .vga_set_state = &r600_vga_set_state, 900 .asic_reset = &r600_asic_reset, 901 .mmio_hdp_flush = r600_mmio_hdp_flush, 902 .gui_idle = &r600_gui_idle, 903 .mc_wait_for_idle = &r600_mc_wait_for_idle, 904 .get_xclk = &r600_get_xclk, 905 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 906 .gart = { 907 .tlb_flush = &r600_pcie_gart_tlb_flush, 908 .set_page = &rs600_gart_set_page, 909 }, 910 .ring = { 911 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, 912 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, 913 }, 914 .irq = { 915 .set = &r600_irq_set, 916 .process = &r600_irq_process, 917 }, 918 .display = { 919 .bandwidth_update = &rv515_bandwidth_update, 920 .get_vblank_counter = &rs600_get_vblank_counter, 921 .wait_for_vblank = &avivo_wait_for_vblank, 922 .set_backlight_level = &atombios_set_backlight_level, 923 .get_backlight_level = &atombios_get_backlight_level, 924 .hdmi_enable = &r600_hdmi_enable, 925 .hdmi_setmode = &r600_hdmi_setmode, 926 }, 927 .copy = { 928 .blit = &r600_copy_cpdma, 929 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 930 .dma = &r600_copy_dma, 931 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 932 .copy = &r600_copy_cpdma, 933 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 934 }, 935 .surface = { 936 .set_reg = r600_set_surface_reg, 937 .clear_reg = r600_clear_surface_reg, 938 }, 939 .hpd = { 940 .init = &r600_hpd_init, 941 .fini = &r600_hpd_fini, 942 .sense = &r600_hpd_sense, 943 .set_polarity = &r600_hpd_set_polarity, 944 }, 945 .pm = { 946 .misc = &r600_pm_misc, 947 .prepare = &rs600_pm_prepare, 948 .finish = &rs600_pm_finish, 949 .init_profile = &r600_pm_init_profile, 950 .get_dynpm_state = &r600_pm_get_dynpm_state, 951 .get_engine_clock = &radeon_atom_get_engine_clock, 952 .set_engine_clock = &radeon_atom_set_engine_clock, 953 .get_memory_clock = &radeon_atom_get_memory_clock, 954 .set_memory_clock = &radeon_atom_set_memory_clock, 955 .get_pcie_lanes = &r600_get_pcie_lanes, 956 .set_pcie_lanes = &r600_set_pcie_lanes, 957 .set_clock_gating = NULL, 958 .get_temperature = &rv6xx_get_temp, 959 }, 960 .pflip = { 961 .page_flip = &rs600_page_flip, 962 .page_flip_pending = &rs600_page_flip_pending, 963 }, 964 }; 965 966 static struct radeon_asic rv6xx_asic = { 967 .init = &r600_init, 968 .fini = &r600_fini, 969 .suspend = &r600_suspend, 970 .resume = &r600_resume, 971 .vga_set_state = &r600_vga_set_state, 972 .asic_reset = &r600_asic_reset, 973 .mmio_hdp_flush = r600_mmio_hdp_flush, 974 .gui_idle = &r600_gui_idle, 975 .mc_wait_for_idle = &r600_mc_wait_for_idle, 976 .get_xclk = &r600_get_xclk, 977 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 978 .gart = { 979 .tlb_flush = &r600_pcie_gart_tlb_flush, 980 .set_page = &rs600_gart_set_page, 981 }, 982 .ring = { 983 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, 984 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, 985 }, 986 .irq = { 987 .set = &r600_irq_set, 988 .process = &r600_irq_process, 989 }, 990 .display = { 991 .bandwidth_update = &rv515_bandwidth_update, 992 .get_vblank_counter = &rs600_get_vblank_counter, 993 .wait_for_vblank = &avivo_wait_for_vblank, 994 .set_backlight_level = &atombios_set_backlight_level, 995 .get_backlight_level = &atombios_get_backlight_level, 996 .hdmi_enable = &r600_hdmi_enable, 997 .hdmi_setmode = &r600_hdmi_setmode, 998 }, 999 .copy = { 1000 .blit = &r600_copy_cpdma, 1001 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1002 .dma = &r600_copy_dma, 1003 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1004 .copy = &r600_copy_cpdma, 1005 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1006 }, 1007 .surface = { 1008 .set_reg = r600_set_surface_reg, 1009 .clear_reg = r600_clear_surface_reg, 1010 }, 1011 .hpd = { 1012 .init = &r600_hpd_init, 1013 .fini = &r600_hpd_fini, 1014 .sense = &r600_hpd_sense, 1015 .set_polarity = &r600_hpd_set_polarity, 1016 }, 1017 .pm = { 1018 .misc = &r600_pm_misc, 1019 .prepare = &rs600_pm_prepare, 1020 .finish = &rs600_pm_finish, 1021 .init_profile = &r600_pm_init_profile, 1022 .get_dynpm_state = &r600_pm_get_dynpm_state, 1023 .get_engine_clock = &radeon_atom_get_engine_clock, 1024 .set_engine_clock = &radeon_atom_set_engine_clock, 1025 .get_memory_clock = &radeon_atom_get_memory_clock, 1026 .set_memory_clock = &radeon_atom_set_memory_clock, 1027 .get_pcie_lanes = &r600_get_pcie_lanes, 1028 .set_pcie_lanes = &r600_set_pcie_lanes, 1029 .set_clock_gating = NULL, 1030 .get_temperature = &rv6xx_get_temp, 1031 .set_uvd_clocks = &r600_set_uvd_clocks, 1032 }, 1033 .dpm = { 1034 .init = &rv6xx_dpm_init, 1035 .setup_asic = &rv6xx_setup_asic, 1036 .enable = &rv6xx_dpm_enable, 1037 .late_enable = &r600_dpm_late_enable, 1038 .disable = &rv6xx_dpm_disable, 1039 .pre_set_power_state = &r600_dpm_pre_set_power_state, 1040 .set_power_state = &rv6xx_dpm_set_power_state, 1041 .post_set_power_state = &r600_dpm_post_set_power_state, 1042 .display_configuration_changed = &rv6xx_dpm_display_configuration_changed, 1043 .fini = &rv6xx_dpm_fini, 1044 .get_sclk = &rv6xx_dpm_get_sclk, 1045 .get_mclk = &rv6xx_dpm_get_mclk, 1046 .print_power_state = &rv6xx_dpm_print_power_state, 1047 .debugfs_print_current_performance_level = &rv6xx_dpm_debugfs_print_current_performance_level, 1048 .force_performance_level = &rv6xx_dpm_force_performance_level, 1049 }, 1050 .pflip = { 1051 .page_flip = &rs600_page_flip, 1052 .page_flip_pending = &rs600_page_flip_pending, 1053 }, 1054 }; 1055 1056 static struct radeon_asic rs780_asic = { 1057 .init = &r600_init, 1058 .fini = &r600_fini, 1059 .suspend = &r600_suspend, 1060 .resume = &r600_resume, 1061 .vga_set_state = &r600_vga_set_state, 1062 .asic_reset = &r600_asic_reset, 1063 .mmio_hdp_flush = r600_mmio_hdp_flush, 1064 .gui_idle = &r600_gui_idle, 1065 .mc_wait_for_idle = &r600_mc_wait_for_idle, 1066 .get_xclk = &r600_get_xclk, 1067 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1068 .gart = { 1069 .tlb_flush = &r600_pcie_gart_tlb_flush, 1070 .set_page = &rs600_gart_set_page, 1071 }, 1072 .ring = { 1073 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, 1074 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, 1075 }, 1076 .irq = { 1077 .set = &r600_irq_set, 1078 .process = &r600_irq_process, 1079 }, 1080 .display = { 1081 .bandwidth_update = &rs690_bandwidth_update, 1082 .get_vblank_counter = &rs600_get_vblank_counter, 1083 .wait_for_vblank = &avivo_wait_for_vblank, 1084 .set_backlight_level = &atombios_set_backlight_level, 1085 .get_backlight_level = &atombios_get_backlight_level, 1086 .hdmi_enable = &r600_hdmi_enable, 1087 .hdmi_setmode = &r600_hdmi_setmode, 1088 }, 1089 .copy = { 1090 .blit = &r600_copy_cpdma, 1091 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1092 .dma = &r600_copy_dma, 1093 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1094 .copy = &r600_copy_cpdma, 1095 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1096 }, 1097 .surface = { 1098 .set_reg = r600_set_surface_reg, 1099 .clear_reg = r600_clear_surface_reg, 1100 }, 1101 .hpd = { 1102 .init = &r600_hpd_init, 1103 .fini = &r600_hpd_fini, 1104 .sense = &r600_hpd_sense, 1105 .set_polarity = &r600_hpd_set_polarity, 1106 }, 1107 .pm = { 1108 .misc = &r600_pm_misc, 1109 .prepare = &rs600_pm_prepare, 1110 .finish = &rs600_pm_finish, 1111 .init_profile = &rs780_pm_init_profile, 1112 .get_dynpm_state = &r600_pm_get_dynpm_state, 1113 .get_engine_clock = &radeon_atom_get_engine_clock, 1114 .set_engine_clock = &radeon_atom_set_engine_clock, 1115 .get_memory_clock = NULL, 1116 .set_memory_clock = NULL, 1117 .get_pcie_lanes = NULL, 1118 .set_pcie_lanes = NULL, 1119 .set_clock_gating = NULL, 1120 .get_temperature = &rv6xx_get_temp, 1121 .set_uvd_clocks = &r600_set_uvd_clocks, 1122 }, 1123 .dpm = { 1124 .init = &rs780_dpm_init, 1125 .setup_asic = &rs780_dpm_setup_asic, 1126 .enable = &rs780_dpm_enable, 1127 .late_enable = &r600_dpm_late_enable, 1128 .disable = &rs780_dpm_disable, 1129 .pre_set_power_state = &r600_dpm_pre_set_power_state, 1130 .set_power_state = &rs780_dpm_set_power_state, 1131 .post_set_power_state = &r600_dpm_post_set_power_state, 1132 .display_configuration_changed = &rs780_dpm_display_configuration_changed, 1133 .fini = &rs780_dpm_fini, 1134 .get_sclk = &rs780_dpm_get_sclk, 1135 .get_mclk = &rs780_dpm_get_mclk, 1136 .print_power_state = &rs780_dpm_print_power_state, 1137 .debugfs_print_current_performance_level = &rs780_dpm_debugfs_print_current_performance_level, 1138 .force_performance_level = &rs780_dpm_force_performance_level, 1139 }, 1140 .pflip = { 1141 .page_flip = &rs600_page_flip, 1142 .page_flip_pending = &rs600_page_flip_pending, 1143 }, 1144 }; 1145 1146 static struct radeon_asic_ring rv770_uvd_ring = { 1147 .ib_execute = &uvd_v1_0_ib_execute, 1148 .emit_fence = &uvd_v2_2_fence_emit, 1149 .emit_semaphore = &uvd_v1_0_semaphore_emit, 1150 .cs_parse = &radeon_uvd_cs_parse, 1151 .ring_test = &uvd_v1_0_ring_test, 1152 .ib_test = &uvd_v1_0_ib_test, 1153 .is_lockup = &radeon_ring_test_lockup, 1154 .get_rptr = &uvd_v1_0_get_rptr, 1155 .get_wptr = &uvd_v1_0_get_wptr, 1156 .set_wptr = &uvd_v1_0_set_wptr, 1157 }; 1158 1159 static struct radeon_asic rv770_asic = { 1160 .init = &rv770_init, 1161 .fini = &rv770_fini, 1162 .suspend = &rv770_suspend, 1163 .resume = &rv770_resume, 1164 .asic_reset = &r600_asic_reset, 1165 .vga_set_state = &r600_vga_set_state, 1166 .mmio_hdp_flush = r600_mmio_hdp_flush, 1167 .gui_idle = &r600_gui_idle, 1168 .mc_wait_for_idle = &r600_mc_wait_for_idle, 1169 .get_xclk = &rv770_get_xclk, 1170 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1171 .gart = { 1172 .tlb_flush = &r600_pcie_gart_tlb_flush, 1173 .set_page = &rs600_gart_set_page, 1174 }, 1175 .ring = { 1176 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, 1177 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, 1178 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring, 1179 }, 1180 .irq = { 1181 .set = &r600_irq_set, 1182 .process = &r600_irq_process, 1183 }, 1184 .display = { 1185 .bandwidth_update = &rv515_bandwidth_update, 1186 .get_vblank_counter = &rs600_get_vblank_counter, 1187 .wait_for_vblank = &avivo_wait_for_vblank, 1188 .set_backlight_level = &atombios_set_backlight_level, 1189 .get_backlight_level = &atombios_get_backlight_level, 1190 .hdmi_enable = &r600_hdmi_enable, 1191 .hdmi_setmode = &dce3_1_hdmi_setmode, 1192 }, 1193 .copy = { 1194 .blit = &r600_copy_cpdma, 1195 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1196 .dma = &rv770_copy_dma, 1197 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1198 .copy = &rv770_copy_dma, 1199 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1200 }, 1201 .surface = { 1202 .set_reg = r600_set_surface_reg, 1203 .clear_reg = r600_clear_surface_reg, 1204 }, 1205 .hpd = { 1206 .init = &r600_hpd_init, 1207 .fini = &r600_hpd_fini, 1208 .sense = &r600_hpd_sense, 1209 .set_polarity = &r600_hpd_set_polarity, 1210 }, 1211 .pm = { 1212 .misc = &rv770_pm_misc, 1213 .prepare = &rs600_pm_prepare, 1214 .finish = &rs600_pm_finish, 1215 .init_profile = &r600_pm_init_profile, 1216 .get_dynpm_state = &r600_pm_get_dynpm_state, 1217 .get_engine_clock = &radeon_atom_get_engine_clock, 1218 .set_engine_clock = &radeon_atom_set_engine_clock, 1219 .get_memory_clock = &radeon_atom_get_memory_clock, 1220 .set_memory_clock = &radeon_atom_set_memory_clock, 1221 .get_pcie_lanes = &r600_get_pcie_lanes, 1222 .set_pcie_lanes = &r600_set_pcie_lanes, 1223 .set_clock_gating = &radeon_atom_set_clock_gating, 1224 .set_uvd_clocks = &rv770_set_uvd_clocks, 1225 .get_temperature = &rv770_get_temp, 1226 }, 1227 .dpm = { 1228 .init = &rv770_dpm_init, 1229 .setup_asic = &rv770_dpm_setup_asic, 1230 .enable = &rv770_dpm_enable, 1231 .late_enable = &rv770_dpm_late_enable, 1232 .disable = &rv770_dpm_disable, 1233 .pre_set_power_state = &r600_dpm_pre_set_power_state, 1234 .set_power_state = &rv770_dpm_set_power_state, 1235 .post_set_power_state = &r600_dpm_post_set_power_state, 1236 .display_configuration_changed = &rv770_dpm_display_configuration_changed, 1237 .fini = &rv770_dpm_fini, 1238 .get_sclk = &rv770_dpm_get_sclk, 1239 .get_mclk = &rv770_dpm_get_mclk, 1240 .print_power_state = &rv770_dpm_print_power_state, 1241 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level, 1242 .force_performance_level = &rv770_dpm_force_performance_level, 1243 .vblank_too_short = &rv770_dpm_vblank_too_short, 1244 }, 1245 .pflip = { 1246 .page_flip = &rv770_page_flip, 1247 .page_flip_pending = &rv770_page_flip_pending, 1248 }, 1249 }; 1250 1251 static struct radeon_asic_ring evergreen_gfx_ring = { 1252 .ib_execute = &evergreen_ring_ib_execute, 1253 .emit_fence = &r600_fence_ring_emit, 1254 .emit_semaphore = &r600_semaphore_ring_emit, 1255 .cs_parse = &evergreen_cs_parse, 1256 .ring_test = &r600_ring_test, 1257 .ib_test = &r600_ib_test, 1258 .is_lockup = &evergreen_gfx_is_lockup, 1259 .get_rptr = &r600_gfx_get_rptr, 1260 .get_wptr = &r600_gfx_get_wptr, 1261 .set_wptr = &r600_gfx_set_wptr, 1262 }; 1263 1264 static struct radeon_asic_ring evergreen_dma_ring = { 1265 .ib_execute = &evergreen_dma_ring_ib_execute, 1266 .emit_fence = &evergreen_dma_fence_ring_emit, 1267 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1268 .cs_parse = &evergreen_dma_cs_parse, 1269 .ring_test = &r600_dma_ring_test, 1270 .ib_test = &r600_dma_ib_test, 1271 .is_lockup = &evergreen_dma_is_lockup, 1272 .get_rptr = &r600_dma_get_rptr, 1273 .get_wptr = &r600_dma_get_wptr, 1274 .set_wptr = &r600_dma_set_wptr, 1275 }; 1276 1277 static struct radeon_asic evergreen_asic = { 1278 .init = &evergreen_init, 1279 .fini = &evergreen_fini, 1280 .suspend = &evergreen_suspend, 1281 .resume = &evergreen_resume, 1282 .asic_reset = &evergreen_asic_reset, 1283 .vga_set_state = &r600_vga_set_state, 1284 .mmio_hdp_flush = r600_mmio_hdp_flush, 1285 .gui_idle = &r600_gui_idle, 1286 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1287 .get_xclk = &rv770_get_xclk, 1288 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1289 .gart = { 1290 .tlb_flush = &evergreen_pcie_gart_tlb_flush, 1291 .set_page = &rs600_gart_set_page, 1292 }, 1293 .ring = { 1294 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring, 1295 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring, 1296 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring, 1297 }, 1298 .irq = { 1299 .set = &evergreen_irq_set, 1300 .process = &evergreen_irq_process, 1301 }, 1302 .display = { 1303 .bandwidth_update = &evergreen_bandwidth_update, 1304 .get_vblank_counter = &evergreen_get_vblank_counter, 1305 .wait_for_vblank = &dce4_wait_for_vblank, 1306 .set_backlight_level = &atombios_set_backlight_level, 1307 .get_backlight_level = &atombios_get_backlight_level, 1308 .hdmi_enable = &evergreen_hdmi_enable, 1309 .hdmi_setmode = &evergreen_hdmi_setmode, 1310 }, 1311 .copy = { 1312 .blit = &r600_copy_cpdma, 1313 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1314 .dma = &evergreen_copy_dma, 1315 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1316 .copy = &evergreen_copy_dma, 1317 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1318 }, 1319 .surface = { 1320 .set_reg = r600_set_surface_reg, 1321 .clear_reg = r600_clear_surface_reg, 1322 }, 1323 .hpd = { 1324 .init = &evergreen_hpd_init, 1325 .fini = &evergreen_hpd_fini, 1326 .sense = &evergreen_hpd_sense, 1327 .set_polarity = &evergreen_hpd_set_polarity, 1328 }, 1329 .pm = { 1330 .misc = &evergreen_pm_misc, 1331 .prepare = &evergreen_pm_prepare, 1332 .finish = &evergreen_pm_finish, 1333 .init_profile = &r600_pm_init_profile, 1334 .get_dynpm_state = &r600_pm_get_dynpm_state, 1335 .get_engine_clock = &radeon_atom_get_engine_clock, 1336 .set_engine_clock = &radeon_atom_set_engine_clock, 1337 .get_memory_clock = &radeon_atom_get_memory_clock, 1338 .set_memory_clock = &radeon_atom_set_memory_clock, 1339 .get_pcie_lanes = &r600_get_pcie_lanes, 1340 .set_pcie_lanes = &r600_set_pcie_lanes, 1341 .set_clock_gating = NULL, 1342 .set_uvd_clocks = &evergreen_set_uvd_clocks, 1343 .get_temperature = &evergreen_get_temp, 1344 }, 1345 .dpm = { 1346 .init = &cypress_dpm_init, 1347 .setup_asic = &cypress_dpm_setup_asic, 1348 .enable = &cypress_dpm_enable, 1349 .late_enable = &rv770_dpm_late_enable, 1350 .disable = &cypress_dpm_disable, 1351 .pre_set_power_state = &r600_dpm_pre_set_power_state, 1352 .set_power_state = &cypress_dpm_set_power_state, 1353 .post_set_power_state = &r600_dpm_post_set_power_state, 1354 .display_configuration_changed = &cypress_dpm_display_configuration_changed, 1355 .fini = &cypress_dpm_fini, 1356 .get_sclk = &rv770_dpm_get_sclk, 1357 .get_mclk = &rv770_dpm_get_mclk, 1358 .print_power_state = &rv770_dpm_print_power_state, 1359 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level, 1360 .force_performance_level = &rv770_dpm_force_performance_level, 1361 .vblank_too_short = &cypress_dpm_vblank_too_short, 1362 }, 1363 .pflip = { 1364 .page_flip = &evergreen_page_flip, 1365 .page_flip_pending = &evergreen_page_flip_pending, 1366 }, 1367 }; 1368 1369 static struct radeon_asic sumo_asic = { 1370 .init = &evergreen_init, 1371 .fini = &evergreen_fini, 1372 .suspend = &evergreen_suspend, 1373 .resume = &evergreen_resume, 1374 .asic_reset = &evergreen_asic_reset, 1375 .vga_set_state = &r600_vga_set_state, 1376 .mmio_hdp_flush = r600_mmio_hdp_flush, 1377 .gui_idle = &r600_gui_idle, 1378 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1379 .get_xclk = &r600_get_xclk, 1380 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1381 .gart = { 1382 .tlb_flush = &evergreen_pcie_gart_tlb_flush, 1383 .set_page = &rs600_gart_set_page, 1384 }, 1385 .ring = { 1386 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring, 1387 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring, 1388 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring, 1389 }, 1390 .irq = { 1391 .set = &evergreen_irq_set, 1392 .process = &evergreen_irq_process, 1393 }, 1394 .display = { 1395 .bandwidth_update = &evergreen_bandwidth_update, 1396 .get_vblank_counter = &evergreen_get_vblank_counter, 1397 .wait_for_vblank = &dce4_wait_for_vblank, 1398 .set_backlight_level = &atombios_set_backlight_level, 1399 .get_backlight_level = &atombios_get_backlight_level, 1400 .hdmi_enable = &evergreen_hdmi_enable, 1401 .hdmi_setmode = &evergreen_hdmi_setmode, 1402 }, 1403 .copy = { 1404 .blit = &r600_copy_cpdma, 1405 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1406 .dma = &evergreen_copy_dma, 1407 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1408 .copy = &evergreen_copy_dma, 1409 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1410 }, 1411 .surface = { 1412 .set_reg = r600_set_surface_reg, 1413 .clear_reg = r600_clear_surface_reg, 1414 }, 1415 .hpd = { 1416 .init = &evergreen_hpd_init, 1417 .fini = &evergreen_hpd_fini, 1418 .sense = &evergreen_hpd_sense, 1419 .set_polarity = &evergreen_hpd_set_polarity, 1420 }, 1421 .pm = { 1422 .misc = &evergreen_pm_misc, 1423 .prepare = &evergreen_pm_prepare, 1424 .finish = &evergreen_pm_finish, 1425 .init_profile = &sumo_pm_init_profile, 1426 .get_dynpm_state = &r600_pm_get_dynpm_state, 1427 .get_engine_clock = &radeon_atom_get_engine_clock, 1428 .set_engine_clock = &radeon_atom_set_engine_clock, 1429 .get_memory_clock = NULL, 1430 .set_memory_clock = NULL, 1431 .get_pcie_lanes = NULL, 1432 .set_pcie_lanes = NULL, 1433 .set_clock_gating = NULL, 1434 .set_uvd_clocks = &sumo_set_uvd_clocks, 1435 .get_temperature = &sumo_get_temp, 1436 }, 1437 .dpm = { 1438 .init = &sumo_dpm_init, 1439 .setup_asic = &sumo_dpm_setup_asic, 1440 .enable = &sumo_dpm_enable, 1441 .late_enable = &sumo_dpm_late_enable, 1442 .disable = &sumo_dpm_disable, 1443 .pre_set_power_state = &sumo_dpm_pre_set_power_state, 1444 .set_power_state = &sumo_dpm_set_power_state, 1445 .post_set_power_state = &sumo_dpm_post_set_power_state, 1446 .display_configuration_changed = &sumo_dpm_display_configuration_changed, 1447 .fini = &sumo_dpm_fini, 1448 .get_sclk = &sumo_dpm_get_sclk, 1449 .get_mclk = &sumo_dpm_get_mclk, 1450 .print_power_state = &sumo_dpm_print_power_state, 1451 .debugfs_print_current_performance_level = &sumo_dpm_debugfs_print_current_performance_level, 1452 .force_performance_level = &sumo_dpm_force_performance_level, 1453 }, 1454 .pflip = { 1455 .page_flip = &evergreen_page_flip, 1456 .page_flip_pending = &evergreen_page_flip_pending, 1457 }, 1458 }; 1459 1460 static struct radeon_asic btc_asic = { 1461 .init = &evergreen_init, 1462 .fini = &evergreen_fini, 1463 .suspend = &evergreen_suspend, 1464 .resume = &evergreen_resume, 1465 .asic_reset = &evergreen_asic_reset, 1466 .vga_set_state = &r600_vga_set_state, 1467 .mmio_hdp_flush = r600_mmio_hdp_flush, 1468 .gui_idle = &r600_gui_idle, 1469 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1470 .get_xclk = &rv770_get_xclk, 1471 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1472 .gart = { 1473 .tlb_flush = &evergreen_pcie_gart_tlb_flush, 1474 .set_page = &rs600_gart_set_page, 1475 }, 1476 .ring = { 1477 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring, 1478 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring, 1479 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring, 1480 }, 1481 .irq = { 1482 .set = &evergreen_irq_set, 1483 .process = &evergreen_irq_process, 1484 }, 1485 .display = { 1486 .bandwidth_update = &evergreen_bandwidth_update, 1487 .get_vblank_counter = &evergreen_get_vblank_counter, 1488 .wait_for_vblank = &dce4_wait_for_vblank, 1489 .set_backlight_level = &atombios_set_backlight_level, 1490 .get_backlight_level = &atombios_get_backlight_level, 1491 .hdmi_enable = &evergreen_hdmi_enable, 1492 .hdmi_setmode = &evergreen_hdmi_setmode, 1493 }, 1494 .copy = { 1495 .blit = &r600_copy_cpdma, 1496 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1497 .dma = &evergreen_copy_dma, 1498 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1499 .copy = &evergreen_copy_dma, 1500 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1501 }, 1502 .surface = { 1503 .set_reg = r600_set_surface_reg, 1504 .clear_reg = r600_clear_surface_reg, 1505 }, 1506 .hpd = { 1507 .init = &evergreen_hpd_init, 1508 .fini = &evergreen_hpd_fini, 1509 .sense = &evergreen_hpd_sense, 1510 .set_polarity = &evergreen_hpd_set_polarity, 1511 }, 1512 .pm = { 1513 .misc = &evergreen_pm_misc, 1514 .prepare = &evergreen_pm_prepare, 1515 .finish = &evergreen_pm_finish, 1516 .init_profile = &btc_pm_init_profile, 1517 .get_dynpm_state = &r600_pm_get_dynpm_state, 1518 .get_engine_clock = &radeon_atom_get_engine_clock, 1519 .set_engine_clock = &radeon_atom_set_engine_clock, 1520 .get_memory_clock = &radeon_atom_get_memory_clock, 1521 .set_memory_clock = &radeon_atom_set_memory_clock, 1522 .get_pcie_lanes = &r600_get_pcie_lanes, 1523 .set_pcie_lanes = &r600_set_pcie_lanes, 1524 .set_clock_gating = NULL, 1525 .set_uvd_clocks = &evergreen_set_uvd_clocks, 1526 .get_temperature = &evergreen_get_temp, 1527 }, 1528 .dpm = { 1529 .init = &btc_dpm_init, 1530 .setup_asic = &btc_dpm_setup_asic, 1531 .enable = &btc_dpm_enable, 1532 .late_enable = &rv770_dpm_late_enable, 1533 .disable = &btc_dpm_disable, 1534 .pre_set_power_state = &btc_dpm_pre_set_power_state, 1535 .set_power_state = &btc_dpm_set_power_state, 1536 .post_set_power_state = &btc_dpm_post_set_power_state, 1537 .display_configuration_changed = &cypress_dpm_display_configuration_changed, 1538 .fini = &btc_dpm_fini, 1539 .get_sclk = &btc_dpm_get_sclk, 1540 .get_mclk = &btc_dpm_get_mclk, 1541 .print_power_state = &rv770_dpm_print_power_state, 1542 .debugfs_print_current_performance_level = &btc_dpm_debugfs_print_current_performance_level, 1543 .force_performance_level = &rv770_dpm_force_performance_level, 1544 .vblank_too_short = &btc_dpm_vblank_too_short, 1545 }, 1546 .pflip = { 1547 .page_flip = &evergreen_page_flip, 1548 .page_flip_pending = &evergreen_page_flip_pending, 1549 }, 1550 }; 1551 1552 static struct radeon_asic_ring cayman_gfx_ring = { 1553 .ib_execute = &cayman_ring_ib_execute, 1554 .ib_parse = &evergreen_ib_parse, 1555 .emit_fence = &cayman_fence_ring_emit, 1556 .emit_semaphore = &r600_semaphore_ring_emit, 1557 .cs_parse = &evergreen_cs_parse, 1558 .ring_test = &r600_ring_test, 1559 .ib_test = &r600_ib_test, 1560 .is_lockup = &cayman_gfx_is_lockup, 1561 .vm_flush = &cayman_vm_flush, 1562 .get_rptr = &cayman_gfx_get_rptr, 1563 .get_wptr = &cayman_gfx_get_wptr, 1564 .set_wptr = &cayman_gfx_set_wptr, 1565 }; 1566 1567 static struct radeon_asic_ring cayman_dma_ring = { 1568 .ib_execute = &cayman_dma_ring_ib_execute, 1569 .ib_parse = &evergreen_dma_ib_parse, 1570 .emit_fence = &evergreen_dma_fence_ring_emit, 1571 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1572 .cs_parse = &evergreen_dma_cs_parse, 1573 .ring_test = &r600_dma_ring_test, 1574 .ib_test = &r600_dma_ib_test, 1575 .is_lockup = &cayman_dma_is_lockup, 1576 .vm_flush = &cayman_dma_vm_flush, 1577 .get_rptr = &cayman_dma_get_rptr, 1578 .get_wptr = &cayman_dma_get_wptr, 1579 .set_wptr = &cayman_dma_set_wptr 1580 }; 1581 1582 static struct radeon_asic_ring cayman_uvd_ring = { 1583 .ib_execute = &uvd_v1_0_ib_execute, 1584 .emit_fence = &uvd_v2_2_fence_emit, 1585 .emit_semaphore = &uvd_v3_1_semaphore_emit, 1586 .cs_parse = &radeon_uvd_cs_parse, 1587 .ring_test = &uvd_v1_0_ring_test, 1588 .ib_test = &uvd_v1_0_ib_test, 1589 .is_lockup = &radeon_ring_test_lockup, 1590 .get_rptr = &uvd_v1_0_get_rptr, 1591 .get_wptr = &uvd_v1_0_get_wptr, 1592 .set_wptr = &uvd_v1_0_set_wptr, 1593 }; 1594 1595 static struct radeon_asic cayman_asic = { 1596 .init = &cayman_init, 1597 .fini = &cayman_fini, 1598 .suspend = &cayman_suspend, 1599 .resume = &cayman_resume, 1600 .asic_reset = &cayman_asic_reset, 1601 .vga_set_state = &r600_vga_set_state, 1602 .mmio_hdp_flush = r600_mmio_hdp_flush, 1603 .gui_idle = &r600_gui_idle, 1604 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1605 .get_xclk = &rv770_get_xclk, 1606 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1607 .gart = { 1608 .tlb_flush = &cayman_pcie_gart_tlb_flush, 1609 .set_page = &rs600_gart_set_page, 1610 }, 1611 .vm = { 1612 .init = &cayman_vm_init, 1613 .fini = &cayman_vm_fini, 1614 .copy_pages = &cayman_dma_vm_copy_pages, 1615 .write_pages = &cayman_dma_vm_write_pages, 1616 .set_pages = &cayman_dma_vm_set_pages, 1617 .pad_ib = &cayman_dma_vm_pad_ib, 1618 }, 1619 .ring = { 1620 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring, 1621 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring, 1622 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring, 1623 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring, 1624 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring, 1625 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, 1626 }, 1627 .irq = { 1628 .set = &evergreen_irq_set, 1629 .process = &evergreen_irq_process, 1630 }, 1631 .display = { 1632 .bandwidth_update = &evergreen_bandwidth_update, 1633 .get_vblank_counter = &evergreen_get_vblank_counter, 1634 .wait_for_vblank = &dce4_wait_for_vblank, 1635 .set_backlight_level = &atombios_set_backlight_level, 1636 .get_backlight_level = &atombios_get_backlight_level, 1637 .hdmi_enable = &evergreen_hdmi_enable, 1638 .hdmi_setmode = &evergreen_hdmi_setmode, 1639 }, 1640 .copy = { 1641 .blit = &r600_copy_cpdma, 1642 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1643 .dma = &evergreen_copy_dma, 1644 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1645 .copy = &evergreen_copy_dma, 1646 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1647 }, 1648 .surface = { 1649 .set_reg = r600_set_surface_reg, 1650 .clear_reg = r600_clear_surface_reg, 1651 }, 1652 .hpd = { 1653 .init = &evergreen_hpd_init, 1654 .fini = &evergreen_hpd_fini, 1655 .sense = &evergreen_hpd_sense, 1656 .set_polarity = &evergreen_hpd_set_polarity, 1657 }, 1658 .pm = { 1659 .misc = &evergreen_pm_misc, 1660 .prepare = &evergreen_pm_prepare, 1661 .finish = &evergreen_pm_finish, 1662 .init_profile = &btc_pm_init_profile, 1663 .get_dynpm_state = &r600_pm_get_dynpm_state, 1664 .get_engine_clock = &radeon_atom_get_engine_clock, 1665 .set_engine_clock = &radeon_atom_set_engine_clock, 1666 .get_memory_clock = &radeon_atom_get_memory_clock, 1667 .set_memory_clock = &radeon_atom_set_memory_clock, 1668 .get_pcie_lanes = &r600_get_pcie_lanes, 1669 .set_pcie_lanes = &r600_set_pcie_lanes, 1670 .set_clock_gating = NULL, 1671 .set_uvd_clocks = &evergreen_set_uvd_clocks, 1672 .get_temperature = &evergreen_get_temp, 1673 }, 1674 .dpm = { 1675 .init = &ni_dpm_init, 1676 .setup_asic = &ni_dpm_setup_asic, 1677 .enable = &ni_dpm_enable, 1678 .late_enable = &rv770_dpm_late_enable, 1679 .disable = &ni_dpm_disable, 1680 .pre_set_power_state = &ni_dpm_pre_set_power_state, 1681 .set_power_state = &ni_dpm_set_power_state, 1682 .post_set_power_state = &ni_dpm_post_set_power_state, 1683 .display_configuration_changed = &cypress_dpm_display_configuration_changed, 1684 .fini = &ni_dpm_fini, 1685 .get_sclk = &ni_dpm_get_sclk, 1686 .get_mclk = &ni_dpm_get_mclk, 1687 .print_power_state = &ni_dpm_print_power_state, 1688 .debugfs_print_current_performance_level = &ni_dpm_debugfs_print_current_performance_level, 1689 .force_performance_level = &ni_dpm_force_performance_level, 1690 .vblank_too_short = &ni_dpm_vblank_too_short, 1691 }, 1692 .pflip = { 1693 .page_flip = &evergreen_page_flip, 1694 .page_flip_pending = &evergreen_page_flip_pending, 1695 }, 1696 }; 1697 1698 static struct radeon_asic trinity_asic = { 1699 .init = &cayman_init, 1700 .fini = &cayman_fini, 1701 .suspend = &cayman_suspend, 1702 .resume = &cayman_resume, 1703 .asic_reset = &cayman_asic_reset, 1704 .vga_set_state = &r600_vga_set_state, 1705 .mmio_hdp_flush = r600_mmio_hdp_flush, 1706 .gui_idle = &r600_gui_idle, 1707 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1708 .get_xclk = &r600_get_xclk, 1709 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1710 .gart = { 1711 .tlb_flush = &cayman_pcie_gart_tlb_flush, 1712 .set_page = &rs600_gart_set_page, 1713 }, 1714 .vm = { 1715 .init = &cayman_vm_init, 1716 .fini = &cayman_vm_fini, 1717 .copy_pages = &cayman_dma_vm_copy_pages, 1718 .write_pages = &cayman_dma_vm_write_pages, 1719 .set_pages = &cayman_dma_vm_set_pages, 1720 .pad_ib = &cayman_dma_vm_pad_ib, 1721 }, 1722 .ring = { 1723 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring, 1724 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring, 1725 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring, 1726 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring, 1727 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring, 1728 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, 1729 }, 1730 .irq = { 1731 .set = &evergreen_irq_set, 1732 .process = &evergreen_irq_process, 1733 }, 1734 .display = { 1735 .bandwidth_update = &dce6_bandwidth_update, 1736 .get_vblank_counter = &evergreen_get_vblank_counter, 1737 .wait_for_vblank = &dce4_wait_for_vblank, 1738 .set_backlight_level = &atombios_set_backlight_level, 1739 .get_backlight_level = &atombios_get_backlight_level, 1740 .hdmi_enable = &evergreen_hdmi_enable, 1741 .hdmi_setmode = &evergreen_hdmi_setmode, 1742 }, 1743 .copy = { 1744 .blit = &r600_copy_cpdma, 1745 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1746 .dma = &evergreen_copy_dma, 1747 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1748 .copy = &evergreen_copy_dma, 1749 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1750 }, 1751 .surface = { 1752 .set_reg = r600_set_surface_reg, 1753 .clear_reg = r600_clear_surface_reg, 1754 }, 1755 .hpd = { 1756 .init = &evergreen_hpd_init, 1757 .fini = &evergreen_hpd_fini, 1758 .sense = &evergreen_hpd_sense, 1759 .set_polarity = &evergreen_hpd_set_polarity, 1760 }, 1761 .pm = { 1762 .misc = &evergreen_pm_misc, 1763 .prepare = &evergreen_pm_prepare, 1764 .finish = &evergreen_pm_finish, 1765 .init_profile = &sumo_pm_init_profile, 1766 .get_dynpm_state = &r600_pm_get_dynpm_state, 1767 .get_engine_clock = &radeon_atom_get_engine_clock, 1768 .set_engine_clock = &radeon_atom_set_engine_clock, 1769 .get_memory_clock = NULL, 1770 .set_memory_clock = NULL, 1771 .get_pcie_lanes = NULL, 1772 .set_pcie_lanes = NULL, 1773 .set_clock_gating = NULL, 1774 .set_uvd_clocks = &sumo_set_uvd_clocks, 1775 .get_temperature = &tn_get_temp, 1776 }, 1777 .dpm = { 1778 .init = &trinity_dpm_init, 1779 .setup_asic = &trinity_dpm_setup_asic, 1780 .enable = &trinity_dpm_enable, 1781 .late_enable = &trinity_dpm_late_enable, 1782 .disable = &trinity_dpm_disable, 1783 .pre_set_power_state = &trinity_dpm_pre_set_power_state, 1784 .set_power_state = &trinity_dpm_set_power_state, 1785 .post_set_power_state = &trinity_dpm_post_set_power_state, 1786 .display_configuration_changed = &trinity_dpm_display_configuration_changed, 1787 .fini = &trinity_dpm_fini, 1788 .get_sclk = &trinity_dpm_get_sclk, 1789 .get_mclk = &trinity_dpm_get_mclk, 1790 .print_power_state = &trinity_dpm_print_power_state, 1791 .debugfs_print_current_performance_level = &trinity_dpm_debugfs_print_current_performance_level, 1792 .force_performance_level = &trinity_dpm_force_performance_level, 1793 .enable_bapm = &trinity_dpm_enable_bapm, 1794 }, 1795 .pflip = { 1796 .page_flip = &evergreen_page_flip, 1797 .page_flip_pending = &evergreen_page_flip_pending, 1798 }, 1799 }; 1800 1801 static struct radeon_asic_ring si_gfx_ring = { 1802 .ib_execute = &si_ring_ib_execute, 1803 .ib_parse = &si_ib_parse, 1804 .emit_fence = &si_fence_ring_emit, 1805 .emit_semaphore = &r600_semaphore_ring_emit, 1806 .cs_parse = NULL, 1807 .ring_test = &r600_ring_test, 1808 .ib_test = &r600_ib_test, 1809 .is_lockup = &si_gfx_is_lockup, 1810 .vm_flush = &si_vm_flush, 1811 .get_rptr = &cayman_gfx_get_rptr, 1812 .get_wptr = &cayman_gfx_get_wptr, 1813 .set_wptr = &cayman_gfx_set_wptr, 1814 }; 1815 1816 static struct radeon_asic_ring si_dma_ring = { 1817 .ib_execute = &cayman_dma_ring_ib_execute, 1818 .ib_parse = &evergreen_dma_ib_parse, 1819 .emit_fence = &evergreen_dma_fence_ring_emit, 1820 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1821 .cs_parse = NULL, 1822 .ring_test = &r600_dma_ring_test, 1823 .ib_test = &r600_dma_ib_test, 1824 .is_lockup = &si_dma_is_lockup, 1825 .vm_flush = &si_dma_vm_flush, 1826 .get_rptr = &cayman_dma_get_rptr, 1827 .get_wptr = &cayman_dma_get_wptr, 1828 .set_wptr = &cayman_dma_set_wptr, 1829 }; 1830 1831 static struct radeon_asic si_asic = { 1832 .init = &si_init, 1833 .fini = &si_fini, 1834 .suspend = &si_suspend, 1835 .resume = &si_resume, 1836 .asic_reset = &si_asic_reset, 1837 .vga_set_state = &r600_vga_set_state, 1838 .mmio_hdp_flush = r600_mmio_hdp_flush, 1839 .gui_idle = &r600_gui_idle, 1840 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1841 .get_xclk = &si_get_xclk, 1842 .get_gpu_clock_counter = &si_get_gpu_clock_counter, 1843 .gart = { 1844 .tlb_flush = &si_pcie_gart_tlb_flush, 1845 .set_page = &rs600_gart_set_page, 1846 }, 1847 .vm = { 1848 .init = &si_vm_init, 1849 .fini = &si_vm_fini, 1850 .copy_pages = &si_dma_vm_copy_pages, 1851 .write_pages = &si_dma_vm_write_pages, 1852 .set_pages = &si_dma_vm_set_pages, 1853 .pad_ib = &cayman_dma_vm_pad_ib, 1854 }, 1855 .ring = { 1856 [RADEON_RING_TYPE_GFX_INDEX] = &si_gfx_ring, 1857 [CAYMAN_RING_TYPE_CP1_INDEX] = &si_gfx_ring, 1858 [CAYMAN_RING_TYPE_CP2_INDEX] = &si_gfx_ring, 1859 [R600_RING_TYPE_DMA_INDEX] = &si_dma_ring, 1860 [CAYMAN_RING_TYPE_DMA1_INDEX] = &si_dma_ring, 1861 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, 1862 }, 1863 .irq = { 1864 .set = &si_irq_set, 1865 .process = &si_irq_process, 1866 }, 1867 .display = { 1868 .bandwidth_update = &dce6_bandwidth_update, 1869 .get_vblank_counter = &evergreen_get_vblank_counter, 1870 .wait_for_vblank = &dce4_wait_for_vblank, 1871 .set_backlight_level = &atombios_set_backlight_level, 1872 .get_backlight_level = &atombios_get_backlight_level, 1873 .hdmi_enable = &evergreen_hdmi_enable, 1874 .hdmi_setmode = &evergreen_hdmi_setmode, 1875 }, 1876 .copy = { 1877 .blit = &r600_copy_cpdma, 1878 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1879 .dma = &si_copy_dma, 1880 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1881 .copy = &si_copy_dma, 1882 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1883 }, 1884 .surface = { 1885 .set_reg = r600_set_surface_reg, 1886 .clear_reg = r600_clear_surface_reg, 1887 }, 1888 .hpd = { 1889 .init = &evergreen_hpd_init, 1890 .fini = &evergreen_hpd_fini, 1891 .sense = &evergreen_hpd_sense, 1892 .set_polarity = &evergreen_hpd_set_polarity, 1893 }, 1894 .pm = { 1895 .misc = &evergreen_pm_misc, 1896 .prepare = &evergreen_pm_prepare, 1897 .finish = &evergreen_pm_finish, 1898 .init_profile = &sumo_pm_init_profile, 1899 .get_dynpm_state = &r600_pm_get_dynpm_state, 1900 .get_engine_clock = &radeon_atom_get_engine_clock, 1901 .set_engine_clock = &radeon_atom_set_engine_clock, 1902 .get_memory_clock = &radeon_atom_get_memory_clock, 1903 .set_memory_clock = &radeon_atom_set_memory_clock, 1904 .get_pcie_lanes = &r600_get_pcie_lanes, 1905 .set_pcie_lanes = &r600_set_pcie_lanes, 1906 .set_clock_gating = NULL, 1907 .set_uvd_clocks = &si_set_uvd_clocks, 1908 .get_temperature = &si_get_temp, 1909 }, 1910 .dpm = { 1911 .init = &si_dpm_init, 1912 .setup_asic = &si_dpm_setup_asic, 1913 .enable = &si_dpm_enable, 1914 .late_enable = &si_dpm_late_enable, 1915 .disable = &si_dpm_disable, 1916 .pre_set_power_state = &si_dpm_pre_set_power_state, 1917 .set_power_state = &si_dpm_set_power_state, 1918 .post_set_power_state = &si_dpm_post_set_power_state, 1919 .display_configuration_changed = &si_dpm_display_configuration_changed, 1920 .fini = &si_dpm_fini, 1921 .get_sclk = &ni_dpm_get_sclk, 1922 .get_mclk = &ni_dpm_get_mclk, 1923 .print_power_state = &ni_dpm_print_power_state, 1924 .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level, 1925 .force_performance_level = &si_dpm_force_performance_level, 1926 .vblank_too_short = &ni_dpm_vblank_too_short, 1927 }, 1928 .pflip = { 1929 .page_flip = &evergreen_page_flip, 1930 .page_flip_pending = &evergreen_page_flip_pending, 1931 }, 1932 }; 1933 1934 static struct radeon_asic_ring ci_gfx_ring = { 1935 .ib_execute = &cik_ring_ib_execute, 1936 .ib_parse = &cik_ib_parse, 1937 .emit_fence = &cik_fence_gfx_ring_emit, 1938 .emit_semaphore = &cik_semaphore_ring_emit, 1939 .cs_parse = NULL, 1940 .ring_test = &cik_ring_test, 1941 .ib_test = &cik_ib_test, 1942 .is_lockup = &cik_gfx_is_lockup, 1943 .vm_flush = &cik_vm_flush, 1944 .get_rptr = &cik_gfx_get_rptr, 1945 .get_wptr = &cik_gfx_get_wptr, 1946 .set_wptr = &cik_gfx_set_wptr, 1947 }; 1948 1949 static struct radeon_asic_ring ci_cp_ring = { 1950 .ib_execute = &cik_ring_ib_execute, 1951 .ib_parse = &cik_ib_parse, 1952 .emit_fence = &cik_fence_compute_ring_emit, 1953 .emit_semaphore = &cik_semaphore_ring_emit, 1954 .cs_parse = NULL, 1955 .ring_test = &cik_ring_test, 1956 .ib_test = &cik_ib_test, 1957 .is_lockup = &cik_gfx_is_lockup, 1958 .vm_flush = &cik_vm_flush, 1959 .get_rptr = &cik_compute_get_rptr, 1960 .get_wptr = &cik_compute_get_wptr, 1961 .set_wptr = &cik_compute_set_wptr, 1962 }; 1963 1964 static struct radeon_asic_ring ci_dma_ring = { 1965 .ib_execute = &cik_sdma_ring_ib_execute, 1966 .ib_parse = &cik_ib_parse, 1967 .emit_fence = &cik_sdma_fence_ring_emit, 1968 .emit_semaphore = &cik_sdma_semaphore_ring_emit, 1969 .cs_parse = NULL, 1970 .ring_test = &cik_sdma_ring_test, 1971 .ib_test = &cik_sdma_ib_test, 1972 .is_lockup = &cik_sdma_is_lockup, 1973 .vm_flush = &cik_dma_vm_flush, 1974 .get_rptr = &cik_sdma_get_rptr, 1975 .get_wptr = &cik_sdma_get_wptr, 1976 .set_wptr = &cik_sdma_set_wptr, 1977 }; 1978 1979 static struct radeon_asic_ring ci_vce_ring = { 1980 .ib_execute = &radeon_vce_ib_execute, 1981 .emit_fence = &radeon_vce_fence_emit, 1982 .emit_semaphore = &radeon_vce_semaphore_emit, 1983 .cs_parse = &radeon_vce_cs_parse, 1984 .ring_test = &radeon_vce_ring_test, 1985 .ib_test = &radeon_vce_ib_test, 1986 .is_lockup = &radeon_ring_test_lockup, 1987 .get_rptr = &vce_v1_0_get_rptr, 1988 .get_wptr = &vce_v1_0_get_wptr, 1989 .set_wptr = &vce_v1_0_set_wptr, 1990 }; 1991 1992 static struct radeon_asic ci_asic = { 1993 .init = &cik_init, 1994 .fini = &cik_fini, 1995 .suspend = &cik_suspend, 1996 .resume = &cik_resume, 1997 .asic_reset = &cik_asic_reset, 1998 .vga_set_state = &r600_vga_set_state, 1999 .mmio_hdp_flush = &r600_mmio_hdp_flush, 2000 .gui_idle = &r600_gui_idle, 2001 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 2002 .get_xclk = &cik_get_xclk, 2003 .get_gpu_clock_counter = &cik_get_gpu_clock_counter, 2004 .gart = { 2005 .tlb_flush = &cik_pcie_gart_tlb_flush, 2006 .set_page = &rs600_gart_set_page, 2007 }, 2008 .vm = { 2009 .init = &cik_vm_init, 2010 .fini = &cik_vm_fini, 2011 .copy_pages = &cik_sdma_vm_copy_pages, 2012 .write_pages = &cik_sdma_vm_write_pages, 2013 .set_pages = &cik_sdma_vm_set_pages, 2014 .pad_ib = &cik_sdma_vm_pad_ib, 2015 }, 2016 .ring = { 2017 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring, 2018 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring, 2019 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring, 2020 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring, 2021 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring, 2022 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, 2023 [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring, 2024 [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring, 2025 }, 2026 .irq = { 2027 .set = &cik_irq_set, 2028 .process = &cik_irq_process, 2029 }, 2030 .display = { 2031 .bandwidth_update = &dce8_bandwidth_update, 2032 .get_vblank_counter = &evergreen_get_vblank_counter, 2033 .wait_for_vblank = &dce4_wait_for_vblank, 2034 .set_backlight_level = &atombios_set_backlight_level, 2035 .get_backlight_level = &atombios_get_backlight_level, 2036 .hdmi_enable = &evergreen_hdmi_enable, 2037 .hdmi_setmode = &evergreen_hdmi_setmode, 2038 }, 2039 .copy = { 2040 .blit = &cik_copy_cpdma, 2041 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 2042 .dma = &cik_copy_dma, 2043 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 2044 .copy = &cik_copy_dma, 2045 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 2046 }, 2047 .surface = { 2048 .set_reg = r600_set_surface_reg, 2049 .clear_reg = r600_clear_surface_reg, 2050 }, 2051 .hpd = { 2052 .init = &evergreen_hpd_init, 2053 .fini = &evergreen_hpd_fini, 2054 .sense = &evergreen_hpd_sense, 2055 .set_polarity = &evergreen_hpd_set_polarity, 2056 }, 2057 .pm = { 2058 .misc = &evergreen_pm_misc, 2059 .prepare = &evergreen_pm_prepare, 2060 .finish = &evergreen_pm_finish, 2061 .init_profile = &sumo_pm_init_profile, 2062 .get_dynpm_state = &r600_pm_get_dynpm_state, 2063 .get_engine_clock = &radeon_atom_get_engine_clock, 2064 .set_engine_clock = &radeon_atom_set_engine_clock, 2065 .get_memory_clock = &radeon_atom_get_memory_clock, 2066 .set_memory_clock = &radeon_atom_set_memory_clock, 2067 .get_pcie_lanes = NULL, 2068 .set_pcie_lanes = NULL, 2069 .set_clock_gating = NULL, 2070 .set_uvd_clocks = &cik_set_uvd_clocks, 2071 .set_vce_clocks = &cik_set_vce_clocks, 2072 .get_temperature = &ci_get_temp, 2073 }, 2074 .dpm = { 2075 .init = &ci_dpm_init, 2076 .setup_asic = &ci_dpm_setup_asic, 2077 .enable = &ci_dpm_enable, 2078 .late_enable = &ci_dpm_late_enable, 2079 .disable = &ci_dpm_disable, 2080 .pre_set_power_state = &ci_dpm_pre_set_power_state, 2081 .set_power_state = &ci_dpm_set_power_state, 2082 .post_set_power_state = &ci_dpm_post_set_power_state, 2083 .display_configuration_changed = &ci_dpm_display_configuration_changed, 2084 .fini = &ci_dpm_fini, 2085 .get_sclk = &ci_dpm_get_sclk, 2086 .get_mclk = &ci_dpm_get_mclk, 2087 .print_power_state = &ci_dpm_print_power_state, 2088 .debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level, 2089 .force_performance_level = &ci_dpm_force_performance_level, 2090 .vblank_too_short = &ci_dpm_vblank_too_short, 2091 .powergate_uvd = &ci_dpm_powergate_uvd, 2092 }, 2093 .pflip = { 2094 .page_flip = &evergreen_page_flip, 2095 .page_flip_pending = &evergreen_page_flip_pending, 2096 }, 2097 }; 2098 2099 static struct radeon_asic kv_asic = { 2100 .init = &cik_init, 2101 .fini = &cik_fini, 2102 .suspend = &cik_suspend, 2103 .resume = &cik_resume, 2104 .asic_reset = &cik_asic_reset, 2105 .vga_set_state = &r600_vga_set_state, 2106 .mmio_hdp_flush = &r600_mmio_hdp_flush, 2107 .gui_idle = &r600_gui_idle, 2108 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 2109 .get_xclk = &cik_get_xclk, 2110 .get_gpu_clock_counter = &cik_get_gpu_clock_counter, 2111 .gart = { 2112 .tlb_flush = &cik_pcie_gart_tlb_flush, 2113 .set_page = &rs600_gart_set_page, 2114 }, 2115 .vm = { 2116 .init = &cik_vm_init, 2117 .fini = &cik_vm_fini, 2118 .copy_pages = &cik_sdma_vm_copy_pages, 2119 .write_pages = &cik_sdma_vm_write_pages, 2120 .set_pages = &cik_sdma_vm_set_pages, 2121 .pad_ib = &cik_sdma_vm_pad_ib, 2122 }, 2123 .ring = { 2124 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring, 2125 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring, 2126 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring, 2127 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring, 2128 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring, 2129 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, 2130 [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring, 2131 [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring, 2132 }, 2133 .irq = { 2134 .set = &cik_irq_set, 2135 .process = &cik_irq_process, 2136 }, 2137 .display = { 2138 .bandwidth_update = &dce8_bandwidth_update, 2139 .get_vblank_counter = &evergreen_get_vblank_counter, 2140 .wait_for_vblank = &dce4_wait_for_vblank, 2141 .set_backlight_level = &atombios_set_backlight_level, 2142 .get_backlight_level = &atombios_get_backlight_level, 2143 .hdmi_enable = &evergreen_hdmi_enable, 2144 .hdmi_setmode = &evergreen_hdmi_setmode, 2145 }, 2146 .copy = { 2147 .blit = &cik_copy_cpdma, 2148 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 2149 .dma = &cik_copy_dma, 2150 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 2151 .copy = &cik_copy_dma, 2152 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 2153 }, 2154 .surface = { 2155 .set_reg = r600_set_surface_reg, 2156 .clear_reg = r600_clear_surface_reg, 2157 }, 2158 .hpd = { 2159 .init = &evergreen_hpd_init, 2160 .fini = &evergreen_hpd_fini, 2161 .sense = &evergreen_hpd_sense, 2162 .set_polarity = &evergreen_hpd_set_polarity, 2163 }, 2164 .pm = { 2165 .misc = &evergreen_pm_misc, 2166 .prepare = &evergreen_pm_prepare, 2167 .finish = &evergreen_pm_finish, 2168 .init_profile = &sumo_pm_init_profile, 2169 .get_dynpm_state = &r600_pm_get_dynpm_state, 2170 .get_engine_clock = &radeon_atom_get_engine_clock, 2171 .set_engine_clock = &radeon_atom_set_engine_clock, 2172 .get_memory_clock = &radeon_atom_get_memory_clock, 2173 .set_memory_clock = &radeon_atom_set_memory_clock, 2174 .get_pcie_lanes = NULL, 2175 .set_pcie_lanes = NULL, 2176 .set_clock_gating = NULL, 2177 .set_uvd_clocks = &cik_set_uvd_clocks, 2178 .set_vce_clocks = &cik_set_vce_clocks, 2179 .get_temperature = &kv_get_temp, 2180 }, 2181 .dpm = { 2182 .init = &kv_dpm_init, 2183 .setup_asic = &kv_dpm_setup_asic, 2184 .enable = &kv_dpm_enable, 2185 .late_enable = &kv_dpm_late_enable, 2186 .disable = &kv_dpm_disable, 2187 .pre_set_power_state = &kv_dpm_pre_set_power_state, 2188 .set_power_state = &kv_dpm_set_power_state, 2189 .post_set_power_state = &kv_dpm_post_set_power_state, 2190 .display_configuration_changed = &kv_dpm_display_configuration_changed, 2191 .fini = &kv_dpm_fini, 2192 .get_sclk = &kv_dpm_get_sclk, 2193 .get_mclk = &kv_dpm_get_mclk, 2194 .print_power_state = &kv_dpm_print_power_state, 2195 .debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level, 2196 .force_performance_level = &kv_dpm_force_performance_level, 2197 .powergate_uvd = &kv_dpm_powergate_uvd, 2198 .enable_bapm = &kv_dpm_enable_bapm, 2199 }, 2200 .pflip = { 2201 .page_flip = &evergreen_page_flip, 2202 .page_flip_pending = &evergreen_page_flip_pending, 2203 }, 2204 }; 2205 2206 /** 2207 * radeon_asic_init - register asic specific callbacks 2208 * 2209 * @rdev: radeon device pointer 2210 * 2211 * Registers the appropriate asic specific callbacks for each 2212 * chip family. Also sets other asics specific info like the number 2213 * of crtcs and the register aperture accessors (all asics). 2214 * Returns 0 for success. 2215 */ 2216 int radeon_asic_init(struct radeon_device *rdev) 2217 { 2218 radeon_register_accessor_init(rdev); 2219 2220 /* set the number of crtcs */ 2221 if (rdev->flags & RADEON_SINGLE_CRTC) 2222 rdev->num_crtc = 1; 2223 else 2224 rdev->num_crtc = 2; 2225 2226 rdev->has_uvd = false; 2227 2228 switch (rdev->family) { 2229 case CHIP_R100: 2230 case CHIP_RV100: 2231 case CHIP_RS100: 2232 case CHIP_RV200: 2233 case CHIP_RS200: 2234 rdev->asic = &r100_asic; 2235 break; 2236 case CHIP_R200: 2237 case CHIP_RV250: 2238 case CHIP_RS300: 2239 case CHIP_RV280: 2240 rdev->asic = &r200_asic; 2241 break; 2242 case CHIP_R300: 2243 case CHIP_R350: 2244 case CHIP_RV350: 2245 case CHIP_RV380: 2246 if (rdev->flags & RADEON_IS_PCIE) 2247 rdev->asic = &r300_asic_pcie; 2248 else 2249 rdev->asic = &r300_asic; 2250 break; 2251 case CHIP_R420: 2252 case CHIP_R423: 2253 case CHIP_RV410: 2254 rdev->asic = &r420_asic; 2255 /* handle macs */ 2256 if (rdev->bios == NULL) { 2257 rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock; 2258 rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock; 2259 rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock; 2260 rdev->asic->pm.set_memory_clock = NULL; 2261 rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level; 2262 } 2263 break; 2264 case CHIP_RS400: 2265 case CHIP_RS480: 2266 rdev->asic = &rs400_asic; 2267 break; 2268 case CHIP_RS600: 2269 rdev->asic = &rs600_asic; 2270 break; 2271 case CHIP_RS690: 2272 case CHIP_RS740: 2273 rdev->asic = &rs690_asic; 2274 break; 2275 case CHIP_RV515: 2276 rdev->asic = &rv515_asic; 2277 break; 2278 case CHIP_R520: 2279 case CHIP_RV530: 2280 case CHIP_RV560: 2281 case CHIP_RV570: 2282 case CHIP_R580: 2283 rdev->asic = &r520_asic; 2284 break; 2285 case CHIP_R600: 2286 rdev->asic = &r600_asic; 2287 break; 2288 case CHIP_RV610: 2289 case CHIP_RV630: 2290 case CHIP_RV620: 2291 case CHIP_RV635: 2292 case CHIP_RV670: 2293 rdev->asic = &rv6xx_asic; 2294 rdev->has_uvd = true; 2295 break; 2296 case CHIP_RS780: 2297 case CHIP_RS880: 2298 rdev->asic = &rs780_asic; 2299 rdev->has_uvd = true; 2300 break; 2301 case CHIP_RV770: 2302 case CHIP_RV730: 2303 case CHIP_RV710: 2304 case CHIP_RV740: 2305 rdev->asic = &rv770_asic; 2306 rdev->has_uvd = true; 2307 break; 2308 case CHIP_CEDAR: 2309 case CHIP_REDWOOD: 2310 case CHIP_JUNIPER: 2311 case CHIP_CYPRESS: 2312 case CHIP_HEMLOCK: 2313 /* set num crtcs */ 2314 if (rdev->family == CHIP_CEDAR) 2315 rdev->num_crtc = 4; 2316 else 2317 rdev->num_crtc = 6; 2318 rdev->asic = &evergreen_asic; 2319 rdev->has_uvd = true; 2320 break; 2321 case CHIP_PALM: 2322 case CHIP_SUMO: 2323 case CHIP_SUMO2: 2324 rdev->asic = &sumo_asic; 2325 rdev->has_uvd = true; 2326 break; 2327 case CHIP_BARTS: 2328 case CHIP_TURKS: 2329 case CHIP_CAICOS: 2330 /* set num crtcs */ 2331 if (rdev->family == CHIP_CAICOS) 2332 rdev->num_crtc = 4; 2333 else 2334 rdev->num_crtc = 6; 2335 rdev->asic = &btc_asic; 2336 rdev->has_uvd = true; 2337 break; 2338 case CHIP_CAYMAN: 2339 rdev->asic = &cayman_asic; 2340 /* set num crtcs */ 2341 rdev->num_crtc = 6; 2342 rdev->has_uvd = true; 2343 break; 2344 case CHIP_ARUBA: 2345 rdev->asic = &trinity_asic; 2346 /* set num crtcs */ 2347 rdev->num_crtc = 4; 2348 rdev->has_uvd = true; 2349 break; 2350 case CHIP_TAHITI: 2351 case CHIP_PITCAIRN: 2352 case CHIP_VERDE: 2353 case CHIP_OLAND: 2354 case CHIP_HAINAN: 2355 rdev->asic = &si_asic; 2356 /* set num crtcs */ 2357 if (rdev->family == CHIP_HAINAN) 2358 rdev->num_crtc = 0; 2359 else if (rdev->family == CHIP_OLAND) 2360 rdev->num_crtc = 2; 2361 else 2362 rdev->num_crtc = 6; 2363 if (rdev->family == CHIP_HAINAN) 2364 rdev->has_uvd = false; 2365 else 2366 rdev->has_uvd = true; 2367 switch (rdev->family) { 2368 case CHIP_TAHITI: 2369 rdev->cg_flags = 2370 RADEON_CG_SUPPORT_GFX_MGCG | 2371 RADEON_CG_SUPPORT_GFX_MGLS | 2372 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2373 RADEON_CG_SUPPORT_GFX_CGLS | 2374 RADEON_CG_SUPPORT_GFX_CGTS | 2375 RADEON_CG_SUPPORT_GFX_CP_LS | 2376 RADEON_CG_SUPPORT_MC_MGCG | 2377 RADEON_CG_SUPPORT_SDMA_MGCG | 2378 RADEON_CG_SUPPORT_BIF_LS | 2379 RADEON_CG_SUPPORT_VCE_MGCG | 2380 RADEON_CG_SUPPORT_UVD_MGCG | 2381 RADEON_CG_SUPPORT_HDP_LS | 2382 RADEON_CG_SUPPORT_HDP_MGCG; 2383 rdev->pg_flags = 0; 2384 break; 2385 case CHIP_PITCAIRN: 2386 rdev->cg_flags = 2387 RADEON_CG_SUPPORT_GFX_MGCG | 2388 RADEON_CG_SUPPORT_GFX_MGLS | 2389 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2390 RADEON_CG_SUPPORT_GFX_CGLS | 2391 RADEON_CG_SUPPORT_GFX_CGTS | 2392 RADEON_CG_SUPPORT_GFX_CP_LS | 2393 RADEON_CG_SUPPORT_GFX_RLC_LS | 2394 RADEON_CG_SUPPORT_MC_LS | 2395 RADEON_CG_SUPPORT_MC_MGCG | 2396 RADEON_CG_SUPPORT_SDMA_MGCG | 2397 RADEON_CG_SUPPORT_BIF_LS | 2398 RADEON_CG_SUPPORT_VCE_MGCG | 2399 RADEON_CG_SUPPORT_UVD_MGCG | 2400 RADEON_CG_SUPPORT_HDP_LS | 2401 RADEON_CG_SUPPORT_HDP_MGCG; 2402 rdev->pg_flags = 0; 2403 break; 2404 case CHIP_VERDE: 2405 rdev->cg_flags = 2406 RADEON_CG_SUPPORT_GFX_MGCG | 2407 RADEON_CG_SUPPORT_GFX_MGLS | 2408 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2409 RADEON_CG_SUPPORT_GFX_CGLS | 2410 RADEON_CG_SUPPORT_GFX_CGTS | 2411 RADEON_CG_SUPPORT_GFX_CP_LS | 2412 RADEON_CG_SUPPORT_GFX_RLC_LS | 2413 RADEON_CG_SUPPORT_MC_LS | 2414 RADEON_CG_SUPPORT_MC_MGCG | 2415 RADEON_CG_SUPPORT_SDMA_MGCG | 2416 RADEON_CG_SUPPORT_BIF_LS | 2417 RADEON_CG_SUPPORT_VCE_MGCG | 2418 RADEON_CG_SUPPORT_UVD_MGCG | 2419 RADEON_CG_SUPPORT_HDP_LS | 2420 RADEON_CG_SUPPORT_HDP_MGCG; 2421 rdev->pg_flags = 0 | 2422 /*RADEON_PG_SUPPORT_GFX_PG | */ 2423 RADEON_PG_SUPPORT_SDMA; 2424 break; 2425 case CHIP_OLAND: 2426 rdev->cg_flags = 2427 RADEON_CG_SUPPORT_GFX_MGCG | 2428 RADEON_CG_SUPPORT_GFX_MGLS | 2429 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2430 RADEON_CG_SUPPORT_GFX_CGLS | 2431 RADEON_CG_SUPPORT_GFX_CGTS | 2432 RADEON_CG_SUPPORT_GFX_CP_LS | 2433 RADEON_CG_SUPPORT_GFX_RLC_LS | 2434 RADEON_CG_SUPPORT_MC_LS | 2435 RADEON_CG_SUPPORT_MC_MGCG | 2436 RADEON_CG_SUPPORT_SDMA_MGCG | 2437 RADEON_CG_SUPPORT_BIF_LS | 2438 RADEON_CG_SUPPORT_UVD_MGCG | 2439 RADEON_CG_SUPPORT_HDP_LS | 2440 RADEON_CG_SUPPORT_HDP_MGCG; 2441 rdev->pg_flags = 0; 2442 break; 2443 case CHIP_HAINAN: 2444 rdev->cg_flags = 2445 RADEON_CG_SUPPORT_GFX_MGCG | 2446 RADEON_CG_SUPPORT_GFX_MGLS | 2447 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2448 RADEON_CG_SUPPORT_GFX_CGLS | 2449 RADEON_CG_SUPPORT_GFX_CGTS | 2450 RADEON_CG_SUPPORT_GFX_CP_LS | 2451 RADEON_CG_SUPPORT_GFX_RLC_LS | 2452 RADEON_CG_SUPPORT_MC_LS | 2453 RADEON_CG_SUPPORT_MC_MGCG | 2454 RADEON_CG_SUPPORT_SDMA_MGCG | 2455 RADEON_CG_SUPPORT_BIF_LS | 2456 RADEON_CG_SUPPORT_HDP_LS | 2457 RADEON_CG_SUPPORT_HDP_MGCG; 2458 rdev->pg_flags = 0; 2459 break; 2460 default: 2461 rdev->cg_flags = 0; 2462 rdev->pg_flags = 0; 2463 break; 2464 } 2465 break; 2466 case CHIP_BONAIRE: 2467 case CHIP_HAWAII: 2468 rdev->asic = &ci_asic; 2469 rdev->num_crtc = 6; 2470 rdev->has_uvd = true; 2471 if (rdev->family == CHIP_BONAIRE) { 2472 rdev->cg_flags = 2473 RADEON_CG_SUPPORT_GFX_MGCG | 2474 RADEON_CG_SUPPORT_GFX_MGLS | 2475 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2476 RADEON_CG_SUPPORT_GFX_CGLS | 2477 RADEON_CG_SUPPORT_GFX_CGTS | 2478 RADEON_CG_SUPPORT_GFX_CGTS_LS | 2479 RADEON_CG_SUPPORT_GFX_CP_LS | 2480 RADEON_CG_SUPPORT_MC_LS | 2481 RADEON_CG_SUPPORT_MC_MGCG | 2482 RADEON_CG_SUPPORT_SDMA_MGCG | 2483 RADEON_CG_SUPPORT_SDMA_LS | 2484 RADEON_CG_SUPPORT_BIF_LS | 2485 RADEON_CG_SUPPORT_VCE_MGCG | 2486 RADEON_CG_SUPPORT_UVD_MGCG | 2487 RADEON_CG_SUPPORT_HDP_LS | 2488 RADEON_CG_SUPPORT_HDP_MGCG; 2489 rdev->pg_flags = 0; 2490 } else { 2491 rdev->cg_flags = 2492 RADEON_CG_SUPPORT_GFX_MGCG | 2493 RADEON_CG_SUPPORT_GFX_MGLS | 2494 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2495 RADEON_CG_SUPPORT_GFX_CGLS | 2496 RADEON_CG_SUPPORT_GFX_CGTS | 2497 RADEON_CG_SUPPORT_GFX_CP_LS | 2498 RADEON_CG_SUPPORT_MC_LS | 2499 RADEON_CG_SUPPORT_MC_MGCG | 2500 RADEON_CG_SUPPORT_SDMA_MGCG | 2501 RADEON_CG_SUPPORT_SDMA_LS | 2502 RADEON_CG_SUPPORT_BIF_LS | 2503 RADEON_CG_SUPPORT_VCE_MGCG | 2504 RADEON_CG_SUPPORT_UVD_MGCG | 2505 RADEON_CG_SUPPORT_HDP_LS | 2506 RADEON_CG_SUPPORT_HDP_MGCG; 2507 rdev->pg_flags = 0; 2508 } 2509 break; 2510 case CHIP_KAVERI: 2511 case CHIP_KABINI: 2512 case CHIP_MULLINS: 2513 rdev->asic = &kv_asic; 2514 /* set num crtcs */ 2515 if (rdev->family == CHIP_KAVERI) { 2516 rdev->num_crtc = 4; 2517 rdev->cg_flags = 2518 RADEON_CG_SUPPORT_GFX_MGCG | 2519 RADEON_CG_SUPPORT_GFX_MGLS | 2520 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2521 RADEON_CG_SUPPORT_GFX_CGLS | 2522 RADEON_CG_SUPPORT_GFX_CGTS | 2523 RADEON_CG_SUPPORT_GFX_CGTS_LS | 2524 RADEON_CG_SUPPORT_GFX_CP_LS | 2525 RADEON_CG_SUPPORT_SDMA_MGCG | 2526 RADEON_CG_SUPPORT_SDMA_LS | 2527 RADEON_CG_SUPPORT_BIF_LS | 2528 RADEON_CG_SUPPORT_VCE_MGCG | 2529 RADEON_CG_SUPPORT_UVD_MGCG | 2530 RADEON_CG_SUPPORT_HDP_LS | 2531 RADEON_CG_SUPPORT_HDP_MGCG; 2532 rdev->pg_flags = 0; 2533 /*RADEON_PG_SUPPORT_GFX_PG | 2534 RADEON_PG_SUPPORT_GFX_SMG | 2535 RADEON_PG_SUPPORT_GFX_DMG | 2536 RADEON_PG_SUPPORT_UVD | 2537 RADEON_PG_SUPPORT_VCE | 2538 RADEON_PG_SUPPORT_CP | 2539 RADEON_PG_SUPPORT_GDS | 2540 RADEON_PG_SUPPORT_RLC_SMU_HS | 2541 RADEON_PG_SUPPORT_ACP | 2542 RADEON_PG_SUPPORT_SAMU;*/ 2543 } else { 2544 rdev->num_crtc = 2; 2545 rdev->cg_flags = 2546 RADEON_CG_SUPPORT_GFX_MGCG | 2547 RADEON_CG_SUPPORT_GFX_MGLS | 2548 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2549 RADEON_CG_SUPPORT_GFX_CGLS | 2550 RADEON_CG_SUPPORT_GFX_CGTS | 2551 RADEON_CG_SUPPORT_GFX_CGTS_LS | 2552 RADEON_CG_SUPPORT_GFX_CP_LS | 2553 RADEON_CG_SUPPORT_SDMA_MGCG | 2554 RADEON_CG_SUPPORT_SDMA_LS | 2555 RADEON_CG_SUPPORT_BIF_LS | 2556 RADEON_CG_SUPPORT_VCE_MGCG | 2557 RADEON_CG_SUPPORT_UVD_MGCG | 2558 RADEON_CG_SUPPORT_HDP_LS | 2559 RADEON_CG_SUPPORT_HDP_MGCG; 2560 rdev->pg_flags = 0; 2561 /*RADEON_PG_SUPPORT_GFX_PG | 2562 RADEON_PG_SUPPORT_GFX_SMG | 2563 RADEON_PG_SUPPORT_UVD | 2564 RADEON_PG_SUPPORT_VCE | 2565 RADEON_PG_SUPPORT_CP | 2566 RADEON_PG_SUPPORT_GDS | 2567 RADEON_PG_SUPPORT_RLC_SMU_HS | 2568 RADEON_PG_SUPPORT_SAMU;*/ 2569 } 2570 rdev->has_uvd = true; 2571 break; 2572 default: 2573 /* FIXME: not supported yet */ 2574 return -EINVAL; 2575 } 2576 2577 if (rdev->flags & RADEON_IS_IGP) { 2578 rdev->asic->pm.get_memory_clock = NULL; 2579 rdev->asic->pm.set_memory_clock = NULL; 2580 } 2581 2582 return 0; 2583 } 2584 2585