1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include <linux/console.h> 30 #include <drm/drmP.h> 31 #include <drm/drm_crtc_helper.h> 32 #include <drm/radeon_drm.h> 33 #include <linux/vgaarb.h> 34 #include <linux/vga_switcheroo.h> 35 #include "radeon_reg.h" 36 #include "radeon.h" 37 #include "radeon_asic.h" 38 #include "atom.h" 39 40 /* 41 * Registers accessors functions. 42 */ 43 /** 44 * radeon_invalid_rreg - dummy reg read function 45 * 46 * @rdev: radeon device pointer 47 * @reg: offset of register 48 * 49 * Dummy register read function. Used for register blocks 50 * that certain asics don't have (all asics). 51 * Returns the value in the register. 52 */ 53 static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg) 54 { 55 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); 56 BUG_ON(1); 57 return 0; 58 } 59 60 /** 61 * radeon_invalid_wreg - dummy reg write function 62 * 63 * @rdev: radeon device pointer 64 * @reg: offset of register 65 * @v: value to write to the register 66 * 67 * Dummy register read function. Used for register blocks 68 * that certain asics don't have (all asics). 69 */ 70 static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 71 { 72 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", 73 reg, v); 74 BUG_ON(1); 75 } 76 77 /** 78 * radeon_register_accessor_init - sets up the register accessor callbacks 79 * 80 * @rdev: radeon device pointer 81 * 82 * Sets up the register accessor callbacks for various register 83 * apertures. Not all asics have all apertures (all asics). 84 */ 85 static void radeon_register_accessor_init(struct radeon_device *rdev) 86 { 87 rdev->mc_rreg = &radeon_invalid_rreg; 88 rdev->mc_wreg = &radeon_invalid_wreg; 89 rdev->pll_rreg = &radeon_invalid_rreg; 90 rdev->pll_wreg = &radeon_invalid_wreg; 91 rdev->pciep_rreg = &radeon_invalid_rreg; 92 rdev->pciep_wreg = &radeon_invalid_wreg; 93 94 /* Don't change order as we are overridding accessor. */ 95 if (rdev->family < CHIP_RV515) { 96 rdev->pcie_reg_mask = 0xff; 97 } else { 98 rdev->pcie_reg_mask = 0x7ff; 99 } 100 /* FIXME: not sure here */ 101 if (rdev->family <= CHIP_R580) { 102 rdev->pll_rreg = &r100_pll_rreg; 103 rdev->pll_wreg = &r100_pll_wreg; 104 } 105 if (rdev->family >= CHIP_R420) { 106 rdev->mc_rreg = &r420_mc_rreg; 107 rdev->mc_wreg = &r420_mc_wreg; 108 } 109 if (rdev->family >= CHIP_RV515) { 110 rdev->mc_rreg = &rv515_mc_rreg; 111 rdev->mc_wreg = &rv515_mc_wreg; 112 } 113 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) { 114 rdev->mc_rreg = &rs400_mc_rreg; 115 rdev->mc_wreg = &rs400_mc_wreg; 116 } 117 if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { 118 rdev->mc_rreg = &rs690_mc_rreg; 119 rdev->mc_wreg = &rs690_mc_wreg; 120 } 121 if (rdev->family == CHIP_RS600) { 122 rdev->mc_rreg = &rs600_mc_rreg; 123 rdev->mc_wreg = &rs600_mc_wreg; 124 } 125 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) { 126 rdev->mc_rreg = &rs780_mc_rreg; 127 rdev->mc_wreg = &rs780_mc_wreg; 128 } 129 130 if (rdev->family >= CHIP_BONAIRE) { 131 rdev->pciep_rreg = &cik_pciep_rreg; 132 rdev->pciep_wreg = &cik_pciep_wreg; 133 } else if (rdev->family >= CHIP_R600) { 134 rdev->pciep_rreg = &r600_pciep_rreg; 135 rdev->pciep_wreg = &r600_pciep_wreg; 136 } 137 } 138 139 140 /* helper to disable agp */ 141 /** 142 * radeon_agp_disable - AGP disable helper function 143 * 144 * @rdev: radeon device pointer 145 * 146 * Removes AGP flags and changes the gart callbacks on AGP 147 * cards when using the internal gart rather than AGP (all asics). 148 */ 149 void radeon_agp_disable(struct radeon_device *rdev) 150 { 151 rdev->flags &= ~RADEON_IS_AGP; 152 if (rdev->family >= CHIP_R600) { 153 DRM_INFO("Forcing AGP to PCIE mode\n"); 154 rdev->flags |= RADEON_IS_PCIE; 155 } else if (rdev->family >= CHIP_RV515 || 156 rdev->family == CHIP_RV380 || 157 rdev->family == CHIP_RV410 || 158 rdev->family == CHIP_R423) { 159 DRM_INFO("Forcing AGP to PCIE mode\n"); 160 rdev->flags |= RADEON_IS_PCIE; 161 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush; 162 rdev->asic->gart.get_page_entry = &rv370_pcie_gart_get_page_entry; 163 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page; 164 } else { 165 DRM_INFO("Forcing AGP to PCI mode\n"); 166 rdev->flags |= RADEON_IS_PCI; 167 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush; 168 rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry; 169 rdev->asic->gart.set_page = &r100_pci_gart_set_page; 170 } 171 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; 172 } 173 174 /* 175 * ASIC 176 */ 177 178 static struct radeon_asic_ring r100_gfx_ring = { 179 .ib_execute = &r100_ring_ib_execute, 180 .emit_fence = &r100_fence_ring_emit, 181 .emit_semaphore = &r100_semaphore_ring_emit, 182 .cs_parse = &r100_cs_parse, 183 .ring_start = &r100_ring_start, 184 .ring_test = &r100_ring_test, 185 .ib_test = &r100_ib_test, 186 .is_lockup = &r100_gpu_is_lockup, 187 .get_rptr = &r100_gfx_get_rptr, 188 .get_wptr = &r100_gfx_get_wptr, 189 .set_wptr = &r100_gfx_set_wptr, 190 }; 191 192 static struct radeon_asic r100_asic = { 193 .init = &r100_init, 194 .fini = &r100_fini, 195 .suspend = &r100_suspend, 196 .resume = &r100_resume, 197 .vga_set_state = &r100_vga_set_state, 198 .asic_reset = &r100_asic_reset, 199 .mmio_hdp_flush = NULL, 200 .gui_idle = &r100_gui_idle, 201 .mc_wait_for_idle = &r100_mc_wait_for_idle, 202 .gart = { 203 .tlb_flush = &r100_pci_gart_tlb_flush, 204 .get_page_entry = &r100_pci_gart_get_page_entry, 205 .set_page = &r100_pci_gart_set_page, 206 }, 207 .ring = { 208 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring 209 }, 210 .irq = { 211 .set = &r100_irq_set, 212 .process = &r100_irq_process, 213 }, 214 .display = { 215 .bandwidth_update = &r100_bandwidth_update, 216 .get_vblank_counter = &r100_get_vblank_counter, 217 .wait_for_vblank = &r100_wait_for_vblank, 218 .set_backlight_level = &radeon_legacy_set_backlight_level, 219 .get_backlight_level = &radeon_legacy_get_backlight_level, 220 }, 221 .copy = { 222 .blit = &r100_copy_blit, 223 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 224 .dma = NULL, 225 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 226 .copy = &r100_copy_blit, 227 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 228 }, 229 .surface = { 230 .set_reg = r100_set_surface_reg, 231 .clear_reg = r100_clear_surface_reg, 232 }, 233 .hpd = { 234 .init = &r100_hpd_init, 235 .fini = &r100_hpd_fini, 236 .sense = &r100_hpd_sense, 237 .set_polarity = &r100_hpd_set_polarity, 238 }, 239 .pm = { 240 .misc = &r100_pm_misc, 241 .prepare = &r100_pm_prepare, 242 .finish = &r100_pm_finish, 243 .init_profile = &r100_pm_init_profile, 244 .get_dynpm_state = &r100_pm_get_dynpm_state, 245 .get_engine_clock = &radeon_legacy_get_engine_clock, 246 .set_engine_clock = &radeon_legacy_set_engine_clock, 247 .get_memory_clock = &radeon_legacy_get_memory_clock, 248 .set_memory_clock = NULL, 249 .get_pcie_lanes = NULL, 250 .set_pcie_lanes = NULL, 251 .set_clock_gating = &radeon_legacy_set_clock_gating, 252 }, 253 .pflip = { 254 .page_flip = &r100_page_flip, 255 .page_flip_pending = &r100_page_flip_pending, 256 }, 257 }; 258 259 static struct radeon_asic r200_asic = { 260 .init = &r100_init, 261 .fini = &r100_fini, 262 .suspend = &r100_suspend, 263 .resume = &r100_resume, 264 .vga_set_state = &r100_vga_set_state, 265 .asic_reset = &r100_asic_reset, 266 .mmio_hdp_flush = NULL, 267 .gui_idle = &r100_gui_idle, 268 .mc_wait_for_idle = &r100_mc_wait_for_idle, 269 .gart = { 270 .tlb_flush = &r100_pci_gart_tlb_flush, 271 .get_page_entry = &r100_pci_gart_get_page_entry, 272 .set_page = &r100_pci_gart_set_page, 273 }, 274 .ring = { 275 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring 276 }, 277 .irq = { 278 .set = &r100_irq_set, 279 .process = &r100_irq_process, 280 }, 281 .display = { 282 .bandwidth_update = &r100_bandwidth_update, 283 .get_vblank_counter = &r100_get_vblank_counter, 284 .wait_for_vblank = &r100_wait_for_vblank, 285 .set_backlight_level = &radeon_legacy_set_backlight_level, 286 .get_backlight_level = &radeon_legacy_get_backlight_level, 287 }, 288 .copy = { 289 .blit = &r100_copy_blit, 290 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 291 .dma = &r200_copy_dma, 292 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 293 .copy = &r100_copy_blit, 294 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 295 }, 296 .surface = { 297 .set_reg = r100_set_surface_reg, 298 .clear_reg = r100_clear_surface_reg, 299 }, 300 .hpd = { 301 .init = &r100_hpd_init, 302 .fini = &r100_hpd_fini, 303 .sense = &r100_hpd_sense, 304 .set_polarity = &r100_hpd_set_polarity, 305 }, 306 .pm = { 307 .misc = &r100_pm_misc, 308 .prepare = &r100_pm_prepare, 309 .finish = &r100_pm_finish, 310 .init_profile = &r100_pm_init_profile, 311 .get_dynpm_state = &r100_pm_get_dynpm_state, 312 .get_engine_clock = &radeon_legacy_get_engine_clock, 313 .set_engine_clock = &radeon_legacy_set_engine_clock, 314 .get_memory_clock = &radeon_legacy_get_memory_clock, 315 .set_memory_clock = NULL, 316 .get_pcie_lanes = NULL, 317 .set_pcie_lanes = NULL, 318 .set_clock_gating = &radeon_legacy_set_clock_gating, 319 }, 320 .pflip = { 321 .page_flip = &r100_page_flip, 322 .page_flip_pending = &r100_page_flip_pending, 323 }, 324 }; 325 326 static struct radeon_asic_ring r300_gfx_ring = { 327 .ib_execute = &r100_ring_ib_execute, 328 .emit_fence = &r300_fence_ring_emit, 329 .emit_semaphore = &r100_semaphore_ring_emit, 330 .cs_parse = &r300_cs_parse, 331 .ring_start = &r300_ring_start, 332 .ring_test = &r100_ring_test, 333 .ib_test = &r100_ib_test, 334 .is_lockup = &r100_gpu_is_lockup, 335 .get_rptr = &r100_gfx_get_rptr, 336 .get_wptr = &r100_gfx_get_wptr, 337 .set_wptr = &r100_gfx_set_wptr, 338 }; 339 340 static struct radeon_asic_ring rv515_gfx_ring = { 341 .ib_execute = &r100_ring_ib_execute, 342 .emit_fence = &r300_fence_ring_emit, 343 .emit_semaphore = &r100_semaphore_ring_emit, 344 .cs_parse = &r300_cs_parse, 345 .ring_start = &rv515_ring_start, 346 .ring_test = &r100_ring_test, 347 .ib_test = &r100_ib_test, 348 .is_lockup = &r100_gpu_is_lockup, 349 .get_rptr = &r100_gfx_get_rptr, 350 .get_wptr = &r100_gfx_get_wptr, 351 .set_wptr = &r100_gfx_set_wptr, 352 }; 353 354 static struct radeon_asic r300_asic = { 355 .init = &r300_init, 356 .fini = &r300_fini, 357 .suspend = &r300_suspend, 358 .resume = &r300_resume, 359 .vga_set_state = &r100_vga_set_state, 360 .asic_reset = &r300_asic_reset, 361 .mmio_hdp_flush = NULL, 362 .gui_idle = &r100_gui_idle, 363 .mc_wait_for_idle = &r300_mc_wait_for_idle, 364 .gart = { 365 .tlb_flush = &r100_pci_gart_tlb_flush, 366 .get_page_entry = &r100_pci_gart_get_page_entry, 367 .set_page = &r100_pci_gart_set_page, 368 }, 369 .ring = { 370 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 371 }, 372 .irq = { 373 .set = &r100_irq_set, 374 .process = &r100_irq_process, 375 }, 376 .display = { 377 .bandwidth_update = &r100_bandwidth_update, 378 .get_vblank_counter = &r100_get_vblank_counter, 379 .wait_for_vblank = &r100_wait_for_vblank, 380 .set_backlight_level = &radeon_legacy_set_backlight_level, 381 .get_backlight_level = &radeon_legacy_get_backlight_level, 382 }, 383 .copy = { 384 .blit = &r100_copy_blit, 385 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 386 .dma = &r200_copy_dma, 387 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 388 .copy = &r100_copy_blit, 389 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 390 }, 391 .surface = { 392 .set_reg = r100_set_surface_reg, 393 .clear_reg = r100_clear_surface_reg, 394 }, 395 .hpd = { 396 .init = &r100_hpd_init, 397 .fini = &r100_hpd_fini, 398 .sense = &r100_hpd_sense, 399 .set_polarity = &r100_hpd_set_polarity, 400 }, 401 .pm = { 402 .misc = &r100_pm_misc, 403 .prepare = &r100_pm_prepare, 404 .finish = &r100_pm_finish, 405 .init_profile = &r100_pm_init_profile, 406 .get_dynpm_state = &r100_pm_get_dynpm_state, 407 .get_engine_clock = &radeon_legacy_get_engine_clock, 408 .set_engine_clock = &radeon_legacy_set_engine_clock, 409 .get_memory_clock = &radeon_legacy_get_memory_clock, 410 .set_memory_clock = NULL, 411 .get_pcie_lanes = &rv370_get_pcie_lanes, 412 .set_pcie_lanes = &rv370_set_pcie_lanes, 413 .set_clock_gating = &radeon_legacy_set_clock_gating, 414 }, 415 .pflip = { 416 .page_flip = &r100_page_flip, 417 .page_flip_pending = &r100_page_flip_pending, 418 }, 419 }; 420 421 static struct radeon_asic r300_asic_pcie = { 422 .init = &r300_init, 423 .fini = &r300_fini, 424 .suspend = &r300_suspend, 425 .resume = &r300_resume, 426 .vga_set_state = &r100_vga_set_state, 427 .asic_reset = &r300_asic_reset, 428 .mmio_hdp_flush = NULL, 429 .gui_idle = &r100_gui_idle, 430 .mc_wait_for_idle = &r300_mc_wait_for_idle, 431 .gart = { 432 .tlb_flush = &rv370_pcie_gart_tlb_flush, 433 .get_page_entry = &rv370_pcie_gart_get_page_entry, 434 .set_page = &rv370_pcie_gart_set_page, 435 }, 436 .ring = { 437 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 438 }, 439 .irq = { 440 .set = &r100_irq_set, 441 .process = &r100_irq_process, 442 }, 443 .display = { 444 .bandwidth_update = &r100_bandwidth_update, 445 .get_vblank_counter = &r100_get_vblank_counter, 446 .wait_for_vblank = &r100_wait_for_vblank, 447 .set_backlight_level = &radeon_legacy_set_backlight_level, 448 .get_backlight_level = &radeon_legacy_get_backlight_level, 449 }, 450 .copy = { 451 .blit = &r100_copy_blit, 452 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 453 .dma = &r200_copy_dma, 454 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 455 .copy = &r100_copy_blit, 456 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 457 }, 458 .surface = { 459 .set_reg = r100_set_surface_reg, 460 .clear_reg = r100_clear_surface_reg, 461 }, 462 .hpd = { 463 .init = &r100_hpd_init, 464 .fini = &r100_hpd_fini, 465 .sense = &r100_hpd_sense, 466 .set_polarity = &r100_hpd_set_polarity, 467 }, 468 .pm = { 469 .misc = &r100_pm_misc, 470 .prepare = &r100_pm_prepare, 471 .finish = &r100_pm_finish, 472 .init_profile = &r100_pm_init_profile, 473 .get_dynpm_state = &r100_pm_get_dynpm_state, 474 .get_engine_clock = &radeon_legacy_get_engine_clock, 475 .set_engine_clock = &radeon_legacy_set_engine_clock, 476 .get_memory_clock = &radeon_legacy_get_memory_clock, 477 .set_memory_clock = NULL, 478 .get_pcie_lanes = &rv370_get_pcie_lanes, 479 .set_pcie_lanes = &rv370_set_pcie_lanes, 480 .set_clock_gating = &radeon_legacy_set_clock_gating, 481 }, 482 .pflip = { 483 .page_flip = &r100_page_flip, 484 .page_flip_pending = &r100_page_flip_pending, 485 }, 486 }; 487 488 static struct radeon_asic r420_asic = { 489 .init = &r420_init, 490 .fini = &r420_fini, 491 .suspend = &r420_suspend, 492 .resume = &r420_resume, 493 .vga_set_state = &r100_vga_set_state, 494 .asic_reset = &r300_asic_reset, 495 .mmio_hdp_flush = NULL, 496 .gui_idle = &r100_gui_idle, 497 .mc_wait_for_idle = &r300_mc_wait_for_idle, 498 .gart = { 499 .tlb_flush = &rv370_pcie_gart_tlb_flush, 500 .get_page_entry = &rv370_pcie_gart_get_page_entry, 501 .set_page = &rv370_pcie_gart_set_page, 502 }, 503 .ring = { 504 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 505 }, 506 .irq = { 507 .set = &r100_irq_set, 508 .process = &r100_irq_process, 509 }, 510 .display = { 511 .bandwidth_update = &r100_bandwidth_update, 512 .get_vblank_counter = &r100_get_vblank_counter, 513 .wait_for_vblank = &r100_wait_for_vblank, 514 .set_backlight_level = &atombios_set_backlight_level, 515 .get_backlight_level = &atombios_get_backlight_level, 516 }, 517 .copy = { 518 .blit = &r100_copy_blit, 519 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 520 .dma = &r200_copy_dma, 521 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 522 .copy = &r100_copy_blit, 523 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 524 }, 525 .surface = { 526 .set_reg = r100_set_surface_reg, 527 .clear_reg = r100_clear_surface_reg, 528 }, 529 .hpd = { 530 .init = &r100_hpd_init, 531 .fini = &r100_hpd_fini, 532 .sense = &r100_hpd_sense, 533 .set_polarity = &r100_hpd_set_polarity, 534 }, 535 .pm = { 536 .misc = &r100_pm_misc, 537 .prepare = &r100_pm_prepare, 538 .finish = &r100_pm_finish, 539 .init_profile = &r420_pm_init_profile, 540 .get_dynpm_state = &r100_pm_get_dynpm_state, 541 .get_engine_clock = &radeon_atom_get_engine_clock, 542 .set_engine_clock = &radeon_atom_set_engine_clock, 543 .get_memory_clock = &radeon_atom_get_memory_clock, 544 .set_memory_clock = &radeon_atom_set_memory_clock, 545 .get_pcie_lanes = &rv370_get_pcie_lanes, 546 .set_pcie_lanes = &rv370_set_pcie_lanes, 547 .set_clock_gating = &radeon_atom_set_clock_gating, 548 }, 549 .pflip = { 550 .page_flip = &r100_page_flip, 551 .page_flip_pending = &r100_page_flip_pending, 552 }, 553 }; 554 555 static struct radeon_asic rs400_asic = { 556 .init = &rs400_init, 557 .fini = &rs400_fini, 558 .suspend = &rs400_suspend, 559 .resume = &rs400_resume, 560 .vga_set_state = &r100_vga_set_state, 561 .asic_reset = &r300_asic_reset, 562 .mmio_hdp_flush = NULL, 563 .gui_idle = &r100_gui_idle, 564 .mc_wait_for_idle = &rs400_mc_wait_for_idle, 565 .gart = { 566 .tlb_flush = &rs400_gart_tlb_flush, 567 .get_page_entry = &rs400_gart_get_page_entry, 568 .set_page = &rs400_gart_set_page, 569 }, 570 .ring = { 571 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 572 }, 573 .irq = { 574 .set = &r100_irq_set, 575 .process = &r100_irq_process, 576 }, 577 .display = { 578 .bandwidth_update = &r100_bandwidth_update, 579 .get_vblank_counter = &r100_get_vblank_counter, 580 .wait_for_vblank = &r100_wait_for_vblank, 581 .set_backlight_level = &radeon_legacy_set_backlight_level, 582 .get_backlight_level = &radeon_legacy_get_backlight_level, 583 }, 584 .copy = { 585 .blit = &r100_copy_blit, 586 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 587 .dma = &r200_copy_dma, 588 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 589 .copy = &r100_copy_blit, 590 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 591 }, 592 .surface = { 593 .set_reg = r100_set_surface_reg, 594 .clear_reg = r100_clear_surface_reg, 595 }, 596 .hpd = { 597 .init = &r100_hpd_init, 598 .fini = &r100_hpd_fini, 599 .sense = &r100_hpd_sense, 600 .set_polarity = &r100_hpd_set_polarity, 601 }, 602 .pm = { 603 .misc = &r100_pm_misc, 604 .prepare = &r100_pm_prepare, 605 .finish = &r100_pm_finish, 606 .init_profile = &r100_pm_init_profile, 607 .get_dynpm_state = &r100_pm_get_dynpm_state, 608 .get_engine_clock = &radeon_legacy_get_engine_clock, 609 .set_engine_clock = &radeon_legacy_set_engine_clock, 610 .get_memory_clock = &radeon_legacy_get_memory_clock, 611 .set_memory_clock = NULL, 612 .get_pcie_lanes = NULL, 613 .set_pcie_lanes = NULL, 614 .set_clock_gating = &radeon_legacy_set_clock_gating, 615 }, 616 .pflip = { 617 .page_flip = &r100_page_flip, 618 .page_flip_pending = &r100_page_flip_pending, 619 }, 620 }; 621 622 static struct radeon_asic rs600_asic = { 623 .init = &rs600_init, 624 .fini = &rs600_fini, 625 .suspend = &rs600_suspend, 626 .resume = &rs600_resume, 627 .vga_set_state = &r100_vga_set_state, 628 .asic_reset = &rs600_asic_reset, 629 .mmio_hdp_flush = NULL, 630 .gui_idle = &r100_gui_idle, 631 .mc_wait_for_idle = &rs600_mc_wait_for_idle, 632 .gart = { 633 .tlb_flush = &rs600_gart_tlb_flush, 634 .get_page_entry = &rs600_gart_get_page_entry, 635 .set_page = &rs600_gart_set_page, 636 }, 637 .ring = { 638 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 639 }, 640 .irq = { 641 .set = &rs600_irq_set, 642 .process = &rs600_irq_process, 643 }, 644 .display = { 645 .bandwidth_update = &rs600_bandwidth_update, 646 .get_vblank_counter = &rs600_get_vblank_counter, 647 .wait_for_vblank = &avivo_wait_for_vblank, 648 .set_backlight_level = &atombios_set_backlight_level, 649 .get_backlight_level = &atombios_get_backlight_level, 650 }, 651 .copy = { 652 .blit = &r100_copy_blit, 653 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 654 .dma = &r200_copy_dma, 655 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 656 .copy = &r100_copy_blit, 657 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 658 }, 659 .surface = { 660 .set_reg = r100_set_surface_reg, 661 .clear_reg = r100_clear_surface_reg, 662 }, 663 .hpd = { 664 .init = &rs600_hpd_init, 665 .fini = &rs600_hpd_fini, 666 .sense = &rs600_hpd_sense, 667 .set_polarity = &rs600_hpd_set_polarity, 668 }, 669 .pm = { 670 .misc = &rs600_pm_misc, 671 .prepare = &rs600_pm_prepare, 672 .finish = &rs600_pm_finish, 673 .init_profile = &r420_pm_init_profile, 674 .get_dynpm_state = &r100_pm_get_dynpm_state, 675 .get_engine_clock = &radeon_atom_get_engine_clock, 676 .set_engine_clock = &radeon_atom_set_engine_clock, 677 .get_memory_clock = &radeon_atom_get_memory_clock, 678 .set_memory_clock = &radeon_atom_set_memory_clock, 679 .get_pcie_lanes = NULL, 680 .set_pcie_lanes = NULL, 681 .set_clock_gating = &radeon_atom_set_clock_gating, 682 }, 683 .pflip = { 684 .page_flip = &rs600_page_flip, 685 .page_flip_pending = &rs600_page_flip_pending, 686 }, 687 }; 688 689 static struct radeon_asic rs690_asic = { 690 .init = &rs690_init, 691 .fini = &rs690_fini, 692 .suspend = &rs690_suspend, 693 .resume = &rs690_resume, 694 .vga_set_state = &r100_vga_set_state, 695 .asic_reset = &rs600_asic_reset, 696 .mmio_hdp_flush = NULL, 697 .gui_idle = &r100_gui_idle, 698 .mc_wait_for_idle = &rs690_mc_wait_for_idle, 699 .gart = { 700 .tlb_flush = &rs400_gart_tlb_flush, 701 .get_page_entry = &rs400_gart_get_page_entry, 702 .set_page = &rs400_gart_set_page, 703 }, 704 .ring = { 705 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 706 }, 707 .irq = { 708 .set = &rs600_irq_set, 709 .process = &rs600_irq_process, 710 }, 711 .display = { 712 .get_vblank_counter = &rs600_get_vblank_counter, 713 .bandwidth_update = &rs690_bandwidth_update, 714 .wait_for_vblank = &avivo_wait_for_vblank, 715 .set_backlight_level = &atombios_set_backlight_level, 716 .get_backlight_level = &atombios_get_backlight_level, 717 }, 718 .copy = { 719 .blit = &r100_copy_blit, 720 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 721 .dma = &r200_copy_dma, 722 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 723 .copy = &r200_copy_dma, 724 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 725 }, 726 .surface = { 727 .set_reg = r100_set_surface_reg, 728 .clear_reg = r100_clear_surface_reg, 729 }, 730 .hpd = { 731 .init = &rs600_hpd_init, 732 .fini = &rs600_hpd_fini, 733 .sense = &rs600_hpd_sense, 734 .set_polarity = &rs600_hpd_set_polarity, 735 }, 736 .pm = { 737 .misc = &rs600_pm_misc, 738 .prepare = &rs600_pm_prepare, 739 .finish = &rs600_pm_finish, 740 .init_profile = &r420_pm_init_profile, 741 .get_dynpm_state = &r100_pm_get_dynpm_state, 742 .get_engine_clock = &radeon_atom_get_engine_clock, 743 .set_engine_clock = &radeon_atom_set_engine_clock, 744 .get_memory_clock = &radeon_atom_get_memory_clock, 745 .set_memory_clock = &radeon_atom_set_memory_clock, 746 .get_pcie_lanes = NULL, 747 .set_pcie_lanes = NULL, 748 .set_clock_gating = &radeon_atom_set_clock_gating, 749 }, 750 .pflip = { 751 .page_flip = &rs600_page_flip, 752 .page_flip_pending = &rs600_page_flip_pending, 753 }, 754 }; 755 756 static struct radeon_asic rv515_asic = { 757 .init = &rv515_init, 758 .fini = &rv515_fini, 759 .suspend = &rv515_suspend, 760 .resume = &rv515_resume, 761 .vga_set_state = &r100_vga_set_state, 762 .asic_reset = &rs600_asic_reset, 763 .mmio_hdp_flush = NULL, 764 .gui_idle = &r100_gui_idle, 765 .mc_wait_for_idle = &rv515_mc_wait_for_idle, 766 .gart = { 767 .tlb_flush = &rv370_pcie_gart_tlb_flush, 768 .get_page_entry = &rv370_pcie_gart_get_page_entry, 769 .set_page = &rv370_pcie_gart_set_page, 770 }, 771 .ring = { 772 [RADEON_RING_TYPE_GFX_INDEX] = &rv515_gfx_ring 773 }, 774 .irq = { 775 .set = &rs600_irq_set, 776 .process = &rs600_irq_process, 777 }, 778 .display = { 779 .get_vblank_counter = &rs600_get_vblank_counter, 780 .bandwidth_update = &rv515_bandwidth_update, 781 .wait_for_vblank = &avivo_wait_for_vblank, 782 .set_backlight_level = &atombios_set_backlight_level, 783 .get_backlight_level = &atombios_get_backlight_level, 784 }, 785 .copy = { 786 .blit = &r100_copy_blit, 787 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 788 .dma = &r200_copy_dma, 789 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 790 .copy = &r100_copy_blit, 791 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 792 }, 793 .surface = { 794 .set_reg = r100_set_surface_reg, 795 .clear_reg = r100_clear_surface_reg, 796 }, 797 .hpd = { 798 .init = &rs600_hpd_init, 799 .fini = &rs600_hpd_fini, 800 .sense = &rs600_hpd_sense, 801 .set_polarity = &rs600_hpd_set_polarity, 802 }, 803 .pm = { 804 .misc = &rs600_pm_misc, 805 .prepare = &rs600_pm_prepare, 806 .finish = &rs600_pm_finish, 807 .init_profile = &r420_pm_init_profile, 808 .get_dynpm_state = &r100_pm_get_dynpm_state, 809 .get_engine_clock = &radeon_atom_get_engine_clock, 810 .set_engine_clock = &radeon_atom_set_engine_clock, 811 .get_memory_clock = &radeon_atom_get_memory_clock, 812 .set_memory_clock = &radeon_atom_set_memory_clock, 813 .get_pcie_lanes = &rv370_get_pcie_lanes, 814 .set_pcie_lanes = &rv370_set_pcie_lanes, 815 .set_clock_gating = &radeon_atom_set_clock_gating, 816 }, 817 .pflip = { 818 .page_flip = &rs600_page_flip, 819 .page_flip_pending = &rs600_page_flip_pending, 820 }, 821 }; 822 823 static struct radeon_asic r520_asic = { 824 .init = &r520_init, 825 .fini = &rv515_fini, 826 .suspend = &rv515_suspend, 827 .resume = &r520_resume, 828 .vga_set_state = &r100_vga_set_state, 829 .asic_reset = &rs600_asic_reset, 830 .mmio_hdp_flush = NULL, 831 .gui_idle = &r100_gui_idle, 832 .mc_wait_for_idle = &r520_mc_wait_for_idle, 833 .gart = { 834 .tlb_flush = &rv370_pcie_gart_tlb_flush, 835 .get_page_entry = &rv370_pcie_gart_get_page_entry, 836 .set_page = &rv370_pcie_gart_set_page, 837 }, 838 .ring = { 839 [RADEON_RING_TYPE_GFX_INDEX] = &rv515_gfx_ring 840 }, 841 .irq = { 842 .set = &rs600_irq_set, 843 .process = &rs600_irq_process, 844 }, 845 .display = { 846 .bandwidth_update = &rv515_bandwidth_update, 847 .get_vblank_counter = &rs600_get_vblank_counter, 848 .wait_for_vblank = &avivo_wait_for_vblank, 849 .set_backlight_level = &atombios_set_backlight_level, 850 .get_backlight_level = &atombios_get_backlight_level, 851 }, 852 .copy = { 853 .blit = &r100_copy_blit, 854 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 855 .dma = &r200_copy_dma, 856 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 857 .copy = &r100_copy_blit, 858 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 859 }, 860 .surface = { 861 .set_reg = r100_set_surface_reg, 862 .clear_reg = r100_clear_surface_reg, 863 }, 864 .hpd = { 865 .init = &rs600_hpd_init, 866 .fini = &rs600_hpd_fini, 867 .sense = &rs600_hpd_sense, 868 .set_polarity = &rs600_hpd_set_polarity, 869 }, 870 .pm = { 871 .misc = &rs600_pm_misc, 872 .prepare = &rs600_pm_prepare, 873 .finish = &rs600_pm_finish, 874 .init_profile = &r420_pm_init_profile, 875 .get_dynpm_state = &r100_pm_get_dynpm_state, 876 .get_engine_clock = &radeon_atom_get_engine_clock, 877 .set_engine_clock = &radeon_atom_set_engine_clock, 878 .get_memory_clock = &radeon_atom_get_memory_clock, 879 .set_memory_clock = &radeon_atom_set_memory_clock, 880 .get_pcie_lanes = &rv370_get_pcie_lanes, 881 .set_pcie_lanes = &rv370_set_pcie_lanes, 882 .set_clock_gating = &radeon_atom_set_clock_gating, 883 }, 884 .pflip = { 885 .page_flip = &rs600_page_flip, 886 .page_flip_pending = &rs600_page_flip_pending, 887 }, 888 }; 889 890 static struct radeon_asic_ring r600_gfx_ring = { 891 .ib_execute = &r600_ring_ib_execute, 892 .emit_fence = &r600_fence_ring_emit, 893 .emit_semaphore = &r600_semaphore_ring_emit, 894 .cs_parse = &r600_cs_parse, 895 .ring_test = &r600_ring_test, 896 .ib_test = &r600_ib_test, 897 .is_lockup = &r600_gfx_is_lockup, 898 .get_rptr = &r600_gfx_get_rptr, 899 .get_wptr = &r600_gfx_get_wptr, 900 .set_wptr = &r600_gfx_set_wptr, 901 }; 902 903 static struct radeon_asic_ring r600_dma_ring = { 904 .ib_execute = &r600_dma_ring_ib_execute, 905 .emit_fence = &r600_dma_fence_ring_emit, 906 .emit_semaphore = &r600_dma_semaphore_ring_emit, 907 .cs_parse = &r600_dma_cs_parse, 908 .ring_test = &r600_dma_ring_test, 909 .ib_test = &r600_dma_ib_test, 910 .is_lockup = &r600_dma_is_lockup, 911 .get_rptr = &r600_dma_get_rptr, 912 .get_wptr = &r600_dma_get_wptr, 913 .set_wptr = &r600_dma_set_wptr, 914 }; 915 916 static struct radeon_asic r600_asic = { 917 .init = &r600_init, 918 .fini = &r600_fini, 919 .suspend = &r600_suspend, 920 .resume = &r600_resume, 921 .vga_set_state = &r600_vga_set_state, 922 .asic_reset = &r600_asic_reset, 923 .mmio_hdp_flush = r600_mmio_hdp_flush, 924 .gui_idle = &r600_gui_idle, 925 .mc_wait_for_idle = &r600_mc_wait_for_idle, 926 .get_xclk = &r600_get_xclk, 927 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 928 .gart = { 929 .tlb_flush = &r600_pcie_gart_tlb_flush, 930 .get_page_entry = &rs600_gart_get_page_entry, 931 .set_page = &rs600_gart_set_page, 932 }, 933 .ring = { 934 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, 935 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, 936 }, 937 .irq = { 938 .set = &r600_irq_set, 939 .process = &r600_irq_process, 940 }, 941 .display = { 942 .bandwidth_update = &rv515_bandwidth_update, 943 .get_vblank_counter = &rs600_get_vblank_counter, 944 .wait_for_vblank = &avivo_wait_for_vblank, 945 .set_backlight_level = &atombios_set_backlight_level, 946 .get_backlight_level = &atombios_get_backlight_level, 947 }, 948 .copy = { 949 .blit = &r600_copy_cpdma, 950 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 951 .dma = &r600_copy_dma, 952 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 953 .copy = &r600_copy_cpdma, 954 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 955 }, 956 .surface = { 957 .set_reg = r600_set_surface_reg, 958 .clear_reg = r600_clear_surface_reg, 959 }, 960 .hpd = { 961 .init = &r600_hpd_init, 962 .fini = &r600_hpd_fini, 963 .sense = &r600_hpd_sense, 964 .set_polarity = &r600_hpd_set_polarity, 965 }, 966 .pm = { 967 .misc = &r600_pm_misc, 968 .prepare = &rs600_pm_prepare, 969 .finish = &rs600_pm_finish, 970 .init_profile = &r600_pm_init_profile, 971 .get_dynpm_state = &r600_pm_get_dynpm_state, 972 .get_engine_clock = &radeon_atom_get_engine_clock, 973 .set_engine_clock = &radeon_atom_set_engine_clock, 974 .get_memory_clock = &radeon_atom_get_memory_clock, 975 .set_memory_clock = &radeon_atom_set_memory_clock, 976 .get_pcie_lanes = &r600_get_pcie_lanes, 977 .set_pcie_lanes = &r600_set_pcie_lanes, 978 .set_clock_gating = NULL, 979 .get_temperature = &rv6xx_get_temp, 980 }, 981 .pflip = { 982 .page_flip = &rs600_page_flip, 983 .page_flip_pending = &rs600_page_flip_pending, 984 }, 985 }; 986 987 static struct radeon_asic_ring rv6xx_uvd_ring = { 988 .ib_execute = &uvd_v1_0_ib_execute, 989 .emit_fence = &uvd_v1_0_fence_emit, 990 .emit_semaphore = &uvd_v1_0_semaphore_emit, 991 .cs_parse = &radeon_uvd_cs_parse, 992 .ring_test = &uvd_v1_0_ring_test, 993 .ib_test = &uvd_v1_0_ib_test, 994 .is_lockup = &radeon_ring_test_lockup, 995 .get_rptr = &uvd_v1_0_get_rptr, 996 .get_wptr = &uvd_v1_0_get_wptr, 997 .set_wptr = &uvd_v1_0_set_wptr, 998 }; 999 1000 static struct radeon_asic rv6xx_asic = { 1001 .init = &r600_init, 1002 .fini = &r600_fini, 1003 .suspend = &r600_suspend, 1004 .resume = &r600_resume, 1005 .vga_set_state = &r600_vga_set_state, 1006 .asic_reset = &r600_asic_reset, 1007 .mmio_hdp_flush = r600_mmio_hdp_flush, 1008 .gui_idle = &r600_gui_idle, 1009 .mc_wait_for_idle = &r600_mc_wait_for_idle, 1010 .get_xclk = &r600_get_xclk, 1011 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1012 .gart = { 1013 .tlb_flush = &r600_pcie_gart_tlb_flush, 1014 .get_page_entry = &rs600_gart_get_page_entry, 1015 .set_page = &rs600_gart_set_page, 1016 }, 1017 .ring = { 1018 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, 1019 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, 1020 [R600_RING_TYPE_UVD_INDEX] = &rv6xx_uvd_ring, 1021 }, 1022 .irq = { 1023 .set = &r600_irq_set, 1024 .process = &r600_irq_process, 1025 }, 1026 .display = { 1027 .bandwidth_update = &rv515_bandwidth_update, 1028 .get_vblank_counter = &rs600_get_vblank_counter, 1029 .wait_for_vblank = &avivo_wait_for_vblank, 1030 .set_backlight_level = &atombios_set_backlight_level, 1031 .get_backlight_level = &atombios_get_backlight_level, 1032 }, 1033 .copy = { 1034 .blit = &r600_copy_cpdma, 1035 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1036 .dma = &r600_copy_dma, 1037 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1038 .copy = &r600_copy_cpdma, 1039 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1040 }, 1041 .surface = { 1042 .set_reg = r600_set_surface_reg, 1043 .clear_reg = r600_clear_surface_reg, 1044 }, 1045 .hpd = { 1046 .init = &r600_hpd_init, 1047 .fini = &r600_hpd_fini, 1048 .sense = &r600_hpd_sense, 1049 .set_polarity = &r600_hpd_set_polarity, 1050 }, 1051 .pm = { 1052 .misc = &r600_pm_misc, 1053 .prepare = &rs600_pm_prepare, 1054 .finish = &rs600_pm_finish, 1055 .init_profile = &r600_pm_init_profile, 1056 .get_dynpm_state = &r600_pm_get_dynpm_state, 1057 .get_engine_clock = &radeon_atom_get_engine_clock, 1058 .set_engine_clock = &radeon_atom_set_engine_clock, 1059 .get_memory_clock = &radeon_atom_get_memory_clock, 1060 .set_memory_clock = &radeon_atom_set_memory_clock, 1061 .get_pcie_lanes = &r600_get_pcie_lanes, 1062 .set_pcie_lanes = &r600_set_pcie_lanes, 1063 .set_clock_gating = NULL, 1064 .get_temperature = &rv6xx_get_temp, 1065 .set_uvd_clocks = &r600_set_uvd_clocks, 1066 }, 1067 .dpm = { 1068 .init = &rv6xx_dpm_init, 1069 .setup_asic = &rv6xx_setup_asic, 1070 .enable = &rv6xx_dpm_enable, 1071 .late_enable = &r600_dpm_late_enable, 1072 .disable = &rv6xx_dpm_disable, 1073 .pre_set_power_state = &r600_dpm_pre_set_power_state, 1074 .set_power_state = &rv6xx_dpm_set_power_state, 1075 .post_set_power_state = &r600_dpm_post_set_power_state, 1076 .display_configuration_changed = &rv6xx_dpm_display_configuration_changed, 1077 .fini = &rv6xx_dpm_fini, 1078 .get_sclk = &rv6xx_dpm_get_sclk, 1079 .get_mclk = &rv6xx_dpm_get_mclk, 1080 .print_power_state = &rv6xx_dpm_print_power_state, 1081 .debugfs_print_current_performance_level = &rv6xx_dpm_debugfs_print_current_performance_level, 1082 .force_performance_level = &rv6xx_dpm_force_performance_level, 1083 }, 1084 .pflip = { 1085 .page_flip = &rs600_page_flip, 1086 .page_flip_pending = &rs600_page_flip_pending, 1087 }, 1088 }; 1089 1090 static struct radeon_asic rs780_asic = { 1091 .init = &r600_init, 1092 .fini = &r600_fini, 1093 .suspend = &r600_suspend, 1094 .resume = &r600_resume, 1095 .vga_set_state = &r600_vga_set_state, 1096 .asic_reset = &r600_asic_reset, 1097 .mmio_hdp_flush = r600_mmio_hdp_flush, 1098 .gui_idle = &r600_gui_idle, 1099 .mc_wait_for_idle = &r600_mc_wait_for_idle, 1100 .get_xclk = &r600_get_xclk, 1101 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1102 .gart = { 1103 .tlb_flush = &r600_pcie_gart_tlb_flush, 1104 .get_page_entry = &rs600_gart_get_page_entry, 1105 .set_page = &rs600_gart_set_page, 1106 }, 1107 .ring = { 1108 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, 1109 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, 1110 [R600_RING_TYPE_UVD_INDEX] = &rv6xx_uvd_ring, 1111 }, 1112 .irq = { 1113 .set = &r600_irq_set, 1114 .process = &r600_irq_process, 1115 }, 1116 .display = { 1117 .bandwidth_update = &rs690_bandwidth_update, 1118 .get_vblank_counter = &rs600_get_vblank_counter, 1119 .wait_for_vblank = &avivo_wait_for_vblank, 1120 .set_backlight_level = &atombios_set_backlight_level, 1121 .get_backlight_level = &atombios_get_backlight_level, 1122 }, 1123 .copy = { 1124 .blit = &r600_copy_cpdma, 1125 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1126 .dma = &r600_copy_dma, 1127 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1128 .copy = &r600_copy_cpdma, 1129 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1130 }, 1131 .surface = { 1132 .set_reg = r600_set_surface_reg, 1133 .clear_reg = r600_clear_surface_reg, 1134 }, 1135 .hpd = { 1136 .init = &r600_hpd_init, 1137 .fini = &r600_hpd_fini, 1138 .sense = &r600_hpd_sense, 1139 .set_polarity = &r600_hpd_set_polarity, 1140 }, 1141 .pm = { 1142 .misc = &r600_pm_misc, 1143 .prepare = &rs600_pm_prepare, 1144 .finish = &rs600_pm_finish, 1145 .init_profile = &rs780_pm_init_profile, 1146 .get_dynpm_state = &r600_pm_get_dynpm_state, 1147 .get_engine_clock = &radeon_atom_get_engine_clock, 1148 .set_engine_clock = &radeon_atom_set_engine_clock, 1149 .get_memory_clock = NULL, 1150 .set_memory_clock = NULL, 1151 .get_pcie_lanes = NULL, 1152 .set_pcie_lanes = NULL, 1153 .set_clock_gating = NULL, 1154 .get_temperature = &rv6xx_get_temp, 1155 .set_uvd_clocks = &r600_set_uvd_clocks, 1156 }, 1157 .dpm = { 1158 .init = &rs780_dpm_init, 1159 .setup_asic = &rs780_dpm_setup_asic, 1160 .enable = &rs780_dpm_enable, 1161 .late_enable = &r600_dpm_late_enable, 1162 .disable = &rs780_dpm_disable, 1163 .pre_set_power_state = &r600_dpm_pre_set_power_state, 1164 .set_power_state = &rs780_dpm_set_power_state, 1165 .post_set_power_state = &r600_dpm_post_set_power_state, 1166 .display_configuration_changed = &rs780_dpm_display_configuration_changed, 1167 .fini = &rs780_dpm_fini, 1168 .get_sclk = &rs780_dpm_get_sclk, 1169 .get_mclk = &rs780_dpm_get_mclk, 1170 .print_power_state = &rs780_dpm_print_power_state, 1171 .debugfs_print_current_performance_level = &rs780_dpm_debugfs_print_current_performance_level, 1172 .force_performance_level = &rs780_dpm_force_performance_level, 1173 }, 1174 .pflip = { 1175 .page_flip = &rs600_page_flip, 1176 .page_flip_pending = &rs600_page_flip_pending, 1177 }, 1178 }; 1179 1180 static struct radeon_asic_ring rv770_uvd_ring = { 1181 .ib_execute = &uvd_v1_0_ib_execute, 1182 .emit_fence = &uvd_v2_2_fence_emit, 1183 .emit_semaphore = &uvd_v1_0_semaphore_emit, 1184 .cs_parse = &radeon_uvd_cs_parse, 1185 .ring_test = &uvd_v1_0_ring_test, 1186 .ib_test = &uvd_v1_0_ib_test, 1187 .is_lockup = &radeon_ring_test_lockup, 1188 .get_rptr = &uvd_v1_0_get_rptr, 1189 .get_wptr = &uvd_v1_0_get_wptr, 1190 .set_wptr = &uvd_v1_0_set_wptr, 1191 }; 1192 1193 static struct radeon_asic rv770_asic = { 1194 .init = &rv770_init, 1195 .fini = &rv770_fini, 1196 .suspend = &rv770_suspend, 1197 .resume = &rv770_resume, 1198 .asic_reset = &r600_asic_reset, 1199 .vga_set_state = &r600_vga_set_state, 1200 .mmio_hdp_flush = r600_mmio_hdp_flush, 1201 .gui_idle = &r600_gui_idle, 1202 .mc_wait_for_idle = &r600_mc_wait_for_idle, 1203 .get_xclk = &rv770_get_xclk, 1204 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1205 .gart = { 1206 .tlb_flush = &r600_pcie_gart_tlb_flush, 1207 .get_page_entry = &rs600_gart_get_page_entry, 1208 .set_page = &rs600_gart_set_page, 1209 }, 1210 .ring = { 1211 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, 1212 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, 1213 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring, 1214 }, 1215 .irq = { 1216 .set = &r600_irq_set, 1217 .process = &r600_irq_process, 1218 }, 1219 .display = { 1220 .bandwidth_update = &rv515_bandwidth_update, 1221 .get_vblank_counter = &rs600_get_vblank_counter, 1222 .wait_for_vblank = &avivo_wait_for_vblank, 1223 .set_backlight_level = &atombios_set_backlight_level, 1224 .get_backlight_level = &atombios_get_backlight_level, 1225 }, 1226 .copy = { 1227 .blit = &r600_copy_cpdma, 1228 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1229 .dma = &rv770_copy_dma, 1230 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1231 .copy = &rv770_copy_dma, 1232 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1233 }, 1234 .surface = { 1235 .set_reg = r600_set_surface_reg, 1236 .clear_reg = r600_clear_surface_reg, 1237 }, 1238 .hpd = { 1239 .init = &r600_hpd_init, 1240 .fini = &r600_hpd_fini, 1241 .sense = &r600_hpd_sense, 1242 .set_polarity = &r600_hpd_set_polarity, 1243 }, 1244 .pm = { 1245 .misc = &rv770_pm_misc, 1246 .prepare = &rs600_pm_prepare, 1247 .finish = &rs600_pm_finish, 1248 .init_profile = &r600_pm_init_profile, 1249 .get_dynpm_state = &r600_pm_get_dynpm_state, 1250 .get_engine_clock = &radeon_atom_get_engine_clock, 1251 .set_engine_clock = &radeon_atom_set_engine_clock, 1252 .get_memory_clock = &radeon_atom_get_memory_clock, 1253 .set_memory_clock = &radeon_atom_set_memory_clock, 1254 .get_pcie_lanes = &r600_get_pcie_lanes, 1255 .set_pcie_lanes = &r600_set_pcie_lanes, 1256 .set_clock_gating = &radeon_atom_set_clock_gating, 1257 .set_uvd_clocks = &rv770_set_uvd_clocks, 1258 .get_temperature = &rv770_get_temp, 1259 }, 1260 .dpm = { 1261 .init = &rv770_dpm_init, 1262 .setup_asic = &rv770_dpm_setup_asic, 1263 .enable = &rv770_dpm_enable, 1264 .late_enable = &rv770_dpm_late_enable, 1265 .disable = &rv770_dpm_disable, 1266 .pre_set_power_state = &r600_dpm_pre_set_power_state, 1267 .set_power_state = &rv770_dpm_set_power_state, 1268 .post_set_power_state = &r600_dpm_post_set_power_state, 1269 .display_configuration_changed = &rv770_dpm_display_configuration_changed, 1270 .fini = &rv770_dpm_fini, 1271 .get_sclk = &rv770_dpm_get_sclk, 1272 .get_mclk = &rv770_dpm_get_mclk, 1273 .print_power_state = &rv770_dpm_print_power_state, 1274 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level, 1275 .force_performance_level = &rv770_dpm_force_performance_level, 1276 .vblank_too_short = &rv770_dpm_vblank_too_short, 1277 }, 1278 .pflip = { 1279 .page_flip = &rv770_page_flip, 1280 .page_flip_pending = &rv770_page_flip_pending, 1281 }, 1282 }; 1283 1284 static struct radeon_asic_ring evergreen_gfx_ring = { 1285 .ib_execute = &evergreen_ring_ib_execute, 1286 .emit_fence = &r600_fence_ring_emit, 1287 .emit_semaphore = &r600_semaphore_ring_emit, 1288 .cs_parse = &evergreen_cs_parse, 1289 .ring_test = &r600_ring_test, 1290 .ib_test = &r600_ib_test, 1291 .is_lockup = &evergreen_gfx_is_lockup, 1292 .get_rptr = &r600_gfx_get_rptr, 1293 .get_wptr = &r600_gfx_get_wptr, 1294 .set_wptr = &r600_gfx_set_wptr, 1295 }; 1296 1297 static struct radeon_asic_ring evergreen_dma_ring = { 1298 .ib_execute = &evergreen_dma_ring_ib_execute, 1299 .emit_fence = &evergreen_dma_fence_ring_emit, 1300 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1301 .cs_parse = &evergreen_dma_cs_parse, 1302 .ring_test = &r600_dma_ring_test, 1303 .ib_test = &r600_dma_ib_test, 1304 .is_lockup = &evergreen_dma_is_lockup, 1305 .get_rptr = &r600_dma_get_rptr, 1306 .get_wptr = &r600_dma_get_wptr, 1307 .set_wptr = &r600_dma_set_wptr, 1308 }; 1309 1310 static struct radeon_asic evergreen_asic = { 1311 .init = &evergreen_init, 1312 .fini = &evergreen_fini, 1313 .suspend = &evergreen_suspend, 1314 .resume = &evergreen_resume, 1315 .asic_reset = &evergreen_asic_reset, 1316 .vga_set_state = &r600_vga_set_state, 1317 .mmio_hdp_flush = r600_mmio_hdp_flush, 1318 .gui_idle = &r600_gui_idle, 1319 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1320 .get_xclk = &rv770_get_xclk, 1321 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1322 .gart = { 1323 .tlb_flush = &evergreen_pcie_gart_tlb_flush, 1324 .get_page_entry = &rs600_gart_get_page_entry, 1325 .set_page = &rs600_gart_set_page, 1326 }, 1327 .ring = { 1328 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring, 1329 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring, 1330 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring, 1331 }, 1332 .irq = { 1333 .set = &evergreen_irq_set, 1334 .process = &evergreen_irq_process, 1335 }, 1336 .display = { 1337 .bandwidth_update = &evergreen_bandwidth_update, 1338 .get_vblank_counter = &evergreen_get_vblank_counter, 1339 .wait_for_vblank = &dce4_wait_for_vblank, 1340 .set_backlight_level = &atombios_set_backlight_level, 1341 .get_backlight_level = &atombios_get_backlight_level, 1342 }, 1343 .copy = { 1344 .blit = &r600_copy_cpdma, 1345 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1346 .dma = &evergreen_copy_dma, 1347 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1348 .copy = &evergreen_copy_dma, 1349 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1350 }, 1351 .surface = { 1352 .set_reg = r600_set_surface_reg, 1353 .clear_reg = r600_clear_surface_reg, 1354 }, 1355 .hpd = { 1356 .init = &evergreen_hpd_init, 1357 .fini = &evergreen_hpd_fini, 1358 .sense = &evergreen_hpd_sense, 1359 .set_polarity = &evergreen_hpd_set_polarity, 1360 }, 1361 .pm = { 1362 .misc = &evergreen_pm_misc, 1363 .prepare = &evergreen_pm_prepare, 1364 .finish = &evergreen_pm_finish, 1365 .init_profile = &r600_pm_init_profile, 1366 .get_dynpm_state = &r600_pm_get_dynpm_state, 1367 .get_engine_clock = &radeon_atom_get_engine_clock, 1368 .set_engine_clock = &radeon_atom_set_engine_clock, 1369 .get_memory_clock = &radeon_atom_get_memory_clock, 1370 .set_memory_clock = &radeon_atom_set_memory_clock, 1371 .get_pcie_lanes = &r600_get_pcie_lanes, 1372 .set_pcie_lanes = &r600_set_pcie_lanes, 1373 .set_clock_gating = NULL, 1374 .set_uvd_clocks = &evergreen_set_uvd_clocks, 1375 .get_temperature = &evergreen_get_temp, 1376 }, 1377 .dpm = { 1378 .init = &cypress_dpm_init, 1379 .setup_asic = &cypress_dpm_setup_asic, 1380 .enable = &cypress_dpm_enable, 1381 .late_enable = &rv770_dpm_late_enable, 1382 .disable = &cypress_dpm_disable, 1383 .pre_set_power_state = &r600_dpm_pre_set_power_state, 1384 .set_power_state = &cypress_dpm_set_power_state, 1385 .post_set_power_state = &r600_dpm_post_set_power_state, 1386 .display_configuration_changed = &cypress_dpm_display_configuration_changed, 1387 .fini = &cypress_dpm_fini, 1388 .get_sclk = &rv770_dpm_get_sclk, 1389 .get_mclk = &rv770_dpm_get_mclk, 1390 .print_power_state = &rv770_dpm_print_power_state, 1391 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level, 1392 .force_performance_level = &rv770_dpm_force_performance_level, 1393 .vblank_too_short = &cypress_dpm_vblank_too_short, 1394 }, 1395 .pflip = { 1396 .page_flip = &evergreen_page_flip, 1397 .page_flip_pending = &evergreen_page_flip_pending, 1398 }, 1399 }; 1400 1401 static struct radeon_asic sumo_asic = { 1402 .init = &evergreen_init, 1403 .fini = &evergreen_fini, 1404 .suspend = &evergreen_suspend, 1405 .resume = &evergreen_resume, 1406 .asic_reset = &evergreen_asic_reset, 1407 .vga_set_state = &r600_vga_set_state, 1408 .mmio_hdp_flush = r600_mmio_hdp_flush, 1409 .gui_idle = &r600_gui_idle, 1410 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1411 .get_xclk = &r600_get_xclk, 1412 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1413 .gart = { 1414 .tlb_flush = &evergreen_pcie_gart_tlb_flush, 1415 .get_page_entry = &rs600_gart_get_page_entry, 1416 .set_page = &rs600_gart_set_page, 1417 }, 1418 .ring = { 1419 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring, 1420 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring, 1421 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring, 1422 }, 1423 .irq = { 1424 .set = &evergreen_irq_set, 1425 .process = &evergreen_irq_process, 1426 }, 1427 .display = { 1428 .bandwidth_update = &evergreen_bandwidth_update, 1429 .get_vblank_counter = &evergreen_get_vblank_counter, 1430 .wait_for_vblank = &dce4_wait_for_vblank, 1431 .set_backlight_level = &atombios_set_backlight_level, 1432 .get_backlight_level = &atombios_get_backlight_level, 1433 }, 1434 .copy = { 1435 .blit = &r600_copy_cpdma, 1436 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1437 .dma = &evergreen_copy_dma, 1438 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1439 .copy = &evergreen_copy_dma, 1440 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1441 }, 1442 .surface = { 1443 .set_reg = r600_set_surface_reg, 1444 .clear_reg = r600_clear_surface_reg, 1445 }, 1446 .hpd = { 1447 .init = &evergreen_hpd_init, 1448 .fini = &evergreen_hpd_fini, 1449 .sense = &evergreen_hpd_sense, 1450 .set_polarity = &evergreen_hpd_set_polarity, 1451 }, 1452 .pm = { 1453 .misc = &evergreen_pm_misc, 1454 .prepare = &evergreen_pm_prepare, 1455 .finish = &evergreen_pm_finish, 1456 .init_profile = &sumo_pm_init_profile, 1457 .get_dynpm_state = &r600_pm_get_dynpm_state, 1458 .get_engine_clock = &radeon_atom_get_engine_clock, 1459 .set_engine_clock = &radeon_atom_set_engine_clock, 1460 .get_memory_clock = NULL, 1461 .set_memory_clock = NULL, 1462 .get_pcie_lanes = NULL, 1463 .set_pcie_lanes = NULL, 1464 .set_clock_gating = NULL, 1465 .set_uvd_clocks = &sumo_set_uvd_clocks, 1466 .get_temperature = &sumo_get_temp, 1467 }, 1468 .dpm = { 1469 .init = &sumo_dpm_init, 1470 .setup_asic = &sumo_dpm_setup_asic, 1471 .enable = &sumo_dpm_enable, 1472 .late_enable = &sumo_dpm_late_enable, 1473 .disable = &sumo_dpm_disable, 1474 .pre_set_power_state = &sumo_dpm_pre_set_power_state, 1475 .set_power_state = &sumo_dpm_set_power_state, 1476 .post_set_power_state = &sumo_dpm_post_set_power_state, 1477 .display_configuration_changed = &sumo_dpm_display_configuration_changed, 1478 .fini = &sumo_dpm_fini, 1479 .get_sclk = &sumo_dpm_get_sclk, 1480 .get_mclk = &sumo_dpm_get_mclk, 1481 .print_power_state = &sumo_dpm_print_power_state, 1482 .debugfs_print_current_performance_level = &sumo_dpm_debugfs_print_current_performance_level, 1483 .force_performance_level = &sumo_dpm_force_performance_level, 1484 }, 1485 .pflip = { 1486 .page_flip = &evergreen_page_flip, 1487 .page_flip_pending = &evergreen_page_flip_pending, 1488 }, 1489 }; 1490 1491 static struct radeon_asic btc_asic = { 1492 .init = &evergreen_init, 1493 .fini = &evergreen_fini, 1494 .suspend = &evergreen_suspend, 1495 .resume = &evergreen_resume, 1496 .asic_reset = &evergreen_asic_reset, 1497 .vga_set_state = &r600_vga_set_state, 1498 .mmio_hdp_flush = r600_mmio_hdp_flush, 1499 .gui_idle = &r600_gui_idle, 1500 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1501 .get_xclk = &rv770_get_xclk, 1502 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1503 .gart = { 1504 .tlb_flush = &evergreen_pcie_gart_tlb_flush, 1505 .get_page_entry = &rs600_gart_get_page_entry, 1506 .set_page = &rs600_gart_set_page, 1507 }, 1508 .ring = { 1509 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring, 1510 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring, 1511 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring, 1512 }, 1513 .irq = { 1514 .set = &evergreen_irq_set, 1515 .process = &evergreen_irq_process, 1516 }, 1517 .display = { 1518 .bandwidth_update = &evergreen_bandwidth_update, 1519 .get_vblank_counter = &evergreen_get_vblank_counter, 1520 .wait_for_vblank = &dce4_wait_for_vblank, 1521 .set_backlight_level = &atombios_set_backlight_level, 1522 .get_backlight_level = &atombios_get_backlight_level, 1523 }, 1524 .copy = { 1525 .blit = &r600_copy_cpdma, 1526 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1527 .dma = &evergreen_copy_dma, 1528 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1529 .copy = &evergreen_copy_dma, 1530 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1531 }, 1532 .surface = { 1533 .set_reg = r600_set_surface_reg, 1534 .clear_reg = r600_clear_surface_reg, 1535 }, 1536 .hpd = { 1537 .init = &evergreen_hpd_init, 1538 .fini = &evergreen_hpd_fini, 1539 .sense = &evergreen_hpd_sense, 1540 .set_polarity = &evergreen_hpd_set_polarity, 1541 }, 1542 .pm = { 1543 .misc = &evergreen_pm_misc, 1544 .prepare = &evergreen_pm_prepare, 1545 .finish = &evergreen_pm_finish, 1546 .init_profile = &btc_pm_init_profile, 1547 .get_dynpm_state = &r600_pm_get_dynpm_state, 1548 .get_engine_clock = &radeon_atom_get_engine_clock, 1549 .set_engine_clock = &radeon_atom_set_engine_clock, 1550 .get_memory_clock = &radeon_atom_get_memory_clock, 1551 .set_memory_clock = &radeon_atom_set_memory_clock, 1552 .get_pcie_lanes = &r600_get_pcie_lanes, 1553 .set_pcie_lanes = &r600_set_pcie_lanes, 1554 .set_clock_gating = NULL, 1555 .set_uvd_clocks = &evergreen_set_uvd_clocks, 1556 .get_temperature = &evergreen_get_temp, 1557 }, 1558 .dpm = { 1559 .init = &btc_dpm_init, 1560 .setup_asic = &btc_dpm_setup_asic, 1561 .enable = &btc_dpm_enable, 1562 .late_enable = &rv770_dpm_late_enable, 1563 .disable = &btc_dpm_disable, 1564 .pre_set_power_state = &btc_dpm_pre_set_power_state, 1565 .set_power_state = &btc_dpm_set_power_state, 1566 .post_set_power_state = &btc_dpm_post_set_power_state, 1567 .display_configuration_changed = &cypress_dpm_display_configuration_changed, 1568 .fini = &btc_dpm_fini, 1569 .get_sclk = &btc_dpm_get_sclk, 1570 .get_mclk = &btc_dpm_get_mclk, 1571 .print_power_state = &rv770_dpm_print_power_state, 1572 .debugfs_print_current_performance_level = &btc_dpm_debugfs_print_current_performance_level, 1573 .force_performance_level = &rv770_dpm_force_performance_level, 1574 .vblank_too_short = &btc_dpm_vblank_too_short, 1575 }, 1576 .pflip = { 1577 .page_flip = &evergreen_page_flip, 1578 .page_flip_pending = &evergreen_page_flip_pending, 1579 }, 1580 }; 1581 1582 static struct radeon_asic_ring cayman_gfx_ring = { 1583 .ib_execute = &cayman_ring_ib_execute, 1584 .ib_parse = &evergreen_ib_parse, 1585 .emit_fence = &cayman_fence_ring_emit, 1586 .emit_semaphore = &r600_semaphore_ring_emit, 1587 .cs_parse = &evergreen_cs_parse, 1588 .ring_test = &r600_ring_test, 1589 .ib_test = &r600_ib_test, 1590 .is_lockup = &cayman_gfx_is_lockup, 1591 .vm_flush = &cayman_vm_flush, 1592 .get_rptr = &cayman_gfx_get_rptr, 1593 .get_wptr = &cayman_gfx_get_wptr, 1594 .set_wptr = &cayman_gfx_set_wptr, 1595 }; 1596 1597 static struct radeon_asic_ring cayman_dma_ring = { 1598 .ib_execute = &cayman_dma_ring_ib_execute, 1599 .ib_parse = &evergreen_dma_ib_parse, 1600 .emit_fence = &evergreen_dma_fence_ring_emit, 1601 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1602 .cs_parse = &evergreen_dma_cs_parse, 1603 .ring_test = &r600_dma_ring_test, 1604 .ib_test = &r600_dma_ib_test, 1605 .is_lockup = &cayman_dma_is_lockup, 1606 .vm_flush = &cayman_dma_vm_flush, 1607 .get_rptr = &cayman_dma_get_rptr, 1608 .get_wptr = &cayman_dma_get_wptr, 1609 .set_wptr = &cayman_dma_set_wptr 1610 }; 1611 1612 static struct radeon_asic_ring cayman_uvd_ring = { 1613 .ib_execute = &uvd_v1_0_ib_execute, 1614 .emit_fence = &uvd_v2_2_fence_emit, 1615 .emit_semaphore = &uvd_v3_1_semaphore_emit, 1616 .cs_parse = &radeon_uvd_cs_parse, 1617 .ring_test = &uvd_v1_0_ring_test, 1618 .ib_test = &uvd_v1_0_ib_test, 1619 .is_lockup = &radeon_ring_test_lockup, 1620 .get_rptr = &uvd_v1_0_get_rptr, 1621 .get_wptr = &uvd_v1_0_get_wptr, 1622 .set_wptr = &uvd_v1_0_set_wptr, 1623 }; 1624 1625 static struct radeon_asic cayman_asic = { 1626 .init = &cayman_init, 1627 .fini = &cayman_fini, 1628 .suspend = &cayman_suspend, 1629 .resume = &cayman_resume, 1630 .asic_reset = &cayman_asic_reset, 1631 .vga_set_state = &r600_vga_set_state, 1632 .mmio_hdp_flush = r600_mmio_hdp_flush, 1633 .gui_idle = &r600_gui_idle, 1634 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1635 .get_xclk = &rv770_get_xclk, 1636 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1637 .gart = { 1638 .tlb_flush = &cayman_pcie_gart_tlb_flush, 1639 .get_page_entry = &rs600_gart_get_page_entry, 1640 .set_page = &rs600_gart_set_page, 1641 }, 1642 .vm = { 1643 .init = &cayman_vm_init, 1644 .fini = &cayman_vm_fini, 1645 .copy_pages = &cayman_dma_vm_copy_pages, 1646 .write_pages = &cayman_dma_vm_write_pages, 1647 .set_pages = &cayman_dma_vm_set_pages, 1648 .pad_ib = &cayman_dma_vm_pad_ib, 1649 }, 1650 .ring = { 1651 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring, 1652 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring, 1653 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring, 1654 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring, 1655 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring, 1656 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, 1657 }, 1658 .irq = { 1659 .set = &evergreen_irq_set, 1660 .process = &evergreen_irq_process, 1661 }, 1662 .display = { 1663 .bandwidth_update = &evergreen_bandwidth_update, 1664 .get_vblank_counter = &evergreen_get_vblank_counter, 1665 .wait_for_vblank = &dce4_wait_for_vblank, 1666 .set_backlight_level = &atombios_set_backlight_level, 1667 .get_backlight_level = &atombios_get_backlight_level, 1668 }, 1669 .copy = { 1670 .blit = &r600_copy_cpdma, 1671 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1672 .dma = &evergreen_copy_dma, 1673 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1674 .copy = &evergreen_copy_dma, 1675 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1676 }, 1677 .surface = { 1678 .set_reg = r600_set_surface_reg, 1679 .clear_reg = r600_clear_surface_reg, 1680 }, 1681 .hpd = { 1682 .init = &evergreen_hpd_init, 1683 .fini = &evergreen_hpd_fini, 1684 .sense = &evergreen_hpd_sense, 1685 .set_polarity = &evergreen_hpd_set_polarity, 1686 }, 1687 .pm = { 1688 .misc = &evergreen_pm_misc, 1689 .prepare = &evergreen_pm_prepare, 1690 .finish = &evergreen_pm_finish, 1691 .init_profile = &btc_pm_init_profile, 1692 .get_dynpm_state = &r600_pm_get_dynpm_state, 1693 .get_engine_clock = &radeon_atom_get_engine_clock, 1694 .set_engine_clock = &radeon_atom_set_engine_clock, 1695 .get_memory_clock = &radeon_atom_get_memory_clock, 1696 .set_memory_clock = &radeon_atom_set_memory_clock, 1697 .get_pcie_lanes = &r600_get_pcie_lanes, 1698 .set_pcie_lanes = &r600_set_pcie_lanes, 1699 .set_clock_gating = NULL, 1700 .set_uvd_clocks = &evergreen_set_uvd_clocks, 1701 .get_temperature = &evergreen_get_temp, 1702 }, 1703 .dpm = { 1704 .init = &ni_dpm_init, 1705 .setup_asic = &ni_dpm_setup_asic, 1706 .enable = &ni_dpm_enable, 1707 .late_enable = &rv770_dpm_late_enable, 1708 .disable = &ni_dpm_disable, 1709 .pre_set_power_state = &ni_dpm_pre_set_power_state, 1710 .set_power_state = &ni_dpm_set_power_state, 1711 .post_set_power_state = &ni_dpm_post_set_power_state, 1712 .display_configuration_changed = &cypress_dpm_display_configuration_changed, 1713 .fini = &ni_dpm_fini, 1714 .get_sclk = &ni_dpm_get_sclk, 1715 .get_mclk = &ni_dpm_get_mclk, 1716 .print_power_state = &ni_dpm_print_power_state, 1717 .debugfs_print_current_performance_level = &ni_dpm_debugfs_print_current_performance_level, 1718 .force_performance_level = &ni_dpm_force_performance_level, 1719 .vblank_too_short = &ni_dpm_vblank_too_short, 1720 }, 1721 .pflip = { 1722 .page_flip = &evergreen_page_flip, 1723 .page_flip_pending = &evergreen_page_flip_pending, 1724 }, 1725 }; 1726 1727 static struct radeon_asic trinity_asic = { 1728 .init = &cayman_init, 1729 .fini = &cayman_fini, 1730 .suspend = &cayman_suspend, 1731 .resume = &cayman_resume, 1732 .asic_reset = &cayman_asic_reset, 1733 .vga_set_state = &r600_vga_set_state, 1734 .mmio_hdp_flush = r600_mmio_hdp_flush, 1735 .gui_idle = &r600_gui_idle, 1736 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1737 .get_xclk = &r600_get_xclk, 1738 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1739 .gart = { 1740 .tlb_flush = &cayman_pcie_gart_tlb_flush, 1741 .get_page_entry = &rs600_gart_get_page_entry, 1742 .set_page = &rs600_gart_set_page, 1743 }, 1744 .vm = { 1745 .init = &cayman_vm_init, 1746 .fini = &cayman_vm_fini, 1747 .copy_pages = &cayman_dma_vm_copy_pages, 1748 .write_pages = &cayman_dma_vm_write_pages, 1749 .set_pages = &cayman_dma_vm_set_pages, 1750 .pad_ib = &cayman_dma_vm_pad_ib, 1751 }, 1752 .ring = { 1753 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring, 1754 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring, 1755 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring, 1756 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring, 1757 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring, 1758 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, 1759 }, 1760 .irq = { 1761 .set = &evergreen_irq_set, 1762 .process = &evergreen_irq_process, 1763 }, 1764 .display = { 1765 .bandwidth_update = &dce6_bandwidth_update, 1766 .get_vblank_counter = &evergreen_get_vblank_counter, 1767 .wait_for_vblank = &dce4_wait_for_vblank, 1768 .set_backlight_level = &atombios_set_backlight_level, 1769 .get_backlight_level = &atombios_get_backlight_level, 1770 }, 1771 .copy = { 1772 .blit = &r600_copy_cpdma, 1773 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1774 .dma = &evergreen_copy_dma, 1775 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1776 .copy = &evergreen_copy_dma, 1777 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1778 }, 1779 .surface = { 1780 .set_reg = r600_set_surface_reg, 1781 .clear_reg = r600_clear_surface_reg, 1782 }, 1783 .hpd = { 1784 .init = &evergreen_hpd_init, 1785 .fini = &evergreen_hpd_fini, 1786 .sense = &evergreen_hpd_sense, 1787 .set_polarity = &evergreen_hpd_set_polarity, 1788 }, 1789 .pm = { 1790 .misc = &evergreen_pm_misc, 1791 .prepare = &evergreen_pm_prepare, 1792 .finish = &evergreen_pm_finish, 1793 .init_profile = &sumo_pm_init_profile, 1794 .get_dynpm_state = &r600_pm_get_dynpm_state, 1795 .get_engine_clock = &radeon_atom_get_engine_clock, 1796 .set_engine_clock = &radeon_atom_set_engine_clock, 1797 .get_memory_clock = NULL, 1798 .set_memory_clock = NULL, 1799 .get_pcie_lanes = NULL, 1800 .set_pcie_lanes = NULL, 1801 .set_clock_gating = NULL, 1802 .set_uvd_clocks = &sumo_set_uvd_clocks, 1803 .get_temperature = &tn_get_temp, 1804 }, 1805 .dpm = { 1806 .init = &trinity_dpm_init, 1807 .setup_asic = &trinity_dpm_setup_asic, 1808 .enable = &trinity_dpm_enable, 1809 .late_enable = &trinity_dpm_late_enable, 1810 .disable = &trinity_dpm_disable, 1811 .pre_set_power_state = &trinity_dpm_pre_set_power_state, 1812 .set_power_state = &trinity_dpm_set_power_state, 1813 .post_set_power_state = &trinity_dpm_post_set_power_state, 1814 .display_configuration_changed = &trinity_dpm_display_configuration_changed, 1815 .fini = &trinity_dpm_fini, 1816 .get_sclk = &trinity_dpm_get_sclk, 1817 .get_mclk = &trinity_dpm_get_mclk, 1818 .print_power_state = &trinity_dpm_print_power_state, 1819 .debugfs_print_current_performance_level = &trinity_dpm_debugfs_print_current_performance_level, 1820 .force_performance_level = &trinity_dpm_force_performance_level, 1821 .enable_bapm = &trinity_dpm_enable_bapm, 1822 }, 1823 .pflip = { 1824 .page_flip = &evergreen_page_flip, 1825 .page_flip_pending = &evergreen_page_flip_pending, 1826 }, 1827 }; 1828 1829 static struct radeon_asic_ring si_gfx_ring = { 1830 .ib_execute = &si_ring_ib_execute, 1831 .ib_parse = &si_ib_parse, 1832 .emit_fence = &si_fence_ring_emit, 1833 .emit_semaphore = &r600_semaphore_ring_emit, 1834 .cs_parse = NULL, 1835 .ring_test = &r600_ring_test, 1836 .ib_test = &r600_ib_test, 1837 .is_lockup = &si_gfx_is_lockup, 1838 .vm_flush = &si_vm_flush, 1839 .get_rptr = &cayman_gfx_get_rptr, 1840 .get_wptr = &cayman_gfx_get_wptr, 1841 .set_wptr = &cayman_gfx_set_wptr, 1842 }; 1843 1844 static struct radeon_asic_ring si_dma_ring = { 1845 .ib_execute = &cayman_dma_ring_ib_execute, 1846 .ib_parse = &evergreen_dma_ib_parse, 1847 .emit_fence = &evergreen_dma_fence_ring_emit, 1848 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1849 .cs_parse = NULL, 1850 .ring_test = &r600_dma_ring_test, 1851 .ib_test = &r600_dma_ib_test, 1852 .is_lockup = &si_dma_is_lockup, 1853 .vm_flush = &si_dma_vm_flush, 1854 .get_rptr = &cayman_dma_get_rptr, 1855 .get_wptr = &cayman_dma_get_wptr, 1856 .set_wptr = &cayman_dma_set_wptr, 1857 }; 1858 1859 static struct radeon_asic si_asic = { 1860 .init = &si_init, 1861 .fini = &si_fini, 1862 .suspend = &si_suspend, 1863 .resume = &si_resume, 1864 .asic_reset = &si_asic_reset, 1865 .vga_set_state = &r600_vga_set_state, 1866 .mmio_hdp_flush = r600_mmio_hdp_flush, 1867 .gui_idle = &r600_gui_idle, 1868 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1869 .get_xclk = &si_get_xclk, 1870 .get_gpu_clock_counter = &si_get_gpu_clock_counter, 1871 .gart = { 1872 .tlb_flush = &si_pcie_gart_tlb_flush, 1873 .get_page_entry = &rs600_gart_get_page_entry, 1874 .set_page = &rs600_gart_set_page, 1875 }, 1876 .vm = { 1877 .init = &si_vm_init, 1878 .fini = &si_vm_fini, 1879 .copy_pages = &si_dma_vm_copy_pages, 1880 .write_pages = &si_dma_vm_write_pages, 1881 .set_pages = &si_dma_vm_set_pages, 1882 .pad_ib = &cayman_dma_vm_pad_ib, 1883 }, 1884 .ring = { 1885 [RADEON_RING_TYPE_GFX_INDEX] = &si_gfx_ring, 1886 [CAYMAN_RING_TYPE_CP1_INDEX] = &si_gfx_ring, 1887 [CAYMAN_RING_TYPE_CP2_INDEX] = &si_gfx_ring, 1888 [R600_RING_TYPE_DMA_INDEX] = &si_dma_ring, 1889 [CAYMAN_RING_TYPE_DMA1_INDEX] = &si_dma_ring, 1890 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, 1891 }, 1892 .irq = { 1893 .set = &si_irq_set, 1894 .process = &si_irq_process, 1895 }, 1896 .display = { 1897 .bandwidth_update = &dce6_bandwidth_update, 1898 .get_vblank_counter = &evergreen_get_vblank_counter, 1899 .wait_for_vblank = &dce4_wait_for_vblank, 1900 .set_backlight_level = &atombios_set_backlight_level, 1901 .get_backlight_level = &atombios_get_backlight_level, 1902 }, 1903 .copy = { 1904 .blit = &r600_copy_cpdma, 1905 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1906 .dma = &si_copy_dma, 1907 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1908 .copy = &si_copy_dma, 1909 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1910 }, 1911 .surface = { 1912 .set_reg = r600_set_surface_reg, 1913 .clear_reg = r600_clear_surface_reg, 1914 }, 1915 .hpd = { 1916 .init = &evergreen_hpd_init, 1917 .fini = &evergreen_hpd_fini, 1918 .sense = &evergreen_hpd_sense, 1919 .set_polarity = &evergreen_hpd_set_polarity, 1920 }, 1921 .pm = { 1922 .misc = &evergreen_pm_misc, 1923 .prepare = &evergreen_pm_prepare, 1924 .finish = &evergreen_pm_finish, 1925 .init_profile = &sumo_pm_init_profile, 1926 .get_dynpm_state = &r600_pm_get_dynpm_state, 1927 .get_engine_clock = &radeon_atom_get_engine_clock, 1928 .set_engine_clock = &radeon_atom_set_engine_clock, 1929 .get_memory_clock = &radeon_atom_get_memory_clock, 1930 .set_memory_clock = &radeon_atom_set_memory_clock, 1931 .get_pcie_lanes = &r600_get_pcie_lanes, 1932 .set_pcie_lanes = &r600_set_pcie_lanes, 1933 .set_clock_gating = NULL, 1934 .set_uvd_clocks = &si_set_uvd_clocks, 1935 .get_temperature = &si_get_temp, 1936 }, 1937 .dpm = { 1938 .init = &si_dpm_init, 1939 .setup_asic = &si_dpm_setup_asic, 1940 .enable = &si_dpm_enable, 1941 .late_enable = &si_dpm_late_enable, 1942 .disable = &si_dpm_disable, 1943 .pre_set_power_state = &si_dpm_pre_set_power_state, 1944 .set_power_state = &si_dpm_set_power_state, 1945 .post_set_power_state = &si_dpm_post_set_power_state, 1946 .display_configuration_changed = &si_dpm_display_configuration_changed, 1947 .fini = &si_dpm_fini, 1948 .get_sclk = &ni_dpm_get_sclk, 1949 .get_mclk = &ni_dpm_get_mclk, 1950 .print_power_state = &ni_dpm_print_power_state, 1951 .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level, 1952 .force_performance_level = &si_dpm_force_performance_level, 1953 .vblank_too_short = &ni_dpm_vblank_too_short, 1954 .fan_ctrl_set_mode = &si_fan_ctrl_set_mode, 1955 .fan_ctrl_get_mode = &si_fan_ctrl_get_mode, 1956 .get_fan_speed_percent = &si_fan_ctrl_get_fan_speed_percent, 1957 .set_fan_speed_percent = &si_fan_ctrl_set_fan_speed_percent, 1958 }, 1959 .pflip = { 1960 .page_flip = &evergreen_page_flip, 1961 .page_flip_pending = &evergreen_page_flip_pending, 1962 }, 1963 }; 1964 1965 static struct radeon_asic_ring ci_gfx_ring = { 1966 .ib_execute = &cik_ring_ib_execute, 1967 .ib_parse = &cik_ib_parse, 1968 .emit_fence = &cik_fence_gfx_ring_emit, 1969 .emit_semaphore = &cik_semaphore_ring_emit, 1970 .cs_parse = NULL, 1971 .ring_test = &cik_ring_test, 1972 .ib_test = &cik_ib_test, 1973 .is_lockup = &cik_gfx_is_lockup, 1974 .vm_flush = &cik_vm_flush, 1975 .get_rptr = &cik_gfx_get_rptr, 1976 .get_wptr = &cik_gfx_get_wptr, 1977 .set_wptr = &cik_gfx_set_wptr, 1978 }; 1979 1980 static struct radeon_asic_ring ci_cp_ring = { 1981 .ib_execute = &cik_ring_ib_execute, 1982 .ib_parse = &cik_ib_parse, 1983 .emit_fence = &cik_fence_compute_ring_emit, 1984 .emit_semaphore = &cik_semaphore_ring_emit, 1985 .cs_parse = NULL, 1986 .ring_test = &cik_ring_test, 1987 .ib_test = &cik_ib_test, 1988 .is_lockup = &cik_gfx_is_lockup, 1989 .vm_flush = &cik_vm_flush, 1990 .get_rptr = &cik_compute_get_rptr, 1991 .get_wptr = &cik_compute_get_wptr, 1992 .set_wptr = &cik_compute_set_wptr, 1993 }; 1994 1995 static struct radeon_asic_ring ci_dma_ring = { 1996 .ib_execute = &cik_sdma_ring_ib_execute, 1997 .ib_parse = &cik_ib_parse, 1998 .emit_fence = &cik_sdma_fence_ring_emit, 1999 .emit_semaphore = &cik_sdma_semaphore_ring_emit, 2000 .cs_parse = NULL, 2001 .ring_test = &cik_sdma_ring_test, 2002 .ib_test = &cik_sdma_ib_test, 2003 .is_lockup = &cik_sdma_is_lockup, 2004 .vm_flush = &cik_dma_vm_flush, 2005 .get_rptr = &cik_sdma_get_rptr, 2006 .get_wptr = &cik_sdma_get_wptr, 2007 .set_wptr = &cik_sdma_set_wptr, 2008 }; 2009 2010 static struct radeon_asic_ring ci_vce_ring = { 2011 .ib_execute = &radeon_vce_ib_execute, 2012 .emit_fence = &radeon_vce_fence_emit, 2013 .emit_semaphore = &radeon_vce_semaphore_emit, 2014 .cs_parse = &radeon_vce_cs_parse, 2015 .ring_test = &radeon_vce_ring_test, 2016 .ib_test = &radeon_vce_ib_test, 2017 .is_lockup = &radeon_ring_test_lockup, 2018 .get_rptr = &vce_v1_0_get_rptr, 2019 .get_wptr = &vce_v1_0_get_wptr, 2020 .set_wptr = &vce_v1_0_set_wptr, 2021 }; 2022 2023 static struct radeon_asic ci_asic = { 2024 .init = &cik_init, 2025 .fini = &cik_fini, 2026 .suspend = &cik_suspend, 2027 .resume = &cik_resume, 2028 .asic_reset = &cik_asic_reset, 2029 .vga_set_state = &r600_vga_set_state, 2030 .mmio_hdp_flush = &r600_mmio_hdp_flush, 2031 .gui_idle = &r600_gui_idle, 2032 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 2033 .get_xclk = &cik_get_xclk, 2034 .get_gpu_clock_counter = &cik_get_gpu_clock_counter, 2035 .gart = { 2036 .tlb_flush = &cik_pcie_gart_tlb_flush, 2037 .get_page_entry = &rs600_gart_get_page_entry, 2038 .set_page = &rs600_gart_set_page, 2039 }, 2040 .vm = { 2041 .init = &cik_vm_init, 2042 .fini = &cik_vm_fini, 2043 .copy_pages = &cik_sdma_vm_copy_pages, 2044 .write_pages = &cik_sdma_vm_write_pages, 2045 .set_pages = &cik_sdma_vm_set_pages, 2046 .pad_ib = &cik_sdma_vm_pad_ib, 2047 }, 2048 .ring = { 2049 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring, 2050 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring, 2051 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring, 2052 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring, 2053 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring, 2054 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, 2055 [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring, 2056 [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring, 2057 }, 2058 .irq = { 2059 .set = &cik_irq_set, 2060 .process = &cik_irq_process, 2061 }, 2062 .display = { 2063 .bandwidth_update = &dce8_bandwidth_update, 2064 .get_vblank_counter = &evergreen_get_vblank_counter, 2065 .wait_for_vblank = &dce4_wait_for_vblank, 2066 .set_backlight_level = &atombios_set_backlight_level, 2067 .get_backlight_level = &atombios_get_backlight_level, 2068 }, 2069 .copy = { 2070 .blit = &cik_copy_cpdma, 2071 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 2072 .dma = &cik_copy_dma, 2073 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 2074 .copy = &cik_copy_dma, 2075 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 2076 }, 2077 .surface = { 2078 .set_reg = r600_set_surface_reg, 2079 .clear_reg = r600_clear_surface_reg, 2080 }, 2081 .hpd = { 2082 .init = &evergreen_hpd_init, 2083 .fini = &evergreen_hpd_fini, 2084 .sense = &evergreen_hpd_sense, 2085 .set_polarity = &evergreen_hpd_set_polarity, 2086 }, 2087 .pm = { 2088 .misc = &evergreen_pm_misc, 2089 .prepare = &evergreen_pm_prepare, 2090 .finish = &evergreen_pm_finish, 2091 .init_profile = &sumo_pm_init_profile, 2092 .get_dynpm_state = &r600_pm_get_dynpm_state, 2093 .get_engine_clock = &radeon_atom_get_engine_clock, 2094 .set_engine_clock = &radeon_atom_set_engine_clock, 2095 .get_memory_clock = &radeon_atom_get_memory_clock, 2096 .set_memory_clock = &radeon_atom_set_memory_clock, 2097 .get_pcie_lanes = NULL, 2098 .set_pcie_lanes = NULL, 2099 .set_clock_gating = NULL, 2100 .set_uvd_clocks = &cik_set_uvd_clocks, 2101 .set_vce_clocks = &cik_set_vce_clocks, 2102 .get_temperature = &ci_get_temp, 2103 }, 2104 .dpm = { 2105 .init = &ci_dpm_init, 2106 .setup_asic = &ci_dpm_setup_asic, 2107 .enable = &ci_dpm_enable, 2108 .late_enable = &ci_dpm_late_enable, 2109 .disable = &ci_dpm_disable, 2110 .pre_set_power_state = &ci_dpm_pre_set_power_state, 2111 .set_power_state = &ci_dpm_set_power_state, 2112 .post_set_power_state = &ci_dpm_post_set_power_state, 2113 .display_configuration_changed = &ci_dpm_display_configuration_changed, 2114 .fini = &ci_dpm_fini, 2115 .get_sclk = &ci_dpm_get_sclk, 2116 .get_mclk = &ci_dpm_get_mclk, 2117 .print_power_state = &ci_dpm_print_power_state, 2118 .debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level, 2119 .force_performance_level = &ci_dpm_force_performance_level, 2120 .vblank_too_short = &ci_dpm_vblank_too_short, 2121 .powergate_uvd = &ci_dpm_powergate_uvd, 2122 .fan_ctrl_set_mode = &ci_fan_ctrl_set_mode, 2123 .fan_ctrl_get_mode = &ci_fan_ctrl_get_mode, 2124 .get_fan_speed_percent = &ci_fan_ctrl_get_fan_speed_percent, 2125 .set_fan_speed_percent = &ci_fan_ctrl_set_fan_speed_percent, 2126 }, 2127 .pflip = { 2128 .page_flip = &evergreen_page_flip, 2129 .page_flip_pending = &evergreen_page_flip_pending, 2130 }, 2131 }; 2132 2133 static struct radeon_asic kv_asic = { 2134 .init = &cik_init, 2135 .fini = &cik_fini, 2136 .suspend = &cik_suspend, 2137 .resume = &cik_resume, 2138 .asic_reset = &cik_asic_reset, 2139 .vga_set_state = &r600_vga_set_state, 2140 .mmio_hdp_flush = &r600_mmio_hdp_flush, 2141 .gui_idle = &r600_gui_idle, 2142 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 2143 .get_xclk = &cik_get_xclk, 2144 .get_gpu_clock_counter = &cik_get_gpu_clock_counter, 2145 .gart = { 2146 .tlb_flush = &cik_pcie_gart_tlb_flush, 2147 .get_page_entry = &rs600_gart_get_page_entry, 2148 .set_page = &rs600_gart_set_page, 2149 }, 2150 .vm = { 2151 .init = &cik_vm_init, 2152 .fini = &cik_vm_fini, 2153 .copy_pages = &cik_sdma_vm_copy_pages, 2154 .write_pages = &cik_sdma_vm_write_pages, 2155 .set_pages = &cik_sdma_vm_set_pages, 2156 .pad_ib = &cik_sdma_vm_pad_ib, 2157 }, 2158 .ring = { 2159 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring, 2160 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring, 2161 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring, 2162 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring, 2163 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring, 2164 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, 2165 [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring, 2166 [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring, 2167 }, 2168 .irq = { 2169 .set = &cik_irq_set, 2170 .process = &cik_irq_process, 2171 }, 2172 .display = { 2173 .bandwidth_update = &dce8_bandwidth_update, 2174 .get_vblank_counter = &evergreen_get_vblank_counter, 2175 .wait_for_vblank = &dce4_wait_for_vblank, 2176 .set_backlight_level = &atombios_set_backlight_level, 2177 .get_backlight_level = &atombios_get_backlight_level, 2178 }, 2179 .copy = { 2180 .blit = &cik_copy_cpdma, 2181 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 2182 .dma = &cik_copy_dma, 2183 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 2184 .copy = &cik_copy_dma, 2185 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 2186 }, 2187 .surface = { 2188 .set_reg = r600_set_surface_reg, 2189 .clear_reg = r600_clear_surface_reg, 2190 }, 2191 .hpd = { 2192 .init = &evergreen_hpd_init, 2193 .fini = &evergreen_hpd_fini, 2194 .sense = &evergreen_hpd_sense, 2195 .set_polarity = &evergreen_hpd_set_polarity, 2196 }, 2197 .pm = { 2198 .misc = &evergreen_pm_misc, 2199 .prepare = &evergreen_pm_prepare, 2200 .finish = &evergreen_pm_finish, 2201 .init_profile = &sumo_pm_init_profile, 2202 .get_dynpm_state = &r600_pm_get_dynpm_state, 2203 .get_engine_clock = &radeon_atom_get_engine_clock, 2204 .set_engine_clock = &radeon_atom_set_engine_clock, 2205 .get_memory_clock = &radeon_atom_get_memory_clock, 2206 .set_memory_clock = &radeon_atom_set_memory_clock, 2207 .get_pcie_lanes = NULL, 2208 .set_pcie_lanes = NULL, 2209 .set_clock_gating = NULL, 2210 .set_uvd_clocks = &cik_set_uvd_clocks, 2211 .set_vce_clocks = &cik_set_vce_clocks, 2212 .get_temperature = &kv_get_temp, 2213 }, 2214 .dpm = { 2215 .init = &kv_dpm_init, 2216 .setup_asic = &kv_dpm_setup_asic, 2217 .enable = &kv_dpm_enable, 2218 .late_enable = &kv_dpm_late_enable, 2219 .disable = &kv_dpm_disable, 2220 .pre_set_power_state = &kv_dpm_pre_set_power_state, 2221 .set_power_state = &kv_dpm_set_power_state, 2222 .post_set_power_state = &kv_dpm_post_set_power_state, 2223 .display_configuration_changed = &kv_dpm_display_configuration_changed, 2224 .fini = &kv_dpm_fini, 2225 .get_sclk = &kv_dpm_get_sclk, 2226 .get_mclk = &kv_dpm_get_mclk, 2227 .print_power_state = &kv_dpm_print_power_state, 2228 .debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level, 2229 .force_performance_level = &kv_dpm_force_performance_level, 2230 .powergate_uvd = &kv_dpm_powergate_uvd, 2231 .enable_bapm = &kv_dpm_enable_bapm, 2232 }, 2233 .pflip = { 2234 .page_flip = &evergreen_page_flip, 2235 .page_flip_pending = &evergreen_page_flip_pending, 2236 }, 2237 }; 2238 2239 /** 2240 * radeon_asic_init - register asic specific callbacks 2241 * 2242 * @rdev: radeon device pointer 2243 * 2244 * Registers the appropriate asic specific callbacks for each 2245 * chip family. Also sets other asics specific info like the number 2246 * of crtcs and the register aperture accessors (all asics). 2247 * Returns 0 for success. 2248 */ 2249 int radeon_asic_init(struct radeon_device *rdev) 2250 { 2251 radeon_register_accessor_init(rdev); 2252 2253 /* set the number of crtcs */ 2254 if (rdev->flags & RADEON_SINGLE_CRTC) 2255 rdev->num_crtc = 1; 2256 else 2257 rdev->num_crtc = 2; 2258 2259 rdev->has_uvd = false; 2260 2261 switch (rdev->family) { 2262 case CHIP_R100: 2263 case CHIP_RV100: 2264 case CHIP_RS100: 2265 case CHIP_RV200: 2266 case CHIP_RS200: 2267 rdev->asic = &r100_asic; 2268 break; 2269 case CHIP_R200: 2270 case CHIP_RV250: 2271 case CHIP_RS300: 2272 case CHIP_RV280: 2273 rdev->asic = &r200_asic; 2274 break; 2275 case CHIP_R300: 2276 case CHIP_R350: 2277 case CHIP_RV350: 2278 case CHIP_RV380: 2279 if (rdev->flags & RADEON_IS_PCIE) 2280 rdev->asic = &r300_asic_pcie; 2281 else 2282 rdev->asic = &r300_asic; 2283 break; 2284 case CHIP_R420: 2285 case CHIP_R423: 2286 case CHIP_RV410: 2287 rdev->asic = &r420_asic; 2288 /* handle macs */ 2289 if (rdev->bios == NULL) { 2290 rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock; 2291 rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock; 2292 rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock; 2293 rdev->asic->pm.set_memory_clock = NULL; 2294 rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level; 2295 } 2296 break; 2297 case CHIP_RS400: 2298 case CHIP_RS480: 2299 rdev->asic = &rs400_asic; 2300 break; 2301 case CHIP_RS600: 2302 rdev->asic = &rs600_asic; 2303 break; 2304 case CHIP_RS690: 2305 case CHIP_RS740: 2306 rdev->asic = &rs690_asic; 2307 break; 2308 case CHIP_RV515: 2309 rdev->asic = &rv515_asic; 2310 break; 2311 case CHIP_R520: 2312 case CHIP_RV530: 2313 case CHIP_RV560: 2314 case CHIP_RV570: 2315 case CHIP_R580: 2316 rdev->asic = &r520_asic; 2317 break; 2318 case CHIP_R600: 2319 rdev->asic = &r600_asic; 2320 break; 2321 case CHIP_RV610: 2322 case CHIP_RV630: 2323 case CHIP_RV620: 2324 case CHIP_RV635: 2325 case CHIP_RV670: 2326 rdev->asic = &rv6xx_asic; 2327 rdev->has_uvd = true; 2328 break; 2329 case CHIP_RS780: 2330 case CHIP_RS880: 2331 rdev->asic = &rs780_asic; 2332 /* 760G/780V/880V don't have UVD */ 2333 if ((rdev->pdev->device == 0x9616)|| 2334 (rdev->pdev->device == 0x9611)|| 2335 (rdev->pdev->device == 0x9613)|| 2336 (rdev->pdev->device == 0x9711)|| 2337 (rdev->pdev->device == 0x9713)) 2338 rdev->has_uvd = false; 2339 else 2340 rdev->has_uvd = true; 2341 break; 2342 case CHIP_RV770: 2343 case CHIP_RV730: 2344 case CHIP_RV710: 2345 case CHIP_RV740: 2346 rdev->asic = &rv770_asic; 2347 rdev->has_uvd = true; 2348 break; 2349 case CHIP_CEDAR: 2350 case CHIP_REDWOOD: 2351 case CHIP_JUNIPER: 2352 case CHIP_CYPRESS: 2353 case CHIP_HEMLOCK: 2354 /* set num crtcs */ 2355 if (rdev->family == CHIP_CEDAR) 2356 rdev->num_crtc = 4; 2357 else 2358 rdev->num_crtc = 6; 2359 rdev->asic = &evergreen_asic; 2360 rdev->has_uvd = true; 2361 break; 2362 case CHIP_PALM: 2363 case CHIP_SUMO: 2364 case CHIP_SUMO2: 2365 rdev->asic = &sumo_asic; 2366 rdev->has_uvd = true; 2367 break; 2368 case CHIP_BARTS: 2369 case CHIP_TURKS: 2370 case CHIP_CAICOS: 2371 /* set num crtcs */ 2372 if (rdev->family == CHIP_CAICOS) 2373 rdev->num_crtc = 4; 2374 else 2375 rdev->num_crtc = 6; 2376 rdev->asic = &btc_asic; 2377 rdev->has_uvd = true; 2378 break; 2379 case CHIP_CAYMAN: 2380 rdev->asic = &cayman_asic; 2381 /* set num crtcs */ 2382 rdev->num_crtc = 6; 2383 rdev->has_uvd = true; 2384 break; 2385 case CHIP_ARUBA: 2386 rdev->asic = &trinity_asic; 2387 /* set num crtcs */ 2388 rdev->num_crtc = 4; 2389 rdev->has_uvd = true; 2390 break; 2391 case CHIP_TAHITI: 2392 case CHIP_PITCAIRN: 2393 case CHIP_VERDE: 2394 case CHIP_OLAND: 2395 case CHIP_HAINAN: 2396 rdev->asic = &si_asic; 2397 /* set num crtcs */ 2398 if (rdev->family == CHIP_HAINAN) 2399 rdev->num_crtc = 0; 2400 else if (rdev->family == CHIP_OLAND) 2401 rdev->num_crtc = 2; 2402 else 2403 rdev->num_crtc = 6; 2404 if (rdev->family == CHIP_HAINAN) 2405 rdev->has_uvd = false; 2406 else 2407 rdev->has_uvd = true; 2408 switch (rdev->family) { 2409 case CHIP_TAHITI: 2410 rdev->cg_flags = 2411 RADEON_CG_SUPPORT_GFX_MGCG | 2412 RADEON_CG_SUPPORT_GFX_MGLS | 2413 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2414 RADEON_CG_SUPPORT_GFX_CGLS | 2415 RADEON_CG_SUPPORT_GFX_CGTS | 2416 RADEON_CG_SUPPORT_GFX_CP_LS | 2417 RADEON_CG_SUPPORT_MC_MGCG | 2418 RADEON_CG_SUPPORT_SDMA_MGCG | 2419 RADEON_CG_SUPPORT_BIF_LS | 2420 RADEON_CG_SUPPORT_VCE_MGCG | 2421 RADEON_CG_SUPPORT_UVD_MGCG | 2422 RADEON_CG_SUPPORT_HDP_LS | 2423 RADEON_CG_SUPPORT_HDP_MGCG; 2424 rdev->pg_flags = 0; 2425 break; 2426 case CHIP_PITCAIRN: 2427 rdev->cg_flags = 2428 RADEON_CG_SUPPORT_GFX_MGCG | 2429 RADEON_CG_SUPPORT_GFX_MGLS | 2430 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2431 RADEON_CG_SUPPORT_GFX_CGLS | 2432 RADEON_CG_SUPPORT_GFX_CGTS | 2433 RADEON_CG_SUPPORT_GFX_CP_LS | 2434 RADEON_CG_SUPPORT_GFX_RLC_LS | 2435 RADEON_CG_SUPPORT_MC_LS | 2436 RADEON_CG_SUPPORT_MC_MGCG | 2437 RADEON_CG_SUPPORT_SDMA_MGCG | 2438 RADEON_CG_SUPPORT_BIF_LS | 2439 RADEON_CG_SUPPORT_VCE_MGCG | 2440 RADEON_CG_SUPPORT_UVD_MGCG | 2441 RADEON_CG_SUPPORT_HDP_LS | 2442 RADEON_CG_SUPPORT_HDP_MGCG; 2443 rdev->pg_flags = 0; 2444 break; 2445 case CHIP_VERDE: 2446 rdev->cg_flags = 2447 RADEON_CG_SUPPORT_GFX_MGCG | 2448 RADEON_CG_SUPPORT_GFX_MGLS | 2449 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2450 RADEON_CG_SUPPORT_GFX_CGLS | 2451 RADEON_CG_SUPPORT_GFX_CGTS | 2452 RADEON_CG_SUPPORT_GFX_CP_LS | 2453 RADEON_CG_SUPPORT_GFX_RLC_LS | 2454 RADEON_CG_SUPPORT_MC_LS | 2455 RADEON_CG_SUPPORT_MC_MGCG | 2456 RADEON_CG_SUPPORT_SDMA_MGCG | 2457 RADEON_CG_SUPPORT_BIF_LS | 2458 RADEON_CG_SUPPORT_VCE_MGCG | 2459 RADEON_CG_SUPPORT_UVD_MGCG | 2460 RADEON_CG_SUPPORT_HDP_LS | 2461 RADEON_CG_SUPPORT_HDP_MGCG; 2462 rdev->pg_flags = 0 | 2463 /*RADEON_PG_SUPPORT_GFX_PG | */ 2464 RADEON_PG_SUPPORT_SDMA; 2465 break; 2466 case CHIP_OLAND: 2467 rdev->cg_flags = 2468 RADEON_CG_SUPPORT_GFX_MGCG | 2469 RADEON_CG_SUPPORT_GFX_MGLS | 2470 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2471 RADEON_CG_SUPPORT_GFX_CGLS | 2472 RADEON_CG_SUPPORT_GFX_CGTS | 2473 RADEON_CG_SUPPORT_GFX_CP_LS | 2474 RADEON_CG_SUPPORT_GFX_RLC_LS | 2475 RADEON_CG_SUPPORT_MC_LS | 2476 RADEON_CG_SUPPORT_MC_MGCG | 2477 RADEON_CG_SUPPORT_SDMA_MGCG | 2478 RADEON_CG_SUPPORT_BIF_LS | 2479 RADEON_CG_SUPPORT_UVD_MGCG | 2480 RADEON_CG_SUPPORT_HDP_LS | 2481 RADEON_CG_SUPPORT_HDP_MGCG; 2482 rdev->pg_flags = 0; 2483 break; 2484 case CHIP_HAINAN: 2485 rdev->cg_flags = 2486 RADEON_CG_SUPPORT_GFX_MGCG | 2487 RADEON_CG_SUPPORT_GFX_MGLS | 2488 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2489 RADEON_CG_SUPPORT_GFX_CGLS | 2490 RADEON_CG_SUPPORT_GFX_CGTS | 2491 RADEON_CG_SUPPORT_GFX_CP_LS | 2492 RADEON_CG_SUPPORT_GFX_RLC_LS | 2493 RADEON_CG_SUPPORT_MC_LS | 2494 RADEON_CG_SUPPORT_MC_MGCG | 2495 RADEON_CG_SUPPORT_SDMA_MGCG | 2496 RADEON_CG_SUPPORT_BIF_LS | 2497 RADEON_CG_SUPPORT_HDP_LS | 2498 RADEON_CG_SUPPORT_HDP_MGCG; 2499 rdev->pg_flags = 0; 2500 break; 2501 default: 2502 rdev->cg_flags = 0; 2503 rdev->pg_flags = 0; 2504 break; 2505 } 2506 break; 2507 case CHIP_BONAIRE: 2508 case CHIP_HAWAII: 2509 rdev->asic = &ci_asic; 2510 rdev->num_crtc = 6; 2511 rdev->has_uvd = true; 2512 if (rdev->family == CHIP_BONAIRE) { 2513 rdev->cg_flags = 2514 RADEON_CG_SUPPORT_GFX_MGCG | 2515 RADEON_CG_SUPPORT_GFX_MGLS | 2516 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2517 RADEON_CG_SUPPORT_GFX_CGLS | 2518 RADEON_CG_SUPPORT_GFX_CGTS | 2519 RADEON_CG_SUPPORT_GFX_CGTS_LS | 2520 RADEON_CG_SUPPORT_GFX_CP_LS | 2521 RADEON_CG_SUPPORT_MC_LS | 2522 RADEON_CG_SUPPORT_MC_MGCG | 2523 RADEON_CG_SUPPORT_SDMA_MGCG | 2524 RADEON_CG_SUPPORT_SDMA_LS | 2525 RADEON_CG_SUPPORT_BIF_LS | 2526 RADEON_CG_SUPPORT_VCE_MGCG | 2527 RADEON_CG_SUPPORT_UVD_MGCG | 2528 RADEON_CG_SUPPORT_HDP_LS | 2529 RADEON_CG_SUPPORT_HDP_MGCG; 2530 rdev->pg_flags = 0; 2531 } else { 2532 rdev->cg_flags = 2533 RADEON_CG_SUPPORT_GFX_MGCG | 2534 RADEON_CG_SUPPORT_GFX_MGLS | 2535 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2536 RADEON_CG_SUPPORT_GFX_CGLS | 2537 RADEON_CG_SUPPORT_GFX_CGTS | 2538 RADEON_CG_SUPPORT_GFX_CP_LS | 2539 RADEON_CG_SUPPORT_MC_LS | 2540 RADEON_CG_SUPPORT_MC_MGCG | 2541 RADEON_CG_SUPPORT_SDMA_MGCG | 2542 RADEON_CG_SUPPORT_SDMA_LS | 2543 RADEON_CG_SUPPORT_BIF_LS | 2544 RADEON_CG_SUPPORT_VCE_MGCG | 2545 RADEON_CG_SUPPORT_UVD_MGCG | 2546 RADEON_CG_SUPPORT_HDP_LS | 2547 RADEON_CG_SUPPORT_HDP_MGCG; 2548 rdev->pg_flags = 0; 2549 } 2550 break; 2551 case CHIP_KAVERI: 2552 case CHIP_KABINI: 2553 case CHIP_MULLINS: 2554 rdev->asic = &kv_asic; 2555 /* set num crtcs */ 2556 if (rdev->family == CHIP_KAVERI) { 2557 rdev->num_crtc = 4; 2558 rdev->cg_flags = 2559 RADEON_CG_SUPPORT_GFX_MGCG | 2560 RADEON_CG_SUPPORT_GFX_MGLS | 2561 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2562 RADEON_CG_SUPPORT_GFX_CGLS | 2563 RADEON_CG_SUPPORT_GFX_CGTS | 2564 RADEON_CG_SUPPORT_GFX_CGTS_LS | 2565 RADEON_CG_SUPPORT_GFX_CP_LS | 2566 RADEON_CG_SUPPORT_SDMA_MGCG | 2567 RADEON_CG_SUPPORT_SDMA_LS | 2568 RADEON_CG_SUPPORT_BIF_LS | 2569 RADEON_CG_SUPPORT_VCE_MGCG | 2570 RADEON_CG_SUPPORT_UVD_MGCG | 2571 RADEON_CG_SUPPORT_HDP_LS | 2572 RADEON_CG_SUPPORT_HDP_MGCG; 2573 rdev->pg_flags = 0; 2574 /*RADEON_PG_SUPPORT_GFX_PG | 2575 RADEON_PG_SUPPORT_GFX_SMG | 2576 RADEON_PG_SUPPORT_GFX_DMG | 2577 RADEON_PG_SUPPORT_UVD | 2578 RADEON_PG_SUPPORT_VCE | 2579 RADEON_PG_SUPPORT_CP | 2580 RADEON_PG_SUPPORT_GDS | 2581 RADEON_PG_SUPPORT_RLC_SMU_HS | 2582 RADEON_PG_SUPPORT_ACP | 2583 RADEON_PG_SUPPORT_SAMU;*/ 2584 } else { 2585 rdev->num_crtc = 2; 2586 rdev->cg_flags = 2587 RADEON_CG_SUPPORT_GFX_MGCG | 2588 RADEON_CG_SUPPORT_GFX_MGLS | 2589 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2590 RADEON_CG_SUPPORT_GFX_CGLS | 2591 RADEON_CG_SUPPORT_GFX_CGTS | 2592 RADEON_CG_SUPPORT_GFX_CGTS_LS | 2593 RADEON_CG_SUPPORT_GFX_CP_LS | 2594 RADEON_CG_SUPPORT_SDMA_MGCG | 2595 RADEON_CG_SUPPORT_SDMA_LS | 2596 RADEON_CG_SUPPORT_BIF_LS | 2597 RADEON_CG_SUPPORT_VCE_MGCG | 2598 RADEON_CG_SUPPORT_UVD_MGCG | 2599 RADEON_CG_SUPPORT_HDP_LS | 2600 RADEON_CG_SUPPORT_HDP_MGCG; 2601 rdev->pg_flags = 0; 2602 /*RADEON_PG_SUPPORT_GFX_PG | 2603 RADEON_PG_SUPPORT_GFX_SMG | 2604 RADEON_PG_SUPPORT_UVD | 2605 RADEON_PG_SUPPORT_VCE | 2606 RADEON_PG_SUPPORT_CP | 2607 RADEON_PG_SUPPORT_GDS | 2608 RADEON_PG_SUPPORT_RLC_SMU_HS | 2609 RADEON_PG_SUPPORT_SAMU;*/ 2610 } 2611 rdev->has_uvd = true; 2612 break; 2613 default: 2614 /* FIXME: not supported yet */ 2615 return -EINVAL; 2616 } 2617 2618 if (rdev->flags & RADEON_IS_IGP) { 2619 rdev->asic->pm.get_memory_clock = NULL; 2620 rdev->asic->pm.set_memory_clock = NULL; 2621 } 2622 2623 return 0; 2624 } 2625 2626