1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __RADEON_H__ 29 #define __RADEON_H__ 30 31 /* TODO: Here are things that needs to be done : 32 * - surface allocator & initializer : (bit like scratch reg) should 33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings 34 * related to surface 35 * - WB : write back stuff (do it bit like scratch reg things) 36 * - Vblank : look at Jesse's rework and what we should do 37 * - r600/r700: gart & cp 38 * - cs : clean cs ioctl use bitmap & things like that. 39 * - power management stuff 40 * - Barrier in gart code 41 * - Unmappabled vram ? 42 * - TESTING, TESTING, TESTING 43 */ 44 45 /* Initialization path: 46 * We expect that acceleration initialization might fail for various 47 * reasons even thought we work hard to make it works on most 48 * configurations. In order to still have a working userspace in such 49 * situation the init path must succeed up to the memory controller 50 * initialization point. Failure before this point are considered as 51 * fatal error. Here is the init callchain : 52 * radeon_device_init perform common structure, mutex initialization 53 * asic_init setup the GPU memory layout and perform all 54 * one time initialization (failure in this 55 * function are considered fatal) 56 * asic_startup setup the GPU acceleration, in order to 57 * follow guideline the first thing this 58 * function should do is setting the GPU 59 * memory controller (only MC setup failure 60 * are considered as fatal) 61 */ 62 63 #include <linux/agp_backend.h> 64 #include <linux/atomic.h> 65 #include <linux/wait.h> 66 #include <linux/list.h> 67 #include <linux/kref.h> 68 #include <linux/interval_tree.h> 69 #include <linux/hashtable.h> 70 #include <linux/dma-fence.h> 71 72 #ifdef CONFIG_MMU_NOTIFIER 73 #include <linux/mmu_notifier.h> 74 #endif 75 76 #include <drm/ttm/ttm_bo.h> 77 #include <drm/ttm/ttm_placement.h> 78 #include <drm/ttm/ttm_execbuf_util.h> 79 80 #include <drm/drm_gem.h> 81 #include <drm/drm_audio_component.h> 82 #include <drm/drm_suballoc.h> 83 84 #include "radeon_family.h" 85 #include "radeon_mode.h" 86 #include "radeon_reg.h" 87 88 /* 89 * Modules parameters. 90 */ 91 extern int radeon_no_wb; 92 extern int radeon_modeset; 93 extern int radeon_dynclks; 94 extern int radeon_r4xx_atom; 95 extern int radeon_agpmode; 96 extern int radeon_vram_limit; 97 extern int radeon_gart_size; 98 extern int radeon_benchmarking; 99 extern int radeon_testing; 100 extern int radeon_connector_table; 101 extern int radeon_tv; 102 extern int radeon_audio; 103 extern int radeon_disp_priority; 104 extern int radeon_hw_i2c; 105 extern int radeon_pcie_gen2; 106 extern int radeon_msi; 107 extern int radeon_lockup_timeout; 108 extern int radeon_fastfb; 109 extern int radeon_dpm; 110 extern int radeon_aspm; 111 extern int radeon_runtime_pm; 112 extern int radeon_hard_reset; 113 extern int radeon_vm_size; 114 extern int radeon_vm_block_size; 115 extern int radeon_deep_color; 116 extern int radeon_use_pflipirq; 117 extern int radeon_bapm; 118 extern int radeon_backlight; 119 extern int radeon_auxch; 120 extern int radeon_uvd; 121 extern int radeon_vce; 122 extern int radeon_si_support; 123 extern int radeon_cik_support; 124 125 /* 126 * Copy from radeon_drv.h so we don't have to include both and have conflicting 127 * symbol; 128 */ 129 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 130 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) 131 #define RADEON_USEC_IB_TEST_TIMEOUT 1000000 /* 1s */ 132 /* RADEON_IB_POOL_SIZE must be a power of 2 */ 133 #define RADEON_IB_POOL_SIZE 16 134 #define RADEON_DEBUGFS_MAX_COMPONENTS 32 135 #define RADEONFB_CONN_LIMIT 4 136 #define RADEON_BIOS_NUM_SCRATCH 8 137 138 /* internal ring indices */ 139 /* r1xx+ has gfx CP ring */ 140 #define RADEON_RING_TYPE_GFX_INDEX 0 141 142 /* cayman has 2 compute CP rings */ 143 #define CAYMAN_RING_TYPE_CP1_INDEX 1 144 #define CAYMAN_RING_TYPE_CP2_INDEX 2 145 146 /* R600+ has an async dma ring */ 147 #define R600_RING_TYPE_DMA_INDEX 3 148 /* cayman add a second async dma ring */ 149 #define CAYMAN_RING_TYPE_DMA1_INDEX 4 150 151 /* R600+ */ 152 #define R600_RING_TYPE_UVD_INDEX 5 153 154 /* TN+ */ 155 #define TN_RING_TYPE_VCE1_INDEX 6 156 #define TN_RING_TYPE_VCE2_INDEX 7 157 158 /* max number of rings */ 159 #define RADEON_NUM_RINGS 8 160 161 /* number of hw syncs before falling back on blocking */ 162 #define RADEON_NUM_SYNCS 4 163 164 /* hardcode those limit for now */ 165 #define RADEON_VA_IB_OFFSET (1 << 20) 166 #define RADEON_VA_RESERVED_SIZE (8 << 20) 167 #define RADEON_IB_VM_MAX_SIZE (64 << 10) 168 169 /* hard reset data */ 170 #define RADEON_ASIC_RESET_DATA 0x39d5e86b 171 172 /* reset flags */ 173 #define RADEON_RESET_GFX (1 << 0) 174 #define RADEON_RESET_COMPUTE (1 << 1) 175 #define RADEON_RESET_DMA (1 << 2) 176 #define RADEON_RESET_CP (1 << 3) 177 #define RADEON_RESET_GRBM (1 << 4) 178 #define RADEON_RESET_DMA1 (1 << 5) 179 #define RADEON_RESET_RLC (1 << 6) 180 #define RADEON_RESET_SEM (1 << 7) 181 #define RADEON_RESET_IH (1 << 8) 182 #define RADEON_RESET_VMC (1 << 9) 183 #define RADEON_RESET_MC (1 << 10) 184 #define RADEON_RESET_DISPLAY (1 << 11) 185 186 /* CG block flags */ 187 #define RADEON_CG_BLOCK_GFX (1 << 0) 188 #define RADEON_CG_BLOCK_MC (1 << 1) 189 #define RADEON_CG_BLOCK_SDMA (1 << 2) 190 #define RADEON_CG_BLOCK_UVD (1 << 3) 191 #define RADEON_CG_BLOCK_VCE (1 << 4) 192 #define RADEON_CG_BLOCK_HDP (1 << 5) 193 #define RADEON_CG_BLOCK_BIF (1 << 6) 194 195 /* CG flags */ 196 #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0) 197 #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1) 198 #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2) 199 #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3) 200 #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4) 201 #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5) 202 #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6) 203 #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7) 204 #define RADEON_CG_SUPPORT_MC_LS (1 << 8) 205 #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9) 206 #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10) 207 #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11) 208 #define RADEON_CG_SUPPORT_BIF_LS (1 << 12) 209 #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13) 210 #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14) 211 #define RADEON_CG_SUPPORT_HDP_LS (1 << 15) 212 #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16) 213 214 /* PG flags */ 215 #define RADEON_PG_SUPPORT_GFX_PG (1 << 0) 216 #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1) 217 #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2) 218 #define RADEON_PG_SUPPORT_UVD (1 << 3) 219 #define RADEON_PG_SUPPORT_VCE (1 << 4) 220 #define RADEON_PG_SUPPORT_CP (1 << 5) 221 #define RADEON_PG_SUPPORT_GDS (1 << 6) 222 #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7) 223 #define RADEON_PG_SUPPORT_SDMA (1 << 8) 224 #define RADEON_PG_SUPPORT_ACP (1 << 9) 225 #define RADEON_PG_SUPPORT_SAMU (1 << 10) 226 227 /* max cursor sizes (in pixels) */ 228 #define CURSOR_WIDTH 64 229 #define CURSOR_HEIGHT 64 230 231 #define CIK_CURSOR_WIDTH 128 232 #define CIK_CURSOR_HEIGHT 128 233 234 /* 235 * Errata workarounds. 236 */ 237 enum radeon_pll_errata { 238 CHIP_ERRATA_R300_CG = 0x00000001, 239 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, 240 CHIP_ERRATA_PLL_DELAY = 0x00000004 241 }; 242 243 244 struct radeon_device; 245 246 247 /* 248 * BIOS. 249 */ 250 bool radeon_get_bios(struct radeon_device *rdev); 251 252 /* 253 * Dummy page 254 */ 255 struct radeon_dummy_page { 256 uint64_t entry; 257 struct page *page; 258 dma_addr_t addr; 259 }; 260 int radeon_dummy_page_init(struct radeon_device *rdev); 261 void radeon_dummy_page_fini(struct radeon_device *rdev); 262 263 264 /* 265 * Clocks 266 */ 267 struct radeon_clock { 268 struct radeon_pll p1pll; 269 struct radeon_pll p2pll; 270 struct radeon_pll dcpll; 271 struct radeon_pll spll; 272 struct radeon_pll mpll; 273 /* 10 Khz units */ 274 uint32_t default_mclk; 275 uint32_t default_sclk; 276 uint32_t default_dispclk; 277 uint32_t current_dispclk; 278 uint32_t dp_extclk; 279 uint32_t max_pixel_clock; 280 uint32_t vco_freq; 281 }; 282 283 /* 284 * Power management 285 */ 286 int radeon_pm_init(struct radeon_device *rdev); 287 int radeon_pm_late_init(struct radeon_device *rdev); 288 void radeon_pm_fini(struct radeon_device *rdev); 289 void radeon_pm_compute_clocks(struct radeon_device *rdev); 290 void radeon_pm_suspend(struct radeon_device *rdev); 291 void radeon_pm_resume(struct radeon_device *rdev); 292 void radeon_combios_get_power_modes(struct radeon_device *rdev); 293 void radeon_atombios_get_power_modes(struct radeon_device *rdev); 294 int radeon_atom_get_clock_dividers(struct radeon_device *rdev, 295 u8 clock_type, 296 u32 clock, 297 bool strobe_mode, 298 struct atom_clock_dividers *dividers); 299 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev, 300 u32 clock, 301 bool strobe_mode, 302 struct atom_mpll_param *mpll_param); 303 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); 304 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev, 305 u16 voltage_level, u8 voltage_type, 306 u32 *gpio_value, u32 *gpio_mask); 307 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev, 308 u32 eng_clock, u32 mem_clock); 309 int radeon_atom_get_voltage_step(struct radeon_device *rdev, 310 u8 voltage_type, u16 *voltage_step); 311 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 312 u16 voltage_id, u16 *voltage); 313 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev, 314 u16 *voltage, 315 u16 leakage_idx); 316 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev, 317 u16 *leakage_id); 318 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev, 319 u16 *vddc, u16 *vddci, 320 u16 virtual_voltage_id, 321 u16 vbios_voltage_id); 322 int radeon_atom_get_voltage_evv(struct radeon_device *rdev, 323 u16 virtual_voltage_id, 324 u16 *voltage); 325 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev, 326 u8 voltage_type, 327 u16 nominal_voltage, 328 u16 *true_voltage); 329 int radeon_atom_get_min_voltage(struct radeon_device *rdev, 330 u8 voltage_type, u16 *min_voltage); 331 int radeon_atom_get_max_voltage(struct radeon_device *rdev, 332 u8 voltage_type, u16 *max_voltage); 333 int radeon_atom_get_voltage_table(struct radeon_device *rdev, 334 u8 voltage_type, u8 voltage_mode, 335 struct atom_voltage_table *voltage_table); 336 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev, 337 u8 voltage_type, u8 voltage_mode); 338 int radeon_atom_get_svi2_info(struct radeon_device *rdev, 339 u8 voltage_type, 340 u8 *svd_gpio_id, u8 *svc_gpio_id); 341 void radeon_atom_update_memory_dll(struct radeon_device *rdev, 342 u32 mem_clock); 343 void radeon_atom_set_ac_timing(struct radeon_device *rdev, 344 u32 mem_clock); 345 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev, 346 u8 module_index, 347 struct atom_mc_reg_table *reg_table); 348 int radeon_atom_get_memory_info(struct radeon_device *rdev, 349 u8 module_index, struct atom_memory_info *mem_info); 350 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev, 351 bool gddr5, u8 module_index, 352 struct atom_memory_clock_range_table *mclk_range_table); 353 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 354 u16 voltage_id, u16 *voltage); 355 void rs690_pm_info(struct radeon_device *rdev); 356 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, 357 unsigned *bankh, unsigned *mtaspect, 358 unsigned *tile_split); 359 360 /* 361 * Fences. 362 */ 363 struct radeon_fence_driver { 364 struct radeon_device *rdev; 365 uint32_t scratch_reg; 366 uint64_t gpu_addr; 367 volatile uint32_t *cpu_addr; 368 /* sync_seq is protected by ring emission lock */ 369 uint64_t sync_seq[RADEON_NUM_RINGS]; 370 atomic64_t last_seq; 371 bool initialized, delayed_irq; 372 struct delayed_work lockup_work; 373 }; 374 375 struct radeon_fence { 376 struct dma_fence base; 377 378 struct radeon_device *rdev; 379 uint64_t seq; 380 /* RB, DMA, etc. */ 381 unsigned ring; 382 bool is_vm_update; 383 384 wait_queue_entry_t fence_wake; 385 }; 386 387 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring); 388 void radeon_fence_driver_init(struct radeon_device *rdev); 389 void radeon_fence_driver_fini(struct radeon_device *rdev); 390 void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring); 391 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring); 392 void radeon_fence_process(struct radeon_device *rdev, int ring); 393 bool radeon_fence_signaled(struct radeon_fence *fence); 394 long radeon_fence_wait_timeout(struct radeon_fence *fence, bool interruptible, long timeout); 395 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); 396 int radeon_fence_wait_next(struct radeon_device *rdev, int ring); 397 int radeon_fence_wait_empty(struct radeon_device *rdev, int ring); 398 int radeon_fence_wait_any(struct radeon_device *rdev, 399 struct radeon_fence **fences, 400 bool intr); 401 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); 402 void radeon_fence_unref(struct radeon_fence **fence); 403 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring); 404 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring); 405 void radeon_fence_note_sync(struct radeon_fence *fence, int ring); 406 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a, 407 struct radeon_fence *b) 408 { 409 if (!a) { 410 return b; 411 } 412 413 if (!b) { 414 return a; 415 } 416 417 BUG_ON(a->ring != b->ring); 418 419 if (a->seq > b->seq) { 420 return a; 421 } else { 422 return b; 423 } 424 } 425 426 static inline bool radeon_fence_is_earlier(struct radeon_fence *a, 427 struct radeon_fence *b) 428 { 429 if (!a) { 430 return false; 431 } 432 433 if (!b) { 434 return true; 435 } 436 437 BUG_ON(a->ring != b->ring); 438 439 return a->seq < b->seq; 440 } 441 442 /* 443 * Tiling registers 444 */ 445 struct radeon_surface_reg { 446 struct radeon_bo *bo; 447 }; 448 449 #define RADEON_GEM_MAX_SURFACES 8 450 451 /* 452 * TTM. 453 */ 454 struct radeon_mman { 455 struct ttm_device bdev; 456 bool initialized; 457 }; 458 459 struct radeon_bo_list { 460 struct radeon_bo *robj; 461 struct ttm_validate_buffer tv; 462 uint64_t gpu_offset; 463 unsigned preferred_domains; 464 unsigned allowed_domains; 465 uint32_t tiling_flags; 466 }; 467 468 /* bo virtual address in a specific vm */ 469 struct radeon_bo_va { 470 /* protected by bo being reserved */ 471 struct list_head bo_list; 472 uint32_t flags; 473 struct radeon_fence *last_pt_update; 474 unsigned ref_count; 475 476 /* protected by vm mutex */ 477 struct interval_tree_node it; 478 struct list_head vm_status; 479 480 /* constant after initialization */ 481 struct radeon_vm *vm; 482 struct radeon_bo *bo; 483 }; 484 485 struct radeon_bo { 486 /* Protected by gem.mutex */ 487 struct list_head list; 488 /* Protected by tbo.reserved */ 489 u32 initial_domain; 490 struct ttm_place placements[4]; 491 struct ttm_placement placement; 492 struct ttm_buffer_object tbo; 493 struct ttm_bo_kmap_obj kmap; 494 u32 flags; 495 void *kptr; 496 u32 tiling_flags; 497 u32 pitch; 498 int surface_reg; 499 unsigned prime_shared_count; 500 /* list of all virtual address to which this bo 501 * is associated to 502 */ 503 struct list_head va; 504 /* Constant after initialization */ 505 struct radeon_device *rdev; 506 507 pid_t pid; 508 509 #ifdef CONFIG_MMU_NOTIFIER 510 struct mmu_interval_notifier notifier; 511 #endif 512 }; 513 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, tbo.base) 514 515 struct radeon_sa_manager { 516 struct drm_suballoc_manager base; 517 struct radeon_bo *bo; 518 uint64_t gpu_addr; 519 void *cpu_ptr; 520 u32 domain; 521 }; 522 523 /* 524 * GEM objects. 525 */ 526 struct radeon_gem { 527 struct mutex mutex; 528 struct list_head objects; 529 }; 530 531 extern const struct drm_gem_object_funcs radeon_gem_object_funcs; 532 533 int radeon_align_pitch(struct radeon_device *rdev, int width, int cpp, bool tiled); 534 535 int radeon_gem_init(struct radeon_device *rdev); 536 void radeon_gem_fini(struct radeon_device *rdev); 537 int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size, 538 int alignment, int initial_domain, 539 u32 flags, bool kernel, 540 struct drm_gem_object **obj); 541 542 int radeon_mode_dumb_create(struct drm_file *file_priv, 543 struct drm_device *dev, 544 struct drm_mode_create_dumb *args); 545 int radeon_mode_dumb_mmap(struct drm_file *filp, 546 struct drm_device *dev, 547 uint32_t handle, uint64_t *offset_p); 548 549 /* 550 * Semaphores. 551 */ 552 struct radeon_semaphore { 553 struct drm_suballoc *sa_bo; 554 signed waiters; 555 uint64_t gpu_addr; 556 }; 557 558 int radeon_semaphore_create(struct radeon_device *rdev, 559 struct radeon_semaphore **semaphore); 560 bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, 561 struct radeon_semaphore *semaphore); 562 bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, 563 struct radeon_semaphore *semaphore); 564 void radeon_semaphore_free(struct radeon_device *rdev, 565 struct radeon_semaphore **semaphore, 566 struct radeon_fence *fence); 567 568 /* 569 * Synchronization 570 */ 571 struct radeon_sync { 572 struct radeon_semaphore *semaphores[RADEON_NUM_SYNCS]; 573 struct radeon_fence *sync_to[RADEON_NUM_RINGS]; 574 struct radeon_fence *last_vm_update; 575 }; 576 577 void radeon_sync_create(struct radeon_sync *sync); 578 void radeon_sync_fence(struct radeon_sync *sync, 579 struct radeon_fence *fence); 580 int radeon_sync_resv(struct radeon_device *rdev, 581 struct radeon_sync *sync, 582 struct dma_resv *resv, 583 bool shared); 584 int radeon_sync_rings(struct radeon_device *rdev, 585 struct radeon_sync *sync, 586 int waiting_ring); 587 void radeon_sync_free(struct radeon_device *rdev, struct radeon_sync *sync, 588 struct radeon_fence *fence); 589 590 /* 591 * GART structures, functions & helpers 592 */ 593 struct radeon_mc; 594 595 #define RADEON_GPU_PAGE_SIZE 4096 596 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) 597 #define RADEON_GPU_PAGE_SHIFT 12 598 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK) 599 600 #define RADEON_GART_PAGE_DUMMY 0 601 #define RADEON_GART_PAGE_VALID (1 << 0) 602 #define RADEON_GART_PAGE_READ (1 << 1) 603 #define RADEON_GART_PAGE_WRITE (1 << 2) 604 #define RADEON_GART_PAGE_SNOOP (1 << 3) 605 606 struct radeon_gart { 607 dma_addr_t table_addr; 608 struct radeon_bo *robj; 609 void *ptr; 610 unsigned num_gpu_pages; 611 unsigned num_cpu_pages; 612 unsigned table_size; 613 struct page **pages; 614 uint64_t *pages_entry; 615 bool ready; 616 }; 617 618 int radeon_gart_table_ram_alloc(struct radeon_device *rdev); 619 void radeon_gart_table_ram_free(struct radeon_device *rdev); 620 int radeon_gart_table_vram_alloc(struct radeon_device *rdev); 621 void radeon_gart_table_vram_free(struct radeon_device *rdev); 622 int radeon_gart_table_vram_pin(struct radeon_device *rdev); 623 void radeon_gart_table_vram_unpin(struct radeon_device *rdev); 624 int radeon_gart_init(struct radeon_device *rdev); 625 void radeon_gart_fini(struct radeon_device *rdev); 626 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, 627 int pages); 628 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, 629 int pages, struct page **pagelist, 630 dma_addr_t *dma_addr, uint32_t flags); 631 632 633 /* 634 * GPU MC structures, functions & helpers 635 */ 636 struct radeon_mc { 637 resource_size_t aper_size; 638 resource_size_t aper_base; 639 resource_size_t agp_base; 640 /* for some chips with <= 32MB we need to lie 641 * about vram size near mc fb location */ 642 u64 mc_vram_size; 643 u64 visible_vram_size; 644 u64 gtt_size; 645 u64 gtt_start; 646 u64 gtt_end; 647 u64 vram_start; 648 u64 vram_end; 649 unsigned vram_width; 650 u64 real_vram_size; 651 int vram_mtrr; 652 bool vram_is_ddr; 653 bool igp_sideport_enabled; 654 u64 gtt_base_align; 655 u64 mc_mask; 656 }; 657 658 bool radeon_combios_sideport_present(struct radeon_device *rdev); 659 bool radeon_atombios_sideport_present(struct radeon_device *rdev); 660 661 /* 662 * GPU scratch registers structures, functions & helpers 663 */ 664 struct radeon_scratch { 665 unsigned num_reg; 666 uint32_t reg_base; 667 bool free[32]; 668 uint32_t reg[32]; 669 }; 670 671 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); 672 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); 673 674 /* 675 * GPU doorbell structures, functions & helpers 676 */ 677 #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */ 678 679 struct radeon_doorbell { 680 /* doorbell mmio */ 681 resource_size_t base; 682 resource_size_t size; 683 u32 __iomem *ptr; 684 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */ 685 DECLARE_BITMAP(used, RADEON_MAX_DOORBELLS); 686 }; 687 688 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page); 689 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell); 690 691 /* 692 * IRQS. 693 */ 694 695 struct radeon_flip_work { 696 struct work_struct flip_work; 697 struct work_struct unpin_work; 698 struct radeon_device *rdev; 699 int crtc_id; 700 u32 target_vblank; 701 uint64_t base; 702 struct drm_pending_vblank_event *event; 703 struct radeon_bo *old_rbo; 704 struct dma_fence *fence; 705 bool async; 706 }; 707 708 struct r500_irq_stat_regs { 709 u32 disp_int; 710 u32 hdmi0_status; 711 }; 712 713 struct r600_irq_stat_regs { 714 u32 disp_int; 715 u32 disp_int_cont; 716 u32 disp_int_cont2; 717 u32 d1grph_int; 718 u32 d2grph_int; 719 u32 hdmi0_status; 720 u32 hdmi1_status; 721 }; 722 723 struct evergreen_irq_stat_regs { 724 u32 disp_int[6]; 725 u32 grph_int[6]; 726 u32 afmt_status[6]; 727 }; 728 729 struct cik_irq_stat_regs { 730 u32 disp_int; 731 u32 disp_int_cont; 732 u32 disp_int_cont2; 733 u32 disp_int_cont3; 734 u32 disp_int_cont4; 735 u32 disp_int_cont5; 736 u32 disp_int_cont6; 737 u32 d1grph_int; 738 u32 d2grph_int; 739 u32 d3grph_int; 740 u32 d4grph_int; 741 u32 d5grph_int; 742 u32 d6grph_int; 743 }; 744 745 union radeon_irq_stat_regs { 746 struct r500_irq_stat_regs r500; 747 struct r600_irq_stat_regs r600; 748 struct evergreen_irq_stat_regs evergreen; 749 struct cik_irq_stat_regs cik; 750 }; 751 752 struct radeon_irq { 753 bool installed; 754 spinlock_t lock; 755 atomic_t ring_int[RADEON_NUM_RINGS]; 756 bool crtc_vblank_int[RADEON_MAX_CRTCS]; 757 atomic_t pflip[RADEON_MAX_CRTCS]; 758 wait_queue_head_t vblank_queue; 759 bool hpd[RADEON_MAX_HPD_PINS]; 760 bool afmt[RADEON_MAX_AFMT_BLOCKS]; 761 union radeon_irq_stat_regs stat_regs; 762 bool dpm_thermal; 763 }; 764 765 int radeon_irq_kms_init(struct radeon_device *rdev); 766 void radeon_irq_kms_fini(struct radeon_device *rdev); 767 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring); 768 bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring); 769 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring); 770 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); 771 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); 772 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block); 773 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block); 774 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 775 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 776 777 /* 778 * CP & rings. 779 */ 780 781 struct radeon_ib { 782 struct drm_suballoc *sa_bo; 783 uint32_t length_dw; 784 uint64_t gpu_addr; 785 uint32_t *ptr; 786 int ring; 787 struct radeon_fence *fence; 788 struct radeon_vm *vm; 789 bool is_const_ib; 790 struct radeon_sync sync; 791 }; 792 793 struct radeon_ring { 794 struct radeon_device *rdev; 795 struct radeon_bo *ring_obj; 796 volatile uint32_t *ring; 797 unsigned rptr_offs; 798 unsigned rptr_save_reg; 799 u64 next_rptr_gpu_addr; 800 volatile u32 *next_rptr_cpu_addr; 801 unsigned wptr; 802 unsigned wptr_old; 803 unsigned ring_size; 804 unsigned ring_free_dw; 805 int count_dw; 806 atomic_t last_rptr; 807 atomic64_t last_activity; 808 uint64_t gpu_addr; 809 uint32_t align_mask; 810 uint32_t ptr_mask; 811 bool ready; 812 u32 nop; 813 u32 idx; 814 u64 last_semaphore_signal_addr; 815 u64 last_semaphore_wait_addr; 816 /* for CIK queues */ 817 u32 me; 818 u32 pipe; 819 u32 queue; 820 struct radeon_bo *mqd_obj; 821 u32 doorbell_index; 822 unsigned wptr_offs; 823 }; 824 825 struct radeon_mec { 826 struct radeon_bo *hpd_eop_obj; 827 u64 hpd_eop_gpu_addr; 828 u32 num_pipe; 829 u32 num_mec; 830 u32 num_queue; 831 }; 832 833 /* 834 * VM 835 */ 836 837 /* maximum number of VMIDs */ 838 #define RADEON_NUM_VM 16 839 840 /* number of entries in page table */ 841 #define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size) 842 843 /* PTBs (Page Table Blocks) need to be aligned to 32K */ 844 #define RADEON_VM_PTB_ALIGN_SIZE 32768 845 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1) 846 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK) 847 848 #define R600_PTE_VALID (1 << 0) 849 #define R600_PTE_SYSTEM (1 << 1) 850 #define R600_PTE_SNOOPED (1 << 2) 851 #define R600_PTE_READABLE (1 << 5) 852 #define R600_PTE_WRITEABLE (1 << 6) 853 854 /* PTE (Page Table Entry) fragment field for different page sizes */ 855 #define R600_PTE_FRAG_4KB (0 << 7) 856 #define R600_PTE_FRAG_64KB (4 << 7) 857 #define R600_PTE_FRAG_256KB (6 << 7) 858 859 /* flags needed to be set so we can copy directly from the GART table */ 860 #define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \ 861 R600_PTE_SYSTEM | R600_PTE_VALID ) 862 863 struct radeon_vm_pt { 864 struct radeon_bo *bo; 865 uint64_t addr; 866 }; 867 868 struct radeon_vm_id { 869 unsigned id; 870 uint64_t pd_gpu_addr; 871 /* last flushed PD/PT update */ 872 struct radeon_fence *flushed_updates; 873 /* last use of vmid */ 874 struct radeon_fence *last_id_use; 875 }; 876 877 struct radeon_vm { 878 struct mutex mutex; 879 880 struct rb_root_cached va; 881 882 /* protecting invalidated and freed */ 883 spinlock_t status_lock; 884 885 /* BOs moved, but not yet updated in the PT */ 886 struct list_head invalidated; 887 888 /* BOs freed, but not yet updated in the PT */ 889 struct list_head freed; 890 891 /* BOs cleared in the PT */ 892 struct list_head cleared; 893 894 /* contains the page directory */ 895 struct radeon_bo *page_directory; 896 unsigned max_pde_used; 897 898 /* array of page tables, one for each page directory entry */ 899 struct radeon_vm_pt *page_tables; 900 901 struct radeon_bo_va *ib_bo_va; 902 903 /* for id and flush management per ring */ 904 struct radeon_vm_id ids[RADEON_NUM_RINGS]; 905 }; 906 907 struct radeon_vm_manager { 908 struct radeon_fence *active[RADEON_NUM_VM]; 909 uint32_t max_pfn; 910 /* number of VMIDs */ 911 unsigned nvm; 912 /* vram base address for page table entry */ 913 u64 vram_base_offset; 914 /* is vm enabled? */ 915 bool enabled; 916 /* for hw to save the PD addr on suspend/resume */ 917 uint32_t saved_table_addr[RADEON_NUM_VM]; 918 }; 919 920 /* 921 * file private structure 922 */ 923 struct radeon_fpriv { 924 struct radeon_vm vm; 925 }; 926 927 /* 928 * R6xx+ IH ring 929 */ 930 struct r600_ih { 931 struct radeon_bo *ring_obj; 932 volatile uint32_t *ring; 933 unsigned rptr; 934 unsigned ring_size; 935 uint64_t gpu_addr; 936 uint32_t ptr_mask; 937 atomic_t lock; 938 bool enabled; 939 }; 940 941 /* 942 * RLC stuff 943 */ 944 #include "clearstate_defs.h" 945 946 struct radeon_rlc { 947 /* for power gating */ 948 struct radeon_bo *save_restore_obj; 949 uint64_t save_restore_gpu_addr; 950 volatile uint32_t *sr_ptr; 951 const u32 *reg_list; 952 u32 reg_list_size; 953 /* for clear state */ 954 struct radeon_bo *clear_state_obj; 955 uint64_t clear_state_gpu_addr; 956 volatile uint32_t *cs_ptr; 957 const struct cs_section_def *cs_data; 958 u32 clear_state_size; 959 /* for cp tables */ 960 struct radeon_bo *cp_table_obj; 961 uint64_t cp_table_gpu_addr; 962 volatile uint32_t *cp_table_ptr; 963 u32 cp_table_size; 964 }; 965 966 int radeon_ib_get(struct radeon_device *rdev, int ring, 967 struct radeon_ib *ib, struct radeon_vm *vm, 968 unsigned size); 969 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); 970 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, 971 struct radeon_ib *const_ib, bool hdp_flush); 972 int radeon_ib_pool_init(struct radeon_device *rdev); 973 void radeon_ib_pool_fini(struct radeon_device *rdev); 974 int radeon_ib_ring_tests(struct radeon_device *rdev); 975 /* Ring access between begin & end cannot sleep */ 976 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, 977 struct radeon_ring *ring); 978 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); 979 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 980 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 981 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp, 982 bool hdp_flush); 983 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp, 984 bool hdp_flush); 985 void radeon_ring_undo(struct radeon_ring *ring); 986 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); 987 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 988 void radeon_ring_lockup_update(struct radeon_device *rdev, 989 struct radeon_ring *ring); 990 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 991 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, 992 uint32_t **data); 993 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, 994 unsigned size, uint32_t *data); 995 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size, 996 unsigned rptr_offs, u32 nop); 997 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); 998 999 1000 /* r600 async dma */ 1001 void r600_dma_stop(struct radeon_device *rdev); 1002 int r600_dma_resume(struct radeon_device *rdev); 1003 void r600_dma_fini(struct radeon_device *rdev); 1004 1005 void cayman_dma_stop(struct radeon_device *rdev); 1006 int cayman_dma_resume(struct radeon_device *rdev); 1007 void cayman_dma_fini(struct radeon_device *rdev); 1008 1009 /* 1010 * CS. 1011 */ 1012 struct radeon_cs_chunk { 1013 uint32_t length_dw; 1014 uint32_t *kdata; 1015 void __user *user_ptr; 1016 }; 1017 1018 struct radeon_cs_parser { 1019 struct device *dev; 1020 struct radeon_device *rdev; 1021 struct drm_file *filp; 1022 /* chunks */ 1023 unsigned nchunks; 1024 struct radeon_cs_chunk *chunks; 1025 uint64_t *chunks_array; 1026 /* IB */ 1027 unsigned idx; 1028 /* relocations */ 1029 unsigned nrelocs; 1030 struct radeon_bo_list *relocs; 1031 struct radeon_bo_list *vm_bos; 1032 struct list_head validated; 1033 unsigned dma_reloc_idx; 1034 /* indices of various chunks */ 1035 struct radeon_cs_chunk *chunk_ib; 1036 struct radeon_cs_chunk *chunk_relocs; 1037 struct radeon_cs_chunk *chunk_flags; 1038 struct radeon_cs_chunk *chunk_const_ib; 1039 struct radeon_ib ib; 1040 struct radeon_ib const_ib; 1041 void *track; 1042 unsigned family; 1043 int parser_error; 1044 u32 cs_flags; 1045 u32 ring; 1046 s32 priority; 1047 struct ww_acquire_ctx ticket; 1048 }; 1049 1050 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) 1051 { 1052 struct radeon_cs_chunk *ibc = p->chunk_ib; 1053 1054 if (ibc->kdata) 1055 return ibc->kdata[idx]; 1056 return p->ib.ptr[idx]; 1057 } 1058 1059 1060 struct radeon_cs_packet { 1061 unsigned idx; 1062 unsigned type; 1063 unsigned reg; 1064 unsigned opcode; 1065 int count; 1066 unsigned one_reg_wr; 1067 }; 1068 1069 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, 1070 struct radeon_cs_packet *pkt, 1071 unsigned idx, unsigned reg); 1072 1073 /* 1074 * AGP 1075 */ 1076 1077 struct radeon_agp_mode { 1078 unsigned long mode; /**< AGP mode */ 1079 }; 1080 1081 struct radeon_agp_info { 1082 int agp_version_major; 1083 int agp_version_minor; 1084 unsigned long mode; 1085 unsigned long aperture_base; /* physical address */ 1086 unsigned long aperture_size; /* bytes */ 1087 unsigned long memory_allowed; /* bytes */ 1088 unsigned long memory_used; 1089 1090 /* PCI information */ 1091 unsigned short id_vendor; 1092 unsigned short id_device; 1093 }; 1094 1095 struct radeon_agp_head { 1096 struct agp_kern_info agp_info; 1097 struct list_head memory; 1098 unsigned long mode; 1099 struct agp_bridge_data *bridge; 1100 int enabled; 1101 int acquired; 1102 unsigned long base; 1103 int agp_mtrr; 1104 int cant_use_aperture; 1105 unsigned long page_mask; 1106 }; 1107 1108 #if IS_ENABLED(CONFIG_AGP) 1109 struct radeon_agp_head *radeon_agp_head_init(struct drm_device *dev); 1110 #else 1111 static inline struct radeon_agp_head *radeon_agp_head_init(struct drm_device *dev) 1112 { 1113 return NULL; 1114 } 1115 #endif 1116 int radeon_agp_init(struct radeon_device *rdev); 1117 void radeon_agp_resume(struct radeon_device *rdev); 1118 void radeon_agp_suspend(struct radeon_device *rdev); 1119 void radeon_agp_fini(struct radeon_device *rdev); 1120 1121 1122 /* 1123 * Writeback 1124 */ 1125 struct radeon_wb { 1126 struct radeon_bo *wb_obj; 1127 volatile uint32_t *wb; 1128 uint64_t gpu_addr; 1129 bool enabled; 1130 bool use_event; 1131 }; 1132 1133 #define RADEON_WB_SCRATCH_OFFSET 0 1134 #define RADEON_WB_RING0_NEXT_RPTR 256 1135 #define RADEON_WB_CP_RPTR_OFFSET 1024 1136 #define RADEON_WB_CP1_RPTR_OFFSET 1280 1137 #define RADEON_WB_CP2_RPTR_OFFSET 1536 1138 #define R600_WB_DMA_RPTR_OFFSET 1792 1139 #define R600_WB_IH_WPTR_OFFSET 2048 1140 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304 1141 #define R600_WB_EVENT_OFFSET 3072 1142 #define CIK_WB_CP1_WPTR_OFFSET 3328 1143 #define CIK_WB_CP2_WPTR_OFFSET 3584 1144 #define R600_WB_DMA_RING_TEST_OFFSET 3588 1145 #define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592 1146 1147 /** 1148 * struct radeon_pm - power management datas 1149 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) 1150 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) 1151 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) 1152 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) 1153 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) 1154 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) 1155 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) 1156 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) 1157 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) 1158 * @sclk: GPU clock Mhz (core bandwidth depends of this clock) 1159 * @needed_bandwidth: current bandwidth needs 1160 * 1161 * It keeps track of various data needed to take powermanagement decision. 1162 * Bandwidth need is used to determine minimun clock of the GPU and memory. 1163 * Equation between gpu/memory clock and available bandwidth is hw dependent 1164 * (type of memory, bus size, efficiency, ...) 1165 */ 1166 1167 enum radeon_pm_method { 1168 PM_METHOD_PROFILE, 1169 PM_METHOD_DYNPM, 1170 PM_METHOD_DPM, 1171 }; 1172 1173 enum radeon_dynpm_state { 1174 DYNPM_STATE_DISABLED, 1175 DYNPM_STATE_MINIMUM, 1176 DYNPM_STATE_PAUSED, 1177 DYNPM_STATE_ACTIVE, 1178 DYNPM_STATE_SUSPENDED, 1179 }; 1180 enum radeon_dynpm_action { 1181 DYNPM_ACTION_NONE, 1182 DYNPM_ACTION_MINIMUM, 1183 DYNPM_ACTION_DOWNCLOCK, 1184 DYNPM_ACTION_UPCLOCK, 1185 DYNPM_ACTION_DEFAULT 1186 }; 1187 1188 enum radeon_voltage_type { 1189 VOLTAGE_NONE = 0, 1190 VOLTAGE_GPIO, 1191 VOLTAGE_VDDC, 1192 VOLTAGE_SW 1193 }; 1194 1195 enum radeon_pm_state_type { 1196 /* not used for dpm */ 1197 POWER_STATE_TYPE_DEFAULT, 1198 POWER_STATE_TYPE_POWERSAVE, 1199 /* user selectable states */ 1200 POWER_STATE_TYPE_BATTERY, 1201 POWER_STATE_TYPE_BALANCED, 1202 POWER_STATE_TYPE_PERFORMANCE, 1203 /* internal states */ 1204 POWER_STATE_TYPE_INTERNAL_UVD, 1205 POWER_STATE_TYPE_INTERNAL_UVD_SD, 1206 POWER_STATE_TYPE_INTERNAL_UVD_HD, 1207 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 1208 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 1209 POWER_STATE_TYPE_INTERNAL_BOOT, 1210 POWER_STATE_TYPE_INTERNAL_THERMAL, 1211 POWER_STATE_TYPE_INTERNAL_ACPI, 1212 POWER_STATE_TYPE_INTERNAL_ULV, 1213 POWER_STATE_TYPE_INTERNAL_3DPERF, 1214 }; 1215 1216 enum radeon_pm_profile_type { 1217 PM_PROFILE_DEFAULT, 1218 PM_PROFILE_AUTO, 1219 PM_PROFILE_LOW, 1220 PM_PROFILE_MID, 1221 PM_PROFILE_HIGH, 1222 }; 1223 1224 #define PM_PROFILE_DEFAULT_IDX 0 1225 #define PM_PROFILE_LOW_SH_IDX 1 1226 #define PM_PROFILE_MID_SH_IDX 2 1227 #define PM_PROFILE_HIGH_SH_IDX 3 1228 #define PM_PROFILE_LOW_MH_IDX 4 1229 #define PM_PROFILE_MID_MH_IDX 5 1230 #define PM_PROFILE_HIGH_MH_IDX 6 1231 #define PM_PROFILE_MAX 7 1232 1233 struct radeon_pm_profile { 1234 int dpms_off_ps_idx; 1235 int dpms_on_ps_idx; 1236 int dpms_off_cm_idx; 1237 int dpms_on_cm_idx; 1238 }; 1239 1240 enum radeon_int_thermal_type { 1241 THERMAL_TYPE_NONE, 1242 THERMAL_TYPE_EXTERNAL, 1243 THERMAL_TYPE_EXTERNAL_GPIO, 1244 THERMAL_TYPE_RV6XX, 1245 THERMAL_TYPE_RV770, 1246 THERMAL_TYPE_ADT7473_WITH_INTERNAL, 1247 THERMAL_TYPE_EVERGREEN, 1248 THERMAL_TYPE_SUMO, 1249 THERMAL_TYPE_NI, 1250 THERMAL_TYPE_SI, 1251 THERMAL_TYPE_EMC2103_WITH_INTERNAL, 1252 THERMAL_TYPE_CI, 1253 THERMAL_TYPE_KV, 1254 }; 1255 1256 struct radeon_voltage { 1257 enum radeon_voltage_type type; 1258 /* gpio voltage */ 1259 struct radeon_gpio_rec gpio; 1260 u32 delay; /* delay in usec from voltage drop to sclk change */ 1261 bool active_high; /* voltage drop is active when bit is high */ 1262 /* VDDC voltage */ 1263 u8 vddc_id; /* index into vddc voltage table */ 1264 u8 vddci_id; /* index into vddci voltage table */ 1265 bool vddci_enabled; 1266 /* r6xx+ sw */ 1267 u16 voltage; 1268 /* evergreen+ vddci */ 1269 u16 vddci; 1270 }; 1271 1272 /* clock mode flags */ 1273 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) 1274 1275 struct radeon_pm_clock_info { 1276 /* memory clock */ 1277 u32 mclk; 1278 /* engine clock */ 1279 u32 sclk; 1280 /* voltage info */ 1281 struct radeon_voltage voltage; 1282 /* standardized clock flags */ 1283 u32 flags; 1284 }; 1285 1286 /* state flags */ 1287 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) 1288 1289 struct radeon_power_state { 1290 enum radeon_pm_state_type type; 1291 struct radeon_pm_clock_info *clock_info; 1292 /* number of valid clock modes in this power state */ 1293 int num_clock_modes; 1294 struct radeon_pm_clock_info *default_clock_mode; 1295 /* standardized state flags */ 1296 u32 flags; 1297 u32 misc; /* vbios specific flags */ 1298 u32 misc2; /* vbios specific flags */ 1299 int pcie_lanes; /* pcie lanes */ 1300 }; 1301 1302 /* 1303 * Some modes are overclocked by very low value, accept them 1304 */ 1305 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ 1306 1307 enum radeon_dpm_auto_throttle_src { 1308 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, 1309 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL 1310 }; 1311 1312 enum radeon_dpm_event_src { 1313 RADEON_DPM_EVENT_SRC_ANALOG = 0, 1314 RADEON_DPM_EVENT_SRC_EXTERNAL = 1, 1315 RADEON_DPM_EVENT_SRC_DIGITAL = 2, 1316 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, 1317 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 1318 }; 1319 1320 #define RADEON_MAX_VCE_LEVELS 6 1321 1322 enum radeon_vce_level { 1323 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 1324 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 1325 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 1326 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 1327 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 1328 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 1329 }; 1330 1331 struct radeon_ps { 1332 u32 caps; /* vbios flags */ 1333 u32 class; /* vbios flags */ 1334 u32 class2; /* vbios flags */ 1335 /* UVD clocks */ 1336 u32 vclk; 1337 u32 dclk; 1338 /* VCE clocks */ 1339 u32 evclk; 1340 u32 ecclk; 1341 bool vce_active; 1342 enum radeon_vce_level vce_level; 1343 /* asic priv */ 1344 void *ps_priv; 1345 }; 1346 1347 struct radeon_dpm_thermal { 1348 /* thermal interrupt work */ 1349 struct work_struct work; 1350 /* low temperature threshold */ 1351 int min_temp; 1352 /* high temperature threshold */ 1353 int max_temp; 1354 /* was interrupt low to high or high to low */ 1355 bool high_to_low; 1356 }; 1357 1358 enum radeon_clk_action { 1359 RADEON_SCLK_UP = 1, 1360 RADEON_SCLK_DOWN 1361 }; 1362 1363 struct radeon_blacklist_clocks { 1364 u32 sclk; 1365 u32 mclk; 1366 enum radeon_clk_action action; 1367 }; 1368 1369 struct radeon_clock_and_voltage_limits { 1370 u32 sclk; 1371 u32 mclk; 1372 u16 vddc; 1373 u16 vddci; 1374 }; 1375 1376 struct radeon_clock_array { 1377 u32 count; 1378 u32 *values; 1379 }; 1380 1381 struct radeon_clock_voltage_dependency_entry { 1382 u32 clk; 1383 u16 v; 1384 }; 1385 1386 struct radeon_clock_voltage_dependency_table { 1387 u32 count; 1388 struct radeon_clock_voltage_dependency_entry *entries; 1389 }; 1390 1391 union radeon_cac_leakage_entry { 1392 struct { 1393 u16 vddc; 1394 u32 leakage; 1395 }; 1396 struct { 1397 u16 vddc1; 1398 u16 vddc2; 1399 u16 vddc3; 1400 }; 1401 }; 1402 1403 struct radeon_cac_leakage_table { 1404 u32 count; 1405 union radeon_cac_leakage_entry *entries; 1406 }; 1407 1408 struct radeon_phase_shedding_limits_entry { 1409 u16 voltage; 1410 u32 sclk; 1411 u32 mclk; 1412 }; 1413 1414 struct radeon_phase_shedding_limits_table { 1415 u32 count; 1416 struct radeon_phase_shedding_limits_entry *entries; 1417 }; 1418 1419 struct radeon_uvd_clock_voltage_dependency_entry { 1420 u32 vclk; 1421 u32 dclk; 1422 u16 v; 1423 }; 1424 1425 struct radeon_uvd_clock_voltage_dependency_table { 1426 u8 count; 1427 struct radeon_uvd_clock_voltage_dependency_entry *entries; 1428 }; 1429 1430 struct radeon_vce_clock_voltage_dependency_entry { 1431 u32 ecclk; 1432 u32 evclk; 1433 u16 v; 1434 }; 1435 1436 struct radeon_vce_clock_voltage_dependency_table { 1437 u8 count; 1438 struct radeon_vce_clock_voltage_dependency_entry *entries; 1439 }; 1440 1441 struct radeon_ppm_table { 1442 u8 ppm_design; 1443 u16 cpu_core_number; 1444 u32 platform_tdp; 1445 u32 small_ac_platform_tdp; 1446 u32 platform_tdc; 1447 u32 small_ac_platform_tdc; 1448 u32 apu_tdp; 1449 u32 dgpu_tdp; 1450 u32 dgpu_ulv_power; 1451 u32 tj_max; 1452 }; 1453 1454 struct radeon_cac_tdp_table { 1455 u16 tdp; 1456 u16 configurable_tdp; 1457 u16 tdc; 1458 u16 battery_power_limit; 1459 u16 small_power_limit; 1460 u16 low_cac_leakage; 1461 u16 high_cac_leakage; 1462 u16 maximum_power_delivery_limit; 1463 }; 1464 1465 struct radeon_dpm_dynamic_state { 1466 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk; 1467 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk; 1468 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk; 1469 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk; 1470 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk; 1471 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; 1472 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; 1473 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table; 1474 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table; 1475 struct radeon_clock_array valid_sclk_values; 1476 struct radeon_clock_array valid_mclk_values; 1477 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc; 1478 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac; 1479 u32 mclk_sclk_ratio; 1480 u32 sclk_mclk_delta; 1481 u16 vddc_vddci_delta; 1482 u16 min_vddc_for_pcie_gen2; 1483 struct radeon_cac_leakage_table cac_leakage_table; 1484 struct radeon_phase_shedding_limits_table phase_shedding_limits_table; 1485 struct radeon_ppm_table *ppm_table; 1486 struct radeon_cac_tdp_table *cac_tdp_table; 1487 }; 1488 1489 struct radeon_dpm_fan { 1490 u16 t_min; 1491 u16 t_med; 1492 u16 t_high; 1493 u16 pwm_min; 1494 u16 pwm_med; 1495 u16 pwm_high; 1496 u8 t_hyst; 1497 u32 cycle_delay; 1498 u16 t_max; 1499 u8 control_mode; 1500 u16 default_max_fan_pwm; 1501 u16 default_fan_output_sensitivity; 1502 u16 fan_output_sensitivity; 1503 bool ucode_fan_control; 1504 }; 1505 1506 enum radeon_pcie_gen { 1507 RADEON_PCIE_GEN1 = 0, 1508 RADEON_PCIE_GEN2 = 1, 1509 RADEON_PCIE_GEN3 = 2, 1510 RADEON_PCIE_GEN_INVALID = 0xffff 1511 }; 1512 1513 enum radeon_dpm_forced_level { 1514 RADEON_DPM_FORCED_LEVEL_AUTO = 0, 1515 RADEON_DPM_FORCED_LEVEL_LOW = 1, 1516 RADEON_DPM_FORCED_LEVEL_HIGH = 2, 1517 }; 1518 1519 struct radeon_vce_state { 1520 /* vce clocks */ 1521 u32 evclk; 1522 u32 ecclk; 1523 /* gpu clocks */ 1524 u32 sclk; 1525 u32 mclk; 1526 u8 clk_idx; 1527 u8 pstate; 1528 }; 1529 1530 struct radeon_dpm { 1531 struct radeon_ps *ps; 1532 /* number of valid power states */ 1533 int num_ps; 1534 /* current power state that is active */ 1535 struct radeon_ps *current_ps; 1536 /* requested power state */ 1537 struct radeon_ps *requested_ps; 1538 /* boot up power state */ 1539 struct radeon_ps *boot_ps; 1540 /* default uvd power state */ 1541 struct radeon_ps *uvd_ps; 1542 /* vce requirements */ 1543 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS]; 1544 enum radeon_vce_level vce_level; 1545 enum radeon_pm_state_type state; 1546 enum radeon_pm_state_type user_state; 1547 u32 platform_caps; 1548 u32 voltage_response_time; 1549 u32 backbias_response_time; 1550 void *priv; 1551 u32 new_active_crtcs; 1552 int new_active_crtc_count; 1553 int high_pixelclock_count; 1554 u32 current_active_crtcs; 1555 int current_active_crtc_count; 1556 bool single_display; 1557 struct radeon_dpm_dynamic_state dyn_state; 1558 struct radeon_dpm_fan fan; 1559 u32 tdp_limit; 1560 u32 near_tdp_limit; 1561 u32 near_tdp_limit_adjusted; 1562 u32 sq_ramping_threshold; 1563 u32 cac_leakage; 1564 u16 tdp_od_limit; 1565 u32 tdp_adjustment; 1566 u16 load_line_slope; 1567 bool power_control; 1568 bool ac_power; 1569 /* special states active */ 1570 bool thermal_active; 1571 bool uvd_active; 1572 bool vce_active; 1573 /* thermal handling */ 1574 struct radeon_dpm_thermal thermal; 1575 /* forced levels */ 1576 enum radeon_dpm_forced_level forced_level; 1577 /* track UVD streams */ 1578 unsigned sd; 1579 unsigned hd; 1580 }; 1581 1582 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable); 1583 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable); 1584 1585 struct radeon_pm { 1586 struct mutex mutex; 1587 /* write locked while reprogramming mclk */ 1588 struct rw_semaphore mclk_lock; 1589 u32 active_crtcs; 1590 int active_crtc_count; 1591 int req_vblank; 1592 bool vblank_sync; 1593 fixed20_12 max_bandwidth; 1594 fixed20_12 igp_sideport_mclk; 1595 fixed20_12 igp_system_mclk; 1596 fixed20_12 igp_ht_link_clk; 1597 fixed20_12 igp_ht_link_width; 1598 fixed20_12 k8_bandwidth; 1599 fixed20_12 sideport_bandwidth; 1600 fixed20_12 ht_bandwidth; 1601 fixed20_12 core_bandwidth; 1602 fixed20_12 sclk; 1603 fixed20_12 mclk; 1604 fixed20_12 needed_bandwidth; 1605 struct radeon_power_state *power_state; 1606 /* number of valid power states */ 1607 int num_power_states; 1608 int current_power_state_index; 1609 int current_clock_mode_index; 1610 int requested_power_state_index; 1611 int requested_clock_mode_index; 1612 int default_power_state_index; 1613 u32 current_sclk; 1614 u32 current_mclk; 1615 u16 current_vddc; 1616 u16 current_vddci; 1617 u32 default_sclk; 1618 u32 default_mclk; 1619 u16 default_vddc; 1620 u16 default_vddci; 1621 struct radeon_i2c_chan *i2c_bus; 1622 /* selected pm method */ 1623 enum radeon_pm_method pm_method; 1624 /* dynpm power management */ 1625 struct delayed_work dynpm_idle_work; 1626 enum radeon_dynpm_state dynpm_state; 1627 enum radeon_dynpm_action dynpm_planned_action; 1628 unsigned long dynpm_action_timeout; 1629 bool dynpm_can_upclock; 1630 bool dynpm_can_downclock; 1631 /* profile-based power management */ 1632 enum radeon_pm_profile_type profile; 1633 int profile_index; 1634 struct radeon_pm_profile profiles[PM_PROFILE_MAX]; 1635 /* internal thermal controller on rv6xx+ */ 1636 enum radeon_int_thermal_type int_thermal_type; 1637 struct device *int_hwmon_dev; 1638 /* fan control parameters */ 1639 bool no_fan; 1640 u8 fan_pulses_per_revolution; 1641 u8 fan_min_rpm; 1642 u8 fan_max_rpm; 1643 /* dpm */ 1644 bool dpm_enabled; 1645 bool sysfs_initialized; 1646 struct radeon_dpm dpm; 1647 }; 1648 1649 #define RADEON_PCIE_SPEED_25 1 1650 #define RADEON_PCIE_SPEED_50 2 1651 #define RADEON_PCIE_SPEED_80 4 1652 1653 int radeon_pm_get_type_index(struct radeon_device *rdev, 1654 enum radeon_pm_state_type ps_type, 1655 int instance); 1656 /* 1657 * UVD 1658 */ 1659 #define RADEON_DEFAULT_UVD_HANDLES 10 1660 #define RADEON_MAX_UVD_HANDLES 30 1661 #define RADEON_UVD_STACK_SIZE (200*1024) 1662 #define RADEON_UVD_HEAP_SIZE (256*1024) 1663 #define RADEON_UVD_SESSION_SIZE (50*1024) 1664 1665 struct radeon_uvd { 1666 bool fw_header_present; 1667 struct radeon_bo *vcpu_bo; 1668 void *cpu_addr; 1669 uint64_t gpu_addr; 1670 unsigned max_handles; 1671 atomic_t handles[RADEON_MAX_UVD_HANDLES]; 1672 struct drm_file *filp[RADEON_MAX_UVD_HANDLES]; 1673 unsigned img_size[RADEON_MAX_UVD_HANDLES]; 1674 struct delayed_work idle_work; 1675 }; 1676 1677 int radeon_uvd_init(struct radeon_device *rdev); 1678 void radeon_uvd_fini(struct radeon_device *rdev); 1679 int radeon_uvd_suspend(struct radeon_device *rdev); 1680 int radeon_uvd_resume(struct radeon_device *rdev); 1681 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring, 1682 uint32_t handle, struct radeon_fence **fence); 1683 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring, 1684 uint32_t handle, struct radeon_fence **fence); 1685 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo, 1686 uint32_t allowed_domains); 1687 void radeon_uvd_free_handles(struct radeon_device *rdev, 1688 struct drm_file *filp); 1689 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser); 1690 void radeon_uvd_note_usage(struct radeon_device *rdev); 1691 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev, 1692 unsigned vclk, unsigned dclk, 1693 unsigned vco_min, unsigned vco_max, 1694 unsigned fb_factor, unsigned fb_mask, 1695 unsigned pd_min, unsigned pd_max, 1696 unsigned pd_even, 1697 unsigned *optimal_fb_div, 1698 unsigned *optimal_vclk_div, 1699 unsigned *optimal_dclk_div); 1700 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev, 1701 unsigned cg_upll_func_cntl); 1702 1703 /* 1704 * VCE 1705 */ 1706 #define RADEON_MAX_VCE_HANDLES 16 1707 1708 struct radeon_vce { 1709 struct radeon_bo *vcpu_bo; 1710 uint64_t gpu_addr; 1711 unsigned fw_version; 1712 unsigned fb_version; 1713 atomic_t handles[RADEON_MAX_VCE_HANDLES]; 1714 struct drm_file *filp[RADEON_MAX_VCE_HANDLES]; 1715 unsigned img_size[RADEON_MAX_VCE_HANDLES]; 1716 struct delayed_work idle_work; 1717 uint32_t keyselect; 1718 }; 1719 1720 int radeon_vce_init(struct radeon_device *rdev); 1721 void radeon_vce_fini(struct radeon_device *rdev); 1722 int radeon_vce_suspend(struct radeon_device *rdev); 1723 int radeon_vce_resume(struct radeon_device *rdev); 1724 int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring, 1725 uint32_t handle, struct radeon_fence **fence); 1726 int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring, 1727 uint32_t handle, struct radeon_fence **fence); 1728 void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp); 1729 void radeon_vce_note_usage(struct radeon_device *rdev); 1730 int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size); 1731 int radeon_vce_cs_parse(struct radeon_cs_parser *p); 1732 bool radeon_vce_semaphore_emit(struct radeon_device *rdev, 1733 struct radeon_ring *ring, 1734 struct radeon_semaphore *semaphore, 1735 bool emit_wait); 1736 void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 1737 void radeon_vce_fence_emit(struct radeon_device *rdev, 1738 struct radeon_fence *fence); 1739 int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); 1740 int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 1741 1742 struct r600_audio_pin { 1743 int channels; 1744 int rate; 1745 int bits_per_sample; 1746 u8 status_bits; 1747 u8 category_code; 1748 u32 offset; 1749 bool connected; 1750 u32 id; 1751 }; 1752 1753 struct r600_audio { 1754 bool enabled; 1755 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS]; 1756 int num_pins; 1757 struct radeon_audio_funcs *hdmi_funcs; 1758 struct radeon_audio_funcs *dp_funcs; 1759 struct radeon_audio_basic_funcs *funcs; 1760 struct drm_audio_component *component; 1761 bool component_registered; 1762 struct mutex component_mutex; 1763 }; 1764 1765 /* 1766 * Benchmarking 1767 */ 1768 void radeon_benchmark(struct radeon_device *rdev, int test_number); 1769 1770 1771 /* 1772 * Testing 1773 */ 1774 void radeon_test_moves(struct radeon_device *rdev); 1775 void radeon_test_ring_sync(struct radeon_device *rdev, 1776 struct radeon_ring *cpA, 1777 struct radeon_ring *cpB); 1778 void radeon_test_syncing(struct radeon_device *rdev); 1779 1780 /* 1781 * MMU Notifier 1782 */ 1783 #if defined(CONFIG_MMU_NOTIFIER) 1784 int radeon_mn_register(struct radeon_bo *bo, unsigned long addr); 1785 void radeon_mn_unregister(struct radeon_bo *bo); 1786 #else 1787 static inline int radeon_mn_register(struct radeon_bo *bo, unsigned long addr) 1788 { 1789 return -ENODEV; 1790 } 1791 static inline void radeon_mn_unregister(struct radeon_bo *bo) {} 1792 #endif 1793 1794 /* 1795 * Debugfs 1796 */ 1797 void radeon_debugfs_fence_init(struct radeon_device *rdev); 1798 void radeon_gem_debugfs_init(struct radeon_device *rdev); 1799 1800 /* 1801 * ASIC ring specific functions. 1802 */ 1803 struct radeon_asic_ring { 1804 /* ring read/write ptr handling */ 1805 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1806 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1807 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1808 1809 /* validating and patching of IBs */ 1810 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib); 1811 int (*cs_parse)(struct radeon_cs_parser *p); 1812 1813 /* command emmit functions */ 1814 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); 1815 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence); 1816 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring); 1817 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp, 1818 struct radeon_semaphore *semaphore, bool emit_wait); 1819 void (*vm_flush)(struct radeon_device *rdev, struct radeon_ring *ring, 1820 unsigned vm_id, uint64_t pd_addr); 1821 1822 /* testing functions */ 1823 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1824 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1825 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); 1826 1827 /* deprecated */ 1828 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp); 1829 }; 1830 1831 /* 1832 * ASIC specific functions. 1833 */ 1834 struct radeon_asic { 1835 int (*init)(struct radeon_device *rdev); 1836 void (*fini)(struct radeon_device *rdev); 1837 int (*resume)(struct radeon_device *rdev); 1838 int (*suspend)(struct radeon_device *rdev); 1839 void (*vga_set_state)(struct radeon_device *rdev, bool state); 1840 int (*asic_reset)(struct radeon_device *rdev, bool hard); 1841 /* Flush the HDP cache via MMIO */ 1842 void (*mmio_hdp_flush)(struct radeon_device *rdev); 1843 /* check if 3D engine is idle */ 1844 bool (*gui_idle)(struct radeon_device *rdev); 1845 /* wait for mc_idle */ 1846 int (*mc_wait_for_idle)(struct radeon_device *rdev); 1847 /* get the reference clock */ 1848 u32 (*get_xclk)(struct radeon_device *rdev); 1849 /* get the gpu clock counter */ 1850 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev); 1851 /* get register for info ioctl */ 1852 int (*get_allowed_info_register)(struct radeon_device *rdev, u32 reg, u32 *val); 1853 /* gart */ 1854 struct { 1855 void (*tlb_flush)(struct radeon_device *rdev); 1856 uint64_t (*get_page_entry)(uint64_t addr, uint32_t flags); 1857 void (*set_page)(struct radeon_device *rdev, unsigned i, 1858 uint64_t entry); 1859 } gart; 1860 struct { 1861 int (*init)(struct radeon_device *rdev); 1862 void (*fini)(struct radeon_device *rdev); 1863 void (*copy_pages)(struct radeon_device *rdev, 1864 struct radeon_ib *ib, 1865 uint64_t pe, uint64_t src, 1866 unsigned count); 1867 void (*write_pages)(struct radeon_device *rdev, 1868 struct radeon_ib *ib, 1869 uint64_t pe, 1870 uint64_t addr, unsigned count, 1871 uint32_t incr, uint32_t flags); 1872 void (*set_pages)(struct radeon_device *rdev, 1873 struct radeon_ib *ib, 1874 uint64_t pe, 1875 uint64_t addr, unsigned count, 1876 uint32_t incr, uint32_t flags); 1877 void (*pad_ib)(struct radeon_ib *ib); 1878 } vm; 1879 /* ring specific callbacks */ 1880 const struct radeon_asic_ring *ring[RADEON_NUM_RINGS]; 1881 /* irqs */ 1882 struct { 1883 int (*set)(struct radeon_device *rdev); 1884 int (*process)(struct radeon_device *rdev); 1885 } irq; 1886 /* displays */ 1887 struct { 1888 /* display watermarks */ 1889 void (*bandwidth_update)(struct radeon_device *rdev); 1890 /* get frame count */ 1891 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); 1892 /* wait for vblank */ 1893 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc); 1894 /* set backlight level */ 1895 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level); 1896 /* get backlight level */ 1897 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder); 1898 /* audio callbacks */ 1899 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable); 1900 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode); 1901 } display; 1902 /* copy functions for bo handling */ 1903 struct { 1904 struct radeon_fence *(*blit)(struct radeon_device *rdev, 1905 uint64_t src_offset, 1906 uint64_t dst_offset, 1907 unsigned num_gpu_pages, 1908 struct dma_resv *resv); 1909 u32 blit_ring_index; 1910 struct radeon_fence *(*dma)(struct radeon_device *rdev, 1911 uint64_t src_offset, 1912 uint64_t dst_offset, 1913 unsigned num_gpu_pages, 1914 struct dma_resv *resv); 1915 u32 dma_ring_index; 1916 /* method used for bo copy */ 1917 struct radeon_fence *(*copy)(struct radeon_device *rdev, 1918 uint64_t src_offset, 1919 uint64_t dst_offset, 1920 unsigned num_gpu_pages, 1921 struct dma_resv *resv); 1922 /* ring used for bo copies */ 1923 u32 copy_ring_index; 1924 } copy; 1925 /* surfaces */ 1926 struct { 1927 int (*set_reg)(struct radeon_device *rdev, int reg, 1928 uint32_t tiling_flags, uint32_t pitch, 1929 uint32_t offset, uint32_t obj_size); 1930 void (*clear_reg)(struct radeon_device *rdev, int reg); 1931 } surface; 1932 /* hotplug detect */ 1933 struct { 1934 void (*init)(struct radeon_device *rdev); 1935 void (*fini)(struct radeon_device *rdev); 1936 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1937 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1938 } hpd; 1939 /* static power management */ 1940 struct { 1941 void (*misc)(struct radeon_device *rdev); 1942 void (*prepare)(struct radeon_device *rdev); 1943 void (*finish)(struct radeon_device *rdev); 1944 void (*init_profile)(struct radeon_device *rdev); 1945 void (*get_dynpm_state)(struct radeon_device *rdev); 1946 uint32_t (*get_engine_clock)(struct radeon_device *rdev); 1947 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); 1948 uint32_t (*get_memory_clock)(struct radeon_device *rdev); 1949 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); 1950 int (*get_pcie_lanes)(struct radeon_device *rdev); 1951 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); 1952 void (*set_clock_gating)(struct radeon_device *rdev, int enable); 1953 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk); 1954 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk); 1955 int (*get_temperature)(struct radeon_device *rdev); 1956 } pm; 1957 /* dynamic power management */ 1958 struct { 1959 int (*init)(struct radeon_device *rdev); 1960 void (*setup_asic)(struct radeon_device *rdev); 1961 int (*enable)(struct radeon_device *rdev); 1962 int (*late_enable)(struct radeon_device *rdev); 1963 void (*disable)(struct radeon_device *rdev); 1964 int (*pre_set_power_state)(struct radeon_device *rdev); 1965 int (*set_power_state)(struct radeon_device *rdev); 1966 void (*post_set_power_state)(struct radeon_device *rdev); 1967 void (*display_configuration_changed)(struct radeon_device *rdev); 1968 void (*fini)(struct radeon_device *rdev); 1969 u32 (*get_sclk)(struct radeon_device *rdev, bool low); 1970 u32 (*get_mclk)(struct radeon_device *rdev, bool low); 1971 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps); 1972 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m); 1973 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level); 1974 bool (*vblank_too_short)(struct radeon_device *rdev); 1975 void (*powergate_uvd)(struct radeon_device *rdev, bool gate); 1976 void (*enable_bapm)(struct radeon_device *rdev, bool enable); 1977 void (*fan_ctrl_set_mode)(struct radeon_device *rdev, u32 mode); 1978 u32 (*fan_ctrl_get_mode)(struct radeon_device *rdev); 1979 int (*set_fan_speed_percent)(struct radeon_device *rdev, u32 speed); 1980 int (*get_fan_speed_percent)(struct radeon_device *rdev, u32 *speed); 1981 u32 (*get_current_sclk)(struct radeon_device *rdev); 1982 u32 (*get_current_mclk)(struct radeon_device *rdev); 1983 u16 (*get_current_vddc)(struct radeon_device *rdev); 1984 } dpm; 1985 /* pageflipping */ 1986 struct { 1987 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base, bool async); 1988 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc); 1989 } pflip; 1990 }; 1991 1992 /* 1993 * Asic structures 1994 */ 1995 struct r100_asic { 1996 const unsigned *reg_safe_bm; 1997 unsigned reg_safe_bm_size; 1998 u32 hdp_cntl; 1999 }; 2000 2001 struct r300_asic { 2002 const unsigned *reg_safe_bm; 2003 unsigned reg_safe_bm_size; 2004 u32 resync_scratch; 2005 u32 hdp_cntl; 2006 }; 2007 2008 struct r600_asic { 2009 unsigned max_pipes; 2010 unsigned max_tile_pipes; 2011 unsigned max_simds; 2012 unsigned max_backends; 2013 unsigned max_gprs; 2014 unsigned max_threads; 2015 unsigned max_stack_entries; 2016 unsigned max_hw_contexts; 2017 unsigned max_gs_threads; 2018 unsigned sx_max_export_size; 2019 unsigned sx_max_export_pos_size; 2020 unsigned sx_max_export_smx_size; 2021 unsigned sq_num_cf_insts; 2022 unsigned tiling_nbanks; 2023 unsigned tiling_npipes; 2024 unsigned tiling_group_size; 2025 unsigned tile_config; 2026 unsigned backend_map; 2027 unsigned active_simds; 2028 }; 2029 2030 struct rv770_asic { 2031 unsigned max_pipes; 2032 unsigned max_tile_pipes; 2033 unsigned max_simds; 2034 unsigned max_backends; 2035 unsigned max_gprs; 2036 unsigned max_threads; 2037 unsigned max_stack_entries; 2038 unsigned max_hw_contexts; 2039 unsigned max_gs_threads; 2040 unsigned sx_max_export_size; 2041 unsigned sx_max_export_pos_size; 2042 unsigned sx_max_export_smx_size; 2043 unsigned sq_num_cf_insts; 2044 unsigned sx_num_of_sets; 2045 unsigned sc_prim_fifo_size; 2046 unsigned sc_hiz_tile_fifo_size; 2047 unsigned sc_earlyz_tile_fifo_fize; 2048 unsigned tiling_nbanks; 2049 unsigned tiling_npipes; 2050 unsigned tiling_group_size; 2051 unsigned tile_config; 2052 unsigned backend_map; 2053 unsigned active_simds; 2054 }; 2055 2056 struct evergreen_asic { 2057 unsigned num_ses; 2058 unsigned max_pipes; 2059 unsigned max_tile_pipes; 2060 unsigned max_simds; 2061 unsigned max_backends; 2062 unsigned max_gprs; 2063 unsigned max_threads; 2064 unsigned max_stack_entries; 2065 unsigned max_hw_contexts; 2066 unsigned max_gs_threads; 2067 unsigned sx_max_export_size; 2068 unsigned sx_max_export_pos_size; 2069 unsigned sx_max_export_smx_size; 2070 unsigned sq_num_cf_insts; 2071 unsigned sx_num_of_sets; 2072 unsigned sc_prim_fifo_size; 2073 unsigned sc_hiz_tile_fifo_size; 2074 unsigned sc_earlyz_tile_fifo_size; 2075 unsigned tiling_nbanks; 2076 unsigned tiling_npipes; 2077 unsigned tiling_group_size; 2078 unsigned tile_config; 2079 unsigned backend_map; 2080 unsigned active_simds; 2081 }; 2082 2083 struct cayman_asic { 2084 unsigned max_shader_engines; 2085 unsigned max_pipes_per_simd; 2086 unsigned max_tile_pipes; 2087 unsigned max_simds_per_se; 2088 unsigned max_backends_per_se; 2089 unsigned max_texture_channel_caches; 2090 unsigned max_gprs; 2091 unsigned max_threads; 2092 unsigned max_gs_threads; 2093 unsigned max_stack_entries; 2094 unsigned sx_num_of_sets; 2095 unsigned sx_max_export_size; 2096 unsigned sx_max_export_pos_size; 2097 unsigned sx_max_export_smx_size; 2098 unsigned max_hw_contexts; 2099 unsigned sq_num_cf_insts; 2100 unsigned sc_prim_fifo_size; 2101 unsigned sc_hiz_tile_fifo_size; 2102 unsigned sc_earlyz_tile_fifo_size; 2103 2104 unsigned num_shader_engines; 2105 unsigned num_shader_pipes_per_simd; 2106 unsigned num_tile_pipes; 2107 unsigned num_simds_per_se; 2108 unsigned num_backends_per_se; 2109 unsigned backend_disable_mask_per_asic; 2110 unsigned backend_map; 2111 unsigned num_texture_channel_caches; 2112 unsigned mem_max_burst_length_bytes; 2113 unsigned mem_row_size_in_kb; 2114 unsigned shader_engine_tile_size; 2115 unsigned num_gpus; 2116 unsigned multi_gpu_tile_size; 2117 2118 unsigned tile_config; 2119 unsigned active_simds; 2120 }; 2121 2122 struct si_asic { 2123 unsigned max_shader_engines; 2124 unsigned max_tile_pipes; 2125 unsigned max_cu_per_sh; 2126 unsigned max_sh_per_se; 2127 unsigned max_backends_per_se; 2128 unsigned max_texture_channel_caches; 2129 unsigned max_gprs; 2130 unsigned max_gs_threads; 2131 unsigned max_hw_contexts; 2132 unsigned sc_prim_fifo_size_frontend; 2133 unsigned sc_prim_fifo_size_backend; 2134 unsigned sc_hiz_tile_fifo_size; 2135 unsigned sc_earlyz_tile_fifo_size; 2136 2137 unsigned num_tile_pipes; 2138 unsigned backend_enable_mask; 2139 unsigned backend_disable_mask_per_asic; 2140 unsigned backend_map; 2141 unsigned num_texture_channel_caches; 2142 unsigned mem_max_burst_length_bytes; 2143 unsigned mem_row_size_in_kb; 2144 unsigned shader_engine_tile_size; 2145 unsigned num_gpus; 2146 unsigned multi_gpu_tile_size; 2147 2148 unsigned tile_config; 2149 uint32_t tile_mode_array[32]; 2150 uint32_t active_cus; 2151 }; 2152 2153 struct cik_asic { 2154 unsigned max_shader_engines; 2155 unsigned max_tile_pipes; 2156 unsigned max_cu_per_sh; 2157 unsigned max_sh_per_se; 2158 unsigned max_backends_per_se; 2159 unsigned max_texture_channel_caches; 2160 unsigned max_gprs; 2161 unsigned max_gs_threads; 2162 unsigned max_hw_contexts; 2163 unsigned sc_prim_fifo_size_frontend; 2164 unsigned sc_prim_fifo_size_backend; 2165 unsigned sc_hiz_tile_fifo_size; 2166 unsigned sc_earlyz_tile_fifo_size; 2167 2168 unsigned num_tile_pipes; 2169 unsigned backend_enable_mask; 2170 unsigned backend_disable_mask_per_asic; 2171 unsigned backend_map; 2172 unsigned num_texture_channel_caches; 2173 unsigned mem_max_burst_length_bytes; 2174 unsigned mem_row_size_in_kb; 2175 unsigned shader_engine_tile_size; 2176 unsigned num_gpus; 2177 unsigned multi_gpu_tile_size; 2178 2179 unsigned tile_config; 2180 uint32_t tile_mode_array[32]; 2181 uint32_t macrotile_mode_array[16]; 2182 uint32_t active_cus; 2183 }; 2184 2185 union radeon_asic_config { 2186 struct r300_asic r300; 2187 struct r100_asic r100; 2188 struct r600_asic r600; 2189 struct rv770_asic rv770; 2190 struct evergreen_asic evergreen; 2191 struct cayman_asic cayman; 2192 struct si_asic si; 2193 struct cik_asic cik; 2194 }; 2195 2196 /* 2197 * asic initizalization from radeon_asic.c 2198 */ 2199 void radeon_agp_disable(struct radeon_device *rdev); 2200 int radeon_asic_init(struct radeon_device *rdev); 2201 2202 2203 /* 2204 * IOCTL. 2205 */ 2206 int radeon_gem_info_ioctl(struct drm_device *dev, void *data, 2207 struct drm_file *filp); 2208 int radeon_gem_create_ioctl(struct drm_device *dev, void *data, 2209 struct drm_file *filp); 2210 int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data, 2211 struct drm_file *filp); 2212 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, 2213 struct drm_file *file_priv); 2214 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, 2215 struct drm_file *file_priv); 2216 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, 2217 struct drm_file *filp); 2218 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, 2219 struct drm_file *filp); 2220 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, 2221 struct drm_file *filp); 2222 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 2223 struct drm_file *filp); 2224 int radeon_gem_va_ioctl(struct drm_device *dev, void *data, 2225 struct drm_file *filp); 2226 int radeon_gem_op_ioctl(struct drm_device *dev, void *data, 2227 struct drm_file *filp); 2228 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 2229 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, 2230 struct drm_file *filp); 2231 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, 2232 struct drm_file *filp); 2233 int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 2234 2235 /* VRAM scratch page for HDP bug, default vram page */ 2236 struct r600_vram_scratch { 2237 struct radeon_bo *robj; 2238 volatile uint32_t *ptr; 2239 u64 gpu_addr; 2240 }; 2241 2242 /* 2243 * ACPI 2244 */ 2245 struct radeon_atif_notification_cfg { 2246 bool enabled; 2247 int command_code; 2248 }; 2249 2250 struct radeon_atif_notifications { 2251 bool display_switch; 2252 bool expansion_mode_change; 2253 bool thermal_state; 2254 bool forced_power_state; 2255 bool system_power_state; 2256 bool display_conf_change; 2257 bool px_gfx_switch; 2258 bool brightness_change; 2259 bool dgpu_display_event; 2260 }; 2261 2262 struct radeon_atif_functions { 2263 bool system_params; 2264 bool sbios_requests; 2265 bool select_active_disp; 2266 bool lid_state; 2267 bool get_tv_standard; 2268 bool set_tv_standard; 2269 bool get_panel_expansion_mode; 2270 bool set_panel_expansion_mode; 2271 bool temperature_change; 2272 bool graphics_device_types; 2273 }; 2274 2275 struct radeon_atif { 2276 struct radeon_atif_notifications notifications; 2277 struct radeon_atif_functions functions; 2278 struct radeon_atif_notification_cfg notification_cfg; 2279 struct radeon_encoder *encoder_for_bl; 2280 }; 2281 2282 struct radeon_atcs_functions { 2283 bool get_ext_state; 2284 bool pcie_perf_req; 2285 bool pcie_dev_rdy; 2286 bool pcie_bus_width; 2287 }; 2288 2289 struct radeon_atcs { 2290 struct radeon_atcs_functions functions; 2291 }; 2292 2293 /* 2294 * Core structure, functions and helpers. 2295 */ 2296 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); 2297 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); 2298 2299 struct radeon_device { 2300 struct device *dev; 2301 struct drm_device *ddev; 2302 struct pci_dev *pdev; 2303 #ifdef __alpha__ 2304 struct pci_controller *hose; 2305 #endif 2306 struct radeon_agp_head *agp; 2307 struct rw_semaphore exclusive_lock; 2308 /* ASIC */ 2309 union radeon_asic_config config; 2310 enum radeon_family family; 2311 unsigned long flags; 2312 int usec_timeout; 2313 enum radeon_pll_errata pll_errata; 2314 int num_gb_pipes; 2315 int num_z_pipes; 2316 int disp_priority; 2317 /* BIOS */ 2318 uint8_t *bios; 2319 bool is_atom_bios; 2320 uint16_t bios_header_start; 2321 struct radeon_bo *stolen_vga_memory; 2322 /* Register mmio */ 2323 resource_size_t rmmio_base; 2324 resource_size_t rmmio_size; 2325 /* protects concurrent MM_INDEX/DATA based register access */ 2326 spinlock_t mmio_idx_lock; 2327 /* protects concurrent SMC based register access */ 2328 spinlock_t smc_idx_lock; 2329 /* protects concurrent PLL register access */ 2330 spinlock_t pll_idx_lock; 2331 /* protects concurrent MC register access */ 2332 spinlock_t mc_idx_lock; 2333 /* protects concurrent PCIE register access */ 2334 spinlock_t pcie_idx_lock; 2335 /* protects concurrent PCIE_PORT register access */ 2336 spinlock_t pciep_idx_lock; 2337 /* protects concurrent PIF register access */ 2338 spinlock_t pif_idx_lock; 2339 /* protects concurrent CG register access */ 2340 spinlock_t cg_idx_lock; 2341 /* protects concurrent UVD register access */ 2342 spinlock_t uvd_idx_lock; 2343 /* protects concurrent RCU register access */ 2344 spinlock_t rcu_idx_lock; 2345 /* protects concurrent DIDT register access */ 2346 spinlock_t didt_idx_lock; 2347 /* protects concurrent ENDPOINT (audio) register access */ 2348 spinlock_t end_idx_lock; 2349 void __iomem *rmmio; 2350 radeon_rreg_t mc_rreg; 2351 radeon_wreg_t mc_wreg; 2352 radeon_rreg_t pll_rreg; 2353 radeon_wreg_t pll_wreg; 2354 uint32_t pcie_reg_mask; 2355 radeon_rreg_t pciep_rreg; 2356 radeon_wreg_t pciep_wreg; 2357 /* io port */ 2358 void __iomem *rio_mem; 2359 resource_size_t rio_mem_size; 2360 struct radeon_clock clock; 2361 struct radeon_mc mc; 2362 struct radeon_gart gart; 2363 struct radeon_mode_info mode_info; 2364 struct radeon_scratch scratch; 2365 struct radeon_doorbell doorbell; 2366 struct radeon_mman mman; 2367 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS]; 2368 wait_queue_head_t fence_queue; 2369 u64 fence_context; 2370 struct mutex ring_lock; 2371 struct radeon_ring ring[RADEON_NUM_RINGS]; 2372 bool ib_pool_ready; 2373 struct radeon_sa_manager ring_tmp_bo; 2374 struct radeon_irq irq; 2375 struct radeon_asic *asic; 2376 struct radeon_gem gem; 2377 struct radeon_pm pm; 2378 struct radeon_uvd uvd; 2379 struct radeon_vce vce; 2380 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; 2381 struct radeon_wb wb; 2382 struct radeon_dummy_page dummy_page; 2383 bool shutdown; 2384 bool need_swiotlb; 2385 bool accel_working; 2386 bool fastfb_working; /* IGP feature*/ 2387 bool needs_reset, in_reset; 2388 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; 2389 const struct firmware *me_fw; /* all family ME firmware */ 2390 const struct firmware *pfp_fw; /* r6/700 PFP firmware */ 2391 const struct firmware *rlc_fw; /* r6/700 RLC firmware */ 2392 const struct firmware *mc_fw; /* NI MC firmware */ 2393 const struct firmware *ce_fw; /* SI CE firmware */ 2394 const struct firmware *mec_fw; /* CIK MEC firmware */ 2395 const struct firmware *mec2_fw; /* KV MEC2 firmware */ 2396 const struct firmware *sdma_fw; /* CIK SDMA firmware */ 2397 const struct firmware *smc_fw; /* SMC firmware */ 2398 const struct firmware *uvd_fw; /* UVD firmware */ 2399 const struct firmware *vce_fw; /* VCE firmware */ 2400 bool new_fw; 2401 struct r600_vram_scratch vram_scratch; 2402 int msi_enabled; /* msi enabled */ 2403 struct r600_ih ih; /* r6/700 interrupt ring */ 2404 struct radeon_rlc rlc; 2405 struct radeon_mec mec; 2406 struct delayed_work hotplug_work; 2407 struct work_struct dp_work; 2408 struct work_struct audio_work; 2409 int num_crtc; /* number of crtcs */ 2410 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ 2411 bool has_uvd; 2412 bool has_vce; 2413 struct r600_audio audio; /* audio stuff */ 2414 struct notifier_block acpi_nb; 2415 /* only one userspace can use Hyperz features or CMASK at a time */ 2416 struct drm_file *hyperz_filp; 2417 struct drm_file *cmask_filp; 2418 /* i2c buses */ 2419 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; 2420 /* virtual memory */ 2421 struct radeon_vm_manager vm_manager; 2422 struct mutex gpu_clock_mutex; 2423 /* memory stats */ 2424 atomic64_t num_bytes_moved; 2425 atomic_t gpu_reset_counter; 2426 /* ACPI interface */ 2427 struct radeon_atif atif; 2428 struct radeon_atcs atcs; 2429 /* srbm instance registers */ 2430 struct mutex srbm_mutex; 2431 /* clock, powergating flags */ 2432 u32 cg_flags; 2433 u32 pg_flags; 2434 2435 struct dev_pm_domain vga_pm_domain; 2436 bool have_disp_power_ref; 2437 u32 px_quirk_flags; 2438 2439 /* tracking pinned memory */ 2440 u64 vram_pin_size; 2441 u64 gart_pin_size; 2442 }; 2443 2444 bool radeon_is_px(struct drm_device *dev); 2445 int radeon_device_init(struct radeon_device *rdev, 2446 struct drm_device *ddev, 2447 struct pci_dev *pdev, 2448 uint32_t flags); 2449 void radeon_device_fini(struct radeon_device *rdev); 2450 int radeon_gpu_wait_for_idle(struct radeon_device *rdev); 2451 2452 #define RADEON_MIN_MMIO_SIZE 0x10000 2453 2454 uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg); 2455 void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v); 2456 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, 2457 bool always_indirect) 2458 { 2459 /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */ 2460 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect) 2461 return readl(((void __iomem *)rdev->rmmio) + reg); 2462 else 2463 return r100_mm_rreg_slow(rdev, reg); 2464 } 2465 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, 2466 bool always_indirect) 2467 { 2468 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect) 2469 writel(v, ((void __iomem *)rdev->rmmio) + reg); 2470 else 2471 r100_mm_wreg_slow(rdev, reg, v); 2472 } 2473 2474 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg); 2475 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2476 2477 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index); 2478 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v); 2479 2480 /* 2481 * Cast helper 2482 */ 2483 extern const struct dma_fence_ops radeon_fence_ops; 2484 2485 static inline struct radeon_fence *to_radeon_fence(struct dma_fence *f) 2486 { 2487 struct radeon_fence *__f = container_of(f, struct radeon_fence, base); 2488 2489 if (__f->base.ops == &radeon_fence_ops) 2490 return __f; 2491 2492 return NULL; 2493 } 2494 2495 /* 2496 * Registers read & write functions. 2497 */ 2498 #define RREG8(reg) readb((rdev->rmmio) + (reg)) 2499 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg)) 2500 #define RREG16(reg) readw((rdev->rmmio) + (reg)) 2501 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg)) 2502 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false) 2503 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true) 2504 #define DREG32(reg) pr_info("REGISTER: " #reg " : 0x%08X\n", \ 2505 r100_mm_rreg(rdev, (reg), false)) 2506 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false) 2507 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true) 2508 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2509 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2510 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) 2511 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) 2512 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) 2513 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) 2514 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) 2515 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) 2516 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg)) 2517 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) 2518 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg)) 2519 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v)) 2520 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg)) 2521 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v)) 2522 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg)) 2523 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v)) 2524 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg)) 2525 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v)) 2526 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg)) 2527 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v)) 2528 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg)) 2529 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v)) 2530 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg)) 2531 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v)) 2532 #define WREG32_P(reg, val, mask) \ 2533 do { \ 2534 uint32_t tmp_ = RREG32(reg); \ 2535 tmp_ &= (mask); \ 2536 tmp_ |= ((val) & ~(mask)); \ 2537 WREG32(reg, tmp_); \ 2538 } while (0) 2539 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 2540 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 2541 #define WREG32_PLL_P(reg, val, mask) \ 2542 do { \ 2543 uint32_t tmp_ = RREG32_PLL(reg); \ 2544 tmp_ &= (mask); \ 2545 tmp_ |= ((val) & ~(mask)); \ 2546 WREG32_PLL(reg, tmp_); \ 2547 } while (0) 2548 #define WREG32_SMC_P(reg, val, mask) \ 2549 do { \ 2550 uint32_t tmp_ = RREG32_SMC(reg); \ 2551 tmp_ &= (mask); \ 2552 tmp_ |= ((val) & ~(mask)); \ 2553 WREG32_SMC(reg, tmp_); \ 2554 } while (0) 2555 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false)) 2556 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) 2557 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) 2558 2559 #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index)) 2560 #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v)) 2561 2562 /* 2563 * Indirect registers accessors. 2564 * They used to be inlined, but this increases code size by ~65 kbytes. 2565 * Since each performs a pair of MMIO ops 2566 * within a spin_lock_irqsave/spin_unlock_irqrestore region, 2567 * the cost of call+ret is almost negligible. MMIO and locking 2568 * costs several dozens of cycles each at best, call+ret is ~5 cycles. 2569 */ 2570 uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg); 2571 void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 2572 u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg); 2573 void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2574 u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg); 2575 void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2576 u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg); 2577 void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2578 u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg); 2579 void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2580 u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg); 2581 void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2582 u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg); 2583 void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2584 u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg); 2585 void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2586 2587 void r100_pll_errata_after_index(struct radeon_device *rdev); 2588 2589 2590 /* 2591 * ASICs helpers. 2592 */ 2593 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ 2594 (rdev->pdev->device == 0x5969)) 2595 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ 2596 (rdev->family == CHIP_RV200) || \ 2597 (rdev->family == CHIP_RS100) || \ 2598 (rdev->family == CHIP_RS200) || \ 2599 (rdev->family == CHIP_RV250) || \ 2600 (rdev->family == CHIP_RV280) || \ 2601 (rdev->family == CHIP_RS300)) 2602 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ 2603 (rdev->family == CHIP_RV350) || \ 2604 (rdev->family == CHIP_R350) || \ 2605 (rdev->family == CHIP_RV380) || \ 2606 (rdev->family == CHIP_R420) || \ 2607 (rdev->family == CHIP_R423) || \ 2608 (rdev->family == CHIP_RV410) || \ 2609 (rdev->family == CHIP_RS400) || \ 2610 (rdev->family == CHIP_RS480)) 2611 #define ASIC_IS_X2(rdev) ((rdev->pdev->device == 0x9441) || \ 2612 (rdev->pdev->device == 0x9443) || \ 2613 (rdev->pdev->device == 0x944B) || \ 2614 (rdev->pdev->device == 0x9506) || \ 2615 (rdev->pdev->device == 0x9509) || \ 2616 (rdev->pdev->device == 0x950F) || \ 2617 (rdev->pdev->device == 0x689C) || \ 2618 (rdev->pdev->device == 0x689D)) 2619 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) 2620 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ 2621 (rdev->family == CHIP_RS690) || \ 2622 (rdev->family == CHIP_RS740) || \ 2623 (rdev->family >= CHIP_R600)) 2624 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) 2625 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) 2626 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) 2627 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ 2628 (rdev->flags & RADEON_IS_IGP)) 2629 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) 2630 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA)) 2631 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ 2632 (rdev->flags & RADEON_IS_IGP)) 2633 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND)) 2634 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN)) 2635 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE)) 2636 #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI)) 2637 #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE)) 2638 #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \ 2639 (rdev->family == CHIP_MULLINS)) 2640 2641 #define ASIC_IS_LOMBOK(rdev) ((rdev->pdev->device == 0x6849) || \ 2642 (rdev->pdev->device == 0x6850) || \ 2643 (rdev->pdev->device == 0x6858) || \ 2644 (rdev->pdev->device == 0x6859) || \ 2645 (rdev->pdev->device == 0x6840) || \ 2646 (rdev->pdev->device == 0x6841) || \ 2647 (rdev->pdev->device == 0x6842) || \ 2648 (rdev->pdev->device == 0x6843)) 2649 2650 /* 2651 * BIOS helpers. 2652 */ 2653 #define RBIOS8(i) (rdev->bios[i]) 2654 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 2655 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 2656 2657 int radeon_combios_init(struct radeon_device *rdev); 2658 void radeon_combios_fini(struct radeon_device *rdev); 2659 int radeon_atombios_init(struct radeon_device *rdev); 2660 void radeon_atombios_fini(struct radeon_device *rdev); 2661 2662 2663 /* 2664 * RING helpers. 2665 */ 2666 2667 /** 2668 * radeon_ring_write - write a value to the ring 2669 * 2670 * @ring: radeon_ring structure holding ring information 2671 * @v: dword (dw) value to write 2672 * 2673 * Write a value to the requested ring buffer (all asics). 2674 */ 2675 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) 2676 { 2677 if (ring->count_dw <= 0) 2678 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n"); 2679 2680 ring->ring[ring->wptr++] = v; 2681 ring->wptr &= ring->ptr_mask; 2682 ring->count_dw--; 2683 ring->ring_free_dw--; 2684 } 2685 2686 /* 2687 * ASICs macro. 2688 */ 2689 #define radeon_init(rdev) (rdev)->asic->init((rdev)) 2690 #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) 2691 #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) 2692 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) 2693 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p)) 2694 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) 2695 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev), false) 2696 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) 2697 #define radeon_gart_get_page_entry(a, f) (rdev)->asic->gart.get_page_entry((a), (f)) 2698 #define radeon_gart_set_page(rdev, i, e) (rdev)->asic->gart.set_page((rdev), (i), (e)) 2699 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) 2700 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) 2701 #define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count))) 2702 #define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) 2703 #define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) 2704 #define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib))) 2705 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp)) 2706 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp)) 2707 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp)) 2708 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib)) 2709 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib)) 2710 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp)) 2711 #define radeon_ring_vm_flush(rdev, r, vm_id, pd_addr) (rdev)->asic->ring[(r)->idx]->vm_flush((rdev), (r), (vm_id), (pd_addr)) 2712 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r)) 2713 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r)) 2714 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r)) 2715 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) 2716 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev)) 2717 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) 2718 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l)) 2719 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e)) 2720 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b)) 2721 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m)) 2722 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence)) 2723 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) 2724 #define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv)) 2725 #define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv)) 2726 #define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv)) 2727 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index 2728 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index 2729 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index 2730 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev)) 2731 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e)) 2732 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev)) 2733 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e)) 2734 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) 2735 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) 2736 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) 2737 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d)) 2738 #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec)) 2739 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev)) 2740 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) 2741 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) 2742 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) 2743 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev)) 2744 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev)) 2745 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h)) 2746 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h)) 2747 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) 2748 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev)) 2749 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev)) 2750 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev)) 2751 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev)) 2752 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev)) 2753 #define radeon_page_flip(rdev, crtc, base, async) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base), (async)) 2754 #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc)) 2755 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc)) 2756 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev)) 2757 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev)) 2758 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev)) 2759 #define radeon_get_allowed_info_register(rdev, r, v) (rdev)->asic->get_allowed_info_register((rdev), (r), (v)) 2760 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev)) 2761 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev)) 2762 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev)) 2763 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev)) 2764 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev)) 2765 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev)) 2766 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev)) 2767 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev)) 2768 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev)) 2769 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev)) 2770 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l)) 2771 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l)) 2772 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps)) 2773 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m)) 2774 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l)) 2775 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev)) 2776 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g)) 2777 #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e)) 2778 #define radeon_dpm_get_current_sclk(rdev) rdev->asic->dpm.get_current_sclk((rdev)) 2779 #define radeon_dpm_get_current_mclk(rdev) rdev->asic->dpm.get_current_mclk((rdev)) 2780 2781 /* Common functions */ 2782 /* AGP */ 2783 extern int radeon_gpu_reset(struct radeon_device *rdev); 2784 extern void radeon_pci_config_reset(struct radeon_device *rdev); 2785 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung); 2786 extern void radeon_agp_disable(struct radeon_device *rdev); 2787 extern int radeon_modeset_init(struct radeon_device *rdev); 2788 extern void radeon_modeset_fini(struct radeon_device *rdev); 2789 extern bool radeon_card_posted(struct radeon_device *rdev); 2790 extern void radeon_update_bandwidth_info(struct radeon_device *rdev); 2791 extern void radeon_update_display_priority(struct radeon_device *rdev); 2792 extern bool radeon_boot_test_post_card(struct radeon_device *rdev); 2793 extern void radeon_scratch_init(struct radeon_device *rdev); 2794 extern void radeon_wb_fini(struct radeon_device *rdev); 2795 extern int radeon_wb_init(struct radeon_device *rdev); 2796 extern void radeon_wb_disable(struct radeon_device *rdev); 2797 extern void radeon_surface_init(struct radeon_device *rdev); 2798 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); 2799 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); 2800 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); 2801 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); 2802 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); 2803 extern int radeon_ttm_tt_set_userptr(struct radeon_device *rdev, 2804 struct ttm_tt *ttm, uint64_t addr, 2805 uint32_t flags); 2806 extern bool radeon_ttm_tt_has_userptr(struct radeon_device *rdev, struct ttm_tt *ttm); 2807 extern bool radeon_ttm_tt_is_readonly(struct radeon_device *rdev, struct ttm_tt *ttm); 2808 bool radeon_ttm_tt_is_bound(struct ttm_device *bdev, struct ttm_tt *ttm); 2809 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); 2810 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); 2811 extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 2812 extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, 2813 bool fbcon, bool freeze); 2814 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); 2815 extern void radeon_program_register_sequence(struct radeon_device *rdev, 2816 const u32 *registers, 2817 const u32 array_size); 2818 struct radeon_device *radeon_get_rdev(struct ttm_device *bdev); 2819 2820 /* KMS */ 2821 2822 u32 radeon_get_vblank_counter_kms(struct drm_crtc *crtc); 2823 int radeon_enable_vblank_kms(struct drm_crtc *crtc); 2824 void radeon_disable_vblank_kms(struct drm_crtc *crtc); 2825 2826 /* 2827 * vm 2828 */ 2829 int radeon_vm_manager_init(struct radeon_device *rdev); 2830 void radeon_vm_manager_fini(struct radeon_device *rdev); 2831 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); 2832 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); 2833 struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev, 2834 struct radeon_vm *vm, 2835 struct list_head *head); 2836 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, 2837 struct radeon_vm *vm, int ring); 2838 void radeon_vm_flush(struct radeon_device *rdev, 2839 struct radeon_vm *vm, 2840 int ring, struct radeon_fence *fence); 2841 void radeon_vm_fence(struct radeon_device *rdev, 2842 struct radeon_vm *vm, 2843 struct radeon_fence *fence); 2844 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr); 2845 int radeon_vm_update_page_directory(struct radeon_device *rdev, 2846 struct radeon_vm *vm); 2847 int radeon_vm_clear_freed(struct radeon_device *rdev, 2848 struct radeon_vm *vm); 2849 int radeon_vm_clear_invalids(struct radeon_device *rdev, 2850 struct radeon_vm *vm); 2851 int radeon_vm_bo_update(struct radeon_device *rdev, 2852 struct radeon_bo_va *bo_va, 2853 struct ttm_resource *mem); 2854 void radeon_vm_bo_invalidate(struct radeon_device *rdev, 2855 struct radeon_bo *bo); 2856 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm, 2857 struct radeon_bo *bo); 2858 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev, 2859 struct radeon_vm *vm, 2860 struct radeon_bo *bo); 2861 int radeon_vm_bo_set_addr(struct radeon_device *rdev, 2862 struct radeon_bo_va *bo_va, 2863 uint64_t offset, 2864 uint32_t flags); 2865 void radeon_vm_bo_rmv(struct radeon_device *rdev, 2866 struct radeon_bo_va *bo_va); 2867 2868 /* audio */ 2869 void r600_audio_update_hdmi(struct work_struct *work); 2870 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev); 2871 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev); 2872 void r600_audio_enable(struct radeon_device *rdev, 2873 struct r600_audio_pin *pin, 2874 u8 enable_mask); 2875 void dce6_audio_enable(struct radeon_device *rdev, 2876 struct r600_audio_pin *pin, 2877 u8 enable_mask); 2878 2879 /* 2880 * R600 vram scratch functions 2881 */ 2882 int r600_vram_scratch_init(struct radeon_device *rdev); 2883 void r600_vram_scratch_fini(struct radeon_device *rdev); 2884 2885 /* 2886 * r600 cs checking helper 2887 */ 2888 unsigned r600_mip_minify(unsigned size, unsigned level); 2889 bool r600_fmt_is_valid_color(u32 format); 2890 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family); 2891 int r600_fmt_get_blocksize(u32 format); 2892 int r600_fmt_get_nblocksx(u32 format, u32 w); 2893 int r600_fmt_get_nblocksy(u32 format, u32 h); 2894 2895 /* 2896 * r600 functions used by radeon_encoder.c 2897 */ 2898 struct radeon_hdmi_acr { 2899 u32 clock; 2900 2901 int n_32khz; 2902 int cts_32khz; 2903 2904 int n_44_1khz; 2905 int cts_44_1khz; 2906 2907 int n_48khz; 2908 int cts_48khz; 2909 2910 }; 2911 2912 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev, 2913 u32 tiling_pipe_num, 2914 u32 max_rb_num, 2915 u32 total_max_rb_num, 2916 u32 enabled_rb_mask); 2917 2918 /* 2919 * evergreen functions used by radeon_encoder.c 2920 */ 2921 2922 extern int ni_init_microcode(struct radeon_device *rdev); 2923 extern int ni_mc_load_microcode(struct radeon_device *rdev); 2924 2925 /* radeon_acpi.c */ 2926 #if defined(CONFIG_ACPI) 2927 extern int radeon_acpi_init(struct radeon_device *rdev); 2928 extern void radeon_acpi_fini(struct radeon_device *rdev); 2929 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev); 2930 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev, 2931 u8 perf_req, bool advertise); 2932 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev); 2933 #else 2934 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; } 2935 static inline void radeon_acpi_fini(struct radeon_device *rdev) { } 2936 #endif 2937 2938 int radeon_cs_packet_parse(struct radeon_cs_parser *p, 2939 struct radeon_cs_packet *pkt, 2940 unsigned idx); 2941 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p); 2942 void radeon_cs_dump_packet(struct radeon_cs_parser *p, 2943 struct radeon_cs_packet *pkt); 2944 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p, 2945 struct radeon_bo_list **cs_reloc, 2946 int nomm); 2947 int r600_cs_common_vline_parse(struct radeon_cs_parser *p, 2948 uint32_t *vline_start_end, 2949 uint32_t *vline_status); 2950 2951 /* interrupt control register helpers */ 2952 void radeon_irq_kms_set_irq_n_enabled(struct radeon_device *rdev, 2953 u32 reg, u32 mask, 2954 bool enable, const char *name, 2955 unsigned n); 2956 2957 /* Audio component binding */ 2958 void radeon_audio_component_init(struct radeon_device *rdev); 2959 void radeon_audio_component_fini(struct radeon_device *rdev); 2960 2961 #include "radeon_object.h" 2962 2963 #endif 2964