1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __RADEON_H__ 29 #define __RADEON_H__ 30 31 /* TODO: Here are things that needs to be done : 32 * - surface allocator & initializer : (bit like scratch reg) should 33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings 34 * related to surface 35 * - WB : write back stuff (do it bit like scratch reg things) 36 * - Vblank : look at Jesse's rework and what we should do 37 * - r600/r700: gart & cp 38 * - cs : clean cs ioctl use bitmap & things like that. 39 * - power management stuff 40 * - Barrier in gart code 41 * - Unmappabled vram ? 42 * - TESTING, TESTING, TESTING 43 */ 44 45 /* Initialization path: 46 * We expect that acceleration initialization might fail for various 47 * reasons even thought we work hard to make it works on most 48 * configurations. In order to still have a working userspace in such 49 * situation the init path must succeed up to the memory controller 50 * initialization point. Failure before this point are considered as 51 * fatal error. Here is the init callchain : 52 * radeon_device_init perform common structure, mutex initialization 53 * asic_init setup the GPU memory layout and perform all 54 * one time initialization (failure in this 55 * function are considered fatal) 56 * asic_startup setup the GPU acceleration, in order to 57 * follow guideline the first thing this 58 * function should do is setting the GPU 59 * memory controller (only MC setup failure 60 * are considered as fatal) 61 */ 62 63 #include <asm/atomic.h> 64 #include <linux/wait.h> 65 #include <linux/list.h> 66 #include <linux/kref.h> 67 68 #include <ttm/ttm_bo_api.h> 69 #include <ttm/ttm_bo_driver.h> 70 #include <ttm/ttm_placement.h> 71 #include <ttm/ttm_module.h> 72 73 #include "radeon_family.h" 74 #include "radeon_mode.h" 75 #include "radeon_reg.h" 76 77 /* 78 * Modules parameters. 79 */ 80 extern int radeon_no_wb; 81 extern int radeon_modeset; 82 extern int radeon_dynclks; 83 extern int radeon_r4xx_atom; 84 extern int radeon_agpmode; 85 extern int radeon_vram_limit; 86 extern int radeon_gart_size; 87 extern int radeon_benchmarking; 88 extern int radeon_testing; 89 extern int radeon_connector_table; 90 extern int radeon_tv; 91 extern int radeon_new_pll; 92 extern int radeon_dynpm; 93 extern int radeon_audio; 94 extern int radeon_disp_priority; 95 extern int radeon_hw_i2c; 96 97 /* 98 * Copy from radeon_drv.h so we don't have to include both and have conflicting 99 * symbol; 100 */ 101 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 102 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) 103 /* RADEON_IB_POOL_SIZE must be a power of 2 */ 104 #define RADEON_IB_POOL_SIZE 16 105 #define RADEON_DEBUGFS_MAX_NUM_FILES 32 106 #define RADEONFB_CONN_LIMIT 4 107 #define RADEON_BIOS_NUM_SCRATCH 8 108 109 /* 110 * Errata workarounds. 111 */ 112 enum radeon_pll_errata { 113 CHIP_ERRATA_R300_CG = 0x00000001, 114 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, 115 CHIP_ERRATA_PLL_DELAY = 0x00000004 116 }; 117 118 119 struct radeon_device; 120 121 122 /* 123 * BIOS. 124 */ 125 #define ATRM_BIOS_PAGE 4096 126 127 #if defined(CONFIG_VGA_SWITCHEROO) 128 bool radeon_atrm_supported(struct pci_dev *pdev); 129 int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len); 130 #else 131 static inline bool radeon_atrm_supported(struct pci_dev *pdev) 132 { 133 return false; 134 } 135 136 static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){ 137 return -EINVAL; 138 } 139 #endif 140 bool radeon_get_bios(struct radeon_device *rdev); 141 142 143 /* 144 * Dummy page 145 */ 146 struct radeon_dummy_page { 147 struct page *page; 148 dma_addr_t addr; 149 }; 150 int radeon_dummy_page_init(struct radeon_device *rdev); 151 void radeon_dummy_page_fini(struct radeon_device *rdev); 152 153 154 /* 155 * Clocks 156 */ 157 struct radeon_clock { 158 struct radeon_pll p1pll; 159 struct radeon_pll p2pll; 160 struct radeon_pll dcpll; 161 struct radeon_pll spll; 162 struct radeon_pll mpll; 163 /* 10 Khz units */ 164 uint32_t default_mclk; 165 uint32_t default_sclk; 166 uint32_t default_dispclk; 167 uint32_t dp_extclk; 168 }; 169 170 /* 171 * Power management 172 */ 173 int radeon_pm_init(struct radeon_device *rdev); 174 void radeon_pm_fini(struct radeon_device *rdev); 175 void radeon_pm_compute_clocks(struct radeon_device *rdev); 176 void radeon_combios_get_power_modes(struct radeon_device *rdev); 177 void radeon_atombios_get_power_modes(struct radeon_device *rdev); 178 179 /* 180 * Fences. 181 */ 182 struct radeon_fence_driver { 183 uint32_t scratch_reg; 184 atomic_t seq; 185 uint32_t last_seq; 186 unsigned long last_jiffies; 187 unsigned long last_timeout; 188 wait_queue_head_t queue; 189 rwlock_t lock; 190 struct list_head created; 191 struct list_head emited; 192 struct list_head signaled; 193 bool initialized; 194 }; 195 196 struct radeon_fence { 197 struct radeon_device *rdev; 198 struct kref kref; 199 struct list_head list; 200 /* protected by radeon_fence.lock */ 201 uint32_t seq; 202 bool emited; 203 bool signaled; 204 }; 205 206 int radeon_fence_driver_init(struct radeon_device *rdev); 207 void radeon_fence_driver_fini(struct radeon_device *rdev); 208 int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence); 209 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence); 210 void radeon_fence_process(struct radeon_device *rdev); 211 bool radeon_fence_signaled(struct radeon_fence *fence); 212 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); 213 int radeon_fence_wait_next(struct radeon_device *rdev); 214 int radeon_fence_wait_last(struct radeon_device *rdev); 215 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); 216 void radeon_fence_unref(struct radeon_fence **fence); 217 218 /* 219 * Tiling registers 220 */ 221 struct radeon_surface_reg { 222 struct radeon_bo *bo; 223 }; 224 225 #define RADEON_GEM_MAX_SURFACES 8 226 227 /* 228 * TTM. 229 */ 230 struct radeon_mman { 231 struct ttm_bo_global_ref bo_global_ref; 232 struct ttm_global_reference mem_global_ref; 233 struct ttm_bo_device bdev; 234 bool mem_global_referenced; 235 bool initialized; 236 }; 237 238 struct radeon_bo { 239 /* Protected by gem.mutex */ 240 struct list_head list; 241 /* Protected by tbo.reserved */ 242 u32 placements[3]; 243 struct ttm_placement placement; 244 struct ttm_buffer_object tbo; 245 struct ttm_bo_kmap_obj kmap; 246 unsigned pin_count; 247 void *kptr; 248 u32 tiling_flags; 249 u32 pitch; 250 int surface_reg; 251 /* Constant after initialization */ 252 struct radeon_device *rdev; 253 struct drm_gem_object *gobj; 254 }; 255 256 struct radeon_bo_list { 257 struct list_head list; 258 struct radeon_bo *bo; 259 uint64_t gpu_offset; 260 unsigned rdomain; 261 unsigned wdomain; 262 u32 tiling_flags; 263 }; 264 265 /* 266 * GEM objects. 267 */ 268 struct radeon_gem { 269 struct mutex mutex; 270 struct list_head objects; 271 }; 272 273 int radeon_gem_init(struct radeon_device *rdev); 274 void radeon_gem_fini(struct radeon_device *rdev); 275 int radeon_gem_object_create(struct radeon_device *rdev, int size, 276 int alignment, int initial_domain, 277 bool discardable, bool kernel, 278 struct drm_gem_object **obj); 279 int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain, 280 uint64_t *gpu_addr); 281 void radeon_gem_object_unpin(struct drm_gem_object *obj); 282 283 284 /* 285 * GART structures, functions & helpers 286 */ 287 struct radeon_mc; 288 289 struct radeon_gart_table_ram { 290 volatile uint32_t *ptr; 291 }; 292 293 struct radeon_gart_table_vram { 294 struct radeon_bo *robj; 295 volatile uint32_t *ptr; 296 }; 297 298 union radeon_gart_table { 299 struct radeon_gart_table_ram ram; 300 struct radeon_gart_table_vram vram; 301 }; 302 303 #define RADEON_GPU_PAGE_SIZE 4096 304 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) 305 306 struct radeon_gart { 307 dma_addr_t table_addr; 308 unsigned num_gpu_pages; 309 unsigned num_cpu_pages; 310 unsigned table_size; 311 union radeon_gart_table table; 312 struct page **pages; 313 dma_addr_t *pages_addr; 314 bool ready; 315 }; 316 317 int radeon_gart_table_ram_alloc(struct radeon_device *rdev); 318 void radeon_gart_table_ram_free(struct radeon_device *rdev); 319 int radeon_gart_table_vram_alloc(struct radeon_device *rdev); 320 void radeon_gart_table_vram_free(struct radeon_device *rdev); 321 int radeon_gart_init(struct radeon_device *rdev); 322 void radeon_gart_fini(struct radeon_device *rdev); 323 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, 324 int pages); 325 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, 326 int pages, struct page **pagelist); 327 328 329 /* 330 * GPU MC structures, functions & helpers 331 */ 332 struct radeon_mc { 333 resource_size_t aper_size; 334 resource_size_t aper_base; 335 resource_size_t agp_base; 336 /* for some chips with <= 32MB we need to lie 337 * about vram size near mc fb location */ 338 u64 mc_vram_size; 339 u64 visible_vram_size; 340 u64 gtt_size; 341 u64 gtt_start; 342 u64 gtt_end; 343 u64 vram_start; 344 u64 vram_end; 345 unsigned vram_width; 346 u64 real_vram_size; 347 int vram_mtrr; 348 bool vram_is_ddr; 349 bool igp_sideport_enabled; 350 }; 351 352 bool radeon_combios_sideport_present(struct radeon_device *rdev); 353 bool radeon_atombios_sideport_present(struct radeon_device *rdev); 354 355 /* 356 * GPU scratch registers structures, functions & helpers 357 */ 358 struct radeon_scratch { 359 unsigned num_reg; 360 bool free[32]; 361 uint32_t reg[32]; 362 }; 363 364 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); 365 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); 366 367 368 /* 369 * IRQS. 370 */ 371 struct radeon_irq { 372 bool installed; 373 bool sw_int; 374 /* FIXME: use a define max crtc rather than hardcode it */ 375 bool crtc_vblank_int[2]; 376 wait_queue_head_t vblank_queue; 377 /* FIXME: use defines for max hpd/dacs */ 378 bool hpd[6]; 379 spinlock_t sw_lock; 380 int sw_refcount; 381 }; 382 383 int radeon_irq_kms_init(struct radeon_device *rdev); 384 void radeon_irq_kms_fini(struct radeon_device *rdev); 385 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev); 386 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev); 387 388 /* 389 * CP & ring. 390 */ 391 struct radeon_ib { 392 struct list_head list; 393 unsigned idx; 394 uint64_t gpu_addr; 395 struct radeon_fence *fence; 396 uint32_t *ptr; 397 uint32_t length_dw; 398 bool free; 399 }; 400 401 /* 402 * locking - 403 * mutex protects scheduled_ibs, ready, alloc_bm 404 */ 405 struct radeon_ib_pool { 406 struct mutex mutex; 407 struct radeon_bo *robj; 408 struct list_head bogus_ib; 409 struct radeon_ib ibs[RADEON_IB_POOL_SIZE]; 410 bool ready; 411 unsigned head_id; 412 }; 413 414 struct radeon_cp { 415 struct radeon_bo *ring_obj; 416 volatile uint32_t *ring; 417 unsigned rptr; 418 unsigned wptr; 419 unsigned wptr_old; 420 unsigned ring_size; 421 unsigned ring_free_dw; 422 int count_dw; 423 uint64_t gpu_addr; 424 uint32_t align_mask; 425 uint32_t ptr_mask; 426 struct mutex mutex; 427 bool ready; 428 }; 429 430 /* 431 * R6xx+ IH ring 432 */ 433 struct r600_ih { 434 struct radeon_bo *ring_obj; 435 volatile uint32_t *ring; 436 unsigned rptr; 437 unsigned wptr; 438 unsigned wptr_old; 439 unsigned ring_size; 440 uint64_t gpu_addr; 441 uint32_t ptr_mask; 442 spinlock_t lock; 443 bool enabled; 444 }; 445 446 struct r600_blit { 447 struct mutex mutex; 448 struct radeon_bo *shader_obj; 449 u64 shader_gpu_addr; 450 u32 vs_offset, ps_offset; 451 u32 state_offset; 452 u32 state_len; 453 u32 vb_used, vb_total; 454 struct radeon_ib *vb_ib; 455 }; 456 457 int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib); 458 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib); 459 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib); 460 int radeon_ib_pool_init(struct radeon_device *rdev); 461 void radeon_ib_pool_fini(struct radeon_device *rdev); 462 int radeon_ib_test(struct radeon_device *rdev); 463 extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib); 464 /* Ring access between begin & end cannot sleep */ 465 void radeon_ring_free_size(struct radeon_device *rdev); 466 int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw); 467 void radeon_ring_unlock_commit(struct radeon_device *rdev); 468 void radeon_ring_unlock_undo(struct radeon_device *rdev); 469 int radeon_ring_test(struct radeon_device *rdev); 470 int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size); 471 void radeon_ring_fini(struct radeon_device *rdev); 472 473 474 /* 475 * CS. 476 */ 477 struct radeon_cs_reloc { 478 struct drm_gem_object *gobj; 479 struct radeon_bo *robj; 480 struct radeon_bo_list lobj; 481 uint32_t handle; 482 uint32_t flags; 483 }; 484 485 struct radeon_cs_chunk { 486 uint32_t chunk_id; 487 uint32_t length_dw; 488 int kpage_idx[2]; 489 uint32_t *kpage[2]; 490 uint32_t *kdata; 491 void __user *user_ptr; 492 int last_copied_page; 493 int last_page_index; 494 }; 495 496 struct radeon_cs_parser { 497 struct device *dev; 498 struct radeon_device *rdev; 499 struct drm_file *filp; 500 /* chunks */ 501 unsigned nchunks; 502 struct radeon_cs_chunk *chunks; 503 uint64_t *chunks_array; 504 /* IB */ 505 unsigned idx; 506 /* relocations */ 507 unsigned nrelocs; 508 struct radeon_cs_reloc *relocs; 509 struct radeon_cs_reloc **relocs_ptr; 510 struct list_head validated; 511 /* indices of various chunks */ 512 int chunk_ib_idx; 513 int chunk_relocs_idx; 514 struct radeon_ib *ib; 515 void *track; 516 unsigned family; 517 int parser_error; 518 }; 519 520 extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx); 521 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p); 522 523 524 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) 525 { 526 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; 527 u32 pg_idx, pg_offset; 528 u32 idx_value = 0; 529 int new_page; 530 531 pg_idx = (idx * 4) / PAGE_SIZE; 532 pg_offset = (idx * 4) % PAGE_SIZE; 533 534 if (ibc->kpage_idx[0] == pg_idx) 535 return ibc->kpage[0][pg_offset/4]; 536 if (ibc->kpage_idx[1] == pg_idx) 537 return ibc->kpage[1][pg_offset/4]; 538 539 new_page = radeon_cs_update_pages(p, pg_idx); 540 if (new_page < 0) { 541 p->parser_error = new_page; 542 return 0; 543 } 544 545 idx_value = ibc->kpage[new_page][pg_offset/4]; 546 return idx_value; 547 } 548 549 struct radeon_cs_packet { 550 unsigned idx; 551 unsigned type; 552 unsigned reg; 553 unsigned opcode; 554 int count; 555 unsigned one_reg_wr; 556 }; 557 558 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, 559 struct radeon_cs_packet *pkt, 560 unsigned idx, unsigned reg); 561 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, 562 struct radeon_cs_packet *pkt); 563 564 565 /* 566 * AGP 567 */ 568 int radeon_agp_init(struct radeon_device *rdev); 569 void radeon_agp_resume(struct radeon_device *rdev); 570 void radeon_agp_fini(struct radeon_device *rdev); 571 572 573 /* 574 * Writeback 575 */ 576 struct radeon_wb { 577 struct radeon_bo *wb_obj; 578 volatile uint32_t *wb; 579 uint64_t gpu_addr; 580 }; 581 582 /** 583 * struct radeon_pm - power management datas 584 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) 585 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) 586 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) 587 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) 588 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) 589 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) 590 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) 591 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) 592 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) 593 * @sclk: GPU clock Mhz (core bandwith depends of this clock) 594 * @needed_bandwidth: current bandwidth needs 595 * 596 * It keeps track of various data needed to take powermanagement decision. 597 * Bandwith need is used to determine minimun clock of the GPU and memory. 598 * Equation between gpu/memory clock and available bandwidth is hw dependent 599 * (type of memory, bus size, efficiency, ...) 600 */ 601 enum radeon_pm_state { 602 PM_STATE_DISABLED, 603 PM_STATE_MINIMUM, 604 PM_STATE_PAUSED, 605 PM_STATE_ACTIVE 606 }; 607 enum radeon_pm_action { 608 PM_ACTION_NONE, 609 PM_ACTION_MINIMUM, 610 PM_ACTION_DOWNCLOCK, 611 PM_ACTION_UPCLOCK 612 }; 613 614 enum radeon_voltage_type { 615 VOLTAGE_NONE = 0, 616 VOLTAGE_GPIO, 617 VOLTAGE_VDDC, 618 VOLTAGE_SW 619 }; 620 621 enum radeon_pm_state_type { 622 POWER_STATE_TYPE_DEFAULT, 623 POWER_STATE_TYPE_POWERSAVE, 624 POWER_STATE_TYPE_BATTERY, 625 POWER_STATE_TYPE_BALANCED, 626 POWER_STATE_TYPE_PERFORMANCE, 627 }; 628 629 enum radeon_pm_clock_mode_type { 630 POWER_MODE_TYPE_DEFAULT, 631 POWER_MODE_TYPE_LOW, 632 POWER_MODE_TYPE_MID, 633 POWER_MODE_TYPE_HIGH, 634 }; 635 636 struct radeon_voltage { 637 enum radeon_voltage_type type; 638 /* gpio voltage */ 639 struct radeon_gpio_rec gpio; 640 u32 delay; /* delay in usec from voltage drop to sclk change */ 641 bool active_high; /* voltage drop is active when bit is high */ 642 /* VDDC voltage */ 643 u8 vddc_id; /* index into vddc voltage table */ 644 u8 vddci_id; /* index into vddci voltage table */ 645 bool vddci_enabled; 646 /* r6xx+ sw */ 647 u32 voltage; 648 }; 649 650 struct radeon_pm_non_clock_info { 651 /* pcie lanes */ 652 int pcie_lanes; 653 /* standardized non-clock flags */ 654 u32 flags; 655 }; 656 657 struct radeon_pm_clock_info { 658 /* memory clock */ 659 u32 mclk; 660 /* engine clock */ 661 u32 sclk; 662 /* voltage info */ 663 struct radeon_voltage voltage; 664 /* standardized clock flags - not sure we'll need these */ 665 u32 flags; 666 }; 667 668 struct radeon_power_state { 669 enum radeon_pm_state_type type; 670 /* XXX: use a define for num clock modes */ 671 struct radeon_pm_clock_info clock_info[8]; 672 /* number of valid clock modes in this power state */ 673 int num_clock_modes; 674 struct radeon_pm_clock_info *default_clock_mode; 675 /* non clock info about this state */ 676 struct radeon_pm_non_clock_info non_clock_info; 677 bool voltage_drop_active; 678 }; 679 680 /* 681 * Some modes are overclocked by very low value, accept them 682 */ 683 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ 684 685 struct radeon_pm { 686 struct mutex mutex; 687 struct delayed_work idle_work; 688 enum radeon_pm_state state; 689 enum radeon_pm_action planned_action; 690 unsigned long action_timeout; 691 bool downclocked; 692 int active_crtcs; 693 int req_vblank; 694 bool vblank_sync; 695 fixed20_12 max_bandwidth; 696 fixed20_12 igp_sideport_mclk; 697 fixed20_12 igp_system_mclk; 698 fixed20_12 igp_ht_link_clk; 699 fixed20_12 igp_ht_link_width; 700 fixed20_12 k8_bandwidth; 701 fixed20_12 sideport_bandwidth; 702 fixed20_12 ht_bandwidth; 703 fixed20_12 core_bandwidth; 704 fixed20_12 sclk; 705 fixed20_12 mclk; 706 fixed20_12 needed_bandwidth; 707 /* XXX: use a define for num power modes */ 708 struct radeon_power_state power_state[8]; 709 /* number of valid power states */ 710 int num_power_states; 711 struct radeon_power_state *current_power_state; 712 struct radeon_pm_clock_info *current_clock_mode; 713 struct radeon_power_state *requested_power_state; 714 struct radeon_pm_clock_info *requested_clock_mode; 715 struct radeon_power_state *default_power_state; 716 struct radeon_i2c_chan *i2c_bus; 717 }; 718 719 720 /* 721 * Benchmarking 722 */ 723 void radeon_benchmark(struct radeon_device *rdev); 724 725 726 /* 727 * Testing 728 */ 729 void radeon_test_moves(struct radeon_device *rdev); 730 731 732 /* 733 * Debugfs 734 */ 735 int radeon_debugfs_add_files(struct radeon_device *rdev, 736 struct drm_info_list *files, 737 unsigned nfiles); 738 int radeon_debugfs_fence_init(struct radeon_device *rdev); 739 740 741 /* 742 * ASIC specific functions. 743 */ 744 struct radeon_asic { 745 int (*init)(struct radeon_device *rdev); 746 void (*fini)(struct radeon_device *rdev); 747 int (*resume)(struct radeon_device *rdev); 748 int (*suspend)(struct radeon_device *rdev); 749 void (*vga_set_state)(struct radeon_device *rdev, bool state); 750 bool (*gpu_is_lockup)(struct radeon_device *rdev); 751 int (*asic_reset)(struct radeon_device *rdev); 752 void (*gart_tlb_flush)(struct radeon_device *rdev); 753 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr); 754 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size); 755 void (*cp_fini)(struct radeon_device *rdev); 756 void (*cp_disable)(struct radeon_device *rdev); 757 void (*cp_commit)(struct radeon_device *rdev); 758 void (*ring_start)(struct radeon_device *rdev); 759 int (*ring_test)(struct radeon_device *rdev); 760 void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); 761 int (*irq_set)(struct radeon_device *rdev); 762 int (*irq_process)(struct radeon_device *rdev); 763 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); 764 void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence); 765 int (*cs_parse)(struct radeon_cs_parser *p); 766 int (*copy_blit)(struct radeon_device *rdev, 767 uint64_t src_offset, 768 uint64_t dst_offset, 769 unsigned num_pages, 770 struct radeon_fence *fence); 771 int (*copy_dma)(struct radeon_device *rdev, 772 uint64_t src_offset, 773 uint64_t dst_offset, 774 unsigned num_pages, 775 struct radeon_fence *fence); 776 int (*copy)(struct radeon_device *rdev, 777 uint64_t src_offset, 778 uint64_t dst_offset, 779 unsigned num_pages, 780 struct radeon_fence *fence); 781 uint32_t (*get_engine_clock)(struct radeon_device *rdev); 782 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); 783 uint32_t (*get_memory_clock)(struct radeon_device *rdev); 784 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); 785 int (*get_pcie_lanes)(struct radeon_device *rdev); 786 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); 787 void (*set_clock_gating)(struct radeon_device *rdev, int enable); 788 int (*set_surface_reg)(struct radeon_device *rdev, int reg, 789 uint32_t tiling_flags, uint32_t pitch, 790 uint32_t offset, uint32_t obj_size); 791 void (*clear_surface_reg)(struct radeon_device *rdev, int reg); 792 void (*bandwidth_update)(struct radeon_device *rdev); 793 void (*hpd_init)(struct radeon_device *rdev); 794 void (*hpd_fini)(struct radeon_device *rdev); 795 bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 796 void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 797 /* ioctl hw specific callback. Some hw might want to perform special 798 * operation on specific ioctl. For instance on wait idle some hw 799 * might want to perform and HDP flush through MMIO as it seems that 800 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed 801 * through ring. 802 */ 803 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo); 804 }; 805 806 /* 807 * Asic structures 808 */ 809 struct r100_gpu_lockup { 810 unsigned long last_jiffies; 811 u32 last_cp_rptr; 812 }; 813 814 struct r100_asic { 815 const unsigned *reg_safe_bm; 816 unsigned reg_safe_bm_size; 817 u32 hdp_cntl; 818 struct r100_gpu_lockup lockup; 819 }; 820 821 struct r300_asic { 822 const unsigned *reg_safe_bm; 823 unsigned reg_safe_bm_size; 824 u32 resync_scratch; 825 u32 hdp_cntl; 826 struct r100_gpu_lockup lockup; 827 }; 828 829 struct r600_asic { 830 unsigned max_pipes; 831 unsigned max_tile_pipes; 832 unsigned max_simds; 833 unsigned max_backends; 834 unsigned max_gprs; 835 unsigned max_threads; 836 unsigned max_stack_entries; 837 unsigned max_hw_contexts; 838 unsigned max_gs_threads; 839 unsigned sx_max_export_size; 840 unsigned sx_max_export_pos_size; 841 unsigned sx_max_export_smx_size; 842 unsigned sq_num_cf_insts; 843 unsigned tiling_nbanks; 844 unsigned tiling_npipes; 845 unsigned tiling_group_size; 846 struct r100_gpu_lockup lockup; 847 }; 848 849 struct rv770_asic { 850 unsigned max_pipes; 851 unsigned max_tile_pipes; 852 unsigned max_simds; 853 unsigned max_backends; 854 unsigned max_gprs; 855 unsigned max_threads; 856 unsigned max_stack_entries; 857 unsigned max_hw_contexts; 858 unsigned max_gs_threads; 859 unsigned sx_max_export_size; 860 unsigned sx_max_export_pos_size; 861 unsigned sx_max_export_smx_size; 862 unsigned sq_num_cf_insts; 863 unsigned sx_num_of_sets; 864 unsigned sc_prim_fifo_size; 865 unsigned sc_hiz_tile_fifo_size; 866 unsigned sc_earlyz_tile_fifo_fize; 867 unsigned tiling_nbanks; 868 unsigned tiling_npipes; 869 unsigned tiling_group_size; 870 struct r100_gpu_lockup lockup; 871 }; 872 873 union radeon_asic_config { 874 struct r300_asic r300; 875 struct r100_asic r100; 876 struct r600_asic r600; 877 struct rv770_asic rv770; 878 }; 879 880 /* 881 * asic initizalization from radeon_asic.c 882 */ 883 void radeon_agp_disable(struct radeon_device *rdev); 884 int radeon_asic_init(struct radeon_device *rdev); 885 886 887 /* 888 * IOCTL. 889 */ 890 int radeon_gem_info_ioctl(struct drm_device *dev, void *data, 891 struct drm_file *filp); 892 int radeon_gem_create_ioctl(struct drm_device *dev, void *data, 893 struct drm_file *filp); 894 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, 895 struct drm_file *file_priv); 896 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, 897 struct drm_file *file_priv); 898 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, 899 struct drm_file *file_priv); 900 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, 901 struct drm_file *file_priv); 902 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, 903 struct drm_file *filp); 904 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, 905 struct drm_file *filp); 906 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, 907 struct drm_file *filp); 908 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 909 struct drm_file *filp); 910 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 911 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, 912 struct drm_file *filp); 913 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, 914 struct drm_file *filp); 915 916 917 /* 918 * Core structure, functions and helpers. 919 */ 920 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); 921 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); 922 923 struct radeon_device { 924 struct device *dev; 925 struct drm_device *ddev; 926 struct pci_dev *pdev; 927 /* ASIC */ 928 union radeon_asic_config config; 929 enum radeon_family family; 930 unsigned long flags; 931 int usec_timeout; 932 enum radeon_pll_errata pll_errata; 933 int num_gb_pipes; 934 int num_z_pipes; 935 int disp_priority; 936 /* BIOS */ 937 uint8_t *bios; 938 bool is_atom_bios; 939 uint16_t bios_header_start; 940 struct radeon_bo *stollen_vga_memory; 941 struct fb_info *fbdev_info; 942 struct radeon_bo *fbdev_rbo; 943 struct radeon_framebuffer *fbdev_rfb; 944 /* Register mmio */ 945 resource_size_t rmmio_base; 946 resource_size_t rmmio_size; 947 void *rmmio; 948 radeon_rreg_t mc_rreg; 949 radeon_wreg_t mc_wreg; 950 radeon_rreg_t pll_rreg; 951 radeon_wreg_t pll_wreg; 952 uint32_t pcie_reg_mask; 953 radeon_rreg_t pciep_rreg; 954 radeon_wreg_t pciep_wreg; 955 struct radeon_clock clock; 956 struct radeon_mc mc; 957 struct radeon_gart gart; 958 struct radeon_mode_info mode_info; 959 struct radeon_scratch scratch; 960 struct radeon_mman mman; 961 struct radeon_fence_driver fence_drv; 962 struct radeon_cp cp; 963 struct radeon_ib_pool ib_pool; 964 struct radeon_irq irq; 965 struct radeon_asic *asic; 966 struct radeon_gem gem; 967 struct radeon_pm pm; 968 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; 969 struct mutex cs_mutex; 970 struct radeon_wb wb; 971 struct radeon_dummy_page dummy_page; 972 bool gpu_lockup; 973 bool shutdown; 974 bool suspend; 975 bool need_dma32; 976 bool accel_working; 977 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; 978 const struct firmware *me_fw; /* all family ME firmware */ 979 const struct firmware *pfp_fw; /* r6/700 PFP firmware */ 980 const struct firmware *rlc_fw; /* r6/700 RLC firmware */ 981 struct r600_blit r600_blit; 982 int msi_enabled; /* msi enabled */ 983 struct r600_ih ih; /* r6/700 interrupt ring */ 984 struct workqueue_struct *wq; 985 struct work_struct hotplug_work; 986 int num_crtc; /* number of crtcs */ 987 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ 988 989 /* audio stuff */ 990 struct timer_list audio_timer; 991 int audio_channels; 992 int audio_rate; 993 int audio_bits_per_sample; 994 uint8_t audio_status_bits; 995 uint8_t audio_category_code; 996 997 bool powered_down; 998 }; 999 1000 int radeon_device_init(struct radeon_device *rdev, 1001 struct drm_device *ddev, 1002 struct pci_dev *pdev, 1003 uint32_t flags); 1004 void radeon_device_fini(struct radeon_device *rdev); 1005 int radeon_gpu_wait_for_idle(struct radeon_device *rdev); 1006 1007 /* r600 blit */ 1008 int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes); 1009 void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence); 1010 void r600_kms_blit_copy(struct radeon_device *rdev, 1011 u64 src_gpu_addr, u64 dst_gpu_addr, 1012 int size_bytes); 1013 1014 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg) 1015 { 1016 if (reg < rdev->rmmio_size) 1017 return readl(((void __iomem *)rdev->rmmio) + reg); 1018 else { 1019 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); 1020 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); 1021 } 1022 } 1023 1024 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 1025 { 1026 if (reg < rdev->rmmio_size) 1027 writel(v, ((void __iomem *)rdev->rmmio) + reg); 1028 else { 1029 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); 1030 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); 1031 } 1032 } 1033 1034 /* 1035 * Cast helper 1036 */ 1037 #define to_radeon_fence(p) ((struct radeon_fence *)(p)) 1038 1039 /* 1040 * Registers read & write functions. 1041 */ 1042 #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg)) 1043 #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg)) 1044 #define RREG32(reg) r100_mm_rreg(rdev, (reg)) 1045 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg))) 1046 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v)) 1047 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1048 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1049 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) 1050 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) 1051 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) 1052 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) 1053 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) 1054 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) 1055 #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg)) 1056 #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) 1057 #define WREG32_P(reg, val, mask) \ 1058 do { \ 1059 uint32_t tmp_ = RREG32(reg); \ 1060 tmp_ &= (mask); \ 1061 tmp_ |= ((val) & ~(mask)); \ 1062 WREG32(reg, tmp_); \ 1063 } while (0) 1064 #define WREG32_PLL_P(reg, val, mask) \ 1065 do { \ 1066 uint32_t tmp_ = RREG32_PLL(reg); \ 1067 tmp_ &= (mask); \ 1068 tmp_ |= ((val) & ~(mask)); \ 1069 WREG32_PLL(reg, tmp_); \ 1070 } while (0) 1071 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg))) 1072 1073 /* 1074 * Indirect registers accessor 1075 */ 1076 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) 1077 { 1078 uint32_t r; 1079 1080 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 1081 r = RREG32(RADEON_PCIE_DATA); 1082 return r; 1083 } 1084 1085 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 1086 { 1087 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 1088 WREG32(RADEON_PCIE_DATA, (v)); 1089 } 1090 1091 void r100_pll_errata_after_index(struct radeon_device *rdev); 1092 1093 1094 /* 1095 * ASICs helpers. 1096 */ 1097 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ 1098 (rdev->pdev->device == 0x5969)) 1099 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ 1100 (rdev->family == CHIP_RV200) || \ 1101 (rdev->family == CHIP_RS100) || \ 1102 (rdev->family == CHIP_RS200) || \ 1103 (rdev->family == CHIP_RV250) || \ 1104 (rdev->family == CHIP_RV280) || \ 1105 (rdev->family == CHIP_RS300)) 1106 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ 1107 (rdev->family == CHIP_RV350) || \ 1108 (rdev->family == CHIP_R350) || \ 1109 (rdev->family == CHIP_RV380) || \ 1110 (rdev->family == CHIP_R420) || \ 1111 (rdev->family == CHIP_R423) || \ 1112 (rdev->family == CHIP_RV410) || \ 1113 (rdev->family == CHIP_RS400) || \ 1114 (rdev->family == CHIP_RS480)) 1115 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) 1116 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) 1117 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) 1118 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) 1119 1120 /* 1121 * BIOS helpers. 1122 */ 1123 #define RBIOS8(i) (rdev->bios[i]) 1124 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1125 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1126 1127 int radeon_combios_init(struct radeon_device *rdev); 1128 void radeon_combios_fini(struct radeon_device *rdev); 1129 int radeon_atombios_init(struct radeon_device *rdev); 1130 void radeon_atombios_fini(struct radeon_device *rdev); 1131 1132 1133 /* 1134 * RING helpers. 1135 */ 1136 static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v) 1137 { 1138 #if DRM_DEBUG_CODE 1139 if (rdev->cp.count_dw <= 0) { 1140 DRM_ERROR("radeon: writting more dword to ring than expected !\n"); 1141 } 1142 #endif 1143 rdev->cp.ring[rdev->cp.wptr++] = v; 1144 rdev->cp.wptr &= rdev->cp.ptr_mask; 1145 rdev->cp.count_dw--; 1146 rdev->cp.ring_free_dw--; 1147 } 1148 1149 1150 /* 1151 * ASICs macro. 1152 */ 1153 #define radeon_init(rdev) (rdev)->asic->init((rdev)) 1154 #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) 1155 #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) 1156 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) 1157 #define radeon_cs_parse(p) rdev->asic->cs_parse((p)) 1158 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) 1159 #define radeon_gpu_is_lockup(rdev) (rdev)->asic->gpu_is_lockup((rdev)) 1160 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) 1161 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev)) 1162 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p)) 1163 #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev)) 1164 #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev)) 1165 #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev)) 1166 #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib)) 1167 #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev)) 1168 #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev)) 1169 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc)) 1170 #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence)) 1171 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f)) 1172 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f)) 1173 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f)) 1174 #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev)) 1175 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e)) 1176 #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev)) 1177 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e)) 1178 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev)) 1179 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l)) 1180 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e)) 1181 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s))) 1182 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r))) 1183 #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev)) 1184 #define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev)) 1185 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev)) 1186 #define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd)) 1187 #define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd)) 1188 1189 /* Common functions */ 1190 /* AGP */ 1191 extern void radeon_agp_disable(struct radeon_device *rdev); 1192 extern int radeon_gart_table_vram_pin(struct radeon_device *rdev); 1193 extern void radeon_gart_restore(struct radeon_device *rdev); 1194 extern int radeon_modeset_init(struct radeon_device *rdev); 1195 extern void radeon_modeset_fini(struct radeon_device *rdev); 1196 extern bool radeon_card_posted(struct radeon_device *rdev); 1197 extern void radeon_update_bandwidth_info(struct radeon_device *rdev); 1198 extern void radeon_update_display_priority(struct radeon_device *rdev); 1199 extern bool radeon_boot_test_post_card(struct radeon_device *rdev); 1200 extern int radeon_clocks_init(struct radeon_device *rdev); 1201 extern void radeon_clocks_fini(struct radeon_device *rdev); 1202 extern void radeon_scratch_init(struct radeon_device *rdev); 1203 extern void radeon_surface_init(struct radeon_device *rdev); 1204 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); 1205 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); 1206 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); 1207 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); 1208 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); 1209 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); 1210 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); 1211 extern int radeon_resume_kms(struct drm_device *dev); 1212 extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state); 1213 1214 /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */ 1215 extern void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_cp *cp); 1216 extern bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_cp *cp); 1217 1218 /* rv200,rv250,rv280 */ 1219 extern void r200_set_safe_registers(struct radeon_device *rdev); 1220 1221 /* r300,r350,rv350,rv370,rv380 */ 1222 extern void r300_set_reg_safe(struct radeon_device *rdev); 1223 extern void r300_mc_program(struct radeon_device *rdev); 1224 extern void r300_mc_init(struct radeon_device *rdev); 1225 extern void r300_clock_startup(struct radeon_device *rdev); 1226 extern int r300_mc_wait_for_idle(struct radeon_device *rdev); 1227 extern int rv370_pcie_gart_init(struct radeon_device *rdev); 1228 extern void rv370_pcie_gart_fini(struct radeon_device *rdev); 1229 extern int rv370_pcie_gart_enable(struct radeon_device *rdev); 1230 extern void rv370_pcie_gart_disable(struct radeon_device *rdev); 1231 1232 /* r420,r423,rv410 */ 1233 extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); 1234 extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); 1235 extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev); 1236 extern void r420_pipes_init(struct radeon_device *rdev); 1237 1238 /* rv515 */ 1239 struct rv515_mc_save { 1240 u32 d1vga_control; 1241 u32 d2vga_control; 1242 u32 vga_render_control; 1243 u32 vga_hdp_control; 1244 u32 d1crtc_control; 1245 u32 d2crtc_control; 1246 }; 1247 extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev); 1248 extern void rv515_vga_render_disable(struct radeon_device *rdev); 1249 extern void rv515_set_safe_registers(struct radeon_device *rdev); 1250 extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save); 1251 extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save); 1252 extern void rv515_clock_startup(struct radeon_device *rdev); 1253 extern void rv515_debugfs(struct radeon_device *rdev); 1254 extern int rv515_suspend(struct radeon_device *rdev); 1255 1256 /* rs400 */ 1257 extern int rs400_gart_init(struct radeon_device *rdev); 1258 extern int rs400_gart_enable(struct radeon_device *rdev); 1259 extern void rs400_gart_adjust_size(struct radeon_device *rdev); 1260 extern void rs400_gart_disable(struct radeon_device *rdev); 1261 extern void rs400_gart_fini(struct radeon_device *rdev); 1262 1263 /* rs600 */ 1264 extern void rs600_set_safe_registers(struct radeon_device *rdev); 1265 extern int rs600_irq_set(struct radeon_device *rdev); 1266 extern void rs600_irq_disable(struct radeon_device *rdev); 1267 1268 /* rs690, rs740 */ 1269 extern void rs690_line_buffer_adjust(struct radeon_device *rdev, 1270 struct drm_display_mode *mode1, 1271 struct drm_display_mode *mode2); 1272 1273 /* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */ 1274 extern void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); 1275 extern bool r600_card_posted(struct radeon_device *rdev); 1276 extern void r600_cp_stop(struct radeon_device *rdev); 1277 extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size); 1278 extern int r600_cp_resume(struct radeon_device *rdev); 1279 extern void r600_cp_fini(struct radeon_device *rdev); 1280 extern int r600_count_pipe_bits(uint32_t val); 1281 extern int r600_mc_wait_for_idle(struct radeon_device *rdev); 1282 extern int r600_pcie_gart_init(struct radeon_device *rdev); 1283 extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); 1284 extern int r600_ib_test(struct radeon_device *rdev); 1285 extern int r600_ring_test(struct radeon_device *rdev); 1286 extern void r600_wb_fini(struct radeon_device *rdev); 1287 extern int r600_wb_enable(struct radeon_device *rdev); 1288 extern void r600_wb_disable(struct radeon_device *rdev); 1289 extern void r600_scratch_init(struct radeon_device *rdev); 1290 extern int r600_blit_init(struct radeon_device *rdev); 1291 extern void r600_blit_fini(struct radeon_device *rdev); 1292 extern int r600_init_microcode(struct radeon_device *rdev); 1293 extern int r600_asic_reset(struct radeon_device *rdev); 1294 /* r600 irq */ 1295 extern int r600_irq_init(struct radeon_device *rdev); 1296 extern void r600_irq_fini(struct radeon_device *rdev); 1297 extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size); 1298 extern int r600_irq_set(struct radeon_device *rdev); 1299 extern void r600_irq_suspend(struct radeon_device *rdev); 1300 /* r600 audio */ 1301 extern int r600_audio_init(struct radeon_device *rdev); 1302 extern int r600_audio_tmds_index(struct drm_encoder *encoder); 1303 extern void r600_audio_set_clock(struct drm_encoder *encoder, int clock); 1304 extern void r600_audio_fini(struct radeon_device *rdev); 1305 extern void r600_hdmi_init(struct drm_encoder *encoder); 1306 extern void r600_hdmi_enable(struct drm_encoder *encoder); 1307 extern void r600_hdmi_disable(struct drm_encoder *encoder); 1308 extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); 1309 extern int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder); 1310 extern void r600_hdmi_update_audio_settings(struct drm_encoder *encoder, 1311 int channels, 1312 int rate, 1313 int bps, 1314 uint8_t status_bits, 1315 uint8_t category_code); 1316 1317 /* evergreen */ 1318 struct evergreen_mc_save { 1319 u32 vga_control[6]; 1320 u32 vga_render_control; 1321 u32 vga_hdp_control; 1322 u32 crtc_control[6]; 1323 }; 1324 1325 #include "radeon_object.h" 1326 1327 #endif 1328