1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __RADEON_H__ 29 #define __RADEON_H__ 30 31 /* TODO: Here are things that needs to be done : 32 * - surface allocator & initializer : (bit like scratch reg) should 33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings 34 * related to surface 35 * - WB : write back stuff (do it bit like scratch reg things) 36 * - Vblank : look at Jesse's rework and what we should do 37 * - r600/r700: gart & cp 38 * - cs : clean cs ioctl use bitmap & things like that. 39 * - power management stuff 40 * - Barrier in gart code 41 * - Unmappabled vram ? 42 * - TESTING, TESTING, TESTING 43 */ 44 45 /* Initialization path: 46 * We expect that acceleration initialization might fail for various 47 * reasons even thought we work hard to make it works on most 48 * configurations. In order to still have a working userspace in such 49 * situation the init path must succeed up to the memory controller 50 * initialization point. Failure before this point are considered as 51 * fatal error. Here is the init callchain : 52 * radeon_device_init perform common structure, mutex initialization 53 * asic_init setup the GPU memory layout and perform all 54 * one time initialization (failure in this 55 * function are considered fatal) 56 * asic_startup setup the GPU acceleration, in order to 57 * follow guideline the first thing this 58 * function should do is setting the GPU 59 * memory controller (only MC setup failure 60 * are considered as fatal) 61 */ 62 63 #include <asm/atomic.h> 64 #include <linux/wait.h> 65 #include <linux/list.h> 66 #include <linux/kref.h> 67 68 #include <ttm/ttm_bo_api.h> 69 #include <ttm/ttm_bo_driver.h> 70 #include <ttm/ttm_placement.h> 71 #include <ttm/ttm_module.h> 72 73 #include "radeon_family.h" 74 #include "radeon_mode.h" 75 #include "radeon_reg.h" 76 77 /* 78 * Modules parameters. 79 */ 80 extern int radeon_no_wb; 81 extern int radeon_modeset; 82 extern int radeon_dynclks; 83 extern int radeon_r4xx_atom; 84 extern int radeon_agpmode; 85 extern int radeon_vram_limit; 86 extern int radeon_gart_size; 87 extern int radeon_benchmarking; 88 extern int radeon_testing; 89 extern int radeon_connector_table; 90 extern int radeon_tv; 91 extern int radeon_new_pll; 92 extern int radeon_audio; 93 extern int radeon_disp_priority; 94 extern int radeon_hw_i2c; 95 96 /* 97 * Copy from radeon_drv.h so we don't have to include both and have conflicting 98 * symbol; 99 */ 100 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 101 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) 102 /* RADEON_IB_POOL_SIZE must be a power of 2 */ 103 #define RADEON_IB_POOL_SIZE 16 104 #define RADEON_DEBUGFS_MAX_NUM_FILES 32 105 #define RADEONFB_CONN_LIMIT 4 106 #define RADEON_BIOS_NUM_SCRATCH 8 107 108 /* 109 * Errata workarounds. 110 */ 111 enum radeon_pll_errata { 112 CHIP_ERRATA_R300_CG = 0x00000001, 113 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, 114 CHIP_ERRATA_PLL_DELAY = 0x00000004 115 }; 116 117 118 struct radeon_device; 119 120 121 /* 122 * BIOS. 123 */ 124 #define ATRM_BIOS_PAGE 4096 125 126 #if defined(CONFIG_VGA_SWITCHEROO) 127 bool radeon_atrm_supported(struct pci_dev *pdev); 128 int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len); 129 #else 130 static inline bool radeon_atrm_supported(struct pci_dev *pdev) 131 { 132 return false; 133 } 134 135 static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){ 136 return -EINVAL; 137 } 138 #endif 139 bool radeon_get_bios(struct radeon_device *rdev); 140 141 142 /* 143 * Dummy page 144 */ 145 struct radeon_dummy_page { 146 struct page *page; 147 dma_addr_t addr; 148 }; 149 int radeon_dummy_page_init(struct radeon_device *rdev); 150 void radeon_dummy_page_fini(struct radeon_device *rdev); 151 152 153 /* 154 * Clocks 155 */ 156 struct radeon_clock { 157 struct radeon_pll p1pll; 158 struct radeon_pll p2pll; 159 struct radeon_pll dcpll; 160 struct radeon_pll spll; 161 struct radeon_pll mpll; 162 /* 10 Khz units */ 163 uint32_t default_mclk; 164 uint32_t default_sclk; 165 uint32_t default_dispclk; 166 uint32_t dp_extclk; 167 }; 168 169 /* 170 * Power management 171 */ 172 int radeon_pm_init(struct radeon_device *rdev); 173 void radeon_pm_fini(struct radeon_device *rdev); 174 void radeon_pm_compute_clocks(struct radeon_device *rdev); 175 void radeon_pm_suspend(struct radeon_device *rdev); 176 void radeon_pm_resume(struct radeon_device *rdev); 177 void radeon_combios_get_power_modes(struct radeon_device *rdev); 178 void radeon_atombios_get_power_modes(struct radeon_device *rdev); 179 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 level); 180 void rs690_pm_info(struct radeon_device *rdev); 181 extern u32 rv6xx_get_temp(struct radeon_device *rdev); 182 extern u32 rv770_get_temp(struct radeon_device *rdev); 183 extern u32 evergreen_get_temp(struct radeon_device *rdev); 184 185 /* 186 * Fences. 187 */ 188 struct radeon_fence_driver { 189 uint32_t scratch_reg; 190 atomic_t seq; 191 uint32_t last_seq; 192 unsigned long last_jiffies; 193 unsigned long last_timeout; 194 wait_queue_head_t queue; 195 rwlock_t lock; 196 struct list_head created; 197 struct list_head emited; 198 struct list_head signaled; 199 bool initialized; 200 }; 201 202 struct radeon_fence { 203 struct radeon_device *rdev; 204 struct kref kref; 205 struct list_head list; 206 /* protected by radeon_fence.lock */ 207 uint32_t seq; 208 bool emited; 209 bool signaled; 210 }; 211 212 int radeon_fence_driver_init(struct radeon_device *rdev); 213 void radeon_fence_driver_fini(struct radeon_device *rdev); 214 int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence); 215 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence); 216 void radeon_fence_process(struct radeon_device *rdev); 217 bool radeon_fence_signaled(struct radeon_fence *fence); 218 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); 219 int radeon_fence_wait_next(struct radeon_device *rdev); 220 int radeon_fence_wait_last(struct radeon_device *rdev); 221 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); 222 void radeon_fence_unref(struct radeon_fence **fence); 223 224 /* 225 * Tiling registers 226 */ 227 struct radeon_surface_reg { 228 struct radeon_bo *bo; 229 }; 230 231 #define RADEON_GEM_MAX_SURFACES 8 232 233 /* 234 * TTM. 235 */ 236 struct radeon_mman { 237 struct ttm_bo_global_ref bo_global_ref; 238 struct drm_global_reference mem_global_ref; 239 struct ttm_bo_device bdev; 240 bool mem_global_referenced; 241 bool initialized; 242 }; 243 244 struct radeon_bo { 245 /* Protected by gem.mutex */ 246 struct list_head list; 247 /* Protected by tbo.reserved */ 248 u32 placements[3]; 249 struct ttm_placement placement; 250 struct ttm_buffer_object tbo; 251 struct ttm_bo_kmap_obj kmap; 252 unsigned pin_count; 253 void *kptr; 254 u32 tiling_flags; 255 u32 pitch; 256 int surface_reg; 257 /* Constant after initialization */ 258 struct radeon_device *rdev; 259 struct drm_gem_object *gobj; 260 }; 261 262 struct radeon_bo_list { 263 struct list_head list; 264 struct radeon_bo *bo; 265 uint64_t gpu_offset; 266 unsigned rdomain; 267 unsigned wdomain; 268 u32 tiling_flags; 269 bool reserved; 270 }; 271 272 /* 273 * GEM objects. 274 */ 275 struct radeon_gem { 276 struct mutex mutex; 277 struct list_head objects; 278 }; 279 280 int radeon_gem_init(struct radeon_device *rdev); 281 void radeon_gem_fini(struct radeon_device *rdev); 282 int radeon_gem_object_create(struct radeon_device *rdev, int size, 283 int alignment, int initial_domain, 284 bool discardable, bool kernel, 285 struct drm_gem_object **obj); 286 int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain, 287 uint64_t *gpu_addr); 288 void radeon_gem_object_unpin(struct drm_gem_object *obj); 289 290 291 /* 292 * GART structures, functions & helpers 293 */ 294 struct radeon_mc; 295 296 struct radeon_gart_table_ram { 297 volatile uint32_t *ptr; 298 }; 299 300 struct radeon_gart_table_vram { 301 struct radeon_bo *robj; 302 volatile uint32_t *ptr; 303 }; 304 305 union radeon_gart_table { 306 struct radeon_gart_table_ram ram; 307 struct radeon_gart_table_vram vram; 308 }; 309 310 #define RADEON_GPU_PAGE_SIZE 4096 311 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) 312 313 struct radeon_gart { 314 dma_addr_t table_addr; 315 unsigned num_gpu_pages; 316 unsigned num_cpu_pages; 317 unsigned table_size; 318 union radeon_gart_table table; 319 struct page **pages; 320 dma_addr_t *pages_addr; 321 bool ready; 322 }; 323 324 int radeon_gart_table_ram_alloc(struct radeon_device *rdev); 325 void radeon_gart_table_ram_free(struct radeon_device *rdev); 326 int radeon_gart_table_vram_alloc(struct radeon_device *rdev); 327 void radeon_gart_table_vram_free(struct radeon_device *rdev); 328 int radeon_gart_init(struct radeon_device *rdev); 329 void radeon_gart_fini(struct radeon_device *rdev); 330 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, 331 int pages); 332 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, 333 int pages, struct page **pagelist); 334 335 336 /* 337 * GPU MC structures, functions & helpers 338 */ 339 struct radeon_mc { 340 resource_size_t aper_size; 341 resource_size_t aper_base; 342 resource_size_t agp_base; 343 /* for some chips with <= 32MB we need to lie 344 * about vram size near mc fb location */ 345 u64 mc_vram_size; 346 u64 visible_vram_size; 347 u64 gtt_size; 348 u64 gtt_start; 349 u64 gtt_end; 350 u64 vram_start; 351 u64 vram_end; 352 unsigned vram_width; 353 u64 real_vram_size; 354 int vram_mtrr; 355 bool vram_is_ddr; 356 bool igp_sideport_enabled; 357 u64 gtt_base_align; 358 }; 359 360 bool radeon_combios_sideport_present(struct radeon_device *rdev); 361 bool radeon_atombios_sideport_present(struct radeon_device *rdev); 362 363 /* 364 * GPU scratch registers structures, functions & helpers 365 */ 366 struct radeon_scratch { 367 unsigned num_reg; 368 bool free[32]; 369 uint32_t reg[32]; 370 }; 371 372 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); 373 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); 374 375 376 /* 377 * IRQS. 378 */ 379 struct radeon_irq { 380 bool installed; 381 bool sw_int; 382 /* FIXME: use a define max crtc rather than hardcode it */ 383 bool crtc_vblank_int[6]; 384 wait_queue_head_t vblank_queue; 385 /* FIXME: use defines for max hpd/dacs */ 386 bool hpd[6]; 387 bool gui_idle; 388 bool gui_idle_acked; 389 wait_queue_head_t idle_queue; 390 /* FIXME: use defines for max HDMI blocks */ 391 bool hdmi[2]; 392 spinlock_t sw_lock; 393 int sw_refcount; 394 }; 395 396 int radeon_irq_kms_init(struct radeon_device *rdev); 397 void radeon_irq_kms_fini(struct radeon_device *rdev); 398 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev); 399 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev); 400 401 /* 402 * CP & ring. 403 */ 404 struct radeon_ib { 405 struct list_head list; 406 unsigned idx; 407 uint64_t gpu_addr; 408 struct radeon_fence *fence; 409 uint32_t *ptr; 410 uint32_t length_dw; 411 bool free; 412 }; 413 414 /* 415 * locking - 416 * mutex protects scheduled_ibs, ready, alloc_bm 417 */ 418 struct radeon_ib_pool { 419 struct mutex mutex; 420 struct radeon_bo *robj; 421 struct list_head bogus_ib; 422 struct radeon_ib ibs[RADEON_IB_POOL_SIZE]; 423 bool ready; 424 unsigned head_id; 425 }; 426 427 struct radeon_cp { 428 struct radeon_bo *ring_obj; 429 volatile uint32_t *ring; 430 unsigned rptr; 431 unsigned wptr; 432 unsigned wptr_old; 433 unsigned ring_size; 434 unsigned ring_free_dw; 435 int count_dw; 436 uint64_t gpu_addr; 437 uint32_t align_mask; 438 uint32_t ptr_mask; 439 struct mutex mutex; 440 bool ready; 441 }; 442 443 /* 444 * R6xx+ IH ring 445 */ 446 struct r600_ih { 447 struct radeon_bo *ring_obj; 448 volatile uint32_t *ring; 449 unsigned rptr; 450 unsigned wptr; 451 unsigned wptr_old; 452 unsigned ring_size; 453 uint64_t gpu_addr; 454 uint32_t ptr_mask; 455 spinlock_t lock; 456 bool enabled; 457 }; 458 459 struct r600_blit { 460 struct mutex mutex; 461 struct radeon_bo *shader_obj; 462 u64 shader_gpu_addr; 463 u32 vs_offset, ps_offset; 464 u32 state_offset; 465 u32 state_len; 466 u32 vb_used, vb_total; 467 struct radeon_ib *vb_ib; 468 }; 469 470 int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib); 471 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib); 472 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib); 473 int radeon_ib_pool_init(struct radeon_device *rdev); 474 void radeon_ib_pool_fini(struct radeon_device *rdev); 475 int radeon_ib_test(struct radeon_device *rdev); 476 extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib); 477 /* Ring access between begin & end cannot sleep */ 478 void radeon_ring_free_size(struct radeon_device *rdev); 479 int radeon_ring_alloc(struct radeon_device *rdev, unsigned ndw); 480 int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw); 481 void radeon_ring_commit(struct radeon_device *rdev); 482 void radeon_ring_unlock_commit(struct radeon_device *rdev); 483 void radeon_ring_unlock_undo(struct radeon_device *rdev); 484 int radeon_ring_test(struct radeon_device *rdev); 485 int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size); 486 void radeon_ring_fini(struct radeon_device *rdev); 487 488 489 /* 490 * CS. 491 */ 492 struct radeon_cs_reloc { 493 struct drm_gem_object *gobj; 494 struct radeon_bo *robj; 495 struct radeon_bo_list lobj; 496 uint32_t handle; 497 uint32_t flags; 498 }; 499 500 struct radeon_cs_chunk { 501 uint32_t chunk_id; 502 uint32_t length_dw; 503 int kpage_idx[2]; 504 uint32_t *kpage[2]; 505 uint32_t *kdata; 506 void __user *user_ptr; 507 int last_copied_page; 508 int last_page_index; 509 }; 510 511 struct radeon_cs_parser { 512 struct device *dev; 513 struct radeon_device *rdev; 514 struct drm_file *filp; 515 /* chunks */ 516 unsigned nchunks; 517 struct radeon_cs_chunk *chunks; 518 uint64_t *chunks_array; 519 /* IB */ 520 unsigned idx; 521 /* relocations */ 522 unsigned nrelocs; 523 struct radeon_cs_reloc *relocs; 524 struct radeon_cs_reloc **relocs_ptr; 525 struct list_head validated; 526 /* indices of various chunks */ 527 int chunk_ib_idx; 528 int chunk_relocs_idx; 529 struct radeon_ib *ib; 530 void *track; 531 unsigned family; 532 int parser_error; 533 }; 534 535 extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx); 536 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p); 537 538 539 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) 540 { 541 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; 542 u32 pg_idx, pg_offset; 543 u32 idx_value = 0; 544 int new_page; 545 546 pg_idx = (idx * 4) / PAGE_SIZE; 547 pg_offset = (idx * 4) % PAGE_SIZE; 548 549 if (ibc->kpage_idx[0] == pg_idx) 550 return ibc->kpage[0][pg_offset/4]; 551 if (ibc->kpage_idx[1] == pg_idx) 552 return ibc->kpage[1][pg_offset/4]; 553 554 new_page = radeon_cs_update_pages(p, pg_idx); 555 if (new_page < 0) { 556 p->parser_error = new_page; 557 return 0; 558 } 559 560 idx_value = ibc->kpage[new_page][pg_offset/4]; 561 return idx_value; 562 } 563 564 struct radeon_cs_packet { 565 unsigned idx; 566 unsigned type; 567 unsigned reg; 568 unsigned opcode; 569 int count; 570 unsigned one_reg_wr; 571 }; 572 573 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, 574 struct radeon_cs_packet *pkt, 575 unsigned idx, unsigned reg); 576 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, 577 struct radeon_cs_packet *pkt); 578 579 580 /* 581 * AGP 582 */ 583 int radeon_agp_init(struct radeon_device *rdev); 584 void radeon_agp_resume(struct radeon_device *rdev); 585 void radeon_agp_suspend(struct radeon_device *rdev); 586 void radeon_agp_fini(struct radeon_device *rdev); 587 588 589 /* 590 * Writeback 591 */ 592 struct radeon_wb { 593 struct radeon_bo *wb_obj; 594 volatile uint32_t *wb; 595 uint64_t gpu_addr; 596 }; 597 598 /** 599 * struct radeon_pm - power management datas 600 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) 601 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) 602 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) 603 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) 604 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) 605 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) 606 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) 607 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) 608 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) 609 * @sclk: GPU clock Mhz (core bandwith depends of this clock) 610 * @needed_bandwidth: current bandwidth needs 611 * 612 * It keeps track of various data needed to take powermanagement decision. 613 * Bandwith need is used to determine minimun clock of the GPU and memory. 614 * Equation between gpu/memory clock and available bandwidth is hw dependent 615 * (type of memory, bus size, efficiency, ...) 616 */ 617 618 enum radeon_pm_method { 619 PM_METHOD_PROFILE, 620 PM_METHOD_DYNPM, 621 }; 622 623 enum radeon_dynpm_state { 624 DYNPM_STATE_DISABLED, 625 DYNPM_STATE_MINIMUM, 626 DYNPM_STATE_PAUSED, 627 DYNPM_STATE_ACTIVE, 628 DYNPM_STATE_SUSPENDED, 629 }; 630 enum radeon_dynpm_action { 631 DYNPM_ACTION_NONE, 632 DYNPM_ACTION_MINIMUM, 633 DYNPM_ACTION_DOWNCLOCK, 634 DYNPM_ACTION_UPCLOCK, 635 DYNPM_ACTION_DEFAULT 636 }; 637 638 enum radeon_voltage_type { 639 VOLTAGE_NONE = 0, 640 VOLTAGE_GPIO, 641 VOLTAGE_VDDC, 642 VOLTAGE_SW 643 }; 644 645 enum radeon_pm_state_type { 646 POWER_STATE_TYPE_DEFAULT, 647 POWER_STATE_TYPE_POWERSAVE, 648 POWER_STATE_TYPE_BATTERY, 649 POWER_STATE_TYPE_BALANCED, 650 POWER_STATE_TYPE_PERFORMANCE, 651 }; 652 653 enum radeon_pm_profile_type { 654 PM_PROFILE_DEFAULT, 655 PM_PROFILE_AUTO, 656 PM_PROFILE_LOW, 657 PM_PROFILE_MID, 658 PM_PROFILE_HIGH, 659 }; 660 661 #define PM_PROFILE_DEFAULT_IDX 0 662 #define PM_PROFILE_LOW_SH_IDX 1 663 #define PM_PROFILE_MID_SH_IDX 2 664 #define PM_PROFILE_HIGH_SH_IDX 3 665 #define PM_PROFILE_LOW_MH_IDX 4 666 #define PM_PROFILE_MID_MH_IDX 5 667 #define PM_PROFILE_HIGH_MH_IDX 6 668 #define PM_PROFILE_MAX 7 669 670 struct radeon_pm_profile { 671 int dpms_off_ps_idx; 672 int dpms_on_ps_idx; 673 int dpms_off_cm_idx; 674 int dpms_on_cm_idx; 675 }; 676 677 enum radeon_int_thermal_type { 678 THERMAL_TYPE_NONE, 679 THERMAL_TYPE_RV6XX, 680 THERMAL_TYPE_RV770, 681 THERMAL_TYPE_EVERGREEN, 682 }; 683 684 struct radeon_voltage { 685 enum radeon_voltage_type type; 686 /* gpio voltage */ 687 struct radeon_gpio_rec gpio; 688 u32 delay; /* delay in usec from voltage drop to sclk change */ 689 bool active_high; /* voltage drop is active when bit is high */ 690 /* VDDC voltage */ 691 u8 vddc_id; /* index into vddc voltage table */ 692 u8 vddci_id; /* index into vddci voltage table */ 693 bool vddci_enabled; 694 /* r6xx+ sw */ 695 u32 voltage; 696 }; 697 698 /* clock mode flags */ 699 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) 700 701 struct radeon_pm_clock_info { 702 /* memory clock */ 703 u32 mclk; 704 /* engine clock */ 705 u32 sclk; 706 /* voltage info */ 707 struct radeon_voltage voltage; 708 /* standardized clock flags */ 709 u32 flags; 710 }; 711 712 /* state flags */ 713 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) 714 715 struct radeon_power_state { 716 enum radeon_pm_state_type type; 717 /* XXX: use a define for num clock modes */ 718 struct radeon_pm_clock_info clock_info[8]; 719 /* number of valid clock modes in this power state */ 720 int num_clock_modes; 721 struct radeon_pm_clock_info *default_clock_mode; 722 /* standardized state flags */ 723 u32 flags; 724 u32 misc; /* vbios specific flags */ 725 u32 misc2; /* vbios specific flags */ 726 int pcie_lanes; /* pcie lanes */ 727 }; 728 729 /* 730 * Some modes are overclocked by very low value, accept them 731 */ 732 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ 733 734 struct radeon_pm { 735 struct mutex mutex; 736 u32 active_crtcs; 737 int active_crtc_count; 738 int req_vblank; 739 bool vblank_sync; 740 bool gui_idle; 741 fixed20_12 max_bandwidth; 742 fixed20_12 igp_sideport_mclk; 743 fixed20_12 igp_system_mclk; 744 fixed20_12 igp_ht_link_clk; 745 fixed20_12 igp_ht_link_width; 746 fixed20_12 k8_bandwidth; 747 fixed20_12 sideport_bandwidth; 748 fixed20_12 ht_bandwidth; 749 fixed20_12 core_bandwidth; 750 fixed20_12 sclk; 751 fixed20_12 mclk; 752 fixed20_12 needed_bandwidth; 753 /* XXX: use a define for num power modes */ 754 struct radeon_power_state power_state[8]; 755 /* number of valid power states */ 756 int num_power_states; 757 int current_power_state_index; 758 int current_clock_mode_index; 759 int requested_power_state_index; 760 int requested_clock_mode_index; 761 int default_power_state_index; 762 u32 current_sclk; 763 u32 current_mclk; 764 u32 current_vddc; 765 struct radeon_i2c_chan *i2c_bus; 766 /* selected pm method */ 767 enum radeon_pm_method pm_method; 768 /* dynpm power management */ 769 struct delayed_work dynpm_idle_work; 770 enum radeon_dynpm_state dynpm_state; 771 enum radeon_dynpm_action dynpm_planned_action; 772 unsigned long dynpm_action_timeout; 773 bool dynpm_can_upclock; 774 bool dynpm_can_downclock; 775 /* profile-based power management */ 776 enum radeon_pm_profile_type profile; 777 int profile_index; 778 struct radeon_pm_profile profiles[PM_PROFILE_MAX]; 779 /* internal thermal controller on rv6xx+ */ 780 enum radeon_int_thermal_type int_thermal_type; 781 struct device *int_hwmon_dev; 782 }; 783 784 785 /* 786 * Benchmarking 787 */ 788 void radeon_benchmark(struct radeon_device *rdev); 789 790 791 /* 792 * Testing 793 */ 794 void radeon_test_moves(struct radeon_device *rdev); 795 796 797 /* 798 * Debugfs 799 */ 800 int radeon_debugfs_add_files(struct radeon_device *rdev, 801 struct drm_info_list *files, 802 unsigned nfiles); 803 int radeon_debugfs_fence_init(struct radeon_device *rdev); 804 805 806 /* 807 * ASIC specific functions. 808 */ 809 struct radeon_asic { 810 int (*init)(struct radeon_device *rdev); 811 void (*fini)(struct radeon_device *rdev); 812 int (*resume)(struct radeon_device *rdev); 813 int (*suspend)(struct radeon_device *rdev); 814 void (*vga_set_state)(struct radeon_device *rdev, bool state); 815 bool (*gpu_is_lockup)(struct radeon_device *rdev); 816 int (*asic_reset)(struct radeon_device *rdev); 817 void (*gart_tlb_flush)(struct radeon_device *rdev); 818 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr); 819 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size); 820 void (*cp_fini)(struct radeon_device *rdev); 821 void (*cp_disable)(struct radeon_device *rdev); 822 void (*cp_commit)(struct radeon_device *rdev); 823 void (*ring_start)(struct radeon_device *rdev); 824 int (*ring_test)(struct radeon_device *rdev); 825 void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); 826 int (*irq_set)(struct radeon_device *rdev); 827 int (*irq_process)(struct radeon_device *rdev); 828 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); 829 void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence); 830 int (*cs_parse)(struct radeon_cs_parser *p); 831 int (*copy_blit)(struct radeon_device *rdev, 832 uint64_t src_offset, 833 uint64_t dst_offset, 834 unsigned num_pages, 835 struct radeon_fence *fence); 836 int (*copy_dma)(struct radeon_device *rdev, 837 uint64_t src_offset, 838 uint64_t dst_offset, 839 unsigned num_pages, 840 struct radeon_fence *fence); 841 int (*copy)(struct radeon_device *rdev, 842 uint64_t src_offset, 843 uint64_t dst_offset, 844 unsigned num_pages, 845 struct radeon_fence *fence); 846 uint32_t (*get_engine_clock)(struct radeon_device *rdev); 847 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); 848 uint32_t (*get_memory_clock)(struct radeon_device *rdev); 849 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); 850 int (*get_pcie_lanes)(struct radeon_device *rdev); 851 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); 852 void (*set_clock_gating)(struct radeon_device *rdev, int enable); 853 int (*set_surface_reg)(struct radeon_device *rdev, int reg, 854 uint32_t tiling_flags, uint32_t pitch, 855 uint32_t offset, uint32_t obj_size); 856 void (*clear_surface_reg)(struct radeon_device *rdev, int reg); 857 void (*bandwidth_update)(struct radeon_device *rdev); 858 void (*hpd_init)(struct radeon_device *rdev); 859 void (*hpd_fini)(struct radeon_device *rdev); 860 bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 861 void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 862 /* ioctl hw specific callback. Some hw might want to perform special 863 * operation on specific ioctl. For instance on wait idle some hw 864 * might want to perform and HDP flush through MMIO as it seems that 865 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed 866 * through ring. 867 */ 868 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo); 869 bool (*gui_idle)(struct radeon_device *rdev); 870 /* power management */ 871 void (*pm_misc)(struct radeon_device *rdev); 872 void (*pm_prepare)(struct radeon_device *rdev); 873 void (*pm_finish)(struct radeon_device *rdev); 874 void (*pm_init_profile)(struct radeon_device *rdev); 875 void (*pm_get_dynpm_state)(struct radeon_device *rdev); 876 }; 877 878 /* 879 * Asic structures 880 */ 881 struct r100_gpu_lockup { 882 unsigned long last_jiffies; 883 u32 last_cp_rptr; 884 }; 885 886 struct r100_asic { 887 const unsigned *reg_safe_bm; 888 unsigned reg_safe_bm_size; 889 u32 hdp_cntl; 890 struct r100_gpu_lockup lockup; 891 }; 892 893 struct r300_asic { 894 const unsigned *reg_safe_bm; 895 unsigned reg_safe_bm_size; 896 u32 resync_scratch; 897 u32 hdp_cntl; 898 struct r100_gpu_lockup lockup; 899 }; 900 901 struct r600_asic { 902 unsigned max_pipes; 903 unsigned max_tile_pipes; 904 unsigned max_simds; 905 unsigned max_backends; 906 unsigned max_gprs; 907 unsigned max_threads; 908 unsigned max_stack_entries; 909 unsigned max_hw_contexts; 910 unsigned max_gs_threads; 911 unsigned sx_max_export_size; 912 unsigned sx_max_export_pos_size; 913 unsigned sx_max_export_smx_size; 914 unsigned sq_num_cf_insts; 915 unsigned tiling_nbanks; 916 unsigned tiling_npipes; 917 unsigned tiling_group_size; 918 unsigned tile_config; 919 struct r100_gpu_lockup lockup; 920 }; 921 922 struct rv770_asic { 923 unsigned max_pipes; 924 unsigned max_tile_pipes; 925 unsigned max_simds; 926 unsigned max_backends; 927 unsigned max_gprs; 928 unsigned max_threads; 929 unsigned max_stack_entries; 930 unsigned max_hw_contexts; 931 unsigned max_gs_threads; 932 unsigned sx_max_export_size; 933 unsigned sx_max_export_pos_size; 934 unsigned sx_max_export_smx_size; 935 unsigned sq_num_cf_insts; 936 unsigned sx_num_of_sets; 937 unsigned sc_prim_fifo_size; 938 unsigned sc_hiz_tile_fifo_size; 939 unsigned sc_earlyz_tile_fifo_fize; 940 unsigned tiling_nbanks; 941 unsigned tiling_npipes; 942 unsigned tiling_group_size; 943 unsigned tile_config; 944 struct r100_gpu_lockup lockup; 945 }; 946 947 struct evergreen_asic { 948 unsigned num_ses; 949 unsigned max_pipes; 950 unsigned max_tile_pipes; 951 unsigned max_simds; 952 unsigned max_backends; 953 unsigned max_gprs; 954 unsigned max_threads; 955 unsigned max_stack_entries; 956 unsigned max_hw_contexts; 957 unsigned max_gs_threads; 958 unsigned sx_max_export_size; 959 unsigned sx_max_export_pos_size; 960 unsigned sx_max_export_smx_size; 961 unsigned sq_num_cf_insts; 962 unsigned sx_num_of_sets; 963 unsigned sc_prim_fifo_size; 964 unsigned sc_hiz_tile_fifo_size; 965 unsigned sc_earlyz_tile_fifo_size; 966 unsigned tiling_nbanks; 967 unsigned tiling_npipes; 968 unsigned tiling_group_size; 969 unsigned tile_config; 970 }; 971 972 union radeon_asic_config { 973 struct r300_asic r300; 974 struct r100_asic r100; 975 struct r600_asic r600; 976 struct rv770_asic rv770; 977 struct evergreen_asic evergreen; 978 }; 979 980 /* 981 * asic initizalization from radeon_asic.c 982 */ 983 void radeon_agp_disable(struct radeon_device *rdev); 984 int radeon_asic_init(struct radeon_device *rdev); 985 986 987 /* 988 * IOCTL. 989 */ 990 int radeon_gem_info_ioctl(struct drm_device *dev, void *data, 991 struct drm_file *filp); 992 int radeon_gem_create_ioctl(struct drm_device *dev, void *data, 993 struct drm_file *filp); 994 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, 995 struct drm_file *file_priv); 996 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, 997 struct drm_file *file_priv); 998 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, 999 struct drm_file *file_priv); 1000 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, 1001 struct drm_file *file_priv); 1002 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, 1003 struct drm_file *filp); 1004 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, 1005 struct drm_file *filp); 1006 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, 1007 struct drm_file *filp); 1008 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 1009 struct drm_file *filp); 1010 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1011 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, 1012 struct drm_file *filp); 1013 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, 1014 struct drm_file *filp); 1015 1016 1017 /* 1018 * Core structure, functions and helpers. 1019 */ 1020 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); 1021 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); 1022 1023 struct radeon_device { 1024 struct device *dev; 1025 struct drm_device *ddev; 1026 struct pci_dev *pdev; 1027 /* ASIC */ 1028 union radeon_asic_config config; 1029 enum radeon_family family; 1030 unsigned long flags; 1031 int usec_timeout; 1032 enum radeon_pll_errata pll_errata; 1033 int num_gb_pipes; 1034 int num_z_pipes; 1035 int disp_priority; 1036 /* BIOS */ 1037 uint8_t *bios; 1038 bool is_atom_bios; 1039 uint16_t bios_header_start; 1040 struct radeon_bo *stollen_vga_memory; 1041 /* Register mmio */ 1042 resource_size_t rmmio_base; 1043 resource_size_t rmmio_size; 1044 void *rmmio; 1045 radeon_rreg_t mc_rreg; 1046 radeon_wreg_t mc_wreg; 1047 radeon_rreg_t pll_rreg; 1048 radeon_wreg_t pll_wreg; 1049 uint32_t pcie_reg_mask; 1050 radeon_rreg_t pciep_rreg; 1051 radeon_wreg_t pciep_wreg; 1052 /* io port */ 1053 void __iomem *rio_mem; 1054 resource_size_t rio_mem_size; 1055 struct radeon_clock clock; 1056 struct radeon_mc mc; 1057 struct radeon_gart gart; 1058 struct radeon_mode_info mode_info; 1059 struct radeon_scratch scratch; 1060 struct radeon_mman mman; 1061 struct radeon_fence_driver fence_drv; 1062 struct radeon_cp cp; 1063 struct radeon_ib_pool ib_pool; 1064 struct radeon_irq irq; 1065 struct radeon_asic *asic; 1066 struct radeon_gem gem; 1067 struct radeon_pm pm; 1068 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; 1069 struct mutex cs_mutex; 1070 struct radeon_wb wb; 1071 struct radeon_dummy_page dummy_page; 1072 bool gpu_lockup; 1073 bool shutdown; 1074 bool suspend; 1075 bool need_dma32; 1076 bool accel_working; 1077 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; 1078 const struct firmware *me_fw; /* all family ME firmware */ 1079 const struct firmware *pfp_fw; /* r6/700 PFP firmware */ 1080 const struct firmware *rlc_fw; /* r6/700 RLC firmware */ 1081 struct r600_blit r600_blit; 1082 int msi_enabled; /* msi enabled */ 1083 struct r600_ih ih; /* r6/700 interrupt ring */ 1084 struct workqueue_struct *wq; 1085 struct work_struct hotplug_work; 1086 int num_crtc; /* number of crtcs */ 1087 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ 1088 struct mutex vram_mutex; 1089 1090 /* audio stuff */ 1091 bool audio_enabled; 1092 struct timer_list audio_timer; 1093 int audio_channels; 1094 int audio_rate; 1095 int audio_bits_per_sample; 1096 uint8_t audio_status_bits; 1097 uint8_t audio_category_code; 1098 1099 bool powered_down; 1100 struct notifier_block acpi_nb; 1101 /* only one userspace can use Hyperz features at a time */ 1102 struct drm_file *hyperz_filp; 1103 /* i2c buses */ 1104 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; 1105 }; 1106 1107 int radeon_device_init(struct radeon_device *rdev, 1108 struct drm_device *ddev, 1109 struct pci_dev *pdev, 1110 uint32_t flags); 1111 void radeon_device_fini(struct radeon_device *rdev); 1112 int radeon_gpu_wait_for_idle(struct radeon_device *rdev); 1113 1114 /* r600 blit */ 1115 int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes); 1116 void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence); 1117 void r600_kms_blit_copy(struct radeon_device *rdev, 1118 u64 src_gpu_addr, u64 dst_gpu_addr, 1119 int size_bytes); 1120 1121 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg) 1122 { 1123 if (reg < rdev->rmmio_size) 1124 return readl(((void __iomem *)rdev->rmmio) + reg); 1125 else { 1126 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); 1127 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); 1128 } 1129 } 1130 1131 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 1132 { 1133 if (reg < rdev->rmmio_size) 1134 writel(v, ((void __iomem *)rdev->rmmio) + reg); 1135 else { 1136 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); 1137 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); 1138 } 1139 } 1140 1141 static inline u32 r100_io_rreg(struct radeon_device *rdev, u32 reg) 1142 { 1143 if (reg < rdev->rio_mem_size) 1144 return ioread32(rdev->rio_mem + reg); 1145 else { 1146 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX); 1147 return ioread32(rdev->rio_mem + RADEON_MM_DATA); 1148 } 1149 } 1150 1151 static inline void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v) 1152 { 1153 if (reg < rdev->rio_mem_size) 1154 iowrite32(v, rdev->rio_mem + reg); 1155 else { 1156 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX); 1157 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA); 1158 } 1159 } 1160 1161 /* 1162 * Cast helper 1163 */ 1164 #define to_radeon_fence(p) ((struct radeon_fence *)(p)) 1165 1166 /* 1167 * Registers read & write functions. 1168 */ 1169 #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg)) 1170 #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg)) 1171 #define RREG32(reg) r100_mm_rreg(rdev, (reg)) 1172 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg))) 1173 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v)) 1174 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1175 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1176 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) 1177 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) 1178 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) 1179 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) 1180 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) 1181 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) 1182 #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg)) 1183 #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) 1184 #define WREG32_P(reg, val, mask) \ 1185 do { \ 1186 uint32_t tmp_ = RREG32(reg); \ 1187 tmp_ &= (mask); \ 1188 tmp_ |= ((val) & ~(mask)); \ 1189 WREG32(reg, tmp_); \ 1190 } while (0) 1191 #define WREG32_PLL_P(reg, val, mask) \ 1192 do { \ 1193 uint32_t tmp_ = RREG32_PLL(reg); \ 1194 tmp_ &= (mask); \ 1195 tmp_ |= ((val) & ~(mask)); \ 1196 WREG32_PLL(reg, tmp_); \ 1197 } while (0) 1198 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg))) 1199 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) 1200 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) 1201 1202 /* 1203 * Indirect registers accessor 1204 */ 1205 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) 1206 { 1207 uint32_t r; 1208 1209 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 1210 r = RREG32(RADEON_PCIE_DATA); 1211 return r; 1212 } 1213 1214 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 1215 { 1216 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 1217 WREG32(RADEON_PCIE_DATA, (v)); 1218 } 1219 1220 void r100_pll_errata_after_index(struct radeon_device *rdev); 1221 1222 1223 /* 1224 * ASICs helpers. 1225 */ 1226 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ 1227 (rdev->pdev->device == 0x5969)) 1228 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ 1229 (rdev->family == CHIP_RV200) || \ 1230 (rdev->family == CHIP_RS100) || \ 1231 (rdev->family == CHIP_RS200) || \ 1232 (rdev->family == CHIP_RV250) || \ 1233 (rdev->family == CHIP_RV280) || \ 1234 (rdev->family == CHIP_RS300)) 1235 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ 1236 (rdev->family == CHIP_RV350) || \ 1237 (rdev->family == CHIP_R350) || \ 1238 (rdev->family == CHIP_RV380) || \ 1239 (rdev->family == CHIP_R420) || \ 1240 (rdev->family == CHIP_R423) || \ 1241 (rdev->family == CHIP_RV410) || \ 1242 (rdev->family == CHIP_RS400) || \ 1243 (rdev->family == CHIP_RS480)) 1244 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) 1245 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) 1246 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) 1247 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) 1248 1249 /* 1250 * BIOS helpers. 1251 */ 1252 #define RBIOS8(i) (rdev->bios[i]) 1253 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1254 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1255 1256 int radeon_combios_init(struct radeon_device *rdev); 1257 void radeon_combios_fini(struct radeon_device *rdev); 1258 int radeon_atombios_init(struct radeon_device *rdev); 1259 void radeon_atombios_fini(struct radeon_device *rdev); 1260 1261 1262 /* 1263 * RING helpers. 1264 */ 1265 static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v) 1266 { 1267 #if DRM_DEBUG_CODE 1268 if (rdev->cp.count_dw <= 0) { 1269 DRM_ERROR("radeon: writting more dword to ring than expected !\n"); 1270 } 1271 #endif 1272 rdev->cp.ring[rdev->cp.wptr++] = v; 1273 rdev->cp.wptr &= rdev->cp.ptr_mask; 1274 rdev->cp.count_dw--; 1275 rdev->cp.ring_free_dw--; 1276 } 1277 1278 1279 /* 1280 * ASICs macro. 1281 */ 1282 #define radeon_init(rdev) (rdev)->asic->init((rdev)) 1283 #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) 1284 #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) 1285 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) 1286 #define radeon_cs_parse(p) rdev->asic->cs_parse((p)) 1287 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) 1288 #define radeon_gpu_is_lockup(rdev) (rdev)->asic->gpu_is_lockup((rdev)) 1289 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) 1290 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev)) 1291 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p)) 1292 #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev)) 1293 #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev)) 1294 #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev)) 1295 #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib)) 1296 #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev)) 1297 #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev)) 1298 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc)) 1299 #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence)) 1300 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f)) 1301 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f)) 1302 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f)) 1303 #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev)) 1304 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e)) 1305 #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev)) 1306 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e)) 1307 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev)) 1308 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l)) 1309 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e)) 1310 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s))) 1311 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r))) 1312 #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev)) 1313 #define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev)) 1314 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev)) 1315 #define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd)) 1316 #define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd)) 1317 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) 1318 #define radeon_pm_misc(rdev) (rdev)->asic->pm_misc((rdev)) 1319 #define radeon_pm_prepare(rdev) (rdev)->asic->pm_prepare((rdev)) 1320 #define radeon_pm_finish(rdev) (rdev)->asic->pm_finish((rdev)) 1321 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm_init_profile((rdev)) 1322 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm_get_dynpm_state((rdev)) 1323 1324 /* Common functions */ 1325 /* AGP */ 1326 extern int radeon_gpu_reset(struct radeon_device *rdev); 1327 extern void radeon_agp_disable(struct radeon_device *rdev); 1328 extern int radeon_gart_table_vram_pin(struct radeon_device *rdev); 1329 extern void radeon_gart_restore(struct radeon_device *rdev); 1330 extern int radeon_modeset_init(struct radeon_device *rdev); 1331 extern void radeon_modeset_fini(struct radeon_device *rdev); 1332 extern bool radeon_card_posted(struct radeon_device *rdev); 1333 extern void radeon_update_bandwidth_info(struct radeon_device *rdev); 1334 extern void radeon_update_display_priority(struct radeon_device *rdev); 1335 extern bool radeon_boot_test_post_card(struct radeon_device *rdev); 1336 extern int radeon_clocks_init(struct radeon_device *rdev); 1337 extern void radeon_clocks_fini(struct radeon_device *rdev); 1338 extern void radeon_scratch_init(struct radeon_device *rdev); 1339 extern void radeon_surface_init(struct radeon_device *rdev); 1340 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); 1341 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); 1342 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); 1343 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); 1344 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); 1345 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); 1346 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); 1347 extern int radeon_resume_kms(struct drm_device *dev); 1348 extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state); 1349 1350 /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */ 1351 extern void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_cp *cp); 1352 extern bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_cp *cp); 1353 1354 /* rv200,rv250,rv280 */ 1355 extern void r200_set_safe_registers(struct radeon_device *rdev); 1356 1357 /* r300,r350,rv350,rv370,rv380 */ 1358 extern void r300_set_reg_safe(struct radeon_device *rdev); 1359 extern void r300_mc_program(struct radeon_device *rdev); 1360 extern void r300_mc_init(struct radeon_device *rdev); 1361 extern void r300_clock_startup(struct radeon_device *rdev); 1362 extern int r300_mc_wait_for_idle(struct radeon_device *rdev); 1363 extern int rv370_pcie_gart_init(struct radeon_device *rdev); 1364 extern void rv370_pcie_gart_fini(struct radeon_device *rdev); 1365 extern int rv370_pcie_gart_enable(struct radeon_device *rdev); 1366 extern void rv370_pcie_gart_disable(struct radeon_device *rdev); 1367 1368 /* r420,r423,rv410 */ 1369 extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); 1370 extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); 1371 extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev); 1372 extern void r420_pipes_init(struct radeon_device *rdev); 1373 1374 /* rv515 */ 1375 struct rv515_mc_save { 1376 u32 d1vga_control; 1377 u32 d2vga_control; 1378 u32 vga_render_control; 1379 u32 vga_hdp_control; 1380 u32 d1crtc_control; 1381 u32 d2crtc_control; 1382 }; 1383 extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev); 1384 extern void rv515_vga_render_disable(struct radeon_device *rdev); 1385 extern void rv515_set_safe_registers(struct radeon_device *rdev); 1386 extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save); 1387 extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save); 1388 extern void rv515_clock_startup(struct radeon_device *rdev); 1389 extern void rv515_debugfs(struct radeon_device *rdev); 1390 extern int rv515_suspend(struct radeon_device *rdev); 1391 1392 /* rs400 */ 1393 extern int rs400_gart_init(struct radeon_device *rdev); 1394 extern int rs400_gart_enable(struct radeon_device *rdev); 1395 extern void rs400_gart_adjust_size(struct radeon_device *rdev); 1396 extern void rs400_gart_disable(struct radeon_device *rdev); 1397 extern void rs400_gart_fini(struct radeon_device *rdev); 1398 1399 /* rs600 */ 1400 extern void rs600_set_safe_registers(struct radeon_device *rdev); 1401 extern int rs600_irq_set(struct radeon_device *rdev); 1402 extern void rs600_irq_disable(struct radeon_device *rdev); 1403 1404 /* rs690, rs740 */ 1405 extern void rs690_line_buffer_adjust(struct radeon_device *rdev, 1406 struct drm_display_mode *mode1, 1407 struct drm_display_mode *mode2); 1408 1409 /* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */ 1410 extern void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); 1411 extern bool r600_card_posted(struct radeon_device *rdev); 1412 extern void r600_cp_stop(struct radeon_device *rdev); 1413 extern int r600_cp_start(struct radeon_device *rdev); 1414 extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size); 1415 extern int r600_cp_resume(struct radeon_device *rdev); 1416 extern void r600_cp_fini(struct radeon_device *rdev); 1417 extern int r600_count_pipe_bits(uint32_t val); 1418 extern int r600_mc_wait_for_idle(struct radeon_device *rdev); 1419 extern int r600_pcie_gart_init(struct radeon_device *rdev); 1420 extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); 1421 extern int r600_ib_test(struct radeon_device *rdev); 1422 extern int r600_ring_test(struct radeon_device *rdev); 1423 extern void r600_wb_fini(struct radeon_device *rdev); 1424 extern int r600_wb_enable(struct radeon_device *rdev); 1425 extern void r600_wb_disable(struct radeon_device *rdev); 1426 extern void r600_scratch_init(struct radeon_device *rdev); 1427 extern int r600_blit_init(struct radeon_device *rdev); 1428 extern void r600_blit_fini(struct radeon_device *rdev); 1429 extern int r600_init_microcode(struct radeon_device *rdev); 1430 extern int r600_asic_reset(struct radeon_device *rdev); 1431 /* r600 irq */ 1432 extern int r600_irq_init(struct radeon_device *rdev); 1433 extern void r600_irq_fini(struct radeon_device *rdev); 1434 extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size); 1435 extern int r600_irq_set(struct radeon_device *rdev); 1436 extern void r600_irq_suspend(struct radeon_device *rdev); 1437 extern void r600_disable_interrupts(struct radeon_device *rdev); 1438 extern void r600_rlc_stop(struct radeon_device *rdev); 1439 /* r600 audio */ 1440 extern int r600_audio_init(struct radeon_device *rdev); 1441 extern int r600_audio_tmds_index(struct drm_encoder *encoder); 1442 extern void r600_audio_set_clock(struct drm_encoder *encoder, int clock); 1443 extern int r600_audio_channels(struct radeon_device *rdev); 1444 extern int r600_audio_bits_per_sample(struct radeon_device *rdev); 1445 extern int r600_audio_rate(struct radeon_device *rdev); 1446 extern uint8_t r600_audio_status_bits(struct radeon_device *rdev); 1447 extern uint8_t r600_audio_category_code(struct radeon_device *rdev); 1448 extern void r600_audio_schedule_polling(struct radeon_device *rdev); 1449 extern void r600_audio_enable_polling(struct drm_encoder *encoder); 1450 extern void r600_audio_disable_polling(struct drm_encoder *encoder); 1451 extern void r600_audio_fini(struct radeon_device *rdev); 1452 extern void r600_hdmi_init(struct drm_encoder *encoder); 1453 extern void r600_hdmi_enable(struct drm_encoder *encoder); 1454 extern void r600_hdmi_disable(struct drm_encoder *encoder); 1455 extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); 1456 extern int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder); 1457 extern void r600_hdmi_update_audio_settings(struct drm_encoder *encoder); 1458 1459 extern void r700_cp_stop(struct radeon_device *rdev); 1460 extern void r700_cp_fini(struct radeon_device *rdev); 1461 extern void evergreen_disable_interrupt_state(struct radeon_device *rdev); 1462 extern int evergreen_irq_set(struct radeon_device *rdev); 1463 1464 /* radeon_acpi.c */ 1465 #if defined(CONFIG_ACPI) 1466 extern int radeon_acpi_init(struct radeon_device *rdev); 1467 #else 1468 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; } 1469 #endif 1470 1471 /* evergreen */ 1472 struct evergreen_mc_save { 1473 u32 vga_control[6]; 1474 u32 vga_render_control; 1475 u32 vga_hdp_control; 1476 u32 crtc_control[6]; 1477 }; 1478 1479 #include "radeon_object.h" 1480 1481 #endif 1482