1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __RADEON_H__ 29 #define __RADEON_H__ 30 31 #include "radeon_object.h" 32 33 /* TODO: Here are things that needs to be done : 34 * - surface allocator & initializer : (bit like scratch reg) should 35 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings 36 * related to surface 37 * - WB : write back stuff (do it bit like scratch reg things) 38 * - Vblank : look at Jesse's rework and what we should do 39 * - r600/r700: gart & cp 40 * - cs : clean cs ioctl use bitmap & things like that. 41 * - power management stuff 42 * - Barrier in gart code 43 * - Unmappabled vram ? 44 * - TESTING, TESTING, TESTING 45 */ 46 47 #include <asm/atomic.h> 48 #include <linux/wait.h> 49 #include <linux/list.h> 50 #include <linux/kref.h> 51 52 #include "radeon_mode.h" 53 #include "radeon_reg.h" 54 #include "r300.h" 55 56 /* 57 * Modules parameters. 58 */ 59 extern int radeon_no_wb; 60 extern int radeon_modeset; 61 extern int radeon_dynclks; 62 extern int radeon_r4xx_atom; 63 extern int radeon_agpmode; 64 extern int radeon_vram_limit; 65 extern int radeon_gart_size; 66 extern int radeon_benchmarking; 67 extern int radeon_testing; 68 extern int radeon_connector_table; 69 70 /* 71 * Copy from radeon_drv.h so we don't have to include both and have conflicting 72 * symbol; 73 */ 74 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 75 #define RADEON_IB_POOL_SIZE 16 76 #define RADEON_DEBUGFS_MAX_NUM_FILES 32 77 #define RADEONFB_CONN_LIMIT 4 78 79 enum radeon_family { 80 CHIP_R100, 81 CHIP_RV100, 82 CHIP_RS100, 83 CHIP_RV200, 84 CHIP_RS200, 85 CHIP_R200, 86 CHIP_RV250, 87 CHIP_RS300, 88 CHIP_RV280, 89 CHIP_R300, 90 CHIP_R350, 91 CHIP_RV350, 92 CHIP_RV380, 93 CHIP_R420, 94 CHIP_R423, 95 CHIP_RV410, 96 CHIP_RS400, 97 CHIP_RS480, 98 CHIP_RS600, 99 CHIP_RS690, 100 CHIP_RS740, 101 CHIP_RV515, 102 CHIP_R520, 103 CHIP_RV530, 104 CHIP_RV560, 105 CHIP_RV570, 106 CHIP_R580, 107 CHIP_R600, 108 CHIP_RV610, 109 CHIP_RV630, 110 CHIP_RV620, 111 CHIP_RV635, 112 CHIP_RV670, 113 CHIP_RS780, 114 CHIP_RV770, 115 CHIP_RV730, 116 CHIP_RV710, 117 CHIP_RS880, 118 CHIP_LAST, 119 }; 120 121 enum radeon_chip_flags { 122 RADEON_FAMILY_MASK = 0x0000ffffUL, 123 RADEON_FLAGS_MASK = 0xffff0000UL, 124 RADEON_IS_MOBILITY = 0x00010000UL, 125 RADEON_IS_IGP = 0x00020000UL, 126 RADEON_SINGLE_CRTC = 0x00040000UL, 127 RADEON_IS_AGP = 0x00080000UL, 128 RADEON_HAS_HIERZ = 0x00100000UL, 129 RADEON_IS_PCIE = 0x00200000UL, 130 RADEON_NEW_MEMMAP = 0x00400000UL, 131 RADEON_IS_PCI = 0x00800000UL, 132 RADEON_IS_IGPGART = 0x01000000UL, 133 }; 134 135 136 /* 137 * Errata workarounds. 138 */ 139 enum radeon_pll_errata { 140 CHIP_ERRATA_R300_CG = 0x00000001, 141 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, 142 CHIP_ERRATA_PLL_DELAY = 0x00000004 143 }; 144 145 146 struct radeon_device; 147 148 149 /* 150 * BIOS. 151 */ 152 bool radeon_get_bios(struct radeon_device *rdev); 153 154 /* 155 * Clocks 156 */ 157 158 struct radeon_clock { 159 struct radeon_pll p1pll; 160 struct radeon_pll p2pll; 161 struct radeon_pll spll; 162 struct radeon_pll mpll; 163 /* 10 Khz units */ 164 uint32_t default_mclk; 165 uint32_t default_sclk; 166 }; 167 168 /* 169 * Fences. 170 */ 171 struct radeon_fence_driver { 172 uint32_t scratch_reg; 173 atomic_t seq; 174 uint32_t last_seq; 175 unsigned long count_timeout; 176 wait_queue_head_t queue; 177 rwlock_t lock; 178 struct list_head created; 179 struct list_head emited; 180 struct list_head signaled; 181 }; 182 183 struct radeon_fence { 184 struct radeon_device *rdev; 185 struct kref kref; 186 struct list_head list; 187 /* protected by radeon_fence.lock */ 188 uint32_t seq; 189 unsigned long timeout; 190 bool emited; 191 bool signaled; 192 }; 193 194 int radeon_fence_driver_init(struct radeon_device *rdev); 195 void radeon_fence_driver_fini(struct radeon_device *rdev); 196 int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence); 197 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence); 198 void radeon_fence_process(struct radeon_device *rdev); 199 bool radeon_fence_signaled(struct radeon_fence *fence); 200 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); 201 int radeon_fence_wait_next(struct radeon_device *rdev); 202 int radeon_fence_wait_last(struct radeon_device *rdev); 203 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); 204 void radeon_fence_unref(struct radeon_fence **fence); 205 206 /* 207 * Tiling registers 208 */ 209 struct radeon_surface_reg { 210 struct radeon_object *robj; 211 }; 212 213 #define RADEON_GEM_MAX_SURFACES 8 214 215 /* 216 * Radeon buffer. 217 */ 218 struct radeon_object; 219 220 struct radeon_object_list { 221 struct list_head list; 222 struct radeon_object *robj; 223 uint64_t gpu_offset; 224 unsigned rdomain; 225 unsigned wdomain; 226 uint32_t tiling_flags; 227 }; 228 229 int radeon_object_init(struct radeon_device *rdev); 230 void radeon_object_fini(struct radeon_device *rdev); 231 int radeon_object_create(struct radeon_device *rdev, 232 struct drm_gem_object *gobj, 233 unsigned long size, 234 bool kernel, 235 uint32_t domain, 236 bool interruptible, 237 struct radeon_object **robj_ptr); 238 int radeon_object_kmap(struct radeon_object *robj, void **ptr); 239 void radeon_object_kunmap(struct radeon_object *robj); 240 void radeon_object_unref(struct radeon_object **robj); 241 int radeon_object_pin(struct radeon_object *robj, uint32_t domain, 242 uint64_t *gpu_addr); 243 void radeon_object_unpin(struct radeon_object *robj); 244 int radeon_object_wait(struct radeon_object *robj); 245 int radeon_object_evict_vram(struct radeon_device *rdev); 246 int radeon_object_mmap(struct radeon_object *robj, uint64_t *offset); 247 void radeon_object_force_delete(struct radeon_device *rdev); 248 void radeon_object_list_add_object(struct radeon_object_list *lobj, 249 struct list_head *head); 250 int radeon_object_list_validate(struct list_head *head, void *fence); 251 void radeon_object_list_unvalidate(struct list_head *head); 252 void radeon_object_list_clean(struct list_head *head); 253 int radeon_object_fbdev_mmap(struct radeon_object *robj, 254 struct vm_area_struct *vma); 255 unsigned long radeon_object_size(struct radeon_object *robj); 256 void radeon_object_clear_surface_reg(struct radeon_object *robj); 257 int radeon_object_check_tiling(struct radeon_object *robj, bool has_moved, 258 bool force_drop); 259 void radeon_object_set_tiling_flags(struct radeon_object *robj, 260 uint32_t tiling_flags, uint32_t pitch); 261 void radeon_object_get_tiling_flags(struct radeon_object *robj, uint32_t *tiling_flags, uint32_t *pitch); 262 void radeon_bo_move_notify(struct ttm_buffer_object *bo, 263 struct ttm_mem_reg *mem); 264 void radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo); 265 /* 266 * GEM objects. 267 */ 268 struct radeon_gem { 269 struct list_head objects; 270 }; 271 272 int radeon_gem_init(struct radeon_device *rdev); 273 void radeon_gem_fini(struct radeon_device *rdev); 274 int radeon_gem_object_create(struct radeon_device *rdev, int size, 275 int alignment, int initial_domain, 276 bool discardable, bool kernel, 277 bool interruptible, 278 struct drm_gem_object **obj); 279 int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain, 280 uint64_t *gpu_addr); 281 void radeon_gem_object_unpin(struct drm_gem_object *obj); 282 283 284 /* 285 * GART structures, functions & helpers 286 */ 287 struct radeon_mc; 288 289 struct radeon_gart_table_ram { 290 volatile uint32_t *ptr; 291 }; 292 293 struct radeon_gart_table_vram { 294 struct radeon_object *robj; 295 volatile uint32_t *ptr; 296 }; 297 298 union radeon_gart_table { 299 struct radeon_gart_table_ram ram; 300 struct radeon_gart_table_vram vram; 301 }; 302 303 struct radeon_gart { 304 dma_addr_t table_addr; 305 unsigned num_gpu_pages; 306 unsigned num_cpu_pages; 307 unsigned table_size; 308 union radeon_gart_table table; 309 struct page **pages; 310 dma_addr_t *pages_addr; 311 bool ready; 312 }; 313 314 int radeon_gart_table_ram_alloc(struct radeon_device *rdev); 315 void radeon_gart_table_ram_free(struct radeon_device *rdev); 316 int radeon_gart_table_vram_alloc(struct radeon_device *rdev); 317 void radeon_gart_table_vram_free(struct radeon_device *rdev); 318 int radeon_gart_init(struct radeon_device *rdev); 319 void radeon_gart_fini(struct radeon_device *rdev); 320 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, 321 int pages); 322 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, 323 int pages, struct page **pagelist); 324 325 326 /* 327 * GPU MC structures, functions & helpers 328 */ 329 struct radeon_mc { 330 resource_size_t aper_size; 331 resource_size_t aper_base; 332 resource_size_t agp_base; 333 unsigned gtt_location; 334 unsigned gtt_size; 335 unsigned vram_location; 336 /* for some chips with <= 32MB we need to lie 337 * about vram size near mc fb location */ 338 unsigned mc_vram_size; 339 unsigned vram_width; 340 unsigned real_vram_size; 341 int vram_mtrr; 342 bool vram_is_ddr; 343 }; 344 345 int radeon_mc_setup(struct radeon_device *rdev); 346 347 348 /* 349 * GPU scratch registers structures, functions & helpers 350 */ 351 struct radeon_scratch { 352 unsigned num_reg; 353 bool free[32]; 354 uint32_t reg[32]; 355 }; 356 357 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); 358 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); 359 360 361 /* 362 * IRQS. 363 */ 364 struct radeon_irq { 365 bool installed; 366 bool sw_int; 367 /* FIXME: use a define max crtc rather than hardcode it */ 368 bool crtc_vblank_int[2]; 369 }; 370 371 int radeon_irq_kms_init(struct radeon_device *rdev); 372 void radeon_irq_kms_fini(struct radeon_device *rdev); 373 374 375 /* 376 * CP & ring. 377 */ 378 struct radeon_ib { 379 struct list_head list; 380 unsigned long idx; 381 uint64_t gpu_addr; 382 struct radeon_fence *fence; 383 volatile uint32_t *ptr; 384 uint32_t length_dw; 385 }; 386 387 struct radeon_ib_pool { 388 struct mutex mutex; 389 struct radeon_object *robj; 390 struct list_head scheduled_ibs; 391 struct radeon_ib ibs[RADEON_IB_POOL_SIZE]; 392 bool ready; 393 DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE); 394 }; 395 396 struct radeon_cp { 397 struct radeon_object *ring_obj; 398 volatile uint32_t *ring; 399 unsigned rptr; 400 unsigned wptr; 401 unsigned wptr_old; 402 unsigned ring_size; 403 unsigned ring_free_dw; 404 int count_dw; 405 uint64_t gpu_addr; 406 uint32_t align_mask; 407 uint32_t ptr_mask; 408 struct mutex mutex; 409 bool ready; 410 }; 411 412 int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib); 413 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib); 414 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib); 415 int radeon_ib_pool_init(struct radeon_device *rdev); 416 void radeon_ib_pool_fini(struct radeon_device *rdev); 417 int radeon_ib_test(struct radeon_device *rdev); 418 /* Ring access between begin & end cannot sleep */ 419 void radeon_ring_free_size(struct radeon_device *rdev); 420 int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw); 421 void radeon_ring_unlock_commit(struct radeon_device *rdev); 422 void radeon_ring_unlock_undo(struct radeon_device *rdev); 423 int radeon_ring_test(struct radeon_device *rdev); 424 int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size); 425 void radeon_ring_fini(struct radeon_device *rdev); 426 427 428 /* 429 * CS. 430 */ 431 struct radeon_cs_reloc { 432 struct drm_gem_object *gobj; 433 struct radeon_object *robj; 434 struct radeon_object_list lobj; 435 uint32_t handle; 436 uint32_t flags; 437 }; 438 439 struct radeon_cs_chunk { 440 uint32_t chunk_id; 441 uint32_t length_dw; 442 uint32_t *kdata; 443 }; 444 445 struct radeon_cs_parser { 446 struct radeon_device *rdev; 447 struct drm_file *filp; 448 /* chunks */ 449 unsigned nchunks; 450 struct radeon_cs_chunk *chunks; 451 uint64_t *chunks_array; 452 /* IB */ 453 unsigned idx; 454 /* relocations */ 455 unsigned nrelocs; 456 struct radeon_cs_reloc *relocs; 457 struct radeon_cs_reloc **relocs_ptr; 458 struct list_head validated; 459 /* indices of various chunks */ 460 int chunk_ib_idx; 461 int chunk_relocs_idx; 462 struct radeon_ib *ib; 463 void *track; 464 }; 465 466 struct radeon_cs_packet { 467 unsigned idx; 468 unsigned type; 469 unsigned reg; 470 unsigned opcode; 471 int count; 472 unsigned one_reg_wr; 473 }; 474 475 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, 476 struct radeon_cs_packet *pkt, 477 unsigned idx, unsigned reg); 478 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, 479 struct radeon_cs_packet *pkt); 480 481 482 /* 483 * AGP 484 */ 485 int radeon_agp_init(struct radeon_device *rdev); 486 void radeon_agp_fini(struct radeon_device *rdev); 487 488 489 /* 490 * Writeback 491 */ 492 struct radeon_wb { 493 struct radeon_object *wb_obj; 494 volatile uint32_t *wb; 495 uint64_t gpu_addr; 496 }; 497 498 /** 499 * struct radeon_pm - power management datas 500 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) 501 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) 502 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) 503 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) 504 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) 505 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) 506 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) 507 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) 508 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) 509 * @sclk: GPU clock Mhz (core bandwith depends of this clock) 510 * @needed_bandwidth: current bandwidth needs 511 * 512 * It keeps track of various data needed to take powermanagement decision. 513 * Bandwith need is used to determine minimun clock of the GPU and memory. 514 * Equation between gpu/memory clock and available bandwidth is hw dependent 515 * (type of memory, bus size, efficiency, ...) 516 */ 517 struct radeon_pm { 518 fixed20_12 max_bandwidth; 519 fixed20_12 igp_sideport_mclk; 520 fixed20_12 igp_system_mclk; 521 fixed20_12 igp_ht_link_clk; 522 fixed20_12 igp_ht_link_width; 523 fixed20_12 k8_bandwidth; 524 fixed20_12 sideport_bandwidth; 525 fixed20_12 ht_bandwidth; 526 fixed20_12 core_bandwidth; 527 fixed20_12 sclk; 528 fixed20_12 needed_bandwidth; 529 }; 530 531 532 /* 533 * Benchmarking 534 */ 535 void radeon_benchmark(struct radeon_device *rdev); 536 537 538 /* 539 * Testing 540 */ 541 void radeon_test_moves(struct radeon_device *rdev); 542 543 544 /* 545 * Debugfs 546 */ 547 int radeon_debugfs_add_files(struct radeon_device *rdev, 548 struct drm_info_list *files, 549 unsigned nfiles); 550 int radeon_debugfs_fence_init(struct radeon_device *rdev); 551 int r100_debugfs_rbbm_init(struct radeon_device *rdev); 552 int r100_debugfs_cp_init(struct radeon_device *rdev); 553 554 555 /* 556 * ASIC specific functions. 557 */ 558 struct radeon_asic { 559 int (*init)(struct radeon_device *rdev); 560 void (*errata)(struct radeon_device *rdev); 561 void (*vram_info)(struct radeon_device *rdev); 562 int (*gpu_reset)(struct radeon_device *rdev); 563 int (*mc_init)(struct radeon_device *rdev); 564 void (*mc_fini)(struct radeon_device *rdev); 565 int (*wb_init)(struct radeon_device *rdev); 566 void (*wb_fini)(struct radeon_device *rdev); 567 int (*gart_enable)(struct radeon_device *rdev); 568 void (*gart_disable)(struct radeon_device *rdev); 569 void (*gart_tlb_flush)(struct radeon_device *rdev); 570 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr); 571 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size); 572 void (*cp_fini)(struct radeon_device *rdev); 573 void (*cp_disable)(struct radeon_device *rdev); 574 void (*ring_start)(struct radeon_device *rdev); 575 int (*irq_set)(struct radeon_device *rdev); 576 int (*irq_process)(struct radeon_device *rdev); 577 void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence); 578 int (*cs_parse)(struct radeon_cs_parser *p); 579 int (*copy_blit)(struct radeon_device *rdev, 580 uint64_t src_offset, 581 uint64_t dst_offset, 582 unsigned num_pages, 583 struct radeon_fence *fence); 584 int (*copy_dma)(struct radeon_device *rdev, 585 uint64_t src_offset, 586 uint64_t dst_offset, 587 unsigned num_pages, 588 struct radeon_fence *fence); 589 int (*copy)(struct radeon_device *rdev, 590 uint64_t src_offset, 591 uint64_t dst_offset, 592 unsigned num_pages, 593 struct radeon_fence *fence); 594 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); 595 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); 596 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); 597 void (*set_clock_gating)(struct radeon_device *rdev, int enable); 598 int (*set_surface_reg)(struct radeon_device *rdev, int reg, 599 uint32_t tiling_flags, uint32_t pitch, 600 uint32_t offset, uint32_t obj_size); 601 int (*clear_surface_reg)(struct radeon_device *rdev, int reg); 602 void (*bandwidth_update)(struct radeon_device *rdev); 603 }; 604 605 union radeon_asic_config { 606 struct r300_asic r300; 607 }; 608 609 610 /* 611 * IOCTL. 612 */ 613 int radeon_gem_info_ioctl(struct drm_device *dev, void *data, 614 struct drm_file *filp); 615 int radeon_gem_create_ioctl(struct drm_device *dev, void *data, 616 struct drm_file *filp); 617 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, 618 struct drm_file *file_priv); 619 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, 620 struct drm_file *file_priv); 621 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, 622 struct drm_file *file_priv); 623 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, 624 struct drm_file *file_priv); 625 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, 626 struct drm_file *filp); 627 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, 628 struct drm_file *filp); 629 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, 630 struct drm_file *filp); 631 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 632 struct drm_file *filp); 633 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 634 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, 635 struct drm_file *filp); 636 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, 637 struct drm_file *filp); 638 639 640 /* 641 * Core structure, functions and helpers. 642 */ 643 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); 644 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); 645 646 struct radeon_device { 647 struct drm_device *ddev; 648 struct pci_dev *pdev; 649 /* ASIC */ 650 union radeon_asic_config config; 651 enum radeon_family family; 652 unsigned long flags; 653 int usec_timeout; 654 enum radeon_pll_errata pll_errata; 655 int num_gb_pipes; 656 int disp_priority; 657 /* BIOS */ 658 uint8_t *bios; 659 bool is_atom_bios; 660 uint16_t bios_header_start; 661 struct radeon_object *stollen_vga_memory; 662 struct fb_info *fbdev_info; 663 struct radeon_object *fbdev_robj; 664 struct radeon_framebuffer *fbdev_rfb; 665 /* Register mmio */ 666 resource_size_t rmmio_base; 667 resource_size_t rmmio_size; 668 void *rmmio; 669 radeon_rreg_t mm_rreg; 670 radeon_wreg_t mm_wreg; 671 radeon_rreg_t mc_rreg; 672 radeon_wreg_t mc_wreg; 673 radeon_rreg_t pll_rreg; 674 radeon_wreg_t pll_wreg; 675 radeon_rreg_t pcie_rreg; 676 radeon_wreg_t pcie_wreg; 677 radeon_rreg_t pciep_rreg; 678 radeon_wreg_t pciep_wreg; 679 struct radeon_clock clock; 680 struct radeon_mc mc; 681 struct radeon_gart gart; 682 struct radeon_mode_info mode_info; 683 struct radeon_scratch scratch; 684 struct radeon_mman mman; 685 struct radeon_fence_driver fence_drv; 686 struct radeon_cp cp; 687 struct radeon_ib_pool ib_pool; 688 struct radeon_irq irq; 689 struct radeon_asic *asic; 690 struct radeon_gem gem; 691 struct radeon_pm pm; 692 struct mutex cs_mutex; 693 struct radeon_wb wb; 694 bool gpu_lockup; 695 bool shutdown; 696 bool suspend; 697 bool need_dma32; 698 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; 699 }; 700 701 int radeon_device_init(struct radeon_device *rdev, 702 struct drm_device *ddev, 703 struct pci_dev *pdev, 704 uint32_t flags); 705 void radeon_device_fini(struct radeon_device *rdev); 706 int radeon_gpu_wait_for_idle(struct radeon_device *rdev); 707 708 709 /* 710 * Registers read & write functions. 711 */ 712 #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg)) 713 #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg)) 714 #define RREG32(reg) rdev->mm_rreg(rdev, (reg)) 715 #define WREG32(reg, v) rdev->mm_wreg(rdev, (reg), (v)) 716 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 717 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 718 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) 719 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) 720 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) 721 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) 722 #define RREG32_PCIE(reg) rdev->pcie_rreg(rdev, (reg)) 723 #define WREG32_PCIE(reg, v) rdev->pcie_wreg(rdev, (reg), (v)) 724 #define WREG32_P(reg, val, mask) \ 725 do { \ 726 uint32_t tmp_ = RREG32(reg); \ 727 tmp_ &= (mask); \ 728 tmp_ |= ((val) & ~(mask)); \ 729 WREG32(reg, tmp_); \ 730 } while (0) 731 #define WREG32_PLL_P(reg, val, mask) \ 732 do { \ 733 uint32_t tmp_ = RREG32_PLL(reg); \ 734 tmp_ &= (mask); \ 735 tmp_ |= ((val) & ~(mask)); \ 736 WREG32_PLL(reg, tmp_); \ 737 } while (0) 738 739 void r100_pll_errata_after_index(struct radeon_device *rdev); 740 741 742 /* 743 * ASICs helpers. 744 */ 745 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ 746 (rdev->pdev->device == 0x5969)) 747 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ 748 (rdev->family == CHIP_RV200) || \ 749 (rdev->family == CHIP_RS100) || \ 750 (rdev->family == CHIP_RS200) || \ 751 (rdev->family == CHIP_RV250) || \ 752 (rdev->family == CHIP_RV280) || \ 753 (rdev->family == CHIP_RS300)) 754 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ 755 (rdev->family == CHIP_RV350) || \ 756 (rdev->family == CHIP_R350) || \ 757 (rdev->family == CHIP_RV380) || \ 758 (rdev->family == CHIP_R420) || \ 759 (rdev->family == CHIP_R423) || \ 760 (rdev->family == CHIP_RV410) || \ 761 (rdev->family == CHIP_RS400) || \ 762 (rdev->family == CHIP_RS480)) 763 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) 764 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) 765 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) 766 767 768 /* 769 * BIOS helpers. 770 */ 771 #define RBIOS8(i) (rdev->bios[i]) 772 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 773 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 774 775 int radeon_combios_init(struct radeon_device *rdev); 776 void radeon_combios_fini(struct radeon_device *rdev); 777 int radeon_atombios_init(struct radeon_device *rdev); 778 void radeon_atombios_fini(struct radeon_device *rdev); 779 780 781 /* 782 * RING helpers. 783 */ 784 #define CP_PACKET0 0x00000000 785 #define PACKET0_BASE_INDEX_SHIFT 0 786 #define PACKET0_BASE_INDEX_MASK (0x1ffff << 0) 787 #define PACKET0_COUNT_SHIFT 16 788 #define PACKET0_COUNT_MASK (0x3fff << 16) 789 #define CP_PACKET1 0x40000000 790 #define CP_PACKET2 0x80000000 791 #define PACKET2_PAD_SHIFT 0 792 #define PACKET2_PAD_MASK (0x3fffffff << 0) 793 #define CP_PACKET3 0xC0000000 794 #define PACKET3_IT_OPCODE_SHIFT 8 795 #define PACKET3_IT_OPCODE_MASK (0xff << 8) 796 #define PACKET3_COUNT_SHIFT 16 797 #define PACKET3_COUNT_MASK (0x3fff << 16) 798 /* PACKET3 op code */ 799 #define PACKET3_NOP 0x10 800 #define PACKET3_3D_DRAW_VBUF 0x28 801 #define PACKET3_3D_DRAW_IMMD 0x29 802 #define PACKET3_3D_DRAW_INDX 0x2A 803 #define PACKET3_3D_LOAD_VBPNTR 0x2F 804 #define PACKET3_INDX_BUFFER 0x33 805 #define PACKET3_3D_DRAW_VBUF_2 0x34 806 #define PACKET3_3D_DRAW_IMMD_2 0x35 807 #define PACKET3_3D_DRAW_INDX_2 0x36 808 #define PACKET3_BITBLT_MULTI 0x9B 809 810 #define PACKET0(reg, n) (CP_PACKET0 | \ 811 REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \ 812 REG_SET(PACKET0_COUNT, (n))) 813 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 814 #define PACKET3(op, n) (CP_PACKET3 | \ 815 REG_SET(PACKET3_IT_OPCODE, (op)) | \ 816 REG_SET(PACKET3_COUNT, (n))) 817 818 #define PACKET_TYPE0 0 819 #define PACKET_TYPE1 1 820 #define PACKET_TYPE2 2 821 #define PACKET_TYPE3 3 822 823 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 824 #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 825 #define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2) 826 #define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1) 827 #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 828 829 static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v) 830 { 831 #if DRM_DEBUG_CODE 832 if (rdev->cp.count_dw <= 0) { 833 DRM_ERROR("radeon: writting more dword to ring than expected !\n"); 834 } 835 #endif 836 rdev->cp.ring[rdev->cp.wptr++] = v; 837 rdev->cp.wptr &= rdev->cp.ptr_mask; 838 rdev->cp.count_dw--; 839 rdev->cp.ring_free_dw--; 840 } 841 842 843 /* 844 * ASICs macro. 845 */ 846 #define radeon_init(rdev) (rdev)->asic->init((rdev)) 847 #define radeon_cs_parse(p) rdev->asic->cs_parse((p)) 848 #define radeon_errata(rdev) (rdev)->asic->errata((rdev)) 849 #define radeon_vram_info(rdev) (rdev)->asic->vram_info((rdev)) 850 #define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev)) 851 #define radeon_mc_init(rdev) (rdev)->asic->mc_init((rdev)) 852 #define radeon_mc_fini(rdev) (rdev)->asic->mc_fini((rdev)) 853 #define radeon_wb_init(rdev) (rdev)->asic->wb_init((rdev)) 854 #define radeon_wb_fini(rdev) (rdev)->asic->wb_fini((rdev)) 855 #define radeon_gart_enable(rdev) (rdev)->asic->gart_enable((rdev)) 856 #define radeon_gart_disable(rdev) (rdev)->asic->gart_disable((rdev)) 857 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev)) 858 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p)) 859 #define radeon_cp_init(rdev,rsize) (rdev)->asic->cp_init((rdev), (rsize)) 860 #define radeon_cp_fini(rdev) (rdev)->asic->cp_fini((rdev)) 861 #define radeon_cp_disable(rdev) (rdev)->asic->cp_disable((rdev)) 862 #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev)) 863 #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev)) 864 #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev)) 865 #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence)) 866 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f)) 867 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f)) 868 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f)) 869 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e)) 870 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e)) 871 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l)) 872 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e)) 873 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s))) 874 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r))) 875 #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev)) 876 877 #endif 878