1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __RADEON_H__ 29 #define __RADEON_H__ 30 31 /* TODO: Here are things that needs to be done : 32 * - surface allocator & initializer : (bit like scratch reg) should 33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings 34 * related to surface 35 * - WB : write back stuff (do it bit like scratch reg things) 36 * - Vblank : look at Jesse's rework and what we should do 37 * - r600/r700: gart & cp 38 * - cs : clean cs ioctl use bitmap & things like that. 39 * - power management stuff 40 * - Barrier in gart code 41 * - Unmappabled vram ? 42 * - TESTING, TESTING, TESTING 43 */ 44 45 /* Initialization path: 46 * We expect that acceleration initialization might fail for various 47 * reasons even thought we work hard to make it works on most 48 * configurations. In order to still have a working userspace in such 49 * situation the init path must succeed up to the memory controller 50 * initialization point. Failure before this point are considered as 51 * fatal error. Here is the init callchain : 52 * radeon_device_init perform common structure, mutex initialization 53 * asic_init setup the GPU memory layout and perform all 54 * one time initialization (failure in this 55 * function are considered fatal) 56 * asic_startup setup the GPU acceleration, in order to 57 * follow guideline the first thing this 58 * function should do is setting the GPU 59 * memory controller (only MC setup failure 60 * are considered as fatal) 61 */ 62 63 #include <linux/atomic.h> 64 #include <linux/wait.h> 65 #include <linux/list.h> 66 #include <linux/kref.h> 67 #include <linux/interval_tree.h> 68 #include <linux/hashtable.h> 69 #include <linux/fence.h> 70 71 #include <ttm/ttm_bo_api.h> 72 #include <ttm/ttm_bo_driver.h> 73 #include <ttm/ttm_placement.h> 74 #include <ttm/ttm_module.h> 75 #include <ttm/ttm_execbuf_util.h> 76 77 #include <drm/drm_gem.h> 78 79 #include "radeon_family.h" 80 #include "radeon_mode.h" 81 #include "radeon_reg.h" 82 83 /* 84 * Modules parameters. 85 */ 86 extern int radeon_no_wb; 87 extern int radeon_modeset; 88 extern int radeon_dynclks; 89 extern int radeon_r4xx_atom; 90 extern int radeon_agpmode; 91 extern int radeon_vram_limit; 92 extern int radeon_gart_size; 93 extern int radeon_benchmarking; 94 extern int radeon_testing; 95 extern int radeon_connector_table; 96 extern int radeon_tv; 97 extern int radeon_audio; 98 extern int radeon_disp_priority; 99 extern int radeon_hw_i2c; 100 extern int radeon_pcie_gen2; 101 extern int radeon_msi; 102 extern int radeon_lockup_timeout; 103 extern int radeon_fastfb; 104 extern int radeon_dpm; 105 extern int radeon_aspm; 106 extern int radeon_runtime_pm; 107 extern int radeon_hard_reset; 108 extern int radeon_vm_size; 109 extern int radeon_vm_block_size; 110 extern int radeon_deep_color; 111 extern int radeon_use_pflipirq; 112 extern int radeon_bapm; 113 extern int radeon_backlight; 114 115 /* 116 * Copy from radeon_drv.h so we don't have to include both and have conflicting 117 * symbol; 118 */ 119 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 120 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) 121 /* RADEON_IB_POOL_SIZE must be a power of 2 */ 122 #define RADEON_IB_POOL_SIZE 16 123 #define RADEON_DEBUGFS_MAX_COMPONENTS 32 124 #define RADEONFB_CONN_LIMIT 4 125 #define RADEON_BIOS_NUM_SCRATCH 8 126 127 /* internal ring indices */ 128 /* r1xx+ has gfx CP ring */ 129 #define RADEON_RING_TYPE_GFX_INDEX 0 130 131 /* cayman has 2 compute CP rings */ 132 #define CAYMAN_RING_TYPE_CP1_INDEX 1 133 #define CAYMAN_RING_TYPE_CP2_INDEX 2 134 135 /* R600+ has an async dma ring */ 136 #define R600_RING_TYPE_DMA_INDEX 3 137 /* cayman add a second async dma ring */ 138 #define CAYMAN_RING_TYPE_DMA1_INDEX 4 139 140 /* R600+ */ 141 #define R600_RING_TYPE_UVD_INDEX 5 142 143 /* TN+ */ 144 #define TN_RING_TYPE_VCE1_INDEX 6 145 #define TN_RING_TYPE_VCE2_INDEX 7 146 147 /* max number of rings */ 148 #define RADEON_NUM_RINGS 8 149 150 /* number of hw syncs before falling back on blocking */ 151 #define RADEON_NUM_SYNCS 4 152 153 /* hardcode those limit for now */ 154 #define RADEON_VA_IB_OFFSET (1 << 20) 155 #define RADEON_VA_RESERVED_SIZE (8 << 20) 156 #define RADEON_IB_VM_MAX_SIZE (64 << 10) 157 158 /* hard reset data */ 159 #define RADEON_ASIC_RESET_DATA 0x39d5e86b 160 161 /* reset flags */ 162 #define RADEON_RESET_GFX (1 << 0) 163 #define RADEON_RESET_COMPUTE (1 << 1) 164 #define RADEON_RESET_DMA (1 << 2) 165 #define RADEON_RESET_CP (1 << 3) 166 #define RADEON_RESET_GRBM (1 << 4) 167 #define RADEON_RESET_DMA1 (1 << 5) 168 #define RADEON_RESET_RLC (1 << 6) 169 #define RADEON_RESET_SEM (1 << 7) 170 #define RADEON_RESET_IH (1 << 8) 171 #define RADEON_RESET_VMC (1 << 9) 172 #define RADEON_RESET_MC (1 << 10) 173 #define RADEON_RESET_DISPLAY (1 << 11) 174 175 /* CG block flags */ 176 #define RADEON_CG_BLOCK_GFX (1 << 0) 177 #define RADEON_CG_BLOCK_MC (1 << 1) 178 #define RADEON_CG_BLOCK_SDMA (1 << 2) 179 #define RADEON_CG_BLOCK_UVD (1 << 3) 180 #define RADEON_CG_BLOCK_VCE (1 << 4) 181 #define RADEON_CG_BLOCK_HDP (1 << 5) 182 #define RADEON_CG_BLOCK_BIF (1 << 6) 183 184 /* CG flags */ 185 #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0) 186 #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1) 187 #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2) 188 #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3) 189 #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4) 190 #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5) 191 #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6) 192 #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7) 193 #define RADEON_CG_SUPPORT_MC_LS (1 << 8) 194 #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9) 195 #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10) 196 #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11) 197 #define RADEON_CG_SUPPORT_BIF_LS (1 << 12) 198 #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13) 199 #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14) 200 #define RADEON_CG_SUPPORT_HDP_LS (1 << 15) 201 #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16) 202 203 /* PG flags */ 204 #define RADEON_PG_SUPPORT_GFX_PG (1 << 0) 205 #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1) 206 #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2) 207 #define RADEON_PG_SUPPORT_UVD (1 << 3) 208 #define RADEON_PG_SUPPORT_VCE (1 << 4) 209 #define RADEON_PG_SUPPORT_CP (1 << 5) 210 #define RADEON_PG_SUPPORT_GDS (1 << 6) 211 #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7) 212 #define RADEON_PG_SUPPORT_SDMA (1 << 8) 213 #define RADEON_PG_SUPPORT_ACP (1 << 9) 214 #define RADEON_PG_SUPPORT_SAMU (1 << 10) 215 216 /* max cursor sizes (in pixels) */ 217 #define CURSOR_WIDTH 64 218 #define CURSOR_HEIGHT 64 219 220 #define CIK_CURSOR_WIDTH 128 221 #define CIK_CURSOR_HEIGHT 128 222 223 /* 224 * Errata workarounds. 225 */ 226 enum radeon_pll_errata { 227 CHIP_ERRATA_R300_CG = 0x00000001, 228 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, 229 CHIP_ERRATA_PLL_DELAY = 0x00000004 230 }; 231 232 233 struct radeon_device; 234 235 236 /* 237 * BIOS. 238 */ 239 bool radeon_get_bios(struct radeon_device *rdev); 240 241 /* 242 * Dummy page 243 */ 244 struct radeon_dummy_page { 245 uint64_t entry; 246 struct page *page; 247 dma_addr_t addr; 248 }; 249 int radeon_dummy_page_init(struct radeon_device *rdev); 250 void radeon_dummy_page_fini(struct radeon_device *rdev); 251 252 253 /* 254 * Clocks 255 */ 256 struct radeon_clock { 257 struct radeon_pll p1pll; 258 struct radeon_pll p2pll; 259 struct radeon_pll dcpll; 260 struct radeon_pll spll; 261 struct radeon_pll mpll; 262 /* 10 Khz units */ 263 uint32_t default_mclk; 264 uint32_t default_sclk; 265 uint32_t default_dispclk; 266 uint32_t current_dispclk; 267 uint32_t dp_extclk; 268 uint32_t max_pixel_clock; 269 }; 270 271 /* 272 * Power management 273 */ 274 int radeon_pm_init(struct radeon_device *rdev); 275 int radeon_pm_late_init(struct radeon_device *rdev); 276 void radeon_pm_fini(struct radeon_device *rdev); 277 void radeon_pm_compute_clocks(struct radeon_device *rdev); 278 void radeon_pm_suspend(struct radeon_device *rdev); 279 void radeon_pm_resume(struct radeon_device *rdev); 280 void radeon_combios_get_power_modes(struct radeon_device *rdev); 281 void radeon_atombios_get_power_modes(struct radeon_device *rdev); 282 int radeon_atom_get_clock_dividers(struct radeon_device *rdev, 283 u8 clock_type, 284 u32 clock, 285 bool strobe_mode, 286 struct atom_clock_dividers *dividers); 287 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev, 288 u32 clock, 289 bool strobe_mode, 290 struct atom_mpll_param *mpll_param); 291 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); 292 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev, 293 u16 voltage_level, u8 voltage_type, 294 u32 *gpio_value, u32 *gpio_mask); 295 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev, 296 u32 eng_clock, u32 mem_clock); 297 int radeon_atom_get_voltage_step(struct radeon_device *rdev, 298 u8 voltage_type, u16 *voltage_step); 299 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 300 u16 voltage_id, u16 *voltage); 301 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev, 302 u16 *voltage, 303 u16 leakage_idx); 304 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev, 305 u16 *leakage_id); 306 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev, 307 u16 *vddc, u16 *vddci, 308 u16 virtual_voltage_id, 309 u16 vbios_voltage_id); 310 int radeon_atom_get_voltage_evv(struct radeon_device *rdev, 311 u16 virtual_voltage_id, 312 u16 *voltage); 313 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev, 314 u8 voltage_type, 315 u16 nominal_voltage, 316 u16 *true_voltage); 317 int radeon_atom_get_min_voltage(struct radeon_device *rdev, 318 u8 voltage_type, u16 *min_voltage); 319 int radeon_atom_get_max_voltage(struct radeon_device *rdev, 320 u8 voltage_type, u16 *max_voltage); 321 int radeon_atom_get_voltage_table(struct radeon_device *rdev, 322 u8 voltage_type, u8 voltage_mode, 323 struct atom_voltage_table *voltage_table); 324 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev, 325 u8 voltage_type, u8 voltage_mode); 326 int radeon_atom_get_svi2_info(struct radeon_device *rdev, 327 u8 voltage_type, 328 u8 *svd_gpio_id, u8 *svc_gpio_id); 329 void radeon_atom_update_memory_dll(struct radeon_device *rdev, 330 u32 mem_clock); 331 void radeon_atom_set_ac_timing(struct radeon_device *rdev, 332 u32 mem_clock); 333 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev, 334 u8 module_index, 335 struct atom_mc_reg_table *reg_table); 336 int radeon_atom_get_memory_info(struct radeon_device *rdev, 337 u8 module_index, struct atom_memory_info *mem_info); 338 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev, 339 bool gddr5, u8 module_index, 340 struct atom_memory_clock_range_table *mclk_range_table); 341 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 342 u16 voltage_id, u16 *voltage); 343 void rs690_pm_info(struct radeon_device *rdev); 344 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, 345 unsigned *bankh, unsigned *mtaspect, 346 unsigned *tile_split); 347 348 /* 349 * Fences. 350 */ 351 struct radeon_fence_driver { 352 struct radeon_device *rdev; 353 uint32_t scratch_reg; 354 uint64_t gpu_addr; 355 volatile uint32_t *cpu_addr; 356 /* sync_seq is protected by ring emission lock */ 357 uint64_t sync_seq[RADEON_NUM_RINGS]; 358 atomic64_t last_seq; 359 bool initialized, delayed_irq; 360 struct delayed_work lockup_work; 361 }; 362 363 struct radeon_fence { 364 struct fence base; 365 366 struct radeon_device *rdev; 367 uint64_t seq; 368 /* RB, DMA, etc. */ 369 unsigned ring; 370 bool is_vm_update; 371 372 wait_queue_t fence_wake; 373 }; 374 375 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring); 376 int radeon_fence_driver_init(struct radeon_device *rdev); 377 void radeon_fence_driver_fini(struct radeon_device *rdev); 378 void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring); 379 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring); 380 void radeon_fence_process(struct radeon_device *rdev, int ring); 381 bool radeon_fence_signaled(struct radeon_fence *fence); 382 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); 383 int radeon_fence_wait_next(struct radeon_device *rdev, int ring); 384 int radeon_fence_wait_empty(struct radeon_device *rdev, int ring); 385 int radeon_fence_wait_any(struct radeon_device *rdev, 386 struct radeon_fence **fences, 387 bool intr); 388 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); 389 void radeon_fence_unref(struct radeon_fence **fence); 390 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring); 391 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring); 392 void radeon_fence_note_sync(struct radeon_fence *fence, int ring); 393 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a, 394 struct radeon_fence *b) 395 { 396 if (!a) { 397 return b; 398 } 399 400 if (!b) { 401 return a; 402 } 403 404 BUG_ON(a->ring != b->ring); 405 406 if (a->seq > b->seq) { 407 return a; 408 } else { 409 return b; 410 } 411 } 412 413 static inline bool radeon_fence_is_earlier(struct radeon_fence *a, 414 struct radeon_fence *b) 415 { 416 if (!a) { 417 return false; 418 } 419 420 if (!b) { 421 return true; 422 } 423 424 BUG_ON(a->ring != b->ring); 425 426 return a->seq < b->seq; 427 } 428 429 /* 430 * Tiling registers 431 */ 432 struct radeon_surface_reg { 433 struct radeon_bo *bo; 434 }; 435 436 #define RADEON_GEM_MAX_SURFACES 8 437 438 /* 439 * TTM. 440 */ 441 struct radeon_mman { 442 struct ttm_bo_global_ref bo_global_ref; 443 struct drm_global_reference mem_global_ref; 444 struct ttm_bo_device bdev; 445 bool mem_global_referenced; 446 bool initialized; 447 448 #if defined(CONFIG_DEBUG_FS) 449 struct dentry *vram; 450 struct dentry *gtt; 451 #endif 452 }; 453 454 struct radeon_bo_list { 455 struct radeon_bo *robj; 456 struct ttm_validate_buffer tv; 457 uint64_t gpu_offset; 458 unsigned prefered_domains; 459 unsigned allowed_domains; 460 uint32_t tiling_flags; 461 }; 462 463 /* bo virtual address in a specific vm */ 464 struct radeon_bo_va { 465 /* protected by bo being reserved */ 466 struct list_head bo_list; 467 uint32_t flags; 468 uint64_t addr; 469 struct radeon_fence *last_pt_update; 470 unsigned ref_count; 471 472 /* protected by vm mutex */ 473 struct interval_tree_node it; 474 struct list_head vm_status; 475 476 /* constant after initialization */ 477 struct radeon_vm *vm; 478 struct radeon_bo *bo; 479 }; 480 481 struct radeon_bo { 482 /* Protected by gem.mutex */ 483 struct list_head list; 484 /* Protected by tbo.reserved */ 485 u32 initial_domain; 486 struct ttm_place placements[4]; 487 struct ttm_placement placement; 488 struct ttm_buffer_object tbo; 489 struct ttm_bo_kmap_obj kmap; 490 u32 flags; 491 unsigned pin_count; 492 void *kptr; 493 u32 tiling_flags; 494 u32 pitch; 495 int surface_reg; 496 /* list of all virtual address to which this bo 497 * is associated to 498 */ 499 struct list_head va; 500 /* Constant after initialization */ 501 struct radeon_device *rdev; 502 struct drm_gem_object gem_base; 503 504 struct ttm_bo_kmap_obj dma_buf_vmap; 505 pid_t pid; 506 507 struct radeon_mn *mn; 508 struct interval_tree_node mn_it; 509 }; 510 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base) 511 512 int radeon_gem_debugfs_init(struct radeon_device *rdev); 513 514 /* sub-allocation manager, it has to be protected by another lock. 515 * By conception this is an helper for other part of the driver 516 * like the indirect buffer or semaphore, which both have their 517 * locking. 518 * 519 * Principe is simple, we keep a list of sub allocation in offset 520 * order (first entry has offset == 0, last entry has the highest 521 * offset). 522 * 523 * When allocating new object we first check if there is room at 524 * the end total_size - (last_object_offset + last_object_size) >= 525 * alloc_size. If so we allocate new object there. 526 * 527 * When there is not enough room at the end, we start waiting for 528 * each sub object until we reach object_offset+object_size >= 529 * alloc_size, this object then become the sub object we return. 530 * 531 * Alignment can't be bigger than page size. 532 * 533 * Hole are not considered for allocation to keep things simple. 534 * Assumption is that there won't be hole (all object on same 535 * alignment). 536 */ 537 struct radeon_sa_manager { 538 wait_queue_head_t wq; 539 struct radeon_bo *bo; 540 struct list_head *hole; 541 struct list_head flist[RADEON_NUM_RINGS]; 542 struct list_head olist; 543 unsigned size; 544 uint64_t gpu_addr; 545 void *cpu_ptr; 546 uint32_t domain; 547 uint32_t align; 548 }; 549 550 struct radeon_sa_bo; 551 552 /* sub-allocation buffer */ 553 struct radeon_sa_bo { 554 struct list_head olist; 555 struct list_head flist; 556 struct radeon_sa_manager *manager; 557 unsigned soffset; 558 unsigned eoffset; 559 struct radeon_fence *fence; 560 }; 561 562 /* 563 * GEM objects. 564 */ 565 struct radeon_gem { 566 struct mutex mutex; 567 struct list_head objects; 568 }; 569 570 int radeon_gem_init(struct radeon_device *rdev); 571 void radeon_gem_fini(struct radeon_device *rdev); 572 int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size, 573 int alignment, int initial_domain, 574 u32 flags, bool kernel, 575 struct drm_gem_object **obj); 576 577 int radeon_mode_dumb_create(struct drm_file *file_priv, 578 struct drm_device *dev, 579 struct drm_mode_create_dumb *args); 580 int radeon_mode_dumb_mmap(struct drm_file *filp, 581 struct drm_device *dev, 582 uint32_t handle, uint64_t *offset_p); 583 584 /* 585 * Semaphores. 586 */ 587 struct radeon_semaphore { 588 struct radeon_sa_bo *sa_bo; 589 signed waiters; 590 uint64_t gpu_addr; 591 }; 592 593 int radeon_semaphore_create(struct radeon_device *rdev, 594 struct radeon_semaphore **semaphore); 595 bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, 596 struct radeon_semaphore *semaphore); 597 bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, 598 struct radeon_semaphore *semaphore); 599 void radeon_semaphore_free(struct radeon_device *rdev, 600 struct radeon_semaphore **semaphore, 601 struct radeon_fence *fence); 602 603 /* 604 * Synchronization 605 */ 606 struct radeon_sync { 607 struct radeon_semaphore *semaphores[RADEON_NUM_SYNCS]; 608 struct radeon_fence *sync_to[RADEON_NUM_RINGS]; 609 struct radeon_fence *last_vm_update; 610 }; 611 612 void radeon_sync_create(struct radeon_sync *sync); 613 void radeon_sync_fence(struct radeon_sync *sync, 614 struct radeon_fence *fence); 615 int radeon_sync_resv(struct radeon_device *rdev, 616 struct radeon_sync *sync, 617 struct reservation_object *resv, 618 bool shared); 619 int radeon_sync_rings(struct radeon_device *rdev, 620 struct radeon_sync *sync, 621 int waiting_ring); 622 void radeon_sync_free(struct radeon_device *rdev, struct radeon_sync *sync, 623 struct radeon_fence *fence); 624 625 /* 626 * GART structures, functions & helpers 627 */ 628 struct radeon_mc; 629 630 #define RADEON_GPU_PAGE_SIZE 4096 631 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) 632 #define RADEON_GPU_PAGE_SHIFT 12 633 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK) 634 635 #define RADEON_GART_PAGE_DUMMY 0 636 #define RADEON_GART_PAGE_VALID (1 << 0) 637 #define RADEON_GART_PAGE_READ (1 << 1) 638 #define RADEON_GART_PAGE_WRITE (1 << 2) 639 #define RADEON_GART_PAGE_SNOOP (1 << 3) 640 641 struct radeon_gart { 642 dma_addr_t table_addr; 643 struct radeon_bo *robj; 644 void *ptr; 645 unsigned num_gpu_pages; 646 unsigned num_cpu_pages; 647 unsigned table_size; 648 struct page **pages; 649 uint64_t *pages_entry; 650 bool ready; 651 }; 652 653 int radeon_gart_table_ram_alloc(struct radeon_device *rdev); 654 void radeon_gart_table_ram_free(struct radeon_device *rdev); 655 int radeon_gart_table_vram_alloc(struct radeon_device *rdev); 656 void radeon_gart_table_vram_free(struct radeon_device *rdev); 657 int radeon_gart_table_vram_pin(struct radeon_device *rdev); 658 void radeon_gart_table_vram_unpin(struct radeon_device *rdev); 659 int radeon_gart_init(struct radeon_device *rdev); 660 void radeon_gart_fini(struct radeon_device *rdev); 661 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, 662 int pages); 663 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, 664 int pages, struct page **pagelist, 665 dma_addr_t *dma_addr, uint32_t flags); 666 667 668 /* 669 * GPU MC structures, functions & helpers 670 */ 671 struct radeon_mc { 672 resource_size_t aper_size; 673 resource_size_t aper_base; 674 resource_size_t agp_base; 675 /* for some chips with <= 32MB we need to lie 676 * about vram size near mc fb location */ 677 u64 mc_vram_size; 678 u64 visible_vram_size; 679 u64 gtt_size; 680 u64 gtt_start; 681 u64 gtt_end; 682 u64 vram_start; 683 u64 vram_end; 684 unsigned vram_width; 685 u64 real_vram_size; 686 int vram_mtrr; 687 bool vram_is_ddr; 688 bool igp_sideport_enabled; 689 u64 gtt_base_align; 690 u64 mc_mask; 691 }; 692 693 bool radeon_combios_sideport_present(struct radeon_device *rdev); 694 bool radeon_atombios_sideport_present(struct radeon_device *rdev); 695 696 /* 697 * GPU scratch registers structures, functions & helpers 698 */ 699 struct radeon_scratch { 700 unsigned num_reg; 701 uint32_t reg_base; 702 bool free[32]; 703 uint32_t reg[32]; 704 }; 705 706 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); 707 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); 708 709 /* 710 * GPU doorbell structures, functions & helpers 711 */ 712 #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */ 713 714 struct radeon_doorbell { 715 /* doorbell mmio */ 716 resource_size_t base; 717 resource_size_t size; 718 u32 __iomem *ptr; 719 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */ 720 unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)]; 721 }; 722 723 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page); 724 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell); 725 void radeon_doorbell_get_kfd_info(struct radeon_device *rdev, 726 phys_addr_t *aperture_base, 727 size_t *aperture_size, 728 size_t *start_offset); 729 730 /* 731 * IRQS. 732 */ 733 734 struct radeon_flip_work { 735 struct work_struct flip_work; 736 struct work_struct unpin_work; 737 struct radeon_device *rdev; 738 int crtc_id; 739 uint64_t base; 740 struct drm_pending_vblank_event *event; 741 struct radeon_bo *old_rbo; 742 struct fence *fence; 743 }; 744 745 struct r500_irq_stat_regs { 746 u32 disp_int; 747 u32 hdmi0_status; 748 }; 749 750 struct r600_irq_stat_regs { 751 u32 disp_int; 752 u32 disp_int_cont; 753 u32 disp_int_cont2; 754 u32 d1grph_int; 755 u32 d2grph_int; 756 u32 hdmi0_status; 757 u32 hdmi1_status; 758 }; 759 760 struct evergreen_irq_stat_regs { 761 u32 disp_int; 762 u32 disp_int_cont; 763 u32 disp_int_cont2; 764 u32 disp_int_cont3; 765 u32 disp_int_cont4; 766 u32 disp_int_cont5; 767 u32 d1grph_int; 768 u32 d2grph_int; 769 u32 d3grph_int; 770 u32 d4grph_int; 771 u32 d5grph_int; 772 u32 d6grph_int; 773 u32 afmt_status1; 774 u32 afmt_status2; 775 u32 afmt_status3; 776 u32 afmt_status4; 777 u32 afmt_status5; 778 u32 afmt_status6; 779 }; 780 781 struct cik_irq_stat_regs { 782 u32 disp_int; 783 u32 disp_int_cont; 784 u32 disp_int_cont2; 785 u32 disp_int_cont3; 786 u32 disp_int_cont4; 787 u32 disp_int_cont5; 788 u32 disp_int_cont6; 789 u32 d1grph_int; 790 u32 d2grph_int; 791 u32 d3grph_int; 792 u32 d4grph_int; 793 u32 d5grph_int; 794 u32 d6grph_int; 795 }; 796 797 union radeon_irq_stat_regs { 798 struct r500_irq_stat_regs r500; 799 struct r600_irq_stat_regs r600; 800 struct evergreen_irq_stat_regs evergreen; 801 struct cik_irq_stat_regs cik; 802 }; 803 804 struct radeon_irq { 805 bool installed; 806 spinlock_t lock; 807 atomic_t ring_int[RADEON_NUM_RINGS]; 808 bool crtc_vblank_int[RADEON_MAX_CRTCS]; 809 atomic_t pflip[RADEON_MAX_CRTCS]; 810 wait_queue_head_t vblank_queue; 811 bool hpd[RADEON_MAX_HPD_PINS]; 812 bool afmt[RADEON_MAX_AFMT_BLOCKS]; 813 union radeon_irq_stat_regs stat_regs; 814 bool dpm_thermal; 815 }; 816 817 int radeon_irq_kms_init(struct radeon_device *rdev); 818 void radeon_irq_kms_fini(struct radeon_device *rdev); 819 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring); 820 bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring); 821 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring); 822 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); 823 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); 824 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block); 825 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block); 826 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 827 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 828 829 /* 830 * CP & rings. 831 */ 832 833 struct radeon_ib { 834 struct radeon_sa_bo *sa_bo; 835 uint32_t length_dw; 836 uint64_t gpu_addr; 837 uint32_t *ptr; 838 int ring; 839 struct radeon_fence *fence; 840 struct radeon_vm *vm; 841 bool is_const_ib; 842 struct radeon_sync sync; 843 }; 844 845 struct radeon_ring { 846 struct radeon_bo *ring_obj; 847 volatile uint32_t *ring; 848 unsigned rptr_offs; 849 unsigned rptr_save_reg; 850 u64 next_rptr_gpu_addr; 851 volatile u32 *next_rptr_cpu_addr; 852 unsigned wptr; 853 unsigned wptr_old; 854 unsigned ring_size; 855 unsigned ring_free_dw; 856 int count_dw; 857 atomic_t last_rptr; 858 atomic64_t last_activity; 859 uint64_t gpu_addr; 860 uint32_t align_mask; 861 uint32_t ptr_mask; 862 bool ready; 863 u32 nop; 864 u32 idx; 865 u64 last_semaphore_signal_addr; 866 u64 last_semaphore_wait_addr; 867 /* for CIK queues */ 868 u32 me; 869 u32 pipe; 870 u32 queue; 871 struct radeon_bo *mqd_obj; 872 u32 doorbell_index; 873 unsigned wptr_offs; 874 }; 875 876 struct radeon_mec { 877 struct radeon_bo *hpd_eop_obj; 878 u64 hpd_eop_gpu_addr; 879 u32 num_pipe; 880 u32 num_mec; 881 u32 num_queue; 882 }; 883 884 /* 885 * VM 886 */ 887 888 /* maximum number of VMIDs */ 889 #define RADEON_NUM_VM 16 890 891 /* number of entries in page table */ 892 #define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size) 893 894 /* PTBs (Page Table Blocks) need to be aligned to 32K */ 895 #define RADEON_VM_PTB_ALIGN_SIZE 32768 896 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1) 897 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK) 898 899 #define R600_PTE_VALID (1 << 0) 900 #define R600_PTE_SYSTEM (1 << 1) 901 #define R600_PTE_SNOOPED (1 << 2) 902 #define R600_PTE_READABLE (1 << 5) 903 #define R600_PTE_WRITEABLE (1 << 6) 904 905 /* PTE (Page Table Entry) fragment field for different page sizes */ 906 #define R600_PTE_FRAG_4KB (0 << 7) 907 #define R600_PTE_FRAG_64KB (4 << 7) 908 #define R600_PTE_FRAG_256KB (6 << 7) 909 910 /* flags needed to be set so we can copy directly from the GART table */ 911 #define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \ 912 R600_PTE_SYSTEM | R600_PTE_VALID ) 913 914 struct radeon_vm_pt { 915 struct radeon_bo *bo; 916 uint64_t addr; 917 }; 918 919 struct radeon_vm_id { 920 unsigned id; 921 uint64_t pd_gpu_addr; 922 /* last flushed PD/PT update */ 923 struct radeon_fence *flushed_updates; 924 /* last use of vmid */ 925 struct radeon_fence *last_id_use; 926 }; 927 928 struct radeon_vm { 929 struct mutex mutex; 930 931 struct rb_root va; 932 933 /* protecting invalidated and freed */ 934 spinlock_t status_lock; 935 936 /* BOs moved, but not yet updated in the PT */ 937 struct list_head invalidated; 938 939 /* BOs freed, but not yet updated in the PT */ 940 struct list_head freed; 941 942 /* contains the page directory */ 943 struct radeon_bo *page_directory; 944 unsigned max_pde_used; 945 946 /* array of page tables, one for each page directory entry */ 947 struct radeon_vm_pt *page_tables; 948 949 struct radeon_bo_va *ib_bo_va; 950 951 /* for id and flush management per ring */ 952 struct radeon_vm_id ids[RADEON_NUM_RINGS]; 953 }; 954 955 struct radeon_vm_manager { 956 struct radeon_fence *active[RADEON_NUM_VM]; 957 uint32_t max_pfn; 958 /* number of VMIDs */ 959 unsigned nvm; 960 /* vram base address for page table entry */ 961 u64 vram_base_offset; 962 /* is vm enabled? */ 963 bool enabled; 964 /* for hw to save the PD addr on suspend/resume */ 965 uint32_t saved_table_addr[RADEON_NUM_VM]; 966 }; 967 968 /* 969 * file private structure 970 */ 971 struct radeon_fpriv { 972 struct radeon_vm vm; 973 }; 974 975 /* 976 * R6xx+ IH ring 977 */ 978 struct r600_ih { 979 struct radeon_bo *ring_obj; 980 volatile uint32_t *ring; 981 unsigned rptr; 982 unsigned ring_size; 983 uint64_t gpu_addr; 984 uint32_t ptr_mask; 985 atomic_t lock; 986 bool enabled; 987 }; 988 989 /* 990 * RLC stuff 991 */ 992 #include "clearstate_defs.h" 993 994 struct radeon_rlc { 995 /* for power gating */ 996 struct radeon_bo *save_restore_obj; 997 uint64_t save_restore_gpu_addr; 998 volatile uint32_t *sr_ptr; 999 const u32 *reg_list; 1000 u32 reg_list_size; 1001 /* for clear state */ 1002 struct radeon_bo *clear_state_obj; 1003 uint64_t clear_state_gpu_addr; 1004 volatile uint32_t *cs_ptr; 1005 const struct cs_section_def *cs_data; 1006 u32 clear_state_size; 1007 /* for cp tables */ 1008 struct radeon_bo *cp_table_obj; 1009 uint64_t cp_table_gpu_addr; 1010 volatile uint32_t *cp_table_ptr; 1011 u32 cp_table_size; 1012 }; 1013 1014 int radeon_ib_get(struct radeon_device *rdev, int ring, 1015 struct radeon_ib *ib, struct radeon_vm *vm, 1016 unsigned size); 1017 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); 1018 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, 1019 struct radeon_ib *const_ib, bool hdp_flush); 1020 int radeon_ib_pool_init(struct radeon_device *rdev); 1021 void radeon_ib_pool_fini(struct radeon_device *rdev); 1022 int radeon_ib_ring_tests(struct radeon_device *rdev); 1023 /* Ring access between begin & end cannot sleep */ 1024 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, 1025 struct radeon_ring *ring); 1026 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); 1027 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 1028 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 1029 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp, 1030 bool hdp_flush); 1031 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp, 1032 bool hdp_flush); 1033 void radeon_ring_undo(struct radeon_ring *ring); 1034 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); 1035 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 1036 void radeon_ring_lockup_update(struct radeon_device *rdev, 1037 struct radeon_ring *ring); 1038 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 1039 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, 1040 uint32_t **data); 1041 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, 1042 unsigned size, uint32_t *data); 1043 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size, 1044 unsigned rptr_offs, u32 nop); 1045 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); 1046 1047 1048 /* r600 async dma */ 1049 void r600_dma_stop(struct radeon_device *rdev); 1050 int r600_dma_resume(struct radeon_device *rdev); 1051 void r600_dma_fini(struct radeon_device *rdev); 1052 1053 void cayman_dma_stop(struct radeon_device *rdev); 1054 int cayman_dma_resume(struct radeon_device *rdev); 1055 void cayman_dma_fini(struct radeon_device *rdev); 1056 1057 /* 1058 * CS. 1059 */ 1060 struct radeon_cs_chunk { 1061 uint32_t length_dw; 1062 uint32_t *kdata; 1063 void __user *user_ptr; 1064 }; 1065 1066 struct radeon_cs_parser { 1067 struct device *dev; 1068 struct radeon_device *rdev; 1069 struct drm_file *filp; 1070 /* chunks */ 1071 unsigned nchunks; 1072 struct radeon_cs_chunk *chunks; 1073 uint64_t *chunks_array; 1074 /* IB */ 1075 unsigned idx; 1076 /* relocations */ 1077 unsigned nrelocs; 1078 struct radeon_bo_list *relocs; 1079 struct radeon_bo_list *vm_bos; 1080 struct list_head validated; 1081 unsigned dma_reloc_idx; 1082 /* indices of various chunks */ 1083 struct radeon_cs_chunk *chunk_ib; 1084 struct radeon_cs_chunk *chunk_relocs; 1085 struct radeon_cs_chunk *chunk_flags; 1086 struct radeon_cs_chunk *chunk_const_ib; 1087 struct radeon_ib ib; 1088 struct radeon_ib const_ib; 1089 void *track; 1090 unsigned family; 1091 int parser_error; 1092 u32 cs_flags; 1093 u32 ring; 1094 s32 priority; 1095 struct ww_acquire_ctx ticket; 1096 }; 1097 1098 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) 1099 { 1100 struct radeon_cs_chunk *ibc = p->chunk_ib; 1101 1102 if (ibc->kdata) 1103 return ibc->kdata[idx]; 1104 return p->ib.ptr[idx]; 1105 } 1106 1107 1108 struct radeon_cs_packet { 1109 unsigned idx; 1110 unsigned type; 1111 unsigned reg; 1112 unsigned opcode; 1113 int count; 1114 unsigned one_reg_wr; 1115 }; 1116 1117 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, 1118 struct radeon_cs_packet *pkt, 1119 unsigned idx, unsigned reg); 1120 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, 1121 struct radeon_cs_packet *pkt); 1122 1123 1124 /* 1125 * AGP 1126 */ 1127 int radeon_agp_init(struct radeon_device *rdev); 1128 void radeon_agp_resume(struct radeon_device *rdev); 1129 void radeon_agp_suspend(struct radeon_device *rdev); 1130 void radeon_agp_fini(struct radeon_device *rdev); 1131 1132 1133 /* 1134 * Writeback 1135 */ 1136 struct radeon_wb { 1137 struct radeon_bo *wb_obj; 1138 volatile uint32_t *wb; 1139 uint64_t gpu_addr; 1140 bool enabled; 1141 bool use_event; 1142 }; 1143 1144 #define RADEON_WB_SCRATCH_OFFSET 0 1145 #define RADEON_WB_RING0_NEXT_RPTR 256 1146 #define RADEON_WB_CP_RPTR_OFFSET 1024 1147 #define RADEON_WB_CP1_RPTR_OFFSET 1280 1148 #define RADEON_WB_CP2_RPTR_OFFSET 1536 1149 #define R600_WB_DMA_RPTR_OFFSET 1792 1150 #define R600_WB_IH_WPTR_OFFSET 2048 1151 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304 1152 #define R600_WB_EVENT_OFFSET 3072 1153 #define CIK_WB_CP1_WPTR_OFFSET 3328 1154 #define CIK_WB_CP2_WPTR_OFFSET 3584 1155 #define R600_WB_DMA_RING_TEST_OFFSET 3588 1156 #define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592 1157 1158 /** 1159 * struct radeon_pm - power management datas 1160 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) 1161 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) 1162 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) 1163 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) 1164 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) 1165 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) 1166 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) 1167 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) 1168 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) 1169 * @sclk: GPU clock Mhz (core bandwidth depends of this clock) 1170 * @needed_bandwidth: current bandwidth needs 1171 * 1172 * It keeps track of various data needed to take powermanagement decision. 1173 * Bandwidth need is used to determine minimun clock of the GPU and memory. 1174 * Equation between gpu/memory clock and available bandwidth is hw dependent 1175 * (type of memory, bus size, efficiency, ...) 1176 */ 1177 1178 enum radeon_pm_method { 1179 PM_METHOD_PROFILE, 1180 PM_METHOD_DYNPM, 1181 PM_METHOD_DPM, 1182 }; 1183 1184 enum radeon_dynpm_state { 1185 DYNPM_STATE_DISABLED, 1186 DYNPM_STATE_MINIMUM, 1187 DYNPM_STATE_PAUSED, 1188 DYNPM_STATE_ACTIVE, 1189 DYNPM_STATE_SUSPENDED, 1190 }; 1191 enum radeon_dynpm_action { 1192 DYNPM_ACTION_NONE, 1193 DYNPM_ACTION_MINIMUM, 1194 DYNPM_ACTION_DOWNCLOCK, 1195 DYNPM_ACTION_UPCLOCK, 1196 DYNPM_ACTION_DEFAULT 1197 }; 1198 1199 enum radeon_voltage_type { 1200 VOLTAGE_NONE = 0, 1201 VOLTAGE_GPIO, 1202 VOLTAGE_VDDC, 1203 VOLTAGE_SW 1204 }; 1205 1206 enum radeon_pm_state_type { 1207 /* not used for dpm */ 1208 POWER_STATE_TYPE_DEFAULT, 1209 POWER_STATE_TYPE_POWERSAVE, 1210 /* user selectable states */ 1211 POWER_STATE_TYPE_BATTERY, 1212 POWER_STATE_TYPE_BALANCED, 1213 POWER_STATE_TYPE_PERFORMANCE, 1214 /* internal states */ 1215 POWER_STATE_TYPE_INTERNAL_UVD, 1216 POWER_STATE_TYPE_INTERNAL_UVD_SD, 1217 POWER_STATE_TYPE_INTERNAL_UVD_HD, 1218 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 1219 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 1220 POWER_STATE_TYPE_INTERNAL_BOOT, 1221 POWER_STATE_TYPE_INTERNAL_THERMAL, 1222 POWER_STATE_TYPE_INTERNAL_ACPI, 1223 POWER_STATE_TYPE_INTERNAL_ULV, 1224 POWER_STATE_TYPE_INTERNAL_3DPERF, 1225 }; 1226 1227 enum radeon_pm_profile_type { 1228 PM_PROFILE_DEFAULT, 1229 PM_PROFILE_AUTO, 1230 PM_PROFILE_LOW, 1231 PM_PROFILE_MID, 1232 PM_PROFILE_HIGH, 1233 }; 1234 1235 #define PM_PROFILE_DEFAULT_IDX 0 1236 #define PM_PROFILE_LOW_SH_IDX 1 1237 #define PM_PROFILE_MID_SH_IDX 2 1238 #define PM_PROFILE_HIGH_SH_IDX 3 1239 #define PM_PROFILE_LOW_MH_IDX 4 1240 #define PM_PROFILE_MID_MH_IDX 5 1241 #define PM_PROFILE_HIGH_MH_IDX 6 1242 #define PM_PROFILE_MAX 7 1243 1244 struct radeon_pm_profile { 1245 int dpms_off_ps_idx; 1246 int dpms_on_ps_idx; 1247 int dpms_off_cm_idx; 1248 int dpms_on_cm_idx; 1249 }; 1250 1251 enum radeon_int_thermal_type { 1252 THERMAL_TYPE_NONE, 1253 THERMAL_TYPE_EXTERNAL, 1254 THERMAL_TYPE_EXTERNAL_GPIO, 1255 THERMAL_TYPE_RV6XX, 1256 THERMAL_TYPE_RV770, 1257 THERMAL_TYPE_ADT7473_WITH_INTERNAL, 1258 THERMAL_TYPE_EVERGREEN, 1259 THERMAL_TYPE_SUMO, 1260 THERMAL_TYPE_NI, 1261 THERMAL_TYPE_SI, 1262 THERMAL_TYPE_EMC2103_WITH_INTERNAL, 1263 THERMAL_TYPE_CI, 1264 THERMAL_TYPE_KV, 1265 }; 1266 1267 struct radeon_voltage { 1268 enum radeon_voltage_type type; 1269 /* gpio voltage */ 1270 struct radeon_gpio_rec gpio; 1271 u32 delay; /* delay in usec from voltage drop to sclk change */ 1272 bool active_high; /* voltage drop is active when bit is high */ 1273 /* VDDC voltage */ 1274 u8 vddc_id; /* index into vddc voltage table */ 1275 u8 vddci_id; /* index into vddci voltage table */ 1276 bool vddci_enabled; 1277 /* r6xx+ sw */ 1278 u16 voltage; 1279 /* evergreen+ vddci */ 1280 u16 vddci; 1281 }; 1282 1283 /* clock mode flags */ 1284 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) 1285 1286 struct radeon_pm_clock_info { 1287 /* memory clock */ 1288 u32 mclk; 1289 /* engine clock */ 1290 u32 sclk; 1291 /* voltage info */ 1292 struct radeon_voltage voltage; 1293 /* standardized clock flags */ 1294 u32 flags; 1295 }; 1296 1297 /* state flags */ 1298 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) 1299 1300 struct radeon_power_state { 1301 enum radeon_pm_state_type type; 1302 struct radeon_pm_clock_info *clock_info; 1303 /* number of valid clock modes in this power state */ 1304 int num_clock_modes; 1305 struct radeon_pm_clock_info *default_clock_mode; 1306 /* standardized state flags */ 1307 u32 flags; 1308 u32 misc; /* vbios specific flags */ 1309 u32 misc2; /* vbios specific flags */ 1310 int pcie_lanes; /* pcie lanes */ 1311 }; 1312 1313 /* 1314 * Some modes are overclocked by very low value, accept them 1315 */ 1316 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ 1317 1318 enum radeon_dpm_auto_throttle_src { 1319 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, 1320 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL 1321 }; 1322 1323 enum radeon_dpm_event_src { 1324 RADEON_DPM_EVENT_SRC_ANALOG = 0, 1325 RADEON_DPM_EVENT_SRC_EXTERNAL = 1, 1326 RADEON_DPM_EVENT_SRC_DIGITAL = 2, 1327 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, 1328 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 1329 }; 1330 1331 #define RADEON_MAX_VCE_LEVELS 6 1332 1333 enum radeon_vce_level { 1334 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 1335 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 1336 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 1337 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 1338 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 1339 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 1340 }; 1341 1342 struct radeon_ps { 1343 u32 caps; /* vbios flags */ 1344 u32 class; /* vbios flags */ 1345 u32 class2; /* vbios flags */ 1346 /* UVD clocks */ 1347 u32 vclk; 1348 u32 dclk; 1349 /* VCE clocks */ 1350 u32 evclk; 1351 u32 ecclk; 1352 bool vce_active; 1353 enum radeon_vce_level vce_level; 1354 /* asic priv */ 1355 void *ps_priv; 1356 }; 1357 1358 struct radeon_dpm_thermal { 1359 /* thermal interrupt work */ 1360 struct work_struct work; 1361 /* low temperature threshold */ 1362 int min_temp; 1363 /* high temperature threshold */ 1364 int max_temp; 1365 /* was interrupt low to high or high to low */ 1366 bool high_to_low; 1367 }; 1368 1369 enum radeon_clk_action 1370 { 1371 RADEON_SCLK_UP = 1, 1372 RADEON_SCLK_DOWN 1373 }; 1374 1375 struct radeon_blacklist_clocks 1376 { 1377 u32 sclk; 1378 u32 mclk; 1379 enum radeon_clk_action action; 1380 }; 1381 1382 struct radeon_clock_and_voltage_limits { 1383 u32 sclk; 1384 u32 mclk; 1385 u16 vddc; 1386 u16 vddci; 1387 }; 1388 1389 struct radeon_clock_array { 1390 u32 count; 1391 u32 *values; 1392 }; 1393 1394 struct radeon_clock_voltage_dependency_entry { 1395 u32 clk; 1396 u16 v; 1397 }; 1398 1399 struct radeon_clock_voltage_dependency_table { 1400 u32 count; 1401 struct radeon_clock_voltage_dependency_entry *entries; 1402 }; 1403 1404 union radeon_cac_leakage_entry { 1405 struct { 1406 u16 vddc; 1407 u32 leakage; 1408 }; 1409 struct { 1410 u16 vddc1; 1411 u16 vddc2; 1412 u16 vddc3; 1413 }; 1414 }; 1415 1416 struct radeon_cac_leakage_table { 1417 u32 count; 1418 union radeon_cac_leakage_entry *entries; 1419 }; 1420 1421 struct radeon_phase_shedding_limits_entry { 1422 u16 voltage; 1423 u32 sclk; 1424 u32 mclk; 1425 }; 1426 1427 struct radeon_phase_shedding_limits_table { 1428 u32 count; 1429 struct radeon_phase_shedding_limits_entry *entries; 1430 }; 1431 1432 struct radeon_uvd_clock_voltage_dependency_entry { 1433 u32 vclk; 1434 u32 dclk; 1435 u16 v; 1436 }; 1437 1438 struct radeon_uvd_clock_voltage_dependency_table { 1439 u8 count; 1440 struct radeon_uvd_clock_voltage_dependency_entry *entries; 1441 }; 1442 1443 struct radeon_vce_clock_voltage_dependency_entry { 1444 u32 ecclk; 1445 u32 evclk; 1446 u16 v; 1447 }; 1448 1449 struct radeon_vce_clock_voltage_dependency_table { 1450 u8 count; 1451 struct radeon_vce_clock_voltage_dependency_entry *entries; 1452 }; 1453 1454 struct radeon_ppm_table { 1455 u8 ppm_design; 1456 u16 cpu_core_number; 1457 u32 platform_tdp; 1458 u32 small_ac_platform_tdp; 1459 u32 platform_tdc; 1460 u32 small_ac_platform_tdc; 1461 u32 apu_tdp; 1462 u32 dgpu_tdp; 1463 u32 dgpu_ulv_power; 1464 u32 tj_max; 1465 }; 1466 1467 struct radeon_cac_tdp_table { 1468 u16 tdp; 1469 u16 configurable_tdp; 1470 u16 tdc; 1471 u16 battery_power_limit; 1472 u16 small_power_limit; 1473 u16 low_cac_leakage; 1474 u16 high_cac_leakage; 1475 u16 maximum_power_delivery_limit; 1476 }; 1477 1478 struct radeon_dpm_dynamic_state { 1479 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk; 1480 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk; 1481 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk; 1482 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk; 1483 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk; 1484 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; 1485 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; 1486 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table; 1487 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table; 1488 struct radeon_clock_array valid_sclk_values; 1489 struct radeon_clock_array valid_mclk_values; 1490 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc; 1491 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac; 1492 u32 mclk_sclk_ratio; 1493 u32 sclk_mclk_delta; 1494 u16 vddc_vddci_delta; 1495 u16 min_vddc_for_pcie_gen2; 1496 struct radeon_cac_leakage_table cac_leakage_table; 1497 struct radeon_phase_shedding_limits_table phase_shedding_limits_table; 1498 struct radeon_ppm_table *ppm_table; 1499 struct radeon_cac_tdp_table *cac_tdp_table; 1500 }; 1501 1502 struct radeon_dpm_fan { 1503 u16 t_min; 1504 u16 t_med; 1505 u16 t_high; 1506 u16 pwm_min; 1507 u16 pwm_med; 1508 u16 pwm_high; 1509 u8 t_hyst; 1510 u32 cycle_delay; 1511 u16 t_max; 1512 u8 control_mode; 1513 u16 default_max_fan_pwm; 1514 u16 default_fan_output_sensitivity; 1515 u16 fan_output_sensitivity; 1516 bool ucode_fan_control; 1517 }; 1518 1519 enum radeon_pcie_gen { 1520 RADEON_PCIE_GEN1 = 0, 1521 RADEON_PCIE_GEN2 = 1, 1522 RADEON_PCIE_GEN3 = 2, 1523 RADEON_PCIE_GEN_INVALID = 0xffff 1524 }; 1525 1526 enum radeon_dpm_forced_level { 1527 RADEON_DPM_FORCED_LEVEL_AUTO = 0, 1528 RADEON_DPM_FORCED_LEVEL_LOW = 1, 1529 RADEON_DPM_FORCED_LEVEL_HIGH = 2, 1530 }; 1531 1532 struct radeon_vce_state { 1533 /* vce clocks */ 1534 u32 evclk; 1535 u32 ecclk; 1536 /* gpu clocks */ 1537 u32 sclk; 1538 u32 mclk; 1539 u8 clk_idx; 1540 u8 pstate; 1541 }; 1542 1543 struct radeon_dpm { 1544 struct radeon_ps *ps; 1545 /* number of valid power states */ 1546 int num_ps; 1547 /* current power state that is active */ 1548 struct radeon_ps *current_ps; 1549 /* requested power state */ 1550 struct radeon_ps *requested_ps; 1551 /* boot up power state */ 1552 struct radeon_ps *boot_ps; 1553 /* default uvd power state */ 1554 struct radeon_ps *uvd_ps; 1555 /* vce requirements */ 1556 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS]; 1557 enum radeon_vce_level vce_level; 1558 enum radeon_pm_state_type state; 1559 enum radeon_pm_state_type user_state; 1560 u32 platform_caps; 1561 u32 voltage_response_time; 1562 u32 backbias_response_time; 1563 void *priv; 1564 u32 new_active_crtcs; 1565 int new_active_crtc_count; 1566 u32 current_active_crtcs; 1567 int current_active_crtc_count; 1568 struct radeon_dpm_dynamic_state dyn_state; 1569 struct radeon_dpm_fan fan; 1570 u32 tdp_limit; 1571 u32 near_tdp_limit; 1572 u32 near_tdp_limit_adjusted; 1573 u32 sq_ramping_threshold; 1574 u32 cac_leakage; 1575 u16 tdp_od_limit; 1576 u32 tdp_adjustment; 1577 u16 load_line_slope; 1578 bool power_control; 1579 bool ac_power; 1580 /* special states active */ 1581 bool thermal_active; 1582 bool uvd_active; 1583 bool vce_active; 1584 /* thermal handling */ 1585 struct radeon_dpm_thermal thermal; 1586 /* forced levels */ 1587 enum radeon_dpm_forced_level forced_level; 1588 /* track UVD streams */ 1589 unsigned sd; 1590 unsigned hd; 1591 }; 1592 1593 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable); 1594 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable); 1595 1596 struct radeon_pm { 1597 struct mutex mutex; 1598 /* write locked while reprogramming mclk */ 1599 struct rw_semaphore mclk_lock; 1600 u32 active_crtcs; 1601 int active_crtc_count; 1602 int req_vblank; 1603 bool vblank_sync; 1604 fixed20_12 max_bandwidth; 1605 fixed20_12 igp_sideport_mclk; 1606 fixed20_12 igp_system_mclk; 1607 fixed20_12 igp_ht_link_clk; 1608 fixed20_12 igp_ht_link_width; 1609 fixed20_12 k8_bandwidth; 1610 fixed20_12 sideport_bandwidth; 1611 fixed20_12 ht_bandwidth; 1612 fixed20_12 core_bandwidth; 1613 fixed20_12 sclk; 1614 fixed20_12 mclk; 1615 fixed20_12 needed_bandwidth; 1616 struct radeon_power_state *power_state; 1617 /* number of valid power states */ 1618 int num_power_states; 1619 int current_power_state_index; 1620 int current_clock_mode_index; 1621 int requested_power_state_index; 1622 int requested_clock_mode_index; 1623 int default_power_state_index; 1624 u32 current_sclk; 1625 u32 current_mclk; 1626 u16 current_vddc; 1627 u16 current_vddci; 1628 u32 default_sclk; 1629 u32 default_mclk; 1630 u16 default_vddc; 1631 u16 default_vddci; 1632 struct radeon_i2c_chan *i2c_bus; 1633 /* selected pm method */ 1634 enum radeon_pm_method pm_method; 1635 /* dynpm power management */ 1636 struct delayed_work dynpm_idle_work; 1637 enum radeon_dynpm_state dynpm_state; 1638 enum radeon_dynpm_action dynpm_planned_action; 1639 unsigned long dynpm_action_timeout; 1640 bool dynpm_can_upclock; 1641 bool dynpm_can_downclock; 1642 /* profile-based power management */ 1643 enum radeon_pm_profile_type profile; 1644 int profile_index; 1645 struct radeon_pm_profile profiles[PM_PROFILE_MAX]; 1646 /* internal thermal controller on rv6xx+ */ 1647 enum radeon_int_thermal_type int_thermal_type; 1648 struct device *int_hwmon_dev; 1649 /* fan control parameters */ 1650 bool no_fan; 1651 u8 fan_pulses_per_revolution; 1652 u8 fan_min_rpm; 1653 u8 fan_max_rpm; 1654 /* dpm */ 1655 bool dpm_enabled; 1656 struct radeon_dpm dpm; 1657 }; 1658 1659 int radeon_pm_get_type_index(struct radeon_device *rdev, 1660 enum radeon_pm_state_type ps_type, 1661 int instance); 1662 /* 1663 * UVD 1664 */ 1665 #define RADEON_MAX_UVD_HANDLES 10 1666 #define RADEON_UVD_STACK_SIZE (1024*1024) 1667 #define RADEON_UVD_HEAP_SIZE (1024*1024) 1668 1669 struct radeon_uvd { 1670 struct radeon_bo *vcpu_bo; 1671 void *cpu_addr; 1672 uint64_t gpu_addr; 1673 void *saved_bo; 1674 atomic_t handles[RADEON_MAX_UVD_HANDLES]; 1675 struct drm_file *filp[RADEON_MAX_UVD_HANDLES]; 1676 unsigned img_size[RADEON_MAX_UVD_HANDLES]; 1677 struct delayed_work idle_work; 1678 }; 1679 1680 int radeon_uvd_init(struct radeon_device *rdev); 1681 void radeon_uvd_fini(struct radeon_device *rdev); 1682 int radeon_uvd_suspend(struct radeon_device *rdev); 1683 int radeon_uvd_resume(struct radeon_device *rdev); 1684 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring, 1685 uint32_t handle, struct radeon_fence **fence); 1686 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring, 1687 uint32_t handle, struct radeon_fence **fence); 1688 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo, 1689 uint32_t allowed_domains); 1690 void radeon_uvd_free_handles(struct radeon_device *rdev, 1691 struct drm_file *filp); 1692 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser); 1693 void radeon_uvd_note_usage(struct radeon_device *rdev); 1694 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev, 1695 unsigned vclk, unsigned dclk, 1696 unsigned vco_min, unsigned vco_max, 1697 unsigned fb_factor, unsigned fb_mask, 1698 unsigned pd_min, unsigned pd_max, 1699 unsigned pd_even, 1700 unsigned *optimal_fb_div, 1701 unsigned *optimal_vclk_div, 1702 unsigned *optimal_dclk_div); 1703 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev, 1704 unsigned cg_upll_func_cntl); 1705 1706 /* 1707 * VCE 1708 */ 1709 #define RADEON_MAX_VCE_HANDLES 16 1710 #define RADEON_VCE_STACK_SIZE (1024*1024) 1711 #define RADEON_VCE_HEAP_SIZE (4*1024*1024) 1712 1713 struct radeon_vce { 1714 struct radeon_bo *vcpu_bo; 1715 uint64_t gpu_addr; 1716 unsigned fw_version; 1717 unsigned fb_version; 1718 atomic_t handles[RADEON_MAX_VCE_HANDLES]; 1719 struct drm_file *filp[RADEON_MAX_VCE_HANDLES]; 1720 unsigned img_size[RADEON_MAX_VCE_HANDLES]; 1721 struct delayed_work idle_work; 1722 }; 1723 1724 int radeon_vce_init(struct radeon_device *rdev); 1725 void radeon_vce_fini(struct radeon_device *rdev); 1726 int radeon_vce_suspend(struct radeon_device *rdev); 1727 int radeon_vce_resume(struct radeon_device *rdev); 1728 int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring, 1729 uint32_t handle, struct radeon_fence **fence); 1730 int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring, 1731 uint32_t handle, struct radeon_fence **fence); 1732 void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp); 1733 void radeon_vce_note_usage(struct radeon_device *rdev); 1734 int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size); 1735 int radeon_vce_cs_parse(struct radeon_cs_parser *p); 1736 bool radeon_vce_semaphore_emit(struct radeon_device *rdev, 1737 struct radeon_ring *ring, 1738 struct radeon_semaphore *semaphore, 1739 bool emit_wait); 1740 void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 1741 void radeon_vce_fence_emit(struct radeon_device *rdev, 1742 struct radeon_fence *fence); 1743 int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); 1744 int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 1745 1746 struct r600_audio_pin { 1747 int channels; 1748 int rate; 1749 int bits_per_sample; 1750 u8 status_bits; 1751 u8 category_code; 1752 u32 offset; 1753 bool connected; 1754 u32 id; 1755 }; 1756 1757 struct r600_audio { 1758 bool enabled; 1759 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS]; 1760 int num_pins; 1761 }; 1762 1763 /* 1764 * Benchmarking 1765 */ 1766 void radeon_benchmark(struct radeon_device *rdev, int test_number); 1767 1768 1769 /* 1770 * Testing 1771 */ 1772 void radeon_test_moves(struct radeon_device *rdev); 1773 void radeon_test_ring_sync(struct radeon_device *rdev, 1774 struct radeon_ring *cpA, 1775 struct radeon_ring *cpB); 1776 void radeon_test_syncing(struct radeon_device *rdev); 1777 1778 /* 1779 * MMU Notifier 1780 */ 1781 int radeon_mn_register(struct radeon_bo *bo, unsigned long addr); 1782 void radeon_mn_unregister(struct radeon_bo *bo); 1783 1784 /* 1785 * Debugfs 1786 */ 1787 struct radeon_debugfs { 1788 struct drm_info_list *files; 1789 unsigned num_files; 1790 }; 1791 1792 int radeon_debugfs_add_files(struct radeon_device *rdev, 1793 struct drm_info_list *files, 1794 unsigned nfiles); 1795 int radeon_debugfs_fence_init(struct radeon_device *rdev); 1796 1797 /* 1798 * ASIC ring specific functions. 1799 */ 1800 struct radeon_asic_ring { 1801 /* ring read/write ptr handling */ 1802 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1803 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1804 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1805 1806 /* validating and patching of IBs */ 1807 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib); 1808 int (*cs_parse)(struct radeon_cs_parser *p); 1809 1810 /* command emmit functions */ 1811 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); 1812 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence); 1813 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring); 1814 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp, 1815 struct radeon_semaphore *semaphore, bool emit_wait); 1816 void (*vm_flush)(struct radeon_device *rdev, struct radeon_ring *ring, 1817 unsigned vm_id, uint64_t pd_addr); 1818 1819 /* testing functions */ 1820 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1821 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1822 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); 1823 1824 /* deprecated */ 1825 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp); 1826 }; 1827 1828 /* 1829 * ASIC specific functions. 1830 */ 1831 struct radeon_asic { 1832 int (*init)(struct radeon_device *rdev); 1833 void (*fini)(struct radeon_device *rdev); 1834 int (*resume)(struct radeon_device *rdev); 1835 int (*suspend)(struct radeon_device *rdev); 1836 void (*vga_set_state)(struct radeon_device *rdev, bool state); 1837 int (*asic_reset)(struct radeon_device *rdev); 1838 /* Flush the HDP cache via MMIO */ 1839 void (*mmio_hdp_flush)(struct radeon_device *rdev); 1840 /* check if 3D engine is idle */ 1841 bool (*gui_idle)(struct radeon_device *rdev); 1842 /* wait for mc_idle */ 1843 int (*mc_wait_for_idle)(struct radeon_device *rdev); 1844 /* get the reference clock */ 1845 u32 (*get_xclk)(struct radeon_device *rdev); 1846 /* get the gpu clock counter */ 1847 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev); 1848 /* gart */ 1849 struct { 1850 void (*tlb_flush)(struct radeon_device *rdev); 1851 uint64_t (*get_page_entry)(uint64_t addr, uint32_t flags); 1852 void (*set_page)(struct radeon_device *rdev, unsigned i, 1853 uint64_t entry); 1854 } gart; 1855 struct { 1856 int (*init)(struct radeon_device *rdev); 1857 void (*fini)(struct radeon_device *rdev); 1858 void (*copy_pages)(struct radeon_device *rdev, 1859 struct radeon_ib *ib, 1860 uint64_t pe, uint64_t src, 1861 unsigned count); 1862 void (*write_pages)(struct radeon_device *rdev, 1863 struct radeon_ib *ib, 1864 uint64_t pe, 1865 uint64_t addr, unsigned count, 1866 uint32_t incr, uint32_t flags); 1867 void (*set_pages)(struct radeon_device *rdev, 1868 struct radeon_ib *ib, 1869 uint64_t pe, 1870 uint64_t addr, unsigned count, 1871 uint32_t incr, uint32_t flags); 1872 void (*pad_ib)(struct radeon_ib *ib); 1873 } vm; 1874 /* ring specific callbacks */ 1875 struct radeon_asic_ring *ring[RADEON_NUM_RINGS]; 1876 /* irqs */ 1877 struct { 1878 int (*set)(struct radeon_device *rdev); 1879 int (*process)(struct radeon_device *rdev); 1880 } irq; 1881 /* displays */ 1882 struct { 1883 /* display watermarks */ 1884 void (*bandwidth_update)(struct radeon_device *rdev); 1885 /* get frame count */ 1886 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); 1887 /* wait for vblank */ 1888 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc); 1889 /* set backlight level */ 1890 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level); 1891 /* get backlight level */ 1892 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder); 1893 /* audio callbacks */ 1894 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable); 1895 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode); 1896 } display; 1897 /* copy functions for bo handling */ 1898 struct { 1899 struct radeon_fence *(*blit)(struct radeon_device *rdev, 1900 uint64_t src_offset, 1901 uint64_t dst_offset, 1902 unsigned num_gpu_pages, 1903 struct reservation_object *resv); 1904 u32 blit_ring_index; 1905 struct radeon_fence *(*dma)(struct radeon_device *rdev, 1906 uint64_t src_offset, 1907 uint64_t dst_offset, 1908 unsigned num_gpu_pages, 1909 struct reservation_object *resv); 1910 u32 dma_ring_index; 1911 /* method used for bo copy */ 1912 struct radeon_fence *(*copy)(struct radeon_device *rdev, 1913 uint64_t src_offset, 1914 uint64_t dst_offset, 1915 unsigned num_gpu_pages, 1916 struct reservation_object *resv); 1917 /* ring used for bo copies */ 1918 u32 copy_ring_index; 1919 } copy; 1920 /* surfaces */ 1921 struct { 1922 int (*set_reg)(struct radeon_device *rdev, int reg, 1923 uint32_t tiling_flags, uint32_t pitch, 1924 uint32_t offset, uint32_t obj_size); 1925 void (*clear_reg)(struct radeon_device *rdev, int reg); 1926 } surface; 1927 /* hotplug detect */ 1928 struct { 1929 void (*init)(struct radeon_device *rdev); 1930 void (*fini)(struct radeon_device *rdev); 1931 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1932 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1933 } hpd; 1934 /* static power management */ 1935 struct { 1936 void (*misc)(struct radeon_device *rdev); 1937 void (*prepare)(struct radeon_device *rdev); 1938 void (*finish)(struct radeon_device *rdev); 1939 void (*init_profile)(struct radeon_device *rdev); 1940 void (*get_dynpm_state)(struct radeon_device *rdev); 1941 uint32_t (*get_engine_clock)(struct radeon_device *rdev); 1942 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); 1943 uint32_t (*get_memory_clock)(struct radeon_device *rdev); 1944 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); 1945 int (*get_pcie_lanes)(struct radeon_device *rdev); 1946 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); 1947 void (*set_clock_gating)(struct radeon_device *rdev, int enable); 1948 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk); 1949 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk); 1950 int (*get_temperature)(struct radeon_device *rdev); 1951 } pm; 1952 /* dynamic power management */ 1953 struct { 1954 int (*init)(struct radeon_device *rdev); 1955 void (*setup_asic)(struct radeon_device *rdev); 1956 int (*enable)(struct radeon_device *rdev); 1957 int (*late_enable)(struct radeon_device *rdev); 1958 void (*disable)(struct radeon_device *rdev); 1959 int (*pre_set_power_state)(struct radeon_device *rdev); 1960 int (*set_power_state)(struct radeon_device *rdev); 1961 void (*post_set_power_state)(struct radeon_device *rdev); 1962 void (*display_configuration_changed)(struct radeon_device *rdev); 1963 void (*fini)(struct radeon_device *rdev); 1964 u32 (*get_sclk)(struct radeon_device *rdev, bool low); 1965 u32 (*get_mclk)(struct radeon_device *rdev, bool low); 1966 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps); 1967 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m); 1968 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level); 1969 bool (*vblank_too_short)(struct radeon_device *rdev); 1970 void (*powergate_uvd)(struct radeon_device *rdev, bool gate); 1971 void (*enable_bapm)(struct radeon_device *rdev, bool enable); 1972 } dpm; 1973 /* pageflipping */ 1974 struct { 1975 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base); 1976 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc); 1977 } pflip; 1978 }; 1979 1980 /* 1981 * Asic structures 1982 */ 1983 struct r100_asic { 1984 const unsigned *reg_safe_bm; 1985 unsigned reg_safe_bm_size; 1986 u32 hdp_cntl; 1987 }; 1988 1989 struct r300_asic { 1990 const unsigned *reg_safe_bm; 1991 unsigned reg_safe_bm_size; 1992 u32 resync_scratch; 1993 u32 hdp_cntl; 1994 }; 1995 1996 struct r600_asic { 1997 unsigned max_pipes; 1998 unsigned max_tile_pipes; 1999 unsigned max_simds; 2000 unsigned max_backends; 2001 unsigned max_gprs; 2002 unsigned max_threads; 2003 unsigned max_stack_entries; 2004 unsigned max_hw_contexts; 2005 unsigned max_gs_threads; 2006 unsigned sx_max_export_size; 2007 unsigned sx_max_export_pos_size; 2008 unsigned sx_max_export_smx_size; 2009 unsigned sq_num_cf_insts; 2010 unsigned tiling_nbanks; 2011 unsigned tiling_npipes; 2012 unsigned tiling_group_size; 2013 unsigned tile_config; 2014 unsigned backend_map; 2015 unsigned active_simds; 2016 }; 2017 2018 struct rv770_asic { 2019 unsigned max_pipes; 2020 unsigned max_tile_pipes; 2021 unsigned max_simds; 2022 unsigned max_backends; 2023 unsigned max_gprs; 2024 unsigned max_threads; 2025 unsigned max_stack_entries; 2026 unsigned max_hw_contexts; 2027 unsigned max_gs_threads; 2028 unsigned sx_max_export_size; 2029 unsigned sx_max_export_pos_size; 2030 unsigned sx_max_export_smx_size; 2031 unsigned sq_num_cf_insts; 2032 unsigned sx_num_of_sets; 2033 unsigned sc_prim_fifo_size; 2034 unsigned sc_hiz_tile_fifo_size; 2035 unsigned sc_earlyz_tile_fifo_fize; 2036 unsigned tiling_nbanks; 2037 unsigned tiling_npipes; 2038 unsigned tiling_group_size; 2039 unsigned tile_config; 2040 unsigned backend_map; 2041 unsigned active_simds; 2042 }; 2043 2044 struct evergreen_asic { 2045 unsigned num_ses; 2046 unsigned max_pipes; 2047 unsigned max_tile_pipes; 2048 unsigned max_simds; 2049 unsigned max_backends; 2050 unsigned max_gprs; 2051 unsigned max_threads; 2052 unsigned max_stack_entries; 2053 unsigned max_hw_contexts; 2054 unsigned max_gs_threads; 2055 unsigned sx_max_export_size; 2056 unsigned sx_max_export_pos_size; 2057 unsigned sx_max_export_smx_size; 2058 unsigned sq_num_cf_insts; 2059 unsigned sx_num_of_sets; 2060 unsigned sc_prim_fifo_size; 2061 unsigned sc_hiz_tile_fifo_size; 2062 unsigned sc_earlyz_tile_fifo_size; 2063 unsigned tiling_nbanks; 2064 unsigned tiling_npipes; 2065 unsigned tiling_group_size; 2066 unsigned tile_config; 2067 unsigned backend_map; 2068 unsigned active_simds; 2069 }; 2070 2071 struct cayman_asic { 2072 unsigned max_shader_engines; 2073 unsigned max_pipes_per_simd; 2074 unsigned max_tile_pipes; 2075 unsigned max_simds_per_se; 2076 unsigned max_backends_per_se; 2077 unsigned max_texture_channel_caches; 2078 unsigned max_gprs; 2079 unsigned max_threads; 2080 unsigned max_gs_threads; 2081 unsigned max_stack_entries; 2082 unsigned sx_num_of_sets; 2083 unsigned sx_max_export_size; 2084 unsigned sx_max_export_pos_size; 2085 unsigned sx_max_export_smx_size; 2086 unsigned max_hw_contexts; 2087 unsigned sq_num_cf_insts; 2088 unsigned sc_prim_fifo_size; 2089 unsigned sc_hiz_tile_fifo_size; 2090 unsigned sc_earlyz_tile_fifo_size; 2091 2092 unsigned num_shader_engines; 2093 unsigned num_shader_pipes_per_simd; 2094 unsigned num_tile_pipes; 2095 unsigned num_simds_per_se; 2096 unsigned num_backends_per_se; 2097 unsigned backend_disable_mask_per_asic; 2098 unsigned backend_map; 2099 unsigned num_texture_channel_caches; 2100 unsigned mem_max_burst_length_bytes; 2101 unsigned mem_row_size_in_kb; 2102 unsigned shader_engine_tile_size; 2103 unsigned num_gpus; 2104 unsigned multi_gpu_tile_size; 2105 2106 unsigned tile_config; 2107 unsigned active_simds; 2108 }; 2109 2110 struct si_asic { 2111 unsigned max_shader_engines; 2112 unsigned max_tile_pipes; 2113 unsigned max_cu_per_sh; 2114 unsigned max_sh_per_se; 2115 unsigned max_backends_per_se; 2116 unsigned max_texture_channel_caches; 2117 unsigned max_gprs; 2118 unsigned max_gs_threads; 2119 unsigned max_hw_contexts; 2120 unsigned sc_prim_fifo_size_frontend; 2121 unsigned sc_prim_fifo_size_backend; 2122 unsigned sc_hiz_tile_fifo_size; 2123 unsigned sc_earlyz_tile_fifo_size; 2124 2125 unsigned num_tile_pipes; 2126 unsigned backend_enable_mask; 2127 unsigned backend_disable_mask_per_asic; 2128 unsigned backend_map; 2129 unsigned num_texture_channel_caches; 2130 unsigned mem_max_burst_length_bytes; 2131 unsigned mem_row_size_in_kb; 2132 unsigned shader_engine_tile_size; 2133 unsigned num_gpus; 2134 unsigned multi_gpu_tile_size; 2135 2136 unsigned tile_config; 2137 uint32_t tile_mode_array[32]; 2138 uint32_t active_cus; 2139 }; 2140 2141 struct cik_asic { 2142 unsigned max_shader_engines; 2143 unsigned max_tile_pipes; 2144 unsigned max_cu_per_sh; 2145 unsigned max_sh_per_se; 2146 unsigned max_backends_per_se; 2147 unsigned max_texture_channel_caches; 2148 unsigned max_gprs; 2149 unsigned max_gs_threads; 2150 unsigned max_hw_contexts; 2151 unsigned sc_prim_fifo_size_frontend; 2152 unsigned sc_prim_fifo_size_backend; 2153 unsigned sc_hiz_tile_fifo_size; 2154 unsigned sc_earlyz_tile_fifo_size; 2155 2156 unsigned num_tile_pipes; 2157 unsigned backend_enable_mask; 2158 unsigned backend_disable_mask_per_asic; 2159 unsigned backend_map; 2160 unsigned num_texture_channel_caches; 2161 unsigned mem_max_burst_length_bytes; 2162 unsigned mem_row_size_in_kb; 2163 unsigned shader_engine_tile_size; 2164 unsigned num_gpus; 2165 unsigned multi_gpu_tile_size; 2166 2167 unsigned tile_config; 2168 uint32_t tile_mode_array[32]; 2169 uint32_t macrotile_mode_array[16]; 2170 uint32_t active_cus; 2171 }; 2172 2173 union radeon_asic_config { 2174 struct r300_asic r300; 2175 struct r100_asic r100; 2176 struct r600_asic r600; 2177 struct rv770_asic rv770; 2178 struct evergreen_asic evergreen; 2179 struct cayman_asic cayman; 2180 struct si_asic si; 2181 struct cik_asic cik; 2182 }; 2183 2184 /* 2185 * asic initizalization from radeon_asic.c 2186 */ 2187 void radeon_agp_disable(struct radeon_device *rdev); 2188 int radeon_asic_init(struct radeon_device *rdev); 2189 2190 2191 /* 2192 * IOCTL. 2193 */ 2194 int radeon_gem_info_ioctl(struct drm_device *dev, void *data, 2195 struct drm_file *filp); 2196 int radeon_gem_create_ioctl(struct drm_device *dev, void *data, 2197 struct drm_file *filp); 2198 int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data, 2199 struct drm_file *filp); 2200 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, 2201 struct drm_file *file_priv); 2202 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, 2203 struct drm_file *file_priv); 2204 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, 2205 struct drm_file *file_priv); 2206 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, 2207 struct drm_file *file_priv); 2208 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, 2209 struct drm_file *filp); 2210 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, 2211 struct drm_file *filp); 2212 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, 2213 struct drm_file *filp); 2214 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 2215 struct drm_file *filp); 2216 int radeon_gem_va_ioctl(struct drm_device *dev, void *data, 2217 struct drm_file *filp); 2218 int radeon_gem_op_ioctl(struct drm_device *dev, void *data, 2219 struct drm_file *filp); 2220 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 2221 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, 2222 struct drm_file *filp); 2223 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, 2224 struct drm_file *filp); 2225 2226 /* VRAM scratch page for HDP bug, default vram page */ 2227 struct r600_vram_scratch { 2228 struct radeon_bo *robj; 2229 volatile uint32_t *ptr; 2230 u64 gpu_addr; 2231 }; 2232 2233 /* 2234 * ACPI 2235 */ 2236 struct radeon_atif_notification_cfg { 2237 bool enabled; 2238 int command_code; 2239 }; 2240 2241 struct radeon_atif_notifications { 2242 bool display_switch; 2243 bool expansion_mode_change; 2244 bool thermal_state; 2245 bool forced_power_state; 2246 bool system_power_state; 2247 bool display_conf_change; 2248 bool px_gfx_switch; 2249 bool brightness_change; 2250 bool dgpu_display_event; 2251 }; 2252 2253 struct radeon_atif_functions { 2254 bool system_params; 2255 bool sbios_requests; 2256 bool select_active_disp; 2257 bool lid_state; 2258 bool get_tv_standard; 2259 bool set_tv_standard; 2260 bool get_panel_expansion_mode; 2261 bool set_panel_expansion_mode; 2262 bool temperature_change; 2263 bool graphics_device_types; 2264 }; 2265 2266 struct radeon_atif { 2267 struct radeon_atif_notifications notifications; 2268 struct radeon_atif_functions functions; 2269 struct radeon_atif_notification_cfg notification_cfg; 2270 struct radeon_encoder *encoder_for_bl; 2271 }; 2272 2273 struct radeon_atcs_functions { 2274 bool get_ext_state; 2275 bool pcie_perf_req; 2276 bool pcie_dev_rdy; 2277 bool pcie_bus_width; 2278 }; 2279 2280 struct radeon_atcs { 2281 struct radeon_atcs_functions functions; 2282 }; 2283 2284 /* 2285 * Core structure, functions and helpers. 2286 */ 2287 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); 2288 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); 2289 2290 struct radeon_device { 2291 struct device *dev; 2292 struct drm_device *ddev; 2293 struct pci_dev *pdev; 2294 struct rw_semaphore exclusive_lock; 2295 /* ASIC */ 2296 union radeon_asic_config config; 2297 enum radeon_family family; 2298 unsigned long flags; 2299 int usec_timeout; 2300 enum radeon_pll_errata pll_errata; 2301 int num_gb_pipes; 2302 int num_z_pipes; 2303 int disp_priority; 2304 /* BIOS */ 2305 uint8_t *bios; 2306 bool is_atom_bios; 2307 uint16_t bios_header_start; 2308 struct radeon_bo *stollen_vga_memory; 2309 /* Register mmio */ 2310 resource_size_t rmmio_base; 2311 resource_size_t rmmio_size; 2312 /* protects concurrent MM_INDEX/DATA based register access */ 2313 spinlock_t mmio_idx_lock; 2314 /* protects concurrent SMC based register access */ 2315 spinlock_t smc_idx_lock; 2316 /* protects concurrent PLL register access */ 2317 spinlock_t pll_idx_lock; 2318 /* protects concurrent MC register access */ 2319 spinlock_t mc_idx_lock; 2320 /* protects concurrent PCIE register access */ 2321 spinlock_t pcie_idx_lock; 2322 /* protects concurrent PCIE_PORT register access */ 2323 spinlock_t pciep_idx_lock; 2324 /* protects concurrent PIF register access */ 2325 spinlock_t pif_idx_lock; 2326 /* protects concurrent CG register access */ 2327 spinlock_t cg_idx_lock; 2328 /* protects concurrent UVD register access */ 2329 spinlock_t uvd_idx_lock; 2330 /* protects concurrent RCU register access */ 2331 spinlock_t rcu_idx_lock; 2332 /* protects concurrent DIDT register access */ 2333 spinlock_t didt_idx_lock; 2334 /* protects concurrent ENDPOINT (audio) register access */ 2335 spinlock_t end_idx_lock; 2336 void __iomem *rmmio; 2337 radeon_rreg_t mc_rreg; 2338 radeon_wreg_t mc_wreg; 2339 radeon_rreg_t pll_rreg; 2340 radeon_wreg_t pll_wreg; 2341 uint32_t pcie_reg_mask; 2342 radeon_rreg_t pciep_rreg; 2343 radeon_wreg_t pciep_wreg; 2344 /* io port */ 2345 void __iomem *rio_mem; 2346 resource_size_t rio_mem_size; 2347 struct radeon_clock clock; 2348 struct radeon_mc mc; 2349 struct radeon_gart gart; 2350 struct radeon_mode_info mode_info; 2351 struct radeon_scratch scratch; 2352 struct radeon_doorbell doorbell; 2353 struct radeon_mman mman; 2354 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS]; 2355 wait_queue_head_t fence_queue; 2356 unsigned fence_context; 2357 struct mutex ring_lock; 2358 struct radeon_ring ring[RADEON_NUM_RINGS]; 2359 bool ib_pool_ready; 2360 struct radeon_sa_manager ring_tmp_bo; 2361 struct radeon_irq irq; 2362 struct radeon_asic *asic; 2363 struct radeon_gem gem; 2364 struct radeon_pm pm; 2365 struct radeon_uvd uvd; 2366 struct radeon_vce vce; 2367 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; 2368 struct radeon_wb wb; 2369 struct radeon_dummy_page dummy_page; 2370 bool shutdown; 2371 bool suspend; 2372 bool need_dma32; 2373 bool accel_working; 2374 bool fastfb_working; /* IGP feature*/ 2375 bool needs_reset, in_reset; 2376 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; 2377 const struct firmware *me_fw; /* all family ME firmware */ 2378 const struct firmware *pfp_fw; /* r6/700 PFP firmware */ 2379 const struct firmware *rlc_fw; /* r6/700 RLC firmware */ 2380 const struct firmware *mc_fw; /* NI MC firmware */ 2381 const struct firmware *ce_fw; /* SI CE firmware */ 2382 const struct firmware *mec_fw; /* CIK MEC firmware */ 2383 const struct firmware *mec2_fw; /* KV MEC2 firmware */ 2384 const struct firmware *sdma_fw; /* CIK SDMA firmware */ 2385 const struct firmware *smc_fw; /* SMC firmware */ 2386 const struct firmware *uvd_fw; /* UVD firmware */ 2387 const struct firmware *vce_fw; /* VCE firmware */ 2388 bool new_fw; 2389 struct r600_vram_scratch vram_scratch; 2390 int msi_enabled; /* msi enabled */ 2391 struct r600_ih ih; /* r6/700 interrupt ring */ 2392 struct radeon_rlc rlc; 2393 struct radeon_mec mec; 2394 struct work_struct hotplug_work; 2395 struct work_struct audio_work; 2396 int num_crtc; /* number of crtcs */ 2397 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ 2398 bool has_uvd; 2399 struct r600_audio audio; /* audio stuff */ 2400 struct notifier_block acpi_nb; 2401 /* only one userspace can use Hyperz features or CMASK at a time */ 2402 struct drm_file *hyperz_filp; 2403 struct drm_file *cmask_filp; 2404 /* i2c buses */ 2405 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; 2406 /* debugfs */ 2407 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS]; 2408 unsigned debugfs_count; 2409 /* virtual memory */ 2410 struct radeon_vm_manager vm_manager; 2411 struct mutex gpu_clock_mutex; 2412 /* memory stats */ 2413 atomic64_t vram_usage; 2414 atomic64_t gtt_usage; 2415 atomic64_t num_bytes_moved; 2416 /* ACPI interface */ 2417 struct radeon_atif atif; 2418 struct radeon_atcs atcs; 2419 /* srbm instance registers */ 2420 struct mutex srbm_mutex; 2421 /* GRBM index mutex. Protects concurrents access to GRBM index */ 2422 struct mutex grbm_idx_mutex; 2423 /* clock, powergating flags */ 2424 u32 cg_flags; 2425 u32 pg_flags; 2426 2427 struct dev_pm_domain vga_pm_domain; 2428 bool have_disp_power_ref; 2429 u32 px_quirk_flags; 2430 2431 /* tracking pinned memory */ 2432 u64 vram_pin_size; 2433 u64 gart_pin_size; 2434 2435 /* amdkfd interface */ 2436 struct kfd_dev *kfd; 2437 struct radeon_sa_manager kfd_bo; 2438 2439 struct mutex mn_lock; 2440 DECLARE_HASHTABLE(mn_hash, 7); 2441 }; 2442 2443 bool radeon_is_px(struct drm_device *dev); 2444 int radeon_device_init(struct radeon_device *rdev, 2445 struct drm_device *ddev, 2446 struct pci_dev *pdev, 2447 uint32_t flags); 2448 void radeon_device_fini(struct radeon_device *rdev); 2449 int radeon_gpu_wait_for_idle(struct radeon_device *rdev); 2450 2451 #define RADEON_MIN_MMIO_SIZE 0x10000 2452 2453 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, 2454 bool always_indirect) 2455 { 2456 /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */ 2457 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect) 2458 return readl(((void __iomem *)rdev->rmmio) + reg); 2459 else { 2460 unsigned long flags; 2461 uint32_t ret; 2462 2463 spin_lock_irqsave(&rdev->mmio_idx_lock, flags); 2464 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); 2465 ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); 2466 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); 2467 2468 return ret; 2469 } 2470 } 2471 2472 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, 2473 bool always_indirect) 2474 { 2475 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect) 2476 writel(v, ((void __iomem *)rdev->rmmio) + reg); 2477 else { 2478 unsigned long flags; 2479 2480 spin_lock_irqsave(&rdev->mmio_idx_lock, flags); 2481 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); 2482 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); 2483 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); 2484 } 2485 } 2486 2487 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg); 2488 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2489 2490 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index); 2491 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v); 2492 2493 /* 2494 * Cast helper 2495 */ 2496 extern const struct fence_ops radeon_fence_ops; 2497 2498 static inline struct radeon_fence *to_radeon_fence(struct fence *f) 2499 { 2500 struct radeon_fence *__f = container_of(f, struct radeon_fence, base); 2501 2502 if (__f->base.ops == &radeon_fence_ops) 2503 return __f; 2504 2505 return NULL; 2506 } 2507 2508 /* 2509 * Registers read & write functions. 2510 */ 2511 #define RREG8(reg) readb((rdev->rmmio) + (reg)) 2512 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg)) 2513 #define RREG16(reg) readw((rdev->rmmio) + (reg)) 2514 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg)) 2515 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false) 2516 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true) 2517 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false)) 2518 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false) 2519 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true) 2520 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2521 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2522 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) 2523 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) 2524 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) 2525 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) 2526 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) 2527 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) 2528 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg)) 2529 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) 2530 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg)) 2531 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v)) 2532 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg)) 2533 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v)) 2534 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg)) 2535 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v)) 2536 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg)) 2537 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v)) 2538 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg)) 2539 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v)) 2540 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg)) 2541 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v)) 2542 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg)) 2543 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v)) 2544 #define WREG32_P(reg, val, mask) \ 2545 do { \ 2546 uint32_t tmp_ = RREG32(reg); \ 2547 tmp_ &= (mask); \ 2548 tmp_ |= ((val) & ~(mask)); \ 2549 WREG32(reg, tmp_); \ 2550 } while (0) 2551 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 2552 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 2553 #define WREG32_PLL_P(reg, val, mask) \ 2554 do { \ 2555 uint32_t tmp_ = RREG32_PLL(reg); \ 2556 tmp_ &= (mask); \ 2557 tmp_ |= ((val) & ~(mask)); \ 2558 WREG32_PLL(reg, tmp_); \ 2559 } while (0) 2560 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false)) 2561 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) 2562 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) 2563 2564 #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index)) 2565 #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v)) 2566 2567 /* 2568 * Indirect registers accessor 2569 */ 2570 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) 2571 { 2572 unsigned long flags; 2573 uint32_t r; 2574 2575 spin_lock_irqsave(&rdev->pcie_idx_lock, flags); 2576 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 2577 r = RREG32(RADEON_PCIE_DATA); 2578 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags); 2579 return r; 2580 } 2581 2582 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 2583 { 2584 unsigned long flags; 2585 2586 spin_lock_irqsave(&rdev->pcie_idx_lock, flags); 2587 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 2588 WREG32(RADEON_PCIE_DATA, (v)); 2589 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags); 2590 } 2591 2592 static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg) 2593 { 2594 unsigned long flags; 2595 u32 r; 2596 2597 spin_lock_irqsave(&rdev->smc_idx_lock, flags); 2598 WREG32(TN_SMC_IND_INDEX_0, (reg)); 2599 r = RREG32(TN_SMC_IND_DATA_0); 2600 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); 2601 return r; 2602 } 2603 2604 static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2605 { 2606 unsigned long flags; 2607 2608 spin_lock_irqsave(&rdev->smc_idx_lock, flags); 2609 WREG32(TN_SMC_IND_INDEX_0, (reg)); 2610 WREG32(TN_SMC_IND_DATA_0, (v)); 2611 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); 2612 } 2613 2614 static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg) 2615 { 2616 unsigned long flags; 2617 u32 r; 2618 2619 spin_lock_irqsave(&rdev->rcu_idx_lock, flags); 2620 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); 2621 r = RREG32(R600_RCU_DATA); 2622 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags); 2623 return r; 2624 } 2625 2626 static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2627 { 2628 unsigned long flags; 2629 2630 spin_lock_irqsave(&rdev->rcu_idx_lock, flags); 2631 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); 2632 WREG32(R600_RCU_DATA, (v)); 2633 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags); 2634 } 2635 2636 static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg) 2637 { 2638 unsigned long flags; 2639 u32 r; 2640 2641 spin_lock_irqsave(&rdev->cg_idx_lock, flags); 2642 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); 2643 r = RREG32(EVERGREEN_CG_IND_DATA); 2644 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags); 2645 return r; 2646 } 2647 2648 static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2649 { 2650 unsigned long flags; 2651 2652 spin_lock_irqsave(&rdev->cg_idx_lock, flags); 2653 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); 2654 WREG32(EVERGREEN_CG_IND_DATA, (v)); 2655 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags); 2656 } 2657 2658 static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg) 2659 { 2660 unsigned long flags; 2661 u32 r; 2662 2663 spin_lock_irqsave(&rdev->pif_idx_lock, flags); 2664 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); 2665 r = RREG32(EVERGREEN_PIF_PHY0_DATA); 2666 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); 2667 return r; 2668 } 2669 2670 static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2671 { 2672 unsigned long flags; 2673 2674 spin_lock_irqsave(&rdev->pif_idx_lock, flags); 2675 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); 2676 WREG32(EVERGREEN_PIF_PHY0_DATA, (v)); 2677 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); 2678 } 2679 2680 static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg) 2681 { 2682 unsigned long flags; 2683 u32 r; 2684 2685 spin_lock_irqsave(&rdev->pif_idx_lock, flags); 2686 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); 2687 r = RREG32(EVERGREEN_PIF_PHY1_DATA); 2688 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); 2689 return r; 2690 } 2691 2692 static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2693 { 2694 unsigned long flags; 2695 2696 spin_lock_irqsave(&rdev->pif_idx_lock, flags); 2697 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); 2698 WREG32(EVERGREEN_PIF_PHY1_DATA, (v)); 2699 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); 2700 } 2701 2702 static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg) 2703 { 2704 unsigned long flags; 2705 u32 r; 2706 2707 spin_lock_irqsave(&rdev->uvd_idx_lock, flags); 2708 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); 2709 r = RREG32(R600_UVD_CTX_DATA); 2710 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags); 2711 return r; 2712 } 2713 2714 static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2715 { 2716 unsigned long flags; 2717 2718 spin_lock_irqsave(&rdev->uvd_idx_lock, flags); 2719 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); 2720 WREG32(R600_UVD_CTX_DATA, (v)); 2721 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags); 2722 } 2723 2724 2725 static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg) 2726 { 2727 unsigned long flags; 2728 u32 r; 2729 2730 spin_lock_irqsave(&rdev->didt_idx_lock, flags); 2731 WREG32(CIK_DIDT_IND_INDEX, (reg)); 2732 r = RREG32(CIK_DIDT_IND_DATA); 2733 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags); 2734 return r; 2735 } 2736 2737 static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2738 { 2739 unsigned long flags; 2740 2741 spin_lock_irqsave(&rdev->didt_idx_lock, flags); 2742 WREG32(CIK_DIDT_IND_INDEX, (reg)); 2743 WREG32(CIK_DIDT_IND_DATA, (v)); 2744 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags); 2745 } 2746 2747 void r100_pll_errata_after_index(struct radeon_device *rdev); 2748 2749 2750 /* 2751 * ASICs helpers. 2752 */ 2753 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ 2754 (rdev->pdev->device == 0x5969)) 2755 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ 2756 (rdev->family == CHIP_RV200) || \ 2757 (rdev->family == CHIP_RS100) || \ 2758 (rdev->family == CHIP_RS200) || \ 2759 (rdev->family == CHIP_RV250) || \ 2760 (rdev->family == CHIP_RV280) || \ 2761 (rdev->family == CHIP_RS300)) 2762 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ 2763 (rdev->family == CHIP_RV350) || \ 2764 (rdev->family == CHIP_R350) || \ 2765 (rdev->family == CHIP_RV380) || \ 2766 (rdev->family == CHIP_R420) || \ 2767 (rdev->family == CHIP_R423) || \ 2768 (rdev->family == CHIP_RV410) || \ 2769 (rdev->family == CHIP_RS400) || \ 2770 (rdev->family == CHIP_RS480)) 2771 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \ 2772 (rdev->ddev->pdev->device == 0x9443) || \ 2773 (rdev->ddev->pdev->device == 0x944B) || \ 2774 (rdev->ddev->pdev->device == 0x9506) || \ 2775 (rdev->ddev->pdev->device == 0x9509) || \ 2776 (rdev->ddev->pdev->device == 0x950F) || \ 2777 (rdev->ddev->pdev->device == 0x689C) || \ 2778 (rdev->ddev->pdev->device == 0x689D)) 2779 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) 2780 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ 2781 (rdev->family == CHIP_RS690) || \ 2782 (rdev->family == CHIP_RS740) || \ 2783 (rdev->family >= CHIP_R600)) 2784 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) 2785 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) 2786 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) 2787 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ 2788 (rdev->flags & RADEON_IS_IGP)) 2789 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) 2790 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA)) 2791 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ 2792 (rdev->flags & RADEON_IS_IGP)) 2793 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND)) 2794 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN)) 2795 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE)) 2796 #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI)) 2797 #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE)) 2798 #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \ 2799 (rdev->family == CHIP_MULLINS)) 2800 2801 #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \ 2802 (rdev->ddev->pdev->device == 0x6850) || \ 2803 (rdev->ddev->pdev->device == 0x6858) || \ 2804 (rdev->ddev->pdev->device == 0x6859) || \ 2805 (rdev->ddev->pdev->device == 0x6840) || \ 2806 (rdev->ddev->pdev->device == 0x6841) || \ 2807 (rdev->ddev->pdev->device == 0x6842) || \ 2808 (rdev->ddev->pdev->device == 0x6843)) 2809 2810 /* 2811 * BIOS helpers. 2812 */ 2813 #define RBIOS8(i) (rdev->bios[i]) 2814 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 2815 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 2816 2817 int radeon_combios_init(struct radeon_device *rdev); 2818 void radeon_combios_fini(struct radeon_device *rdev); 2819 int radeon_atombios_init(struct radeon_device *rdev); 2820 void radeon_atombios_fini(struct radeon_device *rdev); 2821 2822 2823 /* 2824 * RING helpers. 2825 */ 2826 2827 /** 2828 * radeon_ring_write - write a value to the ring 2829 * 2830 * @ring: radeon_ring structure holding ring information 2831 * @v: dword (dw) value to write 2832 * 2833 * Write a value to the requested ring buffer (all asics). 2834 */ 2835 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) 2836 { 2837 if (ring->count_dw <= 0) 2838 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n"); 2839 2840 ring->ring[ring->wptr++] = v; 2841 ring->wptr &= ring->ptr_mask; 2842 ring->count_dw--; 2843 ring->ring_free_dw--; 2844 } 2845 2846 /* 2847 * ASICs macro. 2848 */ 2849 #define radeon_init(rdev) (rdev)->asic->init((rdev)) 2850 #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) 2851 #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) 2852 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) 2853 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p)) 2854 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) 2855 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) 2856 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) 2857 #define radeon_gart_get_page_entry(a, f) (rdev)->asic->gart.get_page_entry((a), (f)) 2858 #define radeon_gart_set_page(rdev, i, e) (rdev)->asic->gart.set_page((rdev), (i), (e)) 2859 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) 2860 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) 2861 #define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count))) 2862 #define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) 2863 #define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) 2864 #define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib))) 2865 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp)) 2866 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp)) 2867 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp)) 2868 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib)) 2869 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib)) 2870 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp)) 2871 #define radeon_ring_vm_flush(rdev, r, vm_id, pd_addr) (rdev)->asic->ring[(r)->idx]->vm_flush((rdev), (r), (vm_id), (pd_addr)) 2872 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r)) 2873 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r)) 2874 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r)) 2875 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) 2876 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev)) 2877 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) 2878 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l)) 2879 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e)) 2880 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b)) 2881 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m)) 2882 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence)) 2883 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) 2884 #define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv)) 2885 #define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv)) 2886 #define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv)) 2887 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index 2888 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index 2889 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index 2890 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev)) 2891 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e)) 2892 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev)) 2893 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e)) 2894 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) 2895 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) 2896 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) 2897 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d)) 2898 #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec)) 2899 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev)) 2900 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) 2901 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) 2902 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) 2903 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev)) 2904 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev)) 2905 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h)) 2906 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h)) 2907 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) 2908 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev)) 2909 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev)) 2910 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev)) 2911 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev)) 2912 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev)) 2913 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base)) 2914 #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc)) 2915 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc)) 2916 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev)) 2917 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev)) 2918 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev)) 2919 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev)) 2920 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev)) 2921 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev)) 2922 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev)) 2923 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev)) 2924 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev)) 2925 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev)) 2926 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev)) 2927 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev)) 2928 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev)) 2929 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l)) 2930 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l)) 2931 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps)) 2932 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m)) 2933 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l)) 2934 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev)) 2935 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g)) 2936 #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e)) 2937 2938 /* Common functions */ 2939 /* AGP */ 2940 extern int radeon_gpu_reset(struct radeon_device *rdev); 2941 extern void radeon_pci_config_reset(struct radeon_device *rdev); 2942 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung); 2943 extern void radeon_agp_disable(struct radeon_device *rdev); 2944 extern int radeon_modeset_init(struct radeon_device *rdev); 2945 extern void radeon_modeset_fini(struct radeon_device *rdev); 2946 extern bool radeon_card_posted(struct radeon_device *rdev); 2947 extern void radeon_update_bandwidth_info(struct radeon_device *rdev); 2948 extern void radeon_update_display_priority(struct radeon_device *rdev); 2949 extern bool radeon_boot_test_post_card(struct radeon_device *rdev); 2950 extern void radeon_scratch_init(struct radeon_device *rdev); 2951 extern void radeon_wb_fini(struct radeon_device *rdev); 2952 extern int radeon_wb_init(struct radeon_device *rdev); 2953 extern void radeon_wb_disable(struct radeon_device *rdev); 2954 extern void radeon_surface_init(struct radeon_device *rdev); 2955 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); 2956 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); 2957 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); 2958 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); 2959 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); 2960 extern int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, 2961 uint32_t flags); 2962 extern bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm); 2963 extern bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm); 2964 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); 2965 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); 2966 extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 2967 extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon); 2968 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); 2969 extern void radeon_program_register_sequence(struct radeon_device *rdev, 2970 const u32 *registers, 2971 const u32 array_size); 2972 2973 /* 2974 * vm 2975 */ 2976 int radeon_vm_manager_init(struct radeon_device *rdev); 2977 void radeon_vm_manager_fini(struct radeon_device *rdev); 2978 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); 2979 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); 2980 struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev, 2981 struct radeon_vm *vm, 2982 struct list_head *head); 2983 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, 2984 struct radeon_vm *vm, int ring); 2985 void radeon_vm_flush(struct radeon_device *rdev, 2986 struct radeon_vm *vm, 2987 int ring, struct radeon_fence *fence); 2988 void radeon_vm_fence(struct radeon_device *rdev, 2989 struct radeon_vm *vm, 2990 struct radeon_fence *fence); 2991 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr); 2992 int radeon_vm_update_page_directory(struct radeon_device *rdev, 2993 struct radeon_vm *vm); 2994 int radeon_vm_clear_freed(struct radeon_device *rdev, 2995 struct radeon_vm *vm); 2996 int radeon_vm_clear_invalids(struct radeon_device *rdev, 2997 struct radeon_vm *vm); 2998 int radeon_vm_bo_update(struct radeon_device *rdev, 2999 struct radeon_bo_va *bo_va, 3000 struct ttm_mem_reg *mem); 3001 void radeon_vm_bo_invalidate(struct radeon_device *rdev, 3002 struct radeon_bo *bo); 3003 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm, 3004 struct radeon_bo *bo); 3005 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev, 3006 struct radeon_vm *vm, 3007 struct radeon_bo *bo); 3008 int radeon_vm_bo_set_addr(struct radeon_device *rdev, 3009 struct radeon_bo_va *bo_va, 3010 uint64_t offset, 3011 uint32_t flags); 3012 void radeon_vm_bo_rmv(struct radeon_device *rdev, 3013 struct radeon_bo_va *bo_va); 3014 3015 /* audio */ 3016 void r600_audio_update_hdmi(struct work_struct *work); 3017 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev); 3018 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev); 3019 void r600_audio_enable(struct radeon_device *rdev, 3020 struct r600_audio_pin *pin, 3021 u8 enable_mask); 3022 void dce6_audio_enable(struct radeon_device *rdev, 3023 struct r600_audio_pin *pin, 3024 u8 enable_mask); 3025 3026 /* 3027 * R600 vram scratch functions 3028 */ 3029 int r600_vram_scratch_init(struct radeon_device *rdev); 3030 void r600_vram_scratch_fini(struct radeon_device *rdev); 3031 3032 /* 3033 * r600 cs checking helper 3034 */ 3035 unsigned r600_mip_minify(unsigned size, unsigned level); 3036 bool r600_fmt_is_valid_color(u32 format); 3037 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family); 3038 int r600_fmt_get_blocksize(u32 format); 3039 int r600_fmt_get_nblocksx(u32 format, u32 w); 3040 int r600_fmt_get_nblocksy(u32 format, u32 h); 3041 3042 /* 3043 * r600 functions used by radeon_encoder.c 3044 */ 3045 struct radeon_hdmi_acr { 3046 u32 clock; 3047 3048 int n_32khz; 3049 int cts_32khz; 3050 3051 int n_44_1khz; 3052 int cts_44_1khz; 3053 3054 int n_48khz; 3055 int cts_48khz; 3056 3057 }; 3058 3059 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock); 3060 3061 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev, 3062 u32 tiling_pipe_num, 3063 u32 max_rb_num, 3064 u32 total_max_rb_num, 3065 u32 enabled_rb_mask); 3066 3067 /* 3068 * evergreen functions used by radeon_encoder.c 3069 */ 3070 3071 extern int ni_init_microcode(struct radeon_device *rdev); 3072 extern int ni_mc_load_microcode(struct radeon_device *rdev); 3073 3074 /* radeon_acpi.c */ 3075 #if defined(CONFIG_ACPI) 3076 extern int radeon_acpi_init(struct radeon_device *rdev); 3077 extern void radeon_acpi_fini(struct radeon_device *rdev); 3078 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev); 3079 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev, 3080 u8 perf_req, bool advertise); 3081 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev); 3082 #else 3083 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; } 3084 static inline void radeon_acpi_fini(struct radeon_device *rdev) { } 3085 #endif 3086 3087 int radeon_cs_packet_parse(struct radeon_cs_parser *p, 3088 struct radeon_cs_packet *pkt, 3089 unsigned idx); 3090 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p); 3091 void radeon_cs_dump_packet(struct radeon_cs_parser *p, 3092 struct radeon_cs_packet *pkt); 3093 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p, 3094 struct radeon_bo_list **cs_reloc, 3095 int nomm); 3096 int r600_cs_common_vline_parse(struct radeon_cs_parser *p, 3097 uint32_t *vline_start_end, 3098 uint32_t *vline_status); 3099 3100 #include "radeon_object.h" 3101 3102 #endif 3103