1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __RADEON_H__ 29 #define __RADEON_H__ 30 31 /* TODO: Here are things that needs to be done : 32 * - surface allocator & initializer : (bit like scratch reg) should 33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings 34 * related to surface 35 * - WB : write back stuff (do it bit like scratch reg things) 36 * - Vblank : look at Jesse's rework and what we should do 37 * - r600/r700: gart & cp 38 * - cs : clean cs ioctl use bitmap & things like that. 39 * - power management stuff 40 * - Barrier in gart code 41 * - Unmappabled vram ? 42 * - TESTING, TESTING, TESTING 43 */ 44 45 /* Initialization path: 46 * We expect that acceleration initialization might fail for various 47 * reasons even thought we work hard to make it works on most 48 * configurations. In order to still have a working userspace in such 49 * situation the init path must succeed up to the memory controller 50 * initialization point. Failure before this point are considered as 51 * fatal error. Here is the init callchain : 52 * radeon_device_init perform common structure, mutex initialization 53 * asic_init setup the GPU memory layout and perform all 54 * one time initialization (failure in this 55 * function are considered fatal) 56 * asic_startup setup the GPU acceleration, in order to 57 * follow guideline the first thing this 58 * function should do is setting the GPU 59 * memory controller (only MC setup failure 60 * are considered as fatal) 61 */ 62 63 #include <linux/atomic.h> 64 #include <linux/wait.h> 65 #include <linux/list.h> 66 #include <linux/kref.h> 67 68 #include <ttm/ttm_bo_api.h> 69 #include <ttm/ttm_bo_driver.h> 70 #include <ttm/ttm_placement.h> 71 #include <ttm/ttm_module.h> 72 #include <ttm/ttm_execbuf_util.h> 73 74 #include "radeon_family.h" 75 #include "radeon_mode.h" 76 #include "radeon_reg.h" 77 78 /* 79 * Modules parameters. 80 */ 81 extern int radeon_no_wb; 82 extern int radeon_modeset; 83 extern int radeon_dynclks; 84 extern int radeon_r4xx_atom; 85 extern int radeon_agpmode; 86 extern int radeon_vram_limit; 87 extern int radeon_gart_size; 88 extern int radeon_benchmarking; 89 extern int radeon_testing; 90 extern int radeon_connector_table; 91 extern int radeon_tv; 92 extern int radeon_audio; 93 extern int radeon_disp_priority; 94 extern int radeon_hw_i2c; 95 extern int radeon_pcie_gen2; 96 extern int radeon_msi; 97 extern int radeon_lockup_timeout; 98 99 /* 100 * Copy from radeon_drv.h so we don't have to include both and have conflicting 101 * symbol; 102 */ 103 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 104 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) 105 /* RADEON_IB_POOL_SIZE must be a power of 2 */ 106 #define RADEON_IB_POOL_SIZE 16 107 #define RADEON_DEBUGFS_MAX_COMPONENTS 32 108 #define RADEONFB_CONN_LIMIT 4 109 #define RADEON_BIOS_NUM_SCRATCH 8 110 111 /* max number of rings */ 112 #define RADEON_NUM_RINGS 5 113 114 /* fence seq are set to this number when signaled */ 115 #define RADEON_FENCE_SIGNALED_SEQ 0LL 116 117 /* internal ring indices */ 118 /* r1xx+ has gfx CP ring */ 119 #define RADEON_RING_TYPE_GFX_INDEX 0 120 121 /* cayman has 2 compute CP rings */ 122 #define CAYMAN_RING_TYPE_CP1_INDEX 1 123 #define CAYMAN_RING_TYPE_CP2_INDEX 2 124 125 /* R600+ has an async dma ring */ 126 #define R600_RING_TYPE_DMA_INDEX 3 127 /* cayman add a second async dma ring */ 128 #define CAYMAN_RING_TYPE_DMA1_INDEX 4 129 130 /* hardcode those limit for now */ 131 #define RADEON_VA_IB_OFFSET (1 << 20) 132 #define RADEON_VA_RESERVED_SIZE (8 << 20) 133 #define RADEON_IB_VM_MAX_SIZE (64 << 10) 134 135 /* 136 * Errata workarounds. 137 */ 138 enum radeon_pll_errata { 139 CHIP_ERRATA_R300_CG = 0x00000001, 140 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, 141 CHIP_ERRATA_PLL_DELAY = 0x00000004 142 }; 143 144 145 struct radeon_device; 146 147 148 /* 149 * BIOS. 150 */ 151 bool radeon_get_bios(struct radeon_device *rdev); 152 153 /* 154 * Dummy page 155 */ 156 struct radeon_dummy_page { 157 struct page *page; 158 dma_addr_t addr; 159 }; 160 int radeon_dummy_page_init(struct radeon_device *rdev); 161 void radeon_dummy_page_fini(struct radeon_device *rdev); 162 163 164 /* 165 * Clocks 166 */ 167 struct radeon_clock { 168 struct radeon_pll p1pll; 169 struct radeon_pll p2pll; 170 struct radeon_pll dcpll; 171 struct radeon_pll spll; 172 struct radeon_pll mpll; 173 /* 10 Khz units */ 174 uint32_t default_mclk; 175 uint32_t default_sclk; 176 uint32_t default_dispclk; 177 uint32_t dp_extclk; 178 uint32_t max_pixel_clock; 179 }; 180 181 /* 182 * Power management 183 */ 184 int radeon_pm_init(struct radeon_device *rdev); 185 void radeon_pm_fini(struct radeon_device *rdev); 186 void radeon_pm_compute_clocks(struct radeon_device *rdev); 187 void radeon_pm_suspend(struct radeon_device *rdev); 188 void radeon_pm_resume(struct radeon_device *rdev); 189 void radeon_combios_get_power_modes(struct radeon_device *rdev); 190 void radeon_atombios_get_power_modes(struct radeon_device *rdev); 191 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); 192 void rs690_pm_info(struct radeon_device *rdev); 193 extern int rv6xx_get_temp(struct radeon_device *rdev); 194 extern int rv770_get_temp(struct radeon_device *rdev); 195 extern int evergreen_get_temp(struct radeon_device *rdev); 196 extern int sumo_get_temp(struct radeon_device *rdev); 197 extern int si_get_temp(struct radeon_device *rdev); 198 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, 199 unsigned *bankh, unsigned *mtaspect, 200 unsigned *tile_split); 201 202 /* 203 * Fences. 204 */ 205 struct radeon_fence_driver { 206 uint32_t scratch_reg; 207 uint64_t gpu_addr; 208 volatile uint32_t *cpu_addr; 209 /* sync_seq is protected by ring emission lock */ 210 uint64_t sync_seq[RADEON_NUM_RINGS]; 211 atomic64_t last_seq; 212 unsigned long last_activity; 213 bool initialized; 214 }; 215 216 struct radeon_fence { 217 struct radeon_device *rdev; 218 struct kref kref; 219 /* protected by radeon_fence.lock */ 220 uint64_t seq; 221 /* RB, DMA, etc. */ 222 unsigned ring; 223 }; 224 225 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring); 226 int radeon_fence_driver_init(struct radeon_device *rdev); 227 void radeon_fence_driver_fini(struct radeon_device *rdev); 228 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring); 229 void radeon_fence_process(struct radeon_device *rdev, int ring); 230 bool radeon_fence_signaled(struct radeon_fence *fence); 231 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); 232 int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring); 233 void radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring); 234 int radeon_fence_wait_any(struct radeon_device *rdev, 235 struct radeon_fence **fences, 236 bool intr); 237 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); 238 void radeon_fence_unref(struct radeon_fence **fence); 239 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring); 240 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring); 241 void radeon_fence_note_sync(struct radeon_fence *fence, int ring); 242 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a, 243 struct radeon_fence *b) 244 { 245 if (!a) { 246 return b; 247 } 248 249 if (!b) { 250 return a; 251 } 252 253 BUG_ON(a->ring != b->ring); 254 255 if (a->seq > b->seq) { 256 return a; 257 } else { 258 return b; 259 } 260 } 261 262 static inline bool radeon_fence_is_earlier(struct radeon_fence *a, 263 struct radeon_fence *b) 264 { 265 if (!a) { 266 return false; 267 } 268 269 if (!b) { 270 return true; 271 } 272 273 BUG_ON(a->ring != b->ring); 274 275 return a->seq < b->seq; 276 } 277 278 /* 279 * Tiling registers 280 */ 281 struct radeon_surface_reg { 282 struct radeon_bo *bo; 283 }; 284 285 #define RADEON_GEM_MAX_SURFACES 8 286 287 /* 288 * TTM. 289 */ 290 struct radeon_mman { 291 struct ttm_bo_global_ref bo_global_ref; 292 struct drm_global_reference mem_global_ref; 293 struct ttm_bo_device bdev; 294 bool mem_global_referenced; 295 bool initialized; 296 }; 297 298 /* bo virtual address in a specific vm */ 299 struct radeon_bo_va { 300 /* protected by bo being reserved */ 301 struct list_head bo_list; 302 uint64_t soffset; 303 uint64_t eoffset; 304 uint32_t flags; 305 bool valid; 306 unsigned ref_count; 307 308 /* protected by vm mutex */ 309 struct list_head vm_list; 310 311 /* constant after initialization */ 312 struct radeon_vm *vm; 313 struct radeon_bo *bo; 314 }; 315 316 struct radeon_bo { 317 /* Protected by gem.mutex */ 318 struct list_head list; 319 /* Protected by tbo.reserved */ 320 u32 placements[3]; 321 u32 busy_placements[3]; 322 struct ttm_placement placement; 323 struct ttm_buffer_object tbo; 324 struct ttm_bo_kmap_obj kmap; 325 unsigned pin_count; 326 void *kptr; 327 u32 tiling_flags; 328 u32 pitch; 329 int surface_reg; 330 /* list of all virtual address to which this bo 331 * is associated to 332 */ 333 struct list_head va; 334 /* Constant after initialization */ 335 struct radeon_device *rdev; 336 struct drm_gem_object gem_base; 337 338 struct ttm_bo_kmap_obj dma_buf_vmap; 339 int vmapping_count; 340 }; 341 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base) 342 343 struct radeon_bo_list { 344 struct ttm_validate_buffer tv; 345 struct radeon_bo *bo; 346 uint64_t gpu_offset; 347 unsigned rdomain; 348 unsigned wdomain; 349 u32 tiling_flags; 350 }; 351 352 /* sub-allocation manager, it has to be protected by another lock. 353 * By conception this is an helper for other part of the driver 354 * like the indirect buffer or semaphore, which both have their 355 * locking. 356 * 357 * Principe is simple, we keep a list of sub allocation in offset 358 * order (first entry has offset == 0, last entry has the highest 359 * offset). 360 * 361 * When allocating new object we first check if there is room at 362 * the end total_size - (last_object_offset + last_object_size) >= 363 * alloc_size. If so we allocate new object there. 364 * 365 * When there is not enough room at the end, we start waiting for 366 * each sub object until we reach object_offset+object_size >= 367 * alloc_size, this object then become the sub object we return. 368 * 369 * Alignment can't be bigger than page size. 370 * 371 * Hole are not considered for allocation to keep things simple. 372 * Assumption is that there won't be hole (all object on same 373 * alignment). 374 */ 375 struct radeon_sa_manager { 376 wait_queue_head_t wq; 377 struct radeon_bo *bo; 378 struct list_head *hole; 379 struct list_head flist[RADEON_NUM_RINGS]; 380 struct list_head olist; 381 unsigned size; 382 uint64_t gpu_addr; 383 void *cpu_ptr; 384 uint32_t domain; 385 }; 386 387 struct radeon_sa_bo; 388 389 /* sub-allocation buffer */ 390 struct radeon_sa_bo { 391 struct list_head olist; 392 struct list_head flist; 393 struct radeon_sa_manager *manager; 394 unsigned soffset; 395 unsigned eoffset; 396 struct radeon_fence *fence; 397 }; 398 399 /* 400 * GEM objects. 401 */ 402 struct radeon_gem { 403 struct mutex mutex; 404 struct list_head objects; 405 }; 406 407 int radeon_gem_init(struct radeon_device *rdev); 408 void radeon_gem_fini(struct radeon_device *rdev); 409 int radeon_gem_object_create(struct radeon_device *rdev, int size, 410 int alignment, int initial_domain, 411 bool discardable, bool kernel, 412 struct drm_gem_object **obj); 413 414 int radeon_mode_dumb_create(struct drm_file *file_priv, 415 struct drm_device *dev, 416 struct drm_mode_create_dumb *args); 417 int radeon_mode_dumb_mmap(struct drm_file *filp, 418 struct drm_device *dev, 419 uint32_t handle, uint64_t *offset_p); 420 int radeon_mode_dumb_destroy(struct drm_file *file_priv, 421 struct drm_device *dev, 422 uint32_t handle); 423 424 /* 425 * Semaphores. 426 */ 427 /* everything here is constant */ 428 struct radeon_semaphore { 429 struct radeon_sa_bo *sa_bo; 430 signed waiters; 431 uint64_t gpu_addr; 432 }; 433 434 int radeon_semaphore_create(struct radeon_device *rdev, 435 struct radeon_semaphore **semaphore); 436 void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, 437 struct radeon_semaphore *semaphore); 438 void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, 439 struct radeon_semaphore *semaphore); 440 int radeon_semaphore_sync_rings(struct radeon_device *rdev, 441 struct radeon_semaphore *semaphore, 442 int signaler, int waiter); 443 void radeon_semaphore_free(struct radeon_device *rdev, 444 struct radeon_semaphore **semaphore, 445 struct radeon_fence *fence); 446 447 /* 448 * GART structures, functions & helpers 449 */ 450 struct radeon_mc; 451 452 #define RADEON_GPU_PAGE_SIZE 4096 453 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) 454 #define RADEON_GPU_PAGE_SHIFT 12 455 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK) 456 457 struct radeon_gart { 458 dma_addr_t table_addr; 459 struct radeon_bo *robj; 460 void *ptr; 461 unsigned num_gpu_pages; 462 unsigned num_cpu_pages; 463 unsigned table_size; 464 struct page **pages; 465 dma_addr_t *pages_addr; 466 bool ready; 467 }; 468 469 int radeon_gart_table_ram_alloc(struct radeon_device *rdev); 470 void radeon_gart_table_ram_free(struct radeon_device *rdev); 471 int radeon_gart_table_vram_alloc(struct radeon_device *rdev); 472 void radeon_gart_table_vram_free(struct radeon_device *rdev); 473 int radeon_gart_table_vram_pin(struct radeon_device *rdev); 474 void radeon_gart_table_vram_unpin(struct radeon_device *rdev); 475 int radeon_gart_init(struct radeon_device *rdev); 476 void radeon_gart_fini(struct radeon_device *rdev); 477 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, 478 int pages); 479 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, 480 int pages, struct page **pagelist, 481 dma_addr_t *dma_addr); 482 void radeon_gart_restore(struct radeon_device *rdev); 483 484 485 /* 486 * GPU MC structures, functions & helpers 487 */ 488 struct radeon_mc { 489 resource_size_t aper_size; 490 resource_size_t aper_base; 491 resource_size_t agp_base; 492 /* for some chips with <= 32MB we need to lie 493 * about vram size near mc fb location */ 494 u64 mc_vram_size; 495 u64 visible_vram_size; 496 u64 gtt_size; 497 u64 gtt_start; 498 u64 gtt_end; 499 u64 vram_start; 500 u64 vram_end; 501 unsigned vram_width; 502 u64 real_vram_size; 503 int vram_mtrr; 504 bool vram_is_ddr; 505 bool igp_sideport_enabled; 506 u64 gtt_base_align; 507 }; 508 509 bool radeon_combios_sideport_present(struct radeon_device *rdev); 510 bool radeon_atombios_sideport_present(struct radeon_device *rdev); 511 512 /* 513 * GPU scratch registers structures, functions & helpers 514 */ 515 struct radeon_scratch { 516 unsigned num_reg; 517 uint32_t reg_base; 518 bool free[32]; 519 uint32_t reg[32]; 520 }; 521 522 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); 523 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); 524 525 526 /* 527 * IRQS. 528 */ 529 530 struct radeon_unpin_work { 531 struct work_struct work; 532 struct radeon_device *rdev; 533 int crtc_id; 534 struct radeon_fence *fence; 535 struct drm_pending_vblank_event *event; 536 struct radeon_bo *old_rbo; 537 u64 new_crtc_base; 538 }; 539 540 struct r500_irq_stat_regs { 541 u32 disp_int; 542 u32 hdmi0_status; 543 }; 544 545 struct r600_irq_stat_regs { 546 u32 disp_int; 547 u32 disp_int_cont; 548 u32 disp_int_cont2; 549 u32 d1grph_int; 550 u32 d2grph_int; 551 u32 hdmi0_status; 552 u32 hdmi1_status; 553 }; 554 555 struct evergreen_irq_stat_regs { 556 u32 disp_int; 557 u32 disp_int_cont; 558 u32 disp_int_cont2; 559 u32 disp_int_cont3; 560 u32 disp_int_cont4; 561 u32 disp_int_cont5; 562 u32 d1grph_int; 563 u32 d2grph_int; 564 u32 d3grph_int; 565 u32 d4grph_int; 566 u32 d5grph_int; 567 u32 d6grph_int; 568 u32 afmt_status1; 569 u32 afmt_status2; 570 u32 afmt_status3; 571 u32 afmt_status4; 572 u32 afmt_status5; 573 u32 afmt_status6; 574 }; 575 576 union radeon_irq_stat_regs { 577 struct r500_irq_stat_regs r500; 578 struct r600_irq_stat_regs r600; 579 struct evergreen_irq_stat_regs evergreen; 580 }; 581 582 #define RADEON_MAX_HPD_PINS 6 583 #define RADEON_MAX_CRTCS 6 584 #define RADEON_MAX_AFMT_BLOCKS 6 585 586 struct radeon_irq { 587 bool installed; 588 spinlock_t lock; 589 atomic_t ring_int[RADEON_NUM_RINGS]; 590 bool crtc_vblank_int[RADEON_MAX_CRTCS]; 591 atomic_t pflip[RADEON_MAX_CRTCS]; 592 wait_queue_head_t vblank_queue; 593 bool hpd[RADEON_MAX_HPD_PINS]; 594 bool afmt[RADEON_MAX_AFMT_BLOCKS]; 595 union radeon_irq_stat_regs stat_regs; 596 }; 597 598 int radeon_irq_kms_init(struct radeon_device *rdev); 599 void radeon_irq_kms_fini(struct radeon_device *rdev); 600 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring); 601 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring); 602 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); 603 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); 604 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block); 605 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block); 606 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 607 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 608 609 /* 610 * CP & rings. 611 */ 612 613 struct radeon_ib { 614 struct radeon_sa_bo *sa_bo; 615 uint32_t length_dw; 616 uint64_t gpu_addr; 617 uint32_t *ptr; 618 int ring; 619 struct radeon_fence *fence; 620 struct radeon_vm *vm; 621 bool is_const_ib; 622 struct radeon_fence *sync_to[RADEON_NUM_RINGS]; 623 struct radeon_semaphore *semaphore; 624 }; 625 626 struct radeon_ring { 627 struct radeon_bo *ring_obj; 628 volatile uint32_t *ring; 629 unsigned rptr; 630 unsigned rptr_offs; 631 unsigned rptr_reg; 632 unsigned rptr_save_reg; 633 u64 next_rptr_gpu_addr; 634 volatile u32 *next_rptr_cpu_addr; 635 unsigned wptr; 636 unsigned wptr_old; 637 unsigned wptr_reg; 638 unsigned ring_size; 639 unsigned ring_free_dw; 640 int count_dw; 641 unsigned long last_activity; 642 unsigned last_rptr; 643 uint64_t gpu_addr; 644 uint32_t align_mask; 645 uint32_t ptr_mask; 646 bool ready; 647 u32 ptr_reg_shift; 648 u32 ptr_reg_mask; 649 u32 nop; 650 u32 idx; 651 }; 652 653 /* 654 * VM 655 */ 656 657 /* maximum number of VMIDs */ 658 #define RADEON_NUM_VM 16 659 660 /* defines number of bits in page table versus page directory, 661 * a page is 4KB so we have 12 bits offset, 9 bits in the page 662 * table and the remaining 19 bits are in the page directory */ 663 #define RADEON_VM_BLOCK_SIZE 9 664 665 /* number of entries in page table */ 666 #define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE) 667 668 struct radeon_vm { 669 struct list_head list; 670 struct list_head va; 671 unsigned id; 672 673 /* contains the page directory */ 674 struct radeon_sa_bo *page_directory; 675 uint64_t pd_gpu_addr; 676 677 /* array of page tables, one for each page directory entry */ 678 struct radeon_sa_bo **page_tables; 679 680 struct mutex mutex; 681 /* last fence for cs using this vm */ 682 struct radeon_fence *fence; 683 /* last flush or NULL if we still need to flush */ 684 struct radeon_fence *last_flush; 685 }; 686 687 struct radeon_vm_manager { 688 struct mutex lock; 689 struct list_head lru_vm; 690 struct radeon_fence *active[RADEON_NUM_VM]; 691 struct radeon_sa_manager sa_manager; 692 uint32_t max_pfn; 693 /* number of VMIDs */ 694 unsigned nvm; 695 /* vram base address for page table entry */ 696 u64 vram_base_offset; 697 /* is vm enabled? */ 698 bool enabled; 699 }; 700 701 /* 702 * file private structure 703 */ 704 struct radeon_fpriv { 705 struct radeon_vm vm; 706 }; 707 708 /* 709 * R6xx+ IH ring 710 */ 711 struct r600_ih { 712 struct radeon_bo *ring_obj; 713 volatile uint32_t *ring; 714 unsigned rptr; 715 unsigned ring_size; 716 uint64_t gpu_addr; 717 uint32_t ptr_mask; 718 atomic_t lock; 719 bool enabled; 720 }; 721 722 struct r600_blit_cp_primitives { 723 void (*set_render_target)(struct radeon_device *rdev, int format, 724 int w, int h, u64 gpu_addr); 725 void (*cp_set_surface_sync)(struct radeon_device *rdev, 726 u32 sync_type, u32 size, 727 u64 mc_addr); 728 void (*set_shaders)(struct radeon_device *rdev); 729 void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr); 730 void (*set_tex_resource)(struct radeon_device *rdev, 731 int format, int w, int h, int pitch, 732 u64 gpu_addr, u32 size); 733 void (*set_scissors)(struct radeon_device *rdev, int x1, int y1, 734 int x2, int y2); 735 void (*draw_auto)(struct radeon_device *rdev); 736 void (*set_default_state)(struct radeon_device *rdev); 737 }; 738 739 struct r600_blit { 740 struct radeon_bo *shader_obj; 741 struct r600_blit_cp_primitives primitives; 742 int max_dim; 743 int ring_size_common; 744 int ring_size_per_loop; 745 u64 shader_gpu_addr; 746 u32 vs_offset, ps_offset; 747 u32 state_offset; 748 u32 state_len; 749 }; 750 751 /* 752 * SI RLC stuff 753 */ 754 struct si_rlc { 755 /* for power gating */ 756 struct radeon_bo *save_restore_obj; 757 uint64_t save_restore_gpu_addr; 758 /* for clear state */ 759 struct radeon_bo *clear_state_obj; 760 uint64_t clear_state_gpu_addr; 761 }; 762 763 int radeon_ib_get(struct radeon_device *rdev, int ring, 764 struct radeon_ib *ib, struct radeon_vm *vm, 765 unsigned size); 766 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); 767 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, 768 struct radeon_ib *const_ib); 769 int radeon_ib_pool_init(struct radeon_device *rdev); 770 void radeon_ib_pool_fini(struct radeon_device *rdev); 771 int radeon_ib_ring_tests(struct radeon_device *rdev); 772 /* Ring access between begin & end cannot sleep */ 773 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, 774 struct radeon_ring *ring); 775 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); 776 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 777 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 778 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp); 779 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp); 780 void radeon_ring_undo(struct radeon_ring *ring); 781 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); 782 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 783 void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring); 784 void radeon_ring_lockup_update(struct radeon_ring *ring); 785 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 786 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, 787 uint32_t **data); 788 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, 789 unsigned size, uint32_t *data); 790 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size, 791 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg, 792 u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop); 793 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); 794 795 796 /* r600 async dma */ 797 void r600_dma_stop(struct radeon_device *rdev); 798 int r600_dma_resume(struct radeon_device *rdev); 799 void r600_dma_fini(struct radeon_device *rdev); 800 801 void cayman_dma_stop(struct radeon_device *rdev); 802 int cayman_dma_resume(struct radeon_device *rdev); 803 void cayman_dma_fini(struct radeon_device *rdev); 804 805 /* 806 * CS. 807 */ 808 struct radeon_cs_reloc { 809 struct drm_gem_object *gobj; 810 struct radeon_bo *robj; 811 struct radeon_bo_list lobj; 812 uint32_t handle; 813 uint32_t flags; 814 }; 815 816 struct radeon_cs_chunk { 817 uint32_t chunk_id; 818 uint32_t length_dw; 819 int kpage_idx[2]; 820 uint32_t *kpage[2]; 821 uint32_t *kdata; 822 void __user *user_ptr; 823 int last_copied_page; 824 int last_page_index; 825 }; 826 827 struct radeon_cs_parser { 828 struct device *dev; 829 struct radeon_device *rdev; 830 struct drm_file *filp; 831 /* chunks */ 832 unsigned nchunks; 833 struct radeon_cs_chunk *chunks; 834 uint64_t *chunks_array; 835 /* IB */ 836 unsigned idx; 837 /* relocations */ 838 unsigned nrelocs; 839 struct radeon_cs_reloc *relocs; 840 struct radeon_cs_reloc **relocs_ptr; 841 struct list_head validated; 842 unsigned dma_reloc_idx; 843 /* indices of various chunks */ 844 int chunk_ib_idx; 845 int chunk_relocs_idx; 846 int chunk_flags_idx; 847 int chunk_const_ib_idx; 848 struct radeon_ib ib; 849 struct radeon_ib const_ib; 850 void *track; 851 unsigned family; 852 int parser_error; 853 u32 cs_flags; 854 u32 ring; 855 s32 priority; 856 }; 857 858 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p); 859 extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx); 860 861 struct radeon_cs_packet { 862 unsigned idx; 863 unsigned type; 864 unsigned reg; 865 unsigned opcode; 866 int count; 867 unsigned one_reg_wr; 868 }; 869 870 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, 871 struct radeon_cs_packet *pkt, 872 unsigned idx, unsigned reg); 873 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, 874 struct radeon_cs_packet *pkt); 875 876 877 /* 878 * AGP 879 */ 880 int radeon_agp_init(struct radeon_device *rdev); 881 void radeon_agp_resume(struct radeon_device *rdev); 882 void radeon_agp_suspend(struct radeon_device *rdev); 883 void radeon_agp_fini(struct radeon_device *rdev); 884 885 886 /* 887 * Writeback 888 */ 889 struct radeon_wb { 890 struct radeon_bo *wb_obj; 891 volatile uint32_t *wb; 892 uint64_t gpu_addr; 893 bool enabled; 894 bool use_event; 895 }; 896 897 #define RADEON_WB_SCRATCH_OFFSET 0 898 #define RADEON_WB_RING0_NEXT_RPTR 256 899 #define RADEON_WB_CP_RPTR_OFFSET 1024 900 #define RADEON_WB_CP1_RPTR_OFFSET 1280 901 #define RADEON_WB_CP2_RPTR_OFFSET 1536 902 #define R600_WB_DMA_RPTR_OFFSET 1792 903 #define R600_WB_IH_WPTR_OFFSET 2048 904 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304 905 #define R600_WB_EVENT_OFFSET 3072 906 907 /** 908 * struct radeon_pm - power management datas 909 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) 910 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) 911 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) 912 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) 913 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) 914 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) 915 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) 916 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) 917 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) 918 * @sclk: GPU clock Mhz (core bandwidth depends of this clock) 919 * @needed_bandwidth: current bandwidth needs 920 * 921 * It keeps track of various data needed to take powermanagement decision. 922 * Bandwidth need is used to determine minimun clock of the GPU and memory. 923 * Equation between gpu/memory clock and available bandwidth is hw dependent 924 * (type of memory, bus size, efficiency, ...) 925 */ 926 927 enum radeon_pm_method { 928 PM_METHOD_PROFILE, 929 PM_METHOD_DYNPM, 930 }; 931 932 enum radeon_dynpm_state { 933 DYNPM_STATE_DISABLED, 934 DYNPM_STATE_MINIMUM, 935 DYNPM_STATE_PAUSED, 936 DYNPM_STATE_ACTIVE, 937 DYNPM_STATE_SUSPENDED, 938 }; 939 enum radeon_dynpm_action { 940 DYNPM_ACTION_NONE, 941 DYNPM_ACTION_MINIMUM, 942 DYNPM_ACTION_DOWNCLOCK, 943 DYNPM_ACTION_UPCLOCK, 944 DYNPM_ACTION_DEFAULT 945 }; 946 947 enum radeon_voltage_type { 948 VOLTAGE_NONE = 0, 949 VOLTAGE_GPIO, 950 VOLTAGE_VDDC, 951 VOLTAGE_SW 952 }; 953 954 enum radeon_pm_state_type { 955 POWER_STATE_TYPE_DEFAULT, 956 POWER_STATE_TYPE_POWERSAVE, 957 POWER_STATE_TYPE_BATTERY, 958 POWER_STATE_TYPE_BALANCED, 959 POWER_STATE_TYPE_PERFORMANCE, 960 }; 961 962 enum radeon_pm_profile_type { 963 PM_PROFILE_DEFAULT, 964 PM_PROFILE_AUTO, 965 PM_PROFILE_LOW, 966 PM_PROFILE_MID, 967 PM_PROFILE_HIGH, 968 }; 969 970 #define PM_PROFILE_DEFAULT_IDX 0 971 #define PM_PROFILE_LOW_SH_IDX 1 972 #define PM_PROFILE_MID_SH_IDX 2 973 #define PM_PROFILE_HIGH_SH_IDX 3 974 #define PM_PROFILE_LOW_MH_IDX 4 975 #define PM_PROFILE_MID_MH_IDX 5 976 #define PM_PROFILE_HIGH_MH_IDX 6 977 #define PM_PROFILE_MAX 7 978 979 struct radeon_pm_profile { 980 int dpms_off_ps_idx; 981 int dpms_on_ps_idx; 982 int dpms_off_cm_idx; 983 int dpms_on_cm_idx; 984 }; 985 986 enum radeon_int_thermal_type { 987 THERMAL_TYPE_NONE, 988 THERMAL_TYPE_RV6XX, 989 THERMAL_TYPE_RV770, 990 THERMAL_TYPE_EVERGREEN, 991 THERMAL_TYPE_SUMO, 992 THERMAL_TYPE_NI, 993 THERMAL_TYPE_SI, 994 }; 995 996 struct radeon_voltage { 997 enum radeon_voltage_type type; 998 /* gpio voltage */ 999 struct radeon_gpio_rec gpio; 1000 u32 delay; /* delay in usec from voltage drop to sclk change */ 1001 bool active_high; /* voltage drop is active when bit is high */ 1002 /* VDDC voltage */ 1003 u8 vddc_id; /* index into vddc voltage table */ 1004 u8 vddci_id; /* index into vddci voltage table */ 1005 bool vddci_enabled; 1006 /* r6xx+ sw */ 1007 u16 voltage; 1008 /* evergreen+ vddci */ 1009 u16 vddci; 1010 }; 1011 1012 /* clock mode flags */ 1013 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) 1014 1015 struct radeon_pm_clock_info { 1016 /* memory clock */ 1017 u32 mclk; 1018 /* engine clock */ 1019 u32 sclk; 1020 /* voltage info */ 1021 struct radeon_voltage voltage; 1022 /* standardized clock flags */ 1023 u32 flags; 1024 }; 1025 1026 /* state flags */ 1027 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) 1028 1029 struct radeon_power_state { 1030 enum radeon_pm_state_type type; 1031 struct radeon_pm_clock_info *clock_info; 1032 /* number of valid clock modes in this power state */ 1033 int num_clock_modes; 1034 struct radeon_pm_clock_info *default_clock_mode; 1035 /* standardized state flags */ 1036 u32 flags; 1037 u32 misc; /* vbios specific flags */ 1038 u32 misc2; /* vbios specific flags */ 1039 int pcie_lanes; /* pcie lanes */ 1040 }; 1041 1042 /* 1043 * Some modes are overclocked by very low value, accept them 1044 */ 1045 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ 1046 1047 struct radeon_pm { 1048 struct mutex mutex; 1049 /* write locked while reprogramming mclk */ 1050 struct rw_semaphore mclk_lock; 1051 u32 active_crtcs; 1052 int active_crtc_count; 1053 int req_vblank; 1054 bool vblank_sync; 1055 fixed20_12 max_bandwidth; 1056 fixed20_12 igp_sideport_mclk; 1057 fixed20_12 igp_system_mclk; 1058 fixed20_12 igp_ht_link_clk; 1059 fixed20_12 igp_ht_link_width; 1060 fixed20_12 k8_bandwidth; 1061 fixed20_12 sideport_bandwidth; 1062 fixed20_12 ht_bandwidth; 1063 fixed20_12 core_bandwidth; 1064 fixed20_12 sclk; 1065 fixed20_12 mclk; 1066 fixed20_12 needed_bandwidth; 1067 struct radeon_power_state *power_state; 1068 /* number of valid power states */ 1069 int num_power_states; 1070 int current_power_state_index; 1071 int current_clock_mode_index; 1072 int requested_power_state_index; 1073 int requested_clock_mode_index; 1074 int default_power_state_index; 1075 u32 current_sclk; 1076 u32 current_mclk; 1077 u16 current_vddc; 1078 u16 current_vddci; 1079 u32 default_sclk; 1080 u32 default_mclk; 1081 u16 default_vddc; 1082 u16 default_vddci; 1083 struct radeon_i2c_chan *i2c_bus; 1084 /* selected pm method */ 1085 enum radeon_pm_method pm_method; 1086 /* dynpm power management */ 1087 struct delayed_work dynpm_idle_work; 1088 enum radeon_dynpm_state dynpm_state; 1089 enum radeon_dynpm_action dynpm_planned_action; 1090 unsigned long dynpm_action_timeout; 1091 bool dynpm_can_upclock; 1092 bool dynpm_can_downclock; 1093 /* profile-based power management */ 1094 enum radeon_pm_profile_type profile; 1095 int profile_index; 1096 struct radeon_pm_profile profiles[PM_PROFILE_MAX]; 1097 /* internal thermal controller on rv6xx+ */ 1098 enum radeon_int_thermal_type int_thermal_type; 1099 struct device *int_hwmon_dev; 1100 }; 1101 1102 int radeon_pm_get_type_index(struct radeon_device *rdev, 1103 enum radeon_pm_state_type ps_type, 1104 int instance); 1105 1106 struct r600_audio { 1107 int channels; 1108 int rate; 1109 int bits_per_sample; 1110 u8 status_bits; 1111 u8 category_code; 1112 }; 1113 1114 /* 1115 * Benchmarking 1116 */ 1117 void radeon_benchmark(struct radeon_device *rdev, int test_number); 1118 1119 1120 /* 1121 * Testing 1122 */ 1123 void radeon_test_moves(struct radeon_device *rdev); 1124 void radeon_test_ring_sync(struct radeon_device *rdev, 1125 struct radeon_ring *cpA, 1126 struct radeon_ring *cpB); 1127 void radeon_test_syncing(struct radeon_device *rdev); 1128 1129 1130 /* 1131 * Debugfs 1132 */ 1133 struct radeon_debugfs { 1134 struct drm_info_list *files; 1135 unsigned num_files; 1136 }; 1137 1138 int radeon_debugfs_add_files(struct radeon_device *rdev, 1139 struct drm_info_list *files, 1140 unsigned nfiles); 1141 int radeon_debugfs_fence_init(struct radeon_device *rdev); 1142 1143 1144 /* 1145 * ASIC specific functions. 1146 */ 1147 struct radeon_asic { 1148 int (*init)(struct radeon_device *rdev); 1149 void (*fini)(struct radeon_device *rdev); 1150 int (*resume)(struct radeon_device *rdev); 1151 int (*suspend)(struct radeon_device *rdev); 1152 void (*vga_set_state)(struct radeon_device *rdev, bool state); 1153 int (*asic_reset)(struct radeon_device *rdev); 1154 /* ioctl hw specific callback. Some hw might want to perform special 1155 * operation on specific ioctl. For instance on wait idle some hw 1156 * might want to perform and HDP flush through MMIO as it seems that 1157 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed 1158 * through ring. 1159 */ 1160 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo); 1161 /* check if 3D engine is idle */ 1162 bool (*gui_idle)(struct radeon_device *rdev); 1163 /* wait for mc_idle */ 1164 int (*mc_wait_for_idle)(struct radeon_device *rdev); 1165 /* gart */ 1166 struct { 1167 void (*tlb_flush)(struct radeon_device *rdev); 1168 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr); 1169 } gart; 1170 struct { 1171 int (*init)(struct radeon_device *rdev); 1172 void (*fini)(struct radeon_device *rdev); 1173 1174 u32 pt_ring_index; 1175 void (*set_page)(struct radeon_device *rdev, uint64_t pe, 1176 uint64_t addr, unsigned count, 1177 uint32_t incr, uint32_t flags); 1178 } vm; 1179 /* ring specific callbacks */ 1180 struct { 1181 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); 1182 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib); 1183 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence); 1184 void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp, 1185 struct radeon_semaphore *semaphore, bool emit_wait); 1186 int (*cs_parse)(struct radeon_cs_parser *p); 1187 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp); 1188 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1189 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1190 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); 1191 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 1192 } ring[RADEON_NUM_RINGS]; 1193 /* irqs */ 1194 struct { 1195 int (*set)(struct radeon_device *rdev); 1196 int (*process)(struct radeon_device *rdev); 1197 } irq; 1198 /* displays */ 1199 struct { 1200 /* display watermarks */ 1201 void (*bandwidth_update)(struct radeon_device *rdev); 1202 /* get frame count */ 1203 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); 1204 /* wait for vblank */ 1205 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc); 1206 /* set backlight level */ 1207 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level); 1208 /* get backlight level */ 1209 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder); 1210 } display; 1211 /* copy functions for bo handling */ 1212 struct { 1213 int (*blit)(struct radeon_device *rdev, 1214 uint64_t src_offset, 1215 uint64_t dst_offset, 1216 unsigned num_gpu_pages, 1217 struct radeon_fence **fence); 1218 u32 blit_ring_index; 1219 int (*dma)(struct radeon_device *rdev, 1220 uint64_t src_offset, 1221 uint64_t dst_offset, 1222 unsigned num_gpu_pages, 1223 struct radeon_fence **fence); 1224 u32 dma_ring_index; 1225 /* method used for bo copy */ 1226 int (*copy)(struct radeon_device *rdev, 1227 uint64_t src_offset, 1228 uint64_t dst_offset, 1229 unsigned num_gpu_pages, 1230 struct radeon_fence **fence); 1231 /* ring used for bo copies */ 1232 u32 copy_ring_index; 1233 } copy; 1234 /* surfaces */ 1235 struct { 1236 int (*set_reg)(struct radeon_device *rdev, int reg, 1237 uint32_t tiling_flags, uint32_t pitch, 1238 uint32_t offset, uint32_t obj_size); 1239 void (*clear_reg)(struct radeon_device *rdev, int reg); 1240 } surface; 1241 /* hotplug detect */ 1242 struct { 1243 void (*init)(struct radeon_device *rdev); 1244 void (*fini)(struct radeon_device *rdev); 1245 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1246 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1247 } hpd; 1248 /* power management */ 1249 struct { 1250 void (*misc)(struct radeon_device *rdev); 1251 void (*prepare)(struct radeon_device *rdev); 1252 void (*finish)(struct radeon_device *rdev); 1253 void (*init_profile)(struct radeon_device *rdev); 1254 void (*get_dynpm_state)(struct radeon_device *rdev); 1255 uint32_t (*get_engine_clock)(struct radeon_device *rdev); 1256 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); 1257 uint32_t (*get_memory_clock)(struct radeon_device *rdev); 1258 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); 1259 int (*get_pcie_lanes)(struct radeon_device *rdev); 1260 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); 1261 void (*set_clock_gating)(struct radeon_device *rdev, int enable); 1262 } pm; 1263 /* pageflipping */ 1264 struct { 1265 void (*pre_page_flip)(struct radeon_device *rdev, int crtc); 1266 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base); 1267 void (*post_page_flip)(struct radeon_device *rdev, int crtc); 1268 } pflip; 1269 }; 1270 1271 /* 1272 * Asic structures 1273 */ 1274 struct r100_asic { 1275 const unsigned *reg_safe_bm; 1276 unsigned reg_safe_bm_size; 1277 u32 hdp_cntl; 1278 }; 1279 1280 struct r300_asic { 1281 const unsigned *reg_safe_bm; 1282 unsigned reg_safe_bm_size; 1283 u32 resync_scratch; 1284 u32 hdp_cntl; 1285 }; 1286 1287 struct r600_asic { 1288 unsigned max_pipes; 1289 unsigned max_tile_pipes; 1290 unsigned max_simds; 1291 unsigned max_backends; 1292 unsigned max_gprs; 1293 unsigned max_threads; 1294 unsigned max_stack_entries; 1295 unsigned max_hw_contexts; 1296 unsigned max_gs_threads; 1297 unsigned sx_max_export_size; 1298 unsigned sx_max_export_pos_size; 1299 unsigned sx_max_export_smx_size; 1300 unsigned sq_num_cf_insts; 1301 unsigned tiling_nbanks; 1302 unsigned tiling_npipes; 1303 unsigned tiling_group_size; 1304 unsigned tile_config; 1305 unsigned backend_map; 1306 }; 1307 1308 struct rv770_asic { 1309 unsigned max_pipes; 1310 unsigned max_tile_pipes; 1311 unsigned max_simds; 1312 unsigned max_backends; 1313 unsigned max_gprs; 1314 unsigned max_threads; 1315 unsigned max_stack_entries; 1316 unsigned max_hw_contexts; 1317 unsigned max_gs_threads; 1318 unsigned sx_max_export_size; 1319 unsigned sx_max_export_pos_size; 1320 unsigned sx_max_export_smx_size; 1321 unsigned sq_num_cf_insts; 1322 unsigned sx_num_of_sets; 1323 unsigned sc_prim_fifo_size; 1324 unsigned sc_hiz_tile_fifo_size; 1325 unsigned sc_earlyz_tile_fifo_fize; 1326 unsigned tiling_nbanks; 1327 unsigned tiling_npipes; 1328 unsigned tiling_group_size; 1329 unsigned tile_config; 1330 unsigned backend_map; 1331 }; 1332 1333 struct evergreen_asic { 1334 unsigned num_ses; 1335 unsigned max_pipes; 1336 unsigned max_tile_pipes; 1337 unsigned max_simds; 1338 unsigned max_backends; 1339 unsigned max_gprs; 1340 unsigned max_threads; 1341 unsigned max_stack_entries; 1342 unsigned max_hw_contexts; 1343 unsigned max_gs_threads; 1344 unsigned sx_max_export_size; 1345 unsigned sx_max_export_pos_size; 1346 unsigned sx_max_export_smx_size; 1347 unsigned sq_num_cf_insts; 1348 unsigned sx_num_of_sets; 1349 unsigned sc_prim_fifo_size; 1350 unsigned sc_hiz_tile_fifo_size; 1351 unsigned sc_earlyz_tile_fifo_size; 1352 unsigned tiling_nbanks; 1353 unsigned tiling_npipes; 1354 unsigned tiling_group_size; 1355 unsigned tile_config; 1356 unsigned backend_map; 1357 }; 1358 1359 struct cayman_asic { 1360 unsigned max_shader_engines; 1361 unsigned max_pipes_per_simd; 1362 unsigned max_tile_pipes; 1363 unsigned max_simds_per_se; 1364 unsigned max_backends_per_se; 1365 unsigned max_texture_channel_caches; 1366 unsigned max_gprs; 1367 unsigned max_threads; 1368 unsigned max_gs_threads; 1369 unsigned max_stack_entries; 1370 unsigned sx_num_of_sets; 1371 unsigned sx_max_export_size; 1372 unsigned sx_max_export_pos_size; 1373 unsigned sx_max_export_smx_size; 1374 unsigned max_hw_contexts; 1375 unsigned sq_num_cf_insts; 1376 unsigned sc_prim_fifo_size; 1377 unsigned sc_hiz_tile_fifo_size; 1378 unsigned sc_earlyz_tile_fifo_size; 1379 1380 unsigned num_shader_engines; 1381 unsigned num_shader_pipes_per_simd; 1382 unsigned num_tile_pipes; 1383 unsigned num_simds_per_se; 1384 unsigned num_backends_per_se; 1385 unsigned backend_disable_mask_per_asic; 1386 unsigned backend_map; 1387 unsigned num_texture_channel_caches; 1388 unsigned mem_max_burst_length_bytes; 1389 unsigned mem_row_size_in_kb; 1390 unsigned shader_engine_tile_size; 1391 unsigned num_gpus; 1392 unsigned multi_gpu_tile_size; 1393 1394 unsigned tile_config; 1395 }; 1396 1397 struct si_asic { 1398 unsigned max_shader_engines; 1399 unsigned max_tile_pipes; 1400 unsigned max_cu_per_sh; 1401 unsigned max_sh_per_se; 1402 unsigned max_backends_per_se; 1403 unsigned max_texture_channel_caches; 1404 unsigned max_gprs; 1405 unsigned max_gs_threads; 1406 unsigned max_hw_contexts; 1407 unsigned sc_prim_fifo_size_frontend; 1408 unsigned sc_prim_fifo_size_backend; 1409 unsigned sc_hiz_tile_fifo_size; 1410 unsigned sc_earlyz_tile_fifo_size; 1411 1412 unsigned num_tile_pipes; 1413 unsigned num_backends_per_se; 1414 unsigned backend_disable_mask_per_asic; 1415 unsigned backend_map; 1416 unsigned num_texture_channel_caches; 1417 unsigned mem_max_burst_length_bytes; 1418 unsigned mem_row_size_in_kb; 1419 unsigned shader_engine_tile_size; 1420 unsigned num_gpus; 1421 unsigned multi_gpu_tile_size; 1422 1423 unsigned tile_config; 1424 }; 1425 1426 union radeon_asic_config { 1427 struct r300_asic r300; 1428 struct r100_asic r100; 1429 struct r600_asic r600; 1430 struct rv770_asic rv770; 1431 struct evergreen_asic evergreen; 1432 struct cayman_asic cayman; 1433 struct si_asic si; 1434 }; 1435 1436 /* 1437 * asic initizalization from radeon_asic.c 1438 */ 1439 void radeon_agp_disable(struct radeon_device *rdev); 1440 int radeon_asic_init(struct radeon_device *rdev); 1441 1442 1443 /* 1444 * IOCTL. 1445 */ 1446 int radeon_gem_info_ioctl(struct drm_device *dev, void *data, 1447 struct drm_file *filp); 1448 int radeon_gem_create_ioctl(struct drm_device *dev, void *data, 1449 struct drm_file *filp); 1450 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, 1451 struct drm_file *file_priv); 1452 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, 1453 struct drm_file *file_priv); 1454 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, 1455 struct drm_file *file_priv); 1456 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, 1457 struct drm_file *file_priv); 1458 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, 1459 struct drm_file *filp); 1460 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, 1461 struct drm_file *filp); 1462 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, 1463 struct drm_file *filp); 1464 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 1465 struct drm_file *filp); 1466 int radeon_gem_va_ioctl(struct drm_device *dev, void *data, 1467 struct drm_file *filp); 1468 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1469 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, 1470 struct drm_file *filp); 1471 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, 1472 struct drm_file *filp); 1473 1474 /* VRAM scratch page for HDP bug, default vram page */ 1475 struct r600_vram_scratch { 1476 struct radeon_bo *robj; 1477 volatile uint32_t *ptr; 1478 u64 gpu_addr; 1479 }; 1480 1481 /* 1482 * ACPI 1483 */ 1484 struct radeon_atif_notification_cfg { 1485 bool enabled; 1486 int command_code; 1487 }; 1488 1489 struct radeon_atif_notifications { 1490 bool display_switch; 1491 bool expansion_mode_change; 1492 bool thermal_state; 1493 bool forced_power_state; 1494 bool system_power_state; 1495 bool display_conf_change; 1496 bool px_gfx_switch; 1497 bool brightness_change; 1498 bool dgpu_display_event; 1499 }; 1500 1501 struct radeon_atif_functions { 1502 bool system_params; 1503 bool sbios_requests; 1504 bool select_active_disp; 1505 bool lid_state; 1506 bool get_tv_standard; 1507 bool set_tv_standard; 1508 bool get_panel_expansion_mode; 1509 bool set_panel_expansion_mode; 1510 bool temperature_change; 1511 bool graphics_device_types; 1512 }; 1513 1514 struct radeon_atif { 1515 struct radeon_atif_notifications notifications; 1516 struct radeon_atif_functions functions; 1517 struct radeon_atif_notification_cfg notification_cfg; 1518 struct radeon_encoder *encoder_for_bl; 1519 }; 1520 1521 struct radeon_atcs_functions { 1522 bool get_ext_state; 1523 bool pcie_perf_req; 1524 bool pcie_dev_rdy; 1525 bool pcie_bus_width; 1526 }; 1527 1528 struct radeon_atcs { 1529 struct radeon_atcs_functions functions; 1530 }; 1531 1532 /* 1533 * Core structure, functions and helpers. 1534 */ 1535 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); 1536 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); 1537 1538 struct radeon_device { 1539 struct device *dev; 1540 struct drm_device *ddev; 1541 struct pci_dev *pdev; 1542 struct rw_semaphore exclusive_lock; 1543 /* ASIC */ 1544 union radeon_asic_config config; 1545 enum radeon_family family; 1546 unsigned long flags; 1547 int usec_timeout; 1548 enum radeon_pll_errata pll_errata; 1549 int num_gb_pipes; 1550 int num_z_pipes; 1551 int disp_priority; 1552 /* BIOS */ 1553 uint8_t *bios; 1554 bool is_atom_bios; 1555 uint16_t bios_header_start; 1556 struct radeon_bo *stollen_vga_memory; 1557 /* Register mmio */ 1558 resource_size_t rmmio_base; 1559 resource_size_t rmmio_size; 1560 /* protects concurrent MM_INDEX/DATA based register access */ 1561 spinlock_t mmio_idx_lock; 1562 void __iomem *rmmio; 1563 radeon_rreg_t mc_rreg; 1564 radeon_wreg_t mc_wreg; 1565 radeon_rreg_t pll_rreg; 1566 radeon_wreg_t pll_wreg; 1567 uint32_t pcie_reg_mask; 1568 radeon_rreg_t pciep_rreg; 1569 radeon_wreg_t pciep_wreg; 1570 /* io port */ 1571 void __iomem *rio_mem; 1572 resource_size_t rio_mem_size; 1573 struct radeon_clock clock; 1574 struct radeon_mc mc; 1575 struct radeon_gart gart; 1576 struct radeon_mode_info mode_info; 1577 struct radeon_scratch scratch; 1578 struct radeon_mman mman; 1579 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS]; 1580 wait_queue_head_t fence_queue; 1581 struct mutex ring_lock; 1582 struct radeon_ring ring[RADEON_NUM_RINGS]; 1583 bool ib_pool_ready; 1584 struct radeon_sa_manager ring_tmp_bo; 1585 struct radeon_irq irq; 1586 struct radeon_asic *asic; 1587 struct radeon_gem gem; 1588 struct radeon_pm pm; 1589 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; 1590 struct radeon_wb wb; 1591 struct radeon_dummy_page dummy_page; 1592 bool shutdown; 1593 bool suspend; 1594 bool need_dma32; 1595 bool accel_working; 1596 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; 1597 const struct firmware *me_fw; /* all family ME firmware */ 1598 const struct firmware *pfp_fw; /* r6/700 PFP firmware */ 1599 const struct firmware *rlc_fw; /* r6/700 RLC firmware */ 1600 const struct firmware *mc_fw; /* NI MC firmware */ 1601 const struct firmware *ce_fw; /* SI CE firmware */ 1602 struct r600_blit r600_blit; 1603 struct r600_vram_scratch vram_scratch; 1604 int msi_enabled; /* msi enabled */ 1605 struct r600_ih ih; /* r6/700 interrupt ring */ 1606 struct si_rlc rlc; 1607 struct work_struct hotplug_work; 1608 struct work_struct audio_work; 1609 int num_crtc; /* number of crtcs */ 1610 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ 1611 bool audio_enabled; 1612 struct r600_audio audio_status; /* audio stuff */ 1613 struct notifier_block acpi_nb; 1614 /* only one userspace can use Hyperz features or CMASK at a time */ 1615 struct drm_file *hyperz_filp; 1616 struct drm_file *cmask_filp; 1617 /* i2c buses */ 1618 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; 1619 /* debugfs */ 1620 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS]; 1621 unsigned debugfs_count; 1622 /* virtual memory */ 1623 struct radeon_vm_manager vm_manager; 1624 struct mutex gpu_clock_mutex; 1625 /* ACPI interface */ 1626 struct radeon_atif atif; 1627 struct radeon_atcs atcs; 1628 }; 1629 1630 int radeon_device_init(struct radeon_device *rdev, 1631 struct drm_device *ddev, 1632 struct pci_dev *pdev, 1633 uint32_t flags); 1634 void radeon_device_fini(struct radeon_device *rdev); 1635 int radeon_gpu_wait_for_idle(struct radeon_device *rdev); 1636 1637 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, 1638 bool always_indirect); 1639 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, 1640 bool always_indirect); 1641 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg); 1642 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); 1643 1644 /* 1645 * Cast helper 1646 */ 1647 #define to_radeon_fence(p) ((struct radeon_fence *)(p)) 1648 1649 /* 1650 * Registers read & write functions. 1651 */ 1652 #define RREG8(reg) readb((rdev->rmmio) + (reg)) 1653 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg)) 1654 #define RREG16(reg) readw((rdev->rmmio) + (reg)) 1655 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg)) 1656 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false) 1657 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true) 1658 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false)) 1659 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false) 1660 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true) 1661 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1662 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1663 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) 1664 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) 1665 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) 1666 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) 1667 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) 1668 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) 1669 #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg)) 1670 #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) 1671 #define WREG32_P(reg, val, mask) \ 1672 do { \ 1673 uint32_t tmp_ = RREG32(reg); \ 1674 tmp_ &= (mask); \ 1675 tmp_ |= ((val) & ~(mask)); \ 1676 WREG32(reg, tmp_); \ 1677 } while (0) 1678 #define WREG32_PLL_P(reg, val, mask) \ 1679 do { \ 1680 uint32_t tmp_ = RREG32_PLL(reg); \ 1681 tmp_ &= (mask); \ 1682 tmp_ |= ((val) & ~(mask)); \ 1683 WREG32_PLL(reg, tmp_); \ 1684 } while (0) 1685 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false)) 1686 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) 1687 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) 1688 1689 /* 1690 * Indirect registers accessor 1691 */ 1692 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) 1693 { 1694 uint32_t r; 1695 1696 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 1697 r = RREG32(RADEON_PCIE_DATA); 1698 return r; 1699 } 1700 1701 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 1702 { 1703 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 1704 WREG32(RADEON_PCIE_DATA, (v)); 1705 } 1706 1707 void r100_pll_errata_after_index(struct radeon_device *rdev); 1708 1709 1710 /* 1711 * ASICs helpers. 1712 */ 1713 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ 1714 (rdev->pdev->device == 0x5969)) 1715 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ 1716 (rdev->family == CHIP_RV200) || \ 1717 (rdev->family == CHIP_RS100) || \ 1718 (rdev->family == CHIP_RS200) || \ 1719 (rdev->family == CHIP_RV250) || \ 1720 (rdev->family == CHIP_RV280) || \ 1721 (rdev->family == CHIP_RS300)) 1722 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ 1723 (rdev->family == CHIP_RV350) || \ 1724 (rdev->family == CHIP_R350) || \ 1725 (rdev->family == CHIP_RV380) || \ 1726 (rdev->family == CHIP_R420) || \ 1727 (rdev->family == CHIP_R423) || \ 1728 (rdev->family == CHIP_RV410) || \ 1729 (rdev->family == CHIP_RS400) || \ 1730 (rdev->family == CHIP_RS480)) 1731 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \ 1732 (rdev->ddev->pdev->device == 0x9443) || \ 1733 (rdev->ddev->pdev->device == 0x944B) || \ 1734 (rdev->ddev->pdev->device == 0x9506) || \ 1735 (rdev->ddev->pdev->device == 0x9509) || \ 1736 (rdev->ddev->pdev->device == 0x950F) || \ 1737 (rdev->ddev->pdev->device == 0x689C) || \ 1738 (rdev->ddev->pdev->device == 0x689D)) 1739 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) 1740 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ 1741 (rdev->family == CHIP_RS690) || \ 1742 (rdev->family == CHIP_RS740) || \ 1743 (rdev->family >= CHIP_R600)) 1744 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) 1745 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) 1746 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) 1747 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ 1748 (rdev->flags & RADEON_IS_IGP)) 1749 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) 1750 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA)) 1751 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ 1752 (rdev->flags & RADEON_IS_IGP)) 1753 1754 /* 1755 * BIOS helpers. 1756 */ 1757 #define RBIOS8(i) (rdev->bios[i]) 1758 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1759 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1760 1761 int radeon_combios_init(struct radeon_device *rdev); 1762 void radeon_combios_fini(struct radeon_device *rdev); 1763 int radeon_atombios_init(struct radeon_device *rdev); 1764 void radeon_atombios_fini(struct radeon_device *rdev); 1765 1766 1767 /* 1768 * RING helpers. 1769 */ 1770 #if DRM_DEBUG_CODE == 0 1771 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) 1772 { 1773 ring->ring[ring->wptr++] = v; 1774 ring->wptr &= ring->ptr_mask; 1775 ring->count_dw--; 1776 ring->ring_free_dw--; 1777 } 1778 #else 1779 /* With debugging this is just too big to inline */ 1780 void radeon_ring_write(struct radeon_ring *ring, uint32_t v); 1781 #endif 1782 1783 /* 1784 * ASICs macro. 1785 */ 1786 #define radeon_init(rdev) (rdev)->asic->init((rdev)) 1787 #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) 1788 #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) 1789 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) 1790 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p)) 1791 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) 1792 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) 1793 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) 1794 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p)) 1795 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) 1796 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) 1797 #define radeon_asic_vm_set_page(rdev, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (pe), (addr), (count), (incr), (flags))) 1798 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp)) 1799 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp)) 1800 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp)) 1801 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib)) 1802 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib)) 1803 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)].is_lockup((rdev), (cp)) 1804 #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)].vm_flush((rdev), (r), (vm)) 1805 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) 1806 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev)) 1807 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) 1808 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l)) 1809 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e)) 1810 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence)) 1811 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) 1812 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f)) 1813 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f)) 1814 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f)) 1815 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index 1816 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index 1817 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index 1818 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev)) 1819 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e)) 1820 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev)) 1821 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e)) 1822 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) 1823 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) 1824 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) 1825 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) 1826 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) 1827 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) 1828 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev)) 1829 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev)) 1830 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h)) 1831 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h)) 1832 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) 1833 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev)) 1834 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev)) 1835 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev)) 1836 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev)) 1837 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev)) 1838 #define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc)) 1839 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base)) 1840 #define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc)) 1841 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc)) 1842 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev)) 1843 1844 /* Common functions */ 1845 /* AGP */ 1846 extern int radeon_gpu_reset(struct radeon_device *rdev); 1847 extern void radeon_agp_disable(struct radeon_device *rdev); 1848 extern int radeon_modeset_init(struct radeon_device *rdev); 1849 extern void radeon_modeset_fini(struct radeon_device *rdev); 1850 extern bool radeon_card_posted(struct radeon_device *rdev); 1851 extern void radeon_update_bandwidth_info(struct radeon_device *rdev); 1852 extern void radeon_update_display_priority(struct radeon_device *rdev); 1853 extern bool radeon_boot_test_post_card(struct radeon_device *rdev); 1854 extern void radeon_scratch_init(struct radeon_device *rdev); 1855 extern void radeon_wb_fini(struct radeon_device *rdev); 1856 extern int radeon_wb_init(struct radeon_device *rdev); 1857 extern void radeon_wb_disable(struct radeon_device *rdev); 1858 extern void radeon_surface_init(struct radeon_device *rdev); 1859 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); 1860 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); 1861 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); 1862 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); 1863 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); 1864 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); 1865 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); 1866 extern int radeon_resume_kms(struct drm_device *dev); 1867 extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state); 1868 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); 1869 1870 /* 1871 * vm 1872 */ 1873 int radeon_vm_manager_init(struct radeon_device *rdev); 1874 void radeon_vm_manager_fini(struct radeon_device *rdev); 1875 void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); 1876 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); 1877 int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm); 1878 void radeon_vm_add_to_lru(struct radeon_device *rdev, struct radeon_vm *vm); 1879 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, 1880 struct radeon_vm *vm, int ring); 1881 void radeon_vm_fence(struct radeon_device *rdev, 1882 struct radeon_vm *vm, 1883 struct radeon_fence *fence); 1884 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr); 1885 int radeon_vm_bo_update_pte(struct radeon_device *rdev, 1886 struct radeon_vm *vm, 1887 struct radeon_bo *bo, 1888 struct ttm_mem_reg *mem); 1889 void radeon_vm_bo_invalidate(struct radeon_device *rdev, 1890 struct radeon_bo *bo); 1891 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm, 1892 struct radeon_bo *bo); 1893 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev, 1894 struct radeon_vm *vm, 1895 struct radeon_bo *bo); 1896 int radeon_vm_bo_set_addr(struct radeon_device *rdev, 1897 struct radeon_bo_va *bo_va, 1898 uint64_t offset, 1899 uint32_t flags); 1900 int radeon_vm_bo_rmv(struct radeon_device *rdev, 1901 struct radeon_bo_va *bo_va); 1902 1903 /* audio */ 1904 void r600_audio_update_hdmi(struct work_struct *work); 1905 1906 /* 1907 * R600 vram scratch functions 1908 */ 1909 int r600_vram_scratch_init(struct radeon_device *rdev); 1910 void r600_vram_scratch_fini(struct radeon_device *rdev); 1911 1912 /* 1913 * r600 cs checking helper 1914 */ 1915 unsigned r600_mip_minify(unsigned size, unsigned level); 1916 bool r600_fmt_is_valid_color(u32 format); 1917 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family); 1918 int r600_fmt_get_blocksize(u32 format); 1919 int r600_fmt_get_nblocksx(u32 format, u32 w); 1920 int r600_fmt_get_nblocksy(u32 format, u32 h); 1921 1922 /* 1923 * r600 functions used by radeon_encoder.c 1924 */ 1925 struct radeon_hdmi_acr { 1926 u32 clock; 1927 1928 int n_32khz; 1929 int cts_32khz; 1930 1931 int n_44_1khz; 1932 int cts_44_1khz; 1933 1934 int n_48khz; 1935 int cts_48khz; 1936 1937 }; 1938 1939 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock); 1940 1941 extern void r600_hdmi_enable(struct drm_encoder *encoder); 1942 extern void r600_hdmi_disable(struct drm_encoder *encoder); 1943 extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); 1944 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev, 1945 u32 tiling_pipe_num, 1946 u32 max_rb_num, 1947 u32 total_max_rb_num, 1948 u32 enabled_rb_mask); 1949 1950 /* 1951 * evergreen functions used by radeon_encoder.c 1952 */ 1953 1954 extern void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); 1955 1956 extern int ni_init_microcode(struct radeon_device *rdev); 1957 extern int ni_mc_load_microcode(struct radeon_device *rdev); 1958 1959 /* radeon_acpi.c */ 1960 #if defined(CONFIG_ACPI) 1961 extern int radeon_acpi_init(struct radeon_device *rdev); 1962 extern void radeon_acpi_fini(struct radeon_device *rdev); 1963 #else 1964 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; } 1965 static inline void radeon_acpi_fini(struct radeon_device *rdev) { } 1966 #endif 1967 1968 #include "radeon_object.h" 1969 1970 #endif 1971