1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __RADEON_H__ 29 #define __RADEON_H__ 30 31 #include "radeon_object.h" 32 33 /* TODO: Here are things that needs to be done : 34 * - surface allocator & initializer : (bit like scratch reg) should 35 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings 36 * related to surface 37 * - WB : write back stuff (do it bit like scratch reg things) 38 * - Vblank : look at Jesse's rework and what we should do 39 * - r600/r700: gart & cp 40 * - cs : clean cs ioctl use bitmap & things like that. 41 * - power management stuff 42 * - Barrier in gart code 43 * - Unmappabled vram ? 44 * - TESTING, TESTING, TESTING 45 */ 46 47 #include <asm/atomic.h> 48 #include <linux/wait.h> 49 #include <linux/list.h> 50 #include <linux/kref.h> 51 52 #include "radeon_mode.h" 53 #include "radeon_reg.h" 54 55 /* 56 * Modules parameters. 57 */ 58 extern int radeon_no_wb; 59 extern int radeon_modeset; 60 extern int radeon_dynclks; 61 extern int radeon_r4xx_atom; 62 extern int radeon_agpmode; 63 extern int radeon_vram_limit; 64 extern int radeon_gart_size; 65 extern int radeon_benchmarking; 66 extern int radeon_testing; 67 extern int radeon_connector_table; 68 extern int radeon_tv; 69 70 /* 71 * Copy from radeon_drv.h so we don't have to include both and have conflicting 72 * symbol; 73 */ 74 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 75 #define RADEON_IB_POOL_SIZE 16 76 #define RADEON_DEBUGFS_MAX_NUM_FILES 32 77 #define RADEONFB_CONN_LIMIT 4 78 #define RADEON_BIOS_NUM_SCRATCH 8 79 80 enum radeon_family { 81 CHIP_R100, 82 CHIP_RV100, 83 CHIP_RS100, 84 CHIP_RV200, 85 CHIP_RS200, 86 CHIP_R200, 87 CHIP_RV250, 88 CHIP_RS300, 89 CHIP_RV280, 90 CHIP_R300, 91 CHIP_R350, 92 CHIP_RV350, 93 CHIP_RV380, 94 CHIP_R420, 95 CHIP_R423, 96 CHIP_RV410, 97 CHIP_RS400, 98 CHIP_RS480, 99 CHIP_RS600, 100 CHIP_RS690, 101 CHIP_RS740, 102 CHIP_RV515, 103 CHIP_R520, 104 CHIP_RV530, 105 CHIP_RV560, 106 CHIP_RV570, 107 CHIP_R580, 108 CHIP_R600, 109 CHIP_RV610, 110 CHIP_RV630, 111 CHIP_RV670, 112 CHIP_RV620, 113 CHIP_RV635, 114 CHIP_RS780, 115 CHIP_RS880, 116 CHIP_RV770, 117 CHIP_RV730, 118 CHIP_RV710, 119 CHIP_RV740, 120 CHIP_LAST, 121 }; 122 123 enum radeon_chip_flags { 124 RADEON_FAMILY_MASK = 0x0000ffffUL, 125 RADEON_FLAGS_MASK = 0xffff0000UL, 126 RADEON_IS_MOBILITY = 0x00010000UL, 127 RADEON_IS_IGP = 0x00020000UL, 128 RADEON_SINGLE_CRTC = 0x00040000UL, 129 RADEON_IS_AGP = 0x00080000UL, 130 RADEON_HAS_HIERZ = 0x00100000UL, 131 RADEON_IS_PCIE = 0x00200000UL, 132 RADEON_NEW_MEMMAP = 0x00400000UL, 133 RADEON_IS_PCI = 0x00800000UL, 134 RADEON_IS_IGPGART = 0x01000000UL, 135 }; 136 137 138 /* 139 * Errata workarounds. 140 */ 141 enum radeon_pll_errata { 142 CHIP_ERRATA_R300_CG = 0x00000001, 143 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, 144 CHIP_ERRATA_PLL_DELAY = 0x00000004 145 }; 146 147 148 struct radeon_device; 149 150 151 /* 152 * BIOS. 153 */ 154 bool radeon_get_bios(struct radeon_device *rdev); 155 156 157 /* 158 * Dummy page 159 */ 160 struct radeon_dummy_page { 161 struct page *page; 162 dma_addr_t addr; 163 }; 164 int radeon_dummy_page_init(struct radeon_device *rdev); 165 void radeon_dummy_page_fini(struct radeon_device *rdev); 166 167 168 /* 169 * Clocks 170 */ 171 struct radeon_clock { 172 struct radeon_pll p1pll; 173 struct radeon_pll p2pll; 174 struct radeon_pll spll; 175 struct radeon_pll mpll; 176 /* 10 Khz units */ 177 uint32_t default_mclk; 178 uint32_t default_sclk; 179 }; 180 181 182 /* 183 * Fences. 184 */ 185 struct radeon_fence_driver { 186 uint32_t scratch_reg; 187 atomic_t seq; 188 uint32_t last_seq; 189 unsigned long count_timeout; 190 wait_queue_head_t queue; 191 rwlock_t lock; 192 struct list_head created; 193 struct list_head emited; 194 struct list_head signaled; 195 }; 196 197 struct radeon_fence { 198 struct radeon_device *rdev; 199 struct kref kref; 200 struct list_head list; 201 /* protected by radeon_fence.lock */ 202 uint32_t seq; 203 unsigned long timeout; 204 bool emited; 205 bool signaled; 206 }; 207 208 int radeon_fence_driver_init(struct radeon_device *rdev); 209 void radeon_fence_driver_fini(struct radeon_device *rdev); 210 int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence); 211 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence); 212 void radeon_fence_process(struct radeon_device *rdev); 213 bool radeon_fence_signaled(struct radeon_fence *fence); 214 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); 215 int radeon_fence_wait_next(struct radeon_device *rdev); 216 int radeon_fence_wait_last(struct radeon_device *rdev); 217 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); 218 void radeon_fence_unref(struct radeon_fence **fence); 219 220 /* 221 * Tiling registers 222 */ 223 struct radeon_surface_reg { 224 struct radeon_object *robj; 225 }; 226 227 #define RADEON_GEM_MAX_SURFACES 8 228 229 /* 230 * Radeon buffer. 231 */ 232 struct radeon_object; 233 234 struct radeon_object_list { 235 struct list_head list; 236 struct radeon_object *robj; 237 uint64_t gpu_offset; 238 unsigned rdomain; 239 unsigned wdomain; 240 uint32_t tiling_flags; 241 }; 242 243 int radeon_object_init(struct radeon_device *rdev); 244 void radeon_object_fini(struct radeon_device *rdev); 245 int radeon_object_create(struct radeon_device *rdev, 246 struct drm_gem_object *gobj, 247 unsigned long size, 248 bool kernel, 249 uint32_t domain, 250 bool interruptible, 251 struct radeon_object **robj_ptr); 252 int radeon_object_kmap(struct radeon_object *robj, void **ptr); 253 void radeon_object_kunmap(struct radeon_object *robj); 254 void radeon_object_unref(struct radeon_object **robj); 255 int radeon_object_pin(struct radeon_object *robj, uint32_t domain, 256 uint64_t *gpu_addr); 257 void radeon_object_unpin(struct radeon_object *robj); 258 int radeon_object_wait(struct radeon_object *robj); 259 int radeon_object_busy_domain(struct radeon_object *robj, uint32_t *cur_placement); 260 int radeon_object_evict_vram(struct radeon_device *rdev); 261 int radeon_object_mmap(struct radeon_object *robj, uint64_t *offset); 262 void radeon_object_force_delete(struct radeon_device *rdev); 263 void radeon_object_list_add_object(struct radeon_object_list *lobj, 264 struct list_head *head); 265 int radeon_object_list_validate(struct list_head *head, void *fence); 266 void radeon_object_list_unvalidate(struct list_head *head); 267 void radeon_object_list_clean(struct list_head *head); 268 int radeon_object_fbdev_mmap(struct radeon_object *robj, 269 struct vm_area_struct *vma); 270 unsigned long radeon_object_size(struct radeon_object *robj); 271 void radeon_object_clear_surface_reg(struct radeon_object *robj); 272 int radeon_object_check_tiling(struct radeon_object *robj, bool has_moved, 273 bool force_drop); 274 void radeon_object_set_tiling_flags(struct radeon_object *robj, 275 uint32_t tiling_flags, uint32_t pitch); 276 void radeon_object_get_tiling_flags(struct radeon_object *robj, uint32_t *tiling_flags, uint32_t *pitch); 277 void radeon_bo_move_notify(struct ttm_buffer_object *bo, 278 struct ttm_mem_reg *mem); 279 void radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo); 280 /* 281 * GEM objects. 282 */ 283 struct radeon_gem { 284 struct list_head objects; 285 }; 286 287 int radeon_gem_init(struct radeon_device *rdev); 288 void radeon_gem_fini(struct radeon_device *rdev); 289 int radeon_gem_object_create(struct radeon_device *rdev, int size, 290 int alignment, int initial_domain, 291 bool discardable, bool kernel, 292 bool interruptible, 293 struct drm_gem_object **obj); 294 int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain, 295 uint64_t *gpu_addr); 296 void radeon_gem_object_unpin(struct drm_gem_object *obj); 297 298 299 /* 300 * GART structures, functions & helpers 301 */ 302 struct radeon_mc; 303 304 struct radeon_gart_table_ram { 305 volatile uint32_t *ptr; 306 }; 307 308 struct radeon_gart_table_vram { 309 struct radeon_object *robj; 310 volatile uint32_t *ptr; 311 }; 312 313 union radeon_gart_table { 314 struct radeon_gart_table_ram ram; 315 struct radeon_gart_table_vram vram; 316 }; 317 318 struct radeon_gart { 319 dma_addr_t table_addr; 320 unsigned num_gpu_pages; 321 unsigned num_cpu_pages; 322 unsigned table_size; 323 union radeon_gart_table table; 324 struct page **pages; 325 dma_addr_t *pages_addr; 326 bool ready; 327 }; 328 329 int radeon_gart_table_ram_alloc(struct radeon_device *rdev); 330 void radeon_gart_table_ram_free(struct radeon_device *rdev); 331 int radeon_gart_table_vram_alloc(struct radeon_device *rdev); 332 void radeon_gart_table_vram_free(struct radeon_device *rdev); 333 int radeon_gart_init(struct radeon_device *rdev); 334 void radeon_gart_fini(struct radeon_device *rdev); 335 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, 336 int pages); 337 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, 338 int pages, struct page **pagelist); 339 340 341 /* 342 * GPU MC structures, functions & helpers 343 */ 344 struct radeon_mc { 345 resource_size_t aper_size; 346 resource_size_t aper_base; 347 resource_size_t agp_base; 348 /* for some chips with <= 32MB we need to lie 349 * about vram size near mc fb location */ 350 u64 mc_vram_size; 351 u64 gtt_location; 352 u64 gtt_size; 353 u64 gtt_start; 354 u64 gtt_end; 355 u64 vram_location; 356 u64 vram_start; 357 u64 vram_end; 358 unsigned vram_width; 359 u64 real_vram_size; 360 int vram_mtrr; 361 bool vram_is_ddr; 362 }; 363 364 int radeon_mc_setup(struct radeon_device *rdev); 365 366 367 /* 368 * GPU scratch registers structures, functions & helpers 369 */ 370 struct radeon_scratch { 371 unsigned num_reg; 372 bool free[32]; 373 uint32_t reg[32]; 374 }; 375 376 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); 377 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); 378 379 380 /* 381 * IRQS. 382 */ 383 struct radeon_irq { 384 bool installed; 385 bool sw_int; 386 /* FIXME: use a define max crtc rather than hardcode it */ 387 bool crtc_vblank_int[2]; 388 }; 389 390 int radeon_irq_kms_init(struct radeon_device *rdev); 391 void radeon_irq_kms_fini(struct radeon_device *rdev); 392 393 394 /* 395 * CP & ring. 396 */ 397 struct radeon_ib { 398 struct list_head list; 399 unsigned long idx; 400 uint64_t gpu_addr; 401 struct radeon_fence *fence; 402 volatile uint32_t *ptr; 403 uint32_t length_dw; 404 }; 405 406 /* 407 * locking - 408 * mutex protects scheduled_ibs, ready, alloc_bm 409 */ 410 struct radeon_ib_pool { 411 struct mutex mutex; 412 struct radeon_object *robj; 413 struct list_head scheduled_ibs; 414 struct radeon_ib ibs[RADEON_IB_POOL_SIZE]; 415 bool ready; 416 DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE); 417 }; 418 419 struct radeon_cp { 420 struct radeon_object *ring_obj; 421 volatile uint32_t *ring; 422 unsigned rptr; 423 unsigned wptr; 424 unsigned wptr_old; 425 unsigned ring_size; 426 unsigned ring_free_dw; 427 int count_dw; 428 uint64_t gpu_addr; 429 uint32_t align_mask; 430 uint32_t ptr_mask; 431 struct mutex mutex; 432 bool ready; 433 }; 434 435 struct r600_blit { 436 struct radeon_object *shader_obj; 437 u64 shader_gpu_addr; 438 u32 vs_offset, ps_offset; 439 u32 state_offset; 440 u32 state_len; 441 u32 vb_used, vb_total; 442 struct radeon_ib *vb_ib; 443 }; 444 445 int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib); 446 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib); 447 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib); 448 int radeon_ib_pool_init(struct radeon_device *rdev); 449 void radeon_ib_pool_fini(struct radeon_device *rdev); 450 int radeon_ib_test(struct radeon_device *rdev); 451 /* Ring access between begin & end cannot sleep */ 452 void radeon_ring_free_size(struct radeon_device *rdev); 453 int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw); 454 void radeon_ring_unlock_commit(struct radeon_device *rdev); 455 void radeon_ring_unlock_undo(struct radeon_device *rdev); 456 int radeon_ring_test(struct radeon_device *rdev); 457 int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size); 458 void radeon_ring_fini(struct radeon_device *rdev); 459 460 461 /* 462 * CS. 463 */ 464 struct radeon_cs_reloc { 465 struct drm_gem_object *gobj; 466 struct radeon_object *robj; 467 struct radeon_object_list lobj; 468 uint32_t handle; 469 uint32_t flags; 470 }; 471 472 struct radeon_cs_chunk { 473 uint32_t chunk_id; 474 uint32_t length_dw; 475 uint32_t *kdata; 476 }; 477 478 struct radeon_cs_parser { 479 struct radeon_device *rdev; 480 struct drm_file *filp; 481 /* chunks */ 482 unsigned nchunks; 483 struct radeon_cs_chunk *chunks; 484 uint64_t *chunks_array; 485 /* IB */ 486 unsigned idx; 487 /* relocations */ 488 unsigned nrelocs; 489 struct radeon_cs_reloc *relocs; 490 struct radeon_cs_reloc **relocs_ptr; 491 struct list_head validated; 492 /* indices of various chunks */ 493 int chunk_ib_idx; 494 int chunk_relocs_idx; 495 struct radeon_ib *ib; 496 void *track; 497 unsigned family; 498 }; 499 500 struct radeon_cs_packet { 501 unsigned idx; 502 unsigned type; 503 unsigned reg; 504 unsigned opcode; 505 int count; 506 unsigned one_reg_wr; 507 }; 508 509 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, 510 struct radeon_cs_packet *pkt, 511 unsigned idx, unsigned reg); 512 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, 513 struct radeon_cs_packet *pkt); 514 515 516 /* 517 * AGP 518 */ 519 int radeon_agp_init(struct radeon_device *rdev); 520 void radeon_agp_fini(struct radeon_device *rdev); 521 522 523 /* 524 * Writeback 525 */ 526 struct radeon_wb { 527 struct radeon_object *wb_obj; 528 volatile uint32_t *wb; 529 uint64_t gpu_addr; 530 }; 531 532 /** 533 * struct radeon_pm - power management datas 534 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) 535 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) 536 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) 537 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) 538 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) 539 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) 540 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) 541 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) 542 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) 543 * @sclk: GPU clock Mhz (core bandwith depends of this clock) 544 * @needed_bandwidth: current bandwidth needs 545 * 546 * It keeps track of various data needed to take powermanagement decision. 547 * Bandwith need is used to determine minimun clock of the GPU and memory. 548 * Equation between gpu/memory clock and available bandwidth is hw dependent 549 * (type of memory, bus size, efficiency, ...) 550 */ 551 struct radeon_pm { 552 fixed20_12 max_bandwidth; 553 fixed20_12 igp_sideport_mclk; 554 fixed20_12 igp_system_mclk; 555 fixed20_12 igp_ht_link_clk; 556 fixed20_12 igp_ht_link_width; 557 fixed20_12 k8_bandwidth; 558 fixed20_12 sideport_bandwidth; 559 fixed20_12 ht_bandwidth; 560 fixed20_12 core_bandwidth; 561 fixed20_12 sclk; 562 fixed20_12 needed_bandwidth; 563 }; 564 565 566 /* 567 * Benchmarking 568 */ 569 void radeon_benchmark(struct radeon_device *rdev); 570 571 572 /* 573 * Testing 574 */ 575 void radeon_test_moves(struct radeon_device *rdev); 576 577 578 /* 579 * Debugfs 580 */ 581 int radeon_debugfs_add_files(struct radeon_device *rdev, 582 struct drm_info_list *files, 583 unsigned nfiles); 584 int radeon_debugfs_fence_init(struct radeon_device *rdev); 585 int r100_debugfs_rbbm_init(struct radeon_device *rdev); 586 int r100_debugfs_cp_init(struct radeon_device *rdev); 587 588 589 /* 590 * ASIC specific functions. 591 */ 592 struct radeon_asic { 593 int (*init)(struct radeon_device *rdev); 594 void (*fini)(struct radeon_device *rdev); 595 int (*resume)(struct radeon_device *rdev); 596 int (*suspend)(struct radeon_device *rdev); 597 void (*errata)(struct radeon_device *rdev); 598 void (*vram_info)(struct radeon_device *rdev); 599 void (*vga_set_state)(struct radeon_device *rdev, bool state); 600 int (*gpu_reset)(struct radeon_device *rdev); 601 int (*mc_init)(struct radeon_device *rdev); 602 void (*mc_fini)(struct radeon_device *rdev); 603 int (*wb_init)(struct radeon_device *rdev); 604 void (*wb_fini)(struct radeon_device *rdev); 605 int (*gart_init)(struct radeon_device *rdev); 606 void (*gart_fini)(struct radeon_device *rdev); 607 int (*gart_enable)(struct radeon_device *rdev); 608 void (*gart_disable)(struct radeon_device *rdev); 609 void (*gart_tlb_flush)(struct radeon_device *rdev); 610 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr); 611 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size); 612 void (*cp_fini)(struct radeon_device *rdev); 613 void (*cp_disable)(struct radeon_device *rdev); 614 void (*cp_commit)(struct radeon_device *rdev); 615 void (*ring_start)(struct radeon_device *rdev); 616 int (*ring_test)(struct radeon_device *rdev); 617 void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); 618 int (*ib_test)(struct radeon_device *rdev); 619 int (*irq_set)(struct radeon_device *rdev); 620 int (*irq_process)(struct radeon_device *rdev); 621 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); 622 void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence); 623 int (*cs_parse)(struct radeon_cs_parser *p); 624 int (*copy_blit)(struct radeon_device *rdev, 625 uint64_t src_offset, 626 uint64_t dst_offset, 627 unsigned num_pages, 628 struct radeon_fence *fence); 629 int (*copy_dma)(struct radeon_device *rdev, 630 uint64_t src_offset, 631 uint64_t dst_offset, 632 unsigned num_pages, 633 struct radeon_fence *fence); 634 int (*copy)(struct radeon_device *rdev, 635 uint64_t src_offset, 636 uint64_t dst_offset, 637 unsigned num_pages, 638 struct radeon_fence *fence); 639 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); 640 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); 641 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); 642 void (*set_clock_gating)(struct radeon_device *rdev, int enable); 643 int (*set_surface_reg)(struct radeon_device *rdev, int reg, 644 uint32_t tiling_flags, uint32_t pitch, 645 uint32_t offset, uint32_t obj_size); 646 int (*clear_surface_reg)(struct radeon_device *rdev, int reg); 647 void (*bandwidth_update)(struct radeon_device *rdev); 648 }; 649 650 /* 651 * Asic structures 652 */ 653 struct r100_asic { 654 const unsigned *reg_safe_bm; 655 unsigned reg_safe_bm_size; 656 }; 657 658 struct r300_asic { 659 const unsigned *reg_safe_bm; 660 unsigned reg_safe_bm_size; 661 }; 662 663 struct r600_asic { 664 unsigned max_pipes; 665 unsigned max_tile_pipes; 666 unsigned max_simds; 667 unsigned max_backends; 668 unsigned max_gprs; 669 unsigned max_threads; 670 unsigned max_stack_entries; 671 unsigned max_hw_contexts; 672 unsigned max_gs_threads; 673 unsigned sx_max_export_size; 674 unsigned sx_max_export_pos_size; 675 unsigned sx_max_export_smx_size; 676 unsigned sq_num_cf_insts; 677 }; 678 679 struct rv770_asic { 680 unsigned max_pipes; 681 unsigned max_tile_pipes; 682 unsigned max_simds; 683 unsigned max_backends; 684 unsigned max_gprs; 685 unsigned max_threads; 686 unsigned max_stack_entries; 687 unsigned max_hw_contexts; 688 unsigned max_gs_threads; 689 unsigned sx_max_export_size; 690 unsigned sx_max_export_pos_size; 691 unsigned sx_max_export_smx_size; 692 unsigned sq_num_cf_insts; 693 unsigned sx_num_of_sets; 694 unsigned sc_prim_fifo_size; 695 unsigned sc_hiz_tile_fifo_size; 696 unsigned sc_earlyz_tile_fifo_fize; 697 }; 698 699 union radeon_asic_config { 700 struct r300_asic r300; 701 struct r100_asic r100; 702 struct r600_asic r600; 703 struct rv770_asic rv770; 704 }; 705 706 707 /* 708 * IOCTL. 709 */ 710 int radeon_gem_info_ioctl(struct drm_device *dev, void *data, 711 struct drm_file *filp); 712 int radeon_gem_create_ioctl(struct drm_device *dev, void *data, 713 struct drm_file *filp); 714 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, 715 struct drm_file *file_priv); 716 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, 717 struct drm_file *file_priv); 718 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, 719 struct drm_file *file_priv); 720 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, 721 struct drm_file *file_priv); 722 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, 723 struct drm_file *filp); 724 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, 725 struct drm_file *filp); 726 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, 727 struct drm_file *filp); 728 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 729 struct drm_file *filp); 730 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 731 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, 732 struct drm_file *filp); 733 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, 734 struct drm_file *filp); 735 736 737 /* 738 * Core structure, functions and helpers. 739 */ 740 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); 741 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); 742 743 struct radeon_device { 744 struct device *dev; 745 struct drm_device *ddev; 746 struct pci_dev *pdev; 747 /* ASIC */ 748 union radeon_asic_config config; 749 enum radeon_family family; 750 unsigned long flags; 751 int usec_timeout; 752 enum radeon_pll_errata pll_errata; 753 int num_gb_pipes; 754 int num_z_pipes; 755 int disp_priority; 756 /* BIOS */ 757 uint8_t *bios; 758 bool is_atom_bios; 759 uint16_t bios_header_start; 760 struct radeon_object *stollen_vga_memory; 761 struct fb_info *fbdev_info; 762 struct radeon_object *fbdev_robj; 763 struct radeon_framebuffer *fbdev_rfb; 764 /* Register mmio */ 765 resource_size_t rmmio_base; 766 resource_size_t rmmio_size; 767 void *rmmio; 768 radeon_rreg_t mc_rreg; 769 radeon_wreg_t mc_wreg; 770 radeon_rreg_t pll_rreg; 771 radeon_wreg_t pll_wreg; 772 uint32_t pcie_reg_mask; 773 radeon_rreg_t pciep_rreg; 774 radeon_wreg_t pciep_wreg; 775 struct radeon_clock clock; 776 struct radeon_mc mc; 777 struct radeon_gart gart; 778 struct radeon_mode_info mode_info; 779 struct radeon_scratch scratch; 780 struct radeon_mman mman; 781 struct radeon_fence_driver fence_drv; 782 struct radeon_cp cp; 783 struct radeon_ib_pool ib_pool; 784 struct radeon_irq irq; 785 struct radeon_asic *asic; 786 struct radeon_gem gem; 787 struct radeon_pm pm; 788 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; 789 struct mutex cs_mutex; 790 struct radeon_wb wb; 791 struct radeon_dummy_page dummy_page; 792 bool gpu_lockup; 793 bool shutdown; 794 bool suspend; 795 bool need_dma32; 796 bool new_init_path; 797 bool accel_working; 798 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; 799 const struct firmware *me_fw; /* all family ME firmware */ 800 const struct firmware *pfp_fw; /* r6/700 PFP firmware */ 801 struct r600_blit r600_blit; 802 }; 803 804 int radeon_device_init(struct radeon_device *rdev, 805 struct drm_device *ddev, 806 struct pci_dev *pdev, 807 uint32_t flags); 808 void radeon_device_fini(struct radeon_device *rdev); 809 int radeon_gpu_wait_for_idle(struct radeon_device *rdev); 810 811 /* r600 blit */ 812 int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes); 813 void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence); 814 void r600_kms_blit_copy(struct radeon_device *rdev, 815 u64 src_gpu_addr, u64 dst_gpu_addr, 816 int size_bytes); 817 818 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg) 819 { 820 if (reg < 0x10000) 821 return readl(((void __iomem *)rdev->rmmio) + reg); 822 else { 823 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); 824 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); 825 } 826 } 827 828 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 829 { 830 if (reg < 0x10000) 831 writel(v, ((void __iomem *)rdev->rmmio) + reg); 832 else { 833 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); 834 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); 835 } 836 } 837 838 839 /* 840 * Registers read & write functions. 841 */ 842 #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg)) 843 #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg)) 844 #define RREG32(reg) r100_mm_rreg(rdev, (reg)) 845 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg))) 846 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v)) 847 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 848 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 849 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) 850 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) 851 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) 852 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) 853 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) 854 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) 855 #define WREG32_P(reg, val, mask) \ 856 do { \ 857 uint32_t tmp_ = RREG32(reg); \ 858 tmp_ &= (mask); \ 859 tmp_ |= ((val) & ~(mask)); \ 860 WREG32(reg, tmp_); \ 861 } while (0) 862 #define WREG32_PLL_P(reg, val, mask) \ 863 do { \ 864 uint32_t tmp_ = RREG32_PLL(reg); \ 865 tmp_ &= (mask); \ 866 tmp_ |= ((val) & ~(mask)); \ 867 WREG32_PLL(reg, tmp_); \ 868 } while (0) 869 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg))) 870 871 /* 872 * Indirect registers accessor 873 */ 874 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) 875 { 876 uint32_t r; 877 878 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 879 r = RREG32(RADEON_PCIE_DATA); 880 return r; 881 } 882 883 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 884 { 885 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 886 WREG32(RADEON_PCIE_DATA, (v)); 887 } 888 889 void r100_pll_errata_after_index(struct radeon_device *rdev); 890 891 892 /* 893 * ASICs helpers. 894 */ 895 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ 896 (rdev->pdev->device == 0x5969)) 897 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ 898 (rdev->family == CHIP_RV200) || \ 899 (rdev->family == CHIP_RS100) || \ 900 (rdev->family == CHIP_RS200) || \ 901 (rdev->family == CHIP_RV250) || \ 902 (rdev->family == CHIP_RV280) || \ 903 (rdev->family == CHIP_RS300)) 904 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ 905 (rdev->family == CHIP_RV350) || \ 906 (rdev->family == CHIP_R350) || \ 907 (rdev->family == CHIP_RV380) || \ 908 (rdev->family == CHIP_R420) || \ 909 (rdev->family == CHIP_R423) || \ 910 (rdev->family == CHIP_RV410) || \ 911 (rdev->family == CHIP_RS400) || \ 912 (rdev->family == CHIP_RS480)) 913 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) 914 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) 915 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) 916 917 918 /* 919 * BIOS helpers. 920 */ 921 #define RBIOS8(i) (rdev->bios[i]) 922 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 923 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 924 925 int radeon_combios_init(struct radeon_device *rdev); 926 void radeon_combios_fini(struct radeon_device *rdev); 927 int radeon_atombios_init(struct radeon_device *rdev); 928 void radeon_atombios_fini(struct radeon_device *rdev); 929 930 931 /* 932 * RING helpers. 933 */ 934 static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v) 935 { 936 #if DRM_DEBUG_CODE 937 if (rdev->cp.count_dw <= 0) { 938 DRM_ERROR("radeon: writting more dword to ring than expected !\n"); 939 } 940 #endif 941 rdev->cp.ring[rdev->cp.wptr++] = v; 942 rdev->cp.wptr &= rdev->cp.ptr_mask; 943 rdev->cp.count_dw--; 944 rdev->cp.ring_free_dw--; 945 } 946 947 948 /* 949 * ASICs macro. 950 */ 951 #define radeon_init(rdev) (rdev)->asic->init((rdev)) 952 #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) 953 #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) 954 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) 955 #define radeon_cs_parse(p) rdev->asic->cs_parse((p)) 956 #define radeon_errata(rdev) (rdev)->asic->errata((rdev)) 957 #define radeon_vram_info(rdev) (rdev)->asic->vram_info((rdev)) 958 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) 959 #define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev)) 960 #define radeon_mc_init(rdev) (rdev)->asic->mc_init((rdev)) 961 #define radeon_mc_fini(rdev) (rdev)->asic->mc_fini((rdev)) 962 #define radeon_wb_init(rdev) (rdev)->asic->wb_init((rdev)) 963 #define radeon_wb_fini(rdev) (rdev)->asic->wb_fini((rdev)) 964 #define radeon_gpu_gart_init(rdev) (rdev)->asic->gart_init((rdev)) 965 #define radeon_gpu_gart_fini(rdev) (rdev)->asic->gart_fini((rdev)) 966 #define radeon_gart_enable(rdev) (rdev)->asic->gart_enable((rdev)) 967 #define radeon_gart_disable(rdev) (rdev)->asic->gart_disable((rdev)) 968 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev)) 969 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p)) 970 #define radeon_cp_init(rdev,rsize) (rdev)->asic->cp_init((rdev), (rsize)) 971 #define radeon_cp_fini(rdev) (rdev)->asic->cp_fini((rdev)) 972 #define radeon_cp_disable(rdev) (rdev)->asic->cp_disable((rdev)) 973 #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev)) 974 #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev)) 975 #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev)) 976 #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib)) 977 #define radeon_ib_test(rdev) (rdev)->asic->ib_test((rdev)) 978 #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev)) 979 #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev)) 980 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc)) 981 #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence)) 982 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f)) 983 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f)) 984 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f)) 985 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e)) 986 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e)) 987 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l)) 988 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e)) 989 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s))) 990 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r))) 991 #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev)) 992 993 /* Common functions */ 994 extern int radeon_gart_table_vram_pin(struct radeon_device *rdev); 995 extern int radeon_modeset_init(struct radeon_device *rdev); 996 extern void radeon_modeset_fini(struct radeon_device *rdev); 997 extern bool radeon_card_posted(struct radeon_device *rdev); 998 extern int radeon_clocks_init(struct radeon_device *rdev); 999 extern void radeon_clocks_fini(struct radeon_device *rdev); 1000 extern void radeon_scratch_init(struct radeon_device *rdev); 1001 extern void radeon_surface_init(struct radeon_device *rdev); 1002 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); 1003 1004 /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */ 1005 struct r100_mc_save { 1006 u32 GENMO_WT; 1007 u32 CRTC_EXT_CNTL; 1008 u32 CRTC_GEN_CNTL; 1009 u32 CRTC2_GEN_CNTL; 1010 u32 CUR_OFFSET; 1011 u32 CUR2_OFFSET; 1012 }; 1013 extern void r100_cp_disable(struct radeon_device *rdev); 1014 extern int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); 1015 extern void r100_cp_fini(struct radeon_device *rdev); 1016 extern void r100_pci_gart_tlb_flush(struct radeon_device *rdev); 1017 extern int r100_pci_gart_init(struct radeon_device *rdev); 1018 extern void r100_pci_gart_fini(struct radeon_device *rdev); 1019 extern int r100_pci_gart_enable(struct radeon_device *rdev); 1020 extern void r100_pci_gart_disable(struct radeon_device *rdev); 1021 extern int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); 1022 extern int r100_debugfs_mc_info_init(struct radeon_device *rdev); 1023 extern int r100_gui_wait_for_idle(struct radeon_device *rdev); 1024 extern void r100_ib_fini(struct radeon_device *rdev); 1025 extern int r100_ib_init(struct radeon_device *rdev); 1026 extern void r100_irq_disable(struct radeon_device *rdev); 1027 extern int r100_irq_set(struct radeon_device *rdev); 1028 extern void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save); 1029 extern void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save); 1030 extern void r100_vram_init_sizes(struct radeon_device *rdev); 1031 extern void r100_wb_disable(struct radeon_device *rdev); 1032 extern void r100_wb_fini(struct radeon_device *rdev); 1033 extern int r100_wb_init(struct radeon_device *rdev); 1034 1035 /* r300,r350,rv350,rv370,rv380 */ 1036 extern void r300_set_reg_safe(struct radeon_device *rdev); 1037 extern void r300_mc_program(struct radeon_device *rdev); 1038 extern void r300_vram_info(struct radeon_device *rdev); 1039 extern int rv370_pcie_gart_init(struct radeon_device *rdev); 1040 extern void rv370_pcie_gart_fini(struct radeon_device *rdev); 1041 extern int rv370_pcie_gart_enable(struct radeon_device *rdev); 1042 extern void rv370_pcie_gart_disable(struct radeon_device *rdev); 1043 1044 /* r420,r423,rv410 */ 1045 extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); 1046 extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); 1047 extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev); 1048 1049 /* rv515 */ 1050 extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev); 1051 1052 /* rs690, rs740 */ 1053 extern void rs690_line_buffer_adjust(struct radeon_device *rdev, 1054 struct drm_display_mode *mode1, 1055 struct drm_display_mode *mode2); 1056 1057 /* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */ 1058 extern bool r600_card_posted(struct radeon_device *rdev); 1059 extern void r600_cp_stop(struct radeon_device *rdev); 1060 extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size); 1061 extern int r600_cp_resume(struct radeon_device *rdev); 1062 extern int r600_count_pipe_bits(uint32_t val); 1063 extern int r600_gart_clear_page(struct radeon_device *rdev, int i); 1064 extern int r600_mc_wait_for_idle(struct radeon_device *rdev); 1065 extern int r600_pcie_gart_init(struct radeon_device *rdev); 1066 extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); 1067 extern int r600_ib_test(struct radeon_device *rdev); 1068 extern int r600_ring_test(struct radeon_device *rdev); 1069 extern int r600_wb_init(struct radeon_device *rdev); 1070 extern void r600_wb_fini(struct radeon_device *rdev); 1071 extern void r600_scratch_init(struct radeon_device *rdev); 1072 extern int r600_blit_init(struct radeon_device *rdev); 1073 extern void r600_blit_fini(struct radeon_device *rdev); 1074 extern int r600_cp_init_microcode(struct radeon_device *rdev); 1075 extern int r600_gpu_reset(struct radeon_device *rdev); 1076 1077 #endif 1078