1 /* 2 * Copyright 2009 Advanced Micro Devices, Inc. 3 * Copyright 2009 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 * Jerome Glisse 26 */ 27 #ifndef R600D_H 28 #define R600D_H 29 30 #define CP_PACKET2 0x80000000 31 #define PACKET2_PAD_SHIFT 0 32 #define PACKET2_PAD_MASK (0x3fffffff << 0) 33 34 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 35 36 #define R6XX_MAX_SH_GPRS 256 37 #define R6XX_MAX_TEMP_GPRS 16 38 #define R6XX_MAX_SH_THREADS 256 39 #define R6XX_MAX_SH_STACK_ENTRIES 4096 40 #define R6XX_MAX_BACKENDS 8 41 #define R6XX_MAX_BACKENDS_MASK 0xff 42 #define R6XX_MAX_SIMDS 8 43 #define R6XX_MAX_SIMDS_MASK 0xff 44 #define R6XX_MAX_PIPES 8 45 #define R6XX_MAX_PIPES_MASK 0xff 46 47 /* PTE flags */ 48 #define PTE_VALID (1 << 0) 49 #define PTE_SYSTEM (1 << 1) 50 #define PTE_SNOOPED (1 << 2) 51 #define PTE_READABLE (1 << 5) 52 #define PTE_WRITEABLE (1 << 6) 53 54 /* tiling bits */ 55 #define ARRAY_LINEAR_GENERAL 0x00000000 56 #define ARRAY_LINEAR_ALIGNED 0x00000001 57 #define ARRAY_1D_TILED_THIN1 0x00000002 58 #define ARRAY_2D_TILED_THIN1 0x00000004 59 60 /* Registers */ 61 #define ARB_POP 0x2418 62 #define ENABLE_TC128 (1 << 30) 63 #define ARB_GDEC_RD_CNTL 0x246C 64 65 #define CC_GC_SHADER_PIPE_CONFIG 0x8950 66 #define CC_RB_BACKEND_DISABLE 0x98F4 67 #define BACKEND_DISABLE(x) ((x) << 16) 68 69 #define CB_COLOR0_BASE 0x28040 70 #define CB_COLOR1_BASE 0x28044 71 #define CB_COLOR2_BASE 0x28048 72 #define CB_COLOR3_BASE 0x2804C 73 #define CB_COLOR4_BASE 0x28050 74 #define CB_COLOR5_BASE 0x28054 75 #define CB_COLOR6_BASE 0x28058 76 #define CB_COLOR7_BASE 0x2805C 77 #define CB_COLOR7_FRAG 0x280FC 78 79 #define CB_COLOR0_SIZE 0x28060 80 #define CB_COLOR0_VIEW 0x28080 81 #define CB_COLOR0_INFO 0x280a0 82 # define CB_FORMAT(x) ((x) << 2) 83 # define CB_ARRAY_MODE(x) ((x) << 8) 84 # define CB_SOURCE_FORMAT(x) ((x) << 27) 85 # define CB_SF_EXPORT_FULL 0 86 # define CB_SF_EXPORT_NORM 1 87 #define CB_COLOR0_TILE 0x280c0 88 #define CB_COLOR0_FRAG 0x280e0 89 #define CB_COLOR0_MASK 0x28100 90 91 #define SQ_ALU_CONST_CACHE_PS_0 0x28940 92 #define SQ_ALU_CONST_CACHE_PS_1 0x28944 93 #define SQ_ALU_CONST_CACHE_PS_2 0x28948 94 #define SQ_ALU_CONST_CACHE_PS_3 0x2894c 95 #define SQ_ALU_CONST_CACHE_PS_4 0x28950 96 #define SQ_ALU_CONST_CACHE_PS_5 0x28954 97 #define SQ_ALU_CONST_CACHE_PS_6 0x28958 98 #define SQ_ALU_CONST_CACHE_PS_7 0x2895c 99 #define SQ_ALU_CONST_CACHE_PS_8 0x28960 100 #define SQ_ALU_CONST_CACHE_PS_9 0x28964 101 #define SQ_ALU_CONST_CACHE_PS_10 0x28968 102 #define SQ_ALU_CONST_CACHE_PS_11 0x2896c 103 #define SQ_ALU_CONST_CACHE_PS_12 0x28970 104 #define SQ_ALU_CONST_CACHE_PS_13 0x28974 105 #define SQ_ALU_CONST_CACHE_PS_14 0x28978 106 #define SQ_ALU_CONST_CACHE_PS_15 0x2897c 107 #define SQ_ALU_CONST_CACHE_VS_0 0x28980 108 #define SQ_ALU_CONST_CACHE_VS_1 0x28984 109 #define SQ_ALU_CONST_CACHE_VS_2 0x28988 110 #define SQ_ALU_CONST_CACHE_VS_3 0x2898c 111 #define SQ_ALU_CONST_CACHE_VS_4 0x28990 112 #define SQ_ALU_CONST_CACHE_VS_5 0x28994 113 #define SQ_ALU_CONST_CACHE_VS_6 0x28998 114 #define SQ_ALU_CONST_CACHE_VS_7 0x2899c 115 #define SQ_ALU_CONST_CACHE_VS_8 0x289a0 116 #define SQ_ALU_CONST_CACHE_VS_9 0x289a4 117 #define SQ_ALU_CONST_CACHE_VS_10 0x289a8 118 #define SQ_ALU_CONST_CACHE_VS_11 0x289ac 119 #define SQ_ALU_CONST_CACHE_VS_12 0x289b0 120 #define SQ_ALU_CONST_CACHE_VS_13 0x289b4 121 #define SQ_ALU_CONST_CACHE_VS_14 0x289b8 122 #define SQ_ALU_CONST_CACHE_VS_15 0x289bc 123 #define SQ_ALU_CONST_CACHE_GS_0 0x289c0 124 #define SQ_ALU_CONST_CACHE_GS_1 0x289c4 125 #define SQ_ALU_CONST_CACHE_GS_2 0x289c8 126 #define SQ_ALU_CONST_CACHE_GS_3 0x289cc 127 #define SQ_ALU_CONST_CACHE_GS_4 0x289d0 128 #define SQ_ALU_CONST_CACHE_GS_5 0x289d4 129 #define SQ_ALU_CONST_CACHE_GS_6 0x289d8 130 #define SQ_ALU_CONST_CACHE_GS_7 0x289dc 131 #define SQ_ALU_CONST_CACHE_GS_8 0x289e0 132 #define SQ_ALU_CONST_CACHE_GS_9 0x289e4 133 #define SQ_ALU_CONST_CACHE_GS_10 0x289e8 134 #define SQ_ALU_CONST_CACHE_GS_11 0x289ec 135 #define SQ_ALU_CONST_CACHE_GS_12 0x289f0 136 #define SQ_ALU_CONST_CACHE_GS_13 0x289f4 137 #define SQ_ALU_CONST_CACHE_GS_14 0x289f8 138 #define SQ_ALU_CONST_CACHE_GS_15 0x289fc 139 140 #define CONFIG_MEMSIZE 0x5428 141 #define CONFIG_CNTL 0x5424 142 #define CP_STAT 0x8680 143 #define CP_COHER_BASE 0x85F8 144 #define CP_DEBUG 0xC1FC 145 #define R_0086D8_CP_ME_CNTL 0x86D8 146 #define S_0086D8_CP_ME_HALT(x) (((x) & 1)<<28) 147 #define C_0086D8_CP_ME_HALT(x) ((x) & 0xEFFFFFFF) 148 #define CP_ME_RAM_DATA 0xC160 149 #define CP_ME_RAM_RADDR 0xC158 150 #define CP_ME_RAM_WADDR 0xC15C 151 #define CP_MEQ_THRESHOLDS 0x8764 152 #define MEQ_END(x) ((x) << 16) 153 #define ROQ_END(x) ((x) << 24) 154 #define CP_PERFMON_CNTL 0x87FC 155 #define CP_PFP_UCODE_ADDR 0xC150 156 #define CP_PFP_UCODE_DATA 0xC154 157 #define CP_QUEUE_THRESHOLDS 0x8760 158 #define ROQ_IB1_START(x) ((x) << 0) 159 #define ROQ_IB2_START(x) ((x) << 8) 160 #define CP_RB_BASE 0xC100 161 #define CP_RB_CNTL 0xC104 162 #define RB_BUFSZ(x) ((x) << 0) 163 #define RB_BLKSZ(x) ((x) << 8) 164 #define RB_NO_UPDATE (1 << 27) 165 #define RB_RPTR_WR_ENA (1 << 31) 166 #define BUF_SWAP_32BIT (2 << 16) 167 #define CP_RB_RPTR 0x8700 168 #define CP_RB_RPTR_ADDR 0xC10C 169 #define RB_RPTR_SWAP(x) ((x) << 0) 170 #define CP_RB_RPTR_ADDR_HI 0xC110 171 #define CP_RB_RPTR_WR 0xC108 172 #define CP_RB_WPTR 0xC114 173 #define CP_RB_WPTR_ADDR 0xC118 174 #define CP_RB_WPTR_ADDR_HI 0xC11C 175 #define CP_RB_WPTR_DELAY 0x8704 176 #define CP_ROQ_IB1_STAT 0x8784 177 #define CP_ROQ_IB2_STAT 0x8788 178 #define CP_SEM_WAIT_TIMER 0x85BC 179 180 #define DB_DEBUG 0x9830 181 #define PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31) 182 #define DB_DEPTH_BASE 0x2800C 183 #define DB_HTILE_DATA_BASE 0x28014 184 #define DB_WATERMARKS 0x9838 185 #define DEPTH_FREE(x) ((x) << 0) 186 #define DEPTH_FLUSH(x) ((x) << 5) 187 #define DEPTH_PENDING_FREE(x) ((x) << 15) 188 #define DEPTH_CACHELINE_FREE(x) ((x) << 20) 189 190 #define DCP_TILING_CONFIG 0x6CA0 191 #define PIPE_TILING(x) ((x) << 1) 192 #define BANK_TILING(x) ((x) << 4) 193 #define GROUP_SIZE(x) ((x) << 6) 194 #define ROW_TILING(x) ((x) << 8) 195 #define BANK_SWAPS(x) ((x) << 11) 196 #define SAMPLE_SPLIT(x) ((x) << 14) 197 #define BACKEND_MAP(x) ((x) << 16) 198 199 #define GB_TILING_CONFIG 0x98F0 200 201 #define GC_USER_SHADER_PIPE_CONFIG 0x8954 202 #define INACTIVE_QD_PIPES(x) ((x) << 8) 203 #define INACTIVE_QD_PIPES_MASK 0x0000FF00 204 #define INACTIVE_SIMDS(x) ((x) << 16) 205 #define INACTIVE_SIMDS_MASK 0x00FF0000 206 207 #define SQ_CONFIG 0x8c00 208 # define VC_ENABLE (1 << 0) 209 # define EXPORT_SRC_C (1 << 1) 210 # define DX9_CONSTS (1 << 2) 211 # define ALU_INST_PREFER_VECTOR (1 << 3) 212 # define DX10_CLAMP (1 << 4) 213 # define CLAUSE_SEQ_PRIO(x) ((x) << 8) 214 # define PS_PRIO(x) ((x) << 24) 215 # define VS_PRIO(x) ((x) << 26) 216 # define GS_PRIO(x) ((x) << 28) 217 # define ES_PRIO(x) ((x) << 30) 218 #define SQ_GPR_RESOURCE_MGMT_1 0x8c04 219 # define NUM_PS_GPRS(x) ((x) << 0) 220 # define NUM_VS_GPRS(x) ((x) << 16) 221 # define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) 222 #define SQ_GPR_RESOURCE_MGMT_2 0x8c08 223 # define NUM_GS_GPRS(x) ((x) << 0) 224 # define NUM_ES_GPRS(x) ((x) << 16) 225 #define SQ_THREAD_RESOURCE_MGMT 0x8c0c 226 # define NUM_PS_THREADS(x) ((x) << 0) 227 # define NUM_VS_THREADS(x) ((x) << 8) 228 # define NUM_GS_THREADS(x) ((x) << 16) 229 # define NUM_ES_THREADS(x) ((x) << 24) 230 #define SQ_STACK_RESOURCE_MGMT_1 0x8c10 231 # define NUM_PS_STACK_ENTRIES(x) ((x) << 0) 232 # define NUM_VS_STACK_ENTRIES(x) ((x) << 16) 233 #define SQ_STACK_RESOURCE_MGMT_2 0x8c14 234 # define NUM_GS_STACK_ENTRIES(x) ((x) << 0) 235 # define NUM_ES_STACK_ENTRIES(x) ((x) << 16) 236 #define SQ_ESGS_RING_BASE 0x8c40 237 #define SQ_GSVS_RING_BASE 0x8c48 238 #define SQ_ESTMP_RING_BASE 0x8c50 239 #define SQ_GSTMP_RING_BASE 0x8c58 240 #define SQ_VSTMP_RING_BASE 0x8c60 241 #define SQ_PSTMP_RING_BASE 0x8c68 242 #define SQ_FBUF_RING_BASE 0x8c70 243 #define SQ_REDUC_RING_BASE 0x8c78 244 245 #define GRBM_CNTL 0x8000 246 # define GRBM_READ_TIMEOUT(x) ((x) << 0) 247 #define GRBM_STATUS 0x8010 248 #define CMDFIFO_AVAIL_MASK 0x0000001F 249 #define GUI_ACTIVE (1<<31) 250 #define GRBM_STATUS2 0x8014 251 #define GRBM_SOFT_RESET 0x8020 252 #define SOFT_RESET_CP (1<<0) 253 254 #define CG_THERMAL_STATUS 0x7F4 255 #define ASIC_T(x) ((x) << 0) 256 #define ASIC_T_MASK 0x1FF 257 #define ASIC_T_SHIFT 0 258 259 #define HDP_HOST_PATH_CNTL 0x2C00 260 #define HDP_NONSURFACE_BASE 0x2C04 261 #define HDP_NONSURFACE_INFO 0x2C08 262 #define HDP_NONSURFACE_SIZE 0x2C0C 263 #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 264 #define HDP_TILING_CONFIG 0x2F3C 265 #define HDP_DEBUG1 0x2F34 266 267 #define MC_VM_AGP_TOP 0x2184 268 #define MC_VM_AGP_BOT 0x2188 269 #define MC_VM_AGP_BASE 0x218C 270 #define MC_VM_FB_LOCATION 0x2180 271 #define MC_VM_L1_TLB_MCD_RD_A_CNTL 0x219C 272 #define ENABLE_L1_TLB (1 << 0) 273 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 274 #define ENABLE_L1_STRICT_ORDERING (1 << 2) 275 #define SYSTEM_ACCESS_MODE_MASK 0x000000C0 276 #define SYSTEM_ACCESS_MODE_SHIFT 6 277 #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 6) 278 #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 6) 279 #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 6) 280 #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 6) 281 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 8) 282 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 8) 283 #define ENABLE_SEMAPHORE_MODE (1 << 10) 284 #define ENABLE_WAIT_L2_QUERY (1 << 11) 285 #define EFFECTIVE_L1_TLB_SIZE(x) (((x) & 7) << 12) 286 #define EFFECTIVE_L1_TLB_SIZE_MASK 0x00007000 287 #define EFFECTIVE_L1_TLB_SIZE_SHIFT 12 288 #define EFFECTIVE_L1_QUEUE_SIZE(x) (((x) & 7) << 15) 289 #define EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00038000 290 #define EFFECTIVE_L1_QUEUE_SIZE_SHIFT 15 291 #define MC_VM_L1_TLB_MCD_RD_B_CNTL 0x21A0 292 #define MC_VM_L1_TLB_MCB_RD_GFX_CNTL 0x21FC 293 #define MC_VM_L1_TLB_MCB_RD_HDP_CNTL 0x2204 294 #define MC_VM_L1_TLB_MCB_RD_PDMA_CNTL 0x2208 295 #define MC_VM_L1_TLB_MCB_RD_SEM_CNTL 0x220C 296 #define MC_VM_L1_TLB_MCB_RD_SYS_CNTL 0x2200 297 #define MC_VM_L1_TLB_MCD_WR_A_CNTL 0x21A4 298 #define MC_VM_L1_TLB_MCD_WR_B_CNTL 0x21A8 299 #define MC_VM_L1_TLB_MCB_WR_GFX_CNTL 0x2210 300 #define MC_VM_L1_TLB_MCB_WR_HDP_CNTL 0x2218 301 #define MC_VM_L1_TLB_MCB_WR_PDMA_CNTL 0x221C 302 #define MC_VM_L1_TLB_MCB_WR_SEM_CNTL 0x2220 303 #define MC_VM_L1_TLB_MCB_WR_SYS_CNTL 0x2214 304 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190 305 #define LOGICAL_PAGE_NUMBER_MASK 0x000FFFFF 306 #define LOGICAL_PAGE_NUMBER_SHIFT 0 307 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194 308 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198 309 310 #define PA_CL_ENHANCE 0x8A14 311 #define CLIP_VTX_REORDER_ENA (1 << 0) 312 #define NUM_CLIP_SEQ(x) ((x) << 1) 313 #define PA_SC_AA_CONFIG 0x28C04 314 #define PA_SC_AA_SAMPLE_LOCS_2S 0x8B40 315 #define PA_SC_AA_SAMPLE_LOCS_4S 0x8B44 316 #define PA_SC_AA_SAMPLE_LOCS_8S_WD0 0x8B48 317 #define PA_SC_AA_SAMPLE_LOCS_8S_WD1 0x8B4C 318 #define S0_X(x) ((x) << 0) 319 #define S0_Y(x) ((x) << 4) 320 #define S1_X(x) ((x) << 8) 321 #define S1_Y(x) ((x) << 12) 322 #define S2_X(x) ((x) << 16) 323 #define S2_Y(x) ((x) << 20) 324 #define S3_X(x) ((x) << 24) 325 #define S3_Y(x) ((x) << 28) 326 #define S4_X(x) ((x) << 0) 327 #define S4_Y(x) ((x) << 4) 328 #define S5_X(x) ((x) << 8) 329 #define S5_Y(x) ((x) << 12) 330 #define S6_X(x) ((x) << 16) 331 #define S6_Y(x) ((x) << 20) 332 #define S7_X(x) ((x) << 24) 333 #define S7_Y(x) ((x) << 28) 334 #define PA_SC_CLIPRECT_RULE 0x2820c 335 #define PA_SC_ENHANCE 0x8BF0 336 #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 337 #define FORCE_EOV_MAX_TILE_CNT(x) ((x) << 12) 338 #define PA_SC_LINE_STIPPLE 0x28A0C 339 #define PA_SC_LINE_STIPPLE_STATE 0x8B10 340 #define PA_SC_MODE_CNTL 0x28A4C 341 #define PA_SC_MULTI_CHIP_CNTL 0x8B20 342 343 #define PA_SC_SCREEN_SCISSOR_TL 0x28030 344 #define PA_SC_GENERIC_SCISSOR_TL 0x28240 345 #define PA_SC_WINDOW_SCISSOR_TL 0x28204 346 347 #define PCIE_PORT_INDEX 0x0038 348 #define PCIE_PORT_DATA 0x003C 349 350 #define CHMAP 0x2004 351 #define NOOFCHAN_SHIFT 12 352 #define NOOFCHAN_MASK 0x00003000 353 354 #define RAMCFG 0x2408 355 #define NOOFBANK_SHIFT 0 356 #define NOOFBANK_MASK 0x00000001 357 #define NOOFRANK_SHIFT 1 358 #define NOOFRANK_MASK 0x00000002 359 #define NOOFROWS_SHIFT 2 360 #define NOOFROWS_MASK 0x0000001C 361 #define NOOFCOLS_SHIFT 5 362 #define NOOFCOLS_MASK 0x00000060 363 #define CHANSIZE_SHIFT 7 364 #define CHANSIZE_MASK 0x00000080 365 #define BURSTLENGTH_SHIFT 8 366 #define BURSTLENGTH_MASK 0x00000100 367 #define CHANSIZE_OVERRIDE (1 << 10) 368 369 #define SCRATCH_REG0 0x8500 370 #define SCRATCH_REG1 0x8504 371 #define SCRATCH_REG2 0x8508 372 #define SCRATCH_REG3 0x850C 373 #define SCRATCH_REG4 0x8510 374 #define SCRATCH_REG5 0x8514 375 #define SCRATCH_REG6 0x8518 376 #define SCRATCH_REG7 0x851C 377 #define SCRATCH_UMSK 0x8540 378 #define SCRATCH_ADDR 0x8544 379 380 #define SPI_CONFIG_CNTL 0x9100 381 #define GPR_WRITE_PRIORITY(x) ((x) << 0) 382 #define DISABLE_INTERP_1 (1 << 5) 383 #define SPI_CONFIG_CNTL_1 0x913C 384 #define VTX_DONE_DELAY(x) ((x) << 0) 385 #define INTERP_ONE_PRIM_PER_ROW (1 << 4) 386 #define SPI_INPUT_Z 0x286D8 387 #define SPI_PS_IN_CONTROL_0 0x286CC 388 #define NUM_INTERP(x) ((x)<<0) 389 #define POSITION_ENA (1<<8) 390 #define POSITION_CENTROID (1<<9) 391 #define POSITION_ADDR(x) ((x)<<10) 392 #define PARAM_GEN(x) ((x)<<15) 393 #define PARAM_GEN_ADDR(x) ((x)<<19) 394 #define BARYC_SAMPLE_CNTL(x) ((x)<<26) 395 #define PERSP_GRADIENT_ENA (1<<28) 396 #define LINEAR_GRADIENT_ENA (1<<29) 397 #define POSITION_SAMPLE (1<<30) 398 #define BARYC_AT_SAMPLE_ENA (1<<31) 399 #define SPI_PS_IN_CONTROL_1 0x286D0 400 #define GEN_INDEX_PIX (1<<0) 401 #define GEN_INDEX_PIX_ADDR(x) ((x)<<1) 402 #define FRONT_FACE_ENA (1<<8) 403 #define FRONT_FACE_CHAN(x) ((x)<<9) 404 #define FRONT_FACE_ALL_BITS (1<<11) 405 #define FRONT_FACE_ADDR(x) ((x)<<12) 406 #define FOG_ADDR(x) ((x)<<17) 407 #define FIXED_PT_POSITION_ENA (1<<24) 408 #define FIXED_PT_POSITION_ADDR(x) ((x)<<25) 409 410 #define SQ_MS_FIFO_SIZES 0x8CF0 411 #define CACHE_FIFO_SIZE(x) ((x) << 0) 412 #define FETCH_FIFO_HIWATER(x) ((x) << 8) 413 #define DONE_FIFO_HIWATER(x) ((x) << 16) 414 #define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) 415 #define SQ_PGM_START_ES 0x28880 416 #define SQ_PGM_START_FS 0x28894 417 #define SQ_PGM_START_GS 0x2886C 418 #define SQ_PGM_START_PS 0x28840 419 #define SQ_PGM_RESOURCES_PS 0x28850 420 #define SQ_PGM_EXPORTS_PS 0x28854 421 #define SQ_PGM_CF_OFFSET_PS 0x288cc 422 #define SQ_PGM_START_VS 0x28858 423 #define SQ_PGM_RESOURCES_VS 0x28868 424 #define SQ_PGM_CF_OFFSET_VS 0x288d0 425 426 #define SQ_VTX_CONSTANT_WORD0_0 0x30000 427 #define SQ_VTX_CONSTANT_WORD1_0 0x30004 428 #define SQ_VTX_CONSTANT_WORD2_0 0x30008 429 # define SQ_VTXC_BASE_ADDR_HI(x) ((x) << 0) 430 # define SQ_VTXC_STRIDE(x) ((x) << 8) 431 # define SQ_VTXC_ENDIAN_SWAP(x) ((x) << 30) 432 # define SQ_ENDIAN_NONE 0 433 # define SQ_ENDIAN_8IN16 1 434 # define SQ_ENDIAN_8IN32 2 435 #define SQ_VTX_CONSTANT_WORD3_0 0x3000c 436 #define SQ_VTX_CONSTANT_WORD6_0 0x38018 437 #define S__SQ_VTX_CONSTANT_TYPE(x) (((x) & 3) << 30) 438 #define G__SQ_VTX_CONSTANT_TYPE(x) (((x) >> 30) & 3) 439 #define SQ_TEX_VTX_INVALID_TEXTURE 0x0 440 #define SQ_TEX_VTX_INVALID_BUFFER 0x1 441 #define SQ_TEX_VTX_VALID_TEXTURE 0x2 442 #define SQ_TEX_VTX_VALID_BUFFER 0x3 443 444 445 #define SX_MISC 0x28350 446 #define SX_MEMORY_EXPORT_BASE 0x9010 447 #define SX_DEBUG_1 0x9054 448 #define SMX_EVENT_RELEASE (1 << 0) 449 #define ENABLE_NEW_SMX_ADDRESS (1 << 16) 450 451 #define TA_CNTL_AUX 0x9508 452 #define DISABLE_CUBE_WRAP (1 << 0) 453 #define DISABLE_CUBE_ANISO (1 << 1) 454 #define SYNC_GRADIENT (1 << 24) 455 #define SYNC_WALKER (1 << 25) 456 #define SYNC_ALIGNER (1 << 26) 457 #define BILINEAR_PRECISION_6_BIT (0 << 31) 458 #define BILINEAR_PRECISION_8_BIT (1 << 31) 459 460 #define TC_CNTL 0x9608 461 #define TC_L2_SIZE(x) ((x)<<5) 462 #define L2_DISABLE_LATE_HIT (1<<9) 463 464 465 #define VGT_CACHE_INVALIDATION 0x88C4 466 #define CACHE_INVALIDATION(x) ((x)<<0) 467 #define VC_ONLY 0 468 #define TC_ONLY 1 469 #define VC_AND_TC 2 470 #define VGT_DMA_BASE 0x287E8 471 #define VGT_DMA_BASE_HI 0x287E4 472 #define VGT_ES_PER_GS 0x88CC 473 #define VGT_GS_PER_ES 0x88C8 474 #define VGT_GS_PER_VS 0x88E8 475 #define VGT_GS_VERTEX_REUSE 0x88D4 476 #define VGT_PRIMITIVE_TYPE 0x8958 477 #define VGT_NUM_INSTANCES 0x8974 478 #define VGT_OUT_DEALLOC_CNTL 0x28C5C 479 #define DEALLOC_DIST_MASK 0x0000007F 480 #define VGT_STRMOUT_BASE_OFFSET_0 0x28B10 481 #define VGT_STRMOUT_BASE_OFFSET_1 0x28B14 482 #define VGT_STRMOUT_BASE_OFFSET_2 0x28B18 483 #define VGT_STRMOUT_BASE_OFFSET_3 0x28B1c 484 #define VGT_STRMOUT_BASE_OFFSET_HI_0 0x28B44 485 #define VGT_STRMOUT_BASE_OFFSET_HI_1 0x28B48 486 #define VGT_STRMOUT_BASE_OFFSET_HI_2 0x28B4c 487 #define VGT_STRMOUT_BASE_OFFSET_HI_3 0x28B50 488 #define VGT_STRMOUT_BUFFER_BASE_0 0x28AD8 489 #define VGT_STRMOUT_BUFFER_BASE_1 0x28AE8 490 #define VGT_STRMOUT_BUFFER_BASE_2 0x28AF8 491 #define VGT_STRMOUT_BUFFER_BASE_3 0x28B08 492 #define VGT_STRMOUT_BUFFER_OFFSET_0 0x28ADC 493 #define VGT_STRMOUT_BUFFER_OFFSET_1 0x28AEC 494 #define VGT_STRMOUT_BUFFER_OFFSET_2 0x28AFC 495 #define VGT_STRMOUT_BUFFER_OFFSET_3 0x28B0C 496 #define VGT_STRMOUT_EN 0x28AB0 497 #define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58 498 #define VTX_REUSE_DEPTH_MASK 0x000000FF 499 #define VGT_EVENT_INITIATOR 0x28a90 500 # define CACHE_FLUSH_AND_INV_EVENT_TS (0x14 << 0) 501 # define CACHE_FLUSH_AND_INV_EVENT (0x16 << 0) 502 503 #define VM_CONTEXT0_CNTL 0x1410 504 #define ENABLE_CONTEXT (1 << 0) 505 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 506 #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 507 #define VM_CONTEXT0_INVALIDATION_LOW_ADDR 0x1490 508 #define VM_CONTEXT0_INVALIDATION_HIGH_ADDR 0x14B0 509 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x1574 510 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x1594 511 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x15B4 512 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1554 513 #define VM_CONTEXT0_REQUEST_RESPONSE 0x1470 514 #define REQUEST_TYPE(x) (((x) & 0xf) << 0) 515 #define RESPONSE_TYPE_MASK 0x000000F0 516 #define RESPONSE_TYPE_SHIFT 4 517 #define VM_L2_CNTL 0x1400 518 #define ENABLE_L2_CACHE (1 << 0) 519 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 520 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 521 #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 13) 522 #define VM_L2_CNTL2 0x1404 523 #define INVALIDATE_ALL_L1_TLBS (1 << 0) 524 #define INVALIDATE_L2_CACHE (1 << 1) 525 #define VM_L2_CNTL3 0x1408 526 #define BANK_SELECT_0(x) (((x) & 0x1f) << 0) 527 #define BANK_SELECT_1(x) (((x) & 0x1f) << 5) 528 #define L2_CACHE_UPDATE_MODE(x) (((x) & 3) << 10) 529 #define VM_L2_STATUS 0x140C 530 #define L2_BUSY (1 << 0) 531 532 #define WAIT_UNTIL 0x8040 533 #define WAIT_2D_IDLE_bit (1 << 14) 534 #define WAIT_3D_IDLE_bit (1 << 15) 535 #define WAIT_2D_IDLECLEAN_bit (1 << 16) 536 #define WAIT_3D_IDLECLEAN_bit (1 << 17) 537 538 #define IH_RB_CNTL 0x3e00 539 # define IH_RB_ENABLE (1 << 0) 540 # define IH_IB_SIZE(x) ((x) << 1) /* log2 */ 541 # define IH_RB_FULL_DRAIN_ENABLE (1 << 6) 542 # define IH_WPTR_WRITEBACK_ENABLE (1 << 8) 543 # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ 544 # define IH_WPTR_OVERFLOW_ENABLE (1 << 16) 545 # define IH_WPTR_OVERFLOW_CLEAR (1 << 31) 546 #define IH_RB_BASE 0x3e04 547 #define IH_RB_RPTR 0x3e08 548 #define IH_RB_WPTR 0x3e0c 549 # define RB_OVERFLOW (1 << 0) 550 # define WPTR_OFFSET_MASK 0x3fffc 551 #define IH_RB_WPTR_ADDR_HI 0x3e10 552 #define IH_RB_WPTR_ADDR_LO 0x3e14 553 #define IH_CNTL 0x3e18 554 # define ENABLE_INTR (1 << 0) 555 # define IH_MC_SWAP(x) ((x) << 1) 556 # define IH_MC_SWAP_NONE 0 557 # define IH_MC_SWAP_16BIT 1 558 # define IH_MC_SWAP_32BIT 2 559 # define IH_MC_SWAP_64BIT 3 560 # define RPTR_REARM (1 << 4) 561 # define MC_WRREQ_CREDIT(x) ((x) << 15) 562 # define MC_WR_CLEAN_CNT(x) ((x) << 20) 563 564 #define RLC_CNTL 0x3f00 565 # define RLC_ENABLE (1 << 0) 566 #define RLC_HB_BASE 0x3f10 567 #define RLC_HB_CNTL 0x3f0c 568 #define RLC_HB_RPTR 0x3f20 569 #define RLC_HB_WPTR 0x3f1c 570 #define RLC_HB_WPTR_LSB_ADDR 0x3f14 571 #define RLC_HB_WPTR_MSB_ADDR 0x3f18 572 #define RLC_MC_CNTL 0x3f44 573 #define RLC_UCODE_CNTL 0x3f48 574 #define RLC_UCODE_ADDR 0x3f2c 575 #define RLC_UCODE_DATA 0x3f30 576 577 #define SRBM_SOFT_RESET 0xe60 578 # define SOFT_RESET_RLC (1 << 13) 579 580 #define CP_INT_CNTL 0xc124 581 # define CNTX_BUSY_INT_ENABLE (1 << 19) 582 # define CNTX_EMPTY_INT_ENABLE (1 << 20) 583 # define SCRATCH_INT_ENABLE (1 << 25) 584 # define TIME_STAMP_INT_ENABLE (1 << 26) 585 # define IB2_INT_ENABLE (1 << 29) 586 # define IB1_INT_ENABLE (1 << 30) 587 # define RB_INT_ENABLE (1 << 31) 588 #define CP_INT_STATUS 0xc128 589 # define SCRATCH_INT_STAT (1 << 25) 590 # define TIME_STAMP_INT_STAT (1 << 26) 591 # define IB2_INT_STAT (1 << 29) 592 # define IB1_INT_STAT (1 << 30) 593 # define RB_INT_STAT (1 << 31) 594 595 #define GRBM_INT_CNTL 0x8060 596 # define RDERR_INT_ENABLE (1 << 0) 597 # define WAIT_COUNT_TIMEOUT_INT_ENABLE (1 << 1) 598 # define GUI_IDLE_INT_ENABLE (1 << 19) 599 600 #define INTERRUPT_CNTL 0x5468 601 # define IH_DUMMY_RD_OVERRIDE (1 << 0) 602 # define IH_DUMMY_RD_EN (1 << 1) 603 # define IH_REQ_NONSNOOP_EN (1 << 3) 604 # define GEN_IH_INT_EN (1 << 8) 605 #define INTERRUPT_CNTL2 0x546c 606 607 #define D1MODE_VBLANK_STATUS 0x6534 608 #define D2MODE_VBLANK_STATUS 0x6d34 609 # define DxMODE_VBLANK_OCCURRED (1 << 0) 610 # define DxMODE_VBLANK_ACK (1 << 4) 611 # define DxMODE_VBLANK_STAT (1 << 12) 612 # define DxMODE_VBLANK_INTERRUPT (1 << 16) 613 # define DxMODE_VBLANK_INTERRUPT_TYPE (1 << 17) 614 #define D1MODE_VLINE_STATUS 0x653c 615 #define D2MODE_VLINE_STATUS 0x6d3c 616 # define DxMODE_VLINE_OCCURRED (1 << 0) 617 # define DxMODE_VLINE_ACK (1 << 4) 618 # define DxMODE_VLINE_STAT (1 << 12) 619 # define DxMODE_VLINE_INTERRUPT (1 << 16) 620 # define DxMODE_VLINE_INTERRUPT_TYPE (1 << 17) 621 #define DxMODE_INT_MASK 0x6540 622 # define D1MODE_VBLANK_INT_MASK (1 << 0) 623 # define D1MODE_VLINE_INT_MASK (1 << 4) 624 # define D2MODE_VBLANK_INT_MASK (1 << 8) 625 # define D2MODE_VLINE_INT_MASK (1 << 12) 626 #define DCE3_DISP_INTERRUPT_STATUS 0x7ddc 627 # define DC_HPD1_INTERRUPT (1 << 18) 628 # define DC_HPD2_INTERRUPT (1 << 19) 629 #define DISP_INTERRUPT_STATUS 0x7edc 630 # define LB_D1_VLINE_INTERRUPT (1 << 2) 631 # define LB_D2_VLINE_INTERRUPT (1 << 3) 632 # define LB_D1_VBLANK_INTERRUPT (1 << 4) 633 # define LB_D2_VBLANK_INTERRUPT (1 << 5) 634 # define DACA_AUTODETECT_INTERRUPT (1 << 16) 635 # define DACB_AUTODETECT_INTERRUPT (1 << 17) 636 # define DC_HOT_PLUG_DETECT1_INTERRUPT (1 << 18) 637 # define DC_HOT_PLUG_DETECT2_INTERRUPT (1 << 19) 638 # define DC_I2C_SW_DONE_INTERRUPT (1 << 20) 639 # define DC_I2C_HW_DONE_INTERRUPT (1 << 21) 640 #define DISP_INTERRUPT_STATUS_CONTINUE 0x7ee8 641 #define DCE3_DISP_INTERRUPT_STATUS_CONTINUE 0x7de8 642 # define DC_HPD4_INTERRUPT (1 << 14) 643 # define DC_HPD4_RX_INTERRUPT (1 << 15) 644 # define DC_HPD3_INTERRUPT (1 << 28) 645 # define DC_HPD1_RX_INTERRUPT (1 << 29) 646 # define DC_HPD2_RX_INTERRUPT (1 << 30) 647 #define DCE3_DISP_INTERRUPT_STATUS_CONTINUE2 0x7dec 648 # define DC_HPD3_RX_INTERRUPT (1 << 0) 649 # define DIGA_DP_VID_STREAM_DISABLE_INTERRUPT (1 << 1) 650 # define DIGA_DP_STEER_FIFO_OVERFLOW_INTERRUPT (1 << 2) 651 # define DIGB_DP_VID_STREAM_DISABLE_INTERRUPT (1 << 3) 652 # define DIGB_DP_STEER_FIFO_OVERFLOW_INTERRUPT (1 << 4) 653 # define AUX1_SW_DONE_INTERRUPT (1 << 5) 654 # define AUX1_LS_DONE_INTERRUPT (1 << 6) 655 # define AUX2_SW_DONE_INTERRUPT (1 << 7) 656 # define AUX2_LS_DONE_INTERRUPT (1 << 8) 657 # define AUX3_SW_DONE_INTERRUPT (1 << 9) 658 # define AUX3_LS_DONE_INTERRUPT (1 << 10) 659 # define AUX4_SW_DONE_INTERRUPT (1 << 11) 660 # define AUX4_LS_DONE_INTERRUPT (1 << 12) 661 # define DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT (1 << 13) 662 # define DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT (1 << 14) 663 /* DCE 3.2 */ 664 # define AUX5_SW_DONE_INTERRUPT (1 << 15) 665 # define AUX5_LS_DONE_INTERRUPT (1 << 16) 666 # define AUX6_SW_DONE_INTERRUPT (1 << 17) 667 # define AUX6_LS_DONE_INTERRUPT (1 << 18) 668 # define DC_HPD5_INTERRUPT (1 << 19) 669 # define DC_HPD5_RX_INTERRUPT (1 << 20) 670 # define DC_HPD6_INTERRUPT (1 << 21) 671 # define DC_HPD6_RX_INTERRUPT (1 << 22) 672 673 #define DACA_AUTO_DETECT_CONTROL 0x7828 674 #define DACB_AUTO_DETECT_CONTROL 0x7a28 675 #define DCE3_DACA_AUTO_DETECT_CONTROL 0x7028 676 #define DCE3_DACB_AUTO_DETECT_CONTROL 0x7128 677 # define DACx_AUTODETECT_MODE(x) ((x) << 0) 678 # define DACx_AUTODETECT_MODE_NONE 0 679 # define DACx_AUTODETECT_MODE_CONNECT 1 680 # define DACx_AUTODETECT_MODE_DISCONNECT 2 681 # define DACx_AUTODETECT_FRAME_TIME_COUNTER(x) ((x) << 8) 682 /* bit 18 = R/C, 17 = G/Y, 16 = B/Comp */ 683 # define DACx_AUTODETECT_CHECK_MASK(x) ((x) << 16) 684 685 #define DCE3_DACA_AUTODETECT_INT_CONTROL 0x7038 686 #define DCE3_DACB_AUTODETECT_INT_CONTROL 0x7138 687 #define DACA_AUTODETECT_INT_CONTROL 0x7838 688 #define DACB_AUTODETECT_INT_CONTROL 0x7a38 689 # define DACx_AUTODETECT_ACK (1 << 0) 690 # define DACx_AUTODETECT_INT_ENABLE (1 << 16) 691 692 #define DC_HOT_PLUG_DETECT1_CONTROL 0x7d00 693 #define DC_HOT_PLUG_DETECT2_CONTROL 0x7d10 694 #define DC_HOT_PLUG_DETECT3_CONTROL 0x7d24 695 # define DC_HOT_PLUG_DETECTx_EN (1 << 0) 696 697 #define DC_HOT_PLUG_DETECT1_INT_STATUS 0x7d04 698 #define DC_HOT_PLUG_DETECT2_INT_STATUS 0x7d14 699 #define DC_HOT_PLUG_DETECT3_INT_STATUS 0x7d28 700 # define DC_HOT_PLUG_DETECTx_INT_STATUS (1 << 0) 701 # define DC_HOT_PLUG_DETECTx_SENSE (1 << 1) 702 703 /* DCE 3.0 */ 704 #define DC_HPD1_INT_STATUS 0x7d00 705 #define DC_HPD2_INT_STATUS 0x7d0c 706 #define DC_HPD3_INT_STATUS 0x7d18 707 #define DC_HPD4_INT_STATUS 0x7d24 708 /* DCE 3.2 */ 709 #define DC_HPD5_INT_STATUS 0x7dc0 710 #define DC_HPD6_INT_STATUS 0x7df4 711 # define DC_HPDx_INT_STATUS (1 << 0) 712 # define DC_HPDx_SENSE (1 << 1) 713 # define DC_HPDx_RX_INT_STATUS (1 << 8) 714 715 #define DC_HOT_PLUG_DETECT1_INT_CONTROL 0x7d08 716 #define DC_HOT_PLUG_DETECT2_INT_CONTROL 0x7d18 717 #define DC_HOT_PLUG_DETECT3_INT_CONTROL 0x7d2c 718 # define DC_HOT_PLUG_DETECTx_INT_ACK (1 << 0) 719 # define DC_HOT_PLUG_DETECTx_INT_POLARITY (1 << 8) 720 # define DC_HOT_PLUG_DETECTx_INT_EN (1 << 16) 721 /* DCE 3.0 */ 722 #define DC_HPD1_INT_CONTROL 0x7d04 723 #define DC_HPD2_INT_CONTROL 0x7d10 724 #define DC_HPD3_INT_CONTROL 0x7d1c 725 #define DC_HPD4_INT_CONTROL 0x7d28 726 /* DCE 3.2 */ 727 #define DC_HPD5_INT_CONTROL 0x7dc4 728 #define DC_HPD6_INT_CONTROL 0x7df8 729 # define DC_HPDx_INT_ACK (1 << 0) 730 # define DC_HPDx_INT_POLARITY (1 << 8) 731 # define DC_HPDx_INT_EN (1 << 16) 732 # define DC_HPDx_RX_INT_ACK (1 << 20) 733 # define DC_HPDx_RX_INT_EN (1 << 24) 734 735 /* DCE 3.0 */ 736 #define DC_HPD1_CONTROL 0x7d08 737 #define DC_HPD2_CONTROL 0x7d14 738 #define DC_HPD3_CONTROL 0x7d20 739 #define DC_HPD4_CONTROL 0x7d2c 740 /* DCE 3.2 */ 741 #define DC_HPD5_CONTROL 0x7dc8 742 #define DC_HPD6_CONTROL 0x7dfc 743 # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) 744 # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) 745 /* DCE 3.2 */ 746 # define DC_HPDx_EN (1 << 28) 747 748 #define D1GRPH_INTERRUPT_STATUS 0x6158 749 #define D2GRPH_INTERRUPT_STATUS 0x6958 750 # define DxGRPH_PFLIP_INT_OCCURRED (1 << 0) 751 # define DxGRPH_PFLIP_INT_CLEAR (1 << 8) 752 #define D1GRPH_INTERRUPT_CONTROL 0x615c 753 #define D2GRPH_INTERRUPT_CONTROL 0x695c 754 # define DxGRPH_PFLIP_INT_MASK (1 << 0) 755 # define DxGRPH_PFLIP_INT_TYPE (1 << 8) 756 757 /* PCIE link stuff */ 758 #define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */ 759 # define LC_POINT_7_PLUS_EN (1 << 6) 760 #define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */ 761 # define LC_LINK_WIDTH_SHIFT 0 762 # define LC_LINK_WIDTH_MASK 0x7 763 # define LC_LINK_WIDTH_X0 0 764 # define LC_LINK_WIDTH_X1 1 765 # define LC_LINK_WIDTH_X2 2 766 # define LC_LINK_WIDTH_X4 3 767 # define LC_LINK_WIDTH_X8 4 768 # define LC_LINK_WIDTH_X16 6 769 # define LC_LINK_WIDTH_RD_SHIFT 4 770 # define LC_LINK_WIDTH_RD_MASK 0x70 771 # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) 772 # define LC_RECONFIG_NOW (1 << 8) 773 # define LC_RENEGOTIATION_SUPPORT (1 << 9) 774 # define LC_RENEGOTIATE_EN (1 << 10) 775 # define LC_SHORT_RECONFIG_EN (1 << 11) 776 # define LC_UPCONFIGURE_SUPPORT (1 << 12) 777 # define LC_UPCONFIGURE_DIS (1 << 13) 778 #define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */ 779 # define LC_GEN2_EN_STRAP (1 << 0) 780 # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1) 781 # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5) 782 # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6) 783 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8) 784 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3 785 # define LC_CURRENT_DATA_RATE (1 << 11) 786 # define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14) 787 # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21) 788 # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23) 789 # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24) 790 #define MM_CFGREGS_CNTL 0x544c 791 # define MM_WR_TO_CFG_EN (1 << 3) 792 #define LINK_CNTL2 0x88 /* F0 */ 793 # define TARGET_LINK_SPEED_MASK (0xf << 0) 794 # define SELECTABLE_DEEMPHASIS (1 << 6) 795 796 /* 797 * PM4 798 */ 799 #define PACKET_TYPE0 0 800 #define PACKET_TYPE1 1 801 #define PACKET_TYPE2 2 802 #define PACKET_TYPE3 3 803 804 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 805 #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 806 #define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2) 807 #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 808 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 809 (((reg) >> 2) & 0xFFFF) | \ 810 ((n) & 0x3FFF) << 16) 811 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 812 (((op) & 0xFF) << 8) | \ 813 ((n) & 0x3FFF) << 16) 814 815 /* Packet 3 types */ 816 #define PACKET3_NOP 0x10 817 #define PACKET3_INDIRECT_BUFFER_END 0x17 818 #define PACKET3_SET_PREDICATION 0x20 819 #define PACKET3_REG_RMW 0x21 820 #define PACKET3_COND_EXEC 0x22 821 #define PACKET3_PRED_EXEC 0x23 822 #define PACKET3_START_3D_CMDBUF 0x24 823 #define PACKET3_DRAW_INDEX_2 0x27 824 #define PACKET3_CONTEXT_CONTROL 0x28 825 #define PACKET3_DRAW_INDEX_IMMD_BE 0x29 826 #define PACKET3_INDEX_TYPE 0x2A 827 #define PACKET3_DRAW_INDEX 0x2B 828 #define PACKET3_DRAW_INDEX_AUTO 0x2D 829 #define PACKET3_DRAW_INDEX_IMMD 0x2E 830 #define PACKET3_NUM_INSTANCES 0x2F 831 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 832 #define PACKET3_INDIRECT_BUFFER_MP 0x38 833 #define PACKET3_MEM_SEMAPHORE 0x39 834 #define PACKET3_MPEG_INDEX 0x3A 835 #define PACKET3_WAIT_REG_MEM 0x3C 836 #define PACKET3_MEM_WRITE 0x3D 837 #define PACKET3_INDIRECT_BUFFER 0x32 838 #define PACKET3_SURFACE_SYNC 0x43 839 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 840 # define PACKET3_TC_ACTION_ENA (1 << 23) 841 # define PACKET3_VC_ACTION_ENA (1 << 24) 842 # define PACKET3_CB_ACTION_ENA (1 << 25) 843 # define PACKET3_DB_ACTION_ENA (1 << 26) 844 # define PACKET3_SH_ACTION_ENA (1 << 27) 845 # define PACKET3_SMX_ACTION_ENA (1 << 28) 846 #define PACKET3_ME_INITIALIZE 0x44 847 #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 848 #define PACKET3_COND_WRITE 0x45 849 #define PACKET3_EVENT_WRITE 0x46 850 #define EVENT_TYPE(x) ((x) << 0) 851 #define EVENT_INDEX(x) ((x) << 8) 852 /* 0 - any non-TS event 853 * 1 - ZPASS_DONE 854 * 2 - SAMPLE_PIPELINESTAT 855 * 3 - SAMPLE_STREAMOUTSTAT* 856 * 4 - *S_PARTIAL_FLUSH 857 * 5 - TS events 858 */ 859 #define PACKET3_EVENT_WRITE_EOP 0x47 860 #define DATA_SEL(x) ((x) << 29) 861 /* 0 - discard 862 * 1 - send low 32bit data 863 * 2 - send 64bit data 864 * 3 - send 64bit counter value 865 */ 866 #define INT_SEL(x) ((x) << 24) 867 /* 0 - none 868 * 1 - interrupt only (DATA_SEL = 0) 869 * 2 - interrupt when data write is confirmed 870 */ 871 #define PACKET3_ONE_REG_WRITE 0x57 872 #define PACKET3_SET_CONFIG_REG 0x68 873 #define PACKET3_SET_CONFIG_REG_OFFSET 0x00008000 874 #define PACKET3_SET_CONFIG_REG_END 0x0000ac00 875 #define PACKET3_SET_CONTEXT_REG 0x69 876 #define PACKET3_SET_CONTEXT_REG_OFFSET 0x00028000 877 #define PACKET3_SET_CONTEXT_REG_END 0x00029000 878 #define PACKET3_SET_ALU_CONST 0x6A 879 #define PACKET3_SET_ALU_CONST_OFFSET 0x00030000 880 #define PACKET3_SET_ALU_CONST_END 0x00032000 881 #define PACKET3_SET_BOOL_CONST 0x6B 882 #define PACKET3_SET_BOOL_CONST_OFFSET 0x0003e380 883 #define PACKET3_SET_BOOL_CONST_END 0x00040000 884 #define PACKET3_SET_LOOP_CONST 0x6C 885 #define PACKET3_SET_LOOP_CONST_OFFSET 0x0003e200 886 #define PACKET3_SET_LOOP_CONST_END 0x0003e380 887 #define PACKET3_SET_RESOURCE 0x6D 888 #define PACKET3_SET_RESOURCE_OFFSET 0x00038000 889 #define PACKET3_SET_RESOURCE_END 0x0003c000 890 #define PACKET3_SET_SAMPLER 0x6E 891 #define PACKET3_SET_SAMPLER_OFFSET 0x0003c000 892 #define PACKET3_SET_SAMPLER_END 0x0003cff0 893 #define PACKET3_SET_CTL_CONST 0x6F 894 #define PACKET3_SET_CTL_CONST_OFFSET 0x0003cff0 895 #define PACKET3_SET_CTL_CONST_END 0x0003e200 896 #define PACKET3_SURFACE_BASE_UPDATE 0x73 897 898 899 #define R_008020_GRBM_SOFT_RESET 0x8020 900 #define S_008020_SOFT_RESET_CP(x) (((x) & 1) << 0) 901 #define S_008020_SOFT_RESET_CB(x) (((x) & 1) << 1) 902 #define S_008020_SOFT_RESET_CR(x) (((x) & 1) << 2) 903 #define S_008020_SOFT_RESET_DB(x) (((x) & 1) << 3) 904 #define S_008020_SOFT_RESET_PA(x) (((x) & 1) << 5) 905 #define S_008020_SOFT_RESET_SC(x) (((x) & 1) << 6) 906 #define S_008020_SOFT_RESET_SMX(x) (((x) & 1) << 7) 907 #define S_008020_SOFT_RESET_SPI(x) (((x) & 1) << 8) 908 #define S_008020_SOFT_RESET_SH(x) (((x) & 1) << 9) 909 #define S_008020_SOFT_RESET_SX(x) (((x) & 1) << 10) 910 #define S_008020_SOFT_RESET_TC(x) (((x) & 1) << 11) 911 #define S_008020_SOFT_RESET_TA(x) (((x) & 1) << 12) 912 #define S_008020_SOFT_RESET_VC(x) (((x) & 1) << 13) 913 #define S_008020_SOFT_RESET_VGT(x) (((x) & 1) << 14) 914 #define R_008010_GRBM_STATUS 0x8010 915 #define S_008010_CMDFIFO_AVAIL(x) (((x) & 0x1F) << 0) 916 #define S_008010_CP_RQ_PENDING(x) (((x) & 1) << 6) 917 #define S_008010_CF_RQ_PENDING(x) (((x) & 1) << 7) 918 #define S_008010_PF_RQ_PENDING(x) (((x) & 1) << 8) 919 #define S_008010_GRBM_EE_BUSY(x) (((x) & 1) << 10) 920 #define S_008010_VC_BUSY(x) (((x) & 1) << 11) 921 #define S_008010_DB03_CLEAN(x) (((x) & 1) << 12) 922 #define S_008010_CB03_CLEAN(x) (((x) & 1) << 13) 923 #define S_008010_VGT_BUSY_NO_DMA(x) (((x) & 1) << 16) 924 #define S_008010_VGT_BUSY(x) (((x) & 1) << 17) 925 #define S_008010_TA03_BUSY(x) (((x) & 1) << 18) 926 #define S_008010_TC_BUSY(x) (((x) & 1) << 19) 927 #define S_008010_SX_BUSY(x) (((x) & 1) << 20) 928 #define S_008010_SH_BUSY(x) (((x) & 1) << 21) 929 #define S_008010_SPI03_BUSY(x) (((x) & 1) << 22) 930 #define S_008010_SMX_BUSY(x) (((x) & 1) << 23) 931 #define S_008010_SC_BUSY(x) (((x) & 1) << 24) 932 #define S_008010_PA_BUSY(x) (((x) & 1) << 25) 933 #define S_008010_DB03_BUSY(x) (((x) & 1) << 26) 934 #define S_008010_CR_BUSY(x) (((x) & 1) << 27) 935 #define S_008010_CP_COHERENCY_BUSY(x) (((x) & 1) << 28) 936 #define S_008010_CP_BUSY(x) (((x) & 1) << 29) 937 #define S_008010_CB03_BUSY(x) (((x) & 1) << 30) 938 #define S_008010_GUI_ACTIVE(x) (((x) & 1) << 31) 939 #define G_008010_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x1F) 940 #define G_008010_CP_RQ_PENDING(x) (((x) >> 6) & 1) 941 #define G_008010_CF_RQ_PENDING(x) (((x) >> 7) & 1) 942 #define G_008010_PF_RQ_PENDING(x) (((x) >> 8) & 1) 943 #define G_008010_GRBM_EE_BUSY(x) (((x) >> 10) & 1) 944 #define G_008010_VC_BUSY(x) (((x) >> 11) & 1) 945 #define G_008010_DB03_CLEAN(x) (((x) >> 12) & 1) 946 #define G_008010_CB03_CLEAN(x) (((x) >> 13) & 1) 947 #define G_008010_VGT_BUSY_NO_DMA(x) (((x) >> 16) & 1) 948 #define G_008010_VGT_BUSY(x) (((x) >> 17) & 1) 949 #define G_008010_TA03_BUSY(x) (((x) >> 18) & 1) 950 #define G_008010_TC_BUSY(x) (((x) >> 19) & 1) 951 #define G_008010_SX_BUSY(x) (((x) >> 20) & 1) 952 #define G_008010_SH_BUSY(x) (((x) >> 21) & 1) 953 #define G_008010_SPI03_BUSY(x) (((x) >> 22) & 1) 954 #define G_008010_SMX_BUSY(x) (((x) >> 23) & 1) 955 #define G_008010_SC_BUSY(x) (((x) >> 24) & 1) 956 #define G_008010_PA_BUSY(x) (((x) >> 25) & 1) 957 #define G_008010_DB03_BUSY(x) (((x) >> 26) & 1) 958 #define G_008010_CR_BUSY(x) (((x) >> 27) & 1) 959 #define G_008010_CP_COHERENCY_BUSY(x) (((x) >> 28) & 1) 960 #define G_008010_CP_BUSY(x) (((x) >> 29) & 1) 961 #define G_008010_CB03_BUSY(x) (((x) >> 30) & 1) 962 #define G_008010_GUI_ACTIVE(x) (((x) >> 31) & 1) 963 #define R_008014_GRBM_STATUS2 0x8014 964 #define S_008014_CR_CLEAN(x) (((x) & 1) << 0) 965 #define S_008014_SMX_CLEAN(x) (((x) & 1) << 1) 966 #define S_008014_SPI0_BUSY(x) (((x) & 1) << 8) 967 #define S_008014_SPI1_BUSY(x) (((x) & 1) << 9) 968 #define S_008014_SPI2_BUSY(x) (((x) & 1) << 10) 969 #define S_008014_SPI3_BUSY(x) (((x) & 1) << 11) 970 #define S_008014_TA0_BUSY(x) (((x) & 1) << 12) 971 #define S_008014_TA1_BUSY(x) (((x) & 1) << 13) 972 #define S_008014_TA2_BUSY(x) (((x) & 1) << 14) 973 #define S_008014_TA3_BUSY(x) (((x) & 1) << 15) 974 #define S_008014_DB0_BUSY(x) (((x) & 1) << 16) 975 #define S_008014_DB1_BUSY(x) (((x) & 1) << 17) 976 #define S_008014_DB2_BUSY(x) (((x) & 1) << 18) 977 #define S_008014_DB3_BUSY(x) (((x) & 1) << 19) 978 #define S_008014_CB0_BUSY(x) (((x) & 1) << 20) 979 #define S_008014_CB1_BUSY(x) (((x) & 1) << 21) 980 #define S_008014_CB2_BUSY(x) (((x) & 1) << 22) 981 #define S_008014_CB3_BUSY(x) (((x) & 1) << 23) 982 #define G_008014_CR_CLEAN(x) (((x) >> 0) & 1) 983 #define G_008014_SMX_CLEAN(x) (((x) >> 1) & 1) 984 #define G_008014_SPI0_BUSY(x) (((x) >> 8) & 1) 985 #define G_008014_SPI1_BUSY(x) (((x) >> 9) & 1) 986 #define G_008014_SPI2_BUSY(x) (((x) >> 10) & 1) 987 #define G_008014_SPI3_BUSY(x) (((x) >> 11) & 1) 988 #define G_008014_TA0_BUSY(x) (((x) >> 12) & 1) 989 #define G_008014_TA1_BUSY(x) (((x) >> 13) & 1) 990 #define G_008014_TA2_BUSY(x) (((x) >> 14) & 1) 991 #define G_008014_TA3_BUSY(x) (((x) >> 15) & 1) 992 #define G_008014_DB0_BUSY(x) (((x) >> 16) & 1) 993 #define G_008014_DB1_BUSY(x) (((x) >> 17) & 1) 994 #define G_008014_DB2_BUSY(x) (((x) >> 18) & 1) 995 #define G_008014_DB3_BUSY(x) (((x) >> 19) & 1) 996 #define G_008014_CB0_BUSY(x) (((x) >> 20) & 1) 997 #define G_008014_CB1_BUSY(x) (((x) >> 21) & 1) 998 #define G_008014_CB2_BUSY(x) (((x) >> 22) & 1) 999 #define G_008014_CB3_BUSY(x) (((x) >> 23) & 1) 1000 #define R_000E50_SRBM_STATUS 0x0E50 1001 #define G_000E50_RLC_RQ_PENDING(x) (((x) >> 3) & 1) 1002 #define G_000E50_RCU_RQ_PENDING(x) (((x) >> 4) & 1) 1003 #define G_000E50_GRBM_RQ_PENDING(x) (((x) >> 5) & 1) 1004 #define G_000E50_HI_RQ_PENDING(x) (((x) >> 6) & 1) 1005 #define G_000E50_IO_EXTERN_SIGNAL(x) (((x) >> 7) & 1) 1006 #define G_000E50_VMC_BUSY(x) (((x) >> 8) & 1) 1007 #define G_000E50_MCB_BUSY(x) (((x) >> 9) & 1) 1008 #define G_000E50_MCDZ_BUSY(x) (((x) >> 10) & 1) 1009 #define G_000E50_MCDY_BUSY(x) (((x) >> 11) & 1) 1010 #define G_000E50_MCDX_BUSY(x) (((x) >> 12) & 1) 1011 #define G_000E50_MCDW_BUSY(x) (((x) >> 13) & 1) 1012 #define G_000E50_SEM_BUSY(x) (((x) >> 14) & 1) 1013 #define G_000E50_RLC_BUSY(x) (((x) >> 15) & 1) 1014 #define G_000E50_BIF_BUSY(x) (((x) >> 29) & 1) 1015 #define R_000E60_SRBM_SOFT_RESET 0x0E60 1016 #define S_000E60_SOFT_RESET_BIF(x) (((x) & 1) << 1) 1017 #define S_000E60_SOFT_RESET_CG(x) (((x) & 1) << 2) 1018 #define S_000E60_SOFT_RESET_CMC(x) (((x) & 1) << 3) 1019 #define S_000E60_SOFT_RESET_CSC(x) (((x) & 1) << 4) 1020 #define S_000E60_SOFT_RESET_DC(x) (((x) & 1) << 5) 1021 #define S_000E60_SOFT_RESET_GRBM(x) (((x) & 1) << 8) 1022 #define S_000E60_SOFT_RESET_HDP(x) (((x) & 1) << 9) 1023 #define S_000E60_SOFT_RESET_IH(x) (((x) & 1) << 10) 1024 #define S_000E60_SOFT_RESET_MC(x) (((x) & 1) << 11) 1025 #define S_000E60_SOFT_RESET_RLC(x) (((x) & 1) << 13) 1026 #define S_000E60_SOFT_RESET_ROM(x) (((x) & 1) << 14) 1027 #define S_000E60_SOFT_RESET_SEM(x) (((x) & 1) << 15) 1028 #define S_000E60_SOFT_RESET_TSC(x) (((x) & 1) << 16) 1029 #define S_000E60_SOFT_RESET_VMC(x) (((x) & 1) << 17) 1030 1031 #define R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 1032 1033 #define R_028C04_PA_SC_AA_CONFIG 0x028C04 1034 #define S_028C04_MSAA_NUM_SAMPLES(x) (((x) & 0x3) << 0) 1035 #define G_028C04_MSAA_NUM_SAMPLES(x) (((x) >> 0) & 0x3) 1036 #define C_028C04_MSAA_NUM_SAMPLES 0xFFFFFFFC 1037 #define S_028C04_AA_MASK_CENTROID_DTMN(x) (((x) & 0x1) << 4) 1038 #define G_028C04_AA_MASK_CENTROID_DTMN(x) (((x) >> 4) & 0x1) 1039 #define C_028C04_AA_MASK_CENTROID_DTMN 0xFFFFFFEF 1040 #define S_028C04_MAX_SAMPLE_DIST(x) (((x) & 0xF) << 13) 1041 #define G_028C04_MAX_SAMPLE_DIST(x) (((x) >> 13) & 0xF) 1042 #define C_028C04_MAX_SAMPLE_DIST 0xFFFE1FFF 1043 #define R_0280E0_CB_COLOR0_FRAG 0x0280E0 1044 #define S_0280E0_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0) 1045 #define G_0280E0_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF) 1046 #define C_0280E0_BASE_256B 0x00000000 1047 #define R_0280E4_CB_COLOR1_FRAG 0x0280E4 1048 #define R_0280E8_CB_COLOR2_FRAG 0x0280E8 1049 #define R_0280EC_CB_COLOR3_FRAG 0x0280EC 1050 #define R_0280F0_CB_COLOR4_FRAG 0x0280F0 1051 #define R_0280F4_CB_COLOR5_FRAG 0x0280F4 1052 #define R_0280F8_CB_COLOR6_FRAG 0x0280F8 1053 #define R_0280FC_CB_COLOR7_FRAG 0x0280FC 1054 #define R_0280C0_CB_COLOR0_TILE 0x0280C0 1055 #define S_0280C0_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0) 1056 #define G_0280C0_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF) 1057 #define C_0280C0_BASE_256B 0x00000000 1058 #define R_0280C4_CB_COLOR1_TILE 0x0280C4 1059 #define R_0280C8_CB_COLOR2_TILE 0x0280C8 1060 #define R_0280CC_CB_COLOR3_TILE 0x0280CC 1061 #define R_0280D0_CB_COLOR4_TILE 0x0280D0 1062 #define R_0280D4_CB_COLOR5_TILE 0x0280D4 1063 #define R_0280D8_CB_COLOR6_TILE 0x0280D8 1064 #define R_0280DC_CB_COLOR7_TILE 0x0280DC 1065 #define R_0280A0_CB_COLOR0_INFO 0x0280A0 1066 #define S_0280A0_ENDIAN(x) (((x) & 0x3) << 0) 1067 #define G_0280A0_ENDIAN(x) (((x) >> 0) & 0x3) 1068 #define C_0280A0_ENDIAN 0xFFFFFFFC 1069 #define S_0280A0_FORMAT(x) (((x) & 0x3F) << 2) 1070 #define G_0280A0_FORMAT(x) (((x) >> 2) & 0x3F) 1071 #define C_0280A0_FORMAT 0xFFFFFF03 1072 #define V_0280A0_COLOR_INVALID 0x00000000 1073 #define V_0280A0_COLOR_8 0x00000001 1074 #define V_0280A0_COLOR_4_4 0x00000002 1075 #define V_0280A0_COLOR_3_3_2 0x00000003 1076 #define V_0280A0_COLOR_16 0x00000005 1077 #define V_0280A0_COLOR_16_FLOAT 0x00000006 1078 #define V_0280A0_COLOR_8_8 0x00000007 1079 #define V_0280A0_COLOR_5_6_5 0x00000008 1080 #define V_0280A0_COLOR_6_5_5 0x00000009 1081 #define V_0280A0_COLOR_1_5_5_5 0x0000000A 1082 #define V_0280A0_COLOR_4_4_4_4 0x0000000B 1083 #define V_0280A0_COLOR_5_5_5_1 0x0000000C 1084 #define V_0280A0_COLOR_32 0x0000000D 1085 #define V_0280A0_COLOR_32_FLOAT 0x0000000E 1086 #define V_0280A0_COLOR_16_16 0x0000000F 1087 #define V_0280A0_COLOR_16_16_FLOAT 0x00000010 1088 #define V_0280A0_COLOR_8_24 0x00000011 1089 #define V_0280A0_COLOR_8_24_FLOAT 0x00000012 1090 #define V_0280A0_COLOR_24_8 0x00000013 1091 #define V_0280A0_COLOR_24_8_FLOAT 0x00000014 1092 #define V_0280A0_COLOR_10_11_11 0x00000015 1093 #define V_0280A0_COLOR_10_11_11_FLOAT 0x00000016 1094 #define V_0280A0_COLOR_11_11_10 0x00000017 1095 #define V_0280A0_COLOR_11_11_10_FLOAT 0x00000018 1096 #define V_0280A0_COLOR_2_10_10_10 0x00000019 1097 #define V_0280A0_COLOR_8_8_8_8 0x0000001A 1098 #define V_0280A0_COLOR_10_10_10_2 0x0000001B 1099 #define V_0280A0_COLOR_X24_8_32_FLOAT 0x0000001C 1100 #define V_0280A0_COLOR_32_32 0x0000001D 1101 #define V_0280A0_COLOR_32_32_FLOAT 0x0000001E 1102 #define V_0280A0_COLOR_16_16_16_16 0x0000001F 1103 #define V_0280A0_COLOR_16_16_16_16_FLOAT 0x00000020 1104 #define V_0280A0_COLOR_32_32_32_32 0x00000022 1105 #define V_0280A0_COLOR_32_32_32_32_FLOAT 0x00000023 1106 #define S_0280A0_ARRAY_MODE(x) (((x) & 0xF) << 8) 1107 #define G_0280A0_ARRAY_MODE(x) (((x) >> 8) & 0xF) 1108 #define C_0280A0_ARRAY_MODE 0xFFFFF0FF 1109 #define V_0280A0_ARRAY_LINEAR_GENERAL 0x00000000 1110 #define V_0280A0_ARRAY_LINEAR_ALIGNED 0x00000001 1111 #define V_0280A0_ARRAY_1D_TILED_THIN1 0x00000002 1112 #define V_0280A0_ARRAY_2D_TILED_THIN1 0x00000004 1113 #define S_0280A0_NUMBER_TYPE(x) (((x) & 0x7) << 12) 1114 #define G_0280A0_NUMBER_TYPE(x) (((x) >> 12) & 0x7) 1115 #define C_0280A0_NUMBER_TYPE 0xFFFF8FFF 1116 #define S_0280A0_READ_SIZE(x) (((x) & 0x1) << 15) 1117 #define G_0280A0_READ_SIZE(x) (((x) >> 15) & 0x1) 1118 #define C_0280A0_READ_SIZE 0xFFFF7FFF 1119 #define S_0280A0_COMP_SWAP(x) (((x) & 0x3) << 16) 1120 #define G_0280A0_COMP_SWAP(x) (((x) >> 16) & 0x3) 1121 #define C_0280A0_COMP_SWAP 0xFFFCFFFF 1122 #define S_0280A0_TILE_MODE(x) (((x) & 0x3) << 18) 1123 #define G_0280A0_TILE_MODE(x) (((x) >> 18) & 0x3) 1124 #define C_0280A0_TILE_MODE 0xFFF3FFFF 1125 #define S_0280A0_BLEND_CLAMP(x) (((x) & 0x1) << 20) 1126 #define G_0280A0_BLEND_CLAMP(x) (((x) >> 20) & 0x1) 1127 #define C_0280A0_BLEND_CLAMP 0xFFEFFFFF 1128 #define S_0280A0_CLEAR_COLOR(x) (((x) & 0x1) << 21) 1129 #define G_0280A0_CLEAR_COLOR(x) (((x) >> 21) & 0x1) 1130 #define C_0280A0_CLEAR_COLOR 0xFFDFFFFF 1131 #define S_0280A0_BLEND_BYPASS(x) (((x) & 0x1) << 22) 1132 #define G_0280A0_BLEND_BYPASS(x) (((x) >> 22) & 0x1) 1133 #define C_0280A0_BLEND_BYPASS 0xFFBFFFFF 1134 #define S_0280A0_BLEND_FLOAT32(x) (((x) & 0x1) << 23) 1135 #define G_0280A0_BLEND_FLOAT32(x) (((x) >> 23) & 0x1) 1136 #define C_0280A0_BLEND_FLOAT32 0xFF7FFFFF 1137 #define S_0280A0_SIMPLE_FLOAT(x) (((x) & 0x1) << 24) 1138 #define G_0280A0_SIMPLE_FLOAT(x) (((x) >> 24) & 0x1) 1139 #define C_0280A0_SIMPLE_FLOAT 0xFEFFFFFF 1140 #define S_0280A0_ROUND_MODE(x) (((x) & 0x1) << 25) 1141 #define G_0280A0_ROUND_MODE(x) (((x) >> 25) & 0x1) 1142 #define C_0280A0_ROUND_MODE 0xFDFFFFFF 1143 #define S_0280A0_TILE_COMPACT(x) (((x) & 0x1) << 26) 1144 #define G_0280A0_TILE_COMPACT(x) (((x) >> 26) & 0x1) 1145 #define C_0280A0_TILE_COMPACT 0xFBFFFFFF 1146 #define S_0280A0_SOURCE_FORMAT(x) (((x) & 0x1) << 27) 1147 #define G_0280A0_SOURCE_FORMAT(x) (((x) >> 27) & 0x1) 1148 #define C_0280A0_SOURCE_FORMAT 0xF7FFFFFF 1149 #define R_0280A4_CB_COLOR1_INFO 0x0280A4 1150 #define R_0280A8_CB_COLOR2_INFO 0x0280A8 1151 #define R_0280AC_CB_COLOR3_INFO 0x0280AC 1152 #define R_0280B0_CB_COLOR4_INFO 0x0280B0 1153 #define R_0280B4_CB_COLOR5_INFO 0x0280B4 1154 #define R_0280B8_CB_COLOR6_INFO 0x0280B8 1155 #define R_0280BC_CB_COLOR7_INFO 0x0280BC 1156 #define R_028060_CB_COLOR0_SIZE 0x028060 1157 #define S_028060_PITCH_TILE_MAX(x) (((x) & 0x3FF) << 0) 1158 #define G_028060_PITCH_TILE_MAX(x) (((x) >> 0) & 0x3FF) 1159 #define C_028060_PITCH_TILE_MAX 0xFFFFFC00 1160 #define S_028060_SLICE_TILE_MAX(x) (((x) & 0xFFFFF) << 10) 1161 #define G_028060_SLICE_TILE_MAX(x) (((x) >> 10) & 0xFFFFF) 1162 #define C_028060_SLICE_TILE_MAX 0xC00003FF 1163 #define R_028064_CB_COLOR1_SIZE 0x028064 1164 #define R_028068_CB_COLOR2_SIZE 0x028068 1165 #define R_02806C_CB_COLOR3_SIZE 0x02806C 1166 #define R_028070_CB_COLOR4_SIZE 0x028070 1167 #define R_028074_CB_COLOR5_SIZE 0x028074 1168 #define R_028078_CB_COLOR6_SIZE 0x028078 1169 #define R_02807C_CB_COLOR7_SIZE 0x02807C 1170 #define R_028238_CB_TARGET_MASK 0x028238 1171 #define S_028238_TARGET0_ENABLE(x) (((x) & 0xF) << 0) 1172 #define G_028238_TARGET0_ENABLE(x) (((x) >> 0) & 0xF) 1173 #define C_028238_TARGET0_ENABLE 0xFFFFFFF0 1174 #define S_028238_TARGET1_ENABLE(x) (((x) & 0xF) << 4) 1175 #define G_028238_TARGET1_ENABLE(x) (((x) >> 4) & 0xF) 1176 #define C_028238_TARGET1_ENABLE 0xFFFFFF0F 1177 #define S_028238_TARGET2_ENABLE(x) (((x) & 0xF) << 8) 1178 #define G_028238_TARGET2_ENABLE(x) (((x) >> 8) & 0xF) 1179 #define C_028238_TARGET2_ENABLE 0xFFFFF0FF 1180 #define S_028238_TARGET3_ENABLE(x) (((x) & 0xF) << 12) 1181 #define G_028238_TARGET3_ENABLE(x) (((x) >> 12) & 0xF) 1182 #define C_028238_TARGET3_ENABLE 0xFFFF0FFF 1183 #define S_028238_TARGET4_ENABLE(x) (((x) & 0xF) << 16) 1184 #define G_028238_TARGET4_ENABLE(x) (((x) >> 16) & 0xF) 1185 #define C_028238_TARGET4_ENABLE 0xFFF0FFFF 1186 #define S_028238_TARGET5_ENABLE(x) (((x) & 0xF) << 20) 1187 #define G_028238_TARGET5_ENABLE(x) (((x) >> 20) & 0xF) 1188 #define C_028238_TARGET5_ENABLE 0xFF0FFFFF 1189 #define S_028238_TARGET6_ENABLE(x) (((x) & 0xF) << 24) 1190 #define G_028238_TARGET6_ENABLE(x) (((x) >> 24) & 0xF) 1191 #define C_028238_TARGET6_ENABLE 0xF0FFFFFF 1192 #define S_028238_TARGET7_ENABLE(x) (((x) & 0xF) << 28) 1193 #define G_028238_TARGET7_ENABLE(x) (((x) >> 28) & 0xF) 1194 #define C_028238_TARGET7_ENABLE 0x0FFFFFFF 1195 #define R_02823C_CB_SHADER_MASK 0x02823C 1196 #define S_02823C_OUTPUT0_ENABLE(x) (((x) & 0xF) << 0) 1197 #define G_02823C_OUTPUT0_ENABLE(x) (((x) >> 0) & 0xF) 1198 #define C_02823C_OUTPUT0_ENABLE 0xFFFFFFF0 1199 #define S_02823C_OUTPUT1_ENABLE(x) (((x) & 0xF) << 4) 1200 #define G_02823C_OUTPUT1_ENABLE(x) (((x) >> 4) & 0xF) 1201 #define C_02823C_OUTPUT1_ENABLE 0xFFFFFF0F 1202 #define S_02823C_OUTPUT2_ENABLE(x) (((x) & 0xF) << 8) 1203 #define G_02823C_OUTPUT2_ENABLE(x) (((x) >> 8) & 0xF) 1204 #define C_02823C_OUTPUT2_ENABLE 0xFFFFF0FF 1205 #define S_02823C_OUTPUT3_ENABLE(x) (((x) & 0xF) << 12) 1206 #define G_02823C_OUTPUT3_ENABLE(x) (((x) >> 12) & 0xF) 1207 #define C_02823C_OUTPUT3_ENABLE 0xFFFF0FFF 1208 #define S_02823C_OUTPUT4_ENABLE(x) (((x) & 0xF) << 16) 1209 #define G_02823C_OUTPUT4_ENABLE(x) (((x) >> 16) & 0xF) 1210 #define C_02823C_OUTPUT4_ENABLE 0xFFF0FFFF 1211 #define S_02823C_OUTPUT5_ENABLE(x) (((x) & 0xF) << 20) 1212 #define G_02823C_OUTPUT5_ENABLE(x) (((x) >> 20) & 0xF) 1213 #define C_02823C_OUTPUT5_ENABLE 0xFF0FFFFF 1214 #define S_02823C_OUTPUT6_ENABLE(x) (((x) & 0xF) << 24) 1215 #define G_02823C_OUTPUT6_ENABLE(x) (((x) >> 24) & 0xF) 1216 #define C_02823C_OUTPUT6_ENABLE 0xF0FFFFFF 1217 #define S_02823C_OUTPUT7_ENABLE(x) (((x) & 0xF) << 28) 1218 #define G_02823C_OUTPUT7_ENABLE(x) (((x) >> 28) & 0xF) 1219 #define C_02823C_OUTPUT7_ENABLE 0x0FFFFFFF 1220 #define R_028AB0_VGT_STRMOUT_EN 0x028AB0 1221 #define S_028AB0_STREAMOUT(x) (((x) & 0x1) << 0) 1222 #define G_028AB0_STREAMOUT(x) (((x) >> 0) & 0x1) 1223 #define C_028AB0_STREAMOUT 0xFFFFFFFE 1224 #define R_028B20_VGT_STRMOUT_BUFFER_EN 0x028B20 1225 #define S_028B20_BUFFER_0_EN(x) (((x) & 0x1) << 0) 1226 #define G_028B20_BUFFER_0_EN(x) (((x) >> 0) & 0x1) 1227 #define C_028B20_BUFFER_0_EN 0xFFFFFFFE 1228 #define S_028B20_BUFFER_1_EN(x) (((x) & 0x1) << 1) 1229 #define G_028B20_BUFFER_1_EN(x) (((x) >> 1) & 0x1) 1230 #define C_028B20_BUFFER_1_EN 0xFFFFFFFD 1231 #define S_028B20_BUFFER_2_EN(x) (((x) & 0x1) << 2) 1232 #define G_028B20_BUFFER_2_EN(x) (((x) >> 2) & 0x1) 1233 #define C_028B20_BUFFER_2_EN 0xFFFFFFFB 1234 #define S_028B20_BUFFER_3_EN(x) (((x) & 0x1) << 3) 1235 #define G_028B20_BUFFER_3_EN(x) (((x) >> 3) & 0x1) 1236 #define C_028B20_BUFFER_3_EN 0xFFFFFFF7 1237 #define S_028B20_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 1238 #define G_028B20_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 1239 #define C_028B20_SIZE 0x00000000 1240 #define R_038000_SQ_TEX_RESOURCE_WORD0_0 0x038000 1241 #define S_038000_DIM(x) (((x) & 0x7) << 0) 1242 #define G_038000_DIM(x) (((x) >> 0) & 0x7) 1243 #define C_038000_DIM 0xFFFFFFF8 1244 #define V_038000_SQ_TEX_DIM_1D 0x00000000 1245 #define V_038000_SQ_TEX_DIM_2D 0x00000001 1246 #define V_038000_SQ_TEX_DIM_3D 0x00000002 1247 #define V_038000_SQ_TEX_DIM_CUBEMAP 0x00000003 1248 #define V_038000_SQ_TEX_DIM_1D_ARRAY 0x00000004 1249 #define V_038000_SQ_TEX_DIM_2D_ARRAY 0x00000005 1250 #define V_038000_SQ_TEX_DIM_2D_MSAA 0x00000006 1251 #define V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA 0x00000007 1252 #define S_038000_TILE_MODE(x) (((x) & 0xF) << 3) 1253 #define G_038000_TILE_MODE(x) (((x) >> 3) & 0xF) 1254 #define C_038000_TILE_MODE 0xFFFFFF87 1255 #define V_038000_ARRAY_LINEAR_GENERAL 0x00000000 1256 #define V_038000_ARRAY_LINEAR_ALIGNED 0x00000001 1257 #define V_038000_ARRAY_1D_TILED_THIN1 0x00000002 1258 #define V_038000_ARRAY_2D_TILED_THIN1 0x00000004 1259 #define S_038000_TILE_TYPE(x) (((x) & 0x1) << 7) 1260 #define G_038000_TILE_TYPE(x) (((x) >> 7) & 0x1) 1261 #define C_038000_TILE_TYPE 0xFFFFFF7F 1262 #define S_038000_PITCH(x) (((x) & 0x7FF) << 8) 1263 #define G_038000_PITCH(x) (((x) >> 8) & 0x7FF) 1264 #define C_038000_PITCH 0xFFF800FF 1265 #define S_038000_TEX_WIDTH(x) (((x) & 0x1FFF) << 19) 1266 #define G_038000_TEX_WIDTH(x) (((x) >> 19) & 0x1FFF) 1267 #define C_038000_TEX_WIDTH 0x0007FFFF 1268 #define R_038004_SQ_TEX_RESOURCE_WORD1_0 0x038004 1269 #define S_038004_TEX_HEIGHT(x) (((x) & 0x1FFF) << 0) 1270 #define G_038004_TEX_HEIGHT(x) (((x) >> 0) & 0x1FFF) 1271 #define C_038004_TEX_HEIGHT 0xFFFFE000 1272 #define S_038004_TEX_DEPTH(x) (((x) & 0x1FFF) << 13) 1273 #define G_038004_TEX_DEPTH(x) (((x) >> 13) & 0x1FFF) 1274 #define C_038004_TEX_DEPTH 0xFC001FFF 1275 #define S_038004_DATA_FORMAT(x) (((x) & 0x3F) << 26) 1276 #define G_038004_DATA_FORMAT(x) (((x) >> 26) & 0x3F) 1277 #define C_038004_DATA_FORMAT 0x03FFFFFF 1278 #define V_038004_COLOR_INVALID 0x00000000 1279 #define V_038004_COLOR_8 0x00000001 1280 #define V_038004_COLOR_4_4 0x00000002 1281 #define V_038004_COLOR_3_3_2 0x00000003 1282 #define V_038004_COLOR_16 0x00000005 1283 #define V_038004_COLOR_16_FLOAT 0x00000006 1284 #define V_038004_COLOR_8_8 0x00000007 1285 #define V_038004_COLOR_5_6_5 0x00000008 1286 #define V_038004_COLOR_6_5_5 0x00000009 1287 #define V_038004_COLOR_1_5_5_5 0x0000000A 1288 #define V_038004_COLOR_4_4_4_4 0x0000000B 1289 #define V_038004_COLOR_5_5_5_1 0x0000000C 1290 #define V_038004_COLOR_32 0x0000000D 1291 #define V_038004_COLOR_32_FLOAT 0x0000000E 1292 #define V_038004_COLOR_16_16 0x0000000F 1293 #define V_038004_COLOR_16_16_FLOAT 0x00000010 1294 #define V_038004_COLOR_8_24 0x00000011 1295 #define V_038004_COLOR_8_24_FLOAT 0x00000012 1296 #define V_038004_COLOR_24_8 0x00000013 1297 #define V_038004_COLOR_24_8_FLOAT 0x00000014 1298 #define V_038004_COLOR_10_11_11 0x00000015 1299 #define V_038004_COLOR_10_11_11_FLOAT 0x00000016 1300 #define V_038004_COLOR_11_11_10 0x00000017 1301 #define V_038004_COLOR_11_11_10_FLOAT 0x00000018 1302 #define V_038004_COLOR_2_10_10_10 0x00000019 1303 #define V_038004_COLOR_8_8_8_8 0x0000001A 1304 #define V_038004_COLOR_10_10_10_2 0x0000001B 1305 #define V_038004_COLOR_X24_8_32_FLOAT 0x0000001C 1306 #define V_038004_COLOR_32_32 0x0000001D 1307 #define V_038004_COLOR_32_32_FLOAT 0x0000001E 1308 #define V_038004_COLOR_16_16_16_16 0x0000001F 1309 #define V_038004_COLOR_16_16_16_16_FLOAT 0x00000020 1310 #define V_038004_COLOR_32_32_32_32 0x00000022 1311 #define V_038004_COLOR_32_32_32_32_FLOAT 0x00000023 1312 #define V_038004_FMT_1 0x00000025 1313 #define V_038004_FMT_GB_GR 0x00000027 1314 #define V_038004_FMT_BG_RG 0x00000028 1315 #define V_038004_FMT_32_AS_8 0x00000029 1316 #define V_038004_FMT_32_AS_8_8 0x0000002A 1317 #define V_038004_FMT_5_9_9_9_SHAREDEXP 0x0000002B 1318 #define V_038004_FMT_8_8_8 0x0000002C 1319 #define V_038004_FMT_16_16_16 0x0000002D 1320 #define V_038004_FMT_16_16_16_FLOAT 0x0000002E 1321 #define V_038004_FMT_32_32_32 0x0000002F 1322 #define V_038004_FMT_32_32_32_FLOAT 0x00000030 1323 #define V_038004_FMT_BC1 0x00000031 1324 #define V_038004_FMT_BC2 0x00000032 1325 #define V_038004_FMT_BC3 0x00000033 1326 #define V_038004_FMT_BC4 0x00000034 1327 #define V_038004_FMT_BC5 0x00000035 1328 #define V_038004_FMT_BC6 0x00000036 1329 #define V_038004_FMT_BC7 0x00000037 1330 #define V_038004_FMT_32_AS_32_32_32_32 0x00000038 1331 #define R_038010_SQ_TEX_RESOURCE_WORD4_0 0x038010 1332 #define S_038010_FORMAT_COMP_X(x) (((x) & 0x3) << 0) 1333 #define G_038010_FORMAT_COMP_X(x) (((x) >> 0) & 0x3) 1334 #define C_038010_FORMAT_COMP_X 0xFFFFFFFC 1335 #define S_038010_FORMAT_COMP_Y(x) (((x) & 0x3) << 2) 1336 #define G_038010_FORMAT_COMP_Y(x) (((x) >> 2) & 0x3) 1337 #define C_038010_FORMAT_COMP_Y 0xFFFFFFF3 1338 #define S_038010_FORMAT_COMP_Z(x) (((x) & 0x3) << 4) 1339 #define G_038010_FORMAT_COMP_Z(x) (((x) >> 4) & 0x3) 1340 #define C_038010_FORMAT_COMP_Z 0xFFFFFFCF 1341 #define S_038010_FORMAT_COMP_W(x) (((x) & 0x3) << 6) 1342 #define G_038010_FORMAT_COMP_W(x) (((x) >> 6) & 0x3) 1343 #define C_038010_FORMAT_COMP_W 0xFFFFFF3F 1344 #define S_038010_NUM_FORMAT_ALL(x) (((x) & 0x3) << 8) 1345 #define G_038010_NUM_FORMAT_ALL(x) (((x) >> 8) & 0x3) 1346 #define C_038010_NUM_FORMAT_ALL 0xFFFFFCFF 1347 #define S_038010_SRF_MODE_ALL(x) (((x) & 0x1) << 10) 1348 #define G_038010_SRF_MODE_ALL(x) (((x) >> 10) & 0x1) 1349 #define C_038010_SRF_MODE_ALL 0xFFFFFBFF 1350 #define S_038010_FORCE_DEGAMMA(x) (((x) & 0x1) << 11) 1351 #define G_038010_FORCE_DEGAMMA(x) (((x) >> 11) & 0x1) 1352 #define C_038010_FORCE_DEGAMMA 0xFFFFF7FF 1353 #define S_038010_ENDIAN_SWAP(x) (((x) & 0x3) << 12) 1354 #define G_038010_ENDIAN_SWAP(x) (((x) >> 12) & 0x3) 1355 #define C_038010_ENDIAN_SWAP 0xFFFFCFFF 1356 #define S_038010_REQUEST_SIZE(x) (((x) & 0x3) << 14) 1357 #define G_038010_REQUEST_SIZE(x) (((x) >> 14) & 0x3) 1358 #define C_038010_REQUEST_SIZE 0xFFFF3FFF 1359 #define S_038010_DST_SEL_X(x) (((x) & 0x7) << 16) 1360 #define G_038010_DST_SEL_X(x) (((x) >> 16) & 0x7) 1361 #define C_038010_DST_SEL_X 0xFFF8FFFF 1362 #define S_038010_DST_SEL_Y(x) (((x) & 0x7) << 19) 1363 #define G_038010_DST_SEL_Y(x) (((x) >> 19) & 0x7) 1364 #define C_038010_DST_SEL_Y 0xFFC7FFFF 1365 #define S_038010_DST_SEL_Z(x) (((x) & 0x7) << 22) 1366 #define G_038010_DST_SEL_Z(x) (((x) >> 22) & 0x7) 1367 #define C_038010_DST_SEL_Z 0xFE3FFFFF 1368 #define S_038010_DST_SEL_W(x) (((x) & 0x7) << 25) 1369 #define G_038010_DST_SEL_W(x) (((x) >> 25) & 0x7) 1370 #define C_038010_DST_SEL_W 0xF1FFFFFF 1371 # define SQ_SEL_X 0 1372 # define SQ_SEL_Y 1 1373 # define SQ_SEL_Z 2 1374 # define SQ_SEL_W 3 1375 # define SQ_SEL_0 4 1376 # define SQ_SEL_1 5 1377 #define S_038010_BASE_LEVEL(x) (((x) & 0xF) << 28) 1378 #define G_038010_BASE_LEVEL(x) (((x) >> 28) & 0xF) 1379 #define C_038010_BASE_LEVEL 0x0FFFFFFF 1380 #define R_038014_SQ_TEX_RESOURCE_WORD5_0 0x038014 1381 #define S_038014_LAST_LEVEL(x) (((x) & 0xF) << 0) 1382 #define G_038014_LAST_LEVEL(x) (((x) >> 0) & 0xF) 1383 #define C_038014_LAST_LEVEL 0xFFFFFFF0 1384 #define S_038014_BASE_ARRAY(x) (((x) & 0x1FFF) << 4) 1385 #define G_038014_BASE_ARRAY(x) (((x) >> 4) & 0x1FFF) 1386 #define C_038014_BASE_ARRAY 0xFFFE000F 1387 #define S_038014_LAST_ARRAY(x) (((x) & 0x1FFF) << 17) 1388 #define G_038014_LAST_ARRAY(x) (((x) >> 17) & 0x1FFF) 1389 #define C_038014_LAST_ARRAY 0xC001FFFF 1390 #define R_0288A8_SQ_ESGS_RING_ITEMSIZE 0x0288A8 1391 #define S_0288A8_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 1392 #define G_0288A8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 1393 #define C_0288A8_ITEMSIZE 0xFFFF8000 1394 #define R_008C44_SQ_ESGS_RING_SIZE 0x008C44 1395 #define S_008C44_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 1396 #define G_008C44_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 1397 #define C_008C44_MEM_SIZE 0x00000000 1398 #define R_0288B0_SQ_ESTMP_RING_ITEMSIZE 0x0288B0 1399 #define S_0288B0_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 1400 #define G_0288B0_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 1401 #define C_0288B0_ITEMSIZE 0xFFFF8000 1402 #define R_008C54_SQ_ESTMP_RING_SIZE 0x008C54 1403 #define S_008C54_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 1404 #define G_008C54_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 1405 #define C_008C54_MEM_SIZE 0x00000000 1406 #define R_0288C0_SQ_FBUF_RING_ITEMSIZE 0x0288C0 1407 #define S_0288C0_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 1408 #define G_0288C0_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 1409 #define C_0288C0_ITEMSIZE 0xFFFF8000 1410 #define R_008C74_SQ_FBUF_RING_SIZE 0x008C74 1411 #define S_008C74_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 1412 #define G_008C74_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 1413 #define C_008C74_MEM_SIZE 0x00000000 1414 #define R_0288B4_SQ_GSTMP_RING_ITEMSIZE 0x0288B4 1415 #define S_0288B4_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 1416 #define G_0288B4_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 1417 #define C_0288B4_ITEMSIZE 0xFFFF8000 1418 #define R_008C5C_SQ_GSTMP_RING_SIZE 0x008C5C 1419 #define S_008C5C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 1420 #define G_008C5C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 1421 #define C_008C5C_MEM_SIZE 0x00000000 1422 #define R_0288AC_SQ_GSVS_RING_ITEMSIZE 0x0288AC 1423 #define S_0288AC_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 1424 #define G_0288AC_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 1425 #define C_0288AC_ITEMSIZE 0xFFFF8000 1426 #define R_008C4C_SQ_GSVS_RING_SIZE 0x008C4C 1427 #define S_008C4C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 1428 #define G_008C4C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 1429 #define C_008C4C_MEM_SIZE 0x00000000 1430 #define R_0288BC_SQ_PSTMP_RING_ITEMSIZE 0x0288BC 1431 #define S_0288BC_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 1432 #define G_0288BC_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 1433 #define C_0288BC_ITEMSIZE 0xFFFF8000 1434 #define R_008C6C_SQ_PSTMP_RING_SIZE 0x008C6C 1435 #define S_008C6C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 1436 #define G_008C6C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 1437 #define C_008C6C_MEM_SIZE 0x00000000 1438 #define R_0288C4_SQ_REDUC_RING_ITEMSIZE 0x0288C4 1439 #define S_0288C4_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 1440 #define G_0288C4_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 1441 #define C_0288C4_ITEMSIZE 0xFFFF8000 1442 #define R_008C7C_SQ_REDUC_RING_SIZE 0x008C7C 1443 #define S_008C7C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 1444 #define G_008C7C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 1445 #define C_008C7C_MEM_SIZE 0x00000000 1446 #define R_0288B8_SQ_VSTMP_RING_ITEMSIZE 0x0288B8 1447 #define S_0288B8_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 1448 #define G_0288B8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 1449 #define C_0288B8_ITEMSIZE 0xFFFF8000 1450 #define R_008C64_SQ_VSTMP_RING_SIZE 0x008C64 1451 #define S_008C64_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 1452 #define G_008C64_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 1453 #define C_008C64_MEM_SIZE 0x00000000 1454 #define R_0288C8_SQ_GS_VERT_ITEMSIZE 0x0288C8 1455 #define S_0288C8_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 1456 #define G_0288C8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 1457 #define C_0288C8_ITEMSIZE 0xFFFF8000 1458 #define R_028010_DB_DEPTH_INFO 0x028010 1459 #define S_028010_FORMAT(x) (((x) & 0x7) << 0) 1460 #define G_028010_FORMAT(x) (((x) >> 0) & 0x7) 1461 #define C_028010_FORMAT 0xFFFFFFF8 1462 #define V_028010_DEPTH_INVALID 0x00000000 1463 #define V_028010_DEPTH_16 0x00000001 1464 #define V_028010_DEPTH_X8_24 0x00000002 1465 #define V_028010_DEPTH_8_24 0x00000003 1466 #define V_028010_DEPTH_X8_24_FLOAT 0x00000004 1467 #define V_028010_DEPTH_8_24_FLOAT 0x00000005 1468 #define V_028010_DEPTH_32_FLOAT 0x00000006 1469 #define V_028010_DEPTH_X24_8_32_FLOAT 0x00000007 1470 #define S_028010_READ_SIZE(x) (((x) & 0x1) << 3) 1471 #define G_028010_READ_SIZE(x) (((x) >> 3) & 0x1) 1472 #define C_028010_READ_SIZE 0xFFFFFFF7 1473 #define S_028010_ARRAY_MODE(x) (((x) & 0xF) << 15) 1474 #define G_028010_ARRAY_MODE(x) (((x) >> 15) & 0xF) 1475 #define C_028010_ARRAY_MODE 0xFFF87FFF 1476 #define V_028010_ARRAY_1D_TILED_THIN1 0x00000002 1477 #define V_028010_ARRAY_2D_TILED_THIN1 0x00000004 1478 #define S_028010_TILE_SURFACE_ENABLE(x) (((x) & 0x1) << 25) 1479 #define G_028010_TILE_SURFACE_ENABLE(x) (((x) >> 25) & 0x1) 1480 #define C_028010_TILE_SURFACE_ENABLE 0xFDFFFFFF 1481 #define S_028010_TILE_COMPACT(x) (((x) & 0x1) << 26) 1482 #define G_028010_TILE_COMPACT(x) (((x) >> 26) & 0x1) 1483 #define C_028010_TILE_COMPACT 0xFBFFFFFF 1484 #define S_028010_ZRANGE_PRECISION(x) (((x) & 0x1) << 31) 1485 #define G_028010_ZRANGE_PRECISION(x) (((x) >> 31) & 0x1) 1486 #define C_028010_ZRANGE_PRECISION 0x7FFFFFFF 1487 #define R_028000_DB_DEPTH_SIZE 0x028000 1488 #define S_028000_PITCH_TILE_MAX(x) (((x) & 0x3FF) << 0) 1489 #define G_028000_PITCH_TILE_MAX(x) (((x) >> 0) & 0x3FF) 1490 #define C_028000_PITCH_TILE_MAX 0xFFFFFC00 1491 #define S_028000_SLICE_TILE_MAX(x) (((x) & 0xFFFFF) << 10) 1492 #define G_028000_SLICE_TILE_MAX(x) (((x) >> 10) & 0xFFFFF) 1493 #define C_028000_SLICE_TILE_MAX 0xC00003FF 1494 #define R_028004_DB_DEPTH_VIEW 0x028004 1495 #define S_028004_SLICE_START(x) (((x) & 0x7FF) << 0) 1496 #define G_028004_SLICE_START(x) (((x) >> 0) & 0x7FF) 1497 #define C_028004_SLICE_START 0xFFFFF800 1498 #define S_028004_SLICE_MAX(x) (((x) & 0x7FF) << 13) 1499 #define G_028004_SLICE_MAX(x) (((x) >> 13) & 0x7FF) 1500 #define C_028004_SLICE_MAX 0xFF001FFF 1501 #define R_028800_DB_DEPTH_CONTROL 0x028800 1502 #define S_028800_STENCIL_ENABLE(x) (((x) & 0x1) << 0) 1503 #define G_028800_STENCIL_ENABLE(x) (((x) >> 0) & 0x1) 1504 #define C_028800_STENCIL_ENABLE 0xFFFFFFFE 1505 #define S_028800_Z_ENABLE(x) (((x) & 0x1) << 1) 1506 #define G_028800_Z_ENABLE(x) (((x) >> 1) & 0x1) 1507 #define C_028800_Z_ENABLE 0xFFFFFFFD 1508 #define S_028800_Z_WRITE_ENABLE(x) (((x) & 0x1) << 2) 1509 #define G_028800_Z_WRITE_ENABLE(x) (((x) >> 2) & 0x1) 1510 #define C_028800_Z_WRITE_ENABLE 0xFFFFFFFB 1511 #define S_028800_ZFUNC(x) (((x) & 0x7) << 4) 1512 #define G_028800_ZFUNC(x) (((x) >> 4) & 0x7) 1513 #define C_028800_ZFUNC 0xFFFFFF8F 1514 #define S_028800_BACKFACE_ENABLE(x) (((x) & 0x1) << 7) 1515 #define G_028800_BACKFACE_ENABLE(x) (((x) >> 7) & 0x1) 1516 #define C_028800_BACKFACE_ENABLE 0xFFFFFF7F 1517 #define S_028800_STENCILFUNC(x) (((x) & 0x7) << 8) 1518 #define G_028800_STENCILFUNC(x) (((x) >> 8) & 0x7) 1519 #define C_028800_STENCILFUNC 0xFFFFF8FF 1520 #define S_028800_STENCILFAIL(x) (((x) & 0x7) << 11) 1521 #define G_028800_STENCILFAIL(x) (((x) >> 11) & 0x7) 1522 #define C_028800_STENCILFAIL 0xFFFFC7FF 1523 #define S_028800_STENCILZPASS(x) (((x) & 0x7) << 14) 1524 #define G_028800_STENCILZPASS(x) (((x) >> 14) & 0x7) 1525 #define C_028800_STENCILZPASS 0xFFFE3FFF 1526 #define S_028800_STENCILZFAIL(x) (((x) & 0x7) << 17) 1527 #define G_028800_STENCILZFAIL(x) (((x) >> 17) & 0x7) 1528 #define C_028800_STENCILZFAIL 0xFFF1FFFF 1529 #define S_028800_STENCILFUNC_BF(x) (((x) & 0x7) << 20) 1530 #define G_028800_STENCILFUNC_BF(x) (((x) >> 20) & 0x7) 1531 #define C_028800_STENCILFUNC_BF 0xFF8FFFFF 1532 #define S_028800_STENCILFAIL_BF(x) (((x) & 0x7) << 23) 1533 #define G_028800_STENCILFAIL_BF(x) (((x) >> 23) & 0x7) 1534 #define C_028800_STENCILFAIL_BF 0xFC7FFFFF 1535 #define S_028800_STENCILZPASS_BF(x) (((x) & 0x7) << 26) 1536 #define G_028800_STENCILZPASS_BF(x) (((x) >> 26) & 0x7) 1537 #define C_028800_STENCILZPASS_BF 0xE3FFFFFF 1538 #define S_028800_STENCILZFAIL_BF(x) (((x) & 0x7) << 29) 1539 #define G_028800_STENCILZFAIL_BF(x) (((x) >> 29) & 0x7) 1540 #define C_028800_STENCILZFAIL_BF 0x1FFFFFFF 1541 1542 #endif 1543