1 /* 2 * Copyright 2009 Advanced Micro Devices, Inc. 3 * Copyright 2009 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 * Jerome Glisse 26 */ 27 #ifndef R600D_H 28 #define R600D_H 29 30 #define CP_PACKET2 0x80000000 31 #define PACKET2_PAD_SHIFT 0 32 #define PACKET2_PAD_MASK (0x3fffffff << 0) 33 34 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 35 36 #define R6XX_MAX_SH_GPRS 256 37 #define R6XX_MAX_TEMP_GPRS 16 38 #define R6XX_MAX_SH_THREADS 256 39 #define R6XX_MAX_SH_STACK_ENTRIES 4096 40 #define R6XX_MAX_BACKENDS 8 41 #define R6XX_MAX_BACKENDS_MASK 0xff 42 #define R6XX_MAX_SIMDS 8 43 #define R6XX_MAX_SIMDS_MASK 0xff 44 #define R6XX_MAX_PIPES 8 45 #define R6XX_MAX_PIPES_MASK 0xff 46 47 /* PTE flags */ 48 #define PTE_VALID (1 << 0) 49 #define PTE_SYSTEM (1 << 1) 50 #define PTE_SNOOPED (1 << 2) 51 #define PTE_READABLE (1 << 5) 52 #define PTE_WRITEABLE (1 << 6) 53 54 /* Registers */ 55 #define ARB_POP 0x2418 56 #define ENABLE_TC128 (1 << 30) 57 #define ARB_GDEC_RD_CNTL 0x246C 58 59 #define CC_GC_SHADER_PIPE_CONFIG 0x8950 60 #define CC_RB_BACKEND_DISABLE 0x98F4 61 #define BACKEND_DISABLE(x) ((x) << 16) 62 63 #define CB_COLOR0_BASE 0x28040 64 #define CB_COLOR1_BASE 0x28044 65 #define CB_COLOR2_BASE 0x28048 66 #define CB_COLOR3_BASE 0x2804C 67 #define CB_COLOR4_BASE 0x28050 68 #define CB_COLOR5_BASE 0x28054 69 #define CB_COLOR6_BASE 0x28058 70 #define CB_COLOR7_BASE 0x2805C 71 #define CB_COLOR7_FRAG 0x280FC 72 73 #define CB_COLOR0_SIZE 0x28060 74 #define CB_COLOR0_VIEW 0x28080 75 #define CB_COLOR0_INFO 0x280a0 76 #define CB_COLOR0_TILE 0x280c0 77 #define CB_COLOR0_FRAG 0x280e0 78 #define CB_COLOR0_MASK 0x28100 79 80 #define CONFIG_MEMSIZE 0x5428 81 #define CONFIG_CNTL 0x5424 82 #define CP_STAT 0x8680 83 #define CP_COHER_BASE 0x85F8 84 #define CP_DEBUG 0xC1FC 85 #define R_0086D8_CP_ME_CNTL 0x86D8 86 #define S_0086D8_CP_ME_HALT(x) (((x) & 1)<<28) 87 #define C_0086D8_CP_ME_HALT(x) ((x) & 0xEFFFFFFF) 88 #define CP_ME_RAM_DATA 0xC160 89 #define CP_ME_RAM_RADDR 0xC158 90 #define CP_ME_RAM_WADDR 0xC15C 91 #define CP_MEQ_THRESHOLDS 0x8764 92 #define MEQ_END(x) ((x) << 16) 93 #define ROQ_END(x) ((x) << 24) 94 #define CP_PERFMON_CNTL 0x87FC 95 #define CP_PFP_UCODE_ADDR 0xC150 96 #define CP_PFP_UCODE_DATA 0xC154 97 #define CP_QUEUE_THRESHOLDS 0x8760 98 #define ROQ_IB1_START(x) ((x) << 0) 99 #define ROQ_IB2_START(x) ((x) << 8) 100 #define CP_RB_BASE 0xC100 101 #define CP_RB_CNTL 0xC104 102 #define RB_BUFSZ(x) ((x)<<0) 103 #define RB_BLKSZ(x) ((x)<<8) 104 #define RB_NO_UPDATE (1<<27) 105 #define RB_RPTR_WR_ENA (1<<31) 106 #define BUF_SWAP_32BIT (2 << 16) 107 #define CP_RB_RPTR 0x8700 108 #define CP_RB_RPTR_ADDR 0xC10C 109 #define CP_RB_RPTR_ADDR_HI 0xC110 110 #define CP_RB_RPTR_WR 0xC108 111 #define CP_RB_WPTR 0xC114 112 #define CP_RB_WPTR_ADDR 0xC118 113 #define CP_RB_WPTR_ADDR_HI 0xC11C 114 #define CP_RB_WPTR_DELAY 0x8704 115 #define CP_ROQ_IB1_STAT 0x8784 116 #define CP_ROQ_IB2_STAT 0x8788 117 #define CP_SEM_WAIT_TIMER 0x85BC 118 119 #define DB_DEBUG 0x9830 120 #define PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31) 121 #define DB_DEPTH_BASE 0x2800C 122 #define DB_HTILE_DATA_BASE 0x28014 123 #define DB_WATERMARKS 0x9838 124 #define DEPTH_FREE(x) ((x) << 0) 125 #define DEPTH_FLUSH(x) ((x) << 5) 126 #define DEPTH_PENDING_FREE(x) ((x) << 15) 127 #define DEPTH_CACHELINE_FREE(x) ((x) << 20) 128 129 #define DCP_TILING_CONFIG 0x6CA0 130 #define PIPE_TILING(x) ((x) << 1) 131 #define BANK_TILING(x) ((x) << 4) 132 #define GROUP_SIZE(x) ((x) << 6) 133 #define ROW_TILING(x) ((x) << 8) 134 #define BANK_SWAPS(x) ((x) << 11) 135 #define SAMPLE_SPLIT(x) ((x) << 14) 136 #define BACKEND_MAP(x) ((x) << 16) 137 138 #define GB_TILING_CONFIG 0x98F0 139 140 #define GC_USER_SHADER_PIPE_CONFIG 0x8954 141 #define INACTIVE_QD_PIPES(x) ((x) << 8) 142 #define INACTIVE_QD_PIPES_MASK 0x0000FF00 143 #define INACTIVE_SIMDS(x) ((x) << 16) 144 #define INACTIVE_SIMDS_MASK 0x00FF0000 145 146 #define SQ_CONFIG 0x8c00 147 # define VC_ENABLE (1 << 0) 148 # define EXPORT_SRC_C (1 << 1) 149 # define DX9_CONSTS (1 << 2) 150 # define ALU_INST_PREFER_VECTOR (1 << 3) 151 # define DX10_CLAMP (1 << 4) 152 # define CLAUSE_SEQ_PRIO(x) ((x) << 8) 153 # define PS_PRIO(x) ((x) << 24) 154 # define VS_PRIO(x) ((x) << 26) 155 # define GS_PRIO(x) ((x) << 28) 156 # define ES_PRIO(x) ((x) << 30) 157 #define SQ_GPR_RESOURCE_MGMT_1 0x8c04 158 # define NUM_PS_GPRS(x) ((x) << 0) 159 # define NUM_VS_GPRS(x) ((x) << 16) 160 # define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) 161 #define SQ_GPR_RESOURCE_MGMT_2 0x8c08 162 # define NUM_GS_GPRS(x) ((x) << 0) 163 # define NUM_ES_GPRS(x) ((x) << 16) 164 #define SQ_THREAD_RESOURCE_MGMT 0x8c0c 165 # define NUM_PS_THREADS(x) ((x) << 0) 166 # define NUM_VS_THREADS(x) ((x) << 8) 167 # define NUM_GS_THREADS(x) ((x) << 16) 168 # define NUM_ES_THREADS(x) ((x) << 24) 169 #define SQ_STACK_RESOURCE_MGMT_1 0x8c10 170 # define NUM_PS_STACK_ENTRIES(x) ((x) << 0) 171 # define NUM_VS_STACK_ENTRIES(x) ((x) << 16) 172 #define SQ_STACK_RESOURCE_MGMT_2 0x8c14 173 # define NUM_GS_STACK_ENTRIES(x) ((x) << 0) 174 # define NUM_ES_STACK_ENTRIES(x) ((x) << 16) 175 #define SQ_ESGS_RING_BASE 0x8c40 176 #define SQ_GSVS_RING_BASE 0x8c48 177 #define SQ_ESTMP_RING_BASE 0x8c50 178 #define SQ_GSTMP_RING_BASE 0x8c58 179 #define SQ_VSTMP_RING_BASE 0x8c60 180 #define SQ_PSTMP_RING_BASE 0x8c68 181 #define SQ_FBUF_RING_BASE 0x8c70 182 #define SQ_REDUC_RING_BASE 0x8c78 183 184 #define GRBM_CNTL 0x8000 185 # define GRBM_READ_TIMEOUT(x) ((x) << 0) 186 #define GRBM_STATUS 0x8010 187 #define CMDFIFO_AVAIL_MASK 0x0000001F 188 #define GUI_ACTIVE (1<<31) 189 #define GRBM_STATUS2 0x8014 190 #define GRBM_SOFT_RESET 0x8020 191 #define SOFT_RESET_CP (1<<0) 192 193 #define HDP_HOST_PATH_CNTL 0x2C00 194 #define HDP_NONSURFACE_BASE 0x2C04 195 #define HDP_NONSURFACE_INFO 0x2C08 196 #define HDP_NONSURFACE_SIZE 0x2C0C 197 #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 198 #define HDP_TILING_CONFIG 0x2F3C 199 200 #define MC_VM_AGP_TOP 0x2184 201 #define MC_VM_AGP_BOT 0x2188 202 #define MC_VM_AGP_BASE 0x218C 203 #define MC_VM_FB_LOCATION 0x2180 204 #define MC_VM_L1_TLB_MCD_RD_A_CNTL 0x219C 205 #define ENABLE_L1_TLB (1 << 0) 206 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 207 #define ENABLE_L1_STRICT_ORDERING (1 << 2) 208 #define SYSTEM_ACCESS_MODE_MASK 0x000000C0 209 #define SYSTEM_ACCESS_MODE_SHIFT 6 210 #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 6) 211 #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 6) 212 #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 6) 213 #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 6) 214 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 8) 215 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 8) 216 #define ENABLE_SEMAPHORE_MODE (1 << 10) 217 #define ENABLE_WAIT_L2_QUERY (1 << 11) 218 #define EFFECTIVE_L1_TLB_SIZE(x) (((x) & 7) << 12) 219 #define EFFECTIVE_L1_TLB_SIZE_MASK 0x00007000 220 #define EFFECTIVE_L1_TLB_SIZE_SHIFT 12 221 #define EFFECTIVE_L1_QUEUE_SIZE(x) (((x) & 7) << 15) 222 #define EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00038000 223 #define EFFECTIVE_L1_QUEUE_SIZE_SHIFT 15 224 #define MC_VM_L1_TLB_MCD_RD_B_CNTL 0x21A0 225 #define MC_VM_L1_TLB_MCB_RD_GFX_CNTL 0x21FC 226 #define MC_VM_L1_TLB_MCB_RD_HDP_CNTL 0x2204 227 #define MC_VM_L1_TLB_MCB_RD_PDMA_CNTL 0x2208 228 #define MC_VM_L1_TLB_MCB_RD_SEM_CNTL 0x220C 229 #define MC_VM_L1_TLB_MCB_RD_SYS_CNTL 0x2200 230 #define MC_VM_L1_TLB_MCD_WR_A_CNTL 0x21A4 231 #define MC_VM_L1_TLB_MCD_WR_B_CNTL 0x21A8 232 #define MC_VM_L1_TLB_MCB_WR_GFX_CNTL 0x2210 233 #define MC_VM_L1_TLB_MCB_WR_HDP_CNTL 0x2218 234 #define MC_VM_L1_TLB_MCB_WR_PDMA_CNTL 0x221C 235 #define MC_VM_L1_TLB_MCB_WR_SEM_CNTL 0x2220 236 #define MC_VM_L1_TLB_MCB_WR_SYS_CNTL 0x2214 237 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190 238 #define LOGICAL_PAGE_NUMBER_MASK 0x000FFFFF 239 #define LOGICAL_PAGE_NUMBER_SHIFT 0 240 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194 241 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198 242 243 #define PA_CL_ENHANCE 0x8A14 244 #define CLIP_VTX_REORDER_ENA (1 << 0) 245 #define NUM_CLIP_SEQ(x) ((x) << 1) 246 #define PA_SC_AA_CONFIG 0x28C04 247 #define PA_SC_AA_SAMPLE_LOCS_2S 0x8B40 248 #define PA_SC_AA_SAMPLE_LOCS_4S 0x8B44 249 #define PA_SC_AA_SAMPLE_LOCS_8S_WD0 0x8B48 250 #define PA_SC_AA_SAMPLE_LOCS_8S_WD1 0x8B4C 251 #define S0_X(x) ((x) << 0) 252 #define S0_Y(x) ((x) << 4) 253 #define S1_X(x) ((x) << 8) 254 #define S1_Y(x) ((x) << 12) 255 #define S2_X(x) ((x) << 16) 256 #define S2_Y(x) ((x) << 20) 257 #define S3_X(x) ((x) << 24) 258 #define S3_Y(x) ((x) << 28) 259 #define S4_X(x) ((x) << 0) 260 #define S4_Y(x) ((x) << 4) 261 #define S5_X(x) ((x) << 8) 262 #define S5_Y(x) ((x) << 12) 263 #define S6_X(x) ((x) << 16) 264 #define S6_Y(x) ((x) << 20) 265 #define S7_X(x) ((x) << 24) 266 #define S7_Y(x) ((x) << 28) 267 #define PA_SC_CLIPRECT_RULE 0x2820c 268 #define PA_SC_ENHANCE 0x8BF0 269 #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 270 #define FORCE_EOV_MAX_TILE_CNT(x) ((x) << 12) 271 #define PA_SC_LINE_STIPPLE 0x28A0C 272 #define PA_SC_LINE_STIPPLE_STATE 0x8B10 273 #define PA_SC_MODE_CNTL 0x28A4C 274 #define PA_SC_MULTI_CHIP_CNTL 0x8B20 275 276 #define PA_SC_SCREEN_SCISSOR_TL 0x28030 277 #define PA_SC_GENERIC_SCISSOR_TL 0x28240 278 #define PA_SC_WINDOW_SCISSOR_TL 0x28204 279 280 #define PCIE_PORT_INDEX 0x0038 281 #define PCIE_PORT_DATA 0x003C 282 283 #define CHMAP 0x2004 284 #define NOOFCHAN_SHIFT 12 285 #define NOOFCHAN_MASK 0x00003000 286 287 #define RAMCFG 0x2408 288 #define NOOFBANK_SHIFT 0 289 #define NOOFBANK_MASK 0x00000001 290 #define NOOFRANK_SHIFT 1 291 #define NOOFRANK_MASK 0x00000002 292 #define NOOFROWS_SHIFT 2 293 #define NOOFROWS_MASK 0x0000001C 294 #define NOOFCOLS_SHIFT 5 295 #define NOOFCOLS_MASK 0x00000060 296 #define CHANSIZE_SHIFT 7 297 #define CHANSIZE_MASK 0x00000080 298 #define BURSTLENGTH_SHIFT 8 299 #define BURSTLENGTH_MASK 0x00000100 300 #define CHANSIZE_OVERRIDE (1 << 10) 301 302 #define SCRATCH_REG0 0x8500 303 #define SCRATCH_REG1 0x8504 304 #define SCRATCH_REG2 0x8508 305 #define SCRATCH_REG3 0x850C 306 #define SCRATCH_REG4 0x8510 307 #define SCRATCH_REG5 0x8514 308 #define SCRATCH_REG6 0x8518 309 #define SCRATCH_REG7 0x851C 310 #define SCRATCH_UMSK 0x8540 311 #define SCRATCH_ADDR 0x8544 312 313 #define SPI_CONFIG_CNTL 0x9100 314 #define GPR_WRITE_PRIORITY(x) ((x) << 0) 315 #define DISABLE_INTERP_1 (1 << 5) 316 #define SPI_CONFIG_CNTL_1 0x913C 317 #define VTX_DONE_DELAY(x) ((x) << 0) 318 #define INTERP_ONE_PRIM_PER_ROW (1 << 4) 319 #define SPI_INPUT_Z 0x286D8 320 #define SPI_PS_IN_CONTROL_0 0x286CC 321 #define NUM_INTERP(x) ((x)<<0) 322 #define POSITION_ENA (1<<8) 323 #define POSITION_CENTROID (1<<9) 324 #define POSITION_ADDR(x) ((x)<<10) 325 #define PARAM_GEN(x) ((x)<<15) 326 #define PARAM_GEN_ADDR(x) ((x)<<19) 327 #define BARYC_SAMPLE_CNTL(x) ((x)<<26) 328 #define PERSP_GRADIENT_ENA (1<<28) 329 #define LINEAR_GRADIENT_ENA (1<<29) 330 #define POSITION_SAMPLE (1<<30) 331 #define BARYC_AT_SAMPLE_ENA (1<<31) 332 #define SPI_PS_IN_CONTROL_1 0x286D0 333 #define GEN_INDEX_PIX (1<<0) 334 #define GEN_INDEX_PIX_ADDR(x) ((x)<<1) 335 #define FRONT_FACE_ENA (1<<8) 336 #define FRONT_FACE_CHAN(x) ((x)<<9) 337 #define FRONT_FACE_ALL_BITS (1<<11) 338 #define FRONT_FACE_ADDR(x) ((x)<<12) 339 #define FOG_ADDR(x) ((x)<<17) 340 #define FIXED_PT_POSITION_ENA (1<<24) 341 #define FIXED_PT_POSITION_ADDR(x) ((x)<<25) 342 343 #define SQ_MS_FIFO_SIZES 0x8CF0 344 #define CACHE_FIFO_SIZE(x) ((x) << 0) 345 #define FETCH_FIFO_HIWATER(x) ((x) << 8) 346 #define DONE_FIFO_HIWATER(x) ((x) << 16) 347 #define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) 348 #define SQ_PGM_START_ES 0x28880 349 #define SQ_PGM_START_FS 0x28894 350 #define SQ_PGM_START_GS 0x2886C 351 #define SQ_PGM_START_PS 0x28840 352 #define SQ_PGM_RESOURCES_PS 0x28850 353 #define SQ_PGM_EXPORTS_PS 0x28854 354 #define SQ_PGM_CF_OFFSET_PS 0x288cc 355 #define SQ_PGM_START_VS 0x28858 356 #define SQ_PGM_RESOURCES_VS 0x28868 357 #define SQ_PGM_CF_OFFSET_VS 0x288d0 358 #define SQ_VTX_CONSTANT_WORD6_0 0x38018 359 #define S__SQ_VTX_CONSTANT_TYPE(x) (((x) & 3) << 30) 360 #define G__SQ_VTX_CONSTANT_TYPE(x) (((x) >> 30) & 3) 361 #define SQ_TEX_VTX_INVALID_TEXTURE 0x0 362 #define SQ_TEX_VTX_INVALID_BUFFER 0x1 363 #define SQ_TEX_VTX_VALID_TEXTURE 0x2 364 #define SQ_TEX_VTX_VALID_BUFFER 0x3 365 366 367 #define SX_MISC 0x28350 368 #define SX_MEMORY_EXPORT_BASE 0x9010 369 #define SX_DEBUG_1 0x9054 370 #define SMX_EVENT_RELEASE (1 << 0) 371 #define ENABLE_NEW_SMX_ADDRESS (1 << 16) 372 373 #define TA_CNTL_AUX 0x9508 374 #define DISABLE_CUBE_WRAP (1 << 0) 375 #define DISABLE_CUBE_ANISO (1 << 1) 376 #define SYNC_GRADIENT (1 << 24) 377 #define SYNC_WALKER (1 << 25) 378 #define SYNC_ALIGNER (1 << 26) 379 #define BILINEAR_PRECISION_6_BIT (0 << 31) 380 #define BILINEAR_PRECISION_8_BIT (1 << 31) 381 382 #define TC_CNTL 0x9608 383 #define TC_L2_SIZE(x) ((x)<<5) 384 #define L2_DISABLE_LATE_HIT (1<<9) 385 386 387 #define VGT_CACHE_INVALIDATION 0x88C4 388 #define CACHE_INVALIDATION(x) ((x)<<0) 389 #define VC_ONLY 0 390 #define TC_ONLY 1 391 #define VC_AND_TC 2 392 #define VGT_DMA_BASE 0x287E8 393 #define VGT_DMA_BASE_HI 0x287E4 394 #define VGT_ES_PER_GS 0x88CC 395 #define VGT_GS_PER_ES 0x88C8 396 #define VGT_GS_PER_VS 0x88E8 397 #define VGT_GS_VERTEX_REUSE 0x88D4 398 #define VGT_PRIMITIVE_TYPE 0x8958 399 #define VGT_NUM_INSTANCES 0x8974 400 #define VGT_OUT_DEALLOC_CNTL 0x28C5C 401 #define DEALLOC_DIST_MASK 0x0000007F 402 #define VGT_STRMOUT_BASE_OFFSET_0 0x28B10 403 #define VGT_STRMOUT_BASE_OFFSET_1 0x28B14 404 #define VGT_STRMOUT_BASE_OFFSET_2 0x28B18 405 #define VGT_STRMOUT_BASE_OFFSET_3 0x28B1c 406 #define VGT_STRMOUT_BASE_OFFSET_HI_0 0x28B44 407 #define VGT_STRMOUT_BASE_OFFSET_HI_1 0x28B48 408 #define VGT_STRMOUT_BASE_OFFSET_HI_2 0x28B4c 409 #define VGT_STRMOUT_BASE_OFFSET_HI_3 0x28B50 410 #define VGT_STRMOUT_BUFFER_BASE_0 0x28AD8 411 #define VGT_STRMOUT_BUFFER_BASE_1 0x28AE8 412 #define VGT_STRMOUT_BUFFER_BASE_2 0x28AF8 413 #define VGT_STRMOUT_BUFFER_BASE_3 0x28B08 414 #define VGT_STRMOUT_BUFFER_OFFSET_0 0x28ADC 415 #define VGT_STRMOUT_BUFFER_OFFSET_1 0x28AEC 416 #define VGT_STRMOUT_BUFFER_OFFSET_2 0x28AFC 417 #define VGT_STRMOUT_BUFFER_OFFSET_3 0x28B0C 418 #define VGT_STRMOUT_EN 0x28AB0 419 #define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58 420 #define VTX_REUSE_DEPTH_MASK 0x000000FF 421 #define VGT_EVENT_INITIATOR 0x28a90 422 # define CACHE_FLUSH_AND_INV_EVENT (0x16 << 0) 423 424 #define VM_CONTEXT0_CNTL 0x1410 425 #define ENABLE_CONTEXT (1 << 0) 426 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 427 #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 428 #define VM_CONTEXT0_INVALIDATION_LOW_ADDR 0x1490 429 #define VM_CONTEXT0_INVALIDATION_HIGH_ADDR 0x14B0 430 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x1574 431 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x1594 432 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x15B4 433 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1554 434 #define VM_CONTEXT0_REQUEST_RESPONSE 0x1470 435 #define REQUEST_TYPE(x) (((x) & 0xf) << 0) 436 #define RESPONSE_TYPE_MASK 0x000000F0 437 #define RESPONSE_TYPE_SHIFT 4 438 #define VM_L2_CNTL 0x1400 439 #define ENABLE_L2_CACHE (1 << 0) 440 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 441 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 442 #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 13) 443 #define VM_L2_CNTL2 0x1404 444 #define INVALIDATE_ALL_L1_TLBS (1 << 0) 445 #define INVALIDATE_L2_CACHE (1 << 1) 446 #define VM_L2_CNTL3 0x1408 447 #define BANK_SELECT_0(x) (((x) & 0x1f) << 0) 448 #define BANK_SELECT_1(x) (((x) & 0x1f) << 5) 449 #define L2_CACHE_UPDATE_MODE(x) (((x) & 3) << 10) 450 #define VM_L2_STATUS 0x140C 451 #define L2_BUSY (1 << 0) 452 453 #define WAIT_UNTIL 0x8040 454 #define WAIT_2D_IDLE_bit (1 << 14) 455 #define WAIT_3D_IDLE_bit (1 << 15) 456 #define WAIT_2D_IDLECLEAN_bit (1 << 16) 457 #define WAIT_3D_IDLECLEAN_bit (1 << 17) 458 459 460 461 /* 462 * PM4 463 */ 464 #define PACKET_TYPE0 0 465 #define PACKET_TYPE1 1 466 #define PACKET_TYPE2 2 467 #define PACKET_TYPE3 3 468 469 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 470 #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 471 #define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2) 472 #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 473 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 474 (((reg) >> 2) & 0xFFFF) | \ 475 ((n) & 0x3FFF) << 16) 476 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 477 (((op) & 0xFF) << 8) | \ 478 ((n) & 0x3FFF) << 16) 479 480 /* Packet 3 types */ 481 #define PACKET3_NOP 0x10 482 #define PACKET3_INDIRECT_BUFFER_END 0x17 483 #define PACKET3_SET_PREDICATION 0x20 484 #define PACKET3_REG_RMW 0x21 485 #define PACKET3_COND_EXEC 0x22 486 #define PACKET3_PRED_EXEC 0x23 487 #define PACKET3_START_3D_CMDBUF 0x24 488 #define PACKET3_DRAW_INDEX_2 0x27 489 #define PACKET3_CONTEXT_CONTROL 0x28 490 #define PACKET3_DRAW_INDEX_IMMD_BE 0x29 491 #define PACKET3_INDEX_TYPE 0x2A 492 #define PACKET3_DRAW_INDEX 0x2B 493 #define PACKET3_DRAW_INDEX_AUTO 0x2D 494 #define PACKET3_DRAW_INDEX_IMMD 0x2E 495 #define PACKET3_NUM_INSTANCES 0x2F 496 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 497 #define PACKET3_INDIRECT_BUFFER_MP 0x38 498 #define PACKET3_MEM_SEMAPHORE 0x39 499 #define PACKET3_MPEG_INDEX 0x3A 500 #define PACKET3_WAIT_REG_MEM 0x3C 501 #define PACKET3_MEM_WRITE 0x3D 502 #define PACKET3_INDIRECT_BUFFER 0x32 503 #define PACKET3_CP_INTERRUPT 0x40 504 #define PACKET3_SURFACE_SYNC 0x43 505 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 506 # define PACKET3_TC_ACTION_ENA (1 << 23) 507 # define PACKET3_VC_ACTION_ENA (1 << 24) 508 # define PACKET3_CB_ACTION_ENA (1 << 25) 509 # define PACKET3_DB_ACTION_ENA (1 << 26) 510 # define PACKET3_SH_ACTION_ENA (1 << 27) 511 # define PACKET3_SMX_ACTION_ENA (1 << 28) 512 #define PACKET3_ME_INITIALIZE 0x44 513 #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 514 #define PACKET3_COND_WRITE 0x45 515 #define PACKET3_EVENT_WRITE 0x46 516 #define PACKET3_EVENT_WRITE_EOP 0x47 517 #define PACKET3_ONE_REG_WRITE 0x57 518 #define PACKET3_SET_CONFIG_REG 0x68 519 #define PACKET3_SET_CONFIG_REG_OFFSET 0x00008000 520 #define PACKET3_SET_CONFIG_REG_END 0x0000ac00 521 #define PACKET3_SET_CONTEXT_REG 0x69 522 #define PACKET3_SET_CONTEXT_REG_OFFSET 0x00028000 523 #define PACKET3_SET_CONTEXT_REG_END 0x00029000 524 #define PACKET3_SET_ALU_CONST 0x6A 525 #define PACKET3_SET_ALU_CONST_OFFSET 0x00030000 526 #define PACKET3_SET_ALU_CONST_END 0x00032000 527 #define PACKET3_SET_BOOL_CONST 0x6B 528 #define PACKET3_SET_BOOL_CONST_OFFSET 0x0003e380 529 #define PACKET3_SET_BOOL_CONST_END 0x00040000 530 #define PACKET3_SET_LOOP_CONST 0x6C 531 #define PACKET3_SET_LOOP_CONST_OFFSET 0x0003e200 532 #define PACKET3_SET_LOOP_CONST_END 0x0003e380 533 #define PACKET3_SET_RESOURCE 0x6D 534 #define PACKET3_SET_RESOURCE_OFFSET 0x00038000 535 #define PACKET3_SET_RESOURCE_END 0x0003c000 536 #define PACKET3_SET_SAMPLER 0x6E 537 #define PACKET3_SET_SAMPLER_OFFSET 0x0003c000 538 #define PACKET3_SET_SAMPLER_END 0x0003cff0 539 #define PACKET3_SET_CTL_CONST 0x6F 540 #define PACKET3_SET_CTL_CONST_OFFSET 0x0003cff0 541 #define PACKET3_SET_CTL_CONST_END 0x0003e200 542 #define PACKET3_SURFACE_BASE_UPDATE 0x73 543 544 545 #define R_008020_GRBM_SOFT_RESET 0x8020 546 #define S_008020_SOFT_RESET_CP(x) (((x) & 1) << 0) 547 #define S_008020_SOFT_RESET_CB(x) (((x) & 1) << 1) 548 #define S_008020_SOFT_RESET_CR(x) (((x) & 1) << 2) 549 #define S_008020_SOFT_RESET_DB(x) (((x) & 1) << 3) 550 #define S_008020_SOFT_RESET_PA(x) (((x) & 1) << 5) 551 #define S_008020_SOFT_RESET_SC(x) (((x) & 1) << 6) 552 #define S_008020_SOFT_RESET_SMX(x) (((x) & 1) << 7) 553 #define S_008020_SOFT_RESET_SPI(x) (((x) & 1) << 8) 554 #define S_008020_SOFT_RESET_SH(x) (((x) & 1) << 9) 555 #define S_008020_SOFT_RESET_SX(x) (((x) & 1) << 10) 556 #define S_008020_SOFT_RESET_TC(x) (((x) & 1) << 11) 557 #define S_008020_SOFT_RESET_TA(x) (((x) & 1) << 12) 558 #define S_008020_SOFT_RESET_VC(x) (((x) & 1) << 13) 559 #define S_008020_SOFT_RESET_VGT(x) (((x) & 1) << 14) 560 #define R_008010_GRBM_STATUS 0x8010 561 #define S_008010_CMDFIFO_AVAIL(x) (((x) & 0x1F) << 0) 562 #define S_008010_CP_RQ_PENDING(x) (((x) & 1) << 6) 563 #define S_008010_CF_RQ_PENDING(x) (((x) & 1) << 7) 564 #define S_008010_PF_RQ_PENDING(x) (((x) & 1) << 8) 565 #define S_008010_GRBM_EE_BUSY(x) (((x) & 1) << 10) 566 #define S_008010_VC_BUSY(x) (((x) & 1) << 11) 567 #define S_008010_DB03_CLEAN(x) (((x) & 1) << 12) 568 #define S_008010_CB03_CLEAN(x) (((x) & 1) << 13) 569 #define S_008010_VGT_BUSY_NO_DMA(x) (((x) & 1) << 16) 570 #define S_008010_VGT_BUSY(x) (((x) & 1) << 17) 571 #define S_008010_TA03_BUSY(x) (((x) & 1) << 18) 572 #define S_008010_TC_BUSY(x) (((x) & 1) << 19) 573 #define S_008010_SX_BUSY(x) (((x) & 1) << 20) 574 #define S_008010_SH_BUSY(x) (((x) & 1) << 21) 575 #define S_008010_SPI03_BUSY(x) (((x) & 1) << 22) 576 #define S_008010_SMX_BUSY(x) (((x) & 1) << 23) 577 #define S_008010_SC_BUSY(x) (((x) & 1) << 24) 578 #define S_008010_PA_BUSY(x) (((x) & 1) << 25) 579 #define S_008010_DB03_BUSY(x) (((x) & 1) << 26) 580 #define S_008010_CR_BUSY(x) (((x) & 1) << 27) 581 #define S_008010_CP_COHERENCY_BUSY(x) (((x) & 1) << 28) 582 #define S_008010_CP_BUSY(x) (((x) & 1) << 29) 583 #define S_008010_CB03_BUSY(x) (((x) & 1) << 30) 584 #define S_008010_GUI_ACTIVE(x) (((x) & 1) << 31) 585 #define G_008010_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x1F) 586 #define G_008010_CP_RQ_PENDING(x) (((x) >> 6) & 1) 587 #define G_008010_CF_RQ_PENDING(x) (((x) >> 7) & 1) 588 #define G_008010_PF_RQ_PENDING(x) (((x) >> 8) & 1) 589 #define G_008010_GRBM_EE_BUSY(x) (((x) >> 10) & 1) 590 #define G_008010_VC_BUSY(x) (((x) >> 11) & 1) 591 #define G_008010_DB03_CLEAN(x) (((x) >> 12) & 1) 592 #define G_008010_CB03_CLEAN(x) (((x) >> 13) & 1) 593 #define G_008010_VGT_BUSY_NO_DMA(x) (((x) >> 16) & 1) 594 #define G_008010_VGT_BUSY(x) (((x) >> 17) & 1) 595 #define G_008010_TA03_BUSY(x) (((x) >> 18) & 1) 596 #define G_008010_TC_BUSY(x) (((x) >> 19) & 1) 597 #define G_008010_SX_BUSY(x) (((x) >> 20) & 1) 598 #define G_008010_SH_BUSY(x) (((x) >> 21) & 1) 599 #define G_008010_SPI03_BUSY(x) (((x) >> 22) & 1) 600 #define G_008010_SMX_BUSY(x) (((x) >> 23) & 1) 601 #define G_008010_SC_BUSY(x) (((x) >> 24) & 1) 602 #define G_008010_PA_BUSY(x) (((x) >> 25) & 1) 603 #define G_008010_DB03_BUSY(x) (((x) >> 26) & 1) 604 #define G_008010_CR_BUSY(x) (((x) >> 27) & 1) 605 #define G_008010_CP_COHERENCY_BUSY(x) (((x) >> 28) & 1) 606 #define G_008010_CP_BUSY(x) (((x) >> 29) & 1) 607 #define G_008010_CB03_BUSY(x) (((x) >> 30) & 1) 608 #define G_008010_GUI_ACTIVE(x) (((x) >> 31) & 1) 609 #define R_008014_GRBM_STATUS2 0x8014 610 #define S_008014_CR_CLEAN(x) (((x) & 1) << 0) 611 #define S_008014_SMX_CLEAN(x) (((x) & 1) << 1) 612 #define S_008014_SPI0_BUSY(x) (((x) & 1) << 8) 613 #define S_008014_SPI1_BUSY(x) (((x) & 1) << 9) 614 #define S_008014_SPI2_BUSY(x) (((x) & 1) << 10) 615 #define S_008014_SPI3_BUSY(x) (((x) & 1) << 11) 616 #define S_008014_TA0_BUSY(x) (((x) & 1) << 12) 617 #define S_008014_TA1_BUSY(x) (((x) & 1) << 13) 618 #define S_008014_TA2_BUSY(x) (((x) & 1) << 14) 619 #define S_008014_TA3_BUSY(x) (((x) & 1) << 15) 620 #define S_008014_DB0_BUSY(x) (((x) & 1) << 16) 621 #define S_008014_DB1_BUSY(x) (((x) & 1) << 17) 622 #define S_008014_DB2_BUSY(x) (((x) & 1) << 18) 623 #define S_008014_DB3_BUSY(x) (((x) & 1) << 19) 624 #define S_008014_CB0_BUSY(x) (((x) & 1) << 20) 625 #define S_008014_CB1_BUSY(x) (((x) & 1) << 21) 626 #define S_008014_CB2_BUSY(x) (((x) & 1) << 22) 627 #define S_008014_CB3_BUSY(x) (((x) & 1) << 23) 628 #define G_008014_CR_CLEAN(x) (((x) >> 0) & 1) 629 #define G_008014_SMX_CLEAN(x) (((x) >> 1) & 1) 630 #define G_008014_SPI0_BUSY(x) (((x) >> 8) & 1) 631 #define G_008014_SPI1_BUSY(x) (((x) >> 9) & 1) 632 #define G_008014_SPI2_BUSY(x) (((x) >> 10) & 1) 633 #define G_008014_SPI3_BUSY(x) (((x) >> 11) & 1) 634 #define G_008014_TA0_BUSY(x) (((x) >> 12) & 1) 635 #define G_008014_TA1_BUSY(x) (((x) >> 13) & 1) 636 #define G_008014_TA2_BUSY(x) (((x) >> 14) & 1) 637 #define G_008014_TA3_BUSY(x) (((x) >> 15) & 1) 638 #define G_008014_DB0_BUSY(x) (((x) >> 16) & 1) 639 #define G_008014_DB1_BUSY(x) (((x) >> 17) & 1) 640 #define G_008014_DB2_BUSY(x) (((x) >> 18) & 1) 641 #define G_008014_DB3_BUSY(x) (((x) >> 19) & 1) 642 #define G_008014_CB0_BUSY(x) (((x) >> 20) & 1) 643 #define G_008014_CB1_BUSY(x) (((x) >> 21) & 1) 644 #define G_008014_CB2_BUSY(x) (((x) >> 22) & 1) 645 #define G_008014_CB3_BUSY(x) (((x) >> 23) & 1) 646 #define R_000E50_SRBM_STATUS 0x0E50 647 #define G_000E50_RLC_RQ_PENDING(x) (((x) >> 3) & 1) 648 #define G_000E50_RCU_RQ_PENDING(x) (((x) >> 4) & 1) 649 #define G_000E50_GRBM_RQ_PENDING(x) (((x) >> 5) & 1) 650 #define G_000E50_HI_RQ_PENDING(x) (((x) >> 6) & 1) 651 #define G_000E50_IO_EXTERN_SIGNAL(x) (((x) >> 7) & 1) 652 #define G_000E50_VMC_BUSY(x) (((x) >> 8) & 1) 653 #define G_000E50_MCB_BUSY(x) (((x) >> 9) & 1) 654 #define G_000E50_MCDZ_BUSY(x) (((x) >> 10) & 1) 655 #define G_000E50_MCDY_BUSY(x) (((x) >> 11) & 1) 656 #define G_000E50_MCDX_BUSY(x) (((x) >> 12) & 1) 657 #define G_000E50_MCDW_BUSY(x) (((x) >> 13) & 1) 658 #define G_000E50_SEM_BUSY(x) (((x) >> 14) & 1) 659 #define G_000E50_RLC_BUSY(x) (((x) >> 15) & 1) 660 #define G_000E50_BIF_BUSY(x) (((x) >> 29) & 1) 661 #define R_000E60_SRBM_SOFT_RESET 0x0E60 662 #define S_000E60_SOFT_RESET_BIF(x) (((x) & 1) << 1) 663 #define S_000E60_SOFT_RESET_CG(x) (((x) & 1) << 2) 664 #define S_000E60_SOFT_RESET_CMC(x) (((x) & 1) << 3) 665 #define S_000E60_SOFT_RESET_CSC(x) (((x) & 1) << 4) 666 #define S_000E60_SOFT_RESET_DC(x) (((x) & 1) << 5) 667 #define S_000E60_SOFT_RESET_GRBM(x) (((x) & 1) << 8) 668 #define S_000E60_SOFT_RESET_HDP(x) (((x) & 1) << 9) 669 #define S_000E60_SOFT_RESET_IH(x) (((x) & 1) << 10) 670 #define S_000E60_SOFT_RESET_MC(x) (((x) & 1) << 11) 671 #define S_000E60_SOFT_RESET_RLC(x) (((x) & 1) << 13) 672 #define S_000E60_SOFT_RESET_ROM(x) (((x) & 1) << 14) 673 #define S_000E60_SOFT_RESET_SEM(x) (((x) & 1) << 15) 674 #define S_000E60_SOFT_RESET_TSC(x) (((x) & 1) << 16) 675 #define S_000E60_SOFT_RESET_VMC(x) (((x) & 1) << 17) 676 677 #endif 678