1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/slab.h> 29 #include <linux/seq_file.h> 30 #include <linux/firmware.h> 31 #include <linux/platform_device.h> 32 #include <linux/module.h> 33 #include <drm/drmP.h> 34 #include <drm/radeon_drm.h> 35 #include "radeon.h" 36 #include "radeon_asic.h" 37 #include "radeon_mode.h" 38 #include "r600d.h" 39 #include "atom.h" 40 #include "avivod.h" 41 42 #define PFP_UCODE_SIZE 576 43 #define PM4_UCODE_SIZE 1792 44 #define RLC_UCODE_SIZE 768 45 #define R700_PFP_UCODE_SIZE 848 46 #define R700_PM4_UCODE_SIZE 1360 47 #define R700_RLC_UCODE_SIZE 1024 48 #define EVERGREEN_PFP_UCODE_SIZE 1120 49 #define EVERGREEN_PM4_UCODE_SIZE 1376 50 #define EVERGREEN_RLC_UCODE_SIZE 768 51 #define CAYMAN_RLC_UCODE_SIZE 1024 52 #define ARUBA_RLC_UCODE_SIZE 1536 53 54 /* Firmware Names */ 55 MODULE_FIRMWARE("radeon/R600_pfp.bin"); 56 MODULE_FIRMWARE("radeon/R600_me.bin"); 57 MODULE_FIRMWARE("radeon/RV610_pfp.bin"); 58 MODULE_FIRMWARE("radeon/RV610_me.bin"); 59 MODULE_FIRMWARE("radeon/RV630_pfp.bin"); 60 MODULE_FIRMWARE("radeon/RV630_me.bin"); 61 MODULE_FIRMWARE("radeon/RV620_pfp.bin"); 62 MODULE_FIRMWARE("radeon/RV620_me.bin"); 63 MODULE_FIRMWARE("radeon/RV635_pfp.bin"); 64 MODULE_FIRMWARE("radeon/RV635_me.bin"); 65 MODULE_FIRMWARE("radeon/RV670_pfp.bin"); 66 MODULE_FIRMWARE("radeon/RV670_me.bin"); 67 MODULE_FIRMWARE("radeon/RS780_pfp.bin"); 68 MODULE_FIRMWARE("radeon/RS780_me.bin"); 69 MODULE_FIRMWARE("radeon/RV770_pfp.bin"); 70 MODULE_FIRMWARE("radeon/RV770_me.bin"); 71 MODULE_FIRMWARE("radeon/RV730_pfp.bin"); 72 MODULE_FIRMWARE("radeon/RV730_me.bin"); 73 MODULE_FIRMWARE("radeon/RV710_pfp.bin"); 74 MODULE_FIRMWARE("radeon/RV710_me.bin"); 75 MODULE_FIRMWARE("radeon/R600_rlc.bin"); 76 MODULE_FIRMWARE("radeon/R700_rlc.bin"); 77 MODULE_FIRMWARE("radeon/CEDAR_pfp.bin"); 78 MODULE_FIRMWARE("radeon/CEDAR_me.bin"); 79 MODULE_FIRMWARE("radeon/CEDAR_rlc.bin"); 80 MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin"); 81 MODULE_FIRMWARE("radeon/REDWOOD_me.bin"); 82 MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin"); 83 MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin"); 84 MODULE_FIRMWARE("radeon/JUNIPER_me.bin"); 85 MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin"); 86 MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin"); 87 MODULE_FIRMWARE("radeon/CYPRESS_me.bin"); 88 MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin"); 89 MODULE_FIRMWARE("radeon/PALM_pfp.bin"); 90 MODULE_FIRMWARE("radeon/PALM_me.bin"); 91 MODULE_FIRMWARE("radeon/SUMO_rlc.bin"); 92 MODULE_FIRMWARE("radeon/SUMO_pfp.bin"); 93 MODULE_FIRMWARE("radeon/SUMO_me.bin"); 94 MODULE_FIRMWARE("radeon/SUMO2_pfp.bin"); 95 MODULE_FIRMWARE("radeon/SUMO2_me.bin"); 96 97 static const u32 crtc_offsets[2] = 98 { 99 0, 100 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL 101 }; 102 103 int r600_debugfs_mc_info_init(struct radeon_device *rdev); 104 105 /* r600,rv610,rv630,rv620,rv635,rv670 */ 106 int r600_mc_wait_for_idle(struct radeon_device *rdev); 107 static void r600_gpu_init(struct radeon_device *rdev); 108 void r600_fini(struct radeon_device *rdev); 109 void r600_irq_disable(struct radeon_device *rdev); 110 static void r600_pcie_gen2_enable(struct radeon_device *rdev); 111 112 /** 113 * r600_get_xclk - get the xclk 114 * 115 * @rdev: radeon_device pointer 116 * 117 * Returns the reference clock used by the gfx engine 118 * (r6xx, IGPs, APUs). 119 */ 120 u32 r600_get_xclk(struct radeon_device *rdev) 121 { 122 return rdev->clock.spll.reference_freq; 123 } 124 125 /* get temperature in millidegrees */ 126 int rv6xx_get_temp(struct radeon_device *rdev) 127 { 128 u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >> 129 ASIC_T_SHIFT; 130 int actual_temp = temp & 0xff; 131 132 if (temp & 0x100) 133 actual_temp -= 256; 134 135 return actual_temp * 1000; 136 } 137 138 void r600_pm_get_dynpm_state(struct radeon_device *rdev) 139 { 140 int i; 141 142 rdev->pm.dynpm_can_upclock = true; 143 rdev->pm.dynpm_can_downclock = true; 144 145 /* power state array is low to high, default is first */ 146 if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) { 147 int min_power_state_index = 0; 148 149 if (rdev->pm.num_power_states > 2) 150 min_power_state_index = 1; 151 152 switch (rdev->pm.dynpm_planned_action) { 153 case DYNPM_ACTION_MINIMUM: 154 rdev->pm.requested_power_state_index = min_power_state_index; 155 rdev->pm.requested_clock_mode_index = 0; 156 rdev->pm.dynpm_can_downclock = false; 157 break; 158 case DYNPM_ACTION_DOWNCLOCK: 159 if (rdev->pm.current_power_state_index == min_power_state_index) { 160 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 161 rdev->pm.dynpm_can_downclock = false; 162 } else { 163 if (rdev->pm.active_crtc_count > 1) { 164 for (i = 0; i < rdev->pm.num_power_states; i++) { 165 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 166 continue; 167 else if (i >= rdev->pm.current_power_state_index) { 168 rdev->pm.requested_power_state_index = 169 rdev->pm.current_power_state_index; 170 break; 171 } else { 172 rdev->pm.requested_power_state_index = i; 173 break; 174 } 175 } 176 } else { 177 if (rdev->pm.current_power_state_index == 0) 178 rdev->pm.requested_power_state_index = 179 rdev->pm.num_power_states - 1; 180 else 181 rdev->pm.requested_power_state_index = 182 rdev->pm.current_power_state_index - 1; 183 } 184 } 185 rdev->pm.requested_clock_mode_index = 0; 186 /* don't use the power state if crtcs are active and no display flag is set */ 187 if ((rdev->pm.active_crtc_count > 0) && 188 (rdev->pm.power_state[rdev->pm.requested_power_state_index]. 189 clock_info[rdev->pm.requested_clock_mode_index].flags & 190 RADEON_PM_MODE_NO_DISPLAY)) { 191 rdev->pm.requested_power_state_index++; 192 } 193 break; 194 case DYNPM_ACTION_UPCLOCK: 195 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) { 196 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 197 rdev->pm.dynpm_can_upclock = false; 198 } else { 199 if (rdev->pm.active_crtc_count > 1) { 200 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) { 201 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 202 continue; 203 else if (i <= rdev->pm.current_power_state_index) { 204 rdev->pm.requested_power_state_index = 205 rdev->pm.current_power_state_index; 206 break; 207 } else { 208 rdev->pm.requested_power_state_index = i; 209 break; 210 } 211 } 212 } else 213 rdev->pm.requested_power_state_index = 214 rdev->pm.current_power_state_index + 1; 215 } 216 rdev->pm.requested_clock_mode_index = 0; 217 break; 218 case DYNPM_ACTION_DEFAULT: 219 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; 220 rdev->pm.requested_clock_mode_index = 0; 221 rdev->pm.dynpm_can_upclock = false; 222 break; 223 case DYNPM_ACTION_NONE: 224 default: 225 DRM_ERROR("Requested mode for not defined action\n"); 226 return; 227 } 228 } else { 229 /* XXX select a power state based on AC/DC, single/dualhead, etc. */ 230 /* for now just select the first power state and switch between clock modes */ 231 /* power state array is low to high, default is first (0) */ 232 if (rdev->pm.active_crtc_count > 1) { 233 rdev->pm.requested_power_state_index = -1; 234 /* start at 1 as we don't want the default mode */ 235 for (i = 1; i < rdev->pm.num_power_states; i++) { 236 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 237 continue; 238 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) || 239 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) { 240 rdev->pm.requested_power_state_index = i; 241 break; 242 } 243 } 244 /* if nothing selected, grab the default state. */ 245 if (rdev->pm.requested_power_state_index == -1) 246 rdev->pm.requested_power_state_index = 0; 247 } else 248 rdev->pm.requested_power_state_index = 1; 249 250 switch (rdev->pm.dynpm_planned_action) { 251 case DYNPM_ACTION_MINIMUM: 252 rdev->pm.requested_clock_mode_index = 0; 253 rdev->pm.dynpm_can_downclock = false; 254 break; 255 case DYNPM_ACTION_DOWNCLOCK: 256 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) { 257 if (rdev->pm.current_clock_mode_index == 0) { 258 rdev->pm.requested_clock_mode_index = 0; 259 rdev->pm.dynpm_can_downclock = false; 260 } else 261 rdev->pm.requested_clock_mode_index = 262 rdev->pm.current_clock_mode_index - 1; 263 } else { 264 rdev->pm.requested_clock_mode_index = 0; 265 rdev->pm.dynpm_can_downclock = false; 266 } 267 /* don't use the power state if crtcs are active and no display flag is set */ 268 if ((rdev->pm.active_crtc_count > 0) && 269 (rdev->pm.power_state[rdev->pm.requested_power_state_index]. 270 clock_info[rdev->pm.requested_clock_mode_index].flags & 271 RADEON_PM_MODE_NO_DISPLAY)) { 272 rdev->pm.requested_clock_mode_index++; 273 } 274 break; 275 case DYNPM_ACTION_UPCLOCK: 276 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) { 277 if (rdev->pm.current_clock_mode_index == 278 (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) { 279 rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index; 280 rdev->pm.dynpm_can_upclock = false; 281 } else 282 rdev->pm.requested_clock_mode_index = 283 rdev->pm.current_clock_mode_index + 1; 284 } else { 285 rdev->pm.requested_clock_mode_index = 286 rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1; 287 rdev->pm.dynpm_can_upclock = false; 288 } 289 break; 290 case DYNPM_ACTION_DEFAULT: 291 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; 292 rdev->pm.requested_clock_mode_index = 0; 293 rdev->pm.dynpm_can_upclock = false; 294 break; 295 case DYNPM_ACTION_NONE: 296 default: 297 DRM_ERROR("Requested mode for not defined action\n"); 298 return; 299 } 300 } 301 302 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n", 303 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 304 clock_info[rdev->pm.requested_clock_mode_index].sclk, 305 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 306 clock_info[rdev->pm.requested_clock_mode_index].mclk, 307 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 308 pcie_lanes); 309 } 310 311 void rs780_pm_init_profile(struct radeon_device *rdev) 312 { 313 if (rdev->pm.num_power_states == 2) { 314 /* default */ 315 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 316 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 317 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 318 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 319 /* low sh */ 320 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; 321 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; 322 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 323 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 324 /* mid sh */ 325 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; 326 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0; 327 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 328 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 329 /* high sh */ 330 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; 331 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1; 332 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 333 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 334 /* low mh */ 335 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; 336 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0; 337 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 338 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 339 /* mid mh */ 340 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; 341 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0; 342 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 343 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 344 /* high mh */ 345 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; 346 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1; 347 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 348 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 349 } else if (rdev->pm.num_power_states == 3) { 350 /* default */ 351 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 352 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 353 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 354 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 355 /* low sh */ 356 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1; 357 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1; 358 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 359 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 360 /* mid sh */ 361 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1; 362 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; 363 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 364 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 365 /* high sh */ 366 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1; 367 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2; 368 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 369 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 370 /* low mh */ 371 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1; 372 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1; 373 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 374 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 375 /* mid mh */ 376 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1; 377 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1; 378 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 379 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 380 /* high mh */ 381 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1; 382 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2; 383 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 384 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 385 } else { 386 /* default */ 387 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 388 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 389 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 390 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 391 /* low sh */ 392 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2; 393 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2; 394 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 395 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 396 /* mid sh */ 397 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2; 398 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2; 399 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 400 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 401 /* high sh */ 402 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2; 403 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3; 404 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 405 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 406 /* low mh */ 407 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2; 408 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0; 409 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 410 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 411 /* mid mh */ 412 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2; 413 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0; 414 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 415 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 416 /* high mh */ 417 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2; 418 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3; 419 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 420 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 421 } 422 } 423 424 void r600_pm_init_profile(struct radeon_device *rdev) 425 { 426 int idx; 427 428 if (rdev->family == CHIP_R600) { 429 /* XXX */ 430 /* default */ 431 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 432 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 433 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 434 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 435 /* low sh */ 436 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 437 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 438 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 439 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 440 /* mid sh */ 441 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 442 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 443 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 444 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 445 /* high sh */ 446 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 447 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 448 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 449 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 450 /* low mh */ 451 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 452 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 453 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 454 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 455 /* mid mh */ 456 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 457 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 458 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 459 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 460 /* high mh */ 461 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 462 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 463 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 464 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 465 } else { 466 if (rdev->pm.num_power_states < 4) { 467 /* default */ 468 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 469 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 470 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 471 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; 472 /* low sh */ 473 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1; 474 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1; 475 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 476 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 477 /* mid sh */ 478 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1; 479 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; 480 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 481 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; 482 /* high sh */ 483 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1; 484 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1; 485 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 486 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; 487 /* low mh */ 488 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2; 489 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2; 490 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 491 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 492 /* low mh */ 493 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2; 494 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2; 495 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 496 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; 497 /* high mh */ 498 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2; 499 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2; 500 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 501 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; 502 } else { 503 /* default */ 504 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 505 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 506 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 507 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; 508 /* low sh */ 509 if (rdev->flags & RADEON_IS_MOBILITY) 510 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0); 511 else 512 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); 513 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx; 514 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx; 515 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 516 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 517 /* mid sh */ 518 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx; 519 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx; 520 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 521 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; 522 /* high sh */ 523 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); 524 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx; 525 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx; 526 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 527 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; 528 /* low mh */ 529 if (rdev->flags & RADEON_IS_MOBILITY) 530 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1); 531 else 532 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1); 533 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx; 534 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx; 535 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 536 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 537 /* mid mh */ 538 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx; 539 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx; 540 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 541 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; 542 /* high mh */ 543 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1); 544 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx; 545 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx; 546 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 547 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; 548 } 549 } 550 } 551 552 void r600_pm_misc(struct radeon_device *rdev) 553 { 554 int req_ps_idx = rdev->pm.requested_power_state_index; 555 int req_cm_idx = rdev->pm.requested_clock_mode_index; 556 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx]; 557 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage; 558 559 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) { 560 /* 0xff01 is a flag rather then an actual voltage */ 561 if (voltage->voltage == 0xff01) 562 return; 563 if (voltage->voltage != rdev->pm.current_vddc) { 564 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); 565 rdev->pm.current_vddc = voltage->voltage; 566 DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage); 567 } 568 } 569 } 570 571 bool r600_gui_idle(struct radeon_device *rdev) 572 { 573 if (RREG32(GRBM_STATUS) & GUI_ACTIVE) 574 return false; 575 else 576 return true; 577 } 578 579 /* hpd for digital panel detect/disconnect */ 580 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) 581 { 582 bool connected = false; 583 584 if (ASIC_IS_DCE3(rdev)) { 585 switch (hpd) { 586 case RADEON_HPD_1: 587 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE) 588 connected = true; 589 break; 590 case RADEON_HPD_2: 591 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE) 592 connected = true; 593 break; 594 case RADEON_HPD_3: 595 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE) 596 connected = true; 597 break; 598 case RADEON_HPD_4: 599 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE) 600 connected = true; 601 break; 602 /* DCE 3.2 */ 603 case RADEON_HPD_5: 604 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE) 605 connected = true; 606 break; 607 case RADEON_HPD_6: 608 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE) 609 connected = true; 610 break; 611 default: 612 break; 613 } 614 } else { 615 switch (hpd) { 616 case RADEON_HPD_1: 617 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) 618 connected = true; 619 break; 620 case RADEON_HPD_2: 621 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) 622 connected = true; 623 break; 624 case RADEON_HPD_3: 625 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) 626 connected = true; 627 break; 628 default: 629 break; 630 } 631 } 632 return connected; 633 } 634 635 void r600_hpd_set_polarity(struct radeon_device *rdev, 636 enum radeon_hpd_id hpd) 637 { 638 u32 tmp; 639 bool connected = r600_hpd_sense(rdev, hpd); 640 641 if (ASIC_IS_DCE3(rdev)) { 642 switch (hpd) { 643 case RADEON_HPD_1: 644 tmp = RREG32(DC_HPD1_INT_CONTROL); 645 if (connected) 646 tmp &= ~DC_HPDx_INT_POLARITY; 647 else 648 tmp |= DC_HPDx_INT_POLARITY; 649 WREG32(DC_HPD1_INT_CONTROL, tmp); 650 break; 651 case RADEON_HPD_2: 652 tmp = RREG32(DC_HPD2_INT_CONTROL); 653 if (connected) 654 tmp &= ~DC_HPDx_INT_POLARITY; 655 else 656 tmp |= DC_HPDx_INT_POLARITY; 657 WREG32(DC_HPD2_INT_CONTROL, tmp); 658 break; 659 case RADEON_HPD_3: 660 tmp = RREG32(DC_HPD3_INT_CONTROL); 661 if (connected) 662 tmp &= ~DC_HPDx_INT_POLARITY; 663 else 664 tmp |= DC_HPDx_INT_POLARITY; 665 WREG32(DC_HPD3_INT_CONTROL, tmp); 666 break; 667 case RADEON_HPD_4: 668 tmp = RREG32(DC_HPD4_INT_CONTROL); 669 if (connected) 670 tmp &= ~DC_HPDx_INT_POLARITY; 671 else 672 tmp |= DC_HPDx_INT_POLARITY; 673 WREG32(DC_HPD4_INT_CONTROL, tmp); 674 break; 675 case RADEON_HPD_5: 676 tmp = RREG32(DC_HPD5_INT_CONTROL); 677 if (connected) 678 tmp &= ~DC_HPDx_INT_POLARITY; 679 else 680 tmp |= DC_HPDx_INT_POLARITY; 681 WREG32(DC_HPD5_INT_CONTROL, tmp); 682 break; 683 /* DCE 3.2 */ 684 case RADEON_HPD_6: 685 tmp = RREG32(DC_HPD6_INT_CONTROL); 686 if (connected) 687 tmp &= ~DC_HPDx_INT_POLARITY; 688 else 689 tmp |= DC_HPDx_INT_POLARITY; 690 WREG32(DC_HPD6_INT_CONTROL, tmp); 691 break; 692 default: 693 break; 694 } 695 } else { 696 switch (hpd) { 697 case RADEON_HPD_1: 698 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); 699 if (connected) 700 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; 701 else 702 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; 703 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 704 break; 705 case RADEON_HPD_2: 706 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); 707 if (connected) 708 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; 709 else 710 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; 711 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 712 break; 713 case RADEON_HPD_3: 714 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); 715 if (connected) 716 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; 717 else 718 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; 719 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); 720 break; 721 default: 722 break; 723 } 724 } 725 } 726 727 void r600_hpd_init(struct radeon_device *rdev) 728 { 729 struct drm_device *dev = rdev->ddev; 730 struct drm_connector *connector; 731 unsigned enable = 0; 732 733 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 734 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 735 736 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || 737 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { 738 /* don't try to enable hpd on eDP or LVDS avoid breaking the 739 * aux dp channel on imac and help (but not completely fix) 740 * https://bugzilla.redhat.com/show_bug.cgi?id=726143 741 */ 742 continue; 743 } 744 if (ASIC_IS_DCE3(rdev)) { 745 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa); 746 if (ASIC_IS_DCE32(rdev)) 747 tmp |= DC_HPDx_EN; 748 749 switch (radeon_connector->hpd.hpd) { 750 case RADEON_HPD_1: 751 WREG32(DC_HPD1_CONTROL, tmp); 752 break; 753 case RADEON_HPD_2: 754 WREG32(DC_HPD2_CONTROL, tmp); 755 break; 756 case RADEON_HPD_3: 757 WREG32(DC_HPD3_CONTROL, tmp); 758 break; 759 case RADEON_HPD_4: 760 WREG32(DC_HPD4_CONTROL, tmp); 761 break; 762 /* DCE 3.2 */ 763 case RADEON_HPD_5: 764 WREG32(DC_HPD5_CONTROL, tmp); 765 break; 766 case RADEON_HPD_6: 767 WREG32(DC_HPD6_CONTROL, tmp); 768 break; 769 default: 770 break; 771 } 772 } else { 773 switch (radeon_connector->hpd.hpd) { 774 case RADEON_HPD_1: 775 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN); 776 break; 777 case RADEON_HPD_2: 778 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN); 779 break; 780 case RADEON_HPD_3: 781 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN); 782 break; 783 default: 784 break; 785 } 786 } 787 enable |= 1 << radeon_connector->hpd.hpd; 788 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); 789 } 790 radeon_irq_kms_enable_hpd(rdev, enable); 791 } 792 793 void r600_hpd_fini(struct radeon_device *rdev) 794 { 795 struct drm_device *dev = rdev->ddev; 796 struct drm_connector *connector; 797 unsigned disable = 0; 798 799 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 800 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 801 if (ASIC_IS_DCE3(rdev)) { 802 switch (radeon_connector->hpd.hpd) { 803 case RADEON_HPD_1: 804 WREG32(DC_HPD1_CONTROL, 0); 805 break; 806 case RADEON_HPD_2: 807 WREG32(DC_HPD2_CONTROL, 0); 808 break; 809 case RADEON_HPD_3: 810 WREG32(DC_HPD3_CONTROL, 0); 811 break; 812 case RADEON_HPD_4: 813 WREG32(DC_HPD4_CONTROL, 0); 814 break; 815 /* DCE 3.2 */ 816 case RADEON_HPD_5: 817 WREG32(DC_HPD5_CONTROL, 0); 818 break; 819 case RADEON_HPD_6: 820 WREG32(DC_HPD6_CONTROL, 0); 821 break; 822 default: 823 break; 824 } 825 } else { 826 switch (radeon_connector->hpd.hpd) { 827 case RADEON_HPD_1: 828 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0); 829 break; 830 case RADEON_HPD_2: 831 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0); 832 break; 833 case RADEON_HPD_3: 834 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0); 835 break; 836 default: 837 break; 838 } 839 } 840 disable |= 1 << radeon_connector->hpd.hpd; 841 } 842 radeon_irq_kms_disable_hpd(rdev, disable); 843 } 844 845 /* 846 * R600 PCIE GART 847 */ 848 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev) 849 { 850 unsigned i; 851 u32 tmp; 852 853 /* flush hdp cache so updates hit vram */ 854 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) && 855 !(rdev->flags & RADEON_IS_AGP)) { 856 void __iomem *ptr = (void *)rdev->gart.ptr; 857 u32 tmp; 858 859 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read 860 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL 861 * This seems to cause problems on some AGP cards. Just use the old 862 * method for them. 863 */ 864 WREG32(HDP_DEBUG1, 0); 865 tmp = readl((void __iomem *)ptr); 866 } else 867 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); 868 869 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12); 870 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12); 871 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1)); 872 for (i = 0; i < rdev->usec_timeout; i++) { 873 /* read MC_STATUS */ 874 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE); 875 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT; 876 if (tmp == 2) { 877 printk(KERN_WARNING "[drm] r600 flush TLB failed\n"); 878 return; 879 } 880 if (tmp) { 881 return; 882 } 883 udelay(1); 884 } 885 } 886 887 int r600_pcie_gart_init(struct radeon_device *rdev) 888 { 889 int r; 890 891 if (rdev->gart.robj) { 892 WARN(1, "R600 PCIE GART already initialized\n"); 893 return 0; 894 } 895 /* Initialize common gart structure */ 896 r = radeon_gart_init(rdev); 897 if (r) 898 return r; 899 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; 900 return radeon_gart_table_vram_alloc(rdev); 901 } 902 903 static int r600_pcie_gart_enable(struct radeon_device *rdev) 904 { 905 u32 tmp; 906 int r, i; 907 908 if (rdev->gart.robj == NULL) { 909 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 910 return -EINVAL; 911 } 912 r = radeon_gart_table_vram_pin(rdev); 913 if (r) 914 return r; 915 radeon_gart_restore(rdev); 916 917 /* Setup L2 cache */ 918 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 919 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 920 EFFECTIVE_L2_QUEUE_SIZE(7)); 921 WREG32(VM_L2_CNTL2, 0); 922 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); 923 /* Setup TLB control */ 924 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | 925 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 926 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | 927 ENABLE_WAIT_L2_QUERY; 928 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); 929 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); 930 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); 931 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); 932 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); 933 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); 934 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); 935 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); 936 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); 937 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); 938 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); 939 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); 940 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 941 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 942 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); 943 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); 944 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); 945 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | 946 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); 947 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 948 (u32)(rdev->dummy_page.addr >> 12)); 949 for (i = 1; i < 7; i++) 950 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 951 952 r600_pcie_gart_tlb_flush(rdev); 953 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 954 (unsigned)(rdev->mc.gtt_size >> 20), 955 (unsigned long long)rdev->gart.table_addr); 956 rdev->gart.ready = true; 957 return 0; 958 } 959 960 static void r600_pcie_gart_disable(struct radeon_device *rdev) 961 { 962 u32 tmp; 963 int i; 964 965 /* Disable all tables */ 966 for (i = 0; i < 7; i++) 967 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 968 969 /* Disable L2 cache */ 970 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | 971 EFFECTIVE_L2_QUEUE_SIZE(7)); 972 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); 973 /* Setup L1 TLB control */ 974 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | 975 ENABLE_WAIT_L2_QUERY; 976 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); 977 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); 978 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); 979 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); 980 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); 981 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); 982 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); 983 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); 984 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp); 985 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp); 986 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); 987 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); 988 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp); 989 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); 990 radeon_gart_table_vram_unpin(rdev); 991 } 992 993 static void r600_pcie_gart_fini(struct radeon_device *rdev) 994 { 995 radeon_gart_fini(rdev); 996 r600_pcie_gart_disable(rdev); 997 radeon_gart_table_vram_free(rdev); 998 } 999 1000 static void r600_agp_enable(struct radeon_device *rdev) 1001 { 1002 u32 tmp; 1003 int i; 1004 1005 /* Setup L2 cache */ 1006 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 1007 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 1008 EFFECTIVE_L2_QUEUE_SIZE(7)); 1009 WREG32(VM_L2_CNTL2, 0); 1010 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); 1011 /* Setup TLB control */ 1012 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | 1013 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 1014 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | 1015 ENABLE_WAIT_L2_QUERY; 1016 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); 1017 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); 1018 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); 1019 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); 1020 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); 1021 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); 1022 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); 1023 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); 1024 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); 1025 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); 1026 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); 1027 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); 1028 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 1029 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 1030 for (i = 0; i < 7; i++) 1031 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 1032 } 1033 1034 int r600_mc_wait_for_idle(struct radeon_device *rdev) 1035 { 1036 unsigned i; 1037 u32 tmp; 1038 1039 for (i = 0; i < rdev->usec_timeout; i++) { 1040 /* read MC_STATUS */ 1041 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00; 1042 if (!tmp) 1043 return 0; 1044 udelay(1); 1045 } 1046 return -1; 1047 } 1048 1049 static void r600_mc_program(struct radeon_device *rdev) 1050 { 1051 struct rv515_mc_save save; 1052 u32 tmp; 1053 int i, j; 1054 1055 /* Initialize HDP */ 1056 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 1057 WREG32((0x2c14 + j), 0x00000000); 1058 WREG32((0x2c18 + j), 0x00000000); 1059 WREG32((0x2c1c + j), 0x00000000); 1060 WREG32((0x2c20 + j), 0x00000000); 1061 WREG32((0x2c24 + j), 0x00000000); 1062 } 1063 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); 1064 1065 rv515_mc_stop(rdev, &save); 1066 if (r600_mc_wait_for_idle(rdev)) { 1067 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1068 } 1069 /* Lockout access through VGA aperture (doesn't exist before R600) */ 1070 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); 1071 /* Update configuration */ 1072 if (rdev->flags & RADEON_IS_AGP) { 1073 if (rdev->mc.vram_start < rdev->mc.gtt_start) { 1074 /* VRAM before AGP */ 1075 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 1076 rdev->mc.vram_start >> 12); 1077 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 1078 rdev->mc.gtt_end >> 12); 1079 } else { 1080 /* VRAM after AGP */ 1081 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 1082 rdev->mc.gtt_start >> 12); 1083 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 1084 rdev->mc.vram_end >> 12); 1085 } 1086 } else { 1087 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12); 1088 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12); 1089 } 1090 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); 1091 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; 1092 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); 1093 WREG32(MC_VM_FB_LOCATION, tmp); 1094 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); 1095 WREG32(HDP_NONSURFACE_INFO, (2 << 7)); 1096 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); 1097 if (rdev->flags & RADEON_IS_AGP) { 1098 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22); 1099 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22); 1100 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); 1101 } else { 1102 WREG32(MC_VM_AGP_BASE, 0); 1103 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); 1104 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); 1105 } 1106 if (r600_mc_wait_for_idle(rdev)) { 1107 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1108 } 1109 rv515_mc_resume(rdev, &save); 1110 /* we need to own VRAM, so turn off the VGA renderer here 1111 * to stop it overwriting our objects */ 1112 rv515_vga_render_disable(rdev); 1113 } 1114 1115 /** 1116 * r600_vram_gtt_location - try to find VRAM & GTT location 1117 * @rdev: radeon device structure holding all necessary informations 1118 * @mc: memory controller structure holding memory informations 1119 * 1120 * Function will place try to place VRAM at same place as in CPU (PCI) 1121 * address space as some GPU seems to have issue when we reprogram at 1122 * different address space. 1123 * 1124 * If there is not enough space to fit the unvisible VRAM after the 1125 * aperture then we limit the VRAM size to the aperture. 1126 * 1127 * If we are using AGP then place VRAM adjacent to AGP aperture are we need 1128 * them to be in one from GPU point of view so that we can program GPU to 1129 * catch access outside them (weird GPU policy see ??). 1130 * 1131 * This function will never fails, worst case are limiting VRAM or GTT. 1132 * 1133 * Note: GTT start, end, size should be initialized before calling this 1134 * function on AGP platform. 1135 */ 1136 static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) 1137 { 1138 u64 size_bf, size_af; 1139 1140 if (mc->mc_vram_size > 0xE0000000) { 1141 /* leave room for at least 512M GTT */ 1142 dev_warn(rdev->dev, "limiting VRAM\n"); 1143 mc->real_vram_size = 0xE0000000; 1144 mc->mc_vram_size = 0xE0000000; 1145 } 1146 if (rdev->flags & RADEON_IS_AGP) { 1147 size_bf = mc->gtt_start; 1148 size_af = 0xFFFFFFFF - mc->gtt_end; 1149 if (size_bf > size_af) { 1150 if (mc->mc_vram_size > size_bf) { 1151 dev_warn(rdev->dev, "limiting VRAM\n"); 1152 mc->real_vram_size = size_bf; 1153 mc->mc_vram_size = size_bf; 1154 } 1155 mc->vram_start = mc->gtt_start - mc->mc_vram_size; 1156 } else { 1157 if (mc->mc_vram_size > size_af) { 1158 dev_warn(rdev->dev, "limiting VRAM\n"); 1159 mc->real_vram_size = size_af; 1160 mc->mc_vram_size = size_af; 1161 } 1162 mc->vram_start = mc->gtt_end + 1; 1163 } 1164 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 1165 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n", 1166 mc->mc_vram_size >> 20, mc->vram_start, 1167 mc->vram_end, mc->real_vram_size >> 20); 1168 } else { 1169 u64 base = 0; 1170 if (rdev->flags & RADEON_IS_IGP) { 1171 base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF; 1172 base <<= 24; 1173 } 1174 radeon_vram_location(rdev, &rdev->mc, base); 1175 rdev->mc.gtt_base_align = 0; 1176 radeon_gtt_location(rdev, mc); 1177 } 1178 } 1179 1180 static int r600_mc_init(struct radeon_device *rdev) 1181 { 1182 u32 tmp; 1183 int chansize, numchan; 1184 1185 /* Get VRAM informations */ 1186 rdev->mc.vram_is_ddr = true; 1187 tmp = RREG32(RAMCFG); 1188 if (tmp & CHANSIZE_OVERRIDE) { 1189 chansize = 16; 1190 } else if (tmp & CHANSIZE_MASK) { 1191 chansize = 64; 1192 } else { 1193 chansize = 32; 1194 } 1195 tmp = RREG32(CHMAP); 1196 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { 1197 case 0: 1198 default: 1199 numchan = 1; 1200 break; 1201 case 1: 1202 numchan = 2; 1203 break; 1204 case 2: 1205 numchan = 4; 1206 break; 1207 case 3: 1208 numchan = 8; 1209 break; 1210 } 1211 rdev->mc.vram_width = numchan * chansize; 1212 /* Could aper size report 0 ? */ 1213 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); 1214 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); 1215 /* Setup GPU memory space */ 1216 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); 1217 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); 1218 rdev->mc.visible_vram_size = rdev->mc.aper_size; 1219 r600_vram_gtt_location(rdev, &rdev->mc); 1220 1221 if (rdev->flags & RADEON_IS_IGP) { 1222 rs690_pm_info(rdev); 1223 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); 1224 } 1225 radeon_update_bandwidth_info(rdev); 1226 return 0; 1227 } 1228 1229 int r600_vram_scratch_init(struct radeon_device *rdev) 1230 { 1231 int r; 1232 1233 if (rdev->vram_scratch.robj == NULL) { 1234 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, 1235 PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM, 1236 NULL, &rdev->vram_scratch.robj); 1237 if (r) { 1238 return r; 1239 } 1240 } 1241 1242 r = radeon_bo_reserve(rdev->vram_scratch.robj, false); 1243 if (unlikely(r != 0)) 1244 return r; 1245 r = radeon_bo_pin(rdev->vram_scratch.robj, 1246 RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr); 1247 if (r) { 1248 radeon_bo_unreserve(rdev->vram_scratch.robj); 1249 return r; 1250 } 1251 r = radeon_bo_kmap(rdev->vram_scratch.robj, 1252 (void **)&rdev->vram_scratch.ptr); 1253 if (r) 1254 radeon_bo_unpin(rdev->vram_scratch.robj); 1255 radeon_bo_unreserve(rdev->vram_scratch.robj); 1256 1257 return r; 1258 } 1259 1260 void r600_vram_scratch_fini(struct radeon_device *rdev) 1261 { 1262 int r; 1263 1264 if (rdev->vram_scratch.robj == NULL) { 1265 return; 1266 } 1267 r = radeon_bo_reserve(rdev->vram_scratch.robj, false); 1268 if (likely(r == 0)) { 1269 radeon_bo_kunmap(rdev->vram_scratch.robj); 1270 radeon_bo_unpin(rdev->vram_scratch.robj); 1271 radeon_bo_unreserve(rdev->vram_scratch.robj); 1272 } 1273 radeon_bo_unref(&rdev->vram_scratch.robj); 1274 } 1275 1276 void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung) 1277 { 1278 u32 tmp = RREG32(R600_BIOS_3_SCRATCH); 1279 1280 if (hung) 1281 tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG; 1282 else 1283 tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG; 1284 1285 WREG32(R600_BIOS_3_SCRATCH, tmp); 1286 } 1287 1288 static void r600_print_gpu_status_regs(struct radeon_device *rdev) 1289 { 1290 dev_info(rdev->dev, " R_008010_GRBM_STATUS = 0x%08X\n", 1291 RREG32(R_008010_GRBM_STATUS)); 1292 dev_info(rdev->dev, " R_008014_GRBM_STATUS2 = 0x%08X\n", 1293 RREG32(R_008014_GRBM_STATUS2)); 1294 dev_info(rdev->dev, " R_000E50_SRBM_STATUS = 0x%08X\n", 1295 RREG32(R_000E50_SRBM_STATUS)); 1296 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n", 1297 RREG32(CP_STALLED_STAT1)); 1298 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n", 1299 RREG32(CP_STALLED_STAT2)); 1300 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n", 1301 RREG32(CP_BUSY_STAT)); 1302 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n", 1303 RREG32(CP_STAT)); 1304 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n", 1305 RREG32(DMA_STATUS_REG)); 1306 } 1307 1308 static bool r600_is_display_hung(struct radeon_device *rdev) 1309 { 1310 u32 crtc_hung = 0; 1311 u32 crtc_status[2]; 1312 u32 i, j, tmp; 1313 1314 for (i = 0; i < rdev->num_crtc; i++) { 1315 if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN) { 1316 crtc_status[i] = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]); 1317 crtc_hung |= (1 << i); 1318 } 1319 } 1320 1321 for (j = 0; j < 10; j++) { 1322 for (i = 0; i < rdev->num_crtc; i++) { 1323 if (crtc_hung & (1 << i)) { 1324 tmp = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]); 1325 if (tmp != crtc_status[i]) 1326 crtc_hung &= ~(1 << i); 1327 } 1328 } 1329 if (crtc_hung == 0) 1330 return false; 1331 udelay(100); 1332 } 1333 1334 return true; 1335 } 1336 1337 static u32 r600_gpu_check_soft_reset(struct radeon_device *rdev) 1338 { 1339 u32 reset_mask = 0; 1340 u32 tmp; 1341 1342 /* GRBM_STATUS */ 1343 tmp = RREG32(R_008010_GRBM_STATUS); 1344 if (rdev->family >= CHIP_RV770) { 1345 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) | 1346 G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) | 1347 G_008010_TA_BUSY(tmp) | G_008010_VGT_BUSY(tmp) | 1348 G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) | 1349 G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp)) 1350 reset_mask |= RADEON_RESET_GFX; 1351 } else { 1352 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) | 1353 G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) | 1354 G_008010_TA03_BUSY(tmp) | G_008010_VGT_BUSY(tmp) | 1355 G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) | 1356 G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp)) 1357 reset_mask |= RADEON_RESET_GFX; 1358 } 1359 1360 if (G_008010_CF_RQ_PENDING(tmp) | G_008010_PF_RQ_PENDING(tmp) | 1361 G_008010_CP_BUSY(tmp) | G_008010_CP_COHERENCY_BUSY(tmp)) 1362 reset_mask |= RADEON_RESET_CP; 1363 1364 if (G_008010_GRBM_EE_BUSY(tmp)) 1365 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP; 1366 1367 /* DMA_STATUS_REG */ 1368 tmp = RREG32(DMA_STATUS_REG); 1369 if (!(tmp & DMA_IDLE)) 1370 reset_mask |= RADEON_RESET_DMA; 1371 1372 /* SRBM_STATUS */ 1373 tmp = RREG32(R_000E50_SRBM_STATUS); 1374 if (G_000E50_RLC_RQ_PENDING(tmp) | G_000E50_RLC_BUSY(tmp)) 1375 reset_mask |= RADEON_RESET_RLC; 1376 1377 if (G_000E50_IH_BUSY(tmp)) 1378 reset_mask |= RADEON_RESET_IH; 1379 1380 if (G_000E50_SEM_BUSY(tmp)) 1381 reset_mask |= RADEON_RESET_SEM; 1382 1383 if (G_000E50_GRBM_RQ_PENDING(tmp)) 1384 reset_mask |= RADEON_RESET_GRBM; 1385 1386 if (G_000E50_VMC_BUSY(tmp)) 1387 reset_mask |= RADEON_RESET_VMC; 1388 1389 if (G_000E50_MCB_BUSY(tmp) | G_000E50_MCDZ_BUSY(tmp) | 1390 G_000E50_MCDY_BUSY(tmp) | G_000E50_MCDX_BUSY(tmp) | 1391 G_000E50_MCDW_BUSY(tmp)) 1392 reset_mask |= RADEON_RESET_MC; 1393 1394 if (r600_is_display_hung(rdev)) 1395 reset_mask |= RADEON_RESET_DISPLAY; 1396 1397 /* Skip MC reset as it's mostly likely not hung, just busy */ 1398 if (reset_mask & RADEON_RESET_MC) { 1399 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask); 1400 reset_mask &= ~RADEON_RESET_MC; 1401 } 1402 1403 return reset_mask; 1404 } 1405 1406 static void r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) 1407 { 1408 struct rv515_mc_save save; 1409 u32 grbm_soft_reset = 0, srbm_soft_reset = 0; 1410 u32 tmp; 1411 1412 if (reset_mask == 0) 1413 return; 1414 1415 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask); 1416 1417 r600_print_gpu_status_regs(rdev); 1418 1419 /* Disable CP parsing/prefetching */ 1420 if (rdev->family >= CHIP_RV770) 1421 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1)); 1422 else 1423 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); 1424 1425 /* disable the RLC */ 1426 WREG32(RLC_CNTL, 0); 1427 1428 if (reset_mask & RADEON_RESET_DMA) { 1429 /* Disable DMA */ 1430 tmp = RREG32(DMA_RB_CNTL); 1431 tmp &= ~DMA_RB_ENABLE; 1432 WREG32(DMA_RB_CNTL, tmp); 1433 } 1434 1435 mdelay(50); 1436 1437 rv515_mc_stop(rdev, &save); 1438 if (r600_mc_wait_for_idle(rdev)) { 1439 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1440 } 1441 1442 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) { 1443 if (rdev->family >= CHIP_RV770) 1444 grbm_soft_reset |= S_008020_SOFT_RESET_DB(1) | 1445 S_008020_SOFT_RESET_CB(1) | 1446 S_008020_SOFT_RESET_PA(1) | 1447 S_008020_SOFT_RESET_SC(1) | 1448 S_008020_SOFT_RESET_SPI(1) | 1449 S_008020_SOFT_RESET_SX(1) | 1450 S_008020_SOFT_RESET_SH(1) | 1451 S_008020_SOFT_RESET_TC(1) | 1452 S_008020_SOFT_RESET_TA(1) | 1453 S_008020_SOFT_RESET_VC(1) | 1454 S_008020_SOFT_RESET_VGT(1); 1455 else 1456 grbm_soft_reset |= S_008020_SOFT_RESET_CR(1) | 1457 S_008020_SOFT_RESET_DB(1) | 1458 S_008020_SOFT_RESET_CB(1) | 1459 S_008020_SOFT_RESET_PA(1) | 1460 S_008020_SOFT_RESET_SC(1) | 1461 S_008020_SOFT_RESET_SMX(1) | 1462 S_008020_SOFT_RESET_SPI(1) | 1463 S_008020_SOFT_RESET_SX(1) | 1464 S_008020_SOFT_RESET_SH(1) | 1465 S_008020_SOFT_RESET_TC(1) | 1466 S_008020_SOFT_RESET_TA(1) | 1467 S_008020_SOFT_RESET_VC(1) | 1468 S_008020_SOFT_RESET_VGT(1); 1469 } 1470 1471 if (reset_mask & RADEON_RESET_CP) { 1472 grbm_soft_reset |= S_008020_SOFT_RESET_CP(1) | 1473 S_008020_SOFT_RESET_VGT(1); 1474 1475 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1); 1476 } 1477 1478 if (reset_mask & RADEON_RESET_DMA) { 1479 if (rdev->family >= CHIP_RV770) 1480 srbm_soft_reset |= RV770_SOFT_RESET_DMA; 1481 else 1482 srbm_soft_reset |= SOFT_RESET_DMA; 1483 } 1484 1485 if (reset_mask & RADEON_RESET_RLC) 1486 srbm_soft_reset |= S_000E60_SOFT_RESET_RLC(1); 1487 1488 if (reset_mask & RADEON_RESET_SEM) 1489 srbm_soft_reset |= S_000E60_SOFT_RESET_SEM(1); 1490 1491 if (reset_mask & RADEON_RESET_IH) 1492 srbm_soft_reset |= S_000E60_SOFT_RESET_IH(1); 1493 1494 if (reset_mask & RADEON_RESET_GRBM) 1495 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1); 1496 1497 if (!(rdev->flags & RADEON_IS_IGP)) { 1498 if (reset_mask & RADEON_RESET_MC) 1499 srbm_soft_reset |= S_000E60_SOFT_RESET_MC(1); 1500 } 1501 1502 if (reset_mask & RADEON_RESET_VMC) 1503 srbm_soft_reset |= S_000E60_SOFT_RESET_VMC(1); 1504 1505 if (grbm_soft_reset) { 1506 tmp = RREG32(R_008020_GRBM_SOFT_RESET); 1507 tmp |= grbm_soft_reset; 1508 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp); 1509 WREG32(R_008020_GRBM_SOFT_RESET, tmp); 1510 tmp = RREG32(R_008020_GRBM_SOFT_RESET); 1511 1512 udelay(50); 1513 1514 tmp &= ~grbm_soft_reset; 1515 WREG32(R_008020_GRBM_SOFT_RESET, tmp); 1516 tmp = RREG32(R_008020_GRBM_SOFT_RESET); 1517 } 1518 1519 if (srbm_soft_reset) { 1520 tmp = RREG32(SRBM_SOFT_RESET); 1521 tmp |= srbm_soft_reset; 1522 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1523 WREG32(SRBM_SOFT_RESET, tmp); 1524 tmp = RREG32(SRBM_SOFT_RESET); 1525 1526 udelay(50); 1527 1528 tmp &= ~srbm_soft_reset; 1529 WREG32(SRBM_SOFT_RESET, tmp); 1530 tmp = RREG32(SRBM_SOFT_RESET); 1531 } 1532 1533 /* Wait a little for things to settle down */ 1534 mdelay(1); 1535 1536 rv515_mc_resume(rdev, &save); 1537 udelay(50); 1538 1539 r600_print_gpu_status_regs(rdev); 1540 } 1541 1542 int r600_asic_reset(struct radeon_device *rdev) 1543 { 1544 u32 reset_mask; 1545 1546 reset_mask = r600_gpu_check_soft_reset(rdev); 1547 1548 if (reset_mask) 1549 r600_set_bios_scratch_engine_hung(rdev, true); 1550 1551 r600_gpu_soft_reset(rdev, reset_mask); 1552 1553 reset_mask = r600_gpu_check_soft_reset(rdev); 1554 1555 if (!reset_mask) 1556 r600_set_bios_scratch_engine_hung(rdev, false); 1557 1558 return 0; 1559 } 1560 1561 /** 1562 * r600_gfx_is_lockup - Check if the GFX engine is locked up 1563 * 1564 * @rdev: radeon_device pointer 1565 * @ring: radeon_ring structure holding ring information 1566 * 1567 * Check if the GFX engine is locked up. 1568 * Returns true if the engine appears to be locked up, false if not. 1569 */ 1570 bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 1571 { 1572 u32 reset_mask = r600_gpu_check_soft_reset(rdev); 1573 1574 if (!(reset_mask & (RADEON_RESET_GFX | 1575 RADEON_RESET_COMPUTE | 1576 RADEON_RESET_CP))) { 1577 radeon_ring_lockup_update(ring); 1578 return false; 1579 } 1580 /* force CP activities */ 1581 radeon_ring_force_activity(rdev, ring); 1582 return radeon_ring_test_lockup(rdev, ring); 1583 } 1584 1585 /** 1586 * r600_dma_is_lockup - Check if the DMA engine is locked up 1587 * 1588 * @rdev: radeon_device pointer 1589 * @ring: radeon_ring structure holding ring information 1590 * 1591 * Check if the async DMA engine is locked up. 1592 * Returns true if the engine appears to be locked up, false if not. 1593 */ 1594 bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 1595 { 1596 u32 reset_mask = r600_gpu_check_soft_reset(rdev); 1597 1598 if (!(reset_mask & RADEON_RESET_DMA)) { 1599 radeon_ring_lockup_update(ring); 1600 return false; 1601 } 1602 /* force ring activities */ 1603 radeon_ring_force_activity(rdev, ring); 1604 return radeon_ring_test_lockup(rdev, ring); 1605 } 1606 1607 u32 r6xx_remap_render_backend(struct radeon_device *rdev, 1608 u32 tiling_pipe_num, 1609 u32 max_rb_num, 1610 u32 total_max_rb_num, 1611 u32 disabled_rb_mask) 1612 { 1613 u32 rendering_pipe_num, rb_num_width, req_rb_num; 1614 u32 pipe_rb_ratio, pipe_rb_remain, tmp; 1615 u32 data = 0, mask = 1 << (max_rb_num - 1); 1616 unsigned i, j; 1617 1618 /* mask out the RBs that don't exist on that asic */ 1619 tmp = disabled_rb_mask | ((0xff << max_rb_num) & 0xff); 1620 /* make sure at least one RB is available */ 1621 if ((tmp & 0xff) != 0xff) 1622 disabled_rb_mask = tmp; 1623 1624 rendering_pipe_num = 1 << tiling_pipe_num; 1625 req_rb_num = total_max_rb_num - r600_count_pipe_bits(disabled_rb_mask); 1626 BUG_ON(rendering_pipe_num < req_rb_num); 1627 1628 pipe_rb_ratio = rendering_pipe_num / req_rb_num; 1629 pipe_rb_remain = rendering_pipe_num - pipe_rb_ratio * req_rb_num; 1630 1631 if (rdev->family <= CHIP_RV740) { 1632 /* r6xx/r7xx */ 1633 rb_num_width = 2; 1634 } else { 1635 /* eg+ */ 1636 rb_num_width = 4; 1637 } 1638 1639 for (i = 0; i < max_rb_num; i++) { 1640 if (!(mask & disabled_rb_mask)) { 1641 for (j = 0; j < pipe_rb_ratio; j++) { 1642 data <<= rb_num_width; 1643 data |= max_rb_num - i - 1; 1644 } 1645 if (pipe_rb_remain) { 1646 data <<= rb_num_width; 1647 data |= max_rb_num - i - 1; 1648 pipe_rb_remain--; 1649 } 1650 } 1651 mask >>= 1; 1652 } 1653 1654 return data; 1655 } 1656 1657 int r600_count_pipe_bits(uint32_t val) 1658 { 1659 return hweight32(val); 1660 } 1661 1662 static void r600_gpu_init(struct radeon_device *rdev) 1663 { 1664 u32 tiling_config; 1665 u32 ramcfg; 1666 u32 cc_rb_backend_disable; 1667 u32 cc_gc_shader_pipe_config; 1668 u32 tmp; 1669 int i, j; 1670 u32 sq_config; 1671 u32 sq_gpr_resource_mgmt_1 = 0; 1672 u32 sq_gpr_resource_mgmt_2 = 0; 1673 u32 sq_thread_resource_mgmt = 0; 1674 u32 sq_stack_resource_mgmt_1 = 0; 1675 u32 sq_stack_resource_mgmt_2 = 0; 1676 u32 disabled_rb_mask; 1677 1678 rdev->config.r600.tiling_group_size = 256; 1679 switch (rdev->family) { 1680 case CHIP_R600: 1681 rdev->config.r600.max_pipes = 4; 1682 rdev->config.r600.max_tile_pipes = 8; 1683 rdev->config.r600.max_simds = 4; 1684 rdev->config.r600.max_backends = 4; 1685 rdev->config.r600.max_gprs = 256; 1686 rdev->config.r600.max_threads = 192; 1687 rdev->config.r600.max_stack_entries = 256; 1688 rdev->config.r600.max_hw_contexts = 8; 1689 rdev->config.r600.max_gs_threads = 16; 1690 rdev->config.r600.sx_max_export_size = 128; 1691 rdev->config.r600.sx_max_export_pos_size = 16; 1692 rdev->config.r600.sx_max_export_smx_size = 128; 1693 rdev->config.r600.sq_num_cf_insts = 2; 1694 break; 1695 case CHIP_RV630: 1696 case CHIP_RV635: 1697 rdev->config.r600.max_pipes = 2; 1698 rdev->config.r600.max_tile_pipes = 2; 1699 rdev->config.r600.max_simds = 3; 1700 rdev->config.r600.max_backends = 1; 1701 rdev->config.r600.max_gprs = 128; 1702 rdev->config.r600.max_threads = 192; 1703 rdev->config.r600.max_stack_entries = 128; 1704 rdev->config.r600.max_hw_contexts = 8; 1705 rdev->config.r600.max_gs_threads = 4; 1706 rdev->config.r600.sx_max_export_size = 128; 1707 rdev->config.r600.sx_max_export_pos_size = 16; 1708 rdev->config.r600.sx_max_export_smx_size = 128; 1709 rdev->config.r600.sq_num_cf_insts = 2; 1710 break; 1711 case CHIP_RV610: 1712 case CHIP_RV620: 1713 case CHIP_RS780: 1714 case CHIP_RS880: 1715 rdev->config.r600.max_pipes = 1; 1716 rdev->config.r600.max_tile_pipes = 1; 1717 rdev->config.r600.max_simds = 2; 1718 rdev->config.r600.max_backends = 1; 1719 rdev->config.r600.max_gprs = 128; 1720 rdev->config.r600.max_threads = 192; 1721 rdev->config.r600.max_stack_entries = 128; 1722 rdev->config.r600.max_hw_contexts = 4; 1723 rdev->config.r600.max_gs_threads = 4; 1724 rdev->config.r600.sx_max_export_size = 128; 1725 rdev->config.r600.sx_max_export_pos_size = 16; 1726 rdev->config.r600.sx_max_export_smx_size = 128; 1727 rdev->config.r600.sq_num_cf_insts = 1; 1728 break; 1729 case CHIP_RV670: 1730 rdev->config.r600.max_pipes = 4; 1731 rdev->config.r600.max_tile_pipes = 4; 1732 rdev->config.r600.max_simds = 4; 1733 rdev->config.r600.max_backends = 4; 1734 rdev->config.r600.max_gprs = 192; 1735 rdev->config.r600.max_threads = 192; 1736 rdev->config.r600.max_stack_entries = 256; 1737 rdev->config.r600.max_hw_contexts = 8; 1738 rdev->config.r600.max_gs_threads = 16; 1739 rdev->config.r600.sx_max_export_size = 128; 1740 rdev->config.r600.sx_max_export_pos_size = 16; 1741 rdev->config.r600.sx_max_export_smx_size = 128; 1742 rdev->config.r600.sq_num_cf_insts = 2; 1743 break; 1744 default: 1745 break; 1746 } 1747 1748 /* Initialize HDP */ 1749 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 1750 WREG32((0x2c14 + j), 0x00000000); 1751 WREG32((0x2c18 + j), 0x00000000); 1752 WREG32((0x2c1c + j), 0x00000000); 1753 WREG32((0x2c20 + j), 0x00000000); 1754 WREG32((0x2c24 + j), 0x00000000); 1755 } 1756 1757 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); 1758 1759 /* Setup tiling */ 1760 tiling_config = 0; 1761 ramcfg = RREG32(RAMCFG); 1762 switch (rdev->config.r600.max_tile_pipes) { 1763 case 1: 1764 tiling_config |= PIPE_TILING(0); 1765 break; 1766 case 2: 1767 tiling_config |= PIPE_TILING(1); 1768 break; 1769 case 4: 1770 tiling_config |= PIPE_TILING(2); 1771 break; 1772 case 8: 1773 tiling_config |= PIPE_TILING(3); 1774 break; 1775 default: 1776 break; 1777 } 1778 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes; 1779 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); 1780 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); 1781 tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT); 1782 1783 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT; 1784 if (tmp > 3) { 1785 tiling_config |= ROW_TILING(3); 1786 tiling_config |= SAMPLE_SPLIT(3); 1787 } else { 1788 tiling_config |= ROW_TILING(tmp); 1789 tiling_config |= SAMPLE_SPLIT(tmp); 1790 } 1791 tiling_config |= BANK_SWAPS(1); 1792 1793 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000; 1794 tmp = R6XX_MAX_BACKENDS - 1795 r600_count_pipe_bits((cc_rb_backend_disable >> 16) & R6XX_MAX_BACKENDS_MASK); 1796 if (tmp < rdev->config.r600.max_backends) { 1797 rdev->config.r600.max_backends = tmp; 1798 } 1799 1800 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0x00ffff00; 1801 tmp = R6XX_MAX_PIPES - 1802 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 8) & R6XX_MAX_PIPES_MASK); 1803 if (tmp < rdev->config.r600.max_pipes) { 1804 rdev->config.r600.max_pipes = tmp; 1805 } 1806 tmp = R6XX_MAX_SIMDS - 1807 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R6XX_MAX_SIMDS_MASK); 1808 if (tmp < rdev->config.r600.max_simds) { 1809 rdev->config.r600.max_simds = tmp; 1810 } 1811 1812 disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R6XX_MAX_BACKENDS_MASK; 1813 tmp = (tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT; 1814 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends, 1815 R6XX_MAX_BACKENDS, disabled_rb_mask); 1816 tiling_config |= tmp << 16; 1817 rdev->config.r600.backend_map = tmp; 1818 1819 rdev->config.r600.tile_config = tiling_config; 1820 WREG32(GB_TILING_CONFIG, tiling_config); 1821 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff); 1822 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff); 1823 WREG32(DMA_TILING_CONFIG, tiling_config & 0xffff); 1824 1825 tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8); 1826 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK); 1827 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK); 1828 1829 /* Setup some CP states */ 1830 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b))); 1831 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40))); 1832 1833 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT | 1834 SYNC_WALKER | SYNC_ALIGNER)); 1835 /* Setup various GPU states */ 1836 if (rdev->family == CHIP_RV670) 1837 WREG32(ARB_GDEC_RD_CNTL, 0x00000021); 1838 1839 tmp = RREG32(SX_DEBUG_1); 1840 tmp |= SMX_EVENT_RELEASE; 1841 if ((rdev->family > CHIP_R600)) 1842 tmp |= ENABLE_NEW_SMX_ADDRESS; 1843 WREG32(SX_DEBUG_1, tmp); 1844 1845 if (((rdev->family) == CHIP_R600) || 1846 ((rdev->family) == CHIP_RV630) || 1847 ((rdev->family) == CHIP_RV610) || 1848 ((rdev->family) == CHIP_RV620) || 1849 ((rdev->family) == CHIP_RS780) || 1850 ((rdev->family) == CHIP_RS880)) { 1851 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE); 1852 } else { 1853 WREG32(DB_DEBUG, 0); 1854 } 1855 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) | 1856 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4))); 1857 1858 WREG32(PA_SC_MULTI_CHIP_CNTL, 0); 1859 WREG32(VGT_NUM_INSTANCES, 0); 1860 1861 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0)); 1862 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0)); 1863 1864 tmp = RREG32(SQ_MS_FIFO_SIZES); 1865 if (((rdev->family) == CHIP_RV610) || 1866 ((rdev->family) == CHIP_RV620) || 1867 ((rdev->family) == CHIP_RS780) || 1868 ((rdev->family) == CHIP_RS880)) { 1869 tmp = (CACHE_FIFO_SIZE(0xa) | 1870 FETCH_FIFO_HIWATER(0xa) | 1871 DONE_FIFO_HIWATER(0xe0) | 1872 ALU_UPDATE_FIFO_HIWATER(0x8)); 1873 } else if (((rdev->family) == CHIP_R600) || 1874 ((rdev->family) == CHIP_RV630)) { 1875 tmp &= ~DONE_FIFO_HIWATER(0xff); 1876 tmp |= DONE_FIFO_HIWATER(0x4); 1877 } 1878 WREG32(SQ_MS_FIFO_SIZES, tmp); 1879 1880 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT 1881 * should be adjusted as needed by the 2D/3D drivers. This just sets default values 1882 */ 1883 sq_config = RREG32(SQ_CONFIG); 1884 sq_config &= ~(PS_PRIO(3) | 1885 VS_PRIO(3) | 1886 GS_PRIO(3) | 1887 ES_PRIO(3)); 1888 sq_config |= (DX9_CONSTS | 1889 VC_ENABLE | 1890 PS_PRIO(0) | 1891 VS_PRIO(1) | 1892 GS_PRIO(2) | 1893 ES_PRIO(3)); 1894 1895 if ((rdev->family) == CHIP_R600) { 1896 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) | 1897 NUM_VS_GPRS(124) | 1898 NUM_CLAUSE_TEMP_GPRS(4)); 1899 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) | 1900 NUM_ES_GPRS(0)); 1901 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) | 1902 NUM_VS_THREADS(48) | 1903 NUM_GS_THREADS(4) | 1904 NUM_ES_THREADS(4)); 1905 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) | 1906 NUM_VS_STACK_ENTRIES(128)); 1907 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) | 1908 NUM_ES_STACK_ENTRIES(0)); 1909 } else if (((rdev->family) == CHIP_RV610) || 1910 ((rdev->family) == CHIP_RV620) || 1911 ((rdev->family) == CHIP_RS780) || 1912 ((rdev->family) == CHIP_RS880)) { 1913 /* no vertex cache */ 1914 sq_config &= ~VC_ENABLE; 1915 1916 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | 1917 NUM_VS_GPRS(44) | 1918 NUM_CLAUSE_TEMP_GPRS(2)); 1919 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | 1920 NUM_ES_GPRS(17)); 1921 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | 1922 NUM_VS_THREADS(78) | 1923 NUM_GS_THREADS(4) | 1924 NUM_ES_THREADS(31)); 1925 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | 1926 NUM_VS_STACK_ENTRIES(40)); 1927 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | 1928 NUM_ES_STACK_ENTRIES(16)); 1929 } else if (((rdev->family) == CHIP_RV630) || 1930 ((rdev->family) == CHIP_RV635)) { 1931 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | 1932 NUM_VS_GPRS(44) | 1933 NUM_CLAUSE_TEMP_GPRS(2)); 1934 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) | 1935 NUM_ES_GPRS(18)); 1936 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | 1937 NUM_VS_THREADS(78) | 1938 NUM_GS_THREADS(4) | 1939 NUM_ES_THREADS(31)); 1940 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | 1941 NUM_VS_STACK_ENTRIES(40)); 1942 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | 1943 NUM_ES_STACK_ENTRIES(16)); 1944 } else if ((rdev->family) == CHIP_RV670) { 1945 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | 1946 NUM_VS_GPRS(44) | 1947 NUM_CLAUSE_TEMP_GPRS(2)); 1948 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | 1949 NUM_ES_GPRS(17)); 1950 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | 1951 NUM_VS_THREADS(78) | 1952 NUM_GS_THREADS(4) | 1953 NUM_ES_THREADS(31)); 1954 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) | 1955 NUM_VS_STACK_ENTRIES(64)); 1956 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) | 1957 NUM_ES_STACK_ENTRIES(64)); 1958 } 1959 1960 WREG32(SQ_CONFIG, sq_config); 1961 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1); 1962 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2); 1963 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); 1964 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1); 1965 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2); 1966 1967 if (((rdev->family) == CHIP_RV610) || 1968 ((rdev->family) == CHIP_RV620) || 1969 ((rdev->family) == CHIP_RS780) || 1970 ((rdev->family) == CHIP_RS880)) { 1971 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY)); 1972 } else { 1973 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC)); 1974 } 1975 1976 /* More default values. 2D/3D driver should adjust as needed */ 1977 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) | 1978 S1_X(0x4) | S1_Y(0xc))); 1979 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) | 1980 S1_X(0x2) | S1_Y(0x2) | 1981 S2_X(0xa) | S2_Y(0x6) | 1982 S3_X(0x6) | S3_Y(0xa))); 1983 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) | 1984 S1_X(0x4) | S1_Y(0xc) | 1985 S2_X(0x1) | S2_Y(0x6) | 1986 S3_X(0xa) | S3_Y(0xe))); 1987 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) | 1988 S5_X(0x0) | S5_Y(0x0) | 1989 S6_X(0xb) | S6_Y(0x4) | 1990 S7_X(0x7) | S7_Y(0x8))); 1991 1992 WREG32(VGT_STRMOUT_EN, 0); 1993 tmp = rdev->config.r600.max_pipes * 16; 1994 switch (rdev->family) { 1995 case CHIP_RV610: 1996 case CHIP_RV620: 1997 case CHIP_RS780: 1998 case CHIP_RS880: 1999 tmp += 32; 2000 break; 2001 case CHIP_RV670: 2002 tmp += 128; 2003 break; 2004 default: 2005 break; 2006 } 2007 if (tmp > 256) { 2008 tmp = 256; 2009 } 2010 WREG32(VGT_ES_PER_GS, 128); 2011 WREG32(VGT_GS_PER_ES, tmp); 2012 WREG32(VGT_GS_PER_VS, 2); 2013 WREG32(VGT_GS_VERTEX_REUSE, 16); 2014 2015 /* more default values. 2D/3D driver should adjust as needed */ 2016 WREG32(PA_SC_LINE_STIPPLE_STATE, 0); 2017 WREG32(VGT_STRMOUT_EN, 0); 2018 WREG32(SX_MISC, 0); 2019 WREG32(PA_SC_MODE_CNTL, 0); 2020 WREG32(PA_SC_AA_CONFIG, 0); 2021 WREG32(PA_SC_LINE_STIPPLE, 0); 2022 WREG32(SPI_INPUT_Z, 0); 2023 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2)); 2024 WREG32(CB_COLOR7_FRAG, 0); 2025 2026 /* Clear render buffer base addresses */ 2027 WREG32(CB_COLOR0_BASE, 0); 2028 WREG32(CB_COLOR1_BASE, 0); 2029 WREG32(CB_COLOR2_BASE, 0); 2030 WREG32(CB_COLOR3_BASE, 0); 2031 WREG32(CB_COLOR4_BASE, 0); 2032 WREG32(CB_COLOR5_BASE, 0); 2033 WREG32(CB_COLOR6_BASE, 0); 2034 WREG32(CB_COLOR7_BASE, 0); 2035 WREG32(CB_COLOR7_FRAG, 0); 2036 2037 switch (rdev->family) { 2038 case CHIP_RV610: 2039 case CHIP_RV620: 2040 case CHIP_RS780: 2041 case CHIP_RS880: 2042 tmp = TC_L2_SIZE(8); 2043 break; 2044 case CHIP_RV630: 2045 case CHIP_RV635: 2046 tmp = TC_L2_SIZE(4); 2047 break; 2048 case CHIP_R600: 2049 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT; 2050 break; 2051 default: 2052 tmp = TC_L2_SIZE(0); 2053 break; 2054 } 2055 WREG32(TC_CNTL, tmp); 2056 2057 tmp = RREG32(HDP_HOST_PATH_CNTL); 2058 WREG32(HDP_HOST_PATH_CNTL, tmp); 2059 2060 tmp = RREG32(ARB_POP); 2061 tmp |= ENABLE_TC128; 2062 WREG32(ARB_POP, tmp); 2063 2064 WREG32(PA_SC_MULTI_CHIP_CNTL, 0); 2065 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | 2066 NUM_CLIP_SEQ(3))); 2067 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095)); 2068 WREG32(VC_ENHANCE, 0); 2069 } 2070 2071 2072 /* 2073 * Indirect registers accessor 2074 */ 2075 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg) 2076 { 2077 u32 r; 2078 2079 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); 2080 (void)RREG32(PCIE_PORT_INDEX); 2081 r = RREG32(PCIE_PORT_DATA); 2082 return r; 2083 } 2084 2085 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2086 { 2087 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); 2088 (void)RREG32(PCIE_PORT_INDEX); 2089 WREG32(PCIE_PORT_DATA, (v)); 2090 (void)RREG32(PCIE_PORT_DATA); 2091 } 2092 2093 /* 2094 * CP & Ring 2095 */ 2096 void r600_cp_stop(struct radeon_device *rdev) 2097 { 2098 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 2099 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); 2100 WREG32(SCRATCH_UMSK, 0); 2101 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 2102 } 2103 2104 int r600_init_microcode(struct radeon_device *rdev) 2105 { 2106 struct platform_device *pdev; 2107 const char *chip_name; 2108 const char *rlc_chip_name; 2109 size_t pfp_req_size, me_req_size, rlc_req_size; 2110 char fw_name[30]; 2111 int err; 2112 2113 DRM_DEBUG("\n"); 2114 2115 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0); 2116 err = IS_ERR(pdev); 2117 if (err) { 2118 printk(KERN_ERR "radeon_cp: Failed to register firmware\n"); 2119 return -EINVAL; 2120 } 2121 2122 switch (rdev->family) { 2123 case CHIP_R600: 2124 chip_name = "R600"; 2125 rlc_chip_name = "R600"; 2126 break; 2127 case CHIP_RV610: 2128 chip_name = "RV610"; 2129 rlc_chip_name = "R600"; 2130 break; 2131 case CHIP_RV630: 2132 chip_name = "RV630"; 2133 rlc_chip_name = "R600"; 2134 break; 2135 case CHIP_RV620: 2136 chip_name = "RV620"; 2137 rlc_chip_name = "R600"; 2138 break; 2139 case CHIP_RV635: 2140 chip_name = "RV635"; 2141 rlc_chip_name = "R600"; 2142 break; 2143 case CHIP_RV670: 2144 chip_name = "RV670"; 2145 rlc_chip_name = "R600"; 2146 break; 2147 case CHIP_RS780: 2148 case CHIP_RS880: 2149 chip_name = "RS780"; 2150 rlc_chip_name = "R600"; 2151 break; 2152 case CHIP_RV770: 2153 chip_name = "RV770"; 2154 rlc_chip_name = "R700"; 2155 break; 2156 case CHIP_RV730: 2157 case CHIP_RV740: 2158 chip_name = "RV730"; 2159 rlc_chip_name = "R700"; 2160 break; 2161 case CHIP_RV710: 2162 chip_name = "RV710"; 2163 rlc_chip_name = "R700"; 2164 break; 2165 case CHIP_CEDAR: 2166 chip_name = "CEDAR"; 2167 rlc_chip_name = "CEDAR"; 2168 break; 2169 case CHIP_REDWOOD: 2170 chip_name = "REDWOOD"; 2171 rlc_chip_name = "REDWOOD"; 2172 break; 2173 case CHIP_JUNIPER: 2174 chip_name = "JUNIPER"; 2175 rlc_chip_name = "JUNIPER"; 2176 break; 2177 case CHIP_CYPRESS: 2178 case CHIP_HEMLOCK: 2179 chip_name = "CYPRESS"; 2180 rlc_chip_name = "CYPRESS"; 2181 break; 2182 case CHIP_PALM: 2183 chip_name = "PALM"; 2184 rlc_chip_name = "SUMO"; 2185 break; 2186 case CHIP_SUMO: 2187 chip_name = "SUMO"; 2188 rlc_chip_name = "SUMO"; 2189 break; 2190 case CHIP_SUMO2: 2191 chip_name = "SUMO2"; 2192 rlc_chip_name = "SUMO"; 2193 break; 2194 default: BUG(); 2195 } 2196 2197 if (rdev->family >= CHIP_CEDAR) { 2198 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4; 2199 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4; 2200 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4; 2201 } else if (rdev->family >= CHIP_RV770) { 2202 pfp_req_size = R700_PFP_UCODE_SIZE * 4; 2203 me_req_size = R700_PM4_UCODE_SIZE * 4; 2204 rlc_req_size = R700_RLC_UCODE_SIZE * 4; 2205 } else { 2206 pfp_req_size = PFP_UCODE_SIZE * 4; 2207 me_req_size = PM4_UCODE_SIZE * 12; 2208 rlc_req_size = RLC_UCODE_SIZE * 4; 2209 } 2210 2211 DRM_INFO("Loading %s Microcode\n", chip_name); 2212 2213 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name); 2214 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev); 2215 if (err) 2216 goto out; 2217 if (rdev->pfp_fw->size != pfp_req_size) { 2218 printk(KERN_ERR 2219 "r600_cp: Bogus length %zu in firmware \"%s\"\n", 2220 rdev->pfp_fw->size, fw_name); 2221 err = -EINVAL; 2222 goto out; 2223 } 2224 2225 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name); 2226 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev); 2227 if (err) 2228 goto out; 2229 if (rdev->me_fw->size != me_req_size) { 2230 printk(KERN_ERR 2231 "r600_cp: Bogus length %zu in firmware \"%s\"\n", 2232 rdev->me_fw->size, fw_name); 2233 err = -EINVAL; 2234 } 2235 2236 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name); 2237 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev); 2238 if (err) 2239 goto out; 2240 if (rdev->rlc_fw->size != rlc_req_size) { 2241 printk(KERN_ERR 2242 "r600_rlc: Bogus length %zu in firmware \"%s\"\n", 2243 rdev->rlc_fw->size, fw_name); 2244 err = -EINVAL; 2245 } 2246 2247 out: 2248 platform_device_unregister(pdev); 2249 2250 if (err) { 2251 if (err != -EINVAL) 2252 printk(KERN_ERR 2253 "r600_cp: Failed to load firmware \"%s\"\n", 2254 fw_name); 2255 release_firmware(rdev->pfp_fw); 2256 rdev->pfp_fw = NULL; 2257 release_firmware(rdev->me_fw); 2258 rdev->me_fw = NULL; 2259 release_firmware(rdev->rlc_fw); 2260 rdev->rlc_fw = NULL; 2261 } 2262 return err; 2263 } 2264 2265 static int r600_cp_load_microcode(struct radeon_device *rdev) 2266 { 2267 const __be32 *fw_data; 2268 int i; 2269 2270 if (!rdev->me_fw || !rdev->pfp_fw) 2271 return -EINVAL; 2272 2273 r600_cp_stop(rdev); 2274 2275 WREG32(CP_RB_CNTL, 2276 #ifdef __BIG_ENDIAN 2277 BUF_SWAP_32BIT | 2278 #endif 2279 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); 2280 2281 /* Reset cp */ 2282 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); 2283 RREG32(GRBM_SOFT_RESET); 2284 mdelay(15); 2285 WREG32(GRBM_SOFT_RESET, 0); 2286 2287 WREG32(CP_ME_RAM_WADDR, 0); 2288 2289 fw_data = (const __be32 *)rdev->me_fw->data; 2290 WREG32(CP_ME_RAM_WADDR, 0); 2291 for (i = 0; i < PM4_UCODE_SIZE * 3; i++) 2292 WREG32(CP_ME_RAM_DATA, 2293 be32_to_cpup(fw_data++)); 2294 2295 fw_data = (const __be32 *)rdev->pfp_fw->data; 2296 WREG32(CP_PFP_UCODE_ADDR, 0); 2297 for (i = 0; i < PFP_UCODE_SIZE; i++) 2298 WREG32(CP_PFP_UCODE_DATA, 2299 be32_to_cpup(fw_data++)); 2300 2301 WREG32(CP_PFP_UCODE_ADDR, 0); 2302 WREG32(CP_ME_RAM_WADDR, 0); 2303 WREG32(CP_ME_RAM_RADDR, 0); 2304 return 0; 2305 } 2306 2307 int r600_cp_start(struct radeon_device *rdev) 2308 { 2309 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2310 int r; 2311 uint32_t cp_me; 2312 2313 r = radeon_ring_lock(rdev, ring, 7); 2314 if (r) { 2315 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 2316 return r; 2317 } 2318 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); 2319 radeon_ring_write(ring, 0x1); 2320 if (rdev->family >= CHIP_RV770) { 2321 radeon_ring_write(ring, 0x0); 2322 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1); 2323 } else { 2324 radeon_ring_write(ring, 0x3); 2325 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1); 2326 } 2327 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); 2328 radeon_ring_write(ring, 0); 2329 radeon_ring_write(ring, 0); 2330 radeon_ring_unlock_commit(rdev, ring); 2331 2332 cp_me = 0xff; 2333 WREG32(R_0086D8_CP_ME_CNTL, cp_me); 2334 return 0; 2335 } 2336 2337 int r600_cp_resume(struct radeon_device *rdev) 2338 { 2339 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2340 u32 tmp; 2341 u32 rb_bufsz; 2342 int r; 2343 2344 /* Reset cp */ 2345 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); 2346 RREG32(GRBM_SOFT_RESET); 2347 mdelay(15); 2348 WREG32(GRBM_SOFT_RESET, 0); 2349 2350 /* Set ring buffer size */ 2351 rb_bufsz = drm_order(ring->ring_size / 8); 2352 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2353 #ifdef __BIG_ENDIAN 2354 tmp |= BUF_SWAP_32BIT; 2355 #endif 2356 WREG32(CP_RB_CNTL, tmp); 2357 WREG32(CP_SEM_WAIT_TIMER, 0x0); 2358 2359 /* Set the write pointer delay */ 2360 WREG32(CP_RB_WPTR_DELAY, 0); 2361 2362 /* Initialize the ring buffer's read and write pointers */ 2363 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); 2364 WREG32(CP_RB_RPTR_WR, 0); 2365 ring->wptr = 0; 2366 WREG32(CP_RB_WPTR, ring->wptr); 2367 2368 /* set the wb address whether it's enabled or not */ 2369 WREG32(CP_RB_RPTR_ADDR, 2370 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC)); 2371 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); 2372 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); 2373 2374 if (rdev->wb.enabled) 2375 WREG32(SCRATCH_UMSK, 0xff); 2376 else { 2377 tmp |= RB_NO_UPDATE; 2378 WREG32(SCRATCH_UMSK, 0); 2379 } 2380 2381 mdelay(1); 2382 WREG32(CP_RB_CNTL, tmp); 2383 2384 WREG32(CP_RB_BASE, ring->gpu_addr >> 8); 2385 WREG32(CP_DEBUG, (1 << 27) | (1 << 28)); 2386 2387 ring->rptr = RREG32(CP_RB_RPTR); 2388 2389 r600_cp_start(rdev); 2390 ring->ready = true; 2391 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring); 2392 if (r) { 2393 ring->ready = false; 2394 return r; 2395 } 2396 return 0; 2397 } 2398 2399 void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size) 2400 { 2401 u32 rb_bufsz; 2402 int r; 2403 2404 /* Align ring size */ 2405 rb_bufsz = drm_order(ring_size / 8); 2406 ring_size = (1 << (rb_bufsz + 1)) * 4; 2407 ring->ring_size = ring_size; 2408 ring->align_mask = 16 - 1; 2409 2410 if (radeon_ring_supports_scratch_reg(rdev, ring)) { 2411 r = radeon_scratch_get(rdev, &ring->rptr_save_reg); 2412 if (r) { 2413 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r); 2414 ring->rptr_save_reg = 0; 2415 } 2416 } 2417 } 2418 2419 void r600_cp_fini(struct radeon_device *rdev) 2420 { 2421 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2422 r600_cp_stop(rdev); 2423 radeon_ring_fini(rdev, ring); 2424 radeon_scratch_free(rdev, ring->rptr_save_reg); 2425 } 2426 2427 /* 2428 * DMA 2429 * Starting with R600, the GPU has an asynchronous 2430 * DMA engine. The programming model is very similar 2431 * to the 3D engine (ring buffer, IBs, etc.), but the 2432 * DMA controller has it's own packet format that is 2433 * different form the PM4 format used by the 3D engine. 2434 * It supports copying data, writing embedded data, 2435 * solid fills, and a number of other things. It also 2436 * has support for tiling/detiling of buffers. 2437 */ 2438 /** 2439 * r600_dma_stop - stop the async dma engine 2440 * 2441 * @rdev: radeon_device pointer 2442 * 2443 * Stop the async dma engine (r6xx-evergreen). 2444 */ 2445 void r600_dma_stop(struct radeon_device *rdev) 2446 { 2447 u32 rb_cntl = RREG32(DMA_RB_CNTL); 2448 2449 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 2450 2451 rb_cntl &= ~DMA_RB_ENABLE; 2452 WREG32(DMA_RB_CNTL, rb_cntl); 2453 2454 rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false; 2455 } 2456 2457 /** 2458 * r600_dma_resume - setup and start the async dma engine 2459 * 2460 * @rdev: radeon_device pointer 2461 * 2462 * Set up the DMA ring buffer and enable it. (r6xx-evergreen). 2463 * Returns 0 for success, error for failure. 2464 */ 2465 int r600_dma_resume(struct radeon_device *rdev) 2466 { 2467 struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; 2468 u32 rb_cntl, dma_cntl, ib_cntl; 2469 u32 rb_bufsz; 2470 int r; 2471 2472 /* Reset dma */ 2473 if (rdev->family >= CHIP_RV770) 2474 WREG32(SRBM_SOFT_RESET, RV770_SOFT_RESET_DMA); 2475 else 2476 WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA); 2477 RREG32(SRBM_SOFT_RESET); 2478 udelay(50); 2479 WREG32(SRBM_SOFT_RESET, 0); 2480 2481 WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL, 0); 2482 WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL, 0); 2483 2484 /* Set ring buffer size in dwords */ 2485 rb_bufsz = drm_order(ring->ring_size / 4); 2486 rb_cntl = rb_bufsz << 1; 2487 #ifdef __BIG_ENDIAN 2488 rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE; 2489 #endif 2490 WREG32(DMA_RB_CNTL, rb_cntl); 2491 2492 /* Initialize the ring buffer's read and write pointers */ 2493 WREG32(DMA_RB_RPTR, 0); 2494 WREG32(DMA_RB_WPTR, 0); 2495 2496 /* set the wb address whether it's enabled or not */ 2497 WREG32(DMA_RB_RPTR_ADDR_HI, 2498 upper_32_bits(rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFF); 2499 WREG32(DMA_RB_RPTR_ADDR_LO, 2500 ((rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFFFFFFFC)); 2501 2502 if (rdev->wb.enabled) 2503 rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE; 2504 2505 WREG32(DMA_RB_BASE, ring->gpu_addr >> 8); 2506 2507 /* enable DMA IBs */ 2508 ib_cntl = DMA_IB_ENABLE; 2509 #ifdef __BIG_ENDIAN 2510 ib_cntl |= DMA_IB_SWAP_ENABLE; 2511 #endif 2512 WREG32(DMA_IB_CNTL, ib_cntl); 2513 2514 dma_cntl = RREG32(DMA_CNTL); 2515 dma_cntl &= ~CTXEMPTY_INT_ENABLE; 2516 WREG32(DMA_CNTL, dma_cntl); 2517 2518 if (rdev->family >= CHIP_RV770) 2519 WREG32(DMA_MODE, 1); 2520 2521 ring->wptr = 0; 2522 WREG32(DMA_RB_WPTR, ring->wptr << 2); 2523 2524 ring->rptr = RREG32(DMA_RB_RPTR) >> 2; 2525 2526 WREG32(DMA_RB_CNTL, rb_cntl | DMA_RB_ENABLE); 2527 2528 ring->ready = true; 2529 2530 r = radeon_ring_test(rdev, R600_RING_TYPE_DMA_INDEX, ring); 2531 if (r) { 2532 ring->ready = false; 2533 return r; 2534 } 2535 2536 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); 2537 2538 return 0; 2539 } 2540 2541 /** 2542 * r600_dma_fini - tear down the async dma engine 2543 * 2544 * @rdev: radeon_device pointer 2545 * 2546 * Stop the async dma engine and free the ring (r6xx-evergreen). 2547 */ 2548 void r600_dma_fini(struct radeon_device *rdev) 2549 { 2550 r600_dma_stop(rdev); 2551 radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]); 2552 } 2553 2554 /* 2555 * GPU scratch registers helpers function. 2556 */ 2557 void r600_scratch_init(struct radeon_device *rdev) 2558 { 2559 int i; 2560 2561 rdev->scratch.num_reg = 7; 2562 rdev->scratch.reg_base = SCRATCH_REG0; 2563 for (i = 0; i < rdev->scratch.num_reg; i++) { 2564 rdev->scratch.free[i] = true; 2565 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); 2566 } 2567 } 2568 2569 int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) 2570 { 2571 uint32_t scratch; 2572 uint32_t tmp = 0; 2573 unsigned i; 2574 int r; 2575 2576 r = radeon_scratch_get(rdev, &scratch); 2577 if (r) { 2578 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); 2579 return r; 2580 } 2581 WREG32(scratch, 0xCAFEDEAD); 2582 r = radeon_ring_lock(rdev, ring, 3); 2583 if (r) { 2584 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring->idx, r); 2585 radeon_scratch_free(rdev, scratch); 2586 return r; 2587 } 2588 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2589 radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); 2590 radeon_ring_write(ring, 0xDEADBEEF); 2591 radeon_ring_unlock_commit(rdev, ring); 2592 for (i = 0; i < rdev->usec_timeout; i++) { 2593 tmp = RREG32(scratch); 2594 if (tmp == 0xDEADBEEF) 2595 break; 2596 DRM_UDELAY(1); 2597 } 2598 if (i < rdev->usec_timeout) { 2599 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); 2600 } else { 2601 DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n", 2602 ring->idx, scratch, tmp); 2603 r = -EINVAL; 2604 } 2605 radeon_scratch_free(rdev, scratch); 2606 return r; 2607 } 2608 2609 /** 2610 * r600_dma_ring_test - simple async dma engine test 2611 * 2612 * @rdev: radeon_device pointer 2613 * @ring: radeon_ring structure holding ring information 2614 * 2615 * Test the DMA engine by writing using it to write an 2616 * value to memory. (r6xx-SI). 2617 * Returns 0 for success, error for failure. 2618 */ 2619 int r600_dma_ring_test(struct radeon_device *rdev, 2620 struct radeon_ring *ring) 2621 { 2622 unsigned i; 2623 int r; 2624 void __iomem *ptr = (void *)rdev->vram_scratch.ptr; 2625 u32 tmp; 2626 2627 if (!ptr) { 2628 DRM_ERROR("invalid vram scratch pointer\n"); 2629 return -EINVAL; 2630 } 2631 2632 tmp = 0xCAFEDEAD; 2633 writel(tmp, ptr); 2634 2635 r = radeon_ring_lock(rdev, ring, 4); 2636 if (r) { 2637 DRM_ERROR("radeon: dma failed to lock ring %d (%d).\n", ring->idx, r); 2638 return r; 2639 } 2640 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1)); 2641 radeon_ring_write(ring, rdev->vram_scratch.gpu_addr & 0xfffffffc); 2642 radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff); 2643 radeon_ring_write(ring, 0xDEADBEEF); 2644 radeon_ring_unlock_commit(rdev, ring); 2645 2646 for (i = 0; i < rdev->usec_timeout; i++) { 2647 tmp = readl(ptr); 2648 if (tmp == 0xDEADBEEF) 2649 break; 2650 DRM_UDELAY(1); 2651 } 2652 2653 if (i < rdev->usec_timeout) { 2654 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); 2655 } else { 2656 DRM_ERROR("radeon: ring %d test failed (0x%08X)\n", 2657 ring->idx, tmp); 2658 r = -EINVAL; 2659 } 2660 return r; 2661 } 2662 2663 /* 2664 * CP fences/semaphores 2665 */ 2666 2667 void r600_fence_ring_emit(struct radeon_device *rdev, 2668 struct radeon_fence *fence) 2669 { 2670 struct radeon_ring *ring = &rdev->ring[fence->ring]; 2671 2672 if (rdev->wb.use_event) { 2673 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; 2674 /* flush read cache over gart */ 2675 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 2676 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | 2677 PACKET3_VC_ACTION_ENA | 2678 PACKET3_SH_ACTION_ENA); 2679 radeon_ring_write(ring, 0xFFFFFFFF); 2680 radeon_ring_write(ring, 0); 2681 radeon_ring_write(ring, 10); /* poll interval */ 2682 /* EVENT_WRITE_EOP - flush caches, send int */ 2683 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 2684 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5)); 2685 radeon_ring_write(ring, addr & 0xffffffff); 2686 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); 2687 radeon_ring_write(ring, fence->seq); 2688 radeon_ring_write(ring, 0); 2689 } else { 2690 /* flush read cache over gart */ 2691 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 2692 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | 2693 PACKET3_VC_ACTION_ENA | 2694 PACKET3_SH_ACTION_ENA); 2695 radeon_ring_write(ring, 0xFFFFFFFF); 2696 radeon_ring_write(ring, 0); 2697 radeon_ring_write(ring, 10); /* poll interval */ 2698 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); 2699 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0)); 2700 /* wait for 3D idle clean */ 2701 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2702 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 2703 radeon_ring_write(ring, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit); 2704 /* Emit fence sequence & fire IRQ */ 2705 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2706 radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); 2707 radeon_ring_write(ring, fence->seq); 2708 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */ 2709 radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0)); 2710 radeon_ring_write(ring, RB_INT_STAT); 2711 } 2712 } 2713 2714 void r600_semaphore_ring_emit(struct radeon_device *rdev, 2715 struct radeon_ring *ring, 2716 struct radeon_semaphore *semaphore, 2717 bool emit_wait) 2718 { 2719 uint64_t addr = semaphore->gpu_addr; 2720 unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL; 2721 2722 if (rdev->family < CHIP_CAYMAN) 2723 sel |= PACKET3_SEM_WAIT_ON_SIGNAL; 2724 2725 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); 2726 radeon_ring_write(ring, addr & 0xffffffff); 2727 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel); 2728 } 2729 2730 /* 2731 * DMA fences/semaphores 2732 */ 2733 2734 /** 2735 * r600_dma_fence_ring_emit - emit a fence on the DMA ring 2736 * 2737 * @rdev: radeon_device pointer 2738 * @fence: radeon fence object 2739 * 2740 * Add a DMA fence packet to the ring to write 2741 * the fence seq number and DMA trap packet to generate 2742 * an interrupt if needed (r6xx-r7xx). 2743 */ 2744 void r600_dma_fence_ring_emit(struct radeon_device *rdev, 2745 struct radeon_fence *fence) 2746 { 2747 struct radeon_ring *ring = &rdev->ring[fence->ring]; 2748 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; 2749 2750 /* write the fence */ 2751 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0)); 2752 radeon_ring_write(ring, addr & 0xfffffffc); 2753 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff)); 2754 radeon_ring_write(ring, lower_32_bits(fence->seq)); 2755 /* generate an interrupt */ 2756 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0, 0)); 2757 } 2758 2759 /** 2760 * r600_dma_semaphore_ring_emit - emit a semaphore on the dma ring 2761 * 2762 * @rdev: radeon_device pointer 2763 * @ring: radeon_ring structure holding ring information 2764 * @semaphore: radeon semaphore object 2765 * @emit_wait: wait or signal semaphore 2766 * 2767 * Add a DMA semaphore packet to the ring wait on or signal 2768 * other rings (r6xx-SI). 2769 */ 2770 void r600_dma_semaphore_ring_emit(struct radeon_device *rdev, 2771 struct radeon_ring *ring, 2772 struct radeon_semaphore *semaphore, 2773 bool emit_wait) 2774 { 2775 u64 addr = semaphore->gpu_addr; 2776 u32 s = emit_wait ? 0 : 1; 2777 2778 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SEMAPHORE, 0, s, 0)); 2779 radeon_ring_write(ring, addr & 0xfffffffc); 2780 radeon_ring_write(ring, upper_32_bits(addr) & 0xff); 2781 } 2782 2783 int r600_copy_blit(struct radeon_device *rdev, 2784 uint64_t src_offset, 2785 uint64_t dst_offset, 2786 unsigned num_gpu_pages, 2787 struct radeon_fence **fence) 2788 { 2789 struct radeon_semaphore *sem = NULL; 2790 struct radeon_sa_bo *vb = NULL; 2791 int r; 2792 2793 r = r600_blit_prepare_copy(rdev, num_gpu_pages, fence, &vb, &sem); 2794 if (r) { 2795 return r; 2796 } 2797 r600_kms_blit_copy(rdev, src_offset, dst_offset, num_gpu_pages, vb); 2798 r600_blit_done_copy(rdev, fence, vb, sem); 2799 return 0; 2800 } 2801 2802 /** 2803 * r600_copy_dma - copy pages using the DMA engine 2804 * 2805 * @rdev: radeon_device pointer 2806 * @src_offset: src GPU address 2807 * @dst_offset: dst GPU address 2808 * @num_gpu_pages: number of GPU pages to xfer 2809 * @fence: radeon fence object 2810 * 2811 * Copy GPU paging using the DMA engine (r6xx). 2812 * Used by the radeon ttm implementation to move pages if 2813 * registered as the asic copy callback. 2814 */ 2815 int r600_copy_dma(struct radeon_device *rdev, 2816 uint64_t src_offset, uint64_t dst_offset, 2817 unsigned num_gpu_pages, 2818 struct radeon_fence **fence) 2819 { 2820 struct radeon_semaphore *sem = NULL; 2821 int ring_index = rdev->asic->copy.dma_ring_index; 2822 struct radeon_ring *ring = &rdev->ring[ring_index]; 2823 u32 size_in_dw, cur_size_in_dw; 2824 int i, num_loops; 2825 int r = 0; 2826 2827 r = radeon_semaphore_create(rdev, &sem); 2828 if (r) { 2829 DRM_ERROR("radeon: moving bo (%d).\n", r); 2830 return r; 2831 } 2832 2833 size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4; 2834 num_loops = DIV_ROUND_UP(size_in_dw, 0xFFFE); 2835 r = radeon_ring_lock(rdev, ring, num_loops * 4 + 8); 2836 if (r) { 2837 DRM_ERROR("radeon: moving bo (%d).\n", r); 2838 radeon_semaphore_free(rdev, &sem, NULL); 2839 return r; 2840 } 2841 2842 if (radeon_fence_need_sync(*fence, ring->idx)) { 2843 radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring, 2844 ring->idx); 2845 radeon_fence_note_sync(*fence, ring->idx); 2846 } else { 2847 radeon_semaphore_free(rdev, &sem, NULL); 2848 } 2849 2850 for (i = 0; i < num_loops; i++) { 2851 cur_size_in_dw = size_in_dw; 2852 if (cur_size_in_dw > 0xFFFE) 2853 cur_size_in_dw = 0xFFFE; 2854 size_in_dw -= cur_size_in_dw; 2855 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw)); 2856 radeon_ring_write(ring, dst_offset & 0xfffffffc); 2857 radeon_ring_write(ring, src_offset & 0xfffffffc); 2858 radeon_ring_write(ring, (((upper_32_bits(dst_offset) & 0xff) << 16) | 2859 (upper_32_bits(src_offset) & 0xff))); 2860 src_offset += cur_size_in_dw * 4; 2861 dst_offset += cur_size_in_dw * 4; 2862 } 2863 2864 r = radeon_fence_emit(rdev, fence, ring->idx); 2865 if (r) { 2866 radeon_ring_unlock_undo(rdev, ring); 2867 return r; 2868 } 2869 2870 radeon_ring_unlock_commit(rdev, ring); 2871 radeon_semaphore_free(rdev, &sem, *fence); 2872 2873 return r; 2874 } 2875 2876 int r600_set_surface_reg(struct radeon_device *rdev, int reg, 2877 uint32_t tiling_flags, uint32_t pitch, 2878 uint32_t offset, uint32_t obj_size) 2879 { 2880 /* FIXME: implement */ 2881 return 0; 2882 } 2883 2884 void r600_clear_surface_reg(struct radeon_device *rdev, int reg) 2885 { 2886 /* FIXME: implement */ 2887 } 2888 2889 static int r600_startup(struct radeon_device *rdev) 2890 { 2891 struct radeon_ring *ring; 2892 int r; 2893 2894 /* enable pcie gen2 link */ 2895 r600_pcie_gen2_enable(rdev); 2896 2897 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { 2898 r = r600_init_microcode(rdev); 2899 if (r) { 2900 DRM_ERROR("Failed to load firmware!\n"); 2901 return r; 2902 } 2903 } 2904 2905 r = r600_vram_scratch_init(rdev); 2906 if (r) 2907 return r; 2908 2909 r600_mc_program(rdev); 2910 if (rdev->flags & RADEON_IS_AGP) { 2911 r600_agp_enable(rdev); 2912 } else { 2913 r = r600_pcie_gart_enable(rdev); 2914 if (r) 2915 return r; 2916 } 2917 r600_gpu_init(rdev); 2918 r = r600_blit_init(rdev); 2919 if (r) { 2920 r600_blit_fini(rdev); 2921 rdev->asic->copy.copy = NULL; 2922 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); 2923 } 2924 2925 /* allocate wb buffer */ 2926 r = radeon_wb_init(rdev); 2927 if (r) 2928 return r; 2929 2930 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 2931 if (r) { 2932 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 2933 return r; 2934 } 2935 2936 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX); 2937 if (r) { 2938 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); 2939 return r; 2940 } 2941 2942 /* Enable IRQ */ 2943 r = r600_irq_init(rdev); 2944 if (r) { 2945 DRM_ERROR("radeon: IH init failed (%d).\n", r); 2946 radeon_irq_kms_fini(rdev); 2947 return r; 2948 } 2949 r600_irq_set(rdev); 2950 2951 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2952 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, 2953 R600_CP_RB_RPTR, R600_CP_RB_WPTR, 2954 0, 0xfffff, RADEON_CP_PACKET2); 2955 if (r) 2956 return r; 2957 2958 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; 2959 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, 2960 DMA_RB_RPTR, DMA_RB_WPTR, 2961 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); 2962 if (r) 2963 return r; 2964 2965 r = r600_cp_load_microcode(rdev); 2966 if (r) 2967 return r; 2968 r = r600_cp_resume(rdev); 2969 if (r) 2970 return r; 2971 2972 r = r600_dma_resume(rdev); 2973 if (r) 2974 return r; 2975 2976 r = radeon_ib_pool_init(rdev); 2977 if (r) { 2978 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 2979 return r; 2980 } 2981 2982 r = r600_audio_init(rdev); 2983 if (r) { 2984 DRM_ERROR("radeon: audio init failed\n"); 2985 return r; 2986 } 2987 2988 return 0; 2989 } 2990 2991 void r600_vga_set_state(struct radeon_device *rdev, bool state) 2992 { 2993 uint32_t temp; 2994 2995 temp = RREG32(CONFIG_CNTL); 2996 if (state == false) { 2997 temp &= ~(1<<0); 2998 temp |= (1<<1); 2999 } else { 3000 temp &= ~(1<<1); 3001 } 3002 WREG32(CONFIG_CNTL, temp); 3003 } 3004 3005 int r600_resume(struct radeon_device *rdev) 3006 { 3007 int r; 3008 3009 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw, 3010 * posting will perform necessary task to bring back GPU into good 3011 * shape. 3012 */ 3013 /* post card */ 3014 atom_asic_init(rdev->mode_info.atom_context); 3015 3016 rdev->accel_working = true; 3017 r = r600_startup(rdev); 3018 if (r) { 3019 DRM_ERROR("r600 startup failed on resume\n"); 3020 rdev->accel_working = false; 3021 return r; 3022 } 3023 3024 return r; 3025 } 3026 3027 int r600_suspend(struct radeon_device *rdev) 3028 { 3029 r600_audio_fini(rdev); 3030 r600_cp_stop(rdev); 3031 r600_dma_stop(rdev); 3032 r600_irq_suspend(rdev); 3033 radeon_wb_disable(rdev); 3034 r600_pcie_gart_disable(rdev); 3035 3036 return 0; 3037 } 3038 3039 /* Plan is to move initialization in that function and use 3040 * helper function so that radeon_device_init pretty much 3041 * do nothing more than calling asic specific function. This 3042 * should also allow to remove a bunch of callback function 3043 * like vram_info. 3044 */ 3045 int r600_init(struct radeon_device *rdev) 3046 { 3047 int r; 3048 3049 if (r600_debugfs_mc_info_init(rdev)) { 3050 DRM_ERROR("Failed to register debugfs file for mc !\n"); 3051 } 3052 /* Read BIOS */ 3053 if (!radeon_get_bios(rdev)) { 3054 if (ASIC_IS_AVIVO(rdev)) 3055 return -EINVAL; 3056 } 3057 /* Must be an ATOMBIOS */ 3058 if (!rdev->is_atom_bios) { 3059 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n"); 3060 return -EINVAL; 3061 } 3062 r = radeon_atombios_init(rdev); 3063 if (r) 3064 return r; 3065 /* Post card if necessary */ 3066 if (!radeon_card_posted(rdev)) { 3067 if (!rdev->bios) { 3068 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); 3069 return -EINVAL; 3070 } 3071 DRM_INFO("GPU not posted. posting now...\n"); 3072 atom_asic_init(rdev->mode_info.atom_context); 3073 } 3074 /* Initialize scratch registers */ 3075 r600_scratch_init(rdev); 3076 /* Initialize surface registers */ 3077 radeon_surface_init(rdev); 3078 /* Initialize clocks */ 3079 radeon_get_clock_info(rdev->ddev); 3080 /* Fence driver */ 3081 r = radeon_fence_driver_init(rdev); 3082 if (r) 3083 return r; 3084 if (rdev->flags & RADEON_IS_AGP) { 3085 r = radeon_agp_init(rdev); 3086 if (r) 3087 radeon_agp_disable(rdev); 3088 } 3089 r = r600_mc_init(rdev); 3090 if (r) 3091 return r; 3092 /* Memory manager */ 3093 r = radeon_bo_init(rdev); 3094 if (r) 3095 return r; 3096 3097 r = radeon_irq_kms_init(rdev); 3098 if (r) 3099 return r; 3100 3101 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL; 3102 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024); 3103 3104 rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL; 3105 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024); 3106 3107 rdev->ih.ring_obj = NULL; 3108 r600_ih_ring_init(rdev, 64 * 1024); 3109 3110 r = r600_pcie_gart_init(rdev); 3111 if (r) 3112 return r; 3113 3114 rdev->accel_working = true; 3115 r = r600_startup(rdev); 3116 if (r) { 3117 dev_err(rdev->dev, "disabling GPU acceleration\n"); 3118 r600_cp_fini(rdev); 3119 r600_dma_fini(rdev); 3120 r600_irq_fini(rdev); 3121 radeon_wb_fini(rdev); 3122 radeon_ib_pool_fini(rdev); 3123 radeon_irq_kms_fini(rdev); 3124 r600_pcie_gart_fini(rdev); 3125 rdev->accel_working = false; 3126 } 3127 3128 return 0; 3129 } 3130 3131 void r600_fini(struct radeon_device *rdev) 3132 { 3133 r600_audio_fini(rdev); 3134 r600_blit_fini(rdev); 3135 r600_cp_fini(rdev); 3136 r600_dma_fini(rdev); 3137 r600_irq_fini(rdev); 3138 radeon_wb_fini(rdev); 3139 radeon_ib_pool_fini(rdev); 3140 radeon_irq_kms_fini(rdev); 3141 r600_pcie_gart_fini(rdev); 3142 r600_vram_scratch_fini(rdev); 3143 radeon_agp_fini(rdev); 3144 radeon_gem_fini(rdev); 3145 radeon_fence_driver_fini(rdev); 3146 radeon_bo_fini(rdev); 3147 radeon_atombios_fini(rdev); 3148 kfree(rdev->bios); 3149 rdev->bios = NULL; 3150 } 3151 3152 3153 /* 3154 * CS stuff 3155 */ 3156 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 3157 { 3158 struct radeon_ring *ring = &rdev->ring[ib->ring]; 3159 u32 next_rptr; 3160 3161 if (ring->rptr_save_reg) { 3162 next_rptr = ring->wptr + 3 + 4; 3163 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 3164 radeon_ring_write(ring, ((ring->rptr_save_reg - 3165 PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); 3166 radeon_ring_write(ring, next_rptr); 3167 } else if (rdev->wb.enabled) { 3168 next_rptr = ring->wptr + 5 + 4; 3169 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3)); 3170 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); 3171 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18)); 3172 radeon_ring_write(ring, next_rptr); 3173 radeon_ring_write(ring, 0); 3174 } 3175 3176 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 3177 radeon_ring_write(ring, 3178 #ifdef __BIG_ENDIAN 3179 (2 << 0) | 3180 #endif 3181 (ib->gpu_addr & 0xFFFFFFFC)); 3182 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF); 3183 radeon_ring_write(ring, ib->length_dw); 3184 } 3185 3186 int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) 3187 { 3188 struct radeon_ib ib; 3189 uint32_t scratch; 3190 uint32_t tmp = 0; 3191 unsigned i; 3192 int r; 3193 3194 r = radeon_scratch_get(rdev, &scratch); 3195 if (r) { 3196 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); 3197 return r; 3198 } 3199 WREG32(scratch, 0xCAFEDEAD); 3200 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256); 3201 if (r) { 3202 DRM_ERROR("radeon: failed to get ib (%d).\n", r); 3203 goto free_scratch; 3204 } 3205 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1); 3206 ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 3207 ib.ptr[2] = 0xDEADBEEF; 3208 ib.length_dw = 3; 3209 r = radeon_ib_schedule(rdev, &ib, NULL); 3210 if (r) { 3211 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); 3212 goto free_ib; 3213 } 3214 r = radeon_fence_wait(ib.fence, false); 3215 if (r) { 3216 DRM_ERROR("radeon: fence wait failed (%d).\n", r); 3217 goto free_ib; 3218 } 3219 for (i = 0; i < rdev->usec_timeout; i++) { 3220 tmp = RREG32(scratch); 3221 if (tmp == 0xDEADBEEF) 3222 break; 3223 DRM_UDELAY(1); 3224 } 3225 if (i < rdev->usec_timeout) { 3226 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i); 3227 } else { 3228 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n", 3229 scratch, tmp); 3230 r = -EINVAL; 3231 } 3232 free_ib: 3233 radeon_ib_free(rdev, &ib); 3234 free_scratch: 3235 radeon_scratch_free(rdev, scratch); 3236 return r; 3237 } 3238 3239 /** 3240 * r600_dma_ib_test - test an IB on the DMA engine 3241 * 3242 * @rdev: radeon_device pointer 3243 * @ring: radeon_ring structure holding ring information 3244 * 3245 * Test a simple IB in the DMA ring (r6xx-SI). 3246 * Returns 0 on success, error on failure. 3247 */ 3248 int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) 3249 { 3250 struct radeon_ib ib; 3251 unsigned i; 3252 int r; 3253 void __iomem *ptr = (void *)rdev->vram_scratch.ptr; 3254 u32 tmp = 0; 3255 3256 if (!ptr) { 3257 DRM_ERROR("invalid vram scratch pointer\n"); 3258 return -EINVAL; 3259 } 3260 3261 tmp = 0xCAFEDEAD; 3262 writel(tmp, ptr); 3263 3264 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256); 3265 if (r) { 3266 DRM_ERROR("radeon: failed to get ib (%d).\n", r); 3267 return r; 3268 } 3269 3270 ib.ptr[0] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1); 3271 ib.ptr[1] = rdev->vram_scratch.gpu_addr & 0xfffffffc; 3272 ib.ptr[2] = upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff; 3273 ib.ptr[3] = 0xDEADBEEF; 3274 ib.length_dw = 4; 3275 3276 r = radeon_ib_schedule(rdev, &ib, NULL); 3277 if (r) { 3278 radeon_ib_free(rdev, &ib); 3279 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); 3280 return r; 3281 } 3282 r = radeon_fence_wait(ib.fence, false); 3283 if (r) { 3284 DRM_ERROR("radeon: fence wait failed (%d).\n", r); 3285 return r; 3286 } 3287 for (i = 0; i < rdev->usec_timeout; i++) { 3288 tmp = readl(ptr); 3289 if (tmp == 0xDEADBEEF) 3290 break; 3291 DRM_UDELAY(1); 3292 } 3293 if (i < rdev->usec_timeout) { 3294 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i); 3295 } else { 3296 DRM_ERROR("radeon: ib test failed (0x%08X)\n", tmp); 3297 r = -EINVAL; 3298 } 3299 radeon_ib_free(rdev, &ib); 3300 return r; 3301 } 3302 3303 /** 3304 * r600_dma_ring_ib_execute - Schedule an IB on the DMA engine 3305 * 3306 * @rdev: radeon_device pointer 3307 * @ib: IB object to schedule 3308 * 3309 * Schedule an IB in the DMA ring (r6xx-r7xx). 3310 */ 3311 void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 3312 { 3313 struct radeon_ring *ring = &rdev->ring[ib->ring]; 3314 3315 if (rdev->wb.enabled) { 3316 u32 next_rptr = ring->wptr + 4; 3317 while ((next_rptr & 7) != 5) 3318 next_rptr++; 3319 next_rptr += 3; 3320 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1)); 3321 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); 3322 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff); 3323 radeon_ring_write(ring, next_rptr); 3324 } 3325 3326 /* The indirect buffer packet must end on an 8 DW boundary in the DMA ring. 3327 * Pad as necessary with NOPs. 3328 */ 3329 while ((ring->wptr & 7) != 5) 3330 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); 3331 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER, 0, 0, 0)); 3332 radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0)); 3333 radeon_ring_write(ring, (ib->length_dw << 16) | (upper_32_bits(ib->gpu_addr) & 0xFF)); 3334 3335 } 3336 3337 /* 3338 * Interrupts 3339 * 3340 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty 3341 * the same as the CP ring buffer, but in reverse. Rather than the CPU 3342 * writing to the ring and the GPU consuming, the GPU writes to the ring 3343 * and host consumes. As the host irq handler processes interrupts, it 3344 * increments the rptr. When the rptr catches up with the wptr, all the 3345 * current interrupts have been processed. 3346 */ 3347 3348 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size) 3349 { 3350 u32 rb_bufsz; 3351 3352 /* Align ring size */ 3353 rb_bufsz = drm_order(ring_size / 4); 3354 ring_size = (1 << rb_bufsz) * 4; 3355 rdev->ih.ring_size = ring_size; 3356 rdev->ih.ptr_mask = rdev->ih.ring_size - 1; 3357 rdev->ih.rptr = 0; 3358 } 3359 3360 int r600_ih_ring_alloc(struct radeon_device *rdev) 3361 { 3362 int r; 3363 3364 /* Allocate ring buffer */ 3365 if (rdev->ih.ring_obj == NULL) { 3366 r = radeon_bo_create(rdev, rdev->ih.ring_size, 3367 PAGE_SIZE, true, 3368 RADEON_GEM_DOMAIN_GTT, 3369 NULL, &rdev->ih.ring_obj); 3370 if (r) { 3371 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r); 3372 return r; 3373 } 3374 r = radeon_bo_reserve(rdev->ih.ring_obj, false); 3375 if (unlikely(r != 0)) 3376 return r; 3377 r = radeon_bo_pin(rdev->ih.ring_obj, 3378 RADEON_GEM_DOMAIN_GTT, 3379 &rdev->ih.gpu_addr); 3380 if (r) { 3381 radeon_bo_unreserve(rdev->ih.ring_obj); 3382 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r); 3383 return r; 3384 } 3385 r = radeon_bo_kmap(rdev->ih.ring_obj, 3386 (void **)&rdev->ih.ring); 3387 radeon_bo_unreserve(rdev->ih.ring_obj); 3388 if (r) { 3389 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r); 3390 return r; 3391 } 3392 } 3393 return 0; 3394 } 3395 3396 void r600_ih_ring_fini(struct radeon_device *rdev) 3397 { 3398 int r; 3399 if (rdev->ih.ring_obj) { 3400 r = radeon_bo_reserve(rdev->ih.ring_obj, false); 3401 if (likely(r == 0)) { 3402 radeon_bo_kunmap(rdev->ih.ring_obj); 3403 radeon_bo_unpin(rdev->ih.ring_obj); 3404 radeon_bo_unreserve(rdev->ih.ring_obj); 3405 } 3406 radeon_bo_unref(&rdev->ih.ring_obj); 3407 rdev->ih.ring = NULL; 3408 rdev->ih.ring_obj = NULL; 3409 } 3410 } 3411 3412 void r600_rlc_stop(struct radeon_device *rdev) 3413 { 3414 3415 if ((rdev->family >= CHIP_RV770) && 3416 (rdev->family <= CHIP_RV740)) { 3417 /* r7xx asics need to soft reset RLC before halting */ 3418 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC); 3419 RREG32(SRBM_SOFT_RESET); 3420 mdelay(15); 3421 WREG32(SRBM_SOFT_RESET, 0); 3422 RREG32(SRBM_SOFT_RESET); 3423 } 3424 3425 WREG32(RLC_CNTL, 0); 3426 } 3427 3428 static void r600_rlc_start(struct radeon_device *rdev) 3429 { 3430 WREG32(RLC_CNTL, RLC_ENABLE); 3431 } 3432 3433 static int r600_rlc_init(struct radeon_device *rdev) 3434 { 3435 u32 i; 3436 const __be32 *fw_data; 3437 3438 if (!rdev->rlc_fw) 3439 return -EINVAL; 3440 3441 r600_rlc_stop(rdev); 3442 3443 WREG32(RLC_HB_CNTL, 0); 3444 3445 if (rdev->family == CHIP_ARUBA) { 3446 WREG32(TN_RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); 3447 WREG32(TN_RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); 3448 } 3449 if (rdev->family <= CHIP_CAYMAN) { 3450 WREG32(RLC_HB_BASE, 0); 3451 WREG32(RLC_HB_RPTR, 0); 3452 WREG32(RLC_HB_WPTR, 0); 3453 } 3454 if (rdev->family <= CHIP_CAICOS) { 3455 WREG32(RLC_HB_WPTR_LSB_ADDR, 0); 3456 WREG32(RLC_HB_WPTR_MSB_ADDR, 0); 3457 } 3458 WREG32(RLC_MC_CNTL, 0); 3459 WREG32(RLC_UCODE_CNTL, 0); 3460 3461 fw_data = (const __be32 *)rdev->rlc_fw->data; 3462 if (rdev->family >= CHIP_ARUBA) { 3463 for (i = 0; i < ARUBA_RLC_UCODE_SIZE; i++) { 3464 WREG32(RLC_UCODE_ADDR, i); 3465 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); 3466 } 3467 } else if (rdev->family >= CHIP_CAYMAN) { 3468 for (i = 0; i < CAYMAN_RLC_UCODE_SIZE; i++) { 3469 WREG32(RLC_UCODE_ADDR, i); 3470 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); 3471 } 3472 } else if (rdev->family >= CHIP_CEDAR) { 3473 for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) { 3474 WREG32(RLC_UCODE_ADDR, i); 3475 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); 3476 } 3477 } else if (rdev->family >= CHIP_RV770) { 3478 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) { 3479 WREG32(RLC_UCODE_ADDR, i); 3480 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); 3481 } 3482 } else { 3483 for (i = 0; i < RLC_UCODE_SIZE; i++) { 3484 WREG32(RLC_UCODE_ADDR, i); 3485 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); 3486 } 3487 } 3488 WREG32(RLC_UCODE_ADDR, 0); 3489 3490 r600_rlc_start(rdev); 3491 3492 return 0; 3493 } 3494 3495 static void r600_enable_interrupts(struct radeon_device *rdev) 3496 { 3497 u32 ih_cntl = RREG32(IH_CNTL); 3498 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); 3499 3500 ih_cntl |= ENABLE_INTR; 3501 ih_rb_cntl |= IH_RB_ENABLE; 3502 WREG32(IH_CNTL, ih_cntl); 3503 WREG32(IH_RB_CNTL, ih_rb_cntl); 3504 rdev->ih.enabled = true; 3505 } 3506 3507 void r600_disable_interrupts(struct radeon_device *rdev) 3508 { 3509 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); 3510 u32 ih_cntl = RREG32(IH_CNTL); 3511 3512 ih_rb_cntl &= ~IH_RB_ENABLE; 3513 ih_cntl &= ~ENABLE_INTR; 3514 WREG32(IH_RB_CNTL, ih_rb_cntl); 3515 WREG32(IH_CNTL, ih_cntl); 3516 /* set rptr, wptr to 0 */ 3517 WREG32(IH_RB_RPTR, 0); 3518 WREG32(IH_RB_WPTR, 0); 3519 rdev->ih.enabled = false; 3520 rdev->ih.rptr = 0; 3521 } 3522 3523 static void r600_disable_interrupt_state(struct radeon_device *rdev) 3524 { 3525 u32 tmp; 3526 3527 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); 3528 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE; 3529 WREG32(DMA_CNTL, tmp); 3530 WREG32(GRBM_INT_CNTL, 0); 3531 WREG32(DxMODE_INT_MASK, 0); 3532 WREG32(D1GRPH_INTERRUPT_CONTROL, 0); 3533 WREG32(D2GRPH_INTERRUPT_CONTROL, 0); 3534 if (ASIC_IS_DCE3(rdev)) { 3535 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0); 3536 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0); 3537 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3538 WREG32(DC_HPD1_INT_CONTROL, tmp); 3539 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3540 WREG32(DC_HPD2_INT_CONTROL, tmp); 3541 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3542 WREG32(DC_HPD3_INT_CONTROL, tmp); 3543 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3544 WREG32(DC_HPD4_INT_CONTROL, tmp); 3545 if (ASIC_IS_DCE32(rdev)) { 3546 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3547 WREG32(DC_HPD5_INT_CONTROL, tmp); 3548 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3549 WREG32(DC_HPD6_INT_CONTROL, tmp); 3550 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3551 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp); 3552 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3553 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp); 3554 } else { 3555 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3556 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); 3557 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3558 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp); 3559 } 3560 } else { 3561 WREG32(DACA_AUTODETECT_INT_CONTROL, 0); 3562 WREG32(DACB_AUTODETECT_INT_CONTROL, 0); 3563 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; 3564 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 3565 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; 3566 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 3567 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; 3568 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); 3569 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3570 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); 3571 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3572 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp); 3573 } 3574 } 3575 3576 int r600_irq_init(struct radeon_device *rdev) 3577 { 3578 int ret = 0; 3579 int rb_bufsz; 3580 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; 3581 3582 /* allocate ring */ 3583 ret = r600_ih_ring_alloc(rdev); 3584 if (ret) 3585 return ret; 3586 3587 /* disable irqs */ 3588 r600_disable_interrupts(rdev); 3589 3590 /* init rlc */ 3591 ret = r600_rlc_init(rdev); 3592 if (ret) { 3593 r600_ih_ring_fini(rdev); 3594 return ret; 3595 } 3596 3597 /* setup interrupt control */ 3598 /* set dummy read address to ring address */ 3599 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8); 3600 interrupt_cntl = RREG32(INTERRUPT_CNTL); 3601 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi 3602 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN 3603 */ 3604 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE; 3605 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */ 3606 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN; 3607 WREG32(INTERRUPT_CNTL, interrupt_cntl); 3608 3609 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8); 3610 rb_bufsz = drm_order(rdev->ih.ring_size / 4); 3611 3612 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE | 3613 IH_WPTR_OVERFLOW_CLEAR | 3614 (rb_bufsz << 1)); 3615 3616 if (rdev->wb.enabled) 3617 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE; 3618 3619 /* set the writeback address whether it's enabled or not */ 3620 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC); 3621 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF); 3622 3623 WREG32(IH_RB_CNTL, ih_rb_cntl); 3624 3625 /* set rptr, wptr to 0 */ 3626 WREG32(IH_RB_RPTR, 0); 3627 WREG32(IH_RB_WPTR, 0); 3628 3629 /* Default settings for IH_CNTL (disabled at first) */ 3630 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10); 3631 /* RPTR_REARM only works if msi's are enabled */ 3632 if (rdev->msi_enabled) 3633 ih_cntl |= RPTR_REARM; 3634 WREG32(IH_CNTL, ih_cntl); 3635 3636 /* force the active interrupt state to all disabled */ 3637 if (rdev->family >= CHIP_CEDAR) 3638 evergreen_disable_interrupt_state(rdev); 3639 else 3640 r600_disable_interrupt_state(rdev); 3641 3642 /* at this point everything should be setup correctly to enable master */ 3643 pci_set_master(rdev->pdev); 3644 3645 /* enable irqs */ 3646 r600_enable_interrupts(rdev); 3647 3648 return ret; 3649 } 3650 3651 void r600_irq_suspend(struct radeon_device *rdev) 3652 { 3653 r600_irq_disable(rdev); 3654 r600_rlc_stop(rdev); 3655 } 3656 3657 void r600_irq_fini(struct radeon_device *rdev) 3658 { 3659 r600_irq_suspend(rdev); 3660 r600_ih_ring_fini(rdev); 3661 } 3662 3663 int r600_irq_set(struct radeon_device *rdev) 3664 { 3665 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; 3666 u32 mode_int = 0; 3667 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0; 3668 u32 grbm_int_cntl = 0; 3669 u32 hdmi0, hdmi1; 3670 u32 d1grph = 0, d2grph = 0; 3671 u32 dma_cntl; 3672 3673 if (!rdev->irq.installed) { 3674 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); 3675 return -EINVAL; 3676 } 3677 /* don't enable anything if the ih is disabled */ 3678 if (!rdev->ih.enabled) { 3679 r600_disable_interrupts(rdev); 3680 /* force the active interrupt state to all disabled */ 3681 r600_disable_interrupt_state(rdev); 3682 return 0; 3683 } 3684 3685 if (ASIC_IS_DCE3(rdev)) { 3686 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN; 3687 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN; 3688 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN; 3689 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN; 3690 if (ASIC_IS_DCE32(rdev)) { 3691 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; 3692 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN; 3693 hdmi0 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~AFMT_AZ_FORMAT_WTRIG_MASK; 3694 hdmi1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~AFMT_AZ_FORMAT_WTRIG_MASK; 3695 } else { 3696 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3697 hdmi1 = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3698 } 3699 } else { 3700 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN; 3701 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN; 3702 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN; 3703 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3704 hdmi1 = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3705 } 3706 dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE; 3707 3708 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { 3709 DRM_DEBUG("r600_irq_set: sw int\n"); 3710 cp_int_cntl |= RB_INT_ENABLE; 3711 cp_int_cntl |= TIME_STAMP_INT_ENABLE; 3712 } 3713 3714 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) { 3715 DRM_DEBUG("r600_irq_set: sw int dma\n"); 3716 dma_cntl |= TRAP_ENABLE; 3717 } 3718 3719 if (rdev->irq.crtc_vblank_int[0] || 3720 atomic_read(&rdev->irq.pflip[0])) { 3721 DRM_DEBUG("r600_irq_set: vblank 0\n"); 3722 mode_int |= D1MODE_VBLANK_INT_MASK; 3723 } 3724 if (rdev->irq.crtc_vblank_int[1] || 3725 atomic_read(&rdev->irq.pflip[1])) { 3726 DRM_DEBUG("r600_irq_set: vblank 1\n"); 3727 mode_int |= D2MODE_VBLANK_INT_MASK; 3728 } 3729 if (rdev->irq.hpd[0]) { 3730 DRM_DEBUG("r600_irq_set: hpd 1\n"); 3731 hpd1 |= DC_HPDx_INT_EN; 3732 } 3733 if (rdev->irq.hpd[1]) { 3734 DRM_DEBUG("r600_irq_set: hpd 2\n"); 3735 hpd2 |= DC_HPDx_INT_EN; 3736 } 3737 if (rdev->irq.hpd[2]) { 3738 DRM_DEBUG("r600_irq_set: hpd 3\n"); 3739 hpd3 |= DC_HPDx_INT_EN; 3740 } 3741 if (rdev->irq.hpd[3]) { 3742 DRM_DEBUG("r600_irq_set: hpd 4\n"); 3743 hpd4 |= DC_HPDx_INT_EN; 3744 } 3745 if (rdev->irq.hpd[4]) { 3746 DRM_DEBUG("r600_irq_set: hpd 5\n"); 3747 hpd5 |= DC_HPDx_INT_EN; 3748 } 3749 if (rdev->irq.hpd[5]) { 3750 DRM_DEBUG("r600_irq_set: hpd 6\n"); 3751 hpd6 |= DC_HPDx_INT_EN; 3752 } 3753 if (rdev->irq.afmt[0]) { 3754 DRM_DEBUG("r600_irq_set: hdmi 0\n"); 3755 hdmi0 |= HDMI0_AZ_FORMAT_WTRIG_MASK; 3756 } 3757 if (rdev->irq.afmt[1]) { 3758 DRM_DEBUG("r600_irq_set: hdmi 0\n"); 3759 hdmi1 |= HDMI0_AZ_FORMAT_WTRIG_MASK; 3760 } 3761 3762 WREG32(CP_INT_CNTL, cp_int_cntl); 3763 WREG32(DMA_CNTL, dma_cntl); 3764 WREG32(DxMODE_INT_MASK, mode_int); 3765 WREG32(D1GRPH_INTERRUPT_CONTROL, d1grph); 3766 WREG32(D2GRPH_INTERRUPT_CONTROL, d2grph); 3767 WREG32(GRBM_INT_CNTL, grbm_int_cntl); 3768 if (ASIC_IS_DCE3(rdev)) { 3769 WREG32(DC_HPD1_INT_CONTROL, hpd1); 3770 WREG32(DC_HPD2_INT_CONTROL, hpd2); 3771 WREG32(DC_HPD3_INT_CONTROL, hpd3); 3772 WREG32(DC_HPD4_INT_CONTROL, hpd4); 3773 if (ASIC_IS_DCE32(rdev)) { 3774 WREG32(DC_HPD5_INT_CONTROL, hpd5); 3775 WREG32(DC_HPD6_INT_CONTROL, hpd6); 3776 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, hdmi0); 3777 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, hdmi1); 3778 } else { 3779 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0); 3780 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, hdmi1); 3781 } 3782 } else { 3783 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); 3784 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); 3785 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3); 3786 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0); 3787 WREG32(HDMI1_AUDIO_PACKET_CONTROL, hdmi1); 3788 } 3789 3790 return 0; 3791 } 3792 3793 static void r600_irq_ack(struct radeon_device *rdev) 3794 { 3795 u32 tmp; 3796 3797 if (ASIC_IS_DCE3(rdev)) { 3798 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS); 3799 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE); 3800 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2); 3801 if (ASIC_IS_DCE32(rdev)) { 3802 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0); 3803 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1); 3804 } else { 3805 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); 3806 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS); 3807 } 3808 } else { 3809 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS); 3810 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); 3811 rdev->irq.stat_regs.r600.disp_int_cont2 = 0; 3812 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); 3813 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS); 3814 } 3815 rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS); 3816 rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS); 3817 3818 if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED) 3819 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR); 3820 if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED) 3821 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR); 3822 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) 3823 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK); 3824 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) 3825 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK); 3826 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) 3827 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK); 3828 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) 3829 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK); 3830 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) { 3831 if (ASIC_IS_DCE3(rdev)) { 3832 tmp = RREG32(DC_HPD1_INT_CONTROL); 3833 tmp |= DC_HPDx_INT_ACK; 3834 WREG32(DC_HPD1_INT_CONTROL, tmp); 3835 } else { 3836 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); 3837 tmp |= DC_HPDx_INT_ACK; 3838 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 3839 } 3840 } 3841 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) { 3842 if (ASIC_IS_DCE3(rdev)) { 3843 tmp = RREG32(DC_HPD2_INT_CONTROL); 3844 tmp |= DC_HPDx_INT_ACK; 3845 WREG32(DC_HPD2_INT_CONTROL, tmp); 3846 } else { 3847 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); 3848 tmp |= DC_HPDx_INT_ACK; 3849 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 3850 } 3851 } 3852 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) { 3853 if (ASIC_IS_DCE3(rdev)) { 3854 tmp = RREG32(DC_HPD3_INT_CONTROL); 3855 tmp |= DC_HPDx_INT_ACK; 3856 WREG32(DC_HPD3_INT_CONTROL, tmp); 3857 } else { 3858 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); 3859 tmp |= DC_HPDx_INT_ACK; 3860 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); 3861 } 3862 } 3863 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) { 3864 tmp = RREG32(DC_HPD4_INT_CONTROL); 3865 tmp |= DC_HPDx_INT_ACK; 3866 WREG32(DC_HPD4_INT_CONTROL, tmp); 3867 } 3868 if (ASIC_IS_DCE32(rdev)) { 3869 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) { 3870 tmp = RREG32(DC_HPD5_INT_CONTROL); 3871 tmp |= DC_HPDx_INT_ACK; 3872 WREG32(DC_HPD5_INT_CONTROL, tmp); 3873 } 3874 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) { 3875 tmp = RREG32(DC_HPD5_INT_CONTROL); 3876 tmp |= DC_HPDx_INT_ACK; 3877 WREG32(DC_HPD6_INT_CONTROL, tmp); 3878 } 3879 if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG) { 3880 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0); 3881 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; 3882 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp); 3883 } 3884 if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG) { 3885 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1); 3886 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; 3887 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp); 3888 } 3889 } else { 3890 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) { 3891 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL); 3892 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; 3893 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); 3894 } 3895 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) { 3896 if (ASIC_IS_DCE3(rdev)) { 3897 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL); 3898 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; 3899 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp); 3900 } else { 3901 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL); 3902 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; 3903 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp); 3904 } 3905 } 3906 } 3907 } 3908 3909 void r600_irq_disable(struct radeon_device *rdev) 3910 { 3911 r600_disable_interrupts(rdev); 3912 /* Wait and acknowledge irq */ 3913 mdelay(1); 3914 r600_irq_ack(rdev); 3915 r600_disable_interrupt_state(rdev); 3916 } 3917 3918 static u32 r600_get_ih_wptr(struct radeon_device *rdev) 3919 { 3920 u32 wptr, tmp; 3921 3922 if (rdev->wb.enabled) 3923 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]); 3924 else 3925 wptr = RREG32(IH_RB_WPTR); 3926 3927 if (wptr & RB_OVERFLOW) { 3928 /* When a ring buffer overflow happen start parsing interrupt 3929 * from the last not overwritten vector (wptr + 16). Hopefully 3930 * this should allow us to catchup. 3931 */ 3932 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n", 3933 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask); 3934 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; 3935 tmp = RREG32(IH_RB_CNTL); 3936 tmp |= IH_WPTR_OVERFLOW_CLEAR; 3937 WREG32(IH_RB_CNTL, tmp); 3938 } 3939 return (wptr & rdev->ih.ptr_mask); 3940 } 3941 3942 /* r600 IV Ring 3943 * Each IV ring entry is 128 bits: 3944 * [7:0] - interrupt source id 3945 * [31:8] - reserved 3946 * [59:32] - interrupt source data 3947 * [127:60] - reserved 3948 * 3949 * The basic interrupt vector entries 3950 * are decoded as follows: 3951 * src_id src_data description 3952 * 1 0 D1 Vblank 3953 * 1 1 D1 Vline 3954 * 5 0 D2 Vblank 3955 * 5 1 D2 Vline 3956 * 19 0 FP Hot plug detection A 3957 * 19 1 FP Hot plug detection B 3958 * 19 2 DAC A auto-detection 3959 * 19 3 DAC B auto-detection 3960 * 21 4 HDMI block A 3961 * 21 5 HDMI block B 3962 * 176 - CP_INT RB 3963 * 177 - CP_INT IB1 3964 * 178 - CP_INT IB2 3965 * 181 - EOP Interrupt 3966 * 233 - GUI Idle 3967 * 3968 * Note, these are based on r600 and may need to be 3969 * adjusted or added to on newer asics 3970 */ 3971 3972 int r600_irq_process(struct radeon_device *rdev) 3973 { 3974 u32 wptr; 3975 u32 rptr; 3976 u32 src_id, src_data; 3977 u32 ring_index; 3978 bool queue_hotplug = false; 3979 bool queue_hdmi = false; 3980 3981 if (!rdev->ih.enabled || rdev->shutdown) 3982 return IRQ_NONE; 3983 3984 /* No MSIs, need a dummy read to flush PCI DMAs */ 3985 if (!rdev->msi_enabled) 3986 RREG32(IH_RB_WPTR); 3987 3988 wptr = r600_get_ih_wptr(rdev); 3989 3990 restart_ih: 3991 /* is somebody else already processing irqs? */ 3992 if (atomic_xchg(&rdev->ih.lock, 1)) 3993 return IRQ_NONE; 3994 3995 rptr = rdev->ih.rptr; 3996 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr); 3997 3998 /* Order reading of wptr vs. reading of IH ring data */ 3999 rmb(); 4000 4001 /* display interrupts */ 4002 r600_irq_ack(rdev); 4003 4004 while (rptr != wptr) { 4005 /* wptr/rptr are in bytes! */ 4006 ring_index = rptr / 4; 4007 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff; 4008 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff; 4009 4010 switch (src_id) { 4011 case 1: /* D1 vblank/vline */ 4012 switch (src_data) { 4013 case 0: /* D1 vblank */ 4014 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) { 4015 if (rdev->irq.crtc_vblank_int[0]) { 4016 drm_handle_vblank(rdev->ddev, 0); 4017 rdev->pm.vblank_sync = true; 4018 wake_up(&rdev->irq.vblank_queue); 4019 } 4020 if (atomic_read(&rdev->irq.pflip[0])) 4021 radeon_crtc_handle_flip(rdev, 0); 4022 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT; 4023 DRM_DEBUG("IH: D1 vblank\n"); 4024 } 4025 break; 4026 case 1: /* D1 vline */ 4027 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) { 4028 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT; 4029 DRM_DEBUG("IH: D1 vline\n"); 4030 } 4031 break; 4032 default: 4033 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 4034 break; 4035 } 4036 break; 4037 case 5: /* D2 vblank/vline */ 4038 switch (src_data) { 4039 case 0: /* D2 vblank */ 4040 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) { 4041 if (rdev->irq.crtc_vblank_int[1]) { 4042 drm_handle_vblank(rdev->ddev, 1); 4043 rdev->pm.vblank_sync = true; 4044 wake_up(&rdev->irq.vblank_queue); 4045 } 4046 if (atomic_read(&rdev->irq.pflip[1])) 4047 radeon_crtc_handle_flip(rdev, 1); 4048 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT; 4049 DRM_DEBUG("IH: D2 vblank\n"); 4050 } 4051 break; 4052 case 1: /* D1 vline */ 4053 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) { 4054 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT; 4055 DRM_DEBUG("IH: D2 vline\n"); 4056 } 4057 break; 4058 default: 4059 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 4060 break; 4061 } 4062 break; 4063 case 19: /* HPD/DAC hotplug */ 4064 switch (src_data) { 4065 case 0: 4066 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) { 4067 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT; 4068 queue_hotplug = true; 4069 DRM_DEBUG("IH: HPD1\n"); 4070 } 4071 break; 4072 case 1: 4073 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) { 4074 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT; 4075 queue_hotplug = true; 4076 DRM_DEBUG("IH: HPD2\n"); 4077 } 4078 break; 4079 case 4: 4080 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) { 4081 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT; 4082 queue_hotplug = true; 4083 DRM_DEBUG("IH: HPD3\n"); 4084 } 4085 break; 4086 case 5: 4087 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) { 4088 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT; 4089 queue_hotplug = true; 4090 DRM_DEBUG("IH: HPD4\n"); 4091 } 4092 break; 4093 case 10: 4094 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) { 4095 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT; 4096 queue_hotplug = true; 4097 DRM_DEBUG("IH: HPD5\n"); 4098 } 4099 break; 4100 case 12: 4101 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) { 4102 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT; 4103 queue_hotplug = true; 4104 DRM_DEBUG("IH: HPD6\n"); 4105 } 4106 break; 4107 default: 4108 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 4109 break; 4110 } 4111 break; 4112 case 21: /* hdmi */ 4113 switch (src_data) { 4114 case 4: 4115 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) { 4116 rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG; 4117 queue_hdmi = true; 4118 DRM_DEBUG("IH: HDMI0\n"); 4119 } 4120 break; 4121 case 5: 4122 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) { 4123 rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG; 4124 queue_hdmi = true; 4125 DRM_DEBUG("IH: HDMI1\n"); 4126 } 4127 break; 4128 default: 4129 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); 4130 break; 4131 } 4132 break; 4133 case 176: /* CP_INT in ring buffer */ 4134 case 177: /* CP_INT in IB1 */ 4135 case 178: /* CP_INT in IB2 */ 4136 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data); 4137 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 4138 break; 4139 case 181: /* CP EOP event */ 4140 DRM_DEBUG("IH: CP EOP\n"); 4141 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 4142 break; 4143 case 224: /* DMA trap event */ 4144 DRM_DEBUG("IH: DMA trap\n"); 4145 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX); 4146 break; 4147 case 233: /* GUI IDLE */ 4148 DRM_DEBUG("IH: GUI idle\n"); 4149 break; 4150 default: 4151 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 4152 break; 4153 } 4154 4155 /* wptr/rptr are in bytes! */ 4156 rptr += 16; 4157 rptr &= rdev->ih.ptr_mask; 4158 } 4159 if (queue_hotplug) 4160 schedule_work(&rdev->hotplug_work); 4161 if (queue_hdmi) 4162 schedule_work(&rdev->audio_work); 4163 rdev->ih.rptr = rptr; 4164 WREG32(IH_RB_RPTR, rdev->ih.rptr); 4165 atomic_set(&rdev->ih.lock, 0); 4166 4167 /* make sure wptr hasn't changed while processing */ 4168 wptr = r600_get_ih_wptr(rdev); 4169 if (wptr != rptr) 4170 goto restart_ih; 4171 4172 return IRQ_HANDLED; 4173 } 4174 4175 /* 4176 * Debugfs info 4177 */ 4178 #if defined(CONFIG_DEBUG_FS) 4179 4180 static int r600_debugfs_mc_info(struct seq_file *m, void *data) 4181 { 4182 struct drm_info_node *node = (struct drm_info_node *) m->private; 4183 struct drm_device *dev = node->minor->dev; 4184 struct radeon_device *rdev = dev->dev_private; 4185 4186 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS); 4187 DREG32_SYS(m, rdev, VM_L2_STATUS); 4188 return 0; 4189 } 4190 4191 static struct drm_info_list r600_mc_info_list[] = { 4192 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL}, 4193 }; 4194 #endif 4195 4196 int r600_debugfs_mc_info_init(struct radeon_device *rdev) 4197 { 4198 #if defined(CONFIG_DEBUG_FS) 4199 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list)); 4200 #else 4201 return 0; 4202 #endif 4203 } 4204 4205 /** 4206 * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl 4207 * rdev: radeon device structure 4208 * bo: buffer object struct which userspace is waiting for idle 4209 * 4210 * Some R6XX/R7XX doesn't seems to take into account HDP flush performed 4211 * through ring buffer, this leads to corruption in rendering, see 4212 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we 4213 * directly perform HDP flush by writing register through MMIO. 4214 */ 4215 void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo) 4216 { 4217 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read 4218 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL. 4219 * This seems to cause problems on some AGP cards. Just use the old 4220 * method for them. 4221 */ 4222 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) && 4223 rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) { 4224 void __iomem *ptr = (void *)rdev->vram_scratch.ptr; 4225 u32 tmp; 4226 4227 WREG32(HDP_DEBUG1, 0); 4228 tmp = readl((void __iomem *)ptr); 4229 } else 4230 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); 4231 } 4232 4233 void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes) 4234 { 4235 u32 link_width_cntl, mask, target_reg; 4236 4237 if (rdev->flags & RADEON_IS_IGP) 4238 return; 4239 4240 if (!(rdev->flags & RADEON_IS_PCIE)) 4241 return; 4242 4243 /* x2 cards have a special sequence */ 4244 if (ASIC_IS_X2(rdev)) 4245 return; 4246 4247 /* FIXME wait for idle */ 4248 4249 switch (lanes) { 4250 case 0: 4251 mask = RADEON_PCIE_LC_LINK_WIDTH_X0; 4252 break; 4253 case 1: 4254 mask = RADEON_PCIE_LC_LINK_WIDTH_X1; 4255 break; 4256 case 2: 4257 mask = RADEON_PCIE_LC_LINK_WIDTH_X2; 4258 break; 4259 case 4: 4260 mask = RADEON_PCIE_LC_LINK_WIDTH_X4; 4261 break; 4262 case 8: 4263 mask = RADEON_PCIE_LC_LINK_WIDTH_X8; 4264 break; 4265 case 12: 4266 mask = RADEON_PCIE_LC_LINK_WIDTH_X12; 4267 break; 4268 case 16: 4269 default: 4270 mask = RADEON_PCIE_LC_LINK_WIDTH_X16; 4271 break; 4272 } 4273 4274 link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 4275 4276 if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) == 4277 (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT)) 4278 return; 4279 4280 if (link_width_cntl & R600_PCIE_LC_UPCONFIGURE_DIS) 4281 return; 4282 4283 link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK | 4284 RADEON_PCIE_LC_RECONFIG_NOW | 4285 R600_PCIE_LC_RENEGOTIATE_EN | 4286 R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE); 4287 link_width_cntl |= mask; 4288 4289 WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4290 4291 /* some northbridges can renegotiate the link rather than requiring 4292 * a complete re-config. 4293 * e.g., AMD 780/790 northbridges (pci ids: 0x5956, 0x5957, 0x5958, etc.) 4294 */ 4295 if (link_width_cntl & R600_PCIE_LC_RENEGOTIATION_SUPPORT) 4296 link_width_cntl |= R600_PCIE_LC_RENEGOTIATE_EN | R600_PCIE_LC_UPCONFIGURE_SUPPORT; 4297 else 4298 link_width_cntl |= R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE; 4299 4300 WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl | 4301 RADEON_PCIE_LC_RECONFIG_NOW)); 4302 4303 if (rdev->family >= CHIP_RV770) 4304 target_reg = R700_TARGET_AND_CURRENT_PROFILE_INDEX; 4305 else 4306 target_reg = R600_TARGET_AND_CURRENT_PROFILE_INDEX; 4307 4308 /* wait for lane set to complete */ 4309 link_width_cntl = RREG32(target_reg); 4310 while (link_width_cntl == 0xffffffff) 4311 link_width_cntl = RREG32(target_reg); 4312 4313 } 4314 4315 int r600_get_pcie_lanes(struct radeon_device *rdev) 4316 { 4317 u32 link_width_cntl; 4318 4319 if (rdev->flags & RADEON_IS_IGP) 4320 return 0; 4321 4322 if (!(rdev->flags & RADEON_IS_PCIE)) 4323 return 0; 4324 4325 /* x2 cards have a special sequence */ 4326 if (ASIC_IS_X2(rdev)) 4327 return 0; 4328 4329 /* FIXME wait for idle */ 4330 4331 link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 4332 4333 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) { 4334 case RADEON_PCIE_LC_LINK_WIDTH_X0: 4335 return 0; 4336 case RADEON_PCIE_LC_LINK_WIDTH_X1: 4337 return 1; 4338 case RADEON_PCIE_LC_LINK_WIDTH_X2: 4339 return 2; 4340 case RADEON_PCIE_LC_LINK_WIDTH_X4: 4341 return 4; 4342 case RADEON_PCIE_LC_LINK_WIDTH_X8: 4343 return 8; 4344 case RADEON_PCIE_LC_LINK_WIDTH_X16: 4345 default: 4346 return 16; 4347 } 4348 } 4349 4350 static void r600_pcie_gen2_enable(struct radeon_device *rdev) 4351 { 4352 u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp; 4353 u16 link_cntl2; 4354 u32 mask; 4355 int ret; 4356 4357 if (radeon_pcie_gen2 == 0) 4358 return; 4359 4360 if (rdev->flags & RADEON_IS_IGP) 4361 return; 4362 4363 if (!(rdev->flags & RADEON_IS_PCIE)) 4364 return; 4365 4366 /* x2 cards have a special sequence */ 4367 if (ASIC_IS_X2(rdev)) 4368 return; 4369 4370 /* only RV6xx+ chips are supported */ 4371 if (rdev->family <= CHIP_R600) 4372 return; 4373 4374 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); 4375 if (ret != 0) 4376 return; 4377 4378 if (!(mask & DRM_PCIE_SPEED_50)) 4379 return; 4380 4381 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 4382 if (speed_cntl & LC_CURRENT_DATA_RATE) { 4383 DRM_INFO("PCIE gen 2 link speeds already enabled\n"); 4384 return; 4385 } 4386 4387 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"); 4388 4389 /* 55 nm r6xx asics */ 4390 if ((rdev->family == CHIP_RV670) || 4391 (rdev->family == CHIP_RV620) || 4392 (rdev->family == CHIP_RV635)) { 4393 /* advertise upconfig capability */ 4394 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); 4395 link_width_cntl &= ~LC_UPCONFIGURE_DIS; 4396 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4397 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); 4398 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) { 4399 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; 4400 link_width_cntl &= ~(LC_LINK_WIDTH_MASK | 4401 LC_RECONFIG_ARC_MISSING_ESCAPE); 4402 link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN; 4403 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4404 } else { 4405 link_width_cntl |= LC_UPCONFIGURE_DIS; 4406 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4407 } 4408 } 4409 4410 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 4411 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) && 4412 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { 4413 4414 /* 55 nm r6xx asics */ 4415 if ((rdev->family == CHIP_RV670) || 4416 (rdev->family == CHIP_RV620) || 4417 (rdev->family == CHIP_RV635)) { 4418 WREG32(MM_CFGREGS_CNTL, 0x8); 4419 link_cntl2 = RREG32(0x4088); 4420 WREG32(MM_CFGREGS_CNTL, 0); 4421 /* not supported yet */ 4422 if (link_cntl2 & SELECTABLE_DEEMPHASIS) 4423 return; 4424 } 4425 4426 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK; 4427 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT); 4428 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK; 4429 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE; 4430 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE; 4431 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); 4432 4433 tmp = RREG32(0x541c); 4434 WREG32(0x541c, tmp | 0x8); 4435 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN); 4436 link_cntl2 = RREG16(0x4088); 4437 link_cntl2 &= ~TARGET_LINK_SPEED_MASK; 4438 link_cntl2 |= 0x2; 4439 WREG16(0x4088, link_cntl2); 4440 WREG32(MM_CFGREGS_CNTL, 0); 4441 4442 if ((rdev->family == CHIP_RV670) || 4443 (rdev->family == CHIP_RV620) || 4444 (rdev->family == CHIP_RV635)) { 4445 training_cntl = RREG32_PCIE_P(PCIE_LC_TRAINING_CNTL); 4446 training_cntl &= ~LC_POINT_7_PLUS_EN; 4447 WREG32_PCIE_P(PCIE_LC_TRAINING_CNTL, training_cntl); 4448 } else { 4449 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 4450 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN; 4451 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); 4452 } 4453 4454 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 4455 speed_cntl |= LC_GEN2_EN_STRAP; 4456 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); 4457 4458 } else { 4459 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); 4460 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */ 4461 if (1) 4462 link_width_cntl |= LC_UPCONFIGURE_DIS; 4463 else 4464 link_width_cntl &= ~LC_UPCONFIGURE_DIS; 4465 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4466 } 4467 } 4468 4469 /** 4470 * r600_get_gpu_clock_counter - return GPU clock counter snapshot 4471 * 4472 * @rdev: radeon_device pointer 4473 * 4474 * Fetches a GPU clock counter snapshot (R6xx-cayman). 4475 * Returns the 64 bit clock counter snapshot. 4476 */ 4477 uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev) 4478 { 4479 uint64_t clock; 4480 4481 mutex_lock(&rdev->gpu_clock_mutex); 4482 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1); 4483 clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) | 4484 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 4485 mutex_unlock(&rdev->gpu_clock_mutex); 4486 return clock; 4487 } 4488