1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/slab.h> 29 #include <linux/seq_file.h> 30 #include <linux/firmware.h> 31 #include <linux/platform_device.h> 32 #include <linux/module.h> 33 #include "drmP.h" 34 #include "radeon_drm.h" 35 #include "radeon.h" 36 #include "radeon_asic.h" 37 #include "radeon_mode.h" 38 #include "r600d.h" 39 #include "atom.h" 40 #include "avivod.h" 41 42 #define PFP_UCODE_SIZE 576 43 #define PM4_UCODE_SIZE 1792 44 #define RLC_UCODE_SIZE 768 45 #define R700_PFP_UCODE_SIZE 848 46 #define R700_PM4_UCODE_SIZE 1360 47 #define R700_RLC_UCODE_SIZE 1024 48 #define EVERGREEN_PFP_UCODE_SIZE 1120 49 #define EVERGREEN_PM4_UCODE_SIZE 1376 50 #define EVERGREEN_RLC_UCODE_SIZE 768 51 #define CAYMAN_RLC_UCODE_SIZE 1024 52 53 /* Firmware Names */ 54 MODULE_FIRMWARE("radeon/R600_pfp.bin"); 55 MODULE_FIRMWARE("radeon/R600_me.bin"); 56 MODULE_FIRMWARE("radeon/RV610_pfp.bin"); 57 MODULE_FIRMWARE("radeon/RV610_me.bin"); 58 MODULE_FIRMWARE("radeon/RV630_pfp.bin"); 59 MODULE_FIRMWARE("radeon/RV630_me.bin"); 60 MODULE_FIRMWARE("radeon/RV620_pfp.bin"); 61 MODULE_FIRMWARE("radeon/RV620_me.bin"); 62 MODULE_FIRMWARE("radeon/RV635_pfp.bin"); 63 MODULE_FIRMWARE("radeon/RV635_me.bin"); 64 MODULE_FIRMWARE("radeon/RV670_pfp.bin"); 65 MODULE_FIRMWARE("radeon/RV670_me.bin"); 66 MODULE_FIRMWARE("radeon/RS780_pfp.bin"); 67 MODULE_FIRMWARE("radeon/RS780_me.bin"); 68 MODULE_FIRMWARE("radeon/RV770_pfp.bin"); 69 MODULE_FIRMWARE("radeon/RV770_me.bin"); 70 MODULE_FIRMWARE("radeon/RV730_pfp.bin"); 71 MODULE_FIRMWARE("radeon/RV730_me.bin"); 72 MODULE_FIRMWARE("radeon/RV710_pfp.bin"); 73 MODULE_FIRMWARE("radeon/RV710_me.bin"); 74 MODULE_FIRMWARE("radeon/R600_rlc.bin"); 75 MODULE_FIRMWARE("radeon/R700_rlc.bin"); 76 MODULE_FIRMWARE("radeon/CEDAR_pfp.bin"); 77 MODULE_FIRMWARE("radeon/CEDAR_me.bin"); 78 MODULE_FIRMWARE("radeon/CEDAR_rlc.bin"); 79 MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin"); 80 MODULE_FIRMWARE("radeon/REDWOOD_me.bin"); 81 MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin"); 82 MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin"); 83 MODULE_FIRMWARE("radeon/JUNIPER_me.bin"); 84 MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin"); 85 MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin"); 86 MODULE_FIRMWARE("radeon/CYPRESS_me.bin"); 87 MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin"); 88 MODULE_FIRMWARE("radeon/PALM_pfp.bin"); 89 MODULE_FIRMWARE("radeon/PALM_me.bin"); 90 MODULE_FIRMWARE("radeon/SUMO_rlc.bin"); 91 MODULE_FIRMWARE("radeon/SUMO_pfp.bin"); 92 MODULE_FIRMWARE("radeon/SUMO_me.bin"); 93 MODULE_FIRMWARE("radeon/SUMO2_pfp.bin"); 94 MODULE_FIRMWARE("radeon/SUMO2_me.bin"); 95 96 int r600_debugfs_mc_info_init(struct radeon_device *rdev); 97 98 /* r600,rv610,rv630,rv620,rv635,rv670 */ 99 int r600_mc_wait_for_idle(struct radeon_device *rdev); 100 void r600_gpu_init(struct radeon_device *rdev); 101 void r600_fini(struct radeon_device *rdev); 102 void r600_irq_disable(struct radeon_device *rdev); 103 static void r600_pcie_gen2_enable(struct radeon_device *rdev); 104 105 /* get temperature in millidegrees */ 106 int rv6xx_get_temp(struct radeon_device *rdev) 107 { 108 u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >> 109 ASIC_T_SHIFT; 110 int actual_temp = temp & 0xff; 111 112 if (temp & 0x100) 113 actual_temp -= 256; 114 115 return actual_temp * 1000; 116 } 117 118 void r600_pm_get_dynpm_state(struct radeon_device *rdev) 119 { 120 int i; 121 122 rdev->pm.dynpm_can_upclock = true; 123 rdev->pm.dynpm_can_downclock = true; 124 125 /* power state array is low to high, default is first */ 126 if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) { 127 int min_power_state_index = 0; 128 129 if (rdev->pm.num_power_states > 2) 130 min_power_state_index = 1; 131 132 switch (rdev->pm.dynpm_planned_action) { 133 case DYNPM_ACTION_MINIMUM: 134 rdev->pm.requested_power_state_index = min_power_state_index; 135 rdev->pm.requested_clock_mode_index = 0; 136 rdev->pm.dynpm_can_downclock = false; 137 break; 138 case DYNPM_ACTION_DOWNCLOCK: 139 if (rdev->pm.current_power_state_index == min_power_state_index) { 140 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 141 rdev->pm.dynpm_can_downclock = false; 142 } else { 143 if (rdev->pm.active_crtc_count > 1) { 144 for (i = 0; i < rdev->pm.num_power_states; i++) { 145 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 146 continue; 147 else if (i >= rdev->pm.current_power_state_index) { 148 rdev->pm.requested_power_state_index = 149 rdev->pm.current_power_state_index; 150 break; 151 } else { 152 rdev->pm.requested_power_state_index = i; 153 break; 154 } 155 } 156 } else { 157 if (rdev->pm.current_power_state_index == 0) 158 rdev->pm.requested_power_state_index = 159 rdev->pm.num_power_states - 1; 160 else 161 rdev->pm.requested_power_state_index = 162 rdev->pm.current_power_state_index - 1; 163 } 164 } 165 rdev->pm.requested_clock_mode_index = 0; 166 /* don't use the power state if crtcs are active and no display flag is set */ 167 if ((rdev->pm.active_crtc_count > 0) && 168 (rdev->pm.power_state[rdev->pm.requested_power_state_index]. 169 clock_info[rdev->pm.requested_clock_mode_index].flags & 170 RADEON_PM_MODE_NO_DISPLAY)) { 171 rdev->pm.requested_power_state_index++; 172 } 173 break; 174 case DYNPM_ACTION_UPCLOCK: 175 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) { 176 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 177 rdev->pm.dynpm_can_upclock = false; 178 } else { 179 if (rdev->pm.active_crtc_count > 1) { 180 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) { 181 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 182 continue; 183 else if (i <= rdev->pm.current_power_state_index) { 184 rdev->pm.requested_power_state_index = 185 rdev->pm.current_power_state_index; 186 break; 187 } else { 188 rdev->pm.requested_power_state_index = i; 189 break; 190 } 191 } 192 } else 193 rdev->pm.requested_power_state_index = 194 rdev->pm.current_power_state_index + 1; 195 } 196 rdev->pm.requested_clock_mode_index = 0; 197 break; 198 case DYNPM_ACTION_DEFAULT: 199 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; 200 rdev->pm.requested_clock_mode_index = 0; 201 rdev->pm.dynpm_can_upclock = false; 202 break; 203 case DYNPM_ACTION_NONE: 204 default: 205 DRM_ERROR("Requested mode for not defined action\n"); 206 return; 207 } 208 } else { 209 /* XXX select a power state based on AC/DC, single/dualhead, etc. */ 210 /* for now just select the first power state and switch between clock modes */ 211 /* power state array is low to high, default is first (0) */ 212 if (rdev->pm.active_crtc_count > 1) { 213 rdev->pm.requested_power_state_index = -1; 214 /* start at 1 as we don't want the default mode */ 215 for (i = 1; i < rdev->pm.num_power_states; i++) { 216 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 217 continue; 218 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) || 219 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) { 220 rdev->pm.requested_power_state_index = i; 221 break; 222 } 223 } 224 /* if nothing selected, grab the default state. */ 225 if (rdev->pm.requested_power_state_index == -1) 226 rdev->pm.requested_power_state_index = 0; 227 } else 228 rdev->pm.requested_power_state_index = 1; 229 230 switch (rdev->pm.dynpm_planned_action) { 231 case DYNPM_ACTION_MINIMUM: 232 rdev->pm.requested_clock_mode_index = 0; 233 rdev->pm.dynpm_can_downclock = false; 234 break; 235 case DYNPM_ACTION_DOWNCLOCK: 236 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) { 237 if (rdev->pm.current_clock_mode_index == 0) { 238 rdev->pm.requested_clock_mode_index = 0; 239 rdev->pm.dynpm_can_downclock = false; 240 } else 241 rdev->pm.requested_clock_mode_index = 242 rdev->pm.current_clock_mode_index - 1; 243 } else { 244 rdev->pm.requested_clock_mode_index = 0; 245 rdev->pm.dynpm_can_downclock = false; 246 } 247 /* don't use the power state if crtcs are active and no display flag is set */ 248 if ((rdev->pm.active_crtc_count > 0) && 249 (rdev->pm.power_state[rdev->pm.requested_power_state_index]. 250 clock_info[rdev->pm.requested_clock_mode_index].flags & 251 RADEON_PM_MODE_NO_DISPLAY)) { 252 rdev->pm.requested_clock_mode_index++; 253 } 254 break; 255 case DYNPM_ACTION_UPCLOCK: 256 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) { 257 if (rdev->pm.current_clock_mode_index == 258 (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) { 259 rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index; 260 rdev->pm.dynpm_can_upclock = false; 261 } else 262 rdev->pm.requested_clock_mode_index = 263 rdev->pm.current_clock_mode_index + 1; 264 } else { 265 rdev->pm.requested_clock_mode_index = 266 rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1; 267 rdev->pm.dynpm_can_upclock = false; 268 } 269 break; 270 case DYNPM_ACTION_DEFAULT: 271 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; 272 rdev->pm.requested_clock_mode_index = 0; 273 rdev->pm.dynpm_can_upclock = false; 274 break; 275 case DYNPM_ACTION_NONE: 276 default: 277 DRM_ERROR("Requested mode for not defined action\n"); 278 return; 279 } 280 } 281 282 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n", 283 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 284 clock_info[rdev->pm.requested_clock_mode_index].sclk, 285 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 286 clock_info[rdev->pm.requested_clock_mode_index].mclk, 287 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 288 pcie_lanes); 289 } 290 291 static int r600_pm_get_type_index(struct radeon_device *rdev, 292 enum radeon_pm_state_type ps_type, 293 int instance) 294 { 295 int i; 296 int found_instance = -1; 297 298 for (i = 0; i < rdev->pm.num_power_states; i++) { 299 if (rdev->pm.power_state[i].type == ps_type) { 300 found_instance++; 301 if (found_instance == instance) 302 return i; 303 } 304 } 305 /* return default if no match */ 306 return rdev->pm.default_power_state_index; 307 } 308 309 void rs780_pm_init_profile(struct radeon_device *rdev) 310 { 311 if (rdev->pm.num_power_states == 2) { 312 /* default */ 313 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 314 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 315 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 316 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 317 /* low sh */ 318 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; 319 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; 320 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 321 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 322 /* mid sh */ 323 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; 324 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0; 325 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 326 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 327 /* high sh */ 328 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; 329 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1; 330 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 331 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 332 /* low mh */ 333 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; 334 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0; 335 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 336 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 337 /* mid mh */ 338 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; 339 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0; 340 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 341 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 342 /* high mh */ 343 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; 344 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1; 345 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 346 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 347 } else if (rdev->pm.num_power_states == 3) { 348 /* default */ 349 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 350 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 351 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 352 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 353 /* low sh */ 354 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1; 355 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1; 356 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 357 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 358 /* mid sh */ 359 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1; 360 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; 361 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 362 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 363 /* high sh */ 364 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1; 365 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2; 366 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 367 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 368 /* low mh */ 369 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1; 370 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1; 371 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 372 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 373 /* mid mh */ 374 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1; 375 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1; 376 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 377 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 378 /* high mh */ 379 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1; 380 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2; 381 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 382 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 383 } else { 384 /* default */ 385 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 386 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 387 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 388 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 389 /* low sh */ 390 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2; 391 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2; 392 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 393 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 394 /* mid sh */ 395 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2; 396 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2; 397 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 398 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 399 /* high sh */ 400 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2; 401 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3; 402 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 403 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 404 /* low mh */ 405 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2; 406 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0; 407 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 408 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 409 /* mid mh */ 410 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2; 411 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0; 412 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 413 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 414 /* high mh */ 415 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2; 416 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3; 417 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 418 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 419 } 420 } 421 422 void r600_pm_init_profile(struct radeon_device *rdev) 423 { 424 if (rdev->family == CHIP_R600) { 425 /* XXX */ 426 /* default */ 427 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 428 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 429 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 430 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 431 /* low sh */ 432 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 433 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 434 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 435 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 436 /* mid sh */ 437 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 438 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 439 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 440 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 441 /* high sh */ 442 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 443 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 444 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 445 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 446 /* low mh */ 447 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 448 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 449 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 450 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 451 /* mid mh */ 452 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 453 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 454 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 455 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 456 /* high mh */ 457 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 458 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 459 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 460 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 461 } else { 462 if (rdev->pm.num_power_states < 4) { 463 /* default */ 464 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 465 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 466 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 467 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; 468 /* low sh */ 469 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1; 470 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1; 471 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 472 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 473 /* mid sh */ 474 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1; 475 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; 476 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 477 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; 478 /* high sh */ 479 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1; 480 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1; 481 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 482 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; 483 /* low mh */ 484 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2; 485 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2; 486 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 487 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 488 /* low mh */ 489 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2; 490 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2; 491 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 492 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; 493 /* high mh */ 494 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2; 495 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2; 496 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 497 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; 498 } else { 499 /* default */ 500 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 501 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 502 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 503 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; 504 /* low sh */ 505 if (rdev->flags & RADEON_IS_MOBILITY) { 506 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 507 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0); 508 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 509 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0); 510 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 511 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 512 } else { 513 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 514 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); 515 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 516 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); 517 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 518 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 519 } 520 /* mid sh */ 521 if (rdev->flags & RADEON_IS_MOBILITY) { 522 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 523 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0); 524 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 525 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0); 526 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 527 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; 528 } else { 529 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 530 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); 531 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 532 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); 533 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 534 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; 535 } 536 /* high sh */ 537 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 538 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); 539 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 540 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); 541 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 542 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; 543 /* low mh */ 544 if (rdev->flags & RADEON_IS_MOBILITY) { 545 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 546 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1); 547 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 548 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1); 549 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 550 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 551 } else { 552 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 553 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1); 554 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 555 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1); 556 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 557 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 558 } 559 /* mid mh */ 560 if (rdev->flags & RADEON_IS_MOBILITY) { 561 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 562 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1); 563 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 564 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1); 565 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 566 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; 567 } else { 568 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 569 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1); 570 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 571 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1); 572 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 573 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; 574 } 575 /* high mh */ 576 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 577 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1); 578 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 579 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1); 580 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 581 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; 582 } 583 } 584 } 585 586 void r600_pm_misc(struct radeon_device *rdev) 587 { 588 int req_ps_idx = rdev->pm.requested_power_state_index; 589 int req_cm_idx = rdev->pm.requested_clock_mode_index; 590 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx]; 591 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage; 592 593 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) { 594 /* 0xff01 is a flag rather then an actual voltage */ 595 if (voltage->voltage == 0xff01) 596 return; 597 if (voltage->voltage != rdev->pm.current_vddc) { 598 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); 599 rdev->pm.current_vddc = voltage->voltage; 600 DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage); 601 } 602 } 603 } 604 605 bool r600_gui_idle(struct radeon_device *rdev) 606 { 607 if (RREG32(GRBM_STATUS) & GUI_ACTIVE) 608 return false; 609 else 610 return true; 611 } 612 613 /* hpd for digital panel detect/disconnect */ 614 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) 615 { 616 bool connected = false; 617 618 if (ASIC_IS_DCE3(rdev)) { 619 switch (hpd) { 620 case RADEON_HPD_1: 621 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE) 622 connected = true; 623 break; 624 case RADEON_HPD_2: 625 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE) 626 connected = true; 627 break; 628 case RADEON_HPD_3: 629 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE) 630 connected = true; 631 break; 632 case RADEON_HPD_4: 633 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE) 634 connected = true; 635 break; 636 /* DCE 3.2 */ 637 case RADEON_HPD_5: 638 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE) 639 connected = true; 640 break; 641 case RADEON_HPD_6: 642 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE) 643 connected = true; 644 break; 645 default: 646 break; 647 } 648 } else { 649 switch (hpd) { 650 case RADEON_HPD_1: 651 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) 652 connected = true; 653 break; 654 case RADEON_HPD_2: 655 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) 656 connected = true; 657 break; 658 case RADEON_HPD_3: 659 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) 660 connected = true; 661 break; 662 default: 663 break; 664 } 665 } 666 return connected; 667 } 668 669 void r600_hpd_set_polarity(struct radeon_device *rdev, 670 enum radeon_hpd_id hpd) 671 { 672 u32 tmp; 673 bool connected = r600_hpd_sense(rdev, hpd); 674 675 if (ASIC_IS_DCE3(rdev)) { 676 switch (hpd) { 677 case RADEON_HPD_1: 678 tmp = RREG32(DC_HPD1_INT_CONTROL); 679 if (connected) 680 tmp &= ~DC_HPDx_INT_POLARITY; 681 else 682 tmp |= DC_HPDx_INT_POLARITY; 683 WREG32(DC_HPD1_INT_CONTROL, tmp); 684 break; 685 case RADEON_HPD_2: 686 tmp = RREG32(DC_HPD2_INT_CONTROL); 687 if (connected) 688 tmp &= ~DC_HPDx_INT_POLARITY; 689 else 690 tmp |= DC_HPDx_INT_POLARITY; 691 WREG32(DC_HPD2_INT_CONTROL, tmp); 692 break; 693 case RADEON_HPD_3: 694 tmp = RREG32(DC_HPD3_INT_CONTROL); 695 if (connected) 696 tmp &= ~DC_HPDx_INT_POLARITY; 697 else 698 tmp |= DC_HPDx_INT_POLARITY; 699 WREG32(DC_HPD3_INT_CONTROL, tmp); 700 break; 701 case RADEON_HPD_4: 702 tmp = RREG32(DC_HPD4_INT_CONTROL); 703 if (connected) 704 tmp &= ~DC_HPDx_INT_POLARITY; 705 else 706 tmp |= DC_HPDx_INT_POLARITY; 707 WREG32(DC_HPD4_INT_CONTROL, tmp); 708 break; 709 case RADEON_HPD_5: 710 tmp = RREG32(DC_HPD5_INT_CONTROL); 711 if (connected) 712 tmp &= ~DC_HPDx_INT_POLARITY; 713 else 714 tmp |= DC_HPDx_INT_POLARITY; 715 WREG32(DC_HPD5_INT_CONTROL, tmp); 716 break; 717 /* DCE 3.2 */ 718 case RADEON_HPD_6: 719 tmp = RREG32(DC_HPD6_INT_CONTROL); 720 if (connected) 721 tmp &= ~DC_HPDx_INT_POLARITY; 722 else 723 tmp |= DC_HPDx_INT_POLARITY; 724 WREG32(DC_HPD6_INT_CONTROL, tmp); 725 break; 726 default: 727 break; 728 } 729 } else { 730 switch (hpd) { 731 case RADEON_HPD_1: 732 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); 733 if (connected) 734 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; 735 else 736 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; 737 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 738 break; 739 case RADEON_HPD_2: 740 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); 741 if (connected) 742 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; 743 else 744 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; 745 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 746 break; 747 case RADEON_HPD_3: 748 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); 749 if (connected) 750 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; 751 else 752 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; 753 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); 754 break; 755 default: 756 break; 757 } 758 } 759 } 760 761 void r600_hpd_init(struct radeon_device *rdev) 762 { 763 struct drm_device *dev = rdev->ddev; 764 struct drm_connector *connector; 765 766 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 767 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 768 769 if (ASIC_IS_DCE3(rdev)) { 770 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa); 771 if (ASIC_IS_DCE32(rdev)) 772 tmp |= DC_HPDx_EN; 773 774 switch (radeon_connector->hpd.hpd) { 775 case RADEON_HPD_1: 776 WREG32(DC_HPD1_CONTROL, tmp); 777 rdev->irq.hpd[0] = true; 778 break; 779 case RADEON_HPD_2: 780 WREG32(DC_HPD2_CONTROL, tmp); 781 rdev->irq.hpd[1] = true; 782 break; 783 case RADEON_HPD_3: 784 WREG32(DC_HPD3_CONTROL, tmp); 785 rdev->irq.hpd[2] = true; 786 break; 787 case RADEON_HPD_4: 788 WREG32(DC_HPD4_CONTROL, tmp); 789 rdev->irq.hpd[3] = true; 790 break; 791 /* DCE 3.2 */ 792 case RADEON_HPD_5: 793 WREG32(DC_HPD5_CONTROL, tmp); 794 rdev->irq.hpd[4] = true; 795 break; 796 case RADEON_HPD_6: 797 WREG32(DC_HPD6_CONTROL, tmp); 798 rdev->irq.hpd[5] = true; 799 break; 800 default: 801 break; 802 } 803 } else { 804 switch (radeon_connector->hpd.hpd) { 805 case RADEON_HPD_1: 806 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN); 807 rdev->irq.hpd[0] = true; 808 break; 809 case RADEON_HPD_2: 810 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN); 811 rdev->irq.hpd[1] = true; 812 break; 813 case RADEON_HPD_3: 814 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN); 815 rdev->irq.hpd[2] = true; 816 break; 817 default: 818 break; 819 } 820 } 821 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); 822 } 823 if (rdev->irq.installed) 824 r600_irq_set(rdev); 825 } 826 827 void r600_hpd_fini(struct radeon_device *rdev) 828 { 829 struct drm_device *dev = rdev->ddev; 830 struct drm_connector *connector; 831 832 if (ASIC_IS_DCE3(rdev)) { 833 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 834 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 835 switch (radeon_connector->hpd.hpd) { 836 case RADEON_HPD_1: 837 WREG32(DC_HPD1_CONTROL, 0); 838 rdev->irq.hpd[0] = false; 839 break; 840 case RADEON_HPD_2: 841 WREG32(DC_HPD2_CONTROL, 0); 842 rdev->irq.hpd[1] = false; 843 break; 844 case RADEON_HPD_3: 845 WREG32(DC_HPD3_CONTROL, 0); 846 rdev->irq.hpd[2] = false; 847 break; 848 case RADEON_HPD_4: 849 WREG32(DC_HPD4_CONTROL, 0); 850 rdev->irq.hpd[3] = false; 851 break; 852 /* DCE 3.2 */ 853 case RADEON_HPD_5: 854 WREG32(DC_HPD5_CONTROL, 0); 855 rdev->irq.hpd[4] = false; 856 break; 857 case RADEON_HPD_6: 858 WREG32(DC_HPD6_CONTROL, 0); 859 rdev->irq.hpd[5] = false; 860 break; 861 default: 862 break; 863 } 864 } 865 } else { 866 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 867 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 868 switch (radeon_connector->hpd.hpd) { 869 case RADEON_HPD_1: 870 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0); 871 rdev->irq.hpd[0] = false; 872 break; 873 case RADEON_HPD_2: 874 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0); 875 rdev->irq.hpd[1] = false; 876 break; 877 case RADEON_HPD_3: 878 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0); 879 rdev->irq.hpd[2] = false; 880 break; 881 default: 882 break; 883 } 884 } 885 } 886 } 887 888 /* 889 * R600 PCIE GART 890 */ 891 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev) 892 { 893 unsigned i; 894 u32 tmp; 895 896 /* flush hdp cache so updates hit vram */ 897 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) && 898 !(rdev->flags & RADEON_IS_AGP)) { 899 void __iomem *ptr = (void *)rdev->gart.ptr; 900 u32 tmp; 901 902 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read 903 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL 904 * This seems to cause problems on some AGP cards. Just use the old 905 * method for them. 906 */ 907 WREG32(HDP_DEBUG1, 0); 908 tmp = readl((void __iomem *)ptr); 909 } else 910 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); 911 912 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12); 913 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12); 914 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1)); 915 for (i = 0; i < rdev->usec_timeout; i++) { 916 /* read MC_STATUS */ 917 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE); 918 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT; 919 if (tmp == 2) { 920 printk(KERN_WARNING "[drm] r600 flush TLB failed\n"); 921 return; 922 } 923 if (tmp) { 924 return; 925 } 926 udelay(1); 927 } 928 } 929 930 int r600_pcie_gart_init(struct radeon_device *rdev) 931 { 932 int r; 933 934 if (rdev->gart.robj) { 935 WARN(1, "R600 PCIE GART already initialized\n"); 936 return 0; 937 } 938 /* Initialize common gart structure */ 939 r = radeon_gart_init(rdev); 940 if (r) 941 return r; 942 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; 943 return radeon_gart_table_vram_alloc(rdev); 944 } 945 946 int r600_pcie_gart_enable(struct radeon_device *rdev) 947 { 948 u32 tmp; 949 int r, i; 950 951 if (rdev->gart.robj == NULL) { 952 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 953 return -EINVAL; 954 } 955 r = radeon_gart_table_vram_pin(rdev); 956 if (r) 957 return r; 958 radeon_gart_restore(rdev); 959 960 /* Setup L2 cache */ 961 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 962 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 963 EFFECTIVE_L2_QUEUE_SIZE(7)); 964 WREG32(VM_L2_CNTL2, 0); 965 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); 966 /* Setup TLB control */ 967 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | 968 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 969 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | 970 ENABLE_WAIT_L2_QUERY; 971 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); 972 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); 973 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); 974 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); 975 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); 976 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); 977 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); 978 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); 979 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); 980 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); 981 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); 982 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); 983 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 984 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 985 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); 986 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); 987 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); 988 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | 989 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); 990 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 991 (u32)(rdev->dummy_page.addr >> 12)); 992 for (i = 1; i < 7; i++) 993 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 994 995 r600_pcie_gart_tlb_flush(rdev); 996 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 997 (unsigned)(rdev->mc.gtt_size >> 20), 998 (unsigned long long)rdev->gart.table_addr); 999 rdev->gart.ready = true; 1000 return 0; 1001 } 1002 1003 void r600_pcie_gart_disable(struct radeon_device *rdev) 1004 { 1005 u32 tmp; 1006 int i; 1007 1008 /* Disable all tables */ 1009 for (i = 0; i < 7; i++) 1010 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 1011 1012 /* Disable L2 cache */ 1013 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | 1014 EFFECTIVE_L2_QUEUE_SIZE(7)); 1015 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); 1016 /* Setup L1 TLB control */ 1017 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | 1018 ENABLE_WAIT_L2_QUERY; 1019 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); 1020 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); 1021 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); 1022 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); 1023 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); 1024 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); 1025 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); 1026 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); 1027 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp); 1028 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp); 1029 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); 1030 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); 1031 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp); 1032 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); 1033 radeon_gart_table_vram_unpin(rdev); 1034 } 1035 1036 void r600_pcie_gart_fini(struct radeon_device *rdev) 1037 { 1038 radeon_gart_fini(rdev); 1039 r600_pcie_gart_disable(rdev); 1040 radeon_gart_table_vram_free(rdev); 1041 } 1042 1043 void r600_agp_enable(struct radeon_device *rdev) 1044 { 1045 u32 tmp; 1046 int i; 1047 1048 /* Setup L2 cache */ 1049 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 1050 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 1051 EFFECTIVE_L2_QUEUE_SIZE(7)); 1052 WREG32(VM_L2_CNTL2, 0); 1053 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); 1054 /* Setup TLB control */ 1055 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | 1056 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 1057 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | 1058 ENABLE_WAIT_L2_QUERY; 1059 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); 1060 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); 1061 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); 1062 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); 1063 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); 1064 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); 1065 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); 1066 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); 1067 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); 1068 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); 1069 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); 1070 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); 1071 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 1072 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 1073 for (i = 0; i < 7; i++) 1074 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 1075 } 1076 1077 int r600_mc_wait_for_idle(struct radeon_device *rdev) 1078 { 1079 unsigned i; 1080 u32 tmp; 1081 1082 for (i = 0; i < rdev->usec_timeout; i++) { 1083 /* read MC_STATUS */ 1084 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00; 1085 if (!tmp) 1086 return 0; 1087 udelay(1); 1088 } 1089 return -1; 1090 } 1091 1092 static void r600_mc_program(struct radeon_device *rdev) 1093 { 1094 struct rv515_mc_save save; 1095 u32 tmp; 1096 int i, j; 1097 1098 /* Initialize HDP */ 1099 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 1100 WREG32((0x2c14 + j), 0x00000000); 1101 WREG32((0x2c18 + j), 0x00000000); 1102 WREG32((0x2c1c + j), 0x00000000); 1103 WREG32((0x2c20 + j), 0x00000000); 1104 WREG32((0x2c24 + j), 0x00000000); 1105 } 1106 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); 1107 1108 rv515_mc_stop(rdev, &save); 1109 if (r600_mc_wait_for_idle(rdev)) { 1110 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1111 } 1112 /* Lockout access through VGA aperture (doesn't exist before R600) */ 1113 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); 1114 /* Update configuration */ 1115 if (rdev->flags & RADEON_IS_AGP) { 1116 if (rdev->mc.vram_start < rdev->mc.gtt_start) { 1117 /* VRAM before AGP */ 1118 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 1119 rdev->mc.vram_start >> 12); 1120 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 1121 rdev->mc.gtt_end >> 12); 1122 } else { 1123 /* VRAM after AGP */ 1124 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 1125 rdev->mc.gtt_start >> 12); 1126 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 1127 rdev->mc.vram_end >> 12); 1128 } 1129 } else { 1130 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12); 1131 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12); 1132 } 1133 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); 1134 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; 1135 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); 1136 WREG32(MC_VM_FB_LOCATION, tmp); 1137 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); 1138 WREG32(HDP_NONSURFACE_INFO, (2 << 7)); 1139 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); 1140 if (rdev->flags & RADEON_IS_AGP) { 1141 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22); 1142 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22); 1143 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); 1144 } else { 1145 WREG32(MC_VM_AGP_BASE, 0); 1146 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); 1147 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); 1148 } 1149 if (r600_mc_wait_for_idle(rdev)) { 1150 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1151 } 1152 rv515_mc_resume(rdev, &save); 1153 /* we need to own VRAM, so turn off the VGA renderer here 1154 * to stop it overwriting our objects */ 1155 rv515_vga_render_disable(rdev); 1156 } 1157 1158 /** 1159 * r600_vram_gtt_location - try to find VRAM & GTT location 1160 * @rdev: radeon device structure holding all necessary informations 1161 * @mc: memory controller structure holding memory informations 1162 * 1163 * Function will place try to place VRAM at same place as in CPU (PCI) 1164 * address space as some GPU seems to have issue when we reprogram at 1165 * different address space. 1166 * 1167 * If there is not enough space to fit the unvisible VRAM after the 1168 * aperture then we limit the VRAM size to the aperture. 1169 * 1170 * If we are using AGP then place VRAM adjacent to AGP aperture are we need 1171 * them to be in one from GPU point of view so that we can program GPU to 1172 * catch access outside them (weird GPU policy see ??). 1173 * 1174 * This function will never fails, worst case are limiting VRAM or GTT. 1175 * 1176 * Note: GTT start, end, size should be initialized before calling this 1177 * function on AGP platform. 1178 */ 1179 static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) 1180 { 1181 u64 size_bf, size_af; 1182 1183 if (mc->mc_vram_size > 0xE0000000) { 1184 /* leave room for at least 512M GTT */ 1185 dev_warn(rdev->dev, "limiting VRAM\n"); 1186 mc->real_vram_size = 0xE0000000; 1187 mc->mc_vram_size = 0xE0000000; 1188 } 1189 if (rdev->flags & RADEON_IS_AGP) { 1190 size_bf = mc->gtt_start; 1191 size_af = 0xFFFFFFFF - mc->gtt_end + 1; 1192 if (size_bf > size_af) { 1193 if (mc->mc_vram_size > size_bf) { 1194 dev_warn(rdev->dev, "limiting VRAM\n"); 1195 mc->real_vram_size = size_bf; 1196 mc->mc_vram_size = size_bf; 1197 } 1198 mc->vram_start = mc->gtt_start - mc->mc_vram_size; 1199 } else { 1200 if (mc->mc_vram_size > size_af) { 1201 dev_warn(rdev->dev, "limiting VRAM\n"); 1202 mc->real_vram_size = size_af; 1203 mc->mc_vram_size = size_af; 1204 } 1205 mc->vram_start = mc->gtt_end; 1206 } 1207 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 1208 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n", 1209 mc->mc_vram_size >> 20, mc->vram_start, 1210 mc->vram_end, mc->real_vram_size >> 20); 1211 } else { 1212 u64 base = 0; 1213 if (rdev->flags & RADEON_IS_IGP) { 1214 base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF; 1215 base <<= 24; 1216 } 1217 radeon_vram_location(rdev, &rdev->mc, base); 1218 rdev->mc.gtt_base_align = 0; 1219 radeon_gtt_location(rdev, mc); 1220 } 1221 } 1222 1223 int r600_mc_init(struct radeon_device *rdev) 1224 { 1225 u32 tmp; 1226 int chansize, numchan; 1227 1228 /* Get VRAM informations */ 1229 rdev->mc.vram_is_ddr = true; 1230 tmp = RREG32(RAMCFG); 1231 if (tmp & CHANSIZE_OVERRIDE) { 1232 chansize = 16; 1233 } else if (tmp & CHANSIZE_MASK) { 1234 chansize = 64; 1235 } else { 1236 chansize = 32; 1237 } 1238 tmp = RREG32(CHMAP); 1239 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { 1240 case 0: 1241 default: 1242 numchan = 1; 1243 break; 1244 case 1: 1245 numchan = 2; 1246 break; 1247 case 2: 1248 numchan = 4; 1249 break; 1250 case 3: 1251 numchan = 8; 1252 break; 1253 } 1254 rdev->mc.vram_width = numchan * chansize; 1255 /* Could aper size report 0 ? */ 1256 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); 1257 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); 1258 /* Setup GPU memory space */ 1259 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); 1260 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); 1261 rdev->mc.visible_vram_size = rdev->mc.aper_size; 1262 r600_vram_gtt_location(rdev, &rdev->mc); 1263 1264 if (rdev->flags & RADEON_IS_IGP) { 1265 rs690_pm_info(rdev); 1266 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); 1267 } 1268 radeon_update_bandwidth_info(rdev); 1269 return 0; 1270 } 1271 1272 int r600_vram_scratch_init(struct radeon_device *rdev) 1273 { 1274 int r; 1275 1276 if (rdev->vram_scratch.robj == NULL) { 1277 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, 1278 PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM, 1279 &rdev->vram_scratch.robj); 1280 if (r) { 1281 return r; 1282 } 1283 } 1284 1285 r = radeon_bo_reserve(rdev->vram_scratch.robj, false); 1286 if (unlikely(r != 0)) 1287 return r; 1288 r = radeon_bo_pin(rdev->vram_scratch.robj, 1289 RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr); 1290 if (r) { 1291 radeon_bo_unreserve(rdev->vram_scratch.robj); 1292 return r; 1293 } 1294 r = radeon_bo_kmap(rdev->vram_scratch.robj, 1295 (void **)&rdev->vram_scratch.ptr); 1296 if (r) 1297 radeon_bo_unpin(rdev->vram_scratch.robj); 1298 radeon_bo_unreserve(rdev->vram_scratch.robj); 1299 1300 return r; 1301 } 1302 1303 void r600_vram_scratch_fini(struct radeon_device *rdev) 1304 { 1305 int r; 1306 1307 if (rdev->vram_scratch.robj == NULL) { 1308 return; 1309 } 1310 r = radeon_bo_reserve(rdev->vram_scratch.robj, false); 1311 if (likely(r == 0)) { 1312 radeon_bo_kunmap(rdev->vram_scratch.robj); 1313 radeon_bo_unpin(rdev->vram_scratch.robj); 1314 radeon_bo_unreserve(rdev->vram_scratch.robj); 1315 } 1316 radeon_bo_unref(&rdev->vram_scratch.robj); 1317 } 1318 1319 /* We doesn't check that the GPU really needs a reset we simply do the 1320 * reset, it's up to the caller to determine if the GPU needs one. We 1321 * might add an helper function to check that. 1322 */ 1323 int r600_gpu_soft_reset(struct radeon_device *rdev) 1324 { 1325 struct rv515_mc_save save; 1326 u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) | 1327 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) | 1328 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) | 1329 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) | 1330 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) | 1331 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) | 1332 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) | 1333 S_008010_GUI_ACTIVE(1); 1334 u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) | 1335 S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) | 1336 S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) | 1337 S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) | 1338 S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) | 1339 S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) | 1340 S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) | 1341 S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1); 1342 u32 tmp; 1343 1344 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE)) 1345 return 0; 1346 1347 dev_info(rdev->dev, "GPU softreset \n"); 1348 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n", 1349 RREG32(R_008010_GRBM_STATUS)); 1350 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n", 1351 RREG32(R_008014_GRBM_STATUS2)); 1352 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n", 1353 RREG32(R_000E50_SRBM_STATUS)); 1354 rv515_mc_stop(rdev, &save); 1355 if (r600_mc_wait_for_idle(rdev)) { 1356 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1357 } 1358 /* Disable CP parsing/prefetching */ 1359 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); 1360 /* Check if any of the rendering block is busy and reset it */ 1361 if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) || 1362 (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) { 1363 tmp = S_008020_SOFT_RESET_CR(1) | 1364 S_008020_SOFT_RESET_DB(1) | 1365 S_008020_SOFT_RESET_CB(1) | 1366 S_008020_SOFT_RESET_PA(1) | 1367 S_008020_SOFT_RESET_SC(1) | 1368 S_008020_SOFT_RESET_SMX(1) | 1369 S_008020_SOFT_RESET_SPI(1) | 1370 S_008020_SOFT_RESET_SX(1) | 1371 S_008020_SOFT_RESET_SH(1) | 1372 S_008020_SOFT_RESET_TC(1) | 1373 S_008020_SOFT_RESET_TA(1) | 1374 S_008020_SOFT_RESET_VC(1) | 1375 S_008020_SOFT_RESET_VGT(1); 1376 dev_info(rdev->dev, " R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp); 1377 WREG32(R_008020_GRBM_SOFT_RESET, tmp); 1378 RREG32(R_008020_GRBM_SOFT_RESET); 1379 mdelay(15); 1380 WREG32(R_008020_GRBM_SOFT_RESET, 0); 1381 } 1382 /* Reset CP (we always reset CP) */ 1383 tmp = S_008020_SOFT_RESET_CP(1); 1384 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp); 1385 WREG32(R_008020_GRBM_SOFT_RESET, tmp); 1386 RREG32(R_008020_GRBM_SOFT_RESET); 1387 mdelay(15); 1388 WREG32(R_008020_GRBM_SOFT_RESET, 0); 1389 /* Wait a little for things to settle down */ 1390 mdelay(1); 1391 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n", 1392 RREG32(R_008010_GRBM_STATUS)); 1393 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n", 1394 RREG32(R_008014_GRBM_STATUS2)); 1395 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n", 1396 RREG32(R_000E50_SRBM_STATUS)); 1397 rv515_mc_resume(rdev, &save); 1398 return 0; 1399 } 1400 1401 bool r600_gpu_is_lockup(struct radeon_device *rdev) 1402 { 1403 u32 srbm_status; 1404 u32 grbm_status; 1405 u32 grbm_status2; 1406 struct r100_gpu_lockup *lockup; 1407 int r; 1408 1409 if (rdev->family >= CHIP_RV770) 1410 lockup = &rdev->config.rv770.lockup; 1411 else 1412 lockup = &rdev->config.r600.lockup; 1413 1414 srbm_status = RREG32(R_000E50_SRBM_STATUS); 1415 grbm_status = RREG32(R_008010_GRBM_STATUS); 1416 grbm_status2 = RREG32(R_008014_GRBM_STATUS2); 1417 if (!G_008010_GUI_ACTIVE(grbm_status)) { 1418 r100_gpu_lockup_update(lockup, &rdev->cp); 1419 return false; 1420 } 1421 /* force CP activities */ 1422 r = radeon_ring_lock(rdev, 2); 1423 if (!r) { 1424 /* PACKET2 NOP */ 1425 radeon_ring_write(rdev, 0x80000000); 1426 radeon_ring_write(rdev, 0x80000000); 1427 radeon_ring_unlock_commit(rdev); 1428 } 1429 rdev->cp.rptr = RREG32(R600_CP_RB_RPTR); 1430 return r100_gpu_cp_is_lockup(rdev, lockup, &rdev->cp); 1431 } 1432 1433 int r600_asic_reset(struct radeon_device *rdev) 1434 { 1435 return r600_gpu_soft_reset(rdev); 1436 } 1437 1438 static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes, 1439 u32 num_backends, 1440 u32 backend_disable_mask) 1441 { 1442 u32 backend_map = 0; 1443 u32 enabled_backends_mask; 1444 u32 enabled_backends_count; 1445 u32 cur_pipe; 1446 u32 swizzle_pipe[R6XX_MAX_PIPES]; 1447 u32 cur_backend; 1448 u32 i; 1449 1450 if (num_tile_pipes > R6XX_MAX_PIPES) 1451 num_tile_pipes = R6XX_MAX_PIPES; 1452 if (num_tile_pipes < 1) 1453 num_tile_pipes = 1; 1454 if (num_backends > R6XX_MAX_BACKENDS) 1455 num_backends = R6XX_MAX_BACKENDS; 1456 if (num_backends < 1) 1457 num_backends = 1; 1458 1459 enabled_backends_mask = 0; 1460 enabled_backends_count = 0; 1461 for (i = 0; i < R6XX_MAX_BACKENDS; ++i) { 1462 if (((backend_disable_mask >> i) & 1) == 0) { 1463 enabled_backends_mask |= (1 << i); 1464 ++enabled_backends_count; 1465 } 1466 if (enabled_backends_count == num_backends) 1467 break; 1468 } 1469 1470 if (enabled_backends_count == 0) { 1471 enabled_backends_mask = 1; 1472 enabled_backends_count = 1; 1473 } 1474 1475 if (enabled_backends_count != num_backends) 1476 num_backends = enabled_backends_count; 1477 1478 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES); 1479 switch (num_tile_pipes) { 1480 case 1: 1481 swizzle_pipe[0] = 0; 1482 break; 1483 case 2: 1484 swizzle_pipe[0] = 0; 1485 swizzle_pipe[1] = 1; 1486 break; 1487 case 3: 1488 swizzle_pipe[0] = 0; 1489 swizzle_pipe[1] = 1; 1490 swizzle_pipe[2] = 2; 1491 break; 1492 case 4: 1493 swizzle_pipe[0] = 0; 1494 swizzle_pipe[1] = 1; 1495 swizzle_pipe[2] = 2; 1496 swizzle_pipe[3] = 3; 1497 break; 1498 case 5: 1499 swizzle_pipe[0] = 0; 1500 swizzle_pipe[1] = 1; 1501 swizzle_pipe[2] = 2; 1502 swizzle_pipe[3] = 3; 1503 swizzle_pipe[4] = 4; 1504 break; 1505 case 6: 1506 swizzle_pipe[0] = 0; 1507 swizzle_pipe[1] = 2; 1508 swizzle_pipe[2] = 4; 1509 swizzle_pipe[3] = 5; 1510 swizzle_pipe[4] = 1; 1511 swizzle_pipe[5] = 3; 1512 break; 1513 case 7: 1514 swizzle_pipe[0] = 0; 1515 swizzle_pipe[1] = 2; 1516 swizzle_pipe[2] = 4; 1517 swizzle_pipe[3] = 6; 1518 swizzle_pipe[4] = 1; 1519 swizzle_pipe[5] = 3; 1520 swizzle_pipe[6] = 5; 1521 break; 1522 case 8: 1523 swizzle_pipe[0] = 0; 1524 swizzle_pipe[1] = 2; 1525 swizzle_pipe[2] = 4; 1526 swizzle_pipe[3] = 6; 1527 swizzle_pipe[4] = 1; 1528 swizzle_pipe[5] = 3; 1529 swizzle_pipe[6] = 5; 1530 swizzle_pipe[7] = 7; 1531 break; 1532 } 1533 1534 cur_backend = 0; 1535 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) { 1536 while (((1 << cur_backend) & enabled_backends_mask) == 0) 1537 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS; 1538 1539 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2))); 1540 1541 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS; 1542 } 1543 1544 return backend_map; 1545 } 1546 1547 int r600_count_pipe_bits(uint32_t val) 1548 { 1549 int i, ret = 0; 1550 1551 for (i = 0; i < 32; i++) { 1552 ret += val & 1; 1553 val >>= 1; 1554 } 1555 return ret; 1556 } 1557 1558 void r600_gpu_init(struct radeon_device *rdev) 1559 { 1560 u32 tiling_config; 1561 u32 ramcfg; 1562 u32 backend_map; 1563 u32 cc_rb_backend_disable; 1564 u32 cc_gc_shader_pipe_config; 1565 u32 tmp; 1566 int i, j; 1567 u32 sq_config; 1568 u32 sq_gpr_resource_mgmt_1 = 0; 1569 u32 sq_gpr_resource_mgmt_2 = 0; 1570 u32 sq_thread_resource_mgmt = 0; 1571 u32 sq_stack_resource_mgmt_1 = 0; 1572 u32 sq_stack_resource_mgmt_2 = 0; 1573 1574 /* FIXME: implement */ 1575 switch (rdev->family) { 1576 case CHIP_R600: 1577 rdev->config.r600.max_pipes = 4; 1578 rdev->config.r600.max_tile_pipes = 8; 1579 rdev->config.r600.max_simds = 4; 1580 rdev->config.r600.max_backends = 4; 1581 rdev->config.r600.max_gprs = 256; 1582 rdev->config.r600.max_threads = 192; 1583 rdev->config.r600.max_stack_entries = 256; 1584 rdev->config.r600.max_hw_contexts = 8; 1585 rdev->config.r600.max_gs_threads = 16; 1586 rdev->config.r600.sx_max_export_size = 128; 1587 rdev->config.r600.sx_max_export_pos_size = 16; 1588 rdev->config.r600.sx_max_export_smx_size = 128; 1589 rdev->config.r600.sq_num_cf_insts = 2; 1590 break; 1591 case CHIP_RV630: 1592 case CHIP_RV635: 1593 rdev->config.r600.max_pipes = 2; 1594 rdev->config.r600.max_tile_pipes = 2; 1595 rdev->config.r600.max_simds = 3; 1596 rdev->config.r600.max_backends = 1; 1597 rdev->config.r600.max_gprs = 128; 1598 rdev->config.r600.max_threads = 192; 1599 rdev->config.r600.max_stack_entries = 128; 1600 rdev->config.r600.max_hw_contexts = 8; 1601 rdev->config.r600.max_gs_threads = 4; 1602 rdev->config.r600.sx_max_export_size = 128; 1603 rdev->config.r600.sx_max_export_pos_size = 16; 1604 rdev->config.r600.sx_max_export_smx_size = 128; 1605 rdev->config.r600.sq_num_cf_insts = 2; 1606 break; 1607 case CHIP_RV610: 1608 case CHIP_RV620: 1609 case CHIP_RS780: 1610 case CHIP_RS880: 1611 rdev->config.r600.max_pipes = 1; 1612 rdev->config.r600.max_tile_pipes = 1; 1613 rdev->config.r600.max_simds = 2; 1614 rdev->config.r600.max_backends = 1; 1615 rdev->config.r600.max_gprs = 128; 1616 rdev->config.r600.max_threads = 192; 1617 rdev->config.r600.max_stack_entries = 128; 1618 rdev->config.r600.max_hw_contexts = 4; 1619 rdev->config.r600.max_gs_threads = 4; 1620 rdev->config.r600.sx_max_export_size = 128; 1621 rdev->config.r600.sx_max_export_pos_size = 16; 1622 rdev->config.r600.sx_max_export_smx_size = 128; 1623 rdev->config.r600.sq_num_cf_insts = 1; 1624 break; 1625 case CHIP_RV670: 1626 rdev->config.r600.max_pipes = 4; 1627 rdev->config.r600.max_tile_pipes = 4; 1628 rdev->config.r600.max_simds = 4; 1629 rdev->config.r600.max_backends = 4; 1630 rdev->config.r600.max_gprs = 192; 1631 rdev->config.r600.max_threads = 192; 1632 rdev->config.r600.max_stack_entries = 256; 1633 rdev->config.r600.max_hw_contexts = 8; 1634 rdev->config.r600.max_gs_threads = 16; 1635 rdev->config.r600.sx_max_export_size = 128; 1636 rdev->config.r600.sx_max_export_pos_size = 16; 1637 rdev->config.r600.sx_max_export_smx_size = 128; 1638 rdev->config.r600.sq_num_cf_insts = 2; 1639 break; 1640 default: 1641 break; 1642 } 1643 1644 /* Initialize HDP */ 1645 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 1646 WREG32((0x2c14 + j), 0x00000000); 1647 WREG32((0x2c18 + j), 0x00000000); 1648 WREG32((0x2c1c + j), 0x00000000); 1649 WREG32((0x2c20 + j), 0x00000000); 1650 WREG32((0x2c24 + j), 0x00000000); 1651 } 1652 1653 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); 1654 1655 /* Setup tiling */ 1656 tiling_config = 0; 1657 ramcfg = RREG32(RAMCFG); 1658 switch (rdev->config.r600.max_tile_pipes) { 1659 case 1: 1660 tiling_config |= PIPE_TILING(0); 1661 break; 1662 case 2: 1663 tiling_config |= PIPE_TILING(1); 1664 break; 1665 case 4: 1666 tiling_config |= PIPE_TILING(2); 1667 break; 1668 case 8: 1669 tiling_config |= PIPE_TILING(3); 1670 break; 1671 default: 1672 break; 1673 } 1674 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes; 1675 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); 1676 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); 1677 tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT); 1678 if ((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT) 1679 rdev->config.r600.tiling_group_size = 512; 1680 else 1681 rdev->config.r600.tiling_group_size = 256; 1682 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT; 1683 if (tmp > 3) { 1684 tiling_config |= ROW_TILING(3); 1685 tiling_config |= SAMPLE_SPLIT(3); 1686 } else { 1687 tiling_config |= ROW_TILING(tmp); 1688 tiling_config |= SAMPLE_SPLIT(tmp); 1689 } 1690 tiling_config |= BANK_SWAPS(1); 1691 1692 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000; 1693 cc_rb_backend_disable |= 1694 BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK); 1695 1696 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00; 1697 cc_gc_shader_pipe_config |= 1698 INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK); 1699 cc_gc_shader_pipe_config |= 1700 INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK); 1701 1702 backend_map = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes, 1703 (R6XX_MAX_BACKENDS - 1704 r600_count_pipe_bits((cc_rb_backend_disable & 1705 R6XX_MAX_BACKENDS_MASK) >> 16)), 1706 (cc_rb_backend_disable >> 16)); 1707 rdev->config.r600.tile_config = tiling_config; 1708 rdev->config.r600.backend_map = backend_map; 1709 tiling_config |= BACKEND_MAP(backend_map); 1710 WREG32(GB_TILING_CONFIG, tiling_config); 1711 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff); 1712 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff); 1713 1714 /* Setup pipes */ 1715 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); 1716 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 1717 WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 1718 1719 tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8); 1720 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK); 1721 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK); 1722 1723 /* Setup some CP states */ 1724 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b))); 1725 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40))); 1726 1727 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT | 1728 SYNC_WALKER | SYNC_ALIGNER)); 1729 /* Setup various GPU states */ 1730 if (rdev->family == CHIP_RV670) 1731 WREG32(ARB_GDEC_RD_CNTL, 0x00000021); 1732 1733 tmp = RREG32(SX_DEBUG_1); 1734 tmp |= SMX_EVENT_RELEASE; 1735 if ((rdev->family > CHIP_R600)) 1736 tmp |= ENABLE_NEW_SMX_ADDRESS; 1737 WREG32(SX_DEBUG_1, tmp); 1738 1739 if (((rdev->family) == CHIP_R600) || 1740 ((rdev->family) == CHIP_RV630) || 1741 ((rdev->family) == CHIP_RV610) || 1742 ((rdev->family) == CHIP_RV620) || 1743 ((rdev->family) == CHIP_RS780) || 1744 ((rdev->family) == CHIP_RS880)) { 1745 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE); 1746 } else { 1747 WREG32(DB_DEBUG, 0); 1748 } 1749 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) | 1750 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4))); 1751 1752 WREG32(PA_SC_MULTI_CHIP_CNTL, 0); 1753 WREG32(VGT_NUM_INSTANCES, 0); 1754 1755 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0)); 1756 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0)); 1757 1758 tmp = RREG32(SQ_MS_FIFO_SIZES); 1759 if (((rdev->family) == CHIP_RV610) || 1760 ((rdev->family) == CHIP_RV620) || 1761 ((rdev->family) == CHIP_RS780) || 1762 ((rdev->family) == CHIP_RS880)) { 1763 tmp = (CACHE_FIFO_SIZE(0xa) | 1764 FETCH_FIFO_HIWATER(0xa) | 1765 DONE_FIFO_HIWATER(0xe0) | 1766 ALU_UPDATE_FIFO_HIWATER(0x8)); 1767 } else if (((rdev->family) == CHIP_R600) || 1768 ((rdev->family) == CHIP_RV630)) { 1769 tmp &= ~DONE_FIFO_HIWATER(0xff); 1770 tmp |= DONE_FIFO_HIWATER(0x4); 1771 } 1772 WREG32(SQ_MS_FIFO_SIZES, tmp); 1773 1774 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT 1775 * should be adjusted as needed by the 2D/3D drivers. This just sets default values 1776 */ 1777 sq_config = RREG32(SQ_CONFIG); 1778 sq_config &= ~(PS_PRIO(3) | 1779 VS_PRIO(3) | 1780 GS_PRIO(3) | 1781 ES_PRIO(3)); 1782 sq_config |= (DX9_CONSTS | 1783 VC_ENABLE | 1784 PS_PRIO(0) | 1785 VS_PRIO(1) | 1786 GS_PRIO(2) | 1787 ES_PRIO(3)); 1788 1789 if ((rdev->family) == CHIP_R600) { 1790 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) | 1791 NUM_VS_GPRS(124) | 1792 NUM_CLAUSE_TEMP_GPRS(4)); 1793 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) | 1794 NUM_ES_GPRS(0)); 1795 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) | 1796 NUM_VS_THREADS(48) | 1797 NUM_GS_THREADS(4) | 1798 NUM_ES_THREADS(4)); 1799 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) | 1800 NUM_VS_STACK_ENTRIES(128)); 1801 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) | 1802 NUM_ES_STACK_ENTRIES(0)); 1803 } else if (((rdev->family) == CHIP_RV610) || 1804 ((rdev->family) == CHIP_RV620) || 1805 ((rdev->family) == CHIP_RS780) || 1806 ((rdev->family) == CHIP_RS880)) { 1807 /* no vertex cache */ 1808 sq_config &= ~VC_ENABLE; 1809 1810 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | 1811 NUM_VS_GPRS(44) | 1812 NUM_CLAUSE_TEMP_GPRS(2)); 1813 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | 1814 NUM_ES_GPRS(17)); 1815 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | 1816 NUM_VS_THREADS(78) | 1817 NUM_GS_THREADS(4) | 1818 NUM_ES_THREADS(31)); 1819 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | 1820 NUM_VS_STACK_ENTRIES(40)); 1821 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | 1822 NUM_ES_STACK_ENTRIES(16)); 1823 } else if (((rdev->family) == CHIP_RV630) || 1824 ((rdev->family) == CHIP_RV635)) { 1825 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | 1826 NUM_VS_GPRS(44) | 1827 NUM_CLAUSE_TEMP_GPRS(2)); 1828 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) | 1829 NUM_ES_GPRS(18)); 1830 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | 1831 NUM_VS_THREADS(78) | 1832 NUM_GS_THREADS(4) | 1833 NUM_ES_THREADS(31)); 1834 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | 1835 NUM_VS_STACK_ENTRIES(40)); 1836 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | 1837 NUM_ES_STACK_ENTRIES(16)); 1838 } else if ((rdev->family) == CHIP_RV670) { 1839 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | 1840 NUM_VS_GPRS(44) | 1841 NUM_CLAUSE_TEMP_GPRS(2)); 1842 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | 1843 NUM_ES_GPRS(17)); 1844 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | 1845 NUM_VS_THREADS(78) | 1846 NUM_GS_THREADS(4) | 1847 NUM_ES_THREADS(31)); 1848 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) | 1849 NUM_VS_STACK_ENTRIES(64)); 1850 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) | 1851 NUM_ES_STACK_ENTRIES(64)); 1852 } 1853 1854 WREG32(SQ_CONFIG, sq_config); 1855 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1); 1856 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2); 1857 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); 1858 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1); 1859 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2); 1860 1861 if (((rdev->family) == CHIP_RV610) || 1862 ((rdev->family) == CHIP_RV620) || 1863 ((rdev->family) == CHIP_RS780) || 1864 ((rdev->family) == CHIP_RS880)) { 1865 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY)); 1866 } else { 1867 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC)); 1868 } 1869 1870 /* More default values. 2D/3D driver should adjust as needed */ 1871 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) | 1872 S1_X(0x4) | S1_Y(0xc))); 1873 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) | 1874 S1_X(0x2) | S1_Y(0x2) | 1875 S2_X(0xa) | S2_Y(0x6) | 1876 S3_X(0x6) | S3_Y(0xa))); 1877 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) | 1878 S1_X(0x4) | S1_Y(0xc) | 1879 S2_X(0x1) | S2_Y(0x6) | 1880 S3_X(0xa) | S3_Y(0xe))); 1881 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) | 1882 S5_X(0x0) | S5_Y(0x0) | 1883 S6_X(0xb) | S6_Y(0x4) | 1884 S7_X(0x7) | S7_Y(0x8))); 1885 1886 WREG32(VGT_STRMOUT_EN, 0); 1887 tmp = rdev->config.r600.max_pipes * 16; 1888 switch (rdev->family) { 1889 case CHIP_RV610: 1890 case CHIP_RV620: 1891 case CHIP_RS780: 1892 case CHIP_RS880: 1893 tmp += 32; 1894 break; 1895 case CHIP_RV670: 1896 tmp += 128; 1897 break; 1898 default: 1899 break; 1900 } 1901 if (tmp > 256) { 1902 tmp = 256; 1903 } 1904 WREG32(VGT_ES_PER_GS, 128); 1905 WREG32(VGT_GS_PER_ES, tmp); 1906 WREG32(VGT_GS_PER_VS, 2); 1907 WREG32(VGT_GS_VERTEX_REUSE, 16); 1908 1909 /* more default values. 2D/3D driver should adjust as needed */ 1910 WREG32(PA_SC_LINE_STIPPLE_STATE, 0); 1911 WREG32(VGT_STRMOUT_EN, 0); 1912 WREG32(SX_MISC, 0); 1913 WREG32(PA_SC_MODE_CNTL, 0); 1914 WREG32(PA_SC_AA_CONFIG, 0); 1915 WREG32(PA_SC_LINE_STIPPLE, 0); 1916 WREG32(SPI_INPUT_Z, 0); 1917 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2)); 1918 WREG32(CB_COLOR7_FRAG, 0); 1919 1920 /* Clear render buffer base addresses */ 1921 WREG32(CB_COLOR0_BASE, 0); 1922 WREG32(CB_COLOR1_BASE, 0); 1923 WREG32(CB_COLOR2_BASE, 0); 1924 WREG32(CB_COLOR3_BASE, 0); 1925 WREG32(CB_COLOR4_BASE, 0); 1926 WREG32(CB_COLOR5_BASE, 0); 1927 WREG32(CB_COLOR6_BASE, 0); 1928 WREG32(CB_COLOR7_BASE, 0); 1929 WREG32(CB_COLOR7_FRAG, 0); 1930 1931 switch (rdev->family) { 1932 case CHIP_RV610: 1933 case CHIP_RV620: 1934 case CHIP_RS780: 1935 case CHIP_RS880: 1936 tmp = TC_L2_SIZE(8); 1937 break; 1938 case CHIP_RV630: 1939 case CHIP_RV635: 1940 tmp = TC_L2_SIZE(4); 1941 break; 1942 case CHIP_R600: 1943 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT; 1944 break; 1945 default: 1946 tmp = TC_L2_SIZE(0); 1947 break; 1948 } 1949 WREG32(TC_CNTL, tmp); 1950 1951 tmp = RREG32(HDP_HOST_PATH_CNTL); 1952 WREG32(HDP_HOST_PATH_CNTL, tmp); 1953 1954 tmp = RREG32(ARB_POP); 1955 tmp |= ENABLE_TC128; 1956 WREG32(ARB_POP, tmp); 1957 1958 WREG32(PA_SC_MULTI_CHIP_CNTL, 0); 1959 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | 1960 NUM_CLIP_SEQ(3))); 1961 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095)); 1962 } 1963 1964 1965 /* 1966 * Indirect registers accessor 1967 */ 1968 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg) 1969 { 1970 u32 r; 1971 1972 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); 1973 (void)RREG32(PCIE_PORT_INDEX); 1974 r = RREG32(PCIE_PORT_DATA); 1975 return r; 1976 } 1977 1978 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v) 1979 { 1980 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); 1981 (void)RREG32(PCIE_PORT_INDEX); 1982 WREG32(PCIE_PORT_DATA, (v)); 1983 (void)RREG32(PCIE_PORT_DATA); 1984 } 1985 1986 /* 1987 * CP & Ring 1988 */ 1989 void r600_cp_stop(struct radeon_device *rdev) 1990 { 1991 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 1992 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); 1993 WREG32(SCRATCH_UMSK, 0); 1994 } 1995 1996 int r600_init_microcode(struct radeon_device *rdev) 1997 { 1998 struct platform_device *pdev; 1999 const char *chip_name; 2000 const char *rlc_chip_name; 2001 size_t pfp_req_size, me_req_size, rlc_req_size; 2002 char fw_name[30]; 2003 int err; 2004 2005 DRM_DEBUG("\n"); 2006 2007 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0); 2008 err = IS_ERR(pdev); 2009 if (err) { 2010 printk(KERN_ERR "radeon_cp: Failed to register firmware\n"); 2011 return -EINVAL; 2012 } 2013 2014 switch (rdev->family) { 2015 case CHIP_R600: 2016 chip_name = "R600"; 2017 rlc_chip_name = "R600"; 2018 break; 2019 case CHIP_RV610: 2020 chip_name = "RV610"; 2021 rlc_chip_name = "R600"; 2022 break; 2023 case CHIP_RV630: 2024 chip_name = "RV630"; 2025 rlc_chip_name = "R600"; 2026 break; 2027 case CHIP_RV620: 2028 chip_name = "RV620"; 2029 rlc_chip_name = "R600"; 2030 break; 2031 case CHIP_RV635: 2032 chip_name = "RV635"; 2033 rlc_chip_name = "R600"; 2034 break; 2035 case CHIP_RV670: 2036 chip_name = "RV670"; 2037 rlc_chip_name = "R600"; 2038 break; 2039 case CHIP_RS780: 2040 case CHIP_RS880: 2041 chip_name = "RS780"; 2042 rlc_chip_name = "R600"; 2043 break; 2044 case CHIP_RV770: 2045 chip_name = "RV770"; 2046 rlc_chip_name = "R700"; 2047 break; 2048 case CHIP_RV730: 2049 case CHIP_RV740: 2050 chip_name = "RV730"; 2051 rlc_chip_name = "R700"; 2052 break; 2053 case CHIP_RV710: 2054 chip_name = "RV710"; 2055 rlc_chip_name = "R700"; 2056 break; 2057 case CHIP_CEDAR: 2058 chip_name = "CEDAR"; 2059 rlc_chip_name = "CEDAR"; 2060 break; 2061 case CHIP_REDWOOD: 2062 chip_name = "REDWOOD"; 2063 rlc_chip_name = "REDWOOD"; 2064 break; 2065 case CHIP_JUNIPER: 2066 chip_name = "JUNIPER"; 2067 rlc_chip_name = "JUNIPER"; 2068 break; 2069 case CHIP_CYPRESS: 2070 case CHIP_HEMLOCK: 2071 chip_name = "CYPRESS"; 2072 rlc_chip_name = "CYPRESS"; 2073 break; 2074 case CHIP_PALM: 2075 chip_name = "PALM"; 2076 rlc_chip_name = "SUMO"; 2077 break; 2078 case CHIP_SUMO: 2079 chip_name = "SUMO"; 2080 rlc_chip_name = "SUMO"; 2081 break; 2082 case CHIP_SUMO2: 2083 chip_name = "SUMO2"; 2084 rlc_chip_name = "SUMO"; 2085 break; 2086 default: BUG(); 2087 } 2088 2089 if (rdev->family >= CHIP_CEDAR) { 2090 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4; 2091 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4; 2092 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4; 2093 } else if (rdev->family >= CHIP_RV770) { 2094 pfp_req_size = R700_PFP_UCODE_SIZE * 4; 2095 me_req_size = R700_PM4_UCODE_SIZE * 4; 2096 rlc_req_size = R700_RLC_UCODE_SIZE * 4; 2097 } else { 2098 pfp_req_size = PFP_UCODE_SIZE * 4; 2099 me_req_size = PM4_UCODE_SIZE * 12; 2100 rlc_req_size = RLC_UCODE_SIZE * 4; 2101 } 2102 2103 DRM_INFO("Loading %s Microcode\n", chip_name); 2104 2105 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name); 2106 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev); 2107 if (err) 2108 goto out; 2109 if (rdev->pfp_fw->size != pfp_req_size) { 2110 printk(KERN_ERR 2111 "r600_cp: Bogus length %zu in firmware \"%s\"\n", 2112 rdev->pfp_fw->size, fw_name); 2113 err = -EINVAL; 2114 goto out; 2115 } 2116 2117 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name); 2118 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev); 2119 if (err) 2120 goto out; 2121 if (rdev->me_fw->size != me_req_size) { 2122 printk(KERN_ERR 2123 "r600_cp: Bogus length %zu in firmware \"%s\"\n", 2124 rdev->me_fw->size, fw_name); 2125 err = -EINVAL; 2126 } 2127 2128 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name); 2129 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev); 2130 if (err) 2131 goto out; 2132 if (rdev->rlc_fw->size != rlc_req_size) { 2133 printk(KERN_ERR 2134 "r600_rlc: Bogus length %zu in firmware \"%s\"\n", 2135 rdev->rlc_fw->size, fw_name); 2136 err = -EINVAL; 2137 } 2138 2139 out: 2140 platform_device_unregister(pdev); 2141 2142 if (err) { 2143 if (err != -EINVAL) 2144 printk(KERN_ERR 2145 "r600_cp: Failed to load firmware \"%s\"\n", 2146 fw_name); 2147 release_firmware(rdev->pfp_fw); 2148 rdev->pfp_fw = NULL; 2149 release_firmware(rdev->me_fw); 2150 rdev->me_fw = NULL; 2151 release_firmware(rdev->rlc_fw); 2152 rdev->rlc_fw = NULL; 2153 } 2154 return err; 2155 } 2156 2157 static int r600_cp_load_microcode(struct radeon_device *rdev) 2158 { 2159 const __be32 *fw_data; 2160 int i; 2161 2162 if (!rdev->me_fw || !rdev->pfp_fw) 2163 return -EINVAL; 2164 2165 r600_cp_stop(rdev); 2166 2167 WREG32(CP_RB_CNTL, 2168 #ifdef __BIG_ENDIAN 2169 BUF_SWAP_32BIT | 2170 #endif 2171 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); 2172 2173 /* Reset cp */ 2174 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); 2175 RREG32(GRBM_SOFT_RESET); 2176 mdelay(15); 2177 WREG32(GRBM_SOFT_RESET, 0); 2178 2179 WREG32(CP_ME_RAM_WADDR, 0); 2180 2181 fw_data = (const __be32 *)rdev->me_fw->data; 2182 WREG32(CP_ME_RAM_WADDR, 0); 2183 for (i = 0; i < PM4_UCODE_SIZE * 3; i++) 2184 WREG32(CP_ME_RAM_DATA, 2185 be32_to_cpup(fw_data++)); 2186 2187 fw_data = (const __be32 *)rdev->pfp_fw->data; 2188 WREG32(CP_PFP_UCODE_ADDR, 0); 2189 for (i = 0; i < PFP_UCODE_SIZE; i++) 2190 WREG32(CP_PFP_UCODE_DATA, 2191 be32_to_cpup(fw_data++)); 2192 2193 WREG32(CP_PFP_UCODE_ADDR, 0); 2194 WREG32(CP_ME_RAM_WADDR, 0); 2195 WREG32(CP_ME_RAM_RADDR, 0); 2196 return 0; 2197 } 2198 2199 int r600_cp_start(struct radeon_device *rdev) 2200 { 2201 int r; 2202 uint32_t cp_me; 2203 2204 r = radeon_ring_lock(rdev, 7); 2205 if (r) { 2206 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 2207 return r; 2208 } 2209 radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5)); 2210 radeon_ring_write(rdev, 0x1); 2211 if (rdev->family >= CHIP_RV770) { 2212 radeon_ring_write(rdev, 0x0); 2213 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1); 2214 } else { 2215 radeon_ring_write(rdev, 0x3); 2216 radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1); 2217 } 2218 radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); 2219 radeon_ring_write(rdev, 0); 2220 radeon_ring_write(rdev, 0); 2221 radeon_ring_unlock_commit(rdev); 2222 2223 cp_me = 0xff; 2224 WREG32(R_0086D8_CP_ME_CNTL, cp_me); 2225 return 0; 2226 } 2227 2228 int r600_cp_resume(struct radeon_device *rdev) 2229 { 2230 u32 tmp; 2231 u32 rb_bufsz; 2232 int r; 2233 2234 /* Reset cp */ 2235 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); 2236 RREG32(GRBM_SOFT_RESET); 2237 mdelay(15); 2238 WREG32(GRBM_SOFT_RESET, 0); 2239 2240 /* Set ring buffer size */ 2241 rb_bufsz = drm_order(rdev->cp.ring_size / 8); 2242 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2243 #ifdef __BIG_ENDIAN 2244 tmp |= BUF_SWAP_32BIT; 2245 #endif 2246 WREG32(CP_RB_CNTL, tmp); 2247 WREG32(CP_SEM_WAIT_TIMER, 0x4); 2248 2249 /* Set the write pointer delay */ 2250 WREG32(CP_RB_WPTR_DELAY, 0); 2251 2252 /* Initialize the ring buffer's read and write pointers */ 2253 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); 2254 WREG32(CP_RB_RPTR_WR, 0); 2255 rdev->cp.wptr = 0; 2256 WREG32(CP_RB_WPTR, rdev->cp.wptr); 2257 2258 /* set the wb address whether it's enabled or not */ 2259 WREG32(CP_RB_RPTR_ADDR, 2260 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC)); 2261 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); 2262 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); 2263 2264 if (rdev->wb.enabled) 2265 WREG32(SCRATCH_UMSK, 0xff); 2266 else { 2267 tmp |= RB_NO_UPDATE; 2268 WREG32(SCRATCH_UMSK, 0); 2269 } 2270 2271 mdelay(1); 2272 WREG32(CP_RB_CNTL, tmp); 2273 2274 WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8); 2275 WREG32(CP_DEBUG, (1 << 27) | (1 << 28)); 2276 2277 rdev->cp.rptr = RREG32(CP_RB_RPTR); 2278 2279 r600_cp_start(rdev); 2280 rdev->cp.ready = true; 2281 r = radeon_ring_test(rdev); 2282 if (r) { 2283 rdev->cp.ready = false; 2284 return r; 2285 } 2286 return 0; 2287 } 2288 2289 void r600_cp_commit(struct radeon_device *rdev) 2290 { 2291 WREG32(CP_RB_WPTR, rdev->cp.wptr); 2292 (void)RREG32(CP_RB_WPTR); 2293 } 2294 2295 void r600_ring_init(struct radeon_device *rdev, unsigned ring_size) 2296 { 2297 u32 rb_bufsz; 2298 2299 /* Align ring size */ 2300 rb_bufsz = drm_order(ring_size / 8); 2301 ring_size = (1 << (rb_bufsz + 1)) * 4; 2302 rdev->cp.ring_size = ring_size; 2303 rdev->cp.align_mask = 16 - 1; 2304 } 2305 2306 void r600_cp_fini(struct radeon_device *rdev) 2307 { 2308 r600_cp_stop(rdev); 2309 radeon_ring_fini(rdev); 2310 } 2311 2312 2313 /* 2314 * GPU scratch registers helpers function. 2315 */ 2316 void r600_scratch_init(struct radeon_device *rdev) 2317 { 2318 int i; 2319 2320 rdev->scratch.num_reg = 7; 2321 rdev->scratch.reg_base = SCRATCH_REG0; 2322 for (i = 0; i < rdev->scratch.num_reg; i++) { 2323 rdev->scratch.free[i] = true; 2324 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); 2325 } 2326 } 2327 2328 int r600_ring_test(struct radeon_device *rdev) 2329 { 2330 uint32_t scratch; 2331 uint32_t tmp = 0; 2332 unsigned i; 2333 int r; 2334 2335 r = radeon_scratch_get(rdev, &scratch); 2336 if (r) { 2337 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); 2338 return r; 2339 } 2340 WREG32(scratch, 0xCAFEDEAD); 2341 r = radeon_ring_lock(rdev, 3); 2342 if (r) { 2343 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 2344 radeon_scratch_free(rdev, scratch); 2345 return r; 2346 } 2347 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2348 radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); 2349 radeon_ring_write(rdev, 0xDEADBEEF); 2350 radeon_ring_unlock_commit(rdev); 2351 for (i = 0; i < rdev->usec_timeout; i++) { 2352 tmp = RREG32(scratch); 2353 if (tmp == 0xDEADBEEF) 2354 break; 2355 DRM_UDELAY(1); 2356 } 2357 if (i < rdev->usec_timeout) { 2358 DRM_INFO("ring test succeeded in %d usecs\n", i); 2359 } else { 2360 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n", 2361 scratch, tmp); 2362 r = -EINVAL; 2363 } 2364 radeon_scratch_free(rdev, scratch); 2365 return r; 2366 } 2367 2368 void r600_fence_ring_emit(struct radeon_device *rdev, 2369 struct radeon_fence *fence) 2370 { 2371 if (rdev->wb.use_event) { 2372 u64 addr = rdev->wb.gpu_addr + R600_WB_EVENT_OFFSET + 2373 (u64)(rdev->fence_drv.scratch_reg - rdev->scratch.reg_base); 2374 /* flush read cache over gart */ 2375 radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_SYNC, 3)); 2376 radeon_ring_write(rdev, PACKET3_TC_ACTION_ENA | 2377 PACKET3_VC_ACTION_ENA | 2378 PACKET3_SH_ACTION_ENA); 2379 radeon_ring_write(rdev, 0xFFFFFFFF); 2380 radeon_ring_write(rdev, 0); 2381 radeon_ring_write(rdev, 10); /* poll interval */ 2382 /* EVENT_WRITE_EOP - flush caches, send int */ 2383 radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 2384 radeon_ring_write(rdev, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5)); 2385 radeon_ring_write(rdev, addr & 0xffffffff); 2386 radeon_ring_write(rdev, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); 2387 radeon_ring_write(rdev, fence->seq); 2388 radeon_ring_write(rdev, 0); 2389 } else { 2390 /* flush read cache over gart */ 2391 radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_SYNC, 3)); 2392 radeon_ring_write(rdev, PACKET3_TC_ACTION_ENA | 2393 PACKET3_VC_ACTION_ENA | 2394 PACKET3_SH_ACTION_ENA); 2395 radeon_ring_write(rdev, 0xFFFFFFFF); 2396 radeon_ring_write(rdev, 0); 2397 radeon_ring_write(rdev, 10); /* poll interval */ 2398 radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0)); 2399 radeon_ring_write(rdev, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0)); 2400 /* wait for 3D idle clean */ 2401 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2402 radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 2403 radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit); 2404 /* Emit fence sequence & fire IRQ */ 2405 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2406 radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); 2407 radeon_ring_write(rdev, fence->seq); 2408 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */ 2409 radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0)); 2410 radeon_ring_write(rdev, RB_INT_STAT); 2411 } 2412 } 2413 2414 int r600_copy_blit(struct radeon_device *rdev, 2415 uint64_t src_offset, 2416 uint64_t dst_offset, 2417 unsigned num_gpu_pages, 2418 struct radeon_fence *fence) 2419 { 2420 int r; 2421 2422 mutex_lock(&rdev->r600_blit.mutex); 2423 rdev->r600_blit.vb_ib = NULL; 2424 r = r600_blit_prepare_copy(rdev, num_gpu_pages); 2425 if (r) { 2426 if (rdev->r600_blit.vb_ib) 2427 radeon_ib_free(rdev, &rdev->r600_blit.vb_ib); 2428 mutex_unlock(&rdev->r600_blit.mutex); 2429 return r; 2430 } 2431 r600_kms_blit_copy(rdev, src_offset, dst_offset, num_gpu_pages); 2432 r600_blit_done_copy(rdev, fence); 2433 mutex_unlock(&rdev->r600_blit.mutex); 2434 return 0; 2435 } 2436 2437 void r600_blit_suspend(struct radeon_device *rdev) 2438 { 2439 int r; 2440 2441 /* unpin shaders bo */ 2442 if (rdev->r600_blit.shader_obj) { 2443 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); 2444 if (!r) { 2445 radeon_bo_unpin(rdev->r600_blit.shader_obj); 2446 radeon_bo_unreserve(rdev->r600_blit.shader_obj); 2447 } 2448 } 2449 } 2450 2451 int r600_set_surface_reg(struct radeon_device *rdev, int reg, 2452 uint32_t tiling_flags, uint32_t pitch, 2453 uint32_t offset, uint32_t obj_size) 2454 { 2455 /* FIXME: implement */ 2456 return 0; 2457 } 2458 2459 void r600_clear_surface_reg(struct radeon_device *rdev, int reg) 2460 { 2461 /* FIXME: implement */ 2462 } 2463 2464 int r600_startup(struct radeon_device *rdev) 2465 { 2466 int r; 2467 2468 /* enable pcie gen2 link */ 2469 r600_pcie_gen2_enable(rdev); 2470 2471 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { 2472 r = r600_init_microcode(rdev); 2473 if (r) { 2474 DRM_ERROR("Failed to load firmware!\n"); 2475 return r; 2476 } 2477 } 2478 2479 r = r600_vram_scratch_init(rdev); 2480 if (r) 2481 return r; 2482 2483 r600_mc_program(rdev); 2484 if (rdev->flags & RADEON_IS_AGP) { 2485 r600_agp_enable(rdev); 2486 } else { 2487 r = r600_pcie_gart_enable(rdev); 2488 if (r) 2489 return r; 2490 } 2491 r600_gpu_init(rdev); 2492 r = r600_blit_init(rdev); 2493 if (r) { 2494 r600_blit_fini(rdev); 2495 rdev->asic->copy = NULL; 2496 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); 2497 } 2498 2499 /* allocate wb buffer */ 2500 r = radeon_wb_init(rdev); 2501 if (r) 2502 return r; 2503 2504 /* Enable IRQ */ 2505 r = r600_irq_init(rdev); 2506 if (r) { 2507 DRM_ERROR("radeon: IH init failed (%d).\n", r); 2508 radeon_irq_kms_fini(rdev); 2509 return r; 2510 } 2511 r600_irq_set(rdev); 2512 2513 r = radeon_ring_init(rdev, rdev->cp.ring_size); 2514 if (r) 2515 return r; 2516 r = r600_cp_load_microcode(rdev); 2517 if (r) 2518 return r; 2519 r = r600_cp_resume(rdev); 2520 if (r) 2521 return r; 2522 2523 return 0; 2524 } 2525 2526 void r600_vga_set_state(struct radeon_device *rdev, bool state) 2527 { 2528 uint32_t temp; 2529 2530 temp = RREG32(CONFIG_CNTL); 2531 if (state == false) { 2532 temp &= ~(1<<0); 2533 temp |= (1<<1); 2534 } else { 2535 temp &= ~(1<<1); 2536 } 2537 WREG32(CONFIG_CNTL, temp); 2538 } 2539 2540 int r600_resume(struct radeon_device *rdev) 2541 { 2542 int r; 2543 2544 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw, 2545 * posting will perform necessary task to bring back GPU into good 2546 * shape. 2547 */ 2548 /* post card */ 2549 atom_asic_init(rdev->mode_info.atom_context); 2550 2551 r = r600_startup(rdev); 2552 if (r) { 2553 DRM_ERROR("r600 startup failed on resume\n"); 2554 return r; 2555 } 2556 2557 r = r600_ib_test(rdev); 2558 if (r) { 2559 DRM_ERROR("radeon: failed testing IB (%d).\n", r); 2560 return r; 2561 } 2562 2563 r = r600_audio_init(rdev); 2564 if (r) { 2565 DRM_ERROR("radeon: audio resume failed\n"); 2566 return r; 2567 } 2568 2569 return r; 2570 } 2571 2572 int r600_suspend(struct radeon_device *rdev) 2573 { 2574 r600_audio_fini(rdev); 2575 /* FIXME: we should wait for ring to be empty */ 2576 r600_cp_stop(rdev); 2577 rdev->cp.ready = false; 2578 r600_irq_suspend(rdev); 2579 radeon_wb_disable(rdev); 2580 r600_pcie_gart_disable(rdev); 2581 r600_blit_suspend(rdev); 2582 2583 return 0; 2584 } 2585 2586 /* Plan is to move initialization in that function and use 2587 * helper function so that radeon_device_init pretty much 2588 * do nothing more than calling asic specific function. This 2589 * should also allow to remove a bunch of callback function 2590 * like vram_info. 2591 */ 2592 int r600_init(struct radeon_device *rdev) 2593 { 2594 int r; 2595 2596 if (r600_debugfs_mc_info_init(rdev)) { 2597 DRM_ERROR("Failed to register debugfs file for mc !\n"); 2598 } 2599 /* This don't do much */ 2600 r = radeon_gem_init(rdev); 2601 if (r) 2602 return r; 2603 /* Read BIOS */ 2604 if (!radeon_get_bios(rdev)) { 2605 if (ASIC_IS_AVIVO(rdev)) 2606 return -EINVAL; 2607 } 2608 /* Must be an ATOMBIOS */ 2609 if (!rdev->is_atom_bios) { 2610 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n"); 2611 return -EINVAL; 2612 } 2613 r = radeon_atombios_init(rdev); 2614 if (r) 2615 return r; 2616 /* Post card if necessary */ 2617 if (!radeon_card_posted(rdev)) { 2618 if (!rdev->bios) { 2619 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); 2620 return -EINVAL; 2621 } 2622 DRM_INFO("GPU not posted. posting now...\n"); 2623 atom_asic_init(rdev->mode_info.atom_context); 2624 } 2625 /* Initialize scratch registers */ 2626 r600_scratch_init(rdev); 2627 /* Initialize surface registers */ 2628 radeon_surface_init(rdev); 2629 /* Initialize clocks */ 2630 radeon_get_clock_info(rdev->ddev); 2631 /* Fence driver */ 2632 r = radeon_fence_driver_init(rdev); 2633 if (r) 2634 return r; 2635 if (rdev->flags & RADEON_IS_AGP) { 2636 r = radeon_agp_init(rdev); 2637 if (r) 2638 radeon_agp_disable(rdev); 2639 } 2640 r = r600_mc_init(rdev); 2641 if (r) 2642 return r; 2643 /* Memory manager */ 2644 r = radeon_bo_init(rdev); 2645 if (r) 2646 return r; 2647 2648 r = radeon_irq_kms_init(rdev); 2649 if (r) 2650 return r; 2651 2652 rdev->cp.ring_obj = NULL; 2653 r600_ring_init(rdev, 1024 * 1024); 2654 2655 rdev->ih.ring_obj = NULL; 2656 r600_ih_ring_init(rdev, 64 * 1024); 2657 2658 r = r600_pcie_gart_init(rdev); 2659 if (r) 2660 return r; 2661 2662 rdev->accel_working = true; 2663 r = r600_startup(rdev); 2664 if (r) { 2665 dev_err(rdev->dev, "disabling GPU acceleration\n"); 2666 r600_cp_fini(rdev); 2667 r600_irq_fini(rdev); 2668 radeon_wb_fini(rdev); 2669 radeon_irq_kms_fini(rdev); 2670 r600_pcie_gart_fini(rdev); 2671 rdev->accel_working = false; 2672 } 2673 if (rdev->accel_working) { 2674 r = radeon_ib_pool_init(rdev); 2675 if (r) { 2676 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 2677 rdev->accel_working = false; 2678 } else { 2679 r = r600_ib_test(rdev); 2680 if (r) { 2681 dev_err(rdev->dev, "IB test failed (%d).\n", r); 2682 rdev->accel_working = false; 2683 } 2684 } 2685 } 2686 2687 r = r600_audio_init(rdev); 2688 if (r) 2689 return r; /* TODO error handling */ 2690 return 0; 2691 } 2692 2693 void r600_fini(struct radeon_device *rdev) 2694 { 2695 r600_audio_fini(rdev); 2696 r600_blit_fini(rdev); 2697 r600_cp_fini(rdev); 2698 r600_irq_fini(rdev); 2699 radeon_wb_fini(rdev); 2700 radeon_ib_pool_fini(rdev); 2701 radeon_irq_kms_fini(rdev); 2702 r600_pcie_gart_fini(rdev); 2703 r600_vram_scratch_fini(rdev); 2704 radeon_agp_fini(rdev); 2705 radeon_gem_fini(rdev); 2706 radeon_fence_driver_fini(rdev); 2707 radeon_bo_fini(rdev); 2708 radeon_atombios_fini(rdev); 2709 kfree(rdev->bios); 2710 rdev->bios = NULL; 2711 } 2712 2713 2714 /* 2715 * CS stuff 2716 */ 2717 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 2718 { 2719 /* FIXME: implement */ 2720 radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 2721 radeon_ring_write(rdev, 2722 #ifdef __BIG_ENDIAN 2723 (2 << 0) | 2724 #endif 2725 (ib->gpu_addr & 0xFFFFFFFC)); 2726 radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF); 2727 radeon_ring_write(rdev, ib->length_dw); 2728 } 2729 2730 int r600_ib_test(struct radeon_device *rdev) 2731 { 2732 struct radeon_ib *ib; 2733 uint32_t scratch; 2734 uint32_t tmp = 0; 2735 unsigned i; 2736 int r; 2737 2738 r = radeon_scratch_get(rdev, &scratch); 2739 if (r) { 2740 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); 2741 return r; 2742 } 2743 WREG32(scratch, 0xCAFEDEAD); 2744 r = radeon_ib_get(rdev, &ib); 2745 if (r) { 2746 DRM_ERROR("radeon: failed to get ib (%d).\n", r); 2747 return r; 2748 } 2749 ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1); 2750 ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 2751 ib->ptr[2] = 0xDEADBEEF; 2752 ib->ptr[3] = PACKET2(0); 2753 ib->ptr[4] = PACKET2(0); 2754 ib->ptr[5] = PACKET2(0); 2755 ib->ptr[6] = PACKET2(0); 2756 ib->ptr[7] = PACKET2(0); 2757 ib->ptr[8] = PACKET2(0); 2758 ib->ptr[9] = PACKET2(0); 2759 ib->ptr[10] = PACKET2(0); 2760 ib->ptr[11] = PACKET2(0); 2761 ib->ptr[12] = PACKET2(0); 2762 ib->ptr[13] = PACKET2(0); 2763 ib->ptr[14] = PACKET2(0); 2764 ib->ptr[15] = PACKET2(0); 2765 ib->length_dw = 16; 2766 r = radeon_ib_schedule(rdev, ib); 2767 if (r) { 2768 radeon_scratch_free(rdev, scratch); 2769 radeon_ib_free(rdev, &ib); 2770 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); 2771 return r; 2772 } 2773 r = radeon_fence_wait(ib->fence, false); 2774 if (r) { 2775 DRM_ERROR("radeon: fence wait failed (%d).\n", r); 2776 return r; 2777 } 2778 for (i = 0; i < rdev->usec_timeout; i++) { 2779 tmp = RREG32(scratch); 2780 if (tmp == 0xDEADBEEF) 2781 break; 2782 DRM_UDELAY(1); 2783 } 2784 if (i < rdev->usec_timeout) { 2785 DRM_INFO("ib test succeeded in %u usecs\n", i); 2786 } else { 2787 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n", 2788 scratch, tmp); 2789 r = -EINVAL; 2790 } 2791 radeon_scratch_free(rdev, scratch); 2792 radeon_ib_free(rdev, &ib); 2793 return r; 2794 } 2795 2796 /* 2797 * Interrupts 2798 * 2799 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty 2800 * the same as the CP ring buffer, but in reverse. Rather than the CPU 2801 * writing to the ring and the GPU consuming, the GPU writes to the ring 2802 * and host consumes. As the host irq handler processes interrupts, it 2803 * increments the rptr. When the rptr catches up with the wptr, all the 2804 * current interrupts have been processed. 2805 */ 2806 2807 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size) 2808 { 2809 u32 rb_bufsz; 2810 2811 /* Align ring size */ 2812 rb_bufsz = drm_order(ring_size / 4); 2813 ring_size = (1 << rb_bufsz) * 4; 2814 rdev->ih.ring_size = ring_size; 2815 rdev->ih.ptr_mask = rdev->ih.ring_size - 1; 2816 rdev->ih.rptr = 0; 2817 } 2818 2819 static int r600_ih_ring_alloc(struct radeon_device *rdev) 2820 { 2821 int r; 2822 2823 /* Allocate ring buffer */ 2824 if (rdev->ih.ring_obj == NULL) { 2825 r = radeon_bo_create(rdev, rdev->ih.ring_size, 2826 PAGE_SIZE, true, 2827 RADEON_GEM_DOMAIN_GTT, 2828 &rdev->ih.ring_obj); 2829 if (r) { 2830 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r); 2831 return r; 2832 } 2833 r = radeon_bo_reserve(rdev->ih.ring_obj, false); 2834 if (unlikely(r != 0)) 2835 return r; 2836 r = radeon_bo_pin(rdev->ih.ring_obj, 2837 RADEON_GEM_DOMAIN_GTT, 2838 &rdev->ih.gpu_addr); 2839 if (r) { 2840 radeon_bo_unreserve(rdev->ih.ring_obj); 2841 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r); 2842 return r; 2843 } 2844 r = radeon_bo_kmap(rdev->ih.ring_obj, 2845 (void **)&rdev->ih.ring); 2846 radeon_bo_unreserve(rdev->ih.ring_obj); 2847 if (r) { 2848 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r); 2849 return r; 2850 } 2851 } 2852 return 0; 2853 } 2854 2855 static void r600_ih_ring_fini(struct radeon_device *rdev) 2856 { 2857 int r; 2858 if (rdev->ih.ring_obj) { 2859 r = radeon_bo_reserve(rdev->ih.ring_obj, false); 2860 if (likely(r == 0)) { 2861 radeon_bo_kunmap(rdev->ih.ring_obj); 2862 radeon_bo_unpin(rdev->ih.ring_obj); 2863 radeon_bo_unreserve(rdev->ih.ring_obj); 2864 } 2865 radeon_bo_unref(&rdev->ih.ring_obj); 2866 rdev->ih.ring = NULL; 2867 rdev->ih.ring_obj = NULL; 2868 } 2869 } 2870 2871 void r600_rlc_stop(struct radeon_device *rdev) 2872 { 2873 2874 if ((rdev->family >= CHIP_RV770) && 2875 (rdev->family <= CHIP_RV740)) { 2876 /* r7xx asics need to soft reset RLC before halting */ 2877 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC); 2878 RREG32(SRBM_SOFT_RESET); 2879 udelay(15000); 2880 WREG32(SRBM_SOFT_RESET, 0); 2881 RREG32(SRBM_SOFT_RESET); 2882 } 2883 2884 WREG32(RLC_CNTL, 0); 2885 } 2886 2887 static void r600_rlc_start(struct radeon_device *rdev) 2888 { 2889 WREG32(RLC_CNTL, RLC_ENABLE); 2890 } 2891 2892 static int r600_rlc_init(struct radeon_device *rdev) 2893 { 2894 u32 i; 2895 const __be32 *fw_data; 2896 2897 if (!rdev->rlc_fw) 2898 return -EINVAL; 2899 2900 r600_rlc_stop(rdev); 2901 2902 WREG32(RLC_HB_BASE, 0); 2903 WREG32(RLC_HB_CNTL, 0); 2904 WREG32(RLC_HB_RPTR, 0); 2905 WREG32(RLC_HB_WPTR, 0); 2906 if (rdev->family <= CHIP_CAICOS) { 2907 WREG32(RLC_HB_WPTR_LSB_ADDR, 0); 2908 WREG32(RLC_HB_WPTR_MSB_ADDR, 0); 2909 } 2910 WREG32(RLC_MC_CNTL, 0); 2911 WREG32(RLC_UCODE_CNTL, 0); 2912 2913 fw_data = (const __be32 *)rdev->rlc_fw->data; 2914 if (rdev->family >= CHIP_CAYMAN) { 2915 for (i = 0; i < CAYMAN_RLC_UCODE_SIZE; i++) { 2916 WREG32(RLC_UCODE_ADDR, i); 2917 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); 2918 } 2919 } else if (rdev->family >= CHIP_CEDAR) { 2920 for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) { 2921 WREG32(RLC_UCODE_ADDR, i); 2922 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); 2923 } 2924 } else if (rdev->family >= CHIP_RV770) { 2925 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) { 2926 WREG32(RLC_UCODE_ADDR, i); 2927 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); 2928 } 2929 } else { 2930 for (i = 0; i < RLC_UCODE_SIZE; i++) { 2931 WREG32(RLC_UCODE_ADDR, i); 2932 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); 2933 } 2934 } 2935 WREG32(RLC_UCODE_ADDR, 0); 2936 2937 r600_rlc_start(rdev); 2938 2939 return 0; 2940 } 2941 2942 static void r600_enable_interrupts(struct radeon_device *rdev) 2943 { 2944 u32 ih_cntl = RREG32(IH_CNTL); 2945 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); 2946 2947 ih_cntl |= ENABLE_INTR; 2948 ih_rb_cntl |= IH_RB_ENABLE; 2949 WREG32(IH_CNTL, ih_cntl); 2950 WREG32(IH_RB_CNTL, ih_rb_cntl); 2951 rdev->ih.enabled = true; 2952 } 2953 2954 void r600_disable_interrupts(struct radeon_device *rdev) 2955 { 2956 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); 2957 u32 ih_cntl = RREG32(IH_CNTL); 2958 2959 ih_rb_cntl &= ~IH_RB_ENABLE; 2960 ih_cntl &= ~ENABLE_INTR; 2961 WREG32(IH_RB_CNTL, ih_rb_cntl); 2962 WREG32(IH_CNTL, ih_cntl); 2963 /* set rptr, wptr to 0 */ 2964 WREG32(IH_RB_RPTR, 0); 2965 WREG32(IH_RB_WPTR, 0); 2966 rdev->ih.enabled = false; 2967 rdev->ih.wptr = 0; 2968 rdev->ih.rptr = 0; 2969 } 2970 2971 static void r600_disable_interrupt_state(struct radeon_device *rdev) 2972 { 2973 u32 tmp; 2974 2975 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); 2976 WREG32(GRBM_INT_CNTL, 0); 2977 WREG32(DxMODE_INT_MASK, 0); 2978 WREG32(D1GRPH_INTERRUPT_CONTROL, 0); 2979 WREG32(D2GRPH_INTERRUPT_CONTROL, 0); 2980 if (ASIC_IS_DCE3(rdev)) { 2981 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0); 2982 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0); 2983 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; 2984 WREG32(DC_HPD1_INT_CONTROL, tmp); 2985 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY; 2986 WREG32(DC_HPD2_INT_CONTROL, tmp); 2987 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY; 2988 WREG32(DC_HPD3_INT_CONTROL, tmp); 2989 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY; 2990 WREG32(DC_HPD4_INT_CONTROL, tmp); 2991 if (ASIC_IS_DCE32(rdev)) { 2992 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; 2993 WREG32(DC_HPD5_INT_CONTROL, tmp); 2994 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; 2995 WREG32(DC_HPD6_INT_CONTROL, tmp); 2996 } 2997 } else { 2998 WREG32(DACA_AUTODETECT_INT_CONTROL, 0); 2999 WREG32(DACB_AUTODETECT_INT_CONTROL, 0); 3000 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; 3001 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 3002 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; 3003 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 3004 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; 3005 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); 3006 } 3007 } 3008 3009 int r600_irq_init(struct radeon_device *rdev) 3010 { 3011 int ret = 0; 3012 int rb_bufsz; 3013 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; 3014 3015 /* allocate ring */ 3016 ret = r600_ih_ring_alloc(rdev); 3017 if (ret) 3018 return ret; 3019 3020 /* disable irqs */ 3021 r600_disable_interrupts(rdev); 3022 3023 /* init rlc */ 3024 ret = r600_rlc_init(rdev); 3025 if (ret) { 3026 r600_ih_ring_fini(rdev); 3027 return ret; 3028 } 3029 3030 /* setup interrupt control */ 3031 /* set dummy read address to ring address */ 3032 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8); 3033 interrupt_cntl = RREG32(INTERRUPT_CNTL); 3034 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi 3035 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN 3036 */ 3037 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE; 3038 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */ 3039 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN; 3040 WREG32(INTERRUPT_CNTL, interrupt_cntl); 3041 3042 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8); 3043 rb_bufsz = drm_order(rdev->ih.ring_size / 4); 3044 3045 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE | 3046 IH_WPTR_OVERFLOW_CLEAR | 3047 (rb_bufsz << 1)); 3048 3049 if (rdev->wb.enabled) 3050 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE; 3051 3052 /* set the writeback address whether it's enabled or not */ 3053 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC); 3054 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF); 3055 3056 WREG32(IH_RB_CNTL, ih_rb_cntl); 3057 3058 /* set rptr, wptr to 0 */ 3059 WREG32(IH_RB_RPTR, 0); 3060 WREG32(IH_RB_WPTR, 0); 3061 3062 /* Default settings for IH_CNTL (disabled at first) */ 3063 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10); 3064 /* RPTR_REARM only works if msi's are enabled */ 3065 if (rdev->msi_enabled) 3066 ih_cntl |= RPTR_REARM; 3067 WREG32(IH_CNTL, ih_cntl); 3068 3069 /* force the active interrupt state to all disabled */ 3070 if (rdev->family >= CHIP_CEDAR) 3071 evergreen_disable_interrupt_state(rdev); 3072 else 3073 r600_disable_interrupt_state(rdev); 3074 3075 /* enable irqs */ 3076 r600_enable_interrupts(rdev); 3077 3078 return ret; 3079 } 3080 3081 void r600_irq_suspend(struct radeon_device *rdev) 3082 { 3083 r600_irq_disable(rdev); 3084 r600_rlc_stop(rdev); 3085 } 3086 3087 void r600_irq_fini(struct radeon_device *rdev) 3088 { 3089 r600_irq_suspend(rdev); 3090 r600_ih_ring_fini(rdev); 3091 } 3092 3093 int r600_irq_set(struct radeon_device *rdev) 3094 { 3095 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; 3096 u32 mode_int = 0; 3097 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0; 3098 u32 grbm_int_cntl = 0; 3099 u32 hdmi1, hdmi2; 3100 u32 d1grph = 0, d2grph = 0; 3101 3102 if (!rdev->irq.installed) { 3103 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); 3104 return -EINVAL; 3105 } 3106 /* don't enable anything if the ih is disabled */ 3107 if (!rdev->ih.enabled) { 3108 r600_disable_interrupts(rdev); 3109 /* force the active interrupt state to all disabled */ 3110 r600_disable_interrupt_state(rdev); 3111 return 0; 3112 } 3113 3114 hdmi1 = RREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN; 3115 if (ASIC_IS_DCE3(rdev)) { 3116 hdmi2 = RREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN; 3117 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN; 3118 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN; 3119 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN; 3120 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN; 3121 if (ASIC_IS_DCE32(rdev)) { 3122 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; 3123 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN; 3124 } 3125 } else { 3126 hdmi2 = RREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN; 3127 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN; 3128 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN; 3129 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN; 3130 } 3131 3132 if (rdev->irq.sw_int) { 3133 DRM_DEBUG("r600_irq_set: sw int\n"); 3134 cp_int_cntl |= RB_INT_ENABLE; 3135 cp_int_cntl |= TIME_STAMP_INT_ENABLE; 3136 } 3137 if (rdev->irq.crtc_vblank_int[0] || 3138 rdev->irq.pflip[0]) { 3139 DRM_DEBUG("r600_irq_set: vblank 0\n"); 3140 mode_int |= D1MODE_VBLANK_INT_MASK; 3141 } 3142 if (rdev->irq.crtc_vblank_int[1] || 3143 rdev->irq.pflip[1]) { 3144 DRM_DEBUG("r600_irq_set: vblank 1\n"); 3145 mode_int |= D2MODE_VBLANK_INT_MASK; 3146 } 3147 if (rdev->irq.hpd[0]) { 3148 DRM_DEBUG("r600_irq_set: hpd 1\n"); 3149 hpd1 |= DC_HPDx_INT_EN; 3150 } 3151 if (rdev->irq.hpd[1]) { 3152 DRM_DEBUG("r600_irq_set: hpd 2\n"); 3153 hpd2 |= DC_HPDx_INT_EN; 3154 } 3155 if (rdev->irq.hpd[2]) { 3156 DRM_DEBUG("r600_irq_set: hpd 3\n"); 3157 hpd3 |= DC_HPDx_INT_EN; 3158 } 3159 if (rdev->irq.hpd[3]) { 3160 DRM_DEBUG("r600_irq_set: hpd 4\n"); 3161 hpd4 |= DC_HPDx_INT_EN; 3162 } 3163 if (rdev->irq.hpd[4]) { 3164 DRM_DEBUG("r600_irq_set: hpd 5\n"); 3165 hpd5 |= DC_HPDx_INT_EN; 3166 } 3167 if (rdev->irq.hpd[5]) { 3168 DRM_DEBUG("r600_irq_set: hpd 6\n"); 3169 hpd6 |= DC_HPDx_INT_EN; 3170 } 3171 if (rdev->irq.hdmi[0]) { 3172 DRM_DEBUG("r600_irq_set: hdmi 1\n"); 3173 hdmi1 |= R600_HDMI_INT_EN; 3174 } 3175 if (rdev->irq.hdmi[1]) { 3176 DRM_DEBUG("r600_irq_set: hdmi 2\n"); 3177 hdmi2 |= R600_HDMI_INT_EN; 3178 } 3179 if (rdev->irq.gui_idle) { 3180 DRM_DEBUG("gui idle\n"); 3181 grbm_int_cntl |= GUI_IDLE_INT_ENABLE; 3182 } 3183 3184 WREG32(CP_INT_CNTL, cp_int_cntl); 3185 WREG32(DxMODE_INT_MASK, mode_int); 3186 WREG32(D1GRPH_INTERRUPT_CONTROL, d1grph); 3187 WREG32(D2GRPH_INTERRUPT_CONTROL, d2grph); 3188 WREG32(GRBM_INT_CNTL, grbm_int_cntl); 3189 WREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, hdmi1); 3190 if (ASIC_IS_DCE3(rdev)) { 3191 WREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, hdmi2); 3192 WREG32(DC_HPD1_INT_CONTROL, hpd1); 3193 WREG32(DC_HPD2_INT_CONTROL, hpd2); 3194 WREG32(DC_HPD3_INT_CONTROL, hpd3); 3195 WREG32(DC_HPD4_INT_CONTROL, hpd4); 3196 if (ASIC_IS_DCE32(rdev)) { 3197 WREG32(DC_HPD5_INT_CONTROL, hpd5); 3198 WREG32(DC_HPD6_INT_CONTROL, hpd6); 3199 } 3200 } else { 3201 WREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, hdmi2); 3202 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); 3203 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); 3204 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3); 3205 } 3206 3207 return 0; 3208 } 3209 3210 static void r600_irq_ack(struct radeon_device *rdev) 3211 { 3212 u32 tmp; 3213 3214 if (ASIC_IS_DCE3(rdev)) { 3215 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS); 3216 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE); 3217 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2); 3218 } else { 3219 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS); 3220 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); 3221 rdev->irq.stat_regs.r600.disp_int_cont2 = 0; 3222 } 3223 rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS); 3224 rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS); 3225 3226 if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED) 3227 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR); 3228 if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED) 3229 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR); 3230 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) 3231 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK); 3232 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) 3233 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK); 3234 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) 3235 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK); 3236 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) 3237 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK); 3238 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) { 3239 if (ASIC_IS_DCE3(rdev)) { 3240 tmp = RREG32(DC_HPD1_INT_CONTROL); 3241 tmp |= DC_HPDx_INT_ACK; 3242 WREG32(DC_HPD1_INT_CONTROL, tmp); 3243 } else { 3244 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); 3245 tmp |= DC_HPDx_INT_ACK; 3246 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 3247 } 3248 } 3249 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) { 3250 if (ASIC_IS_DCE3(rdev)) { 3251 tmp = RREG32(DC_HPD2_INT_CONTROL); 3252 tmp |= DC_HPDx_INT_ACK; 3253 WREG32(DC_HPD2_INT_CONTROL, tmp); 3254 } else { 3255 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); 3256 tmp |= DC_HPDx_INT_ACK; 3257 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 3258 } 3259 } 3260 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) { 3261 if (ASIC_IS_DCE3(rdev)) { 3262 tmp = RREG32(DC_HPD3_INT_CONTROL); 3263 tmp |= DC_HPDx_INT_ACK; 3264 WREG32(DC_HPD3_INT_CONTROL, tmp); 3265 } else { 3266 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); 3267 tmp |= DC_HPDx_INT_ACK; 3268 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); 3269 } 3270 } 3271 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) { 3272 tmp = RREG32(DC_HPD4_INT_CONTROL); 3273 tmp |= DC_HPDx_INT_ACK; 3274 WREG32(DC_HPD4_INT_CONTROL, tmp); 3275 } 3276 if (ASIC_IS_DCE32(rdev)) { 3277 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) { 3278 tmp = RREG32(DC_HPD5_INT_CONTROL); 3279 tmp |= DC_HPDx_INT_ACK; 3280 WREG32(DC_HPD5_INT_CONTROL, tmp); 3281 } 3282 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) { 3283 tmp = RREG32(DC_HPD5_INT_CONTROL); 3284 tmp |= DC_HPDx_INT_ACK; 3285 WREG32(DC_HPD6_INT_CONTROL, tmp); 3286 } 3287 } 3288 if (RREG32(R600_HDMI_BLOCK1 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) { 3289 WREG32_P(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK); 3290 } 3291 if (ASIC_IS_DCE3(rdev)) { 3292 if (RREG32(R600_HDMI_BLOCK3 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) { 3293 WREG32_P(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK); 3294 } 3295 } else { 3296 if (RREG32(R600_HDMI_BLOCK2 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) { 3297 WREG32_P(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK); 3298 } 3299 } 3300 } 3301 3302 void r600_irq_disable(struct radeon_device *rdev) 3303 { 3304 r600_disable_interrupts(rdev); 3305 /* Wait and acknowledge irq */ 3306 mdelay(1); 3307 r600_irq_ack(rdev); 3308 r600_disable_interrupt_state(rdev); 3309 } 3310 3311 static u32 r600_get_ih_wptr(struct radeon_device *rdev) 3312 { 3313 u32 wptr, tmp; 3314 3315 if (rdev->wb.enabled) 3316 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]); 3317 else 3318 wptr = RREG32(IH_RB_WPTR); 3319 3320 if (wptr & RB_OVERFLOW) { 3321 /* When a ring buffer overflow happen start parsing interrupt 3322 * from the last not overwritten vector (wptr + 16). Hopefully 3323 * this should allow us to catchup. 3324 */ 3325 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n", 3326 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask); 3327 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; 3328 tmp = RREG32(IH_RB_CNTL); 3329 tmp |= IH_WPTR_OVERFLOW_CLEAR; 3330 WREG32(IH_RB_CNTL, tmp); 3331 } 3332 return (wptr & rdev->ih.ptr_mask); 3333 } 3334 3335 /* r600 IV Ring 3336 * Each IV ring entry is 128 bits: 3337 * [7:0] - interrupt source id 3338 * [31:8] - reserved 3339 * [59:32] - interrupt source data 3340 * [127:60] - reserved 3341 * 3342 * The basic interrupt vector entries 3343 * are decoded as follows: 3344 * src_id src_data description 3345 * 1 0 D1 Vblank 3346 * 1 1 D1 Vline 3347 * 5 0 D2 Vblank 3348 * 5 1 D2 Vline 3349 * 19 0 FP Hot plug detection A 3350 * 19 1 FP Hot plug detection B 3351 * 19 2 DAC A auto-detection 3352 * 19 3 DAC B auto-detection 3353 * 21 4 HDMI block A 3354 * 21 5 HDMI block B 3355 * 176 - CP_INT RB 3356 * 177 - CP_INT IB1 3357 * 178 - CP_INT IB2 3358 * 181 - EOP Interrupt 3359 * 233 - GUI Idle 3360 * 3361 * Note, these are based on r600 and may need to be 3362 * adjusted or added to on newer asics 3363 */ 3364 3365 int r600_irq_process(struct radeon_device *rdev) 3366 { 3367 u32 wptr; 3368 u32 rptr; 3369 u32 src_id, src_data; 3370 u32 ring_index; 3371 unsigned long flags; 3372 bool queue_hotplug = false; 3373 3374 if (!rdev->ih.enabled || rdev->shutdown) 3375 return IRQ_NONE; 3376 3377 /* No MSIs, need a dummy read to flush PCI DMAs */ 3378 if (!rdev->msi_enabled) 3379 RREG32(IH_RB_WPTR); 3380 3381 wptr = r600_get_ih_wptr(rdev); 3382 rptr = rdev->ih.rptr; 3383 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr); 3384 3385 spin_lock_irqsave(&rdev->ih.lock, flags); 3386 3387 if (rptr == wptr) { 3388 spin_unlock_irqrestore(&rdev->ih.lock, flags); 3389 return IRQ_NONE; 3390 } 3391 3392 restart_ih: 3393 /* Order reading of wptr vs. reading of IH ring data */ 3394 rmb(); 3395 3396 /* display interrupts */ 3397 r600_irq_ack(rdev); 3398 3399 rdev->ih.wptr = wptr; 3400 while (rptr != wptr) { 3401 /* wptr/rptr are in bytes! */ 3402 ring_index = rptr / 4; 3403 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff; 3404 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff; 3405 3406 switch (src_id) { 3407 case 1: /* D1 vblank/vline */ 3408 switch (src_data) { 3409 case 0: /* D1 vblank */ 3410 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) { 3411 if (rdev->irq.crtc_vblank_int[0]) { 3412 drm_handle_vblank(rdev->ddev, 0); 3413 rdev->pm.vblank_sync = true; 3414 wake_up(&rdev->irq.vblank_queue); 3415 } 3416 if (rdev->irq.pflip[0]) 3417 radeon_crtc_handle_flip(rdev, 0); 3418 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT; 3419 DRM_DEBUG("IH: D1 vblank\n"); 3420 } 3421 break; 3422 case 1: /* D1 vline */ 3423 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) { 3424 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT; 3425 DRM_DEBUG("IH: D1 vline\n"); 3426 } 3427 break; 3428 default: 3429 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 3430 break; 3431 } 3432 break; 3433 case 5: /* D2 vblank/vline */ 3434 switch (src_data) { 3435 case 0: /* D2 vblank */ 3436 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) { 3437 if (rdev->irq.crtc_vblank_int[1]) { 3438 drm_handle_vblank(rdev->ddev, 1); 3439 rdev->pm.vblank_sync = true; 3440 wake_up(&rdev->irq.vblank_queue); 3441 } 3442 if (rdev->irq.pflip[1]) 3443 radeon_crtc_handle_flip(rdev, 1); 3444 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT; 3445 DRM_DEBUG("IH: D2 vblank\n"); 3446 } 3447 break; 3448 case 1: /* D1 vline */ 3449 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) { 3450 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT; 3451 DRM_DEBUG("IH: D2 vline\n"); 3452 } 3453 break; 3454 default: 3455 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 3456 break; 3457 } 3458 break; 3459 case 19: /* HPD/DAC hotplug */ 3460 switch (src_data) { 3461 case 0: 3462 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) { 3463 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT; 3464 queue_hotplug = true; 3465 DRM_DEBUG("IH: HPD1\n"); 3466 } 3467 break; 3468 case 1: 3469 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) { 3470 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT; 3471 queue_hotplug = true; 3472 DRM_DEBUG("IH: HPD2\n"); 3473 } 3474 break; 3475 case 4: 3476 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) { 3477 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT; 3478 queue_hotplug = true; 3479 DRM_DEBUG("IH: HPD3\n"); 3480 } 3481 break; 3482 case 5: 3483 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) { 3484 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT; 3485 queue_hotplug = true; 3486 DRM_DEBUG("IH: HPD4\n"); 3487 } 3488 break; 3489 case 10: 3490 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) { 3491 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT; 3492 queue_hotplug = true; 3493 DRM_DEBUG("IH: HPD5\n"); 3494 } 3495 break; 3496 case 12: 3497 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) { 3498 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT; 3499 queue_hotplug = true; 3500 DRM_DEBUG("IH: HPD6\n"); 3501 } 3502 break; 3503 default: 3504 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 3505 break; 3506 } 3507 break; 3508 case 21: /* HDMI */ 3509 DRM_DEBUG("IH: HDMI: 0x%x\n", src_data); 3510 r600_audio_schedule_polling(rdev); 3511 break; 3512 case 176: /* CP_INT in ring buffer */ 3513 case 177: /* CP_INT in IB1 */ 3514 case 178: /* CP_INT in IB2 */ 3515 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data); 3516 radeon_fence_process(rdev); 3517 break; 3518 case 181: /* CP EOP event */ 3519 DRM_DEBUG("IH: CP EOP\n"); 3520 radeon_fence_process(rdev); 3521 break; 3522 case 233: /* GUI IDLE */ 3523 DRM_DEBUG("IH: GUI idle\n"); 3524 rdev->pm.gui_idle = true; 3525 wake_up(&rdev->irq.idle_queue); 3526 break; 3527 default: 3528 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 3529 break; 3530 } 3531 3532 /* wptr/rptr are in bytes! */ 3533 rptr += 16; 3534 rptr &= rdev->ih.ptr_mask; 3535 } 3536 /* make sure wptr hasn't changed while processing */ 3537 wptr = r600_get_ih_wptr(rdev); 3538 if (wptr != rdev->ih.wptr) 3539 goto restart_ih; 3540 if (queue_hotplug) 3541 schedule_work(&rdev->hotplug_work); 3542 rdev->ih.rptr = rptr; 3543 WREG32(IH_RB_RPTR, rdev->ih.rptr); 3544 spin_unlock_irqrestore(&rdev->ih.lock, flags); 3545 return IRQ_HANDLED; 3546 } 3547 3548 /* 3549 * Debugfs info 3550 */ 3551 #if defined(CONFIG_DEBUG_FS) 3552 3553 static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data) 3554 { 3555 struct drm_info_node *node = (struct drm_info_node *) m->private; 3556 struct drm_device *dev = node->minor->dev; 3557 struct radeon_device *rdev = dev->dev_private; 3558 unsigned count, i, j; 3559 3560 radeon_ring_free_size(rdev); 3561 count = (rdev->cp.ring_size / 4) - rdev->cp.ring_free_dw; 3562 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT)); 3563 seq_printf(m, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR)); 3564 seq_printf(m, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR)); 3565 seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", rdev->cp.wptr); 3566 seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", rdev->cp.rptr); 3567 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw); 3568 seq_printf(m, "%u dwords in ring\n", count); 3569 i = rdev->cp.rptr; 3570 for (j = 0; j <= count; j++) { 3571 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]); 3572 i = (i + 1) & rdev->cp.ptr_mask; 3573 } 3574 return 0; 3575 } 3576 3577 static int r600_debugfs_mc_info(struct seq_file *m, void *data) 3578 { 3579 struct drm_info_node *node = (struct drm_info_node *) m->private; 3580 struct drm_device *dev = node->minor->dev; 3581 struct radeon_device *rdev = dev->dev_private; 3582 3583 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS); 3584 DREG32_SYS(m, rdev, VM_L2_STATUS); 3585 return 0; 3586 } 3587 3588 static struct drm_info_list r600_mc_info_list[] = { 3589 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL}, 3590 {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL}, 3591 }; 3592 #endif 3593 3594 int r600_debugfs_mc_info_init(struct radeon_device *rdev) 3595 { 3596 #if defined(CONFIG_DEBUG_FS) 3597 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list)); 3598 #else 3599 return 0; 3600 #endif 3601 } 3602 3603 /** 3604 * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl 3605 * rdev: radeon device structure 3606 * bo: buffer object struct which userspace is waiting for idle 3607 * 3608 * Some R6XX/R7XX doesn't seems to take into account HDP flush performed 3609 * through ring buffer, this leads to corruption in rendering, see 3610 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we 3611 * directly perform HDP flush by writing register through MMIO. 3612 */ 3613 void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo) 3614 { 3615 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read 3616 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL. 3617 * This seems to cause problems on some AGP cards. Just use the old 3618 * method for them. 3619 */ 3620 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) && 3621 rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) { 3622 void __iomem *ptr = (void *)rdev->vram_scratch.ptr; 3623 u32 tmp; 3624 3625 WREG32(HDP_DEBUG1, 0); 3626 tmp = readl((void __iomem *)ptr); 3627 } else 3628 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); 3629 } 3630 3631 void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes) 3632 { 3633 u32 link_width_cntl, mask, target_reg; 3634 3635 if (rdev->flags & RADEON_IS_IGP) 3636 return; 3637 3638 if (!(rdev->flags & RADEON_IS_PCIE)) 3639 return; 3640 3641 /* x2 cards have a special sequence */ 3642 if (ASIC_IS_X2(rdev)) 3643 return; 3644 3645 /* FIXME wait for idle */ 3646 3647 switch (lanes) { 3648 case 0: 3649 mask = RADEON_PCIE_LC_LINK_WIDTH_X0; 3650 break; 3651 case 1: 3652 mask = RADEON_PCIE_LC_LINK_WIDTH_X1; 3653 break; 3654 case 2: 3655 mask = RADEON_PCIE_LC_LINK_WIDTH_X2; 3656 break; 3657 case 4: 3658 mask = RADEON_PCIE_LC_LINK_WIDTH_X4; 3659 break; 3660 case 8: 3661 mask = RADEON_PCIE_LC_LINK_WIDTH_X8; 3662 break; 3663 case 12: 3664 mask = RADEON_PCIE_LC_LINK_WIDTH_X12; 3665 break; 3666 case 16: 3667 default: 3668 mask = RADEON_PCIE_LC_LINK_WIDTH_X16; 3669 break; 3670 } 3671 3672 link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 3673 3674 if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) == 3675 (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT)) 3676 return; 3677 3678 if (link_width_cntl & R600_PCIE_LC_UPCONFIGURE_DIS) 3679 return; 3680 3681 link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK | 3682 RADEON_PCIE_LC_RECONFIG_NOW | 3683 R600_PCIE_LC_RENEGOTIATE_EN | 3684 R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE); 3685 link_width_cntl |= mask; 3686 3687 WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 3688 3689 /* some northbridges can renegotiate the link rather than requiring 3690 * a complete re-config. 3691 * e.g., AMD 780/790 northbridges (pci ids: 0x5956, 0x5957, 0x5958, etc.) 3692 */ 3693 if (link_width_cntl & R600_PCIE_LC_RENEGOTIATION_SUPPORT) 3694 link_width_cntl |= R600_PCIE_LC_RENEGOTIATE_EN | R600_PCIE_LC_UPCONFIGURE_SUPPORT; 3695 else 3696 link_width_cntl |= R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE; 3697 3698 WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl | 3699 RADEON_PCIE_LC_RECONFIG_NOW)); 3700 3701 if (rdev->family >= CHIP_RV770) 3702 target_reg = R700_TARGET_AND_CURRENT_PROFILE_INDEX; 3703 else 3704 target_reg = R600_TARGET_AND_CURRENT_PROFILE_INDEX; 3705 3706 /* wait for lane set to complete */ 3707 link_width_cntl = RREG32(target_reg); 3708 while (link_width_cntl == 0xffffffff) 3709 link_width_cntl = RREG32(target_reg); 3710 3711 } 3712 3713 int r600_get_pcie_lanes(struct radeon_device *rdev) 3714 { 3715 u32 link_width_cntl; 3716 3717 if (rdev->flags & RADEON_IS_IGP) 3718 return 0; 3719 3720 if (!(rdev->flags & RADEON_IS_PCIE)) 3721 return 0; 3722 3723 /* x2 cards have a special sequence */ 3724 if (ASIC_IS_X2(rdev)) 3725 return 0; 3726 3727 /* FIXME wait for idle */ 3728 3729 link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 3730 3731 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) { 3732 case RADEON_PCIE_LC_LINK_WIDTH_X0: 3733 return 0; 3734 case RADEON_PCIE_LC_LINK_WIDTH_X1: 3735 return 1; 3736 case RADEON_PCIE_LC_LINK_WIDTH_X2: 3737 return 2; 3738 case RADEON_PCIE_LC_LINK_WIDTH_X4: 3739 return 4; 3740 case RADEON_PCIE_LC_LINK_WIDTH_X8: 3741 return 8; 3742 case RADEON_PCIE_LC_LINK_WIDTH_X16: 3743 default: 3744 return 16; 3745 } 3746 } 3747 3748 static void r600_pcie_gen2_enable(struct radeon_device *rdev) 3749 { 3750 u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp; 3751 u16 link_cntl2; 3752 3753 if (radeon_pcie_gen2 == 0) 3754 return; 3755 3756 if (rdev->flags & RADEON_IS_IGP) 3757 return; 3758 3759 if (!(rdev->flags & RADEON_IS_PCIE)) 3760 return; 3761 3762 /* x2 cards have a special sequence */ 3763 if (ASIC_IS_X2(rdev)) 3764 return; 3765 3766 /* only RV6xx+ chips are supported */ 3767 if (rdev->family <= CHIP_R600) 3768 return; 3769 3770 /* 55 nm r6xx asics */ 3771 if ((rdev->family == CHIP_RV670) || 3772 (rdev->family == CHIP_RV620) || 3773 (rdev->family == CHIP_RV635)) { 3774 /* advertise upconfig capability */ 3775 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); 3776 link_width_cntl &= ~LC_UPCONFIGURE_DIS; 3777 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 3778 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); 3779 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) { 3780 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; 3781 link_width_cntl &= ~(LC_LINK_WIDTH_MASK | 3782 LC_RECONFIG_ARC_MISSING_ESCAPE); 3783 link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN; 3784 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 3785 } else { 3786 link_width_cntl |= LC_UPCONFIGURE_DIS; 3787 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 3788 } 3789 } 3790 3791 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 3792 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) && 3793 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { 3794 3795 /* 55 nm r6xx asics */ 3796 if ((rdev->family == CHIP_RV670) || 3797 (rdev->family == CHIP_RV620) || 3798 (rdev->family == CHIP_RV635)) { 3799 WREG32(MM_CFGREGS_CNTL, 0x8); 3800 link_cntl2 = RREG32(0x4088); 3801 WREG32(MM_CFGREGS_CNTL, 0); 3802 /* not supported yet */ 3803 if (link_cntl2 & SELECTABLE_DEEMPHASIS) 3804 return; 3805 } 3806 3807 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK; 3808 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT); 3809 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK; 3810 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE; 3811 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE; 3812 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); 3813 3814 tmp = RREG32(0x541c); 3815 WREG32(0x541c, tmp | 0x8); 3816 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN); 3817 link_cntl2 = RREG16(0x4088); 3818 link_cntl2 &= ~TARGET_LINK_SPEED_MASK; 3819 link_cntl2 |= 0x2; 3820 WREG16(0x4088, link_cntl2); 3821 WREG32(MM_CFGREGS_CNTL, 0); 3822 3823 if ((rdev->family == CHIP_RV670) || 3824 (rdev->family == CHIP_RV620) || 3825 (rdev->family == CHIP_RV635)) { 3826 training_cntl = RREG32_PCIE_P(PCIE_LC_TRAINING_CNTL); 3827 training_cntl &= ~LC_POINT_7_PLUS_EN; 3828 WREG32_PCIE_P(PCIE_LC_TRAINING_CNTL, training_cntl); 3829 } else { 3830 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 3831 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN; 3832 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); 3833 } 3834 3835 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 3836 speed_cntl |= LC_GEN2_EN_STRAP; 3837 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); 3838 3839 } else { 3840 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); 3841 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */ 3842 if (1) 3843 link_width_cntl |= LC_UPCONFIGURE_DIS; 3844 else 3845 link_width_cntl &= ~LC_UPCONFIGURE_DIS; 3846 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 3847 } 3848 } 3849