1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/seq_file.h> 29 #include <linux/firmware.h> 30 #include <linux/platform_device.h> 31 #include "drmP.h" 32 #include "radeon_drm.h" 33 #include "radeon.h" 34 #include "radeon_mode.h" 35 #include "r600d.h" 36 #include "atom.h" 37 #include "avivod.h" 38 39 #define PFP_UCODE_SIZE 576 40 #define PM4_UCODE_SIZE 1792 41 #define RLC_UCODE_SIZE 768 42 #define R700_PFP_UCODE_SIZE 848 43 #define R700_PM4_UCODE_SIZE 1360 44 #define R700_RLC_UCODE_SIZE 1024 45 46 /* Firmware Names */ 47 MODULE_FIRMWARE("radeon/R600_pfp.bin"); 48 MODULE_FIRMWARE("radeon/R600_me.bin"); 49 MODULE_FIRMWARE("radeon/RV610_pfp.bin"); 50 MODULE_FIRMWARE("radeon/RV610_me.bin"); 51 MODULE_FIRMWARE("radeon/RV630_pfp.bin"); 52 MODULE_FIRMWARE("radeon/RV630_me.bin"); 53 MODULE_FIRMWARE("radeon/RV620_pfp.bin"); 54 MODULE_FIRMWARE("radeon/RV620_me.bin"); 55 MODULE_FIRMWARE("radeon/RV635_pfp.bin"); 56 MODULE_FIRMWARE("radeon/RV635_me.bin"); 57 MODULE_FIRMWARE("radeon/RV670_pfp.bin"); 58 MODULE_FIRMWARE("radeon/RV670_me.bin"); 59 MODULE_FIRMWARE("radeon/RS780_pfp.bin"); 60 MODULE_FIRMWARE("radeon/RS780_me.bin"); 61 MODULE_FIRMWARE("radeon/RV770_pfp.bin"); 62 MODULE_FIRMWARE("radeon/RV770_me.bin"); 63 MODULE_FIRMWARE("radeon/RV730_pfp.bin"); 64 MODULE_FIRMWARE("radeon/RV730_me.bin"); 65 MODULE_FIRMWARE("radeon/RV710_pfp.bin"); 66 MODULE_FIRMWARE("radeon/RV710_me.bin"); 67 MODULE_FIRMWARE("radeon/R600_rlc.bin"); 68 MODULE_FIRMWARE("radeon/R700_rlc.bin"); 69 70 int r600_debugfs_mc_info_init(struct radeon_device *rdev); 71 72 /* r600,rv610,rv630,rv620,rv635,rv670 */ 73 int r600_mc_wait_for_idle(struct radeon_device *rdev); 74 void r600_gpu_init(struct radeon_device *rdev); 75 void r600_fini(struct radeon_device *rdev); 76 77 /* hpd for digital panel detect/disconnect */ 78 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) 79 { 80 bool connected = false; 81 82 if (ASIC_IS_DCE3(rdev)) { 83 switch (hpd) { 84 case RADEON_HPD_1: 85 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE) 86 connected = true; 87 break; 88 case RADEON_HPD_2: 89 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE) 90 connected = true; 91 break; 92 case RADEON_HPD_3: 93 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE) 94 connected = true; 95 break; 96 case RADEON_HPD_4: 97 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE) 98 connected = true; 99 break; 100 /* DCE 3.2 */ 101 case RADEON_HPD_5: 102 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE) 103 connected = true; 104 break; 105 case RADEON_HPD_6: 106 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE) 107 connected = true; 108 break; 109 default: 110 break; 111 } 112 } else { 113 switch (hpd) { 114 case RADEON_HPD_1: 115 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) 116 connected = true; 117 break; 118 case RADEON_HPD_2: 119 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) 120 connected = true; 121 break; 122 case RADEON_HPD_3: 123 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) 124 connected = true; 125 break; 126 default: 127 break; 128 } 129 } 130 return connected; 131 } 132 133 void r600_hpd_set_polarity(struct radeon_device *rdev, 134 enum radeon_hpd_id hpd) 135 { 136 u32 tmp; 137 bool connected = r600_hpd_sense(rdev, hpd); 138 139 if (ASIC_IS_DCE3(rdev)) { 140 switch (hpd) { 141 case RADEON_HPD_1: 142 tmp = RREG32(DC_HPD1_INT_CONTROL); 143 if (connected) 144 tmp &= ~DC_HPDx_INT_POLARITY; 145 else 146 tmp |= DC_HPDx_INT_POLARITY; 147 WREG32(DC_HPD1_INT_CONTROL, tmp); 148 break; 149 case RADEON_HPD_2: 150 tmp = RREG32(DC_HPD2_INT_CONTROL); 151 if (connected) 152 tmp &= ~DC_HPDx_INT_POLARITY; 153 else 154 tmp |= DC_HPDx_INT_POLARITY; 155 WREG32(DC_HPD2_INT_CONTROL, tmp); 156 break; 157 case RADEON_HPD_3: 158 tmp = RREG32(DC_HPD3_INT_CONTROL); 159 if (connected) 160 tmp &= ~DC_HPDx_INT_POLARITY; 161 else 162 tmp |= DC_HPDx_INT_POLARITY; 163 WREG32(DC_HPD3_INT_CONTROL, tmp); 164 break; 165 case RADEON_HPD_4: 166 tmp = RREG32(DC_HPD4_INT_CONTROL); 167 if (connected) 168 tmp &= ~DC_HPDx_INT_POLARITY; 169 else 170 tmp |= DC_HPDx_INT_POLARITY; 171 WREG32(DC_HPD4_INT_CONTROL, tmp); 172 break; 173 case RADEON_HPD_5: 174 tmp = RREG32(DC_HPD5_INT_CONTROL); 175 if (connected) 176 tmp &= ~DC_HPDx_INT_POLARITY; 177 else 178 tmp |= DC_HPDx_INT_POLARITY; 179 WREG32(DC_HPD5_INT_CONTROL, tmp); 180 break; 181 /* DCE 3.2 */ 182 case RADEON_HPD_6: 183 tmp = RREG32(DC_HPD6_INT_CONTROL); 184 if (connected) 185 tmp &= ~DC_HPDx_INT_POLARITY; 186 else 187 tmp |= DC_HPDx_INT_POLARITY; 188 WREG32(DC_HPD6_INT_CONTROL, tmp); 189 break; 190 default: 191 break; 192 } 193 } else { 194 switch (hpd) { 195 case RADEON_HPD_1: 196 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); 197 if (connected) 198 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; 199 else 200 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; 201 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 202 break; 203 case RADEON_HPD_2: 204 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); 205 if (connected) 206 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; 207 else 208 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; 209 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 210 break; 211 case RADEON_HPD_3: 212 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); 213 if (connected) 214 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; 215 else 216 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; 217 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); 218 break; 219 default: 220 break; 221 } 222 } 223 } 224 225 void r600_hpd_init(struct radeon_device *rdev) 226 { 227 struct drm_device *dev = rdev->ddev; 228 struct drm_connector *connector; 229 230 if (ASIC_IS_DCE3(rdev)) { 231 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa); 232 if (ASIC_IS_DCE32(rdev)) 233 tmp |= DC_HPDx_EN; 234 235 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 236 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 237 switch (radeon_connector->hpd.hpd) { 238 case RADEON_HPD_1: 239 WREG32(DC_HPD1_CONTROL, tmp); 240 rdev->irq.hpd[0] = true; 241 break; 242 case RADEON_HPD_2: 243 WREG32(DC_HPD2_CONTROL, tmp); 244 rdev->irq.hpd[1] = true; 245 break; 246 case RADEON_HPD_3: 247 WREG32(DC_HPD3_CONTROL, tmp); 248 rdev->irq.hpd[2] = true; 249 break; 250 case RADEON_HPD_4: 251 WREG32(DC_HPD4_CONTROL, tmp); 252 rdev->irq.hpd[3] = true; 253 break; 254 /* DCE 3.2 */ 255 case RADEON_HPD_5: 256 WREG32(DC_HPD5_CONTROL, tmp); 257 rdev->irq.hpd[4] = true; 258 break; 259 case RADEON_HPD_6: 260 WREG32(DC_HPD6_CONTROL, tmp); 261 rdev->irq.hpd[5] = true; 262 break; 263 default: 264 break; 265 } 266 } 267 } else { 268 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 269 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 270 switch (radeon_connector->hpd.hpd) { 271 case RADEON_HPD_1: 272 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN); 273 rdev->irq.hpd[0] = true; 274 break; 275 case RADEON_HPD_2: 276 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN); 277 rdev->irq.hpd[1] = true; 278 break; 279 case RADEON_HPD_3: 280 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN); 281 rdev->irq.hpd[2] = true; 282 break; 283 default: 284 break; 285 } 286 } 287 } 288 r600_irq_set(rdev); 289 } 290 291 void r600_hpd_fini(struct radeon_device *rdev) 292 { 293 struct drm_device *dev = rdev->ddev; 294 struct drm_connector *connector; 295 296 if (ASIC_IS_DCE3(rdev)) { 297 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 298 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 299 switch (radeon_connector->hpd.hpd) { 300 case RADEON_HPD_1: 301 WREG32(DC_HPD1_CONTROL, 0); 302 rdev->irq.hpd[0] = false; 303 break; 304 case RADEON_HPD_2: 305 WREG32(DC_HPD2_CONTROL, 0); 306 rdev->irq.hpd[1] = false; 307 break; 308 case RADEON_HPD_3: 309 WREG32(DC_HPD3_CONTROL, 0); 310 rdev->irq.hpd[2] = false; 311 break; 312 case RADEON_HPD_4: 313 WREG32(DC_HPD4_CONTROL, 0); 314 rdev->irq.hpd[3] = false; 315 break; 316 /* DCE 3.2 */ 317 case RADEON_HPD_5: 318 WREG32(DC_HPD5_CONTROL, 0); 319 rdev->irq.hpd[4] = false; 320 break; 321 case RADEON_HPD_6: 322 WREG32(DC_HPD6_CONTROL, 0); 323 rdev->irq.hpd[5] = false; 324 break; 325 default: 326 break; 327 } 328 } 329 } else { 330 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 331 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 332 switch (radeon_connector->hpd.hpd) { 333 case RADEON_HPD_1: 334 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0); 335 rdev->irq.hpd[0] = false; 336 break; 337 case RADEON_HPD_2: 338 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0); 339 rdev->irq.hpd[1] = false; 340 break; 341 case RADEON_HPD_3: 342 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0); 343 rdev->irq.hpd[2] = false; 344 break; 345 default: 346 break; 347 } 348 } 349 } 350 } 351 352 /* 353 * R600 PCIE GART 354 */ 355 int r600_gart_clear_page(struct radeon_device *rdev, int i) 356 { 357 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr; 358 u64 pte; 359 360 if (i < 0 || i > rdev->gart.num_gpu_pages) 361 return -EINVAL; 362 pte = 0; 363 writeq(pte, ((void __iomem *)ptr) + (i * 8)); 364 return 0; 365 } 366 367 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev) 368 { 369 unsigned i; 370 u32 tmp; 371 372 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12); 373 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12); 374 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1)); 375 for (i = 0; i < rdev->usec_timeout; i++) { 376 /* read MC_STATUS */ 377 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE); 378 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT; 379 if (tmp == 2) { 380 printk(KERN_WARNING "[drm] r600 flush TLB failed\n"); 381 return; 382 } 383 if (tmp) { 384 return; 385 } 386 udelay(1); 387 } 388 } 389 390 int r600_pcie_gart_init(struct radeon_device *rdev) 391 { 392 int r; 393 394 if (rdev->gart.table.vram.robj) { 395 WARN(1, "R600 PCIE GART already initialized.\n"); 396 return 0; 397 } 398 /* Initialize common gart structure */ 399 r = radeon_gart_init(rdev); 400 if (r) 401 return r; 402 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; 403 return radeon_gart_table_vram_alloc(rdev); 404 } 405 406 int r600_pcie_gart_enable(struct radeon_device *rdev) 407 { 408 u32 tmp; 409 int r, i; 410 411 if (rdev->gart.table.vram.robj == NULL) { 412 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 413 return -EINVAL; 414 } 415 r = radeon_gart_table_vram_pin(rdev); 416 if (r) 417 return r; 418 419 /* Setup L2 cache */ 420 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 421 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 422 EFFECTIVE_L2_QUEUE_SIZE(7)); 423 WREG32(VM_L2_CNTL2, 0); 424 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); 425 /* Setup TLB control */ 426 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | 427 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 428 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | 429 ENABLE_WAIT_L2_QUERY; 430 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); 431 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); 432 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); 433 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); 434 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); 435 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); 436 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); 437 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); 438 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); 439 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); 440 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); 441 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); 442 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 443 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 444 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); 445 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); 446 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); 447 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | 448 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); 449 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 450 (u32)(rdev->dummy_page.addr >> 12)); 451 for (i = 1; i < 7; i++) 452 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 453 454 r600_pcie_gart_tlb_flush(rdev); 455 rdev->gart.ready = true; 456 return 0; 457 } 458 459 void r600_pcie_gart_disable(struct radeon_device *rdev) 460 { 461 u32 tmp; 462 int i, r; 463 464 /* Disable all tables */ 465 for (i = 0; i < 7; i++) 466 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 467 468 /* Disable L2 cache */ 469 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | 470 EFFECTIVE_L2_QUEUE_SIZE(7)); 471 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); 472 /* Setup L1 TLB control */ 473 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | 474 ENABLE_WAIT_L2_QUERY; 475 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); 476 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); 477 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); 478 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); 479 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); 480 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); 481 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); 482 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); 483 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp); 484 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp); 485 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); 486 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); 487 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp); 488 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); 489 if (rdev->gart.table.vram.robj) { 490 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false); 491 if (likely(r == 0)) { 492 radeon_bo_kunmap(rdev->gart.table.vram.robj); 493 radeon_bo_unpin(rdev->gart.table.vram.robj); 494 radeon_bo_unreserve(rdev->gart.table.vram.robj); 495 } 496 } 497 } 498 499 void r600_pcie_gart_fini(struct radeon_device *rdev) 500 { 501 r600_pcie_gart_disable(rdev); 502 radeon_gart_table_vram_free(rdev); 503 radeon_gart_fini(rdev); 504 } 505 506 void r600_agp_enable(struct radeon_device *rdev) 507 { 508 u32 tmp; 509 int i; 510 511 /* Setup L2 cache */ 512 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 513 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 514 EFFECTIVE_L2_QUEUE_SIZE(7)); 515 WREG32(VM_L2_CNTL2, 0); 516 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); 517 /* Setup TLB control */ 518 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | 519 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 520 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | 521 ENABLE_WAIT_L2_QUERY; 522 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); 523 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); 524 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); 525 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); 526 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); 527 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); 528 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); 529 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); 530 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); 531 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); 532 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); 533 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); 534 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 535 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 536 for (i = 0; i < 7; i++) 537 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 538 } 539 540 int r600_mc_wait_for_idle(struct radeon_device *rdev) 541 { 542 unsigned i; 543 u32 tmp; 544 545 for (i = 0; i < rdev->usec_timeout; i++) { 546 /* read MC_STATUS */ 547 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00; 548 if (!tmp) 549 return 0; 550 udelay(1); 551 } 552 return -1; 553 } 554 555 static void r600_mc_program(struct radeon_device *rdev) 556 { 557 struct rv515_mc_save save; 558 u32 tmp; 559 int i, j; 560 561 /* Initialize HDP */ 562 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 563 WREG32((0x2c14 + j), 0x00000000); 564 WREG32((0x2c18 + j), 0x00000000); 565 WREG32((0x2c1c + j), 0x00000000); 566 WREG32((0x2c20 + j), 0x00000000); 567 WREG32((0x2c24 + j), 0x00000000); 568 } 569 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); 570 571 rv515_mc_stop(rdev, &save); 572 if (r600_mc_wait_for_idle(rdev)) { 573 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 574 } 575 /* Lockout access through VGA aperture (doesn't exist before R600) */ 576 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); 577 /* Update configuration */ 578 if (rdev->flags & RADEON_IS_AGP) { 579 if (rdev->mc.vram_start < rdev->mc.gtt_start) { 580 /* VRAM before AGP */ 581 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 582 rdev->mc.vram_start >> 12); 583 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 584 rdev->mc.gtt_end >> 12); 585 } else { 586 /* VRAM after AGP */ 587 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 588 rdev->mc.gtt_start >> 12); 589 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 590 rdev->mc.vram_end >> 12); 591 } 592 } else { 593 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12); 594 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12); 595 } 596 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0); 597 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; 598 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); 599 WREG32(MC_VM_FB_LOCATION, tmp); 600 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); 601 WREG32(HDP_NONSURFACE_INFO, (2 << 7)); 602 WREG32(HDP_NONSURFACE_SIZE, rdev->mc.mc_vram_size | 0x3FF); 603 if (rdev->flags & RADEON_IS_AGP) { 604 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22); 605 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22); 606 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); 607 } else { 608 WREG32(MC_VM_AGP_BASE, 0); 609 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); 610 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); 611 } 612 if (r600_mc_wait_for_idle(rdev)) { 613 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 614 } 615 rv515_mc_resume(rdev, &save); 616 /* we need to own VRAM, so turn off the VGA renderer here 617 * to stop it overwriting our objects */ 618 rv515_vga_render_disable(rdev); 619 } 620 621 int r600_mc_init(struct radeon_device *rdev) 622 { 623 fixed20_12 a; 624 u32 tmp; 625 int chansize, numchan; 626 int r; 627 628 /* Get VRAM informations */ 629 rdev->mc.vram_is_ddr = true; 630 tmp = RREG32(RAMCFG); 631 if (tmp & CHANSIZE_OVERRIDE) { 632 chansize = 16; 633 } else if (tmp & CHANSIZE_MASK) { 634 chansize = 64; 635 } else { 636 chansize = 32; 637 } 638 tmp = RREG32(CHMAP); 639 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { 640 case 0: 641 default: 642 numchan = 1; 643 break; 644 case 1: 645 numchan = 2; 646 break; 647 case 2: 648 numchan = 4; 649 break; 650 case 3: 651 numchan = 8; 652 break; 653 } 654 rdev->mc.vram_width = numchan * chansize; 655 /* Could aper size report 0 ? */ 656 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); 657 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); 658 /* Setup GPU memory space */ 659 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); 660 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); 661 662 if (rdev->mc.mc_vram_size > rdev->mc.aper_size) 663 rdev->mc.mc_vram_size = rdev->mc.aper_size; 664 665 if (rdev->mc.real_vram_size > rdev->mc.aper_size) 666 rdev->mc.real_vram_size = rdev->mc.aper_size; 667 668 if (rdev->flags & RADEON_IS_AGP) { 669 r = radeon_agp_init(rdev); 670 if (r) 671 return r; 672 /* gtt_size is setup by radeon_agp_init */ 673 rdev->mc.gtt_location = rdev->mc.agp_base; 674 tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size; 675 /* Try to put vram before or after AGP because we 676 * we want SYSTEM_APERTURE to cover both VRAM and 677 * AGP so that GPU can catch out of VRAM/AGP access 678 */ 679 if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) { 680 /* Enough place before */ 681 rdev->mc.vram_location = rdev->mc.gtt_location - 682 rdev->mc.mc_vram_size; 683 } else if (tmp > rdev->mc.mc_vram_size) { 684 /* Enough place after */ 685 rdev->mc.vram_location = rdev->mc.gtt_location + 686 rdev->mc.gtt_size; 687 } else { 688 /* Try to setup VRAM then AGP might not 689 * not work on some card 690 */ 691 rdev->mc.vram_location = 0x00000000UL; 692 rdev->mc.gtt_location = rdev->mc.mc_vram_size; 693 } 694 } else { 695 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; 696 rdev->mc.vram_location = (RREG32(MC_VM_FB_LOCATION) & 697 0xFFFF) << 24; 698 tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size; 699 if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) { 700 /* Enough place after vram */ 701 rdev->mc.gtt_location = tmp; 702 } else if (rdev->mc.vram_location >= rdev->mc.gtt_size) { 703 /* Enough place before vram */ 704 rdev->mc.gtt_location = 0; 705 } else { 706 /* Not enough place after or before shrink 707 * gart size 708 */ 709 if (rdev->mc.vram_location > (0xFFFFFFFFUL - tmp)) { 710 rdev->mc.gtt_location = 0; 711 rdev->mc.gtt_size = rdev->mc.vram_location; 712 } else { 713 rdev->mc.gtt_location = tmp; 714 rdev->mc.gtt_size = 0xFFFFFFFFUL - tmp; 715 } 716 } 717 rdev->mc.gtt_location = rdev->mc.mc_vram_size; 718 } 719 rdev->mc.vram_start = rdev->mc.vram_location; 720 rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1; 721 rdev->mc.gtt_start = rdev->mc.gtt_location; 722 rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; 723 /* FIXME: we should enforce default clock in case GPU is not in 724 * default setup 725 */ 726 a.full = rfixed_const(100); 727 rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk); 728 rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); 729 return 0; 730 } 731 732 /* We doesn't check that the GPU really needs a reset we simply do the 733 * reset, it's up to the caller to determine if the GPU needs one. We 734 * might add an helper function to check that. 735 */ 736 int r600_gpu_soft_reset(struct radeon_device *rdev) 737 { 738 struct rv515_mc_save save; 739 u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) | 740 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) | 741 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) | 742 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) | 743 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) | 744 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) | 745 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) | 746 S_008010_GUI_ACTIVE(1); 747 u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) | 748 S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) | 749 S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) | 750 S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) | 751 S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) | 752 S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) | 753 S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) | 754 S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1); 755 u32 srbm_reset = 0; 756 u32 tmp; 757 758 dev_info(rdev->dev, "GPU softreset \n"); 759 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n", 760 RREG32(R_008010_GRBM_STATUS)); 761 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n", 762 RREG32(R_008014_GRBM_STATUS2)); 763 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n", 764 RREG32(R_000E50_SRBM_STATUS)); 765 rv515_mc_stop(rdev, &save); 766 if (r600_mc_wait_for_idle(rdev)) { 767 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 768 } 769 /* Disable CP parsing/prefetching */ 770 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(0xff)); 771 /* Check if any of the rendering block is busy and reset it */ 772 if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) || 773 (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) { 774 tmp = S_008020_SOFT_RESET_CR(1) | 775 S_008020_SOFT_RESET_DB(1) | 776 S_008020_SOFT_RESET_CB(1) | 777 S_008020_SOFT_RESET_PA(1) | 778 S_008020_SOFT_RESET_SC(1) | 779 S_008020_SOFT_RESET_SMX(1) | 780 S_008020_SOFT_RESET_SPI(1) | 781 S_008020_SOFT_RESET_SX(1) | 782 S_008020_SOFT_RESET_SH(1) | 783 S_008020_SOFT_RESET_TC(1) | 784 S_008020_SOFT_RESET_TA(1) | 785 S_008020_SOFT_RESET_VC(1) | 786 S_008020_SOFT_RESET_VGT(1); 787 dev_info(rdev->dev, " R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp); 788 WREG32(R_008020_GRBM_SOFT_RESET, tmp); 789 (void)RREG32(R_008020_GRBM_SOFT_RESET); 790 udelay(50); 791 WREG32(R_008020_GRBM_SOFT_RESET, 0); 792 (void)RREG32(R_008020_GRBM_SOFT_RESET); 793 } 794 /* Reset CP (we always reset CP) */ 795 tmp = S_008020_SOFT_RESET_CP(1); 796 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp); 797 WREG32(R_008020_GRBM_SOFT_RESET, tmp); 798 (void)RREG32(R_008020_GRBM_SOFT_RESET); 799 udelay(50); 800 WREG32(R_008020_GRBM_SOFT_RESET, 0); 801 (void)RREG32(R_008020_GRBM_SOFT_RESET); 802 /* Reset others GPU block if necessary */ 803 if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS))) 804 srbm_reset |= S_000E60_SOFT_RESET_RLC(1); 805 if (G_000E50_GRBM_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS))) 806 srbm_reset |= S_000E60_SOFT_RESET_GRBM(1); 807 if (G_000E50_HI_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS))) 808 srbm_reset |= S_000E60_SOFT_RESET_IH(1); 809 if (G_000E50_VMC_BUSY(RREG32(R_000E50_SRBM_STATUS))) 810 srbm_reset |= S_000E60_SOFT_RESET_VMC(1); 811 if (G_000E50_MCB_BUSY(RREG32(R_000E50_SRBM_STATUS))) 812 srbm_reset |= S_000E60_SOFT_RESET_MC(1); 813 if (G_000E50_MCDZ_BUSY(RREG32(R_000E50_SRBM_STATUS))) 814 srbm_reset |= S_000E60_SOFT_RESET_MC(1); 815 if (G_000E50_MCDY_BUSY(RREG32(R_000E50_SRBM_STATUS))) 816 srbm_reset |= S_000E60_SOFT_RESET_MC(1); 817 if (G_000E50_MCDX_BUSY(RREG32(R_000E50_SRBM_STATUS))) 818 srbm_reset |= S_000E60_SOFT_RESET_MC(1); 819 if (G_000E50_MCDW_BUSY(RREG32(R_000E50_SRBM_STATUS))) 820 srbm_reset |= S_000E60_SOFT_RESET_MC(1); 821 if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS))) 822 srbm_reset |= S_000E60_SOFT_RESET_RLC(1); 823 if (G_000E50_SEM_BUSY(RREG32(R_000E50_SRBM_STATUS))) 824 srbm_reset |= S_000E60_SOFT_RESET_SEM(1); 825 if (G_000E50_BIF_BUSY(RREG32(R_000E50_SRBM_STATUS))) 826 srbm_reset |= S_000E60_SOFT_RESET_BIF(1); 827 dev_info(rdev->dev, " R_000E60_SRBM_SOFT_RESET=0x%08X\n", srbm_reset); 828 WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset); 829 (void)RREG32(R_000E60_SRBM_SOFT_RESET); 830 udelay(50); 831 WREG32(R_000E60_SRBM_SOFT_RESET, 0); 832 (void)RREG32(R_000E60_SRBM_SOFT_RESET); 833 WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset); 834 (void)RREG32(R_000E60_SRBM_SOFT_RESET); 835 udelay(50); 836 WREG32(R_000E60_SRBM_SOFT_RESET, 0); 837 (void)RREG32(R_000E60_SRBM_SOFT_RESET); 838 /* Wait a little for things to settle down */ 839 udelay(50); 840 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n", 841 RREG32(R_008010_GRBM_STATUS)); 842 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n", 843 RREG32(R_008014_GRBM_STATUS2)); 844 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n", 845 RREG32(R_000E50_SRBM_STATUS)); 846 /* After reset we need to reinit the asic as GPU often endup in an 847 * incoherent state. 848 */ 849 atom_asic_init(rdev->mode_info.atom_context); 850 rv515_mc_resume(rdev, &save); 851 return 0; 852 } 853 854 int r600_gpu_reset(struct radeon_device *rdev) 855 { 856 return r600_gpu_soft_reset(rdev); 857 } 858 859 static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes, 860 u32 num_backends, 861 u32 backend_disable_mask) 862 { 863 u32 backend_map = 0; 864 u32 enabled_backends_mask; 865 u32 enabled_backends_count; 866 u32 cur_pipe; 867 u32 swizzle_pipe[R6XX_MAX_PIPES]; 868 u32 cur_backend; 869 u32 i; 870 871 if (num_tile_pipes > R6XX_MAX_PIPES) 872 num_tile_pipes = R6XX_MAX_PIPES; 873 if (num_tile_pipes < 1) 874 num_tile_pipes = 1; 875 if (num_backends > R6XX_MAX_BACKENDS) 876 num_backends = R6XX_MAX_BACKENDS; 877 if (num_backends < 1) 878 num_backends = 1; 879 880 enabled_backends_mask = 0; 881 enabled_backends_count = 0; 882 for (i = 0; i < R6XX_MAX_BACKENDS; ++i) { 883 if (((backend_disable_mask >> i) & 1) == 0) { 884 enabled_backends_mask |= (1 << i); 885 ++enabled_backends_count; 886 } 887 if (enabled_backends_count == num_backends) 888 break; 889 } 890 891 if (enabled_backends_count == 0) { 892 enabled_backends_mask = 1; 893 enabled_backends_count = 1; 894 } 895 896 if (enabled_backends_count != num_backends) 897 num_backends = enabled_backends_count; 898 899 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES); 900 switch (num_tile_pipes) { 901 case 1: 902 swizzle_pipe[0] = 0; 903 break; 904 case 2: 905 swizzle_pipe[0] = 0; 906 swizzle_pipe[1] = 1; 907 break; 908 case 3: 909 swizzle_pipe[0] = 0; 910 swizzle_pipe[1] = 1; 911 swizzle_pipe[2] = 2; 912 break; 913 case 4: 914 swizzle_pipe[0] = 0; 915 swizzle_pipe[1] = 1; 916 swizzle_pipe[2] = 2; 917 swizzle_pipe[3] = 3; 918 break; 919 case 5: 920 swizzle_pipe[0] = 0; 921 swizzle_pipe[1] = 1; 922 swizzle_pipe[2] = 2; 923 swizzle_pipe[3] = 3; 924 swizzle_pipe[4] = 4; 925 break; 926 case 6: 927 swizzle_pipe[0] = 0; 928 swizzle_pipe[1] = 2; 929 swizzle_pipe[2] = 4; 930 swizzle_pipe[3] = 5; 931 swizzle_pipe[4] = 1; 932 swizzle_pipe[5] = 3; 933 break; 934 case 7: 935 swizzle_pipe[0] = 0; 936 swizzle_pipe[1] = 2; 937 swizzle_pipe[2] = 4; 938 swizzle_pipe[3] = 6; 939 swizzle_pipe[4] = 1; 940 swizzle_pipe[5] = 3; 941 swizzle_pipe[6] = 5; 942 break; 943 case 8: 944 swizzle_pipe[0] = 0; 945 swizzle_pipe[1] = 2; 946 swizzle_pipe[2] = 4; 947 swizzle_pipe[3] = 6; 948 swizzle_pipe[4] = 1; 949 swizzle_pipe[5] = 3; 950 swizzle_pipe[6] = 5; 951 swizzle_pipe[7] = 7; 952 break; 953 } 954 955 cur_backend = 0; 956 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) { 957 while (((1 << cur_backend) & enabled_backends_mask) == 0) 958 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS; 959 960 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2))); 961 962 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS; 963 } 964 965 return backend_map; 966 } 967 968 int r600_count_pipe_bits(uint32_t val) 969 { 970 int i, ret = 0; 971 972 for (i = 0; i < 32; i++) { 973 ret += val & 1; 974 val >>= 1; 975 } 976 return ret; 977 } 978 979 void r600_gpu_init(struct radeon_device *rdev) 980 { 981 u32 tiling_config; 982 u32 ramcfg; 983 u32 tmp; 984 int i, j; 985 u32 sq_config; 986 u32 sq_gpr_resource_mgmt_1 = 0; 987 u32 sq_gpr_resource_mgmt_2 = 0; 988 u32 sq_thread_resource_mgmt = 0; 989 u32 sq_stack_resource_mgmt_1 = 0; 990 u32 sq_stack_resource_mgmt_2 = 0; 991 992 /* FIXME: implement */ 993 switch (rdev->family) { 994 case CHIP_R600: 995 rdev->config.r600.max_pipes = 4; 996 rdev->config.r600.max_tile_pipes = 8; 997 rdev->config.r600.max_simds = 4; 998 rdev->config.r600.max_backends = 4; 999 rdev->config.r600.max_gprs = 256; 1000 rdev->config.r600.max_threads = 192; 1001 rdev->config.r600.max_stack_entries = 256; 1002 rdev->config.r600.max_hw_contexts = 8; 1003 rdev->config.r600.max_gs_threads = 16; 1004 rdev->config.r600.sx_max_export_size = 128; 1005 rdev->config.r600.sx_max_export_pos_size = 16; 1006 rdev->config.r600.sx_max_export_smx_size = 128; 1007 rdev->config.r600.sq_num_cf_insts = 2; 1008 break; 1009 case CHIP_RV630: 1010 case CHIP_RV635: 1011 rdev->config.r600.max_pipes = 2; 1012 rdev->config.r600.max_tile_pipes = 2; 1013 rdev->config.r600.max_simds = 3; 1014 rdev->config.r600.max_backends = 1; 1015 rdev->config.r600.max_gprs = 128; 1016 rdev->config.r600.max_threads = 192; 1017 rdev->config.r600.max_stack_entries = 128; 1018 rdev->config.r600.max_hw_contexts = 8; 1019 rdev->config.r600.max_gs_threads = 4; 1020 rdev->config.r600.sx_max_export_size = 128; 1021 rdev->config.r600.sx_max_export_pos_size = 16; 1022 rdev->config.r600.sx_max_export_smx_size = 128; 1023 rdev->config.r600.sq_num_cf_insts = 2; 1024 break; 1025 case CHIP_RV610: 1026 case CHIP_RV620: 1027 case CHIP_RS780: 1028 case CHIP_RS880: 1029 rdev->config.r600.max_pipes = 1; 1030 rdev->config.r600.max_tile_pipes = 1; 1031 rdev->config.r600.max_simds = 2; 1032 rdev->config.r600.max_backends = 1; 1033 rdev->config.r600.max_gprs = 128; 1034 rdev->config.r600.max_threads = 192; 1035 rdev->config.r600.max_stack_entries = 128; 1036 rdev->config.r600.max_hw_contexts = 4; 1037 rdev->config.r600.max_gs_threads = 4; 1038 rdev->config.r600.sx_max_export_size = 128; 1039 rdev->config.r600.sx_max_export_pos_size = 16; 1040 rdev->config.r600.sx_max_export_smx_size = 128; 1041 rdev->config.r600.sq_num_cf_insts = 1; 1042 break; 1043 case CHIP_RV670: 1044 rdev->config.r600.max_pipes = 4; 1045 rdev->config.r600.max_tile_pipes = 4; 1046 rdev->config.r600.max_simds = 4; 1047 rdev->config.r600.max_backends = 4; 1048 rdev->config.r600.max_gprs = 192; 1049 rdev->config.r600.max_threads = 192; 1050 rdev->config.r600.max_stack_entries = 256; 1051 rdev->config.r600.max_hw_contexts = 8; 1052 rdev->config.r600.max_gs_threads = 16; 1053 rdev->config.r600.sx_max_export_size = 128; 1054 rdev->config.r600.sx_max_export_pos_size = 16; 1055 rdev->config.r600.sx_max_export_smx_size = 128; 1056 rdev->config.r600.sq_num_cf_insts = 2; 1057 break; 1058 default: 1059 break; 1060 } 1061 1062 /* Initialize HDP */ 1063 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 1064 WREG32((0x2c14 + j), 0x00000000); 1065 WREG32((0x2c18 + j), 0x00000000); 1066 WREG32((0x2c1c + j), 0x00000000); 1067 WREG32((0x2c20 + j), 0x00000000); 1068 WREG32((0x2c24 + j), 0x00000000); 1069 } 1070 1071 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); 1072 1073 /* Setup tiling */ 1074 tiling_config = 0; 1075 ramcfg = RREG32(RAMCFG); 1076 switch (rdev->config.r600.max_tile_pipes) { 1077 case 1: 1078 tiling_config |= PIPE_TILING(0); 1079 break; 1080 case 2: 1081 tiling_config |= PIPE_TILING(1); 1082 break; 1083 case 4: 1084 tiling_config |= PIPE_TILING(2); 1085 break; 1086 case 8: 1087 tiling_config |= PIPE_TILING(3); 1088 break; 1089 default: 1090 break; 1091 } 1092 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); 1093 tiling_config |= GROUP_SIZE(0); 1094 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT; 1095 if (tmp > 3) { 1096 tiling_config |= ROW_TILING(3); 1097 tiling_config |= SAMPLE_SPLIT(3); 1098 } else { 1099 tiling_config |= ROW_TILING(tmp); 1100 tiling_config |= SAMPLE_SPLIT(tmp); 1101 } 1102 tiling_config |= BANK_SWAPS(1); 1103 tmp = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes, 1104 rdev->config.r600.max_backends, 1105 (0xff << rdev->config.r600.max_backends) & 0xff); 1106 tiling_config |= BACKEND_MAP(tmp); 1107 WREG32(GB_TILING_CONFIG, tiling_config); 1108 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff); 1109 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff); 1110 1111 tmp = BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK); 1112 WREG32(CC_RB_BACKEND_DISABLE, tmp); 1113 1114 /* Setup pipes */ 1115 tmp = INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK); 1116 tmp |= INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK); 1117 WREG32(CC_GC_SHADER_PIPE_CONFIG, tmp); 1118 WREG32(GC_USER_SHADER_PIPE_CONFIG, tmp); 1119 1120 tmp = R6XX_MAX_BACKENDS - r600_count_pipe_bits(tmp & INACTIVE_QD_PIPES_MASK); 1121 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK); 1122 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK); 1123 1124 /* Setup some CP states */ 1125 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b))); 1126 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40))); 1127 1128 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT | 1129 SYNC_WALKER | SYNC_ALIGNER)); 1130 /* Setup various GPU states */ 1131 if (rdev->family == CHIP_RV670) 1132 WREG32(ARB_GDEC_RD_CNTL, 0x00000021); 1133 1134 tmp = RREG32(SX_DEBUG_1); 1135 tmp |= SMX_EVENT_RELEASE; 1136 if ((rdev->family > CHIP_R600)) 1137 tmp |= ENABLE_NEW_SMX_ADDRESS; 1138 WREG32(SX_DEBUG_1, tmp); 1139 1140 if (((rdev->family) == CHIP_R600) || 1141 ((rdev->family) == CHIP_RV630) || 1142 ((rdev->family) == CHIP_RV610) || 1143 ((rdev->family) == CHIP_RV620) || 1144 ((rdev->family) == CHIP_RS780) || 1145 ((rdev->family) == CHIP_RS880)) { 1146 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE); 1147 } else { 1148 WREG32(DB_DEBUG, 0); 1149 } 1150 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) | 1151 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4))); 1152 1153 WREG32(PA_SC_MULTI_CHIP_CNTL, 0); 1154 WREG32(VGT_NUM_INSTANCES, 0); 1155 1156 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0)); 1157 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0)); 1158 1159 tmp = RREG32(SQ_MS_FIFO_SIZES); 1160 if (((rdev->family) == CHIP_RV610) || 1161 ((rdev->family) == CHIP_RV620) || 1162 ((rdev->family) == CHIP_RS780) || 1163 ((rdev->family) == CHIP_RS880)) { 1164 tmp = (CACHE_FIFO_SIZE(0xa) | 1165 FETCH_FIFO_HIWATER(0xa) | 1166 DONE_FIFO_HIWATER(0xe0) | 1167 ALU_UPDATE_FIFO_HIWATER(0x8)); 1168 } else if (((rdev->family) == CHIP_R600) || 1169 ((rdev->family) == CHIP_RV630)) { 1170 tmp &= ~DONE_FIFO_HIWATER(0xff); 1171 tmp |= DONE_FIFO_HIWATER(0x4); 1172 } 1173 WREG32(SQ_MS_FIFO_SIZES, tmp); 1174 1175 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT 1176 * should be adjusted as needed by the 2D/3D drivers. This just sets default values 1177 */ 1178 sq_config = RREG32(SQ_CONFIG); 1179 sq_config &= ~(PS_PRIO(3) | 1180 VS_PRIO(3) | 1181 GS_PRIO(3) | 1182 ES_PRIO(3)); 1183 sq_config |= (DX9_CONSTS | 1184 VC_ENABLE | 1185 PS_PRIO(0) | 1186 VS_PRIO(1) | 1187 GS_PRIO(2) | 1188 ES_PRIO(3)); 1189 1190 if ((rdev->family) == CHIP_R600) { 1191 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) | 1192 NUM_VS_GPRS(124) | 1193 NUM_CLAUSE_TEMP_GPRS(4)); 1194 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) | 1195 NUM_ES_GPRS(0)); 1196 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) | 1197 NUM_VS_THREADS(48) | 1198 NUM_GS_THREADS(4) | 1199 NUM_ES_THREADS(4)); 1200 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) | 1201 NUM_VS_STACK_ENTRIES(128)); 1202 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) | 1203 NUM_ES_STACK_ENTRIES(0)); 1204 } else if (((rdev->family) == CHIP_RV610) || 1205 ((rdev->family) == CHIP_RV620) || 1206 ((rdev->family) == CHIP_RS780) || 1207 ((rdev->family) == CHIP_RS880)) { 1208 /* no vertex cache */ 1209 sq_config &= ~VC_ENABLE; 1210 1211 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | 1212 NUM_VS_GPRS(44) | 1213 NUM_CLAUSE_TEMP_GPRS(2)); 1214 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | 1215 NUM_ES_GPRS(17)); 1216 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | 1217 NUM_VS_THREADS(78) | 1218 NUM_GS_THREADS(4) | 1219 NUM_ES_THREADS(31)); 1220 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | 1221 NUM_VS_STACK_ENTRIES(40)); 1222 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | 1223 NUM_ES_STACK_ENTRIES(16)); 1224 } else if (((rdev->family) == CHIP_RV630) || 1225 ((rdev->family) == CHIP_RV635)) { 1226 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | 1227 NUM_VS_GPRS(44) | 1228 NUM_CLAUSE_TEMP_GPRS(2)); 1229 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) | 1230 NUM_ES_GPRS(18)); 1231 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | 1232 NUM_VS_THREADS(78) | 1233 NUM_GS_THREADS(4) | 1234 NUM_ES_THREADS(31)); 1235 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | 1236 NUM_VS_STACK_ENTRIES(40)); 1237 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | 1238 NUM_ES_STACK_ENTRIES(16)); 1239 } else if ((rdev->family) == CHIP_RV670) { 1240 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | 1241 NUM_VS_GPRS(44) | 1242 NUM_CLAUSE_TEMP_GPRS(2)); 1243 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | 1244 NUM_ES_GPRS(17)); 1245 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | 1246 NUM_VS_THREADS(78) | 1247 NUM_GS_THREADS(4) | 1248 NUM_ES_THREADS(31)); 1249 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) | 1250 NUM_VS_STACK_ENTRIES(64)); 1251 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) | 1252 NUM_ES_STACK_ENTRIES(64)); 1253 } 1254 1255 WREG32(SQ_CONFIG, sq_config); 1256 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1); 1257 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2); 1258 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); 1259 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1); 1260 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2); 1261 1262 if (((rdev->family) == CHIP_RV610) || 1263 ((rdev->family) == CHIP_RV620) || 1264 ((rdev->family) == CHIP_RS780) || 1265 ((rdev->family) == CHIP_RS880)) { 1266 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY)); 1267 } else { 1268 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC)); 1269 } 1270 1271 /* More default values. 2D/3D driver should adjust as needed */ 1272 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) | 1273 S1_X(0x4) | S1_Y(0xc))); 1274 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) | 1275 S1_X(0x2) | S1_Y(0x2) | 1276 S2_X(0xa) | S2_Y(0x6) | 1277 S3_X(0x6) | S3_Y(0xa))); 1278 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) | 1279 S1_X(0x4) | S1_Y(0xc) | 1280 S2_X(0x1) | S2_Y(0x6) | 1281 S3_X(0xa) | S3_Y(0xe))); 1282 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) | 1283 S5_X(0x0) | S5_Y(0x0) | 1284 S6_X(0xb) | S6_Y(0x4) | 1285 S7_X(0x7) | S7_Y(0x8))); 1286 1287 WREG32(VGT_STRMOUT_EN, 0); 1288 tmp = rdev->config.r600.max_pipes * 16; 1289 switch (rdev->family) { 1290 case CHIP_RV610: 1291 case CHIP_RV620: 1292 case CHIP_RS780: 1293 case CHIP_RS880: 1294 tmp += 32; 1295 break; 1296 case CHIP_RV670: 1297 tmp += 128; 1298 break; 1299 default: 1300 break; 1301 } 1302 if (tmp > 256) { 1303 tmp = 256; 1304 } 1305 WREG32(VGT_ES_PER_GS, 128); 1306 WREG32(VGT_GS_PER_ES, tmp); 1307 WREG32(VGT_GS_PER_VS, 2); 1308 WREG32(VGT_GS_VERTEX_REUSE, 16); 1309 1310 /* more default values. 2D/3D driver should adjust as needed */ 1311 WREG32(PA_SC_LINE_STIPPLE_STATE, 0); 1312 WREG32(VGT_STRMOUT_EN, 0); 1313 WREG32(SX_MISC, 0); 1314 WREG32(PA_SC_MODE_CNTL, 0); 1315 WREG32(PA_SC_AA_CONFIG, 0); 1316 WREG32(PA_SC_LINE_STIPPLE, 0); 1317 WREG32(SPI_INPUT_Z, 0); 1318 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2)); 1319 WREG32(CB_COLOR7_FRAG, 0); 1320 1321 /* Clear render buffer base addresses */ 1322 WREG32(CB_COLOR0_BASE, 0); 1323 WREG32(CB_COLOR1_BASE, 0); 1324 WREG32(CB_COLOR2_BASE, 0); 1325 WREG32(CB_COLOR3_BASE, 0); 1326 WREG32(CB_COLOR4_BASE, 0); 1327 WREG32(CB_COLOR5_BASE, 0); 1328 WREG32(CB_COLOR6_BASE, 0); 1329 WREG32(CB_COLOR7_BASE, 0); 1330 WREG32(CB_COLOR7_FRAG, 0); 1331 1332 switch (rdev->family) { 1333 case CHIP_RV610: 1334 case CHIP_RV620: 1335 case CHIP_RS780: 1336 case CHIP_RS880: 1337 tmp = TC_L2_SIZE(8); 1338 break; 1339 case CHIP_RV630: 1340 case CHIP_RV635: 1341 tmp = TC_L2_SIZE(4); 1342 break; 1343 case CHIP_R600: 1344 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT; 1345 break; 1346 default: 1347 tmp = TC_L2_SIZE(0); 1348 break; 1349 } 1350 WREG32(TC_CNTL, tmp); 1351 1352 tmp = RREG32(HDP_HOST_PATH_CNTL); 1353 WREG32(HDP_HOST_PATH_CNTL, tmp); 1354 1355 tmp = RREG32(ARB_POP); 1356 tmp |= ENABLE_TC128; 1357 WREG32(ARB_POP, tmp); 1358 1359 WREG32(PA_SC_MULTI_CHIP_CNTL, 0); 1360 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | 1361 NUM_CLIP_SEQ(3))); 1362 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095)); 1363 } 1364 1365 1366 /* 1367 * Indirect registers accessor 1368 */ 1369 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg) 1370 { 1371 u32 r; 1372 1373 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); 1374 (void)RREG32(PCIE_PORT_INDEX); 1375 r = RREG32(PCIE_PORT_DATA); 1376 return r; 1377 } 1378 1379 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v) 1380 { 1381 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); 1382 (void)RREG32(PCIE_PORT_INDEX); 1383 WREG32(PCIE_PORT_DATA, (v)); 1384 (void)RREG32(PCIE_PORT_DATA); 1385 } 1386 1387 void r600_hdp_flush(struct radeon_device *rdev) 1388 { 1389 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); 1390 } 1391 1392 /* 1393 * CP & Ring 1394 */ 1395 void r600_cp_stop(struct radeon_device *rdev) 1396 { 1397 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); 1398 } 1399 1400 int r600_init_microcode(struct radeon_device *rdev) 1401 { 1402 struct platform_device *pdev; 1403 const char *chip_name; 1404 const char *rlc_chip_name; 1405 size_t pfp_req_size, me_req_size, rlc_req_size; 1406 char fw_name[30]; 1407 int err; 1408 1409 DRM_DEBUG("\n"); 1410 1411 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0); 1412 err = IS_ERR(pdev); 1413 if (err) { 1414 printk(KERN_ERR "radeon_cp: Failed to register firmware\n"); 1415 return -EINVAL; 1416 } 1417 1418 switch (rdev->family) { 1419 case CHIP_R600: 1420 chip_name = "R600"; 1421 rlc_chip_name = "R600"; 1422 break; 1423 case CHIP_RV610: 1424 chip_name = "RV610"; 1425 rlc_chip_name = "R600"; 1426 break; 1427 case CHIP_RV630: 1428 chip_name = "RV630"; 1429 rlc_chip_name = "R600"; 1430 break; 1431 case CHIP_RV620: 1432 chip_name = "RV620"; 1433 rlc_chip_name = "R600"; 1434 break; 1435 case CHIP_RV635: 1436 chip_name = "RV635"; 1437 rlc_chip_name = "R600"; 1438 break; 1439 case CHIP_RV670: 1440 chip_name = "RV670"; 1441 rlc_chip_name = "R600"; 1442 break; 1443 case CHIP_RS780: 1444 case CHIP_RS880: 1445 chip_name = "RS780"; 1446 rlc_chip_name = "R600"; 1447 break; 1448 case CHIP_RV770: 1449 chip_name = "RV770"; 1450 rlc_chip_name = "R700"; 1451 break; 1452 case CHIP_RV730: 1453 case CHIP_RV740: 1454 chip_name = "RV730"; 1455 rlc_chip_name = "R700"; 1456 break; 1457 case CHIP_RV710: 1458 chip_name = "RV710"; 1459 rlc_chip_name = "R700"; 1460 break; 1461 default: BUG(); 1462 } 1463 1464 if (rdev->family >= CHIP_RV770) { 1465 pfp_req_size = R700_PFP_UCODE_SIZE * 4; 1466 me_req_size = R700_PM4_UCODE_SIZE * 4; 1467 rlc_req_size = R700_RLC_UCODE_SIZE * 4; 1468 } else { 1469 pfp_req_size = PFP_UCODE_SIZE * 4; 1470 me_req_size = PM4_UCODE_SIZE * 12; 1471 rlc_req_size = RLC_UCODE_SIZE * 4; 1472 } 1473 1474 DRM_INFO("Loading %s Microcode\n", chip_name); 1475 1476 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name); 1477 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev); 1478 if (err) 1479 goto out; 1480 if (rdev->pfp_fw->size != pfp_req_size) { 1481 printk(KERN_ERR 1482 "r600_cp: Bogus length %zu in firmware \"%s\"\n", 1483 rdev->pfp_fw->size, fw_name); 1484 err = -EINVAL; 1485 goto out; 1486 } 1487 1488 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name); 1489 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev); 1490 if (err) 1491 goto out; 1492 if (rdev->me_fw->size != me_req_size) { 1493 printk(KERN_ERR 1494 "r600_cp: Bogus length %zu in firmware \"%s\"\n", 1495 rdev->me_fw->size, fw_name); 1496 err = -EINVAL; 1497 } 1498 1499 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name); 1500 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev); 1501 if (err) 1502 goto out; 1503 if (rdev->rlc_fw->size != rlc_req_size) { 1504 printk(KERN_ERR 1505 "r600_rlc: Bogus length %zu in firmware \"%s\"\n", 1506 rdev->rlc_fw->size, fw_name); 1507 err = -EINVAL; 1508 } 1509 1510 out: 1511 platform_device_unregister(pdev); 1512 1513 if (err) { 1514 if (err != -EINVAL) 1515 printk(KERN_ERR 1516 "r600_cp: Failed to load firmware \"%s\"\n", 1517 fw_name); 1518 release_firmware(rdev->pfp_fw); 1519 rdev->pfp_fw = NULL; 1520 release_firmware(rdev->me_fw); 1521 rdev->me_fw = NULL; 1522 release_firmware(rdev->rlc_fw); 1523 rdev->rlc_fw = NULL; 1524 } 1525 return err; 1526 } 1527 1528 static int r600_cp_load_microcode(struct radeon_device *rdev) 1529 { 1530 const __be32 *fw_data; 1531 int i; 1532 1533 if (!rdev->me_fw || !rdev->pfp_fw) 1534 return -EINVAL; 1535 1536 r600_cp_stop(rdev); 1537 1538 WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); 1539 1540 /* Reset cp */ 1541 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); 1542 RREG32(GRBM_SOFT_RESET); 1543 mdelay(15); 1544 WREG32(GRBM_SOFT_RESET, 0); 1545 1546 WREG32(CP_ME_RAM_WADDR, 0); 1547 1548 fw_data = (const __be32 *)rdev->me_fw->data; 1549 WREG32(CP_ME_RAM_WADDR, 0); 1550 for (i = 0; i < PM4_UCODE_SIZE * 3; i++) 1551 WREG32(CP_ME_RAM_DATA, 1552 be32_to_cpup(fw_data++)); 1553 1554 fw_data = (const __be32 *)rdev->pfp_fw->data; 1555 WREG32(CP_PFP_UCODE_ADDR, 0); 1556 for (i = 0; i < PFP_UCODE_SIZE; i++) 1557 WREG32(CP_PFP_UCODE_DATA, 1558 be32_to_cpup(fw_data++)); 1559 1560 WREG32(CP_PFP_UCODE_ADDR, 0); 1561 WREG32(CP_ME_RAM_WADDR, 0); 1562 WREG32(CP_ME_RAM_RADDR, 0); 1563 return 0; 1564 } 1565 1566 int r600_cp_start(struct radeon_device *rdev) 1567 { 1568 int r; 1569 uint32_t cp_me; 1570 1571 r = radeon_ring_lock(rdev, 7); 1572 if (r) { 1573 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 1574 return r; 1575 } 1576 radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5)); 1577 radeon_ring_write(rdev, 0x1); 1578 if (rdev->family < CHIP_RV770) { 1579 radeon_ring_write(rdev, 0x3); 1580 radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1); 1581 } else { 1582 radeon_ring_write(rdev, 0x0); 1583 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1); 1584 } 1585 radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); 1586 radeon_ring_write(rdev, 0); 1587 radeon_ring_write(rdev, 0); 1588 radeon_ring_unlock_commit(rdev); 1589 1590 cp_me = 0xff; 1591 WREG32(R_0086D8_CP_ME_CNTL, cp_me); 1592 return 0; 1593 } 1594 1595 int r600_cp_resume(struct radeon_device *rdev) 1596 { 1597 u32 tmp; 1598 u32 rb_bufsz; 1599 int r; 1600 1601 /* Reset cp */ 1602 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); 1603 RREG32(GRBM_SOFT_RESET); 1604 mdelay(15); 1605 WREG32(GRBM_SOFT_RESET, 0); 1606 1607 /* Set ring buffer size */ 1608 rb_bufsz = drm_order(rdev->cp.ring_size / 8); 1609 tmp = RB_NO_UPDATE | (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 1610 #ifdef __BIG_ENDIAN 1611 tmp |= BUF_SWAP_32BIT; 1612 #endif 1613 WREG32(CP_RB_CNTL, tmp); 1614 WREG32(CP_SEM_WAIT_TIMER, 0x4); 1615 1616 /* Set the write pointer delay */ 1617 WREG32(CP_RB_WPTR_DELAY, 0); 1618 1619 /* Initialize the ring buffer's read and write pointers */ 1620 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); 1621 WREG32(CP_RB_RPTR_WR, 0); 1622 WREG32(CP_RB_WPTR, 0); 1623 WREG32(CP_RB_RPTR_ADDR, rdev->cp.gpu_addr & 0xFFFFFFFF); 1624 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->cp.gpu_addr)); 1625 mdelay(1); 1626 WREG32(CP_RB_CNTL, tmp); 1627 1628 WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8); 1629 WREG32(CP_DEBUG, (1 << 27) | (1 << 28)); 1630 1631 rdev->cp.rptr = RREG32(CP_RB_RPTR); 1632 rdev->cp.wptr = RREG32(CP_RB_WPTR); 1633 1634 r600_cp_start(rdev); 1635 rdev->cp.ready = true; 1636 r = radeon_ring_test(rdev); 1637 if (r) { 1638 rdev->cp.ready = false; 1639 return r; 1640 } 1641 return 0; 1642 } 1643 1644 void r600_cp_commit(struct radeon_device *rdev) 1645 { 1646 WREG32(CP_RB_WPTR, rdev->cp.wptr); 1647 (void)RREG32(CP_RB_WPTR); 1648 } 1649 1650 void r600_ring_init(struct radeon_device *rdev, unsigned ring_size) 1651 { 1652 u32 rb_bufsz; 1653 1654 /* Align ring size */ 1655 rb_bufsz = drm_order(ring_size / 8); 1656 ring_size = (1 << (rb_bufsz + 1)) * 4; 1657 rdev->cp.ring_size = ring_size; 1658 rdev->cp.align_mask = 16 - 1; 1659 } 1660 1661 1662 /* 1663 * GPU scratch registers helpers function. 1664 */ 1665 void r600_scratch_init(struct radeon_device *rdev) 1666 { 1667 int i; 1668 1669 rdev->scratch.num_reg = 7; 1670 for (i = 0; i < rdev->scratch.num_reg; i++) { 1671 rdev->scratch.free[i] = true; 1672 rdev->scratch.reg[i] = SCRATCH_REG0 + (i * 4); 1673 } 1674 } 1675 1676 int r600_ring_test(struct radeon_device *rdev) 1677 { 1678 uint32_t scratch; 1679 uint32_t tmp = 0; 1680 unsigned i; 1681 int r; 1682 1683 r = radeon_scratch_get(rdev, &scratch); 1684 if (r) { 1685 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); 1686 return r; 1687 } 1688 WREG32(scratch, 0xCAFEDEAD); 1689 r = radeon_ring_lock(rdev, 3); 1690 if (r) { 1691 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 1692 radeon_scratch_free(rdev, scratch); 1693 return r; 1694 } 1695 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 1696 radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); 1697 radeon_ring_write(rdev, 0xDEADBEEF); 1698 radeon_ring_unlock_commit(rdev); 1699 for (i = 0; i < rdev->usec_timeout; i++) { 1700 tmp = RREG32(scratch); 1701 if (tmp == 0xDEADBEEF) 1702 break; 1703 DRM_UDELAY(1); 1704 } 1705 if (i < rdev->usec_timeout) { 1706 DRM_INFO("ring test succeeded in %d usecs\n", i); 1707 } else { 1708 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n", 1709 scratch, tmp); 1710 r = -EINVAL; 1711 } 1712 radeon_scratch_free(rdev, scratch); 1713 return r; 1714 } 1715 1716 void r600_wb_disable(struct radeon_device *rdev) 1717 { 1718 int r; 1719 1720 WREG32(SCRATCH_UMSK, 0); 1721 if (rdev->wb.wb_obj) { 1722 r = radeon_bo_reserve(rdev->wb.wb_obj, false); 1723 if (unlikely(r != 0)) 1724 return; 1725 radeon_bo_kunmap(rdev->wb.wb_obj); 1726 radeon_bo_unpin(rdev->wb.wb_obj); 1727 radeon_bo_unreserve(rdev->wb.wb_obj); 1728 } 1729 } 1730 1731 void r600_wb_fini(struct radeon_device *rdev) 1732 { 1733 r600_wb_disable(rdev); 1734 if (rdev->wb.wb_obj) { 1735 radeon_bo_unref(&rdev->wb.wb_obj); 1736 rdev->wb.wb = NULL; 1737 rdev->wb.wb_obj = NULL; 1738 } 1739 } 1740 1741 int r600_wb_enable(struct radeon_device *rdev) 1742 { 1743 int r; 1744 1745 if (rdev->wb.wb_obj == NULL) { 1746 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true, 1747 RADEON_GEM_DOMAIN_GTT, &rdev->wb.wb_obj); 1748 if (r) { 1749 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r); 1750 return r; 1751 } 1752 r = radeon_bo_reserve(rdev->wb.wb_obj, false); 1753 if (unlikely(r != 0)) { 1754 r600_wb_fini(rdev); 1755 return r; 1756 } 1757 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT, 1758 &rdev->wb.gpu_addr); 1759 if (r) { 1760 radeon_bo_unreserve(rdev->wb.wb_obj); 1761 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r); 1762 r600_wb_fini(rdev); 1763 return r; 1764 } 1765 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb); 1766 radeon_bo_unreserve(rdev->wb.wb_obj); 1767 if (r) { 1768 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r); 1769 r600_wb_fini(rdev); 1770 return r; 1771 } 1772 } 1773 WREG32(SCRATCH_ADDR, (rdev->wb.gpu_addr >> 8) & 0xFFFFFFFF); 1774 WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + 1024) & 0xFFFFFFFC); 1775 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + 1024) & 0xFF); 1776 WREG32(SCRATCH_UMSK, 0xff); 1777 return 0; 1778 } 1779 1780 void r600_fence_ring_emit(struct radeon_device *rdev, 1781 struct radeon_fence *fence) 1782 { 1783 /* Also consider EVENT_WRITE_EOP. it handles the interrupts + timestamps + events */ 1784 /* Emit fence sequence & fire IRQ */ 1785 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 1786 radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); 1787 radeon_ring_write(rdev, fence->seq); 1788 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */ 1789 radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0)); 1790 radeon_ring_write(rdev, RB_INT_STAT); 1791 } 1792 1793 int r600_copy_dma(struct radeon_device *rdev, 1794 uint64_t src_offset, 1795 uint64_t dst_offset, 1796 unsigned num_pages, 1797 struct radeon_fence *fence) 1798 { 1799 /* FIXME: implement */ 1800 return 0; 1801 } 1802 1803 int r600_copy_blit(struct radeon_device *rdev, 1804 uint64_t src_offset, uint64_t dst_offset, 1805 unsigned num_pages, struct radeon_fence *fence) 1806 { 1807 r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE); 1808 r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE); 1809 r600_blit_done_copy(rdev, fence); 1810 return 0; 1811 } 1812 1813 int r600_set_surface_reg(struct radeon_device *rdev, int reg, 1814 uint32_t tiling_flags, uint32_t pitch, 1815 uint32_t offset, uint32_t obj_size) 1816 { 1817 /* FIXME: implement */ 1818 return 0; 1819 } 1820 1821 void r600_clear_surface_reg(struct radeon_device *rdev, int reg) 1822 { 1823 /* FIXME: implement */ 1824 } 1825 1826 1827 bool r600_card_posted(struct radeon_device *rdev) 1828 { 1829 uint32_t reg; 1830 1831 /* first check CRTCs */ 1832 reg = RREG32(D1CRTC_CONTROL) | 1833 RREG32(D2CRTC_CONTROL); 1834 if (reg & CRTC_EN) 1835 return true; 1836 1837 /* then check MEM_SIZE, in case the crtcs are off */ 1838 if (RREG32(CONFIG_MEMSIZE)) 1839 return true; 1840 1841 return false; 1842 } 1843 1844 int r600_startup(struct radeon_device *rdev) 1845 { 1846 int r; 1847 1848 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { 1849 r = r600_init_microcode(rdev); 1850 if (r) { 1851 DRM_ERROR("Failed to load firmware!\n"); 1852 return r; 1853 } 1854 } 1855 1856 r600_mc_program(rdev); 1857 if (rdev->flags & RADEON_IS_AGP) { 1858 r600_agp_enable(rdev); 1859 } else { 1860 r = r600_pcie_gart_enable(rdev); 1861 if (r) 1862 return r; 1863 } 1864 r600_gpu_init(rdev); 1865 1866 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); 1867 if (unlikely(r != 0)) 1868 return r; 1869 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM, 1870 &rdev->r600_blit.shader_gpu_addr); 1871 radeon_bo_unreserve(rdev->r600_blit.shader_obj); 1872 if (r) { 1873 dev_err(rdev->dev, "(%d) pin blit object failed\n", r); 1874 return r; 1875 } 1876 1877 /* Enable IRQ */ 1878 r = r600_irq_init(rdev); 1879 if (r) { 1880 DRM_ERROR("radeon: IH init failed (%d).\n", r); 1881 radeon_irq_kms_fini(rdev); 1882 return r; 1883 } 1884 r600_irq_set(rdev); 1885 1886 r = radeon_ring_init(rdev, rdev->cp.ring_size); 1887 if (r) 1888 return r; 1889 r = r600_cp_load_microcode(rdev); 1890 if (r) 1891 return r; 1892 r = r600_cp_resume(rdev); 1893 if (r) 1894 return r; 1895 /* write back buffer are not vital so don't worry about failure */ 1896 r600_wb_enable(rdev); 1897 return 0; 1898 } 1899 1900 void r600_vga_set_state(struct radeon_device *rdev, bool state) 1901 { 1902 uint32_t temp; 1903 1904 temp = RREG32(CONFIG_CNTL); 1905 if (state == false) { 1906 temp &= ~(1<<0); 1907 temp |= (1<<1); 1908 } else { 1909 temp &= ~(1<<1); 1910 } 1911 WREG32(CONFIG_CNTL, temp); 1912 } 1913 1914 int r600_resume(struct radeon_device *rdev) 1915 { 1916 int r; 1917 1918 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw, 1919 * posting will perform necessary task to bring back GPU into good 1920 * shape. 1921 */ 1922 /* post card */ 1923 atom_asic_init(rdev->mode_info.atom_context); 1924 /* Initialize clocks */ 1925 r = radeon_clocks_init(rdev); 1926 if (r) { 1927 return r; 1928 } 1929 1930 r = r600_startup(rdev); 1931 if (r) { 1932 DRM_ERROR("r600 startup failed on resume\n"); 1933 return r; 1934 } 1935 1936 r = r600_ib_test(rdev); 1937 if (r) { 1938 DRM_ERROR("radeon: failled testing IB (%d).\n", r); 1939 return r; 1940 } 1941 return r; 1942 } 1943 1944 int r600_suspend(struct radeon_device *rdev) 1945 { 1946 int r; 1947 1948 /* FIXME: we should wait for ring to be empty */ 1949 r600_cp_stop(rdev); 1950 rdev->cp.ready = false; 1951 r600_wb_disable(rdev); 1952 r600_pcie_gart_disable(rdev); 1953 /* unpin shaders bo */ 1954 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); 1955 if (unlikely(r != 0)) 1956 return r; 1957 radeon_bo_unpin(rdev->r600_blit.shader_obj); 1958 radeon_bo_unreserve(rdev->r600_blit.shader_obj); 1959 return 0; 1960 } 1961 1962 /* Plan is to move initialization in that function and use 1963 * helper function so that radeon_device_init pretty much 1964 * do nothing more than calling asic specific function. This 1965 * should also allow to remove a bunch of callback function 1966 * like vram_info. 1967 */ 1968 int r600_init(struct radeon_device *rdev) 1969 { 1970 int r; 1971 1972 r = radeon_dummy_page_init(rdev); 1973 if (r) 1974 return r; 1975 if (r600_debugfs_mc_info_init(rdev)) { 1976 DRM_ERROR("Failed to register debugfs file for mc !\n"); 1977 } 1978 /* This don't do much */ 1979 r = radeon_gem_init(rdev); 1980 if (r) 1981 return r; 1982 /* Read BIOS */ 1983 if (!radeon_get_bios(rdev)) { 1984 if (ASIC_IS_AVIVO(rdev)) 1985 return -EINVAL; 1986 } 1987 /* Must be an ATOMBIOS */ 1988 if (!rdev->is_atom_bios) { 1989 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n"); 1990 return -EINVAL; 1991 } 1992 r = radeon_atombios_init(rdev); 1993 if (r) 1994 return r; 1995 /* Post card if necessary */ 1996 if (!r600_card_posted(rdev)) { 1997 if (!rdev->bios) { 1998 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); 1999 return -EINVAL; 2000 } 2001 DRM_INFO("GPU not posted. posting now...\n"); 2002 atom_asic_init(rdev->mode_info.atom_context); 2003 } 2004 /* Initialize scratch registers */ 2005 r600_scratch_init(rdev); 2006 /* Initialize surface registers */ 2007 radeon_surface_init(rdev); 2008 /* Initialize clocks */ 2009 radeon_get_clock_info(rdev->ddev); 2010 r = radeon_clocks_init(rdev); 2011 if (r) 2012 return r; 2013 /* Initialize power management */ 2014 radeon_pm_init(rdev); 2015 /* Fence driver */ 2016 r = radeon_fence_driver_init(rdev); 2017 if (r) 2018 return r; 2019 r = r600_mc_init(rdev); 2020 if (r) 2021 return r; 2022 /* Memory manager */ 2023 r = radeon_bo_init(rdev); 2024 if (r) 2025 return r; 2026 2027 r = radeon_irq_kms_init(rdev); 2028 if (r) 2029 return r; 2030 2031 rdev->cp.ring_obj = NULL; 2032 r600_ring_init(rdev, 1024 * 1024); 2033 2034 rdev->ih.ring_obj = NULL; 2035 r600_ih_ring_init(rdev, 64 * 1024); 2036 2037 r = r600_pcie_gart_init(rdev); 2038 if (r) 2039 return r; 2040 2041 r = r600_blit_init(rdev); 2042 if (r) { 2043 DRM_ERROR("radeon: failed blitter (%d).\n", r); 2044 return r; 2045 } 2046 2047 rdev->accel_working = true; 2048 r = r600_startup(rdev); 2049 if (r) { 2050 r600_suspend(rdev); 2051 r600_wb_fini(rdev); 2052 radeon_ring_fini(rdev); 2053 r600_pcie_gart_fini(rdev); 2054 rdev->accel_working = false; 2055 } 2056 if (rdev->accel_working) { 2057 r = radeon_ib_pool_init(rdev); 2058 if (r) { 2059 DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r); 2060 rdev->accel_working = false; 2061 } 2062 r = r600_ib_test(rdev); 2063 if (r) { 2064 DRM_ERROR("radeon: failed testing IB (%d).\n", r); 2065 rdev->accel_working = false; 2066 } 2067 } 2068 return 0; 2069 } 2070 2071 void r600_fini(struct radeon_device *rdev) 2072 { 2073 /* Suspend operations */ 2074 r600_suspend(rdev); 2075 2076 r600_blit_fini(rdev); 2077 r600_irq_fini(rdev); 2078 radeon_irq_kms_fini(rdev); 2079 radeon_ring_fini(rdev); 2080 r600_wb_fini(rdev); 2081 r600_pcie_gart_fini(rdev); 2082 radeon_gem_fini(rdev); 2083 radeon_fence_driver_fini(rdev); 2084 radeon_clocks_fini(rdev); 2085 if (rdev->flags & RADEON_IS_AGP) 2086 radeon_agp_fini(rdev); 2087 radeon_bo_fini(rdev); 2088 radeon_atombios_fini(rdev); 2089 kfree(rdev->bios); 2090 rdev->bios = NULL; 2091 radeon_dummy_page_fini(rdev); 2092 } 2093 2094 2095 /* 2096 * CS stuff 2097 */ 2098 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 2099 { 2100 /* FIXME: implement */ 2101 radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 2102 radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC); 2103 radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF); 2104 radeon_ring_write(rdev, ib->length_dw); 2105 } 2106 2107 int r600_ib_test(struct radeon_device *rdev) 2108 { 2109 struct radeon_ib *ib; 2110 uint32_t scratch; 2111 uint32_t tmp = 0; 2112 unsigned i; 2113 int r; 2114 2115 r = radeon_scratch_get(rdev, &scratch); 2116 if (r) { 2117 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); 2118 return r; 2119 } 2120 WREG32(scratch, 0xCAFEDEAD); 2121 r = radeon_ib_get(rdev, &ib); 2122 if (r) { 2123 DRM_ERROR("radeon: failed to get ib (%d).\n", r); 2124 return r; 2125 } 2126 ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1); 2127 ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 2128 ib->ptr[2] = 0xDEADBEEF; 2129 ib->ptr[3] = PACKET2(0); 2130 ib->ptr[4] = PACKET2(0); 2131 ib->ptr[5] = PACKET2(0); 2132 ib->ptr[6] = PACKET2(0); 2133 ib->ptr[7] = PACKET2(0); 2134 ib->ptr[8] = PACKET2(0); 2135 ib->ptr[9] = PACKET2(0); 2136 ib->ptr[10] = PACKET2(0); 2137 ib->ptr[11] = PACKET2(0); 2138 ib->ptr[12] = PACKET2(0); 2139 ib->ptr[13] = PACKET2(0); 2140 ib->ptr[14] = PACKET2(0); 2141 ib->ptr[15] = PACKET2(0); 2142 ib->length_dw = 16; 2143 r = radeon_ib_schedule(rdev, ib); 2144 if (r) { 2145 radeon_scratch_free(rdev, scratch); 2146 radeon_ib_free(rdev, &ib); 2147 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); 2148 return r; 2149 } 2150 r = radeon_fence_wait(ib->fence, false); 2151 if (r) { 2152 DRM_ERROR("radeon: fence wait failed (%d).\n", r); 2153 return r; 2154 } 2155 for (i = 0; i < rdev->usec_timeout; i++) { 2156 tmp = RREG32(scratch); 2157 if (tmp == 0xDEADBEEF) 2158 break; 2159 DRM_UDELAY(1); 2160 } 2161 if (i < rdev->usec_timeout) { 2162 DRM_INFO("ib test succeeded in %u usecs\n", i); 2163 } else { 2164 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n", 2165 scratch, tmp); 2166 r = -EINVAL; 2167 } 2168 radeon_scratch_free(rdev, scratch); 2169 radeon_ib_free(rdev, &ib); 2170 return r; 2171 } 2172 2173 /* 2174 * Interrupts 2175 * 2176 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty 2177 * the same as the CP ring buffer, but in reverse. Rather than the CPU 2178 * writing to the ring and the GPU consuming, the GPU writes to the ring 2179 * and host consumes. As the host irq handler processes interrupts, it 2180 * increments the rptr. When the rptr catches up with the wptr, all the 2181 * current interrupts have been processed. 2182 */ 2183 2184 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size) 2185 { 2186 u32 rb_bufsz; 2187 2188 /* Align ring size */ 2189 rb_bufsz = drm_order(ring_size / 4); 2190 ring_size = (1 << rb_bufsz) * 4; 2191 rdev->ih.ring_size = ring_size; 2192 rdev->ih.align_mask = 4 - 1; 2193 } 2194 2195 static int r600_ih_ring_alloc(struct radeon_device *rdev, unsigned ring_size) 2196 { 2197 int r; 2198 2199 rdev->ih.ring_size = ring_size; 2200 /* Allocate ring buffer */ 2201 if (rdev->ih.ring_obj == NULL) { 2202 r = radeon_bo_create(rdev, NULL, rdev->ih.ring_size, 2203 true, 2204 RADEON_GEM_DOMAIN_GTT, 2205 &rdev->ih.ring_obj); 2206 if (r) { 2207 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r); 2208 return r; 2209 } 2210 r = radeon_bo_reserve(rdev->ih.ring_obj, false); 2211 if (unlikely(r != 0)) 2212 return r; 2213 r = radeon_bo_pin(rdev->ih.ring_obj, 2214 RADEON_GEM_DOMAIN_GTT, 2215 &rdev->ih.gpu_addr); 2216 if (r) { 2217 radeon_bo_unreserve(rdev->ih.ring_obj); 2218 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r); 2219 return r; 2220 } 2221 r = radeon_bo_kmap(rdev->ih.ring_obj, 2222 (void **)&rdev->ih.ring); 2223 radeon_bo_unreserve(rdev->ih.ring_obj); 2224 if (r) { 2225 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r); 2226 return r; 2227 } 2228 } 2229 rdev->ih.ptr_mask = (rdev->cp.ring_size / 4) - 1; 2230 rdev->ih.rptr = 0; 2231 2232 return 0; 2233 } 2234 2235 static void r600_ih_ring_fini(struct radeon_device *rdev) 2236 { 2237 int r; 2238 if (rdev->ih.ring_obj) { 2239 r = radeon_bo_reserve(rdev->ih.ring_obj, false); 2240 if (likely(r == 0)) { 2241 radeon_bo_kunmap(rdev->ih.ring_obj); 2242 radeon_bo_unpin(rdev->ih.ring_obj); 2243 radeon_bo_unreserve(rdev->ih.ring_obj); 2244 } 2245 radeon_bo_unref(&rdev->ih.ring_obj); 2246 rdev->ih.ring = NULL; 2247 rdev->ih.ring_obj = NULL; 2248 } 2249 } 2250 2251 static void r600_rlc_stop(struct radeon_device *rdev) 2252 { 2253 2254 if (rdev->family >= CHIP_RV770) { 2255 /* r7xx asics need to soft reset RLC before halting */ 2256 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC); 2257 RREG32(SRBM_SOFT_RESET); 2258 udelay(15000); 2259 WREG32(SRBM_SOFT_RESET, 0); 2260 RREG32(SRBM_SOFT_RESET); 2261 } 2262 2263 WREG32(RLC_CNTL, 0); 2264 } 2265 2266 static void r600_rlc_start(struct radeon_device *rdev) 2267 { 2268 WREG32(RLC_CNTL, RLC_ENABLE); 2269 } 2270 2271 static int r600_rlc_init(struct radeon_device *rdev) 2272 { 2273 u32 i; 2274 const __be32 *fw_data; 2275 2276 if (!rdev->rlc_fw) 2277 return -EINVAL; 2278 2279 r600_rlc_stop(rdev); 2280 2281 WREG32(RLC_HB_BASE, 0); 2282 WREG32(RLC_HB_CNTL, 0); 2283 WREG32(RLC_HB_RPTR, 0); 2284 WREG32(RLC_HB_WPTR, 0); 2285 WREG32(RLC_HB_WPTR_LSB_ADDR, 0); 2286 WREG32(RLC_HB_WPTR_MSB_ADDR, 0); 2287 WREG32(RLC_MC_CNTL, 0); 2288 WREG32(RLC_UCODE_CNTL, 0); 2289 2290 fw_data = (const __be32 *)rdev->rlc_fw->data; 2291 if (rdev->family >= CHIP_RV770) { 2292 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) { 2293 WREG32(RLC_UCODE_ADDR, i); 2294 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); 2295 } 2296 } else { 2297 for (i = 0; i < RLC_UCODE_SIZE; i++) { 2298 WREG32(RLC_UCODE_ADDR, i); 2299 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); 2300 } 2301 } 2302 WREG32(RLC_UCODE_ADDR, 0); 2303 2304 r600_rlc_start(rdev); 2305 2306 return 0; 2307 } 2308 2309 static void r600_enable_interrupts(struct radeon_device *rdev) 2310 { 2311 u32 ih_cntl = RREG32(IH_CNTL); 2312 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); 2313 2314 ih_cntl |= ENABLE_INTR; 2315 ih_rb_cntl |= IH_RB_ENABLE; 2316 WREG32(IH_CNTL, ih_cntl); 2317 WREG32(IH_RB_CNTL, ih_rb_cntl); 2318 rdev->ih.enabled = true; 2319 } 2320 2321 static void r600_disable_interrupts(struct radeon_device *rdev) 2322 { 2323 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); 2324 u32 ih_cntl = RREG32(IH_CNTL); 2325 2326 ih_rb_cntl &= ~IH_RB_ENABLE; 2327 ih_cntl &= ~ENABLE_INTR; 2328 WREG32(IH_RB_CNTL, ih_rb_cntl); 2329 WREG32(IH_CNTL, ih_cntl); 2330 /* set rptr, wptr to 0 */ 2331 WREG32(IH_RB_RPTR, 0); 2332 WREG32(IH_RB_WPTR, 0); 2333 rdev->ih.enabled = false; 2334 rdev->ih.wptr = 0; 2335 rdev->ih.rptr = 0; 2336 } 2337 2338 static void r600_disable_interrupt_state(struct radeon_device *rdev) 2339 { 2340 u32 tmp; 2341 2342 WREG32(CP_INT_CNTL, 0); 2343 WREG32(GRBM_INT_CNTL, 0); 2344 WREG32(DxMODE_INT_MASK, 0); 2345 if (ASIC_IS_DCE3(rdev)) { 2346 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0); 2347 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0); 2348 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; 2349 WREG32(DC_HPD1_INT_CONTROL, tmp); 2350 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY; 2351 WREG32(DC_HPD2_INT_CONTROL, tmp); 2352 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY; 2353 WREG32(DC_HPD3_INT_CONTROL, tmp); 2354 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY; 2355 WREG32(DC_HPD4_INT_CONTROL, tmp); 2356 if (ASIC_IS_DCE32(rdev)) { 2357 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; 2358 WREG32(DC_HPD5_INT_CONTROL, 0); 2359 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; 2360 WREG32(DC_HPD6_INT_CONTROL, 0); 2361 } 2362 } else { 2363 WREG32(DACA_AUTODETECT_INT_CONTROL, 0); 2364 WREG32(DACB_AUTODETECT_INT_CONTROL, 0); 2365 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; 2366 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, 0); 2367 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; 2368 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, 0); 2369 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; 2370 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, 0); 2371 } 2372 } 2373 2374 int r600_irq_init(struct radeon_device *rdev) 2375 { 2376 int ret = 0; 2377 int rb_bufsz; 2378 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; 2379 2380 /* allocate ring */ 2381 ret = r600_ih_ring_alloc(rdev, rdev->ih.ring_size); 2382 if (ret) 2383 return ret; 2384 2385 /* disable irqs */ 2386 r600_disable_interrupts(rdev); 2387 2388 /* init rlc */ 2389 ret = r600_rlc_init(rdev); 2390 if (ret) { 2391 r600_ih_ring_fini(rdev); 2392 return ret; 2393 } 2394 2395 /* setup interrupt control */ 2396 /* set dummy read address to ring address */ 2397 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8); 2398 interrupt_cntl = RREG32(INTERRUPT_CNTL); 2399 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi 2400 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN 2401 */ 2402 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE; 2403 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */ 2404 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN; 2405 WREG32(INTERRUPT_CNTL, interrupt_cntl); 2406 2407 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8); 2408 rb_bufsz = drm_order(rdev->ih.ring_size / 4); 2409 2410 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE | 2411 IH_WPTR_OVERFLOW_CLEAR | 2412 (rb_bufsz << 1)); 2413 /* WPTR writeback, not yet */ 2414 /*ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;*/ 2415 WREG32(IH_RB_WPTR_ADDR_LO, 0); 2416 WREG32(IH_RB_WPTR_ADDR_HI, 0); 2417 2418 WREG32(IH_RB_CNTL, ih_rb_cntl); 2419 2420 /* set rptr, wptr to 0 */ 2421 WREG32(IH_RB_RPTR, 0); 2422 WREG32(IH_RB_WPTR, 0); 2423 2424 /* Default settings for IH_CNTL (disabled at first) */ 2425 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10); 2426 /* RPTR_REARM only works if msi's are enabled */ 2427 if (rdev->msi_enabled) 2428 ih_cntl |= RPTR_REARM; 2429 2430 #ifdef __BIG_ENDIAN 2431 ih_cntl |= IH_MC_SWAP(IH_MC_SWAP_32BIT); 2432 #endif 2433 WREG32(IH_CNTL, ih_cntl); 2434 2435 /* force the active interrupt state to all disabled */ 2436 r600_disable_interrupt_state(rdev); 2437 2438 /* enable irqs */ 2439 r600_enable_interrupts(rdev); 2440 2441 return ret; 2442 } 2443 2444 void r600_irq_fini(struct radeon_device *rdev) 2445 { 2446 r600_disable_interrupts(rdev); 2447 r600_rlc_stop(rdev); 2448 r600_ih_ring_fini(rdev); 2449 } 2450 2451 int r600_irq_set(struct radeon_device *rdev) 2452 { 2453 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; 2454 u32 mode_int = 0; 2455 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0; 2456 2457 /* don't enable anything if the ih is disabled */ 2458 if (!rdev->ih.enabled) 2459 return 0; 2460 2461 if (ASIC_IS_DCE3(rdev)) { 2462 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN; 2463 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN; 2464 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN; 2465 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN; 2466 if (ASIC_IS_DCE32(rdev)) { 2467 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; 2468 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN; 2469 } 2470 } else { 2471 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN; 2472 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN; 2473 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN; 2474 } 2475 2476 if (rdev->irq.sw_int) { 2477 DRM_DEBUG("r600_irq_set: sw int\n"); 2478 cp_int_cntl |= RB_INT_ENABLE; 2479 } 2480 if (rdev->irq.crtc_vblank_int[0]) { 2481 DRM_DEBUG("r600_irq_set: vblank 0\n"); 2482 mode_int |= D1MODE_VBLANK_INT_MASK; 2483 } 2484 if (rdev->irq.crtc_vblank_int[1]) { 2485 DRM_DEBUG("r600_irq_set: vblank 1\n"); 2486 mode_int |= D2MODE_VBLANK_INT_MASK; 2487 } 2488 if (rdev->irq.hpd[0]) { 2489 DRM_DEBUG("r600_irq_set: hpd 1\n"); 2490 hpd1 |= DC_HPDx_INT_EN; 2491 } 2492 if (rdev->irq.hpd[1]) { 2493 DRM_DEBUG("r600_irq_set: hpd 2\n"); 2494 hpd2 |= DC_HPDx_INT_EN; 2495 } 2496 if (rdev->irq.hpd[2]) { 2497 DRM_DEBUG("r600_irq_set: hpd 3\n"); 2498 hpd3 |= DC_HPDx_INT_EN; 2499 } 2500 if (rdev->irq.hpd[3]) { 2501 DRM_DEBUG("r600_irq_set: hpd 4\n"); 2502 hpd4 |= DC_HPDx_INT_EN; 2503 } 2504 if (rdev->irq.hpd[4]) { 2505 DRM_DEBUG("r600_irq_set: hpd 5\n"); 2506 hpd5 |= DC_HPDx_INT_EN; 2507 } 2508 if (rdev->irq.hpd[5]) { 2509 DRM_DEBUG("r600_irq_set: hpd 6\n"); 2510 hpd6 |= DC_HPDx_INT_EN; 2511 } 2512 2513 WREG32(CP_INT_CNTL, cp_int_cntl); 2514 WREG32(DxMODE_INT_MASK, mode_int); 2515 if (ASIC_IS_DCE3(rdev)) { 2516 WREG32(DC_HPD1_INT_CONTROL, hpd1); 2517 WREG32(DC_HPD2_INT_CONTROL, hpd2); 2518 WREG32(DC_HPD3_INT_CONTROL, hpd3); 2519 WREG32(DC_HPD4_INT_CONTROL, hpd4); 2520 if (ASIC_IS_DCE32(rdev)) { 2521 WREG32(DC_HPD5_INT_CONTROL, hpd5); 2522 WREG32(DC_HPD6_INT_CONTROL, hpd6); 2523 } 2524 } else { 2525 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); 2526 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); 2527 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3); 2528 } 2529 2530 return 0; 2531 } 2532 2533 static inline void r600_irq_ack(struct radeon_device *rdev, 2534 u32 *disp_int, 2535 u32 *disp_int_cont, 2536 u32 *disp_int_cont2) 2537 { 2538 u32 tmp; 2539 2540 if (ASIC_IS_DCE3(rdev)) { 2541 *disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS); 2542 *disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE); 2543 *disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2); 2544 } else { 2545 *disp_int = RREG32(DISP_INTERRUPT_STATUS); 2546 *disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); 2547 *disp_int_cont2 = 0; 2548 } 2549 2550 if (*disp_int & LB_D1_VBLANK_INTERRUPT) 2551 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK); 2552 if (*disp_int & LB_D1_VLINE_INTERRUPT) 2553 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK); 2554 if (*disp_int & LB_D2_VBLANK_INTERRUPT) 2555 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK); 2556 if (*disp_int & LB_D2_VLINE_INTERRUPT) 2557 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK); 2558 if (*disp_int & DC_HPD1_INTERRUPT) { 2559 if (ASIC_IS_DCE3(rdev)) { 2560 tmp = RREG32(DC_HPD1_INT_CONTROL); 2561 tmp |= DC_HPDx_INT_ACK; 2562 WREG32(DC_HPD1_INT_CONTROL, tmp); 2563 } else { 2564 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); 2565 tmp |= DC_HPDx_INT_ACK; 2566 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 2567 } 2568 } 2569 if (*disp_int & DC_HPD2_INTERRUPT) { 2570 if (ASIC_IS_DCE3(rdev)) { 2571 tmp = RREG32(DC_HPD2_INT_CONTROL); 2572 tmp |= DC_HPDx_INT_ACK; 2573 WREG32(DC_HPD2_INT_CONTROL, tmp); 2574 } else { 2575 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); 2576 tmp |= DC_HPDx_INT_ACK; 2577 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 2578 } 2579 } 2580 if (*disp_int_cont & DC_HPD3_INTERRUPT) { 2581 if (ASIC_IS_DCE3(rdev)) { 2582 tmp = RREG32(DC_HPD3_INT_CONTROL); 2583 tmp |= DC_HPDx_INT_ACK; 2584 WREG32(DC_HPD3_INT_CONTROL, tmp); 2585 } else { 2586 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); 2587 tmp |= DC_HPDx_INT_ACK; 2588 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); 2589 } 2590 } 2591 if (*disp_int_cont & DC_HPD4_INTERRUPT) { 2592 tmp = RREG32(DC_HPD4_INT_CONTROL); 2593 tmp |= DC_HPDx_INT_ACK; 2594 WREG32(DC_HPD4_INT_CONTROL, tmp); 2595 } 2596 if (ASIC_IS_DCE32(rdev)) { 2597 if (*disp_int_cont2 & DC_HPD5_INTERRUPT) { 2598 tmp = RREG32(DC_HPD5_INT_CONTROL); 2599 tmp |= DC_HPDx_INT_ACK; 2600 WREG32(DC_HPD5_INT_CONTROL, tmp); 2601 } 2602 if (*disp_int_cont2 & DC_HPD6_INTERRUPT) { 2603 tmp = RREG32(DC_HPD5_INT_CONTROL); 2604 tmp |= DC_HPDx_INT_ACK; 2605 WREG32(DC_HPD6_INT_CONTROL, tmp); 2606 } 2607 } 2608 } 2609 2610 void r600_irq_disable(struct radeon_device *rdev) 2611 { 2612 u32 disp_int, disp_int_cont, disp_int_cont2; 2613 2614 r600_disable_interrupts(rdev); 2615 /* Wait and acknowledge irq */ 2616 mdelay(1); 2617 r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2); 2618 r600_disable_interrupt_state(rdev); 2619 } 2620 2621 static inline u32 r600_get_ih_wptr(struct radeon_device *rdev) 2622 { 2623 u32 wptr, tmp; 2624 2625 /* XXX use writeback */ 2626 wptr = RREG32(IH_RB_WPTR); 2627 2628 if (wptr & RB_OVERFLOW) { 2629 WARN_ON(1); 2630 /* XXX deal with overflow */ 2631 DRM_ERROR("IH RB overflow\n"); 2632 tmp = RREG32(IH_RB_CNTL); 2633 tmp |= IH_WPTR_OVERFLOW_CLEAR; 2634 WREG32(IH_RB_CNTL, tmp); 2635 } 2636 wptr = wptr & WPTR_OFFSET_MASK; 2637 2638 return wptr; 2639 } 2640 2641 /* r600 IV Ring 2642 * Each IV ring entry is 128 bits: 2643 * [7:0] - interrupt source id 2644 * [31:8] - reserved 2645 * [59:32] - interrupt source data 2646 * [127:60] - reserved 2647 * 2648 * The basic interrupt vector entries 2649 * are decoded as follows: 2650 * src_id src_data description 2651 * 1 0 D1 Vblank 2652 * 1 1 D1 Vline 2653 * 5 0 D2 Vblank 2654 * 5 1 D2 Vline 2655 * 19 0 FP Hot plug detection A 2656 * 19 1 FP Hot plug detection B 2657 * 19 2 DAC A auto-detection 2658 * 19 3 DAC B auto-detection 2659 * 176 - CP_INT RB 2660 * 177 - CP_INT IB1 2661 * 178 - CP_INT IB2 2662 * 181 - EOP Interrupt 2663 * 233 - GUI Idle 2664 * 2665 * Note, these are based on r600 and may need to be 2666 * adjusted or added to on newer asics 2667 */ 2668 2669 int r600_irq_process(struct radeon_device *rdev) 2670 { 2671 u32 wptr = r600_get_ih_wptr(rdev); 2672 u32 rptr = rdev->ih.rptr; 2673 u32 src_id, src_data; 2674 u32 last_entry = rdev->ih.ring_size - 16; 2675 u32 ring_index, disp_int, disp_int_cont, disp_int_cont2; 2676 unsigned long flags; 2677 bool queue_hotplug = false; 2678 2679 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr); 2680 2681 spin_lock_irqsave(&rdev->ih.lock, flags); 2682 2683 if (rptr == wptr) { 2684 spin_unlock_irqrestore(&rdev->ih.lock, flags); 2685 return IRQ_NONE; 2686 } 2687 if (rdev->shutdown) { 2688 spin_unlock_irqrestore(&rdev->ih.lock, flags); 2689 return IRQ_NONE; 2690 } 2691 2692 restart_ih: 2693 /* display interrupts */ 2694 r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2); 2695 2696 rdev->ih.wptr = wptr; 2697 while (rptr != wptr) { 2698 /* wptr/rptr are in bytes! */ 2699 ring_index = rptr / 4; 2700 src_id = rdev->ih.ring[ring_index] & 0xff; 2701 src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff; 2702 2703 switch (src_id) { 2704 case 1: /* D1 vblank/vline */ 2705 switch (src_data) { 2706 case 0: /* D1 vblank */ 2707 if (disp_int & LB_D1_VBLANK_INTERRUPT) { 2708 drm_handle_vblank(rdev->ddev, 0); 2709 disp_int &= ~LB_D1_VBLANK_INTERRUPT; 2710 DRM_DEBUG("IH: D1 vblank\n"); 2711 } 2712 break; 2713 case 1: /* D1 vline */ 2714 if (disp_int & LB_D1_VLINE_INTERRUPT) { 2715 disp_int &= ~LB_D1_VLINE_INTERRUPT; 2716 DRM_DEBUG("IH: D1 vline\n"); 2717 } 2718 break; 2719 default: 2720 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); 2721 break; 2722 } 2723 break; 2724 case 5: /* D2 vblank/vline */ 2725 switch (src_data) { 2726 case 0: /* D2 vblank */ 2727 if (disp_int & LB_D2_VBLANK_INTERRUPT) { 2728 drm_handle_vblank(rdev->ddev, 1); 2729 disp_int &= ~LB_D2_VBLANK_INTERRUPT; 2730 DRM_DEBUG("IH: D2 vblank\n"); 2731 } 2732 break; 2733 case 1: /* D1 vline */ 2734 if (disp_int & LB_D2_VLINE_INTERRUPT) { 2735 disp_int &= ~LB_D2_VLINE_INTERRUPT; 2736 DRM_DEBUG("IH: D2 vline\n"); 2737 } 2738 break; 2739 default: 2740 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); 2741 break; 2742 } 2743 break; 2744 case 19: /* HPD/DAC hotplug */ 2745 switch (src_data) { 2746 case 0: 2747 if (disp_int & DC_HPD1_INTERRUPT) { 2748 disp_int &= ~DC_HPD1_INTERRUPT; 2749 queue_hotplug = true; 2750 DRM_DEBUG("IH: HPD1\n"); 2751 } 2752 break; 2753 case 1: 2754 if (disp_int & DC_HPD2_INTERRUPT) { 2755 disp_int &= ~DC_HPD2_INTERRUPT; 2756 queue_hotplug = true; 2757 DRM_DEBUG("IH: HPD2\n"); 2758 } 2759 break; 2760 case 4: 2761 if (disp_int_cont & DC_HPD3_INTERRUPT) { 2762 disp_int_cont &= ~DC_HPD3_INTERRUPT; 2763 queue_hotplug = true; 2764 DRM_DEBUG("IH: HPD3\n"); 2765 } 2766 break; 2767 case 5: 2768 if (disp_int_cont & DC_HPD4_INTERRUPT) { 2769 disp_int_cont &= ~DC_HPD4_INTERRUPT; 2770 queue_hotplug = true; 2771 DRM_DEBUG("IH: HPD4\n"); 2772 } 2773 break; 2774 case 10: 2775 if (disp_int_cont2 & DC_HPD5_INTERRUPT) { 2776 disp_int_cont &= ~DC_HPD5_INTERRUPT; 2777 queue_hotplug = true; 2778 DRM_DEBUG("IH: HPD5\n"); 2779 } 2780 break; 2781 case 12: 2782 if (disp_int_cont2 & DC_HPD6_INTERRUPT) { 2783 disp_int_cont &= ~DC_HPD6_INTERRUPT; 2784 queue_hotplug = true; 2785 DRM_DEBUG("IH: HPD6\n"); 2786 } 2787 break; 2788 default: 2789 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); 2790 break; 2791 } 2792 break; 2793 case 176: /* CP_INT in ring buffer */ 2794 case 177: /* CP_INT in IB1 */ 2795 case 178: /* CP_INT in IB2 */ 2796 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data); 2797 radeon_fence_process(rdev); 2798 break; 2799 case 181: /* CP EOP event */ 2800 DRM_DEBUG("IH: CP EOP\n"); 2801 break; 2802 default: 2803 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); 2804 break; 2805 } 2806 2807 /* wptr/rptr are in bytes! */ 2808 if (rptr == last_entry) 2809 rptr = 0; 2810 else 2811 rptr += 16; 2812 } 2813 /* make sure wptr hasn't changed while processing */ 2814 wptr = r600_get_ih_wptr(rdev); 2815 if (wptr != rdev->ih.wptr) 2816 goto restart_ih; 2817 if (queue_hotplug) 2818 queue_work(rdev->wq, &rdev->hotplug_work); 2819 rdev->ih.rptr = rptr; 2820 WREG32(IH_RB_RPTR, rdev->ih.rptr); 2821 spin_unlock_irqrestore(&rdev->ih.lock, flags); 2822 return IRQ_HANDLED; 2823 } 2824 2825 /* 2826 * Debugfs info 2827 */ 2828 #if defined(CONFIG_DEBUG_FS) 2829 2830 static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data) 2831 { 2832 struct drm_info_node *node = (struct drm_info_node *) m->private; 2833 struct drm_device *dev = node->minor->dev; 2834 struct radeon_device *rdev = dev->dev_private; 2835 unsigned count, i, j; 2836 2837 radeon_ring_free_size(rdev); 2838 count = (rdev->cp.ring_size / 4) - rdev->cp.ring_free_dw; 2839 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT)); 2840 seq_printf(m, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR)); 2841 seq_printf(m, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR)); 2842 seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", rdev->cp.wptr); 2843 seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", rdev->cp.rptr); 2844 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw); 2845 seq_printf(m, "%u dwords in ring\n", count); 2846 i = rdev->cp.rptr; 2847 for (j = 0; j <= count; j++) { 2848 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]); 2849 i = (i + 1) & rdev->cp.ptr_mask; 2850 } 2851 return 0; 2852 } 2853 2854 static int r600_debugfs_mc_info(struct seq_file *m, void *data) 2855 { 2856 struct drm_info_node *node = (struct drm_info_node *) m->private; 2857 struct drm_device *dev = node->minor->dev; 2858 struct radeon_device *rdev = dev->dev_private; 2859 2860 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS); 2861 DREG32_SYS(m, rdev, VM_L2_STATUS); 2862 return 0; 2863 } 2864 2865 static struct drm_info_list r600_mc_info_list[] = { 2866 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL}, 2867 {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL}, 2868 }; 2869 #endif 2870 2871 int r600_debugfs_mc_info_init(struct radeon_device *rdev) 2872 { 2873 #if defined(CONFIG_DEBUG_FS) 2874 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list)); 2875 #else 2876 return 0; 2877 #endif 2878 } 2879