1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/slab.h> 29 #include <linux/seq_file.h> 30 #include <linux/firmware.h> 31 #include <linux/platform_device.h> 32 #include <linux/module.h> 33 #include <drm/drmP.h> 34 #include <drm/radeon_drm.h> 35 #include "radeon.h" 36 #include "radeon_asic.h" 37 #include "radeon_mode.h" 38 #include "r600d.h" 39 #include "atom.h" 40 #include "avivod.h" 41 #include "radeon_ucode.h" 42 43 /* Firmware Names */ 44 MODULE_FIRMWARE("radeon/R600_pfp.bin"); 45 MODULE_FIRMWARE("radeon/R600_me.bin"); 46 MODULE_FIRMWARE("radeon/RV610_pfp.bin"); 47 MODULE_FIRMWARE("radeon/RV610_me.bin"); 48 MODULE_FIRMWARE("radeon/RV630_pfp.bin"); 49 MODULE_FIRMWARE("radeon/RV630_me.bin"); 50 MODULE_FIRMWARE("radeon/RV620_pfp.bin"); 51 MODULE_FIRMWARE("radeon/RV620_me.bin"); 52 MODULE_FIRMWARE("radeon/RV635_pfp.bin"); 53 MODULE_FIRMWARE("radeon/RV635_me.bin"); 54 MODULE_FIRMWARE("radeon/RV670_pfp.bin"); 55 MODULE_FIRMWARE("radeon/RV670_me.bin"); 56 MODULE_FIRMWARE("radeon/RS780_pfp.bin"); 57 MODULE_FIRMWARE("radeon/RS780_me.bin"); 58 MODULE_FIRMWARE("radeon/RV770_pfp.bin"); 59 MODULE_FIRMWARE("radeon/RV770_me.bin"); 60 MODULE_FIRMWARE("radeon/RV770_smc.bin"); 61 MODULE_FIRMWARE("radeon/RV730_pfp.bin"); 62 MODULE_FIRMWARE("radeon/RV730_me.bin"); 63 MODULE_FIRMWARE("radeon/RV730_smc.bin"); 64 MODULE_FIRMWARE("radeon/RV740_smc.bin"); 65 MODULE_FIRMWARE("radeon/RV710_pfp.bin"); 66 MODULE_FIRMWARE("radeon/RV710_me.bin"); 67 MODULE_FIRMWARE("radeon/RV710_smc.bin"); 68 MODULE_FIRMWARE("radeon/R600_rlc.bin"); 69 MODULE_FIRMWARE("radeon/R700_rlc.bin"); 70 MODULE_FIRMWARE("radeon/CEDAR_pfp.bin"); 71 MODULE_FIRMWARE("radeon/CEDAR_me.bin"); 72 MODULE_FIRMWARE("radeon/CEDAR_rlc.bin"); 73 MODULE_FIRMWARE("radeon/CEDAR_smc.bin"); 74 MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin"); 75 MODULE_FIRMWARE("radeon/REDWOOD_me.bin"); 76 MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin"); 77 MODULE_FIRMWARE("radeon/REDWOOD_smc.bin"); 78 MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin"); 79 MODULE_FIRMWARE("radeon/JUNIPER_me.bin"); 80 MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin"); 81 MODULE_FIRMWARE("radeon/JUNIPER_smc.bin"); 82 MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin"); 83 MODULE_FIRMWARE("radeon/CYPRESS_me.bin"); 84 MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin"); 85 MODULE_FIRMWARE("radeon/CYPRESS_smc.bin"); 86 MODULE_FIRMWARE("radeon/PALM_pfp.bin"); 87 MODULE_FIRMWARE("radeon/PALM_me.bin"); 88 MODULE_FIRMWARE("radeon/SUMO_rlc.bin"); 89 MODULE_FIRMWARE("radeon/SUMO_pfp.bin"); 90 MODULE_FIRMWARE("radeon/SUMO_me.bin"); 91 MODULE_FIRMWARE("radeon/SUMO2_pfp.bin"); 92 MODULE_FIRMWARE("radeon/SUMO2_me.bin"); 93 94 static const u32 crtc_offsets[2] = 95 { 96 0, 97 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL 98 }; 99 100 int r600_debugfs_mc_info_init(struct radeon_device *rdev); 101 102 /* r600,rv610,rv630,rv620,rv635,rv670 */ 103 int r600_mc_wait_for_idle(struct radeon_device *rdev); 104 static void r600_gpu_init(struct radeon_device *rdev); 105 void r600_fini(struct radeon_device *rdev); 106 void r600_irq_disable(struct radeon_device *rdev); 107 static void r600_pcie_gen2_enable(struct radeon_device *rdev); 108 extern int evergreen_rlc_resume(struct radeon_device *rdev); 109 110 /** 111 * r600_get_xclk - get the xclk 112 * 113 * @rdev: radeon_device pointer 114 * 115 * Returns the reference clock used by the gfx engine 116 * (r6xx, IGPs, APUs). 117 */ 118 u32 r600_get_xclk(struct radeon_device *rdev) 119 { 120 return rdev->clock.spll.reference_freq; 121 } 122 123 /* get temperature in millidegrees */ 124 int rv6xx_get_temp(struct radeon_device *rdev) 125 { 126 u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >> 127 ASIC_T_SHIFT; 128 int actual_temp = temp & 0xff; 129 130 if (temp & 0x100) 131 actual_temp -= 256; 132 133 return actual_temp * 1000; 134 } 135 136 void r600_pm_get_dynpm_state(struct radeon_device *rdev) 137 { 138 int i; 139 140 rdev->pm.dynpm_can_upclock = true; 141 rdev->pm.dynpm_can_downclock = true; 142 143 /* power state array is low to high, default is first */ 144 if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) { 145 int min_power_state_index = 0; 146 147 if (rdev->pm.num_power_states > 2) 148 min_power_state_index = 1; 149 150 switch (rdev->pm.dynpm_planned_action) { 151 case DYNPM_ACTION_MINIMUM: 152 rdev->pm.requested_power_state_index = min_power_state_index; 153 rdev->pm.requested_clock_mode_index = 0; 154 rdev->pm.dynpm_can_downclock = false; 155 break; 156 case DYNPM_ACTION_DOWNCLOCK: 157 if (rdev->pm.current_power_state_index == min_power_state_index) { 158 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 159 rdev->pm.dynpm_can_downclock = false; 160 } else { 161 if (rdev->pm.active_crtc_count > 1) { 162 for (i = 0; i < rdev->pm.num_power_states; i++) { 163 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 164 continue; 165 else if (i >= rdev->pm.current_power_state_index) { 166 rdev->pm.requested_power_state_index = 167 rdev->pm.current_power_state_index; 168 break; 169 } else { 170 rdev->pm.requested_power_state_index = i; 171 break; 172 } 173 } 174 } else { 175 if (rdev->pm.current_power_state_index == 0) 176 rdev->pm.requested_power_state_index = 177 rdev->pm.num_power_states - 1; 178 else 179 rdev->pm.requested_power_state_index = 180 rdev->pm.current_power_state_index - 1; 181 } 182 } 183 rdev->pm.requested_clock_mode_index = 0; 184 /* don't use the power state if crtcs are active and no display flag is set */ 185 if ((rdev->pm.active_crtc_count > 0) && 186 (rdev->pm.power_state[rdev->pm.requested_power_state_index]. 187 clock_info[rdev->pm.requested_clock_mode_index].flags & 188 RADEON_PM_MODE_NO_DISPLAY)) { 189 rdev->pm.requested_power_state_index++; 190 } 191 break; 192 case DYNPM_ACTION_UPCLOCK: 193 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) { 194 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 195 rdev->pm.dynpm_can_upclock = false; 196 } else { 197 if (rdev->pm.active_crtc_count > 1) { 198 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) { 199 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 200 continue; 201 else if (i <= rdev->pm.current_power_state_index) { 202 rdev->pm.requested_power_state_index = 203 rdev->pm.current_power_state_index; 204 break; 205 } else { 206 rdev->pm.requested_power_state_index = i; 207 break; 208 } 209 } 210 } else 211 rdev->pm.requested_power_state_index = 212 rdev->pm.current_power_state_index + 1; 213 } 214 rdev->pm.requested_clock_mode_index = 0; 215 break; 216 case DYNPM_ACTION_DEFAULT: 217 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; 218 rdev->pm.requested_clock_mode_index = 0; 219 rdev->pm.dynpm_can_upclock = false; 220 break; 221 case DYNPM_ACTION_NONE: 222 default: 223 DRM_ERROR("Requested mode for not defined action\n"); 224 return; 225 } 226 } else { 227 /* XXX select a power state based on AC/DC, single/dualhead, etc. */ 228 /* for now just select the first power state and switch between clock modes */ 229 /* power state array is low to high, default is first (0) */ 230 if (rdev->pm.active_crtc_count > 1) { 231 rdev->pm.requested_power_state_index = -1; 232 /* start at 1 as we don't want the default mode */ 233 for (i = 1; i < rdev->pm.num_power_states; i++) { 234 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 235 continue; 236 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) || 237 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) { 238 rdev->pm.requested_power_state_index = i; 239 break; 240 } 241 } 242 /* if nothing selected, grab the default state. */ 243 if (rdev->pm.requested_power_state_index == -1) 244 rdev->pm.requested_power_state_index = 0; 245 } else 246 rdev->pm.requested_power_state_index = 1; 247 248 switch (rdev->pm.dynpm_planned_action) { 249 case DYNPM_ACTION_MINIMUM: 250 rdev->pm.requested_clock_mode_index = 0; 251 rdev->pm.dynpm_can_downclock = false; 252 break; 253 case DYNPM_ACTION_DOWNCLOCK: 254 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) { 255 if (rdev->pm.current_clock_mode_index == 0) { 256 rdev->pm.requested_clock_mode_index = 0; 257 rdev->pm.dynpm_can_downclock = false; 258 } else 259 rdev->pm.requested_clock_mode_index = 260 rdev->pm.current_clock_mode_index - 1; 261 } else { 262 rdev->pm.requested_clock_mode_index = 0; 263 rdev->pm.dynpm_can_downclock = false; 264 } 265 /* don't use the power state if crtcs are active and no display flag is set */ 266 if ((rdev->pm.active_crtc_count > 0) && 267 (rdev->pm.power_state[rdev->pm.requested_power_state_index]. 268 clock_info[rdev->pm.requested_clock_mode_index].flags & 269 RADEON_PM_MODE_NO_DISPLAY)) { 270 rdev->pm.requested_clock_mode_index++; 271 } 272 break; 273 case DYNPM_ACTION_UPCLOCK: 274 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) { 275 if (rdev->pm.current_clock_mode_index == 276 (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) { 277 rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index; 278 rdev->pm.dynpm_can_upclock = false; 279 } else 280 rdev->pm.requested_clock_mode_index = 281 rdev->pm.current_clock_mode_index + 1; 282 } else { 283 rdev->pm.requested_clock_mode_index = 284 rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1; 285 rdev->pm.dynpm_can_upclock = false; 286 } 287 break; 288 case DYNPM_ACTION_DEFAULT: 289 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; 290 rdev->pm.requested_clock_mode_index = 0; 291 rdev->pm.dynpm_can_upclock = false; 292 break; 293 case DYNPM_ACTION_NONE: 294 default: 295 DRM_ERROR("Requested mode for not defined action\n"); 296 return; 297 } 298 } 299 300 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n", 301 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 302 clock_info[rdev->pm.requested_clock_mode_index].sclk, 303 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 304 clock_info[rdev->pm.requested_clock_mode_index].mclk, 305 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 306 pcie_lanes); 307 } 308 309 void rs780_pm_init_profile(struct radeon_device *rdev) 310 { 311 if (rdev->pm.num_power_states == 2) { 312 /* default */ 313 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 314 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 315 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 316 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 317 /* low sh */ 318 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; 319 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; 320 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 321 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 322 /* mid sh */ 323 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; 324 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0; 325 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 326 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 327 /* high sh */ 328 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; 329 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1; 330 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 331 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 332 /* low mh */ 333 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; 334 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0; 335 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 336 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 337 /* mid mh */ 338 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; 339 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0; 340 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 341 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 342 /* high mh */ 343 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; 344 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1; 345 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 346 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 347 } else if (rdev->pm.num_power_states == 3) { 348 /* default */ 349 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 350 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 351 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 352 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 353 /* low sh */ 354 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1; 355 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1; 356 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 357 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 358 /* mid sh */ 359 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1; 360 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; 361 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 362 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 363 /* high sh */ 364 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1; 365 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2; 366 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 367 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 368 /* low mh */ 369 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1; 370 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1; 371 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 372 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 373 /* mid mh */ 374 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1; 375 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1; 376 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 377 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 378 /* high mh */ 379 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1; 380 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2; 381 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 382 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 383 } else { 384 /* default */ 385 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 386 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 387 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 388 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 389 /* low sh */ 390 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2; 391 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2; 392 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 393 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 394 /* mid sh */ 395 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2; 396 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2; 397 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 398 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 399 /* high sh */ 400 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2; 401 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3; 402 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 403 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 404 /* low mh */ 405 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2; 406 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0; 407 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 408 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 409 /* mid mh */ 410 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2; 411 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0; 412 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 413 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 414 /* high mh */ 415 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2; 416 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3; 417 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 418 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 419 } 420 } 421 422 void r600_pm_init_profile(struct radeon_device *rdev) 423 { 424 int idx; 425 426 if (rdev->family == CHIP_R600) { 427 /* XXX */ 428 /* default */ 429 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 430 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 431 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 432 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 433 /* low sh */ 434 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 435 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 436 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 437 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 438 /* mid sh */ 439 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 440 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 441 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 442 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 443 /* high sh */ 444 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 445 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 446 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 447 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 448 /* low mh */ 449 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 450 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 451 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 452 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 453 /* mid mh */ 454 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 455 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 456 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 457 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 458 /* high mh */ 459 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 460 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 461 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 462 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 463 } else { 464 if (rdev->pm.num_power_states < 4) { 465 /* default */ 466 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 467 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 468 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 469 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; 470 /* low sh */ 471 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1; 472 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1; 473 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 474 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 475 /* mid sh */ 476 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1; 477 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; 478 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 479 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; 480 /* high sh */ 481 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1; 482 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1; 483 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 484 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; 485 /* low mh */ 486 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2; 487 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2; 488 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 489 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 490 /* low mh */ 491 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2; 492 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2; 493 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 494 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; 495 /* high mh */ 496 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2; 497 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2; 498 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 499 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; 500 } else { 501 /* default */ 502 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 503 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 504 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 505 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; 506 /* low sh */ 507 if (rdev->flags & RADEON_IS_MOBILITY) 508 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0); 509 else 510 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); 511 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx; 512 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx; 513 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 514 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 515 /* mid sh */ 516 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx; 517 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx; 518 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 519 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; 520 /* high sh */ 521 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); 522 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx; 523 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx; 524 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 525 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; 526 /* low mh */ 527 if (rdev->flags & RADEON_IS_MOBILITY) 528 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1); 529 else 530 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1); 531 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx; 532 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx; 533 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 534 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 535 /* mid mh */ 536 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx; 537 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx; 538 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 539 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; 540 /* high mh */ 541 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1); 542 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx; 543 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx; 544 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 545 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; 546 } 547 } 548 } 549 550 void r600_pm_misc(struct radeon_device *rdev) 551 { 552 int req_ps_idx = rdev->pm.requested_power_state_index; 553 int req_cm_idx = rdev->pm.requested_clock_mode_index; 554 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx]; 555 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage; 556 557 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) { 558 /* 0xff01 is a flag rather then an actual voltage */ 559 if (voltage->voltage == 0xff01) 560 return; 561 if (voltage->voltage != rdev->pm.current_vddc) { 562 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); 563 rdev->pm.current_vddc = voltage->voltage; 564 DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage); 565 } 566 } 567 } 568 569 bool r600_gui_idle(struct radeon_device *rdev) 570 { 571 if (RREG32(GRBM_STATUS) & GUI_ACTIVE) 572 return false; 573 else 574 return true; 575 } 576 577 /* hpd for digital panel detect/disconnect */ 578 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) 579 { 580 bool connected = false; 581 582 if (ASIC_IS_DCE3(rdev)) { 583 switch (hpd) { 584 case RADEON_HPD_1: 585 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE) 586 connected = true; 587 break; 588 case RADEON_HPD_2: 589 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE) 590 connected = true; 591 break; 592 case RADEON_HPD_3: 593 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE) 594 connected = true; 595 break; 596 case RADEON_HPD_4: 597 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE) 598 connected = true; 599 break; 600 /* DCE 3.2 */ 601 case RADEON_HPD_5: 602 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE) 603 connected = true; 604 break; 605 case RADEON_HPD_6: 606 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE) 607 connected = true; 608 break; 609 default: 610 break; 611 } 612 } else { 613 switch (hpd) { 614 case RADEON_HPD_1: 615 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) 616 connected = true; 617 break; 618 case RADEON_HPD_2: 619 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) 620 connected = true; 621 break; 622 case RADEON_HPD_3: 623 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) 624 connected = true; 625 break; 626 default: 627 break; 628 } 629 } 630 return connected; 631 } 632 633 void r600_hpd_set_polarity(struct radeon_device *rdev, 634 enum radeon_hpd_id hpd) 635 { 636 u32 tmp; 637 bool connected = r600_hpd_sense(rdev, hpd); 638 639 if (ASIC_IS_DCE3(rdev)) { 640 switch (hpd) { 641 case RADEON_HPD_1: 642 tmp = RREG32(DC_HPD1_INT_CONTROL); 643 if (connected) 644 tmp &= ~DC_HPDx_INT_POLARITY; 645 else 646 tmp |= DC_HPDx_INT_POLARITY; 647 WREG32(DC_HPD1_INT_CONTROL, tmp); 648 break; 649 case RADEON_HPD_2: 650 tmp = RREG32(DC_HPD2_INT_CONTROL); 651 if (connected) 652 tmp &= ~DC_HPDx_INT_POLARITY; 653 else 654 tmp |= DC_HPDx_INT_POLARITY; 655 WREG32(DC_HPD2_INT_CONTROL, tmp); 656 break; 657 case RADEON_HPD_3: 658 tmp = RREG32(DC_HPD3_INT_CONTROL); 659 if (connected) 660 tmp &= ~DC_HPDx_INT_POLARITY; 661 else 662 tmp |= DC_HPDx_INT_POLARITY; 663 WREG32(DC_HPD3_INT_CONTROL, tmp); 664 break; 665 case RADEON_HPD_4: 666 tmp = RREG32(DC_HPD4_INT_CONTROL); 667 if (connected) 668 tmp &= ~DC_HPDx_INT_POLARITY; 669 else 670 tmp |= DC_HPDx_INT_POLARITY; 671 WREG32(DC_HPD4_INT_CONTROL, tmp); 672 break; 673 case RADEON_HPD_5: 674 tmp = RREG32(DC_HPD5_INT_CONTROL); 675 if (connected) 676 tmp &= ~DC_HPDx_INT_POLARITY; 677 else 678 tmp |= DC_HPDx_INT_POLARITY; 679 WREG32(DC_HPD5_INT_CONTROL, tmp); 680 break; 681 /* DCE 3.2 */ 682 case RADEON_HPD_6: 683 tmp = RREG32(DC_HPD6_INT_CONTROL); 684 if (connected) 685 tmp &= ~DC_HPDx_INT_POLARITY; 686 else 687 tmp |= DC_HPDx_INT_POLARITY; 688 WREG32(DC_HPD6_INT_CONTROL, tmp); 689 break; 690 default: 691 break; 692 } 693 } else { 694 switch (hpd) { 695 case RADEON_HPD_1: 696 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); 697 if (connected) 698 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; 699 else 700 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; 701 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 702 break; 703 case RADEON_HPD_2: 704 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); 705 if (connected) 706 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; 707 else 708 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; 709 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 710 break; 711 case RADEON_HPD_3: 712 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); 713 if (connected) 714 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; 715 else 716 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; 717 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); 718 break; 719 default: 720 break; 721 } 722 } 723 } 724 725 void r600_hpd_init(struct radeon_device *rdev) 726 { 727 struct drm_device *dev = rdev->ddev; 728 struct drm_connector *connector; 729 unsigned enable = 0; 730 731 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 732 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 733 734 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || 735 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { 736 /* don't try to enable hpd on eDP or LVDS avoid breaking the 737 * aux dp channel on imac and help (but not completely fix) 738 * https://bugzilla.redhat.com/show_bug.cgi?id=726143 739 */ 740 continue; 741 } 742 if (ASIC_IS_DCE3(rdev)) { 743 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa); 744 if (ASIC_IS_DCE32(rdev)) 745 tmp |= DC_HPDx_EN; 746 747 switch (radeon_connector->hpd.hpd) { 748 case RADEON_HPD_1: 749 WREG32(DC_HPD1_CONTROL, tmp); 750 break; 751 case RADEON_HPD_2: 752 WREG32(DC_HPD2_CONTROL, tmp); 753 break; 754 case RADEON_HPD_3: 755 WREG32(DC_HPD3_CONTROL, tmp); 756 break; 757 case RADEON_HPD_4: 758 WREG32(DC_HPD4_CONTROL, tmp); 759 break; 760 /* DCE 3.2 */ 761 case RADEON_HPD_5: 762 WREG32(DC_HPD5_CONTROL, tmp); 763 break; 764 case RADEON_HPD_6: 765 WREG32(DC_HPD6_CONTROL, tmp); 766 break; 767 default: 768 break; 769 } 770 } else { 771 switch (radeon_connector->hpd.hpd) { 772 case RADEON_HPD_1: 773 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN); 774 break; 775 case RADEON_HPD_2: 776 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN); 777 break; 778 case RADEON_HPD_3: 779 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN); 780 break; 781 default: 782 break; 783 } 784 } 785 enable |= 1 << radeon_connector->hpd.hpd; 786 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); 787 } 788 radeon_irq_kms_enable_hpd(rdev, enable); 789 } 790 791 void r600_hpd_fini(struct radeon_device *rdev) 792 { 793 struct drm_device *dev = rdev->ddev; 794 struct drm_connector *connector; 795 unsigned disable = 0; 796 797 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 798 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 799 if (ASIC_IS_DCE3(rdev)) { 800 switch (radeon_connector->hpd.hpd) { 801 case RADEON_HPD_1: 802 WREG32(DC_HPD1_CONTROL, 0); 803 break; 804 case RADEON_HPD_2: 805 WREG32(DC_HPD2_CONTROL, 0); 806 break; 807 case RADEON_HPD_3: 808 WREG32(DC_HPD3_CONTROL, 0); 809 break; 810 case RADEON_HPD_4: 811 WREG32(DC_HPD4_CONTROL, 0); 812 break; 813 /* DCE 3.2 */ 814 case RADEON_HPD_5: 815 WREG32(DC_HPD5_CONTROL, 0); 816 break; 817 case RADEON_HPD_6: 818 WREG32(DC_HPD6_CONTROL, 0); 819 break; 820 default: 821 break; 822 } 823 } else { 824 switch (radeon_connector->hpd.hpd) { 825 case RADEON_HPD_1: 826 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0); 827 break; 828 case RADEON_HPD_2: 829 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0); 830 break; 831 case RADEON_HPD_3: 832 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0); 833 break; 834 default: 835 break; 836 } 837 } 838 disable |= 1 << radeon_connector->hpd.hpd; 839 } 840 radeon_irq_kms_disable_hpd(rdev, disable); 841 } 842 843 /* 844 * R600 PCIE GART 845 */ 846 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev) 847 { 848 unsigned i; 849 u32 tmp; 850 851 /* flush hdp cache so updates hit vram */ 852 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) && 853 !(rdev->flags & RADEON_IS_AGP)) { 854 void __iomem *ptr = (void *)rdev->gart.ptr; 855 u32 tmp; 856 857 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read 858 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL 859 * This seems to cause problems on some AGP cards. Just use the old 860 * method for them. 861 */ 862 WREG32(HDP_DEBUG1, 0); 863 tmp = readl((void __iomem *)ptr); 864 } else 865 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); 866 867 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12); 868 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12); 869 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1)); 870 for (i = 0; i < rdev->usec_timeout; i++) { 871 /* read MC_STATUS */ 872 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE); 873 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT; 874 if (tmp == 2) { 875 printk(KERN_WARNING "[drm] r600 flush TLB failed\n"); 876 return; 877 } 878 if (tmp) { 879 return; 880 } 881 udelay(1); 882 } 883 } 884 885 int r600_pcie_gart_init(struct radeon_device *rdev) 886 { 887 int r; 888 889 if (rdev->gart.robj) { 890 WARN(1, "R600 PCIE GART already initialized\n"); 891 return 0; 892 } 893 /* Initialize common gart structure */ 894 r = radeon_gart_init(rdev); 895 if (r) 896 return r; 897 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; 898 return radeon_gart_table_vram_alloc(rdev); 899 } 900 901 static int r600_pcie_gart_enable(struct radeon_device *rdev) 902 { 903 u32 tmp; 904 int r, i; 905 906 if (rdev->gart.robj == NULL) { 907 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 908 return -EINVAL; 909 } 910 r = radeon_gart_table_vram_pin(rdev); 911 if (r) 912 return r; 913 radeon_gart_restore(rdev); 914 915 /* Setup L2 cache */ 916 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 917 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 918 EFFECTIVE_L2_QUEUE_SIZE(7)); 919 WREG32(VM_L2_CNTL2, 0); 920 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); 921 /* Setup TLB control */ 922 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | 923 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 924 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | 925 ENABLE_WAIT_L2_QUERY; 926 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); 927 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); 928 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); 929 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); 930 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); 931 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); 932 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); 933 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); 934 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); 935 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); 936 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); 937 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); 938 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 939 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 940 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); 941 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); 942 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); 943 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | 944 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); 945 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 946 (u32)(rdev->dummy_page.addr >> 12)); 947 for (i = 1; i < 7; i++) 948 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 949 950 r600_pcie_gart_tlb_flush(rdev); 951 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 952 (unsigned)(rdev->mc.gtt_size >> 20), 953 (unsigned long long)rdev->gart.table_addr); 954 rdev->gart.ready = true; 955 return 0; 956 } 957 958 static void r600_pcie_gart_disable(struct radeon_device *rdev) 959 { 960 u32 tmp; 961 int i; 962 963 /* Disable all tables */ 964 for (i = 0; i < 7; i++) 965 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 966 967 /* Disable L2 cache */ 968 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | 969 EFFECTIVE_L2_QUEUE_SIZE(7)); 970 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); 971 /* Setup L1 TLB control */ 972 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | 973 ENABLE_WAIT_L2_QUERY; 974 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); 975 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); 976 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); 977 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); 978 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); 979 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); 980 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); 981 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); 982 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp); 983 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp); 984 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); 985 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); 986 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp); 987 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); 988 radeon_gart_table_vram_unpin(rdev); 989 } 990 991 static void r600_pcie_gart_fini(struct radeon_device *rdev) 992 { 993 radeon_gart_fini(rdev); 994 r600_pcie_gart_disable(rdev); 995 radeon_gart_table_vram_free(rdev); 996 } 997 998 static void r600_agp_enable(struct radeon_device *rdev) 999 { 1000 u32 tmp; 1001 int i; 1002 1003 /* Setup L2 cache */ 1004 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 1005 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 1006 EFFECTIVE_L2_QUEUE_SIZE(7)); 1007 WREG32(VM_L2_CNTL2, 0); 1008 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); 1009 /* Setup TLB control */ 1010 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | 1011 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 1012 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | 1013 ENABLE_WAIT_L2_QUERY; 1014 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); 1015 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); 1016 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); 1017 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); 1018 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); 1019 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); 1020 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); 1021 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); 1022 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); 1023 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); 1024 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); 1025 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); 1026 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 1027 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 1028 for (i = 0; i < 7; i++) 1029 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 1030 } 1031 1032 int r600_mc_wait_for_idle(struct radeon_device *rdev) 1033 { 1034 unsigned i; 1035 u32 tmp; 1036 1037 for (i = 0; i < rdev->usec_timeout; i++) { 1038 /* read MC_STATUS */ 1039 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00; 1040 if (!tmp) 1041 return 0; 1042 udelay(1); 1043 } 1044 return -1; 1045 } 1046 1047 uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg) 1048 { 1049 uint32_t r; 1050 1051 WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg)); 1052 r = RREG32(R_0028FC_MC_DATA); 1053 WREG32(R_0028F8_MC_INDEX, ~C_0028F8_MC_IND_ADDR); 1054 return r; 1055 } 1056 1057 void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 1058 { 1059 WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg) | 1060 S_0028F8_MC_IND_WR_EN(1)); 1061 WREG32(R_0028FC_MC_DATA, v); 1062 WREG32(R_0028F8_MC_INDEX, 0x7F); 1063 } 1064 1065 static void r600_mc_program(struct radeon_device *rdev) 1066 { 1067 struct rv515_mc_save save; 1068 u32 tmp; 1069 int i, j; 1070 1071 /* Initialize HDP */ 1072 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 1073 WREG32((0x2c14 + j), 0x00000000); 1074 WREG32((0x2c18 + j), 0x00000000); 1075 WREG32((0x2c1c + j), 0x00000000); 1076 WREG32((0x2c20 + j), 0x00000000); 1077 WREG32((0x2c24 + j), 0x00000000); 1078 } 1079 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); 1080 1081 rv515_mc_stop(rdev, &save); 1082 if (r600_mc_wait_for_idle(rdev)) { 1083 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1084 } 1085 /* Lockout access through VGA aperture (doesn't exist before R600) */ 1086 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); 1087 /* Update configuration */ 1088 if (rdev->flags & RADEON_IS_AGP) { 1089 if (rdev->mc.vram_start < rdev->mc.gtt_start) { 1090 /* VRAM before AGP */ 1091 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 1092 rdev->mc.vram_start >> 12); 1093 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 1094 rdev->mc.gtt_end >> 12); 1095 } else { 1096 /* VRAM after AGP */ 1097 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 1098 rdev->mc.gtt_start >> 12); 1099 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 1100 rdev->mc.vram_end >> 12); 1101 } 1102 } else { 1103 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12); 1104 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12); 1105 } 1106 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); 1107 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; 1108 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); 1109 WREG32(MC_VM_FB_LOCATION, tmp); 1110 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); 1111 WREG32(HDP_NONSURFACE_INFO, (2 << 7)); 1112 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); 1113 if (rdev->flags & RADEON_IS_AGP) { 1114 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22); 1115 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22); 1116 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); 1117 } else { 1118 WREG32(MC_VM_AGP_BASE, 0); 1119 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); 1120 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); 1121 } 1122 if (r600_mc_wait_for_idle(rdev)) { 1123 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1124 } 1125 rv515_mc_resume(rdev, &save); 1126 /* we need to own VRAM, so turn off the VGA renderer here 1127 * to stop it overwriting our objects */ 1128 rv515_vga_render_disable(rdev); 1129 } 1130 1131 /** 1132 * r600_vram_gtt_location - try to find VRAM & GTT location 1133 * @rdev: radeon device structure holding all necessary informations 1134 * @mc: memory controller structure holding memory informations 1135 * 1136 * Function will place try to place VRAM at same place as in CPU (PCI) 1137 * address space as some GPU seems to have issue when we reprogram at 1138 * different address space. 1139 * 1140 * If there is not enough space to fit the unvisible VRAM after the 1141 * aperture then we limit the VRAM size to the aperture. 1142 * 1143 * If we are using AGP then place VRAM adjacent to AGP aperture are we need 1144 * them to be in one from GPU point of view so that we can program GPU to 1145 * catch access outside them (weird GPU policy see ??). 1146 * 1147 * This function will never fails, worst case are limiting VRAM or GTT. 1148 * 1149 * Note: GTT start, end, size should be initialized before calling this 1150 * function on AGP platform. 1151 */ 1152 static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) 1153 { 1154 u64 size_bf, size_af; 1155 1156 if (mc->mc_vram_size > 0xE0000000) { 1157 /* leave room for at least 512M GTT */ 1158 dev_warn(rdev->dev, "limiting VRAM\n"); 1159 mc->real_vram_size = 0xE0000000; 1160 mc->mc_vram_size = 0xE0000000; 1161 } 1162 if (rdev->flags & RADEON_IS_AGP) { 1163 size_bf = mc->gtt_start; 1164 size_af = mc->mc_mask - mc->gtt_end; 1165 if (size_bf > size_af) { 1166 if (mc->mc_vram_size > size_bf) { 1167 dev_warn(rdev->dev, "limiting VRAM\n"); 1168 mc->real_vram_size = size_bf; 1169 mc->mc_vram_size = size_bf; 1170 } 1171 mc->vram_start = mc->gtt_start - mc->mc_vram_size; 1172 } else { 1173 if (mc->mc_vram_size > size_af) { 1174 dev_warn(rdev->dev, "limiting VRAM\n"); 1175 mc->real_vram_size = size_af; 1176 mc->mc_vram_size = size_af; 1177 } 1178 mc->vram_start = mc->gtt_end + 1; 1179 } 1180 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 1181 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n", 1182 mc->mc_vram_size >> 20, mc->vram_start, 1183 mc->vram_end, mc->real_vram_size >> 20); 1184 } else { 1185 u64 base = 0; 1186 if (rdev->flags & RADEON_IS_IGP) { 1187 base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF; 1188 base <<= 24; 1189 } 1190 radeon_vram_location(rdev, &rdev->mc, base); 1191 rdev->mc.gtt_base_align = 0; 1192 radeon_gtt_location(rdev, mc); 1193 } 1194 } 1195 1196 static int r600_mc_init(struct radeon_device *rdev) 1197 { 1198 u32 tmp; 1199 int chansize, numchan; 1200 uint32_t h_addr, l_addr; 1201 unsigned long long k8_addr; 1202 1203 /* Get VRAM informations */ 1204 rdev->mc.vram_is_ddr = true; 1205 tmp = RREG32(RAMCFG); 1206 if (tmp & CHANSIZE_OVERRIDE) { 1207 chansize = 16; 1208 } else if (tmp & CHANSIZE_MASK) { 1209 chansize = 64; 1210 } else { 1211 chansize = 32; 1212 } 1213 tmp = RREG32(CHMAP); 1214 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { 1215 case 0: 1216 default: 1217 numchan = 1; 1218 break; 1219 case 1: 1220 numchan = 2; 1221 break; 1222 case 2: 1223 numchan = 4; 1224 break; 1225 case 3: 1226 numchan = 8; 1227 break; 1228 } 1229 rdev->mc.vram_width = numchan * chansize; 1230 /* Could aper size report 0 ? */ 1231 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); 1232 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); 1233 /* Setup GPU memory space */ 1234 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); 1235 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); 1236 rdev->mc.visible_vram_size = rdev->mc.aper_size; 1237 r600_vram_gtt_location(rdev, &rdev->mc); 1238 1239 if (rdev->flags & RADEON_IS_IGP) { 1240 rs690_pm_info(rdev); 1241 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); 1242 1243 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) { 1244 /* Use K8 direct mapping for fast fb access. */ 1245 rdev->fastfb_working = false; 1246 h_addr = G_000012_K8_ADDR_EXT(RREG32_MC(R_000012_MC_MISC_UMA_CNTL)); 1247 l_addr = RREG32_MC(R_000011_K8_FB_LOCATION); 1248 k8_addr = ((unsigned long long)h_addr) << 32 | l_addr; 1249 #if defined(CONFIG_X86_32) && !defined(CONFIG_X86_PAE) 1250 if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL) 1251 #endif 1252 { 1253 /* FastFB shall be used with UMA memory. Here it is simply disabled when sideport 1254 * memory is present. 1255 */ 1256 if (rdev->mc.igp_sideport_enabled == false && radeon_fastfb == 1) { 1257 DRM_INFO("Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n", 1258 (unsigned long long)rdev->mc.aper_base, k8_addr); 1259 rdev->mc.aper_base = (resource_size_t)k8_addr; 1260 rdev->fastfb_working = true; 1261 } 1262 } 1263 } 1264 } 1265 1266 radeon_update_bandwidth_info(rdev); 1267 return 0; 1268 } 1269 1270 int r600_vram_scratch_init(struct radeon_device *rdev) 1271 { 1272 int r; 1273 1274 if (rdev->vram_scratch.robj == NULL) { 1275 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, 1276 PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM, 1277 NULL, &rdev->vram_scratch.robj); 1278 if (r) { 1279 return r; 1280 } 1281 } 1282 1283 r = radeon_bo_reserve(rdev->vram_scratch.robj, false); 1284 if (unlikely(r != 0)) 1285 return r; 1286 r = radeon_bo_pin(rdev->vram_scratch.robj, 1287 RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr); 1288 if (r) { 1289 radeon_bo_unreserve(rdev->vram_scratch.robj); 1290 return r; 1291 } 1292 r = radeon_bo_kmap(rdev->vram_scratch.robj, 1293 (void **)&rdev->vram_scratch.ptr); 1294 if (r) 1295 radeon_bo_unpin(rdev->vram_scratch.robj); 1296 radeon_bo_unreserve(rdev->vram_scratch.robj); 1297 1298 return r; 1299 } 1300 1301 void r600_vram_scratch_fini(struct radeon_device *rdev) 1302 { 1303 int r; 1304 1305 if (rdev->vram_scratch.robj == NULL) { 1306 return; 1307 } 1308 r = radeon_bo_reserve(rdev->vram_scratch.robj, false); 1309 if (likely(r == 0)) { 1310 radeon_bo_kunmap(rdev->vram_scratch.robj); 1311 radeon_bo_unpin(rdev->vram_scratch.robj); 1312 radeon_bo_unreserve(rdev->vram_scratch.robj); 1313 } 1314 radeon_bo_unref(&rdev->vram_scratch.robj); 1315 } 1316 1317 void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung) 1318 { 1319 u32 tmp = RREG32(R600_BIOS_3_SCRATCH); 1320 1321 if (hung) 1322 tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG; 1323 else 1324 tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG; 1325 1326 WREG32(R600_BIOS_3_SCRATCH, tmp); 1327 } 1328 1329 static void r600_print_gpu_status_regs(struct radeon_device *rdev) 1330 { 1331 dev_info(rdev->dev, " R_008010_GRBM_STATUS = 0x%08X\n", 1332 RREG32(R_008010_GRBM_STATUS)); 1333 dev_info(rdev->dev, " R_008014_GRBM_STATUS2 = 0x%08X\n", 1334 RREG32(R_008014_GRBM_STATUS2)); 1335 dev_info(rdev->dev, " R_000E50_SRBM_STATUS = 0x%08X\n", 1336 RREG32(R_000E50_SRBM_STATUS)); 1337 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n", 1338 RREG32(CP_STALLED_STAT1)); 1339 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n", 1340 RREG32(CP_STALLED_STAT2)); 1341 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n", 1342 RREG32(CP_BUSY_STAT)); 1343 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n", 1344 RREG32(CP_STAT)); 1345 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n", 1346 RREG32(DMA_STATUS_REG)); 1347 } 1348 1349 static bool r600_is_display_hung(struct radeon_device *rdev) 1350 { 1351 u32 crtc_hung = 0; 1352 u32 crtc_status[2]; 1353 u32 i, j, tmp; 1354 1355 for (i = 0; i < rdev->num_crtc; i++) { 1356 if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN) { 1357 crtc_status[i] = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]); 1358 crtc_hung |= (1 << i); 1359 } 1360 } 1361 1362 for (j = 0; j < 10; j++) { 1363 for (i = 0; i < rdev->num_crtc; i++) { 1364 if (crtc_hung & (1 << i)) { 1365 tmp = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]); 1366 if (tmp != crtc_status[i]) 1367 crtc_hung &= ~(1 << i); 1368 } 1369 } 1370 if (crtc_hung == 0) 1371 return false; 1372 udelay(100); 1373 } 1374 1375 return true; 1376 } 1377 1378 static u32 r600_gpu_check_soft_reset(struct radeon_device *rdev) 1379 { 1380 u32 reset_mask = 0; 1381 u32 tmp; 1382 1383 /* GRBM_STATUS */ 1384 tmp = RREG32(R_008010_GRBM_STATUS); 1385 if (rdev->family >= CHIP_RV770) { 1386 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) | 1387 G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) | 1388 G_008010_TA_BUSY(tmp) | G_008010_VGT_BUSY(tmp) | 1389 G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) | 1390 G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp)) 1391 reset_mask |= RADEON_RESET_GFX; 1392 } else { 1393 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) | 1394 G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) | 1395 G_008010_TA03_BUSY(tmp) | G_008010_VGT_BUSY(tmp) | 1396 G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) | 1397 G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp)) 1398 reset_mask |= RADEON_RESET_GFX; 1399 } 1400 1401 if (G_008010_CF_RQ_PENDING(tmp) | G_008010_PF_RQ_PENDING(tmp) | 1402 G_008010_CP_BUSY(tmp) | G_008010_CP_COHERENCY_BUSY(tmp)) 1403 reset_mask |= RADEON_RESET_CP; 1404 1405 if (G_008010_GRBM_EE_BUSY(tmp)) 1406 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP; 1407 1408 /* DMA_STATUS_REG */ 1409 tmp = RREG32(DMA_STATUS_REG); 1410 if (!(tmp & DMA_IDLE)) 1411 reset_mask |= RADEON_RESET_DMA; 1412 1413 /* SRBM_STATUS */ 1414 tmp = RREG32(R_000E50_SRBM_STATUS); 1415 if (G_000E50_RLC_RQ_PENDING(tmp) | G_000E50_RLC_BUSY(tmp)) 1416 reset_mask |= RADEON_RESET_RLC; 1417 1418 if (G_000E50_IH_BUSY(tmp)) 1419 reset_mask |= RADEON_RESET_IH; 1420 1421 if (G_000E50_SEM_BUSY(tmp)) 1422 reset_mask |= RADEON_RESET_SEM; 1423 1424 if (G_000E50_GRBM_RQ_PENDING(tmp)) 1425 reset_mask |= RADEON_RESET_GRBM; 1426 1427 if (G_000E50_VMC_BUSY(tmp)) 1428 reset_mask |= RADEON_RESET_VMC; 1429 1430 if (G_000E50_MCB_BUSY(tmp) | G_000E50_MCDZ_BUSY(tmp) | 1431 G_000E50_MCDY_BUSY(tmp) | G_000E50_MCDX_BUSY(tmp) | 1432 G_000E50_MCDW_BUSY(tmp)) 1433 reset_mask |= RADEON_RESET_MC; 1434 1435 if (r600_is_display_hung(rdev)) 1436 reset_mask |= RADEON_RESET_DISPLAY; 1437 1438 /* Skip MC reset as it's mostly likely not hung, just busy */ 1439 if (reset_mask & RADEON_RESET_MC) { 1440 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask); 1441 reset_mask &= ~RADEON_RESET_MC; 1442 } 1443 1444 return reset_mask; 1445 } 1446 1447 static void r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) 1448 { 1449 struct rv515_mc_save save; 1450 u32 grbm_soft_reset = 0, srbm_soft_reset = 0; 1451 u32 tmp; 1452 1453 if (reset_mask == 0) 1454 return; 1455 1456 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask); 1457 1458 r600_print_gpu_status_regs(rdev); 1459 1460 /* Disable CP parsing/prefetching */ 1461 if (rdev->family >= CHIP_RV770) 1462 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1)); 1463 else 1464 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); 1465 1466 /* disable the RLC */ 1467 WREG32(RLC_CNTL, 0); 1468 1469 if (reset_mask & RADEON_RESET_DMA) { 1470 /* Disable DMA */ 1471 tmp = RREG32(DMA_RB_CNTL); 1472 tmp &= ~DMA_RB_ENABLE; 1473 WREG32(DMA_RB_CNTL, tmp); 1474 } 1475 1476 mdelay(50); 1477 1478 rv515_mc_stop(rdev, &save); 1479 if (r600_mc_wait_for_idle(rdev)) { 1480 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1481 } 1482 1483 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) { 1484 if (rdev->family >= CHIP_RV770) 1485 grbm_soft_reset |= S_008020_SOFT_RESET_DB(1) | 1486 S_008020_SOFT_RESET_CB(1) | 1487 S_008020_SOFT_RESET_PA(1) | 1488 S_008020_SOFT_RESET_SC(1) | 1489 S_008020_SOFT_RESET_SPI(1) | 1490 S_008020_SOFT_RESET_SX(1) | 1491 S_008020_SOFT_RESET_SH(1) | 1492 S_008020_SOFT_RESET_TC(1) | 1493 S_008020_SOFT_RESET_TA(1) | 1494 S_008020_SOFT_RESET_VC(1) | 1495 S_008020_SOFT_RESET_VGT(1); 1496 else 1497 grbm_soft_reset |= S_008020_SOFT_RESET_CR(1) | 1498 S_008020_SOFT_RESET_DB(1) | 1499 S_008020_SOFT_RESET_CB(1) | 1500 S_008020_SOFT_RESET_PA(1) | 1501 S_008020_SOFT_RESET_SC(1) | 1502 S_008020_SOFT_RESET_SMX(1) | 1503 S_008020_SOFT_RESET_SPI(1) | 1504 S_008020_SOFT_RESET_SX(1) | 1505 S_008020_SOFT_RESET_SH(1) | 1506 S_008020_SOFT_RESET_TC(1) | 1507 S_008020_SOFT_RESET_TA(1) | 1508 S_008020_SOFT_RESET_VC(1) | 1509 S_008020_SOFT_RESET_VGT(1); 1510 } 1511 1512 if (reset_mask & RADEON_RESET_CP) { 1513 grbm_soft_reset |= S_008020_SOFT_RESET_CP(1) | 1514 S_008020_SOFT_RESET_VGT(1); 1515 1516 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1); 1517 } 1518 1519 if (reset_mask & RADEON_RESET_DMA) { 1520 if (rdev->family >= CHIP_RV770) 1521 srbm_soft_reset |= RV770_SOFT_RESET_DMA; 1522 else 1523 srbm_soft_reset |= SOFT_RESET_DMA; 1524 } 1525 1526 if (reset_mask & RADEON_RESET_RLC) 1527 srbm_soft_reset |= S_000E60_SOFT_RESET_RLC(1); 1528 1529 if (reset_mask & RADEON_RESET_SEM) 1530 srbm_soft_reset |= S_000E60_SOFT_RESET_SEM(1); 1531 1532 if (reset_mask & RADEON_RESET_IH) 1533 srbm_soft_reset |= S_000E60_SOFT_RESET_IH(1); 1534 1535 if (reset_mask & RADEON_RESET_GRBM) 1536 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1); 1537 1538 if (!(rdev->flags & RADEON_IS_IGP)) { 1539 if (reset_mask & RADEON_RESET_MC) 1540 srbm_soft_reset |= S_000E60_SOFT_RESET_MC(1); 1541 } 1542 1543 if (reset_mask & RADEON_RESET_VMC) 1544 srbm_soft_reset |= S_000E60_SOFT_RESET_VMC(1); 1545 1546 if (grbm_soft_reset) { 1547 tmp = RREG32(R_008020_GRBM_SOFT_RESET); 1548 tmp |= grbm_soft_reset; 1549 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp); 1550 WREG32(R_008020_GRBM_SOFT_RESET, tmp); 1551 tmp = RREG32(R_008020_GRBM_SOFT_RESET); 1552 1553 udelay(50); 1554 1555 tmp &= ~grbm_soft_reset; 1556 WREG32(R_008020_GRBM_SOFT_RESET, tmp); 1557 tmp = RREG32(R_008020_GRBM_SOFT_RESET); 1558 } 1559 1560 if (srbm_soft_reset) { 1561 tmp = RREG32(SRBM_SOFT_RESET); 1562 tmp |= srbm_soft_reset; 1563 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1564 WREG32(SRBM_SOFT_RESET, tmp); 1565 tmp = RREG32(SRBM_SOFT_RESET); 1566 1567 udelay(50); 1568 1569 tmp &= ~srbm_soft_reset; 1570 WREG32(SRBM_SOFT_RESET, tmp); 1571 tmp = RREG32(SRBM_SOFT_RESET); 1572 } 1573 1574 /* Wait a little for things to settle down */ 1575 mdelay(1); 1576 1577 rv515_mc_resume(rdev, &save); 1578 udelay(50); 1579 1580 r600_print_gpu_status_regs(rdev); 1581 } 1582 1583 int r600_asic_reset(struct radeon_device *rdev) 1584 { 1585 u32 reset_mask; 1586 1587 reset_mask = r600_gpu_check_soft_reset(rdev); 1588 1589 if (reset_mask) 1590 r600_set_bios_scratch_engine_hung(rdev, true); 1591 1592 r600_gpu_soft_reset(rdev, reset_mask); 1593 1594 reset_mask = r600_gpu_check_soft_reset(rdev); 1595 1596 if (!reset_mask) 1597 r600_set_bios_scratch_engine_hung(rdev, false); 1598 1599 return 0; 1600 } 1601 1602 /** 1603 * r600_gfx_is_lockup - Check if the GFX engine is locked up 1604 * 1605 * @rdev: radeon_device pointer 1606 * @ring: radeon_ring structure holding ring information 1607 * 1608 * Check if the GFX engine is locked up. 1609 * Returns true if the engine appears to be locked up, false if not. 1610 */ 1611 bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 1612 { 1613 u32 reset_mask = r600_gpu_check_soft_reset(rdev); 1614 1615 if (!(reset_mask & (RADEON_RESET_GFX | 1616 RADEON_RESET_COMPUTE | 1617 RADEON_RESET_CP))) { 1618 radeon_ring_lockup_update(ring); 1619 return false; 1620 } 1621 /* force CP activities */ 1622 radeon_ring_force_activity(rdev, ring); 1623 return radeon_ring_test_lockup(rdev, ring); 1624 } 1625 1626 /** 1627 * r600_dma_is_lockup - Check if the DMA engine is locked up 1628 * 1629 * @rdev: radeon_device pointer 1630 * @ring: radeon_ring structure holding ring information 1631 * 1632 * Check if the async DMA engine is locked up. 1633 * Returns true if the engine appears to be locked up, false if not. 1634 */ 1635 bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 1636 { 1637 u32 reset_mask = r600_gpu_check_soft_reset(rdev); 1638 1639 if (!(reset_mask & RADEON_RESET_DMA)) { 1640 radeon_ring_lockup_update(ring); 1641 return false; 1642 } 1643 /* force ring activities */ 1644 radeon_ring_force_activity(rdev, ring); 1645 return radeon_ring_test_lockup(rdev, ring); 1646 } 1647 1648 u32 r6xx_remap_render_backend(struct radeon_device *rdev, 1649 u32 tiling_pipe_num, 1650 u32 max_rb_num, 1651 u32 total_max_rb_num, 1652 u32 disabled_rb_mask) 1653 { 1654 u32 rendering_pipe_num, rb_num_width, req_rb_num; 1655 u32 pipe_rb_ratio, pipe_rb_remain, tmp; 1656 u32 data = 0, mask = 1 << (max_rb_num - 1); 1657 unsigned i, j; 1658 1659 /* mask out the RBs that don't exist on that asic */ 1660 tmp = disabled_rb_mask | ((0xff << max_rb_num) & 0xff); 1661 /* make sure at least one RB is available */ 1662 if ((tmp & 0xff) != 0xff) 1663 disabled_rb_mask = tmp; 1664 1665 rendering_pipe_num = 1 << tiling_pipe_num; 1666 req_rb_num = total_max_rb_num - r600_count_pipe_bits(disabled_rb_mask); 1667 BUG_ON(rendering_pipe_num < req_rb_num); 1668 1669 pipe_rb_ratio = rendering_pipe_num / req_rb_num; 1670 pipe_rb_remain = rendering_pipe_num - pipe_rb_ratio * req_rb_num; 1671 1672 if (rdev->family <= CHIP_RV740) { 1673 /* r6xx/r7xx */ 1674 rb_num_width = 2; 1675 } else { 1676 /* eg+ */ 1677 rb_num_width = 4; 1678 } 1679 1680 for (i = 0; i < max_rb_num; i++) { 1681 if (!(mask & disabled_rb_mask)) { 1682 for (j = 0; j < pipe_rb_ratio; j++) { 1683 data <<= rb_num_width; 1684 data |= max_rb_num - i - 1; 1685 } 1686 if (pipe_rb_remain) { 1687 data <<= rb_num_width; 1688 data |= max_rb_num - i - 1; 1689 pipe_rb_remain--; 1690 } 1691 } 1692 mask >>= 1; 1693 } 1694 1695 return data; 1696 } 1697 1698 int r600_count_pipe_bits(uint32_t val) 1699 { 1700 return hweight32(val); 1701 } 1702 1703 static void r600_gpu_init(struct radeon_device *rdev) 1704 { 1705 u32 tiling_config; 1706 u32 ramcfg; 1707 u32 cc_rb_backend_disable; 1708 u32 cc_gc_shader_pipe_config; 1709 u32 tmp; 1710 int i, j; 1711 u32 sq_config; 1712 u32 sq_gpr_resource_mgmt_1 = 0; 1713 u32 sq_gpr_resource_mgmt_2 = 0; 1714 u32 sq_thread_resource_mgmt = 0; 1715 u32 sq_stack_resource_mgmt_1 = 0; 1716 u32 sq_stack_resource_mgmt_2 = 0; 1717 u32 disabled_rb_mask; 1718 1719 rdev->config.r600.tiling_group_size = 256; 1720 switch (rdev->family) { 1721 case CHIP_R600: 1722 rdev->config.r600.max_pipes = 4; 1723 rdev->config.r600.max_tile_pipes = 8; 1724 rdev->config.r600.max_simds = 4; 1725 rdev->config.r600.max_backends = 4; 1726 rdev->config.r600.max_gprs = 256; 1727 rdev->config.r600.max_threads = 192; 1728 rdev->config.r600.max_stack_entries = 256; 1729 rdev->config.r600.max_hw_contexts = 8; 1730 rdev->config.r600.max_gs_threads = 16; 1731 rdev->config.r600.sx_max_export_size = 128; 1732 rdev->config.r600.sx_max_export_pos_size = 16; 1733 rdev->config.r600.sx_max_export_smx_size = 128; 1734 rdev->config.r600.sq_num_cf_insts = 2; 1735 break; 1736 case CHIP_RV630: 1737 case CHIP_RV635: 1738 rdev->config.r600.max_pipes = 2; 1739 rdev->config.r600.max_tile_pipes = 2; 1740 rdev->config.r600.max_simds = 3; 1741 rdev->config.r600.max_backends = 1; 1742 rdev->config.r600.max_gprs = 128; 1743 rdev->config.r600.max_threads = 192; 1744 rdev->config.r600.max_stack_entries = 128; 1745 rdev->config.r600.max_hw_contexts = 8; 1746 rdev->config.r600.max_gs_threads = 4; 1747 rdev->config.r600.sx_max_export_size = 128; 1748 rdev->config.r600.sx_max_export_pos_size = 16; 1749 rdev->config.r600.sx_max_export_smx_size = 128; 1750 rdev->config.r600.sq_num_cf_insts = 2; 1751 break; 1752 case CHIP_RV610: 1753 case CHIP_RV620: 1754 case CHIP_RS780: 1755 case CHIP_RS880: 1756 rdev->config.r600.max_pipes = 1; 1757 rdev->config.r600.max_tile_pipes = 1; 1758 rdev->config.r600.max_simds = 2; 1759 rdev->config.r600.max_backends = 1; 1760 rdev->config.r600.max_gprs = 128; 1761 rdev->config.r600.max_threads = 192; 1762 rdev->config.r600.max_stack_entries = 128; 1763 rdev->config.r600.max_hw_contexts = 4; 1764 rdev->config.r600.max_gs_threads = 4; 1765 rdev->config.r600.sx_max_export_size = 128; 1766 rdev->config.r600.sx_max_export_pos_size = 16; 1767 rdev->config.r600.sx_max_export_smx_size = 128; 1768 rdev->config.r600.sq_num_cf_insts = 1; 1769 break; 1770 case CHIP_RV670: 1771 rdev->config.r600.max_pipes = 4; 1772 rdev->config.r600.max_tile_pipes = 4; 1773 rdev->config.r600.max_simds = 4; 1774 rdev->config.r600.max_backends = 4; 1775 rdev->config.r600.max_gprs = 192; 1776 rdev->config.r600.max_threads = 192; 1777 rdev->config.r600.max_stack_entries = 256; 1778 rdev->config.r600.max_hw_contexts = 8; 1779 rdev->config.r600.max_gs_threads = 16; 1780 rdev->config.r600.sx_max_export_size = 128; 1781 rdev->config.r600.sx_max_export_pos_size = 16; 1782 rdev->config.r600.sx_max_export_smx_size = 128; 1783 rdev->config.r600.sq_num_cf_insts = 2; 1784 break; 1785 default: 1786 break; 1787 } 1788 1789 /* Initialize HDP */ 1790 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 1791 WREG32((0x2c14 + j), 0x00000000); 1792 WREG32((0x2c18 + j), 0x00000000); 1793 WREG32((0x2c1c + j), 0x00000000); 1794 WREG32((0x2c20 + j), 0x00000000); 1795 WREG32((0x2c24 + j), 0x00000000); 1796 } 1797 1798 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); 1799 1800 /* Setup tiling */ 1801 tiling_config = 0; 1802 ramcfg = RREG32(RAMCFG); 1803 switch (rdev->config.r600.max_tile_pipes) { 1804 case 1: 1805 tiling_config |= PIPE_TILING(0); 1806 break; 1807 case 2: 1808 tiling_config |= PIPE_TILING(1); 1809 break; 1810 case 4: 1811 tiling_config |= PIPE_TILING(2); 1812 break; 1813 case 8: 1814 tiling_config |= PIPE_TILING(3); 1815 break; 1816 default: 1817 break; 1818 } 1819 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes; 1820 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); 1821 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); 1822 tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT); 1823 1824 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT; 1825 if (tmp > 3) { 1826 tiling_config |= ROW_TILING(3); 1827 tiling_config |= SAMPLE_SPLIT(3); 1828 } else { 1829 tiling_config |= ROW_TILING(tmp); 1830 tiling_config |= SAMPLE_SPLIT(tmp); 1831 } 1832 tiling_config |= BANK_SWAPS(1); 1833 1834 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000; 1835 tmp = R6XX_MAX_BACKENDS - 1836 r600_count_pipe_bits((cc_rb_backend_disable >> 16) & R6XX_MAX_BACKENDS_MASK); 1837 if (tmp < rdev->config.r600.max_backends) { 1838 rdev->config.r600.max_backends = tmp; 1839 } 1840 1841 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0x00ffff00; 1842 tmp = R6XX_MAX_PIPES - 1843 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 8) & R6XX_MAX_PIPES_MASK); 1844 if (tmp < rdev->config.r600.max_pipes) { 1845 rdev->config.r600.max_pipes = tmp; 1846 } 1847 tmp = R6XX_MAX_SIMDS - 1848 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R6XX_MAX_SIMDS_MASK); 1849 if (tmp < rdev->config.r600.max_simds) { 1850 rdev->config.r600.max_simds = tmp; 1851 } 1852 1853 disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R6XX_MAX_BACKENDS_MASK; 1854 tmp = (tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT; 1855 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends, 1856 R6XX_MAX_BACKENDS, disabled_rb_mask); 1857 tiling_config |= tmp << 16; 1858 rdev->config.r600.backend_map = tmp; 1859 1860 rdev->config.r600.tile_config = tiling_config; 1861 WREG32(GB_TILING_CONFIG, tiling_config); 1862 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff); 1863 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff); 1864 WREG32(DMA_TILING_CONFIG, tiling_config & 0xffff); 1865 1866 tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8); 1867 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK); 1868 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK); 1869 1870 /* Setup some CP states */ 1871 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b))); 1872 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40))); 1873 1874 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT | 1875 SYNC_WALKER | SYNC_ALIGNER)); 1876 /* Setup various GPU states */ 1877 if (rdev->family == CHIP_RV670) 1878 WREG32(ARB_GDEC_RD_CNTL, 0x00000021); 1879 1880 tmp = RREG32(SX_DEBUG_1); 1881 tmp |= SMX_EVENT_RELEASE; 1882 if ((rdev->family > CHIP_R600)) 1883 tmp |= ENABLE_NEW_SMX_ADDRESS; 1884 WREG32(SX_DEBUG_1, tmp); 1885 1886 if (((rdev->family) == CHIP_R600) || 1887 ((rdev->family) == CHIP_RV630) || 1888 ((rdev->family) == CHIP_RV610) || 1889 ((rdev->family) == CHIP_RV620) || 1890 ((rdev->family) == CHIP_RS780) || 1891 ((rdev->family) == CHIP_RS880)) { 1892 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE); 1893 } else { 1894 WREG32(DB_DEBUG, 0); 1895 } 1896 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) | 1897 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4))); 1898 1899 WREG32(PA_SC_MULTI_CHIP_CNTL, 0); 1900 WREG32(VGT_NUM_INSTANCES, 0); 1901 1902 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0)); 1903 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0)); 1904 1905 tmp = RREG32(SQ_MS_FIFO_SIZES); 1906 if (((rdev->family) == CHIP_RV610) || 1907 ((rdev->family) == CHIP_RV620) || 1908 ((rdev->family) == CHIP_RS780) || 1909 ((rdev->family) == CHIP_RS880)) { 1910 tmp = (CACHE_FIFO_SIZE(0xa) | 1911 FETCH_FIFO_HIWATER(0xa) | 1912 DONE_FIFO_HIWATER(0xe0) | 1913 ALU_UPDATE_FIFO_HIWATER(0x8)); 1914 } else if (((rdev->family) == CHIP_R600) || 1915 ((rdev->family) == CHIP_RV630)) { 1916 tmp &= ~DONE_FIFO_HIWATER(0xff); 1917 tmp |= DONE_FIFO_HIWATER(0x4); 1918 } 1919 WREG32(SQ_MS_FIFO_SIZES, tmp); 1920 1921 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT 1922 * should be adjusted as needed by the 2D/3D drivers. This just sets default values 1923 */ 1924 sq_config = RREG32(SQ_CONFIG); 1925 sq_config &= ~(PS_PRIO(3) | 1926 VS_PRIO(3) | 1927 GS_PRIO(3) | 1928 ES_PRIO(3)); 1929 sq_config |= (DX9_CONSTS | 1930 VC_ENABLE | 1931 PS_PRIO(0) | 1932 VS_PRIO(1) | 1933 GS_PRIO(2) | 1934 ES_PRIO(3)); 1935 1936 if ((rdev->family) == CHIP_R600) { 1937 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) | 1938 NUM_VS_GPRS(124) | 1939 NUM_CLAUSE_TEMP_GPRS(4)); 1940 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) | 1941 NUM_ES_GPRS(0)); 1942 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) | 1943 NUM_VS_THREADS(48) | 1944 NUM_GS_THREADS(4) | 1945 NUM_ES_THREADS(4)); 1946 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) | 1947 NUM_VS_STACK_ENTRIES(128)); 1948 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) | 1949 NUM_ES_STACK_ENTRIES(0)); 1950 } else if (((rdev->family) == CHIP_RV610) || 1951 ((rdev->family) == CHIP_RV620) || 1952 ((rdev->family) == CHIP_RS780) || 1953 ((rdev->family) == CHIP_RS880)) { 1954 /* no vertex cache */ 1955 sq_config &= ~VC_ENABLE; 1956 1957 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | 1958 NUM_VS_GPRS(44) | 1959 NUM_CLAUSE_TEMP_GPRS(2)); 1960 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | 1961 NUM_ES_GPRS(17)); 1962 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | 1963 NUM_VS_THREADS(78) | 1964 NUM_GS_THREADS(4) | 1965 NUM_ES_THREADS(31)); 1966 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | 1967 NUM_VS_STACK_ENTRIES(40)); 1968 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | 1969 NUM_ES_STACK_ENTRIES(16)); 1970 } else if (((rdev->family) == CHIP_RV630) || 1971 ((rdev->family) == CHIP_RV635)) { 1972 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | 1973 NUM_VS_GPRS(44) | 1974 NUM_CLAUSE_TEMP_GPRS(2)); 1975 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) | 1976 NUM_ES_GPRS(18)); 1977 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | 1978 NUM_VS_THREADS(78) | 1979 NUM_GS_THREADS(4) | 1980 NUM_ES_THREADS(31)); 1981 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | 1982 NUM_VS_STACK_ENTRIES(40)); 1983 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | 1984 NUM_ES_STACK_ENTRIES(16)); 1985 } else if ((rdev->family) == CHIP_RV670) { 1986 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | 1987 NUM_VS_GPRS(44) | 1988 NUM_CLAUSE_TEMP_GPRS(2)); 1989 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | 1990 NUM_ES_GPRS(17)); 1991 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | 1992 NUM_VS_THREADS(78) | 1993 NUM_GS_THREADS(4) | 1994 NUM_ES_THREADS(31)); 1995 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) | 1996 NUM_VS_STACK_ENTRIES(64)); 1997 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) | 1998 NUM_ES_STACK_ENTRIES(64)); 1999 } 2000 2001 WREG32(SQ_CONFIG, sq_config); 2002 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1); 2003 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2); 2004 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); 2005 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1); 2006 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2); 2007 2008 if (((rdev->family) == CHIP_RV610) || 2009 ((rdev->family) == CHIP_RV620) || 2010 ((rdev->family) == CHIP_RS780) || 2011 ((rdev->family) == CHIP_RS880)) { 2012 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY)); 2013 } else { 2014 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC)); 2015 } 2016 2017 /* More default values. 2D/3D driver should adjust as needed */ 2018 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) | 2019 S1_X(0x4) | S1_Y(0xc))); 2020 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) | 2021 S1_X(0x2) | S1_Y(0x2) | 2022 S2_X(0xa) | S2_Y(0x6) | 2023 S3_X(0x6) | S3_Y(0xa))); 2024 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) | 2025 S1_X(0x4) | S1_Y(0xc) | 2026 S2_X(0x1) | S2_Y(0x6) | 2027 S3_X(0xa) | S3_Y(0xe))); 2028 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) | 2029 S5_X(0x0) | S5_Y(0x0) | 2030 S6_X(0xb) | S6_Y(0x4) | 2031 S7_X(0x7) | S7_Y(0x8))); 2032 2033 WREG32(VGT_STRMOUT_EN, 0); 2034 tmp = rdev->config.r600.max_pipes * 16; 2035 switch (rdev->family) { 2036 case CHIP_RV610: 2037 case CHIP_RV620: 2038 case CHIP_RS780: 2039 case CHIP_RS880: 2040 tmp += 32; 2041 break; 2042 case CHIP_RV670: 2043 tmp += 128; 2044 break; 2045 default: 2046 break; 2047 } 2048 if (tmp > 256) { 2049 tmp = 256; 2050 } 2051 WREG32(VGT_ES_PER_GS, 128); 2052 WREG32(VGT_GS_PER_ES, tmp); 2053 WREG32(VGT_GS_PER_VS, 2); 2054 WREG32(VGT_GS_VERTEX_REUSE, 16); 2055 2056 /* more default values. 2D/3D driver should adjust as needed */ 2057 WREG32(PA_SC_LINE_STIPPLE_STATE, 0); 2058 WREG32(VGT_STRMOUT_EN, 0); 2059 WREG32(SX_MISC, 0); 2060 WREG32(PA_SC_MODE_CNTL, 0); 2061 WREG32(PA_SC_AA_CONFIG, 0); 2062 WREG32(PA_SC_LINE_STIPPLE, 0); 2063 WREG32(SPI_INPUT_Z, 0); 2064 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2)); 2065 WREG32(CB_COLOR7_FRAG, 0); 2066 2067 /* Clear render buffer base addresses */ 2068 WREG32(CB_COLOR0_BASE, 0); 2069 WREG32(CB_COLOR1_BASE, 0); 2070 WREG32(CB_COLOR2_BASE, 0); 2071 WREG32(CB_COLOR3_BASE, 0); 2072 WREG32(CB_COLOR4_BASE, 0); 2073 WREG32(CB_COLOR5_BASE, 0); 2074 WREG32(CB_COLOR6_BASE, 0); 2075 WREG32(CB_COLOR7_BASE, 0); 2076 WREG32(CB_COLOR7_FRAG, 0); 2077 2078 switch (rdev->family) { 2079 case CHIP_RV610: 2080 case CHIP_RV620: 2081 case CHIP_RS780: 2082 case CHIP_RS880: 2083 tmp = TC_L2_SIZE(8); 2084 break; 2085 case CHIP_RV630: 2086 case CHIP_RV635: 2087 tmp = TC_L2_SIZE(4); 2088 break; 2089 case CHIP_R600: 2090 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT; 2091 break; 2092 default: 2093 tmp = TC_L2_SIZE(0); 2094 break; 2095 } 2096 WREG32(TC_CNTL, tmp); 2097 2098 tmp = RREG32(HDP_HOST_PATH_CNTL); 2099 WREG32(HDP_HOST_PATH_CNTL, tmp); 2100 2101 tmp = RREG32(ARB_POP); 2102 tmp |= ENABLE_TC128; 2103 WREG32(ARB_POP, tmp); 2104 2105 WREG32(PA_SC_MULTI_CHIP_CNTL, 0); 2106 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | 2107 NUM_CLIP_SEQ(3))); 2108 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095)); 2109 WREG32(VC_ENHANCE, 0); 2110 } 2111 2112 2113 /* 2114 * Indirect registers accessor 2115 */ 2116 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg) 2117 { 2118 u32 r; 2119 2120 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); 2121 (void)RREG32(PCIE_PORT_INDEX); 2122 r = RREG32(PCIE_PORT_DATA); 2123 return r; 2124 } 2125 2126 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2127 { 2128 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); 2129 (void)RREG32(PCIE_PORT_INDEX); 2130 WREG32(PCIE_PORT_DATA, (v)); 2131 (void)RREG32(PCIE_PORT_DATA); 2132 } 2133 2134 /* 2135 * CP & Ring 2136 */ 2137 void r600_cp_stop(struct radeon_device *rdev) 2138 { 2139 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 2140 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); 2141 WREG32(SCRATCH_UMSK, 0); 2142 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 2143 } 2144 2145 int r600_init_microcode(struct radeon_device *rdev) 2146 { 2147 struct platform_device *pdev; 2148 const char *chip_name; 2149 const char *rlc_chip_name; 2150 const char *smc_chip_name = "RV770"; 2151 size_t pfp_req_size, me_req_size, rlc_req_size, smc_req_size = 0; 2152 char fw_name[30]; 2153 int err; 2154 2155 DRM_DEBUG("\n"); 2156 2157 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0); 2158 err = IS_ERR(pdev); 2159 if (err) { 2160 printk(KERN_ERR "radeon_cp: Failed to register firmware\n"); 2161 return -EINVAL; 2162 } 2163 2164 switch (rdev->family) { 2165 case CHIP_R600: 2166 chip_name = "R600"; 2167 rlc_chip_name = "R600"; 2168 break; 2169 case CHIP_RV610: 2170 chip_name = "RV610"; 2171 rlc_chip_name = "R600"; 2172 break; 2173 case CHIP_RV630: 2174 chip_name = "RV630"; 2175 rlc_chip_name = "R600"; 2176 break; 2177 case CHIP_RV620: 2178 chip_name = "RV620"; 2179 rlc_chip_name = "R600"; 2180 break; 2181 case CHIP_RV635: 2182 chip_name = "RV635"; 2183 rlc_chip_name = "R600"; 2184 break; 2185 case CHIP_RV670: 2186 chip_name = "RV670"; 2187 rlc_chip_name = "R600"; 2188 break; 2189 case CHIP_RS780: 2190 case CHIP_RS880: 2191 chip_name = "RS780"; 2192 rlc_chip_name = "R600"; 2193 break; 2194 case CHIP_RV770: 2195 chip_name = "RV770"; 2196 rlc_chip_name = "R700"; 2197 smc_chip_name = "RV770"; 2198 smc_req_size = ALIGN(RV770_SMC_UCODE_SIZE, 4); 2199 break; 2200 case CHIP_RV730: 2201 chip_name = "RV730"; 2202 rlc_chip_name = "R700"; 2203 smc_chip_name = "RV730"; 2204 smc_req_size = ALIGN(RV730_SMC_UCODE_SIZE, 4); 2205 break; 2206 case CHIP_RV710: 2207 chip_name = "RV710"; 2208 rlc_chip_name = "R700"; 2209 smc_chip_name = "RV710"; 2210 smc_req_size = ALIGN(RV710_SMC_UCODE_SIZE, 4); 2211 break; 2212 case CHIP_RV740: 2213 chip_name = "RV730"; 2214 rlc_chip_name = "R700"; 2215 smc_chip_name = "RV740"; 2216 smc_req_size = ALIGN(RV740_SMC_UCODE_SIZE, 4); 2217 break; 2218 case CHIP_CEDAR: 2219 chip_name = "CEDAR"; 2220 rlc_chip_name = "CEDAR"; 2221 smc_chip_name = "CEDAR"; 2222 smc_req_size = ALIGN(CEDAR_SMC_UCODE_SIZE, 4); 2223 break; 2224 case CHIP_REDWOOD: 2225 chip_name = "REDWOOD"; 2226 rlc_chip_name = "REDWOOD"; 2227 smc_chip_name = "REDWOOD"; 2228 smc_req_size = ALIGN(REDWOOD_SMC_UCODE_SIZE, 4); 2229 break; 2230 case CHIP_JUNIPER: 2231 chip_name = "JUNIPER"; 2232 rlc_chip_name = "JUNIPER"; 2233 smc_chip_name = "JUNIPER"; 2234 smc_req_size = ALIGN(JUNIPER_SMC_UCODE_SIZE, 4); 2235 break; 2236 case CHIP_CYPRESS: 2237 case CHIP_HEMLOCK: 2238 chip_name = "CYPRESS"; 2239 rlc_chip_name = "CYPRESS"; 2240 smc_chip_name = "CYPRESS"; 2241 smc_req_size = ALIGN(CYPRESS_SMC_UCODE_SIZE, 4); 2242 break; 2243 case CHIP_PALM: 2244 chip_name = "PALM"; 2245 rlc_chip_name = "SUMO"; 2246 break; 2247 case CHIP_SUMO: 2248 chip_name = "SUMO"; 2249 rlc_chip_name = "SUMO"; 2250 break; 2251 case CHIP_SUMO2: 2252 chip_name = "SUMO2"; 2253 rlc_chip_name = "SUMO"; 2254 break; 2255 default: BUG(); 2256 } 2257 2258 if (rdev->family >= CHIP_CEDAR) { 2259 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4; 2260 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4; 2261 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4; 2262 } else if (rdev->family >= CHIP_RV770) { 2263 pfp_req_size = R700_PFP_UCODE_SIZE * 4; 2264 me_req_size = R700_PM4_UCODE_SIZE * 4; 2265 rlc_req_size = R700_RLC_UCODE_SIZE * 4; 2266 } else { 2267 pfp_req_size = R600_PFP_UCODE_SIZE * 4; 2268 me_req_size = R600_PM4_UCODE_SIZE * 12; 2269 rlc_req_size = R600_RLC_UCODE_SIZE * 4; 2270 } 2271 2272 DRM_INFO("Loading %s Microcode\n", chip_name); 2273 2274 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name); 2275 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev); 2276 if (err) 2277 goto out; 2278 if (rdev->pfp_fw->size != pfp_req_size) { 2279 printk(KERN_ERR 2280 "r600_cp: Bogus length %zu in firmware \"%s\"\n", 2281 rdev->pfp_fw->size, fw_name); 2282 err = -EINVAL; 2283 goto out; 2284 } 2285 2286 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name); 2287 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev); 2288 if (err) 2289 goto out; 2290 if (rdev->me_fw->size != me_req_size) { 2291 printk(KERN_ERR 2292 "r600_cp: Bogus length %zu in firmware \"%s\"\n", 2293 rdev->me_fw->size, fw_name); 2294 err = -EINVAL; 2295 } 2296 2297 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name); 2298 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev); 2299 if (err) 2300 goto out; 2301 if (rdev->rlc_fw->size != rlc_req_size) { 2302 printk(KERN_ERR 2303 "r600_rlc: Bogus length %zu in firmware \"%s\"\n", 2304 rdev->rlc_fw->size, fw_name); 2305 err = -EINVAL; 2306 } 2307 2308 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_HEMLOCK)) { 2309 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", smc_chip_name); 2310 err = request_firmware(&rdev->smc_fw, fw_name, &pdev->dev); 2311 if (err) 2312 goto out; 2313 if (rdev->smc_fw->size != smc_req_size) { 2314 printk(KERN_ERR 2315 "smc: Bogus length %zu in firmware \"%s\"\n", 2316 rdev->smc_fw->size, fw_name); 2317 err = -EINVAL; 2318 } 2319 } 2320 2321 out: 2322 platform_device_unregister(pdev); 2323 2324 if (err) { 2325 if (err != -EINVAL) 2326 printk(KERN_ERR 2327 "r600_cp: Failed to load firmware \"%s\"\n", 2328 fw_name); 2329 release_firmware(rdev->pfp_fw); 2330 rdev->pfp_fw = NULL; 2331 release_firmware(rdev->me_fw); 2332 rdev->me_fw = NULL; 2333 release_firmware(rdev->rlc_fw); 2334 rdev->rlc_fw = NULL; 2335 release_firmware(rdev->smc_fw); 2336 rdev->smc_fw = NULL; 2337 } 2338 return err; 2339 } 2340 2341 static int r600_cp_load_microcode(struct radeon_device *rdev) 2342 { 2343 const __be32 *fw_data; 2344 int i; 2345 2346 if (!rdev->me_fw || !rdev->pfp_fw) 2347 return -EINVAL; 2348 2349 r600_cp_stop(rdev); 2350 2351 WREG32(CP_RB_CNTL, 2352 #ifdef __BIG_ENDIAN 2353 BUF_SWAP_32BIT | 2354 #endif 2355 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); 2356 2357 /* Reset cp */ 2358 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); 2359 RREG32(GRBM_SOFT_RESET); 2360 mdelay(15); 2361 WREG32(GRBM_SOFT_RESET, 0); 2362 2363 WREG32(CP_ME_RAM_WADDR, 0); 2364 2365 fw_data = (const __be32 *)rdev->me_fw->data; 2366 WREG32(CP_ME_RAM_WADDR, 0); 2367 for (i = 0; i < R600_PM4_UCODE_SIZE * 3; i++) 2368 WREG32(CP_ME_RAM_DATA, 2369 be32_to_cpup(fw_data++)); 2370 2371 fw_data = (const __be32 *)rdev->pfp_fw->data; 2372 WREG32(CP_PFP_UCODE_ADDR, 0); 2373 for (i = 0; i < R600_PFP_UCODE_SIZE; i++) 2374 WREG32(CP_PFP_UCODE_DATA, 2375 be32_to_cpup(fw_data++)); 2376 2377 WREG32(CP_PFP_UCODE_ADDR, 0); 2378 WREG32(CP_ME_RAM_WADDR, 0); 2379 WREG32(CP_ME_RAM_RADDR, 0); 2380 return 0; 2381 } 2382 2383 int r600_cp_start(struct radeon_device *rdev) 2384 { 2385 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2386 int r; 2387 uint32_t cp_me; 2388 2389 r = radeon_ring_lock(rdev, ring, 7); 2390 if (r) { 2391 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 2392 return r; 2393 } 2394 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); 2395 radeon_ring_write(ring, 0x1); 2396 if (rdev->family >= CHIP_RV770) { 2397 radeon_ring_write(ring, 0x0); 2398 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1); 2399 } else { 2400 radeon_ring_write(ring, 0x3); 2401 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1); 2402 } 2403 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); 2404 radeon_ring_write(ring, 0); 2405 radeon_ring_write(ring, 0); 2406 radeon_ring_unlock_commit(rdev, ring); 2407 2408 cp_me = 0xff; 2409 WREG32(R_0086D8_CP_ME_CNTL, cp_me); 2410 return 0; 2411 } 2412 2413 int r600_cp_resume(struct radeon_device *rdev) 2414 { 2415 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2416 u32 tmp; 2417 u32 rb_bufsz; 2418 int r; 2419 2420 /* Reset cp */ 2421 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); 2422 RREG32(GRBM_SOFT_RESET); 2423 mdelay(15); 2424 WREG32(GRBM_SOFT_RESET, 0); 2425 2426 /* Set ring buffer size */ 2427 rb_bufsz = drm_order(ring->ring_size / 8); 2428 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2429 #ifdef __BIG_ENDIAN 2430 tmp |= BUF_SWAP_32BIT; 2431 #endif 2432 WREG32(CP_RB_CNTL, tmp); 2433 WREG32(CP_SEM_WAIT_TIMER, 0x0); 2434 2435 /* Set the write pointer delay */ 2436 WREG32(CP_RB_WPTR_DELAY, 0); 2437 2438 /* Initialize the ring buffer's read and write pointers */ 2439 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); 2440 WREG32(CP_RB_RPTR_WR, 0); 2441 ring->wptr = 0; 2442 WREG32(CP_RB_WPTR, ring->wptr); 2443 2444 /* set the wb address whether it's enabled or not */ 2445 WREG32(CP_RB_RPTR_ADDR, 2446 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC)); 2447 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); 2448 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); 2449 2450 if (rdev->wb.enabled) 2451 WREG32(SCRATCH_UMSK, 0xff); 2452 else { 2453 tmp |= RB_NO_UPDATE; 2454 WREG32(SCRATCH_UMSK, 0); 2455 } 2456 2457 mdelay(1); 2458 WREG32(CP_RB_CNTL, tmp); 2459 2460 WREG32(CP_RB_BASE, ring->gpu_addr >> 8); 2461 WREG32(CP_DEBUG, (1 << 27) | (1 << 28)); 2462 2463 ring->rptr = RREG32(CP_RB_RPTR); 2464 2465 r600_cp_start(rdev); 2466 ring->ready = true; 2467 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring); 2468 if (r) { 2469 ring->ready = false; 2470 return r; 2471 } 2472 return 0; 2473 } 2474 2475 void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size) 2476 { 2477 u32 rb_bufsz; 2478 int r; 2479 2480 /* Align ring size */ 2481 rb_bufsz = drm_order(ring_size / 8); 2482 ring_size = (1 << (rb_bufsz + 1)) * 4; 2483 ring->ring_size = ring_size; 2484 ring->align_mask = 16 - 1; 2485 2486 if (radeon_ring_supports_scratch_reg(rdev, ring)) { 2487 r = radeon_scratch_get(rdev, &ring->rptr_save_reg); 2488 if (r) { 2489 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r); 2490 ring->rptr_save_reg = 0; 2491 } 2492 } 2493 } 2494 2495 void r600_cp_fini(struct radeon_device *rdev) 2496 { 2497 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2498 r600_cp_stop(rdev); 2499 radeon_ring_fini(rdev, ring); 2500 radeon_scratch_free(rdev, ring->rptr_save_reg); 2501 } 2502 2503 /* 2504 * DMA 2505 * Starting with R600, the GPU has an asynchronous 2506 * DMA engine. The programming model is very similar 2507 * to the 3D engine (ring buffer, IBs, etc.), but the 2508 * DMA controller has it's own packet format that is 2509 * different form the PM4 format used by the 3D engine. 2510 * It supports copying data, writing embedded data, 2511 * solid fills, and a number of other things. It also 2512 * has support for tiling/detiling of buffers. 2513 */ 2514 /** 2515 * r600_dma_stop - stop the async dma engine 2516 * 2517 * @rdev: radeon_device pointer 2518 * 2519 * Stop the async dma engine (r6xx-evergreen). 2520 */ 2521 void r600_dma_stop(struct radeon_device *rdev) 2522 { 2523 u32 rb_cntl = RREG32(DMA_RB_CNTL); 2524 2525 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 2526 2527 rb_cntl &= ~DMA_RB_ENABLE; 2528 WREG32(DMA_RB_CNTL, rb_cntl); 2529 2530 rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false; 2531 } 2532 2533 /** 2534 * r600_dma_resume - setup and start the async dma engine 2535 * 2536 * @rdev: radeon_device pointer 2537 * 2538 * Set up the DMA ring buffer and enable it. (r6xx-evergreen). 2539 * Returns 0 for success, error for failure. 2540 */ 2541 int r600_dma_resume(struct radeon_device *rdev) 2542 { 2543 struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; 2544 u32 rb_cntl, dma_cntl, ib_cntl; 2545 u32 rb_bufsz; 2546 int r; 2547 2548 /* Reset dma */ 2549 if (rdev->family >= CHIP_RV770) 2550 WREG32(SRBM_SOFT_RESET, RV770_SOFT_RESET_DMA); 2551 else 2552 WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA); 2553 RREG32(SRBM_SOFT_RESET); 2554 udelay(50); 2555 WREG32(SRBM_SOFT_RESET, 0); 2556 2557 WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL, 0); 2558 WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL, 0); 2559 2560 /* Set ring buffer size in dwords */ 2561 rb_bufsz = drm_order(ring->ring_size / 4); 2562 rb_cntl = rb_bufsz << 1; 2563 #ifdef __BIG_ENDIAN 2564 rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE; 2565 #endif 2566 WREG32(DMA_RB_CNTL, rb_cntl); 2567 2568 /* Initialize the ring buffer's read and write pointers */ 2569 WREG32(DMA_RB_RPTR, 0); 2570 WREG32(DMA_RB_WPTR, 0); 2571 2572 /* set the wb address whether it's enabled or not */ 2573 WREG32(DMA_RB_RPTR_ADDR_HI, 2574 upper_32_bits(rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFF); 2575 WREG32(DMA_RB_RPTR_ADDR_LO, 2576 ((rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFFFFFFFC)); 2577 2578 if (rdev->wb.enabled) 2579 rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE; 2580 2581 WREG32(DMA_RB_BASE, ring->gpu_addr >> 8); 2582 2583 /* enable DMA IBs */ 2584 ib_cntl = DMA_IB_ENABLE; 2585 #ifdef __BIG_ENDIAN 2586 ib_cntl |= DMA_IB_SWAP_ENABLE; 2587 #endif 2588 WREG32(DMA_IB_CNTL, ib_cntl); 2589 2590 dma_cntl = RREG32(DMA_CNTL); 2591 dma_cntl &= ~CTXEMPTY_INT_ENABLE; 2592 WREG32(DMA_CNTL, dma_cntl); 2593 2594 if (rdev->family >= CHIP_RV770) 2595 WREG32(DMA_MODE, 1); 2596 2597 ring->wptr = 0; 2598 WREG32(DMA_RB_WPTR, ring->wptr << 2); 2599 2600 ring->rptr = RREG32(DMA_RB_RPTR) >> 2; 2601 2602 WREG32(DMA_RB_CNTL, rb_cntl | DMA_RB_ENABLE); 2603 2604 ring->ready = true; 2605 2606 r = radeon_ring_test(rdev, R600_RING_TYPE_DMA_INDEX, ring); 2607 if (r) { 2608 ring->ready = false; 2609 return r; 2610 } 2611 2612 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); 2613 2614 return 0; 2615 } 2616 2617 /** 2618 * r600_dma_fini - tear down the async dma engine 2619 * 2620 * @rdev: radeon_device pointer 2621 * 2622 * Stop the async dma engine and free the ring (r6xx-evergreen). 2623 */ 2624 void r600_dma_fini(struct radeon_device *rdev) 2625 { 2626 r600_dma_stop(rdev); 2627 radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]); 2628 } 2629 2630 /* 2631 * UVD 2632 */ 2633 int r600_uvd_rbc_start(struct radeon_device *rdev) 2634 { 2635 struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; 2636 uint64_t rptr_addr; 2637 uint32_t rb_bufsz, tmp; 2638 int r; 2639 2640 rptr_addr = rdev->wb.gpu_addr + R600_WB_UVD_RPTR_OFFSET; 2641 2642 if (upper_32_bits(rptr_addr) != upper_32_bits(ring->gpu_addr)) { 2643 DRM_ERROR("UVD ring and rptr not in the same 4GB segment!\n"); 2644 return -EINVAL; 2645 } 2646 2647 /* force RBC into idle state */ 2648 WREG32(UVD_RBC_RB_CNTL, 0x11010101); 2649 2650 /* Set the write pointer delay */ 2651 WREG32(UVD_RBC_RB_WPTR_CNTL, 0); 2652 2653 /* set the wb address */ 2654 WREG32(UVD_RBC_RB_RPTR_ADDR, rptr_addr >> 2); 2655 2656 /* programm the 4GB memory segment for rptr and ring buffer */ 2657 WREG32(UVD_LMI_EXT40_ADDR, upper_32_bits(rptr_addr) | 2658 (0x7 << 16) | (0x1 << 31)); 2659 2660 /* Initialize the ring buffer's read and write pointers */ 2661 WREG32(UVD_RBC_RB_RPTR, 0x0); 2662 2663 ring->wptr = ring->rptr = RREG32(UVD_RBC_RB_RPTR); 2664 WREG32(UVD_RBC_RB_WPTR, ring->wptr); 2665 2666 /* set the ring address */ 2667 WREG32(UVD_RBC_RB_BASE, ring->gpu_addr); 2668 2669 /* Set ring buffer size */ 2670 rb_bufsz = drm_order(ring->ring_size); 2671 rb_bufsz = (0x1 << 8) | rb_bufsz; 2672 WREG32(UVD_RBC_RB_CNTL, rb_bufsz); 2673 2674 ring->ready = true; 2675 r = radeon_ring_test(rdev, R600_RING_TYPE_UVD_INDEX, ring); 2676 if (r) { 2677 ring->ready = false; 2678 return r; 2679 } 2680 2681 r = radeon_ring_lock(rdev, ring, 10); 2682 if (r) { 2683 DRM_ERROR("radeon: ring failed to lock UVD ring (%d).\n", r); 2684 return r; 2685 } 2686 2687 tmp = PACKET0(UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); 2688 radeon_ring_write(ring, tmp); 2689 radeon_ring_write(ring, 0xFFFFF); 2690 2691 tmp = PACKET0(UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); 2692 radeon_ring_write(ring, tmp); 2693 radeon_ring_write(ring, 0xFFFFF); 2694 2695 tmp = PACKET0(UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); 2696 radeon_ring_write(ring, tmp); 2697 radeon_ring_write(ring, 0xFFFFF); 2698 2699 /* Clear timeout status bits */ 2700 radeon_ring_write(ring, PACKET0(UVD_SEMA_TIMEOUT_STATUS, 0)); 2701 radeon_ring_write(ring, 0x8); 2702 2703 radeon_ring_write(ring, PACKET0(UVD_SEMA_CNTL, 0)); 2704 radeon_ring_write(ring, 3); 2705 2706 radeon_ring_unlock_commit(rdev, ring); 2707 2708 return 0; 2709 } 2710 2711 void r600_uvd_rbc_stop(struct radeon_device *rdev) 2712 { 2713 struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; 2714 2715 /* force RBC into idle state */ 2716 WREG32(UVD_RBC_RB_CNTL, 0x11010101); 2717 ring->ready = false; 2718 } 2719 2720 int r600_uvd_init(struct radeon_device *rdev) 2721 { 2722 int i, j, r; 2723 /* disable byte swapping */ 2724 u32 lmi_swap_cntl = 0; 2725 u32 mp_swap_cntl = 0; 2726 2727 /* raise clocks while booting up the VCPU */ 2728 radeon_set_uvd_clocks(rdev, 53300, 40000); 2729 2730 /* disable clock gating */ 2731 WREG32(UVD_CGC_GATE, 0); 2732 2733 /* disable interupt */ 2734 WREG32_P(UVD_MASTINT_EN, 0, ~(1 << 1)); 2735 2736 /* put LMI, VCPU, RBC etc... into reset */ 2737 WREG32(UVD_SOFT_RESET, LMI_SOFT_RESET | VCPU_SOFT_RESET | 2738 LBSI_SOFT_RESET | RBC_SOFT_RESET | CSM_SOFT_RESET | 2739 CXW_SOFT_RESET | TAP_SOFT_RESET | LMI_UMC_SOFT_RESET); 2740 mdelay(5); 2741 2742 /* take UVD block out of reset */ 2743 WREG32_P(SRBM_SOFT_RESET, 0, ~SOFT_RESET_UVD); 2744 mdelay(5); 2745 2746 /* initialize UVD memory controller */ 2747 WREG32(UVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) | 2748 (1 << 21) | (1 << 9) | (1 << 20)); 2749 2750 #ifdef __BIG_ENDIAN 2751 /* swap (8 in 32) RB and IB */ 2752 lmi_swap_cntl = 0xa; 2753 mp_swap_cntl = 0; 2754 #endif 2755 WREG32(UVD_LMI_SWAP_CNTL, lmi_swap_cntl); 2756 WREG32(UVD_MP_SWAP_CNTL, mp_swap_cntl); 2757 2758 WREG32(UVD_MPC_SET_MUXA0, 0x40c2040); 2759 WREG32(UVD_MPC_SET_MUXA1, 0x0); 2760 WREG32(UVD_MPC_SET_MUXB0, 0x40c2040); 2761 WREG32(UVD_MPC_SET_MUXB1, 0x0); 2762 WREG32(UVD_MPC_SET_ALU, 0); 2763 WREG32(UVD_MPC_SET_MUX, 0x88); 2764 2765 /* Stall UMC */ 2766 WREG32_P(UVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 2767 WREG32_P(UVD_RB_ARB_CTRL, 1 << 3, ~(1 << 3)); 2768 2769 /* take all subblocks out of reset, except VCPU */ 2770 WREG32(UVD_SOFT_RESET, VCPU_SOFT_RESET); 2771 mdelay(5); 2772 2773 /* enable VCPU clock */ 2774 WREG32(UVD_VCPU_CNTL, 1 << 9); 2775 2776 /* enable UMC */ 2777 WREG32_P(UVD_LMI_CTRL2, 0, ~(1 << 8)); 2778 2779 /* boot up the VCPU */ 2780 WREG32(UVD_SOFT_RESET, 0); 2781 mdelay(10); 2782 2783 WREG32_P(UVD_RB_ARB_CTRL, 0, ~(1 << 3)); 2784 2785 for (i = 0; i < 10; ++i) { 2786 uint32_t status; 2787 for (j = 0; j < 100; ++j) { 2788 status = RREG32(UVD_STATUS); 2789 if (status & 2) 2790 break; 2791 mdelay(10); 2792 } 2793 r = 0; 2794 if (status & 2) 2795 break; 2796 2797 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n"); 2798 WREG32_P(UVD_SOFT_RESET, VCPU_SOFT_RESET, ~VCPU_SOFT_RESET); 2799 mdelay(10); 2800 WREG32_P(UVD_SOFT_RESET, 0, ~VCPU_SOFT_RESET); 2801 mdelay(10); 2802 r = -1; 2803 } 2804 2805 if (r) { 2806 DRM_ERROR("UVD not responding, giving up!!!\n"); 2807 radeon_set_uvd_clocks(rdev, 0, 0); 2808 return r; 2809 } 2810 2811 /* enable interupt */ 2812 WREG32_P(UVD_MASTINT_EN, 3<<1, ~(3 << 1)); 2813 2814 r = r600_uvd_rbc_start(rdev); 2815 if (!r) 2816 DRM_INFO("UVD initialized successfully.\n"); 2817 2818 /* lower clocks again */ 2819 radeon_set_uvd_clocks(rdev, 0, 0); 2820 2821 return r; 2822 } 2823 2824 /* 2825 * GPU scratch registers helpers function. 2826 */ 2827 void r600_scratch_init(struct radeon_device *rdev) 2828 { 2829 int i; 2830 2831 rdev->scratch.num_reg = 7; 2832 rdev->scratch.reg_base = SCRATCH_REG0; 2833 for (i = 0; i < rdev->scratch.num_reg; i++) { 2834 rdev->scratch.free[i] = true; 2835 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); 2836 } 2837 } 2838 2839 int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) 2840 { 2841 uint32_t scratch; 2842 uint32_t tmp = 0; 2843 unsigned i; 2844 int r; 2845 2846 r = radeon_scratch_get(rdev, &scratch); 2847 if (r) { 2848 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); 2849 return r; 2850 } 2851 WREG32(scratch, 0xCAFEDEAD); 2852 r = radeon_ring_lock(rdev, ring, 3); 2853 if (r) { 2854 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring->idx, r); 2855 radeon_scratch_free(rdev, scratch); 2856 return r; 2857 } 2858 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2859 radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); 2860 radeon_ring_write(ring, 0xDEADBEEF); 2861 radeon_ring_unlock_commit(rdev, ring); 2862 for (i = 0; i < rdev->usec_timeout; i++) { 2863 tmp = RREG32(scratch); 2864 if (tmp == 0xDEADBEEF) 2865 break; 2866 DRM_UDELAY(1); 2867 } 2868 if (i < rdev->usec_timeout) { 2869 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); 2870 } else { 2871 DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n", 2872 ring->idx, scratch, tmp); 2873 r = -EINVAL; 2874 } 2875 radeon_scratch_free(rdev, scratch); 2876 return r; 2877 } 2878 2879 /** 2880 * r600_dma_ring_test - simple async dma engine test 2881 * 2882 * @rdev: radeon_device pointer 2883 * @ring: radeon_ring structure holding ring information 2884 * 2885 * Test the DMA engine by writing using it to write an 2886 * value to memory. (r6xx-SI). 2887 * Returns 0 for success, error for failure. 2888 */ 2889 int r600_dma_ring_test(struct radeon_device *rdev, 2890 struct radeon_ring *ring) 2891 { 2892 unsigned i; 2893 int r; 2894 void __iomem *ptr = (void *)rdev->vram_scratch.ptr; 2895 u32 tmp; 2896 2897 if (!ptr) { 2898 DRM_ERROR("invalid vram scratch pointer\n"); 2899 return -EINVAL; 2900 } 2901 2902 tmp = 0xCAFEDEAD; 2903 writel(tmp, ptr); 2904 2905 r = radeon_ring_lock(rdev, ring, 4); 2906 if (r) { 2907 DRM_ERROR("radeon: dma failed to lock ring %d (%d).\n", ring->idx, r); 2908 return r; 2909 } 2910 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1)); 2911 radeon_ring_write(ring, rdev->vram_scratch.gpu_addr & 0xfffffffc); 2912 radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff); 2913 radeon_ring_write(ring, 0xDEADBEEF); 2914 radeon_ring_unlock_commit(rdev, ring); 2915 2916 for (i = 0; i < rdev->usec_timeout; i++) { 2917 tmp = readl(ptr); 2918 if (tmp == 0xDEADBEEF) 2919 break; 2920 DRM_UDELAY(1); 2921 } 2922 2923 if (i < rdev->usec_timeout) { 2924 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); 2925 } else { 2926 DRM_ERROR("radeon: ring %d test failed (0x%08X)\n", 2927 ring->idx, tmp); 2928 r = -EINVAL; 2929 } 2930 return r; 2931 } 2932 2933 int r600_uvd_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) 2934 { 2935 uint32_t tmp = 0; 2936 unsigned i; 2937 int r; 2938 2939 WREG32(UVD_CONTEXT_ID, 0xCAFEDEAD); 2940 r = radeon_ring_lock(rdev, ring, 3); 2941 if (r) { 2942 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", 2943 ring->idx, r); 2944 return r; 2945 } 2946 radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0)); 2947 radeon_ring_write(ring, 0xDEADBEEF); 2948 radeon_ring_unlock_commit(rdev, ring); 2949 for (i = 0; i < rdev->usec_timeout; i++) { 2950 tmp = RREG32(UVD_CONTEXT_ID); 2951 if (tmp == 0xDEADBEEF) 2952 break; 2953 DRM_UDELAY(1); 2954 } 2955 2956 if (i < rdev->usec_timeout) { 2957 DRM_INFO("ring test on %d succeeded in %d usecs\n", 2958 ring->idx, i); 2959 } else { 2960 DRM_ERROR("radeon: ring %d test failed (0x%08X)\n", 2961 ring->idx, tmp); 2962 r = -EINVAL; 2963 } 2964 return r; 2965 } 2966 2967 /* 2968 * CP fences/semaphores 2969 */ 2970 2971 void r600_fence_ring_emit(struct radeon_device *rdev, 2972 struct radeon_fence *fence) 2973 { 2974 struct radeon_ring *ring = &rdev->ring[fence->ring]; 2975 2976 if (rdev->wb.use_event) { 2977 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; 2978 /* flush read cache over gart */ 2979 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 2980 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | 2981 PACKET3_VC_ACTION_ENA | 2982 PACKET3_SH_ACTION_ENA); 2983 radeon_ring_write(ring, 0xFFFFFFFF); 2984 radeon_ring_write(ring, 0); 2985 radeon_ring_write(ring, 10); /* poll interval */ 2986 /* EVENT_WRITE_EOP - flush caches, send int */ 2987 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 2988 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5)); 2989 radeon_ring_write(ring, addr & 0xffffffff); 2990 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); 2991 radeon_ring_write(ring, fence->seq); 2992 radeon_ring_write(ring, 0); 2993 } else { 2994 /* flush read cache over gart */ 2995 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 2996 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | 2997 PACKET3_VC_ACTION_ENA | 2998 PACKET3_SH_ACTION_ENA); 2999 radeon_ring_write(ring, 0xFFFFFFFF); 3000 radeon_ring_write(ring, 0); 3001 radeon_ring_write(ring, 10); /* poll interval */ 3002 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); 3003 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0)); 3004 /* wait for 3D idle clean */ 3005 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 3006 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 3007 radeon_ring_write(ring, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit); 3008 /* Emit fence sequence & fire IRQ */ 3009 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 3010 radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); 3011 radeon_ring_write(ring, fence->seq); 3012 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */ 3013 radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0)); 3014 radeon_ring_write(ring, RB_INT_STAT); 3015 } 3016 } 3017 3018 void r600_uvd_fence_emit(struct radeon_device *rdev, 3019 struct radeon_fence *fence) 3020 { 3021 struct radeon_ring *ring = &rdev->ring[fence->ring]; 3022 uint32_t addr = rdev->fence_drv[fence->ring].gpu_addr; 3023 3024 radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0)); 3025 radeon_ring_write(ring, fence->seq); 3026 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0)); 3027 radeon_ring_write(ring, addr & 0xffffffff); 3028 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0)); 3029 radeon_ring_write(ring, upper_32_bits(addr) & 0xff); 3030 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0)); 3031 radeon_ring_write(ring, 0); 3032 3033 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0)); 3034 radeon_ring_write(ring, 0); 3035 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0)); 3036 radeon_ring_write(ring, 0); 3037 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0)); 3038 radeon_ring_write(ring, 2); 3039 return; 3040 } 3041 3042 void r600_semaphore_ring_emit(struct radeon_device *rdev, 3043 struct radeon_ring *ring, 3044 struct radeon_semaphore *semaphore, 3045 bool emit_wait) 3046 { 3047 uint64_t addr = semaphore->gpu_addr; 3048 unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL; 3049 3050 if (rdev->family < CHIP_CAYMAN) 3051 sel |= PACKET3_SEM_WAIT_ON_SIGNAL; 3052 3053 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); 3054 radeon_ring_write(ring, addr & 0xffffffff); 3055 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel); 3056 } 3057 3058 /* 3059 * DMA fences/semaphores 3060 */ 3061 3062 /** 3063 * r600_dma_fence_ring_emit - emit a fence on the DMA ring 3064 * 3065 * @rdev: radeon_device pointer 3066 * @fence: radeon fence object 3067 * 3068 * Add a DMA fence packet to the ring to write 3069 * the fence seq number and DMA trap packet to generate 3070 * an interrupt if needed (r6xx-r7xx). 3071 */ 3072 void r600_dma_fence_ring_emit(struct radeon_device *rdev, 3073 struct radeon_fence *fence) 3074 { 3075 struct radeon_ring *ring = &rdev->ring[fence->ring]; 3076 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; 3077 3078 /* write the fence */ 3079 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0)); 3080 radeon_ring_write(ring, addr & 0xfffffffc); 3081 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff)); 3082 radeon_ring_write(ring, lower_32_bits(fence->seq)); 3083 /* generate an interrupt */ 3084 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0, 0)); 3085 } 3086 3087 /** 3088 * r600_dma_semaphore_ring_emit - emit a semaphore on the dma ring 3089 * 3090 * @rdev: radeon_device pointer 3091 * @ring: radeon_ring structure holding ring information 3092 * @semaphore: radeon semaphore object 3093 * @emit_wait: wait or signal semaphore 3094 * 3095 * Add a DMA semaphore packet to the ring wait on or signal 3096 * other rings (r6xx-SI). 3097 */ 3098 void r600_dma_semaphore_ring_emit(struct radeon_device *rdev, 3099 struct radeon_ring *ring, 3100 struct radeon_semaphore *semaphore, 3101 bool emit_wait) 3102 { 3103 u64 addr = semaphore->gpu_addr; 3104 u32 s = emit_wait ? 0 : 1; 3105 3106 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SEMAPHORE, 0, s, 0)); 3107 radeon_ring_write(ring, addr & 0xfffffffc); 3108 radeon_ring_write(ring, upper_32_bits(addr) & 0xff); 3109 } 3110 3111 void r600_uvd_semaphore_emit(struct radeon_device *rdev, 3112 struct radeon_ring *ring, 3113 struct radeon_semaphore *semaphore, 3114 bool emit_wait) 3115 { 3116 uint64_t addr = semaphore->gpu_addr; 3117 3118 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_LOW, 0)); 3119 radeon_ring_write(ring, (addr >> 3) & 0x000FFFFF); 3120 3121 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_HIGH, 0)); 3122 radeon_ring_write(ring, (addr >> 23) & 0x000FFFFF); 3123 3124 radeon_ring_write(ring, PACKET0(UVD_SEMA_CMD, 0)); 3125 radeon_ring_write(ring, emit_wait ? 1 : 0); 3126 } 3127 3128 int r600_copy_blit(struct radeon_device *rdev, 3129 uint64_t src_offset, 3130 uint64_t dst_offset, 3131 unsigned num_gpu_pages, 3132 struct radeon_fence **fence) 3133 { 3134 struct radeon_semaphore *sem = NULL; 3135 struct radeon_sa_bo *vb = NULL; 3136 int r; 3137 3138 r = r600_blit_prepare_copy(rdev, num_gpu_pages, fence, &vb, &sem); 3139 if (r) { 3140 return r; 3141 } 3142 r600_kms_blit_copy(rdev, src_offset, dst_offset, num_gpu_pages, vb); 3143 r600_blit_done_copy(rdev, fence, vb, sem); 3144 return 0; 3145 } 3146 3147 /** 3148 * r600_copy_dma - copy pages using the DMA engine 3149 * 3150 * @rdev: radeon_device pointer 3151 * @src_offset: src GPU address 3152 * @dst_offset: dst GPU address 3153 * @num_gpu_pages: number of GPU pages to xfer 3154 * @fence: radeon fence object 3155 * 3156 * Copy GPU paging using the DMA engine (r6xx). 3157 * Used by the radeon ttm implementation to move pages if 3158 * registered as the asic copy callback. 3159 */ 3160 int r600_copy_dma(struct radeon_device *rdev, 3161 uint64_t src_offset, uint64_t dst_offset, 3162 unsigned num_gpu_pages, 3163 struct radeon_fence **fence) 3164 { 3165 struct radeon_semaphore *sem = NULL; 3166 int ring_index = rdev->asic->copy.dma_ring_index; 3167 struct radeon_ring *ring = &rdev->ring[ring_index]; 3168 u32 size_in_dw, cur_size_in_dw; 3169 int i, num_loops; 3170 int r = 0; 3171 3172 r = radeon_semaphore_create(rdev, &sem); 3173 if (r) { 3174 DRM_ERROR("radeon: moving bo (%d).\n", r); 3175 return r; 3176 } 3177 3178 size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4; 3179 num_loops = DIV_ROUND_UP(size_in_dw, 0xFFFE); 3180 r = radeon_ring_lock(rdev, ring, num_loops * 4 + 8); 3181 if (r) { 3182 DRM_ERROR("radeon: moving bo (%d).\n", r); 3183 radeon_semaphore_free(rdev, &sem, NULL); 3184 return r; 3185 } 3186 3187 if (radeon_fence_need_sync(*fence, ring->idx)) { 3188 radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring, 3189 ring->idx); 3190 radeon_fence_note_sync(*fence, ring->idx); 3191 } else { 3192 radeon_semaphore_free(rdev, &sem, NULL); 3193 } 3194 3195 for (i = 0; i < num_loops; i++) { 3196 cur_size_in_dw = size_in_dw; 3197 if (cur_size_in_dw > 0xFFFE) 3198 cur_size_in_dw = 0xFFFE; 3199 size_in_dw -= cur_size_in_dw; 3200 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw)); 3201 radeon_ring_write(ring, dst_offset & 0xfffffffc); 3202 radeon_ring_write(ring, src_offset & 0xfffffffc); 3203 radeon_ring_write(ring, (((upper_32_bits(dst_offset) & 0xff) << 16) | 3204 (upper_32_bits(src_offset) & 0xff))); 3205 src_offset += cur_size_in_dw * 4; 3206 dst_offset += cur_size_in_dw * 4; 3207 } 3208 3209 r = radeon_fence_emit(rdev, fence, ring->idx); 3210 if (r) { 3211 radeon_ring_unlock_undo(rdev, ring); 3212 return r; 3213 } 3214 3215 radeon_ring_unlock_commit(rdev, ring); 3216 radeon_semaphore_free(rdev, &sem, *fence); 3217 3218 return r; 3219 } 3220 3221 int r600_set_surface_reg(struct radeon_device *rdev, int reg, 3222 uint32_t tiling_flags, uint32_t pitch, 3223 uint32_t offset, uint32_t obj_size) 3224 { 3225 /* FIXME: implement */ 3226 return 0; 3227 } 3228 3229 void r600_clear_surface_reg(struct radeon_device *rdev, int reg) 3230 { 3231 /* FIXME: implement */ 3232 } 3233 3234 static int r600_startup(struct radeon_device *rdev) 3235 { 3236 struct radeon_ring *ring; 3237 int r; 3238 3239 /* enable pcie gen2 link */ 3240 r600_pcie_gen2_enable(rdev); 3241 3242 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { 3243 r = r600_init_microcode(rdev); 3244 if (r) { 3245 DRM_ERROR("Failed to load firmware!\n"); 3246 return r; 3247 } 3248 } 3249 3250 r = r600_vram_scratch_init(rdev); 3251 if (r) 3252 return r; 3253 3254 r600_mc_program(rdev); 3255 if (rdev->flags & RADEON_IS_AGP) { 3256 r600_agp_enable(rdev); 3257 } else { 3258 r = r600_pcie_gart_enable(rdev); 3259 if (r) 3260 return r; 3261 } 3262 r600_gpu_init(rdev); 3263 r = r600_blit_init(rdev); 3264 if (r) { 3265 r600_blit_fini(rdev); 3266 rdev->asic->copy.copy = NULL; 3267 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); 3268 } 3269 3270 /* allocate wb buffer */ 3271 r = radeon_wb_init(rdev); 3272 if (r) 3273 return r; 3274 3275 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 3276 if (r) { 3277 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 3278 return r; 3279 } 3280 3281 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX); 3282 if (r) { 3283 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); 3284 return r; 3285 } 3286 3287 /* Enable IRQ */ 3288 if (!rdev->irq.installed) { 3289 r = radeon_irq_kms_init(rdev); 3290 if (r) 3291 return r; 3292 } 3293 3294 r = r600_irq_init(rdev); 3295 if (r) { 3296 DRM_ERROR("radeon: IH init failed (%d).\n", r); 3297 radeon_irq_kms_fini(rdev); 3298 return r; 3299 } 3300 r600_irq_set(rdev); 3301 3302 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 3303 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, 3304 R600_CP_RB_RPTR, R600_CP_RB_WPTR, 3305 0, 0xfffff, RADEON_CP_PACKET2); 3306 if (r) 3307 return r; 3308 3309 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; 3310 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, 3311 DMA_RB_RPTR, DMA_RB_WPTR, 3312 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); 3313 if (r) 3314 return r; 3315 3316 r = r600_cp_load_microcode(rdev); 3317 if (r) 3318 return r; 3319 r = r600_cp_resume(rdev); 3320 if (r) 3321 return r; 3322 3323 r = r600_dma_resume(rdev); 3324 if (r) 3325 return r; 3326 3327 r = radeon_ib_pool_init(rdev); 3328 if (r) { 3329 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 3330 return r; 3331 } 3332 3333 r = r600_audio_init(rdev); 3334 if (r) { 3335 DRM_ERROR("radeon: audio init failed\n"); 3336 return r; 3337 } 3338 3339 return 0; 3340 } 3341 3342 void r600_vga_set_state(struct radeon_device *rdev, bool state) 3343 { 3344 uint32_t temp; 3345 3346 temp = RREG32(CONFIG_CNTL); 3347 if (state == false) { 3348 temp &= ~(1<<0); 3349 temp |= (1<<1); 3350 } else { 3351 temp &= ~(1<<1); 3352 } 3353 WREG32(CONFIG_CNTL, temp); 3354 } 3355 3356 int r600_resume(struct radeon_device *rdev) 3357 { 3358 int r; 3359 3360 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw, 3361 * posting will perform necessary task to bring back GPU into good 3362 * shape. 3363 */ 3364 /* post card */ 3365 atom_asic_init(rdev->mode_info.atom_context); 3366 3367 rdev->accel_working = true; 3368 r = r600_startup(rdev); 3369 if (r) { 3370 DRM_ERROR("r600 startup failed on resume\n"); 3371 rdev->accel_working = false; 3372 return r; 3373 } 3374 3375 return r; 3376 } 3377 3378 int r600_suspend(struct radeon_device *rdev) 3379 { 3380 r600_audio_fini(rdev); 3381 r600_cp_stop(rdev); 3382 r600_dma_stop(rdev); 3383 r600_irq_suspend(rdev); 3384 radeon_wb_disable(rdev); 3385 r600_pcie_gart_disable(rdev); 3386 3387 return 0; 3388 } 3389 3390 /* Plan is to move initialization in that function and use 3391 * helper function so that radeon_device_init pretty much 3392 * do nothing more than calling asic specific function. This 3393 * should also allow to remove a bunch of callback function 3394 * like vram_info. 3395 */ 3396 int r600_init(struct radeon_device *rdev) 3397 { 3398 int r; 3399 3400 if (r600_debugfs_mc_info_init(rdev)) { 3401 DRM_ERROR("Failed to register debugfs file for mc !\n"); 3402 } 3403 /* Read BIOS */ 3404 if (!radeon_get_bios(rdev)) { 3405 if (ASIC_IS_AVIVO(rdev)) 3406 return -EINVAL; 3407 } 3408 /* Must be an ATOMBIOS */ 3409 if (!rdev->is_atom_bios) { 3410 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n"); 3411 return -EINVAL; 3412 } 3413 r = radeon_atombios_init(rdev); 3414 if (r) 3415 return r; 3416 /* Post card if necessary */ 3417 if (!radeon_card_posted(rdev)) { 3418 if (!rdev->bios) { 3419 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); 3420 return -EINVAL; 3421 } 3422 DRM_INFO("GPU not posted. posting now...\n"); 3423 atom_asic_init(rdev->mode_info.atom_context); 3424 } 3425 /* Initialize scratch registers */ 3426 r600_scratch_init(rdev); 3427 /* Initialize surface registers */ 3428 radeon_surface_init(rdev); 3429 /* Initialize clocks */ 3430 radeon_get_clock_info(rdev->ddev); 3431 /* Fence driver */ 3432 r = radeon_fence_driver_init(rdev); 3433 if (r) 3434 return r; 3435 if (rdev->flags & RADEON_IS_AGP) { 3436 r = radeon_agp_init(rdev); 3437 if (r) 3438 radeon_agp_disable(rdev); 3439 } 3440 r = r600_mc_init(rdev); 3441 if (r) 3442 return r; 3443 /* Memory manager */ 3444 r = radeon_bo_init(rdev); 3445 if (r) 3446 return r; 3447 3448 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL; 3449 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024); 3450 3451 rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL; 3452 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024); 3453 3454 rdev->ih.ring_obj = NULL; 3455 r600_ih_ring_init(rdev, 64 * 1024); 3456 3457 r = r600_pcie_gart_init(rdev); 3458 if (r) 3459 return r; 3460 3461 rdev->accel_working = true; 3462 r = r600_startup(rdev); 3463 if (r) { 3464 dev_err(rdev->dev, "disabling GPU acceleration\n"); 3465 r600_cp_fini(rdev); 3466 r600_dma_fini(rdev); 3467 r600_irq_fini(rdev); 3468 radeon_wb_fini(rdev); 3469 radeon_ib_pool_fini(rdev); 3470 radeon_irq_kms_fini(rdev); 3471 r600_pcie_gart_fini(rdev); 3472 rdev->accel_working = false; 3473 } 3474 3475 return 0; 3476 } 3477 3478 void r600_fini(struct radeon_device *rdev) 3479 { 3480 r600_audio_fini(rdev); 3481 r600_blit_fini(rdev); 3482 r600_cp_fini(rdev); 3483 r600_dma_fini(rdev); 3484 r600_irq_fini(rdev); 3485 radeon_wb_fini(rdev); 3486 radeon_ib_pool_fini(rdev); 3487 radeon_irq_kms_fini(rdev); 3488 r600_pcie_gart_fini(rdev); 3489 r600_vram_scratch_fini(rdev); 3490 radeon_agp_fini(rdev); 3491 radeon_gem_fini(rdev); 3492 radeon_fence_driver_fini(rdev); 3493 radeon_bo_fini(rdev); 3494 radeon_atombios_fini(rdev); 3495 kfree(rdev->bios); 3496 rdev->bios = NULL; 3497 } 3498 3499 3500 /* 3501 * CS stuff 3502 */ 3503 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 3504 { 3505 struct radeon_ring *ring = &rdev->ring[ib->ring]; 3506 u32 next_rptr; 3507 3508 if (ring->rptr_save_reg) { 3509 next_rptr = ring->wptr + 3 + 4; 3510 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 3511 radeon_ring_write(ring, ((ring->rptr_save_reg - 3512 PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); 3513 radeon_ring_write(ring, next_rptr); 3514 } else if (rdev->wb.enabled) { 3515 next_rptr = ring->wptr + 5 + 4; 3516 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3)); 3517 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); 3518 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18)); 3519 radeon_ring_write(ring, next_rptr); 3520 radeon_ring_write(ring, 0); 3521 } 3522 3523 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 3524 radeon_ring_write(ring, 3525 #ifdef __BIG_ENDIAN 3526 (2 << 0) | 3527 #endif 3528 (ib->gpu_addr & 0xFFFFFFFC)); 3529 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF); 3530 radeon_ring_write(ring, ib->length_dw); 3531 } 3532 3533 void r600_uvd_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 3534 { 3535 struct radeon_ring *ring = &rdev->ring[ib->ring]; 3536 3537 radeon_ring_write(ring, PACKET0(UVD_RBC_IB_BASE, 0)); 3538 radeon_ring_write(ring, ib->gpu_addr); 3539 radeon_ring_write(ring, PACKET0(UVD_RBC_IB_SIZE, 0)); 3540 radeon_ring_write(ring, ib->length_dw); 3541 } 3542 3543 int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) 3544 { 3545 struct radeon_ib ib; 3546 uint32_t scratch; 3547 uint32_t tmp = 0; 3548 unsigned i; 3549 int r; 3550 3551 r = radeon_scratch_get(rdev, &scratch); 3552 if (r) { 3553 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); 3554 return r; 3555 } 3556 WREG32(scratch, 0xCAFEDEAD); 3557 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256); 3558 if (r) { 3559 DRM_ERROR("radeon: failed to get ib (%d).\n", r); 3560 goto free_scratch; 3561 } 3562 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1); 3563 ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 3564 ib.ptr[2] = 0xDEADBEEF; 3565 ib.length_dw = 3; 3566 r = radeon_ib_schedule(rdev, &ib, NULL); 3567 if (r) { 3568 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); 3569 goto free_ib; 3570 } 3571 r = radeon_fence_wait(ib.fence, false); 3572 if (r) { 3573 DRM_ERROR("radeon: fence wait failed (%d).\n", r); 3574 goto free_ib; 3575 } 3576 for (i = 0; i < rdev->usec_timeout; i++) { 3577 tmp = RREG32(scratch); 3578 if (tmp == 0xDEADBEEF) 3579 break; 3580 DRM_UDELAY(1); 3581 } 3582 if (i < rdev->usec_timeout) { 3583 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i); 3584 } else { 3585 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n", 3586 scratch, tmp); 3587 r = -EINVAL; 3588 } 3589 free_ib: 3590 radeon_ib_free(rdev, &ib); 3591 free_scratch: 3592 radeon_scratch_free(rdev, scratch); 3593 return r; 3594 } 3595 3596 /** 3597 * r600_dma_ib_test - test an IB on the DMA engine 3598 * 3599 * @rdev: radeon_device pointer 3600 * @ring: radeon_ring structure holding ring information 3601 * 3602 * Test a simple IB in the DMA ring (r6xx-SI). 3603 * Returns 0 on success, error on failure. 3604 */ 3605 int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) 3606 { 3607 struct radeon_ib ib; 3608 unsigned i; 3609 int r; 3610 void __iomem *ptr = (void *)rdev->vram_scratch.ptr; 3611 u32 tmp = 0; 3612 3613 if (!ptr) { 3614 DRM_ERROR("invalid vram scratch pointer\n"); 3615 return -EINVAL; 3616 } 3617 3618 tmp = 0xCAFEDEAD; 3619 writel(tmp, ptr); 3620 3621 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256); 3622 if (r) { 3623 DRM_ERROR("radeon: failed to get ib (%d).\n", r); 3624 return r; 3625 } 3626 3627 ib.ptr[0] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1); 3628 ib.ptr[1] = rdev->vram_scratch.gpu_addr & 0xfffffffc; 3629 ib.ptr[2] = upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff; 3630 ib.ptr[3] = 0xDEADBEEF; 3631 ib.length_dw = 4; 3632 3633 r = radeon_ib_schedule(rdev, &ib, NULL); 3634 if (r) { 3635 radeon_ib_free(rdev, &ib); 3636 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); 3637 return r; 3638 } 3639 r = radeon_fence_wait(ib.fence, false); 3640 if (r) { 3641 DRM_ERROR("radeon: fence wait failed (%d).\n", r); 3642 return r; 3643 } 3644 for (i = 0; i < rdev->usec_timeout; i++) { 3645 tmp = readl(ptr); 3646 if (tmp == 0xDEADBEEF) 3647 break; 3648 DRM_UDELAY(1); 3649 } 3650 if (i < rdev->usec_timeout) { 3651 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i); 3652 } else { 3653 DRM_ERROR("radeon: ib test failed (0x%08X)\n", tmp); 3654 r = -EINVAL; 3655 } 3656 radeon_ib_free(rdev, &ib); 3657 return r; 3658 } 3659 3660 int r600_uvd_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) 3661 { 3662 struct radeon_fence *fence = NULL; 3663 int r; 3664 3665 r = radeon_set_uvd_clocks(rdev, 53300, 40000); 3666 if (r) { 3667 DRM_ERROR("radeon: failed to raise UVD clocks (%d).\n", r); 3668 return r; 3669 } 3670 3671 r = radeon_uvd_get_create_msg(rdev, ring->idx, 1, NULL); 3672 if (r) { 3673 DRM_ERROR("radeon: failed to get create msg (%d).\n", r); 3674 goto error; 3675 } 3676 3677 r = radeon_uvd_get_destroy_msg(rdev, ring->idx, 1, &fence); 3678 if (r) { 3679 DRM_ERROR("radeon: failed to get destroy ib (%d).\n", r); 3680 goto error; 3681 } 3682 3683 r = radeon_fence_wait(fence, false); 3684 if (r) { 3685 DRM_ERROR("radeon: fence wait failed (%d).\n", r); 3686 goto error; 3687 } 3688 DRM_INFO("ib test on ring %d succeeded\n", ring->idx); 3689 error: 3690 radeon_fence_unref(&fence); 3691 radeon_set_uvd_clocks(rdev, 0, 0); 3692 return r; 3693 } 3694 3695 /** 3696 * r600_dma_ring_ib_execute - Schedule an IB on the DMA engine 3697 * 3698 * @rdev: radeon_device pointer 3699 * @ib: IB object to schedule 3700 * 3701 * Schedule an IB in the DMA ring (r6xx-r7xx). 3702 */ 3703 void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 3704 { 3705 struct radeon_ring *ring = &rdev->ring[ib->ring]; 3706 3707 if (rdev->wb.enabled) { 3708 u32 next_rptr = ring->wptr + 4; 3709 while ((next_rptr & 7) != 5) 3710 next_rptr++; 3711 next_rptr += 3; 3712 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1)); 3713 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); 3714 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff); 3715 radeon_ring_write(ring, next_rptr); 3716 } 3717 3718 /* The indirect buffer packet must end on an 8 DW boundary in the DMA ring. 3719 * Pad as necessary with NOPs. 3720 */ 3721 while ((ring->wptr & 7) != 5) 3722 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); 3723 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER, 0, 0, 0)); 3724 radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0)); 3725 radeon_ring_write(ring, (ib->length_dw << 16) | (upper_32_bits(ib->gpu_addr) & 0xFF)); 3726 3727 } 3728 3729 /* 3730 * Interrupts 3731 * 3732 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty 3733 * the same as the CP ring buffer, but in reverse. Rather than the CPU 3734 * writing to the ring and the GPU consuming, the GPU writes to the ring 3735 * and host consumes. As the host irq handler processes interrupts, it 3736 * increments the rptr. When the rptr catches up with the wptr, all the 3737 * current interrupts have been processed. 3738 */ 3739 3740 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size) 3741 { 3742 u32 rb_bufsz; 3743 3744 /* Align ring size */ 3745 rb_bufsz = drm_order(ring_size / 4); 3746 ring_size = (1 << rb_bufsz) * 4; 3747 rdev->ih.ring_size = ring_size; 3748 rdev->ih.ptr_mask = rdev->ih.ring_size - 1; 3749 rdev->ih.rptr = 0; 3750 } 3751 3752 int r600_ih_ring_alloc(struct radeon_device *rdev) 3753 { 3754 int r; 3755 3756 /* Allocate ring buffer */ 3757 if (rdev->ih.ring_obj == NULL) { 3758 r = radeon_bo_create(rdev, rdev->ih.ring_size, 3759 PAGE_SIZE, true, 3760 RADEON_GEM_DOMAIN_GTT, 3761 NULL, &rdev->ih.ring_obj); 3762 if (r) { 3763 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r); 3764 return r; 3765 } 3766 r = radeon_bo_reserve(rdev->ih.ring_obj, false); 3767 if (unlikely(r != 0)) 3768 return r; 3769 r = radeon_bo_pin(rdev->ih.ring_obj, 3770 RADEON_GEM_DOMAIN_GTT, 3771 &rdev->ih.gpu_addr); 3772 if (r) { 3773 radeon_bo_unreserve(rdev->ih.ring_obj); 3774 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r); 3775 return r; 3776 } 3777 r = radeon_bo_kmap(rdev->ih.ring_obj, 3778 (void **)&rdev->ih.ring); 3779 radeon_bo_unreserve(rdev->ih.ring_obj); 3780 if (r) { 3781 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r); 3782 return r; 3783 } 3784 } 3785 return 0; 3786 } 3787 3788 void r600_ih_ring_fini(struct radeon_device *rdev) 3789 { 3790 int r; 3791 if (rdev->ih.ring_obj) { 3792 r = radeon_bo_reserve(rdev->ih.ring_obj, false); 3793 if (likely(r == 0)) { 3794 radeon_bo_kunmap(rdev->ih.ring_obj); 3795 radeon_bo_unpin(rdev->ih.ring_obj); 3796 radeon_bo_unreserve(rdev->ih.ring_obj); 3797 } 3798 radeon_bo_unref(&rdev->ih.ring_obj); 3799 rdev->ih.ring = NULL; 3800 rdev->ih.ring_obj = NULL; 3801 } 3802 } 3803 3804 void r600_rlc_stop(struct radeon_device *rdev) 3805 { 3806 3807 if ((rdev->family >= CHIP_RV770) && 3808 (rdev->family <= CHIP_RV740)) { 3809 /* r7xx asics need to soft reset RLC before halting */ 3810 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC); 3811 RREG32(SRBM_SOFT_RESET); 3812 mdelay(15); 3813 WREG32(SRBM_SOFT_RESET, 0); 3814 RREG32(SRBM_SOFT_RESET); 3815 } 3816 3817 WREG32(RLC_CNTL, 0); 3818 } 3819 3820 static void r600_rlc_start(struct radeon_device *rdev) 3821 { 3822 WREG32(RLC_CNTL, RLC_ENABLE); 3823 } 3824 3825 static int r600_rlc_resume(struct radeon_device *rdev) 3826 { 3827 u32 i; 3828 const __be32 *fw_data; 3829 3830 if (!rdev->rlc_fw) 3831 return -EINVAL; 3832 3833 r600_rlc_stop(rdev); 3834 3835 WREG32(RLC_HB_CNTL, 0); 3836 3837 WREG32(RLC_HB_BASE, 0); 3838 WREG32(RLC_HB_RPTR, 0); 3839 WREG32(RLC_HB_WPTR, 0); 3840 WREG32(RLC_HB_WPTR_LSB_ADDR, 0); 3841 WREG32(RLC_HB_WPTR_MSB_ADDR, 0); 3842 WREG32(RLC_MC_CNTL, 0); 3843 WREG32(RLC_UCODE_CNTL, 0); 3844 3845 fw_data = (const __be32 *)rdev->rlc_fw->data; 3846 if (rdev->family >= CHIP_RV770) { 3847 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) { 3848 WREG32(RLC_UCODE_ADDR, i); 3849 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); 3850 } 3851 } else { 3852 for (i = 0; i < R600_RLC_UCODE_SIZE; i++) { 3853 WREG32(RLC_UCODE_ADDR, i); 3854 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); 3855 } 3856 } 3857 WREG32(RLC_UCODE_ADDR, 0); 3858 3859 r600_rlc_start(rdev); 3860 3861 return 0; 3862 } 3863 3864 static void r600_enable_interrupts(struct radeon_device *rdev) 3865 { 3866 u32 ih_cntl = RREG32(IH_CNTL); 3867 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); 3868 3869 ih_cntl |= ENABLE_INTR; 3870 ih_rb_cntl |= IH_RB_ENABLE; 3871 WREG32(IH_CNTL, ih_cntl); 3872 WREG32(IH_RB_CNTL, ih_rb_cntl); 3873 rdev->ih.enabled = true; 3874 } 3875 3876 void r600_disable_interrupts(struct radeon_device *rdev) 3877 { 3878 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); 3879 u32 ih_cntl = RREG32(IH_CNTL); 3880 3881 ih_rb_cntl &= ~IH_RB_ENABLE; 3882 ih_cntl &= ~ENABLE_INTR; 3883 WREG32(IH_RB_CNTL, ih_rb_cntl); 3884 WREG32(IH_CNTL, ih_cntl); 3885 /* set rptr, wptr to 0 */ 3886 WREG32(IH_RB_RPTR, 0); 3887 WREG32(IH_RB_WPTR, 0); 3888 rdev->ih.enabled = false; 3889 rdev->ih.rptr = 0; 3890 } 3891 3892 static void r600_disable_interrupt_state(struct radeon_device *rdev) 3893 { 3894 u32 tmp; 3895 3896 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); 3897 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE; 3898 WREG32(DMA_CNTL, tmp); 3899 WREG32(GRBM_INT_CNTL, 0); 3900 WREG32(DxMODE_INT_MASK, 0); 3901 WREG32(D1GRPH_INTERRUPT_CONTROL, 0); 3902 WREG32(D2GRPH_INTERRUPT_CONTROL, 0); 3903 if (ASIC_IS_DCE3(rdev)) { 3904 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0); 3905 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0); 3906 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3907 WREG32(DC_HPD1_INT_CONTROL, tmp); 3908 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3909 WREG32(DC_HPD2_INT_CONTROL, tmp); 3910 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3911 WREG32(DC_HPD3_INT_CONTROL, tmp); 3912 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3913 WREG32(DC_HPD4_INT_CONTROL, tmp); 3914 if (ASIC_IS_DCE32(rdev)) { 3915 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3916 WREG32(DC_HPD5_INT_CONTROL, tmp); 3917 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3918 WREG32(DC_HPD6_INT_CONTROL, tmp); 3919 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3920 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp); 3921 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3922 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp); 3923 } else { 3924 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3925 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); 3926 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3927 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp); 3928 } 3929 } else { 3930 WREG32(DACA_AUTODETECT_INT_CONTROL, 0); 3931 WREG32(DACB_AUTODETECT_INT_CONTROL, 0); 3932 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; 3933 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 3934 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; 3935 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 3936 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; 3937 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); 3938 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3939 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); 3940 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3941 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp); 3942 } 3943 } 3944 3945 int r600_irq_init(struct radeon_device *rdev) 3946 { 3947 int ret = 0; 3948 int rb_bufsz; 3949 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; 3950 3951 /* allocate ring */ 3952 ret = r600_ih_ring_alloc(rdev); 3953 if (ret) 3954 return ret; 3955 3956 /* disable irqs */ 3957 r600_disable_interrupts(rdev); 3958 3959 /* init rlc */ 3960 if (rdev->family >= CHIP_CEDAR) 3961 ret = evergreen_rlc_resume(rdev); 3962 else 3963 ret = r600_rlc_resume(rdev); 3964 if (ret) { 3965 r600_ih_ring_fini(rdev); 3966 return ret; 3967 } 3968 3969 /* setup interrupt control */ 3970 /* set dummy read address to ring address */ 3971 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8); 3972 interrupt_cntl = RREG32(INTERRUPT_CNTL); 3973 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi 3974 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN 3975 */ 3976 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE; 3977 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */ 3978 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN; 3979 WREG32(INTERRUPT_CNTL, interrupt_cntl); 3980 3981 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8); 3982 rb_bufsz = drm_order(rdev->ih.ring_size / 4); 3983 3984 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE | 3985 IH_WPTR_OVERFLOW_CLEAR | 3986 (rb_bufsz << 1)); 3987 3988 if (rdev->wb.enabled) 3989 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE; 3990 3991 /* set the writeback address whether it's enabled or not */ 3992 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC); 3993 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF); 3994 3995 WREG32(IH_RB_CNTL, ih_rb_cntl); 3996 3997 /* set rptr, wptr to 0 */ 3998 WREG32(IH_RB_RPTR, 0); 3999 WREG32(IH_RB_WPTR, 0); 4000 4001 /* Default settings for IH_CNTL (disabled at first) */ 4002 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10); 4003 /* RPTR_REARM only works if msi's are enabled */ 4004 if (rdev->msi_enabled) 4005 ih_cntl |= RPTR_REARM; 4006 WREG32(IH_CNTL, ih_cntl); 4007 4008 /* force the active interrupt state to all disabled */ 4009 if (rdev->family >= CHIP_CEDAR) 4010 evergreen_disable_interrupt_state(rdev); 4011 else 4012 r600_disable_interrupt_state(rdev); 4013 4014 /* at this point everything should be setup correctly to enable master */ 4015 pci_set_master(rdev->pdev); 4016 4017 /* enable irqs */ 4018 r600_enable_interrupts(rdev); 4019 4020 return ret; 4021 } 4022 4023 void r600_irq_suspend(struct radeon_device *rdev) 4024 { 4025 r600_irq_disable(rdev); 4026 r600_rlc_stop(rdev); 4027 } 4028 4029 void r600_irq_fini(struct radeon_device *rdev) 4030 { 4031 r600_irq_suspend(rdev); 4032 r600_ih_ring_fini(rdev); 4033 } 4034 4035 int r600_irq_set(struct radeon_device *rdev) 4036 { 4037 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; 4038 u32 mode_int = 0; 4039 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0; 4040 u32 grbm_int_cntl = 0; 4041 u32 hdmi0, hdmi1; 4042 u32 d1grph = 0, d2grph = 0; 4043 u32 dma_cntl; 4044 u32 thermal_int = 0; 4045 4046 if (!rdev->irq.installed) { 4047 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); 4048 return -EINVAL; 4049 } 4050 /* don't enable anything if the ih is disabled */ 4051 if (!rdev->ih.enabled) { 4052 r600_disable_interrupts(rdev); 4053 /* force the active interrupt state to all disabled */ 4054 r600_disable_interrupt_state(rdev); 4055 return 0; 4056 } 4057 4058 if (ASIC_IS_DCE3(rdev)) { 4059 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN; 4060 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN; 4061 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN; 4062 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN; 4063 if (ASIC_IS_DCE32(rdev)) { 4064 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; 4065 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN; 4066 hdmi0 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~AFMT_AZ_FORMAT_WTRIG_MASK; 4067 hdmi1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~AFMT_AZ_FORMAT_WTRIG_MASK; 4068 } else { 4069 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 4070 hdmi1 = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 4071 } 4072 } else { 4073 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN; 4074 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN; 4075 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN; 4076 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 4077 hdmi1 = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 4078 } 4079 4080 dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE; 4081 4082 if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) { 4083 thermal_int = RREG32(CG_THERMAL_INT) & 4084 ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); 4085 } else if (rdev->family >= CHIP_RV770) { 4086 thermal_int = RREG32(RV770_CG_THERMAL_INT) & 4087 ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); 4088 } 4089 if (rdev->irq.dpm_thermal) { 4090 DRM_DEBUG("dpm thermal\n"); 4091 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW; 4092 } 4093 4094 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { 4095 DRM_DEBUG("r600_irq_set: sw int\n"); 4096 cp_int_cntl |= RB_INT_ENABLE; 4097 cp_int_cntl |= TIME_STAMP_INT_ENABLE; 4098 } 4099 4100 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) { 4101 DRM_DEBUG("r600_irq_set: sw int dma\n"); 4102 dma_cntl |= TRAP_ENABLE; 4103 } 4104 4105 if (rdev->irq.crtc_vblank_int[0] || 4106 atomic_read(&rdev->irq.pflip[0])) { 4107 DRM_DEBUG("r600_irq_set: vblank 0\n"); 4108 mode_int |= D1MODE_VBLANK_INT_MASK; 4109 } 4110 if (rdev->irq.crtc_vblank_int[1] || 4111 atomic_read(&rdev->irq.pflip[1])) { 4112 DRM_DEBUG("r600_irq_set: vblank 1\n"); 4113 mode_int |= D2MODE_VBLANK_INT_MASK; 4114 } 4115 if (rdev->irq.hpd[0]) { 4116 DRM_DEBUG("r600_irq_set: hpd 1\n"); 4117 hpd1 |= DC_HPDx_INT_EN; 4118 } 4119 if (rdev->irq.hpd[1]) { 4120 DRM_DEBUG("r600_irq_set: hpd 2\n"); 4121 hpd2 |= DC_HPDx_INT_EN; 4122 } 4123 if (rdev->irq.hpd[2]) { 4124 DRM_DEBUG("r600_irq_set: hpd 3\n"); 4125 hpd3 |= DC_HPDx_INT_EN; 4126 } 4127 if (rdev->irq.hpd[3]) { 4128 DRM_DEBUG("r600_irq_set: hpd 4\n"); 4129 hpd4 |= DC_HPDx_INT_EN; 4130 } 4131 if (rdev->irq.hpd[4]) { 4132 DRM_DEBUG("r600_irq_set: hpd 5\n"); 4133 hpd5 |= DC_HPDx_INT_EN; 4134 } 4135 if (rdev->irq.hpd[5]) { 4136 DRM_DEBUG("r600_irq_set: hpd 6\n"); 4137 hpd6 |= DC_HPDx_INT_EN; 4138 } 4139 if (rdev->irq.afmt[0]) { 4140 DRM_DEBUG("r600_irq_set: hdmi 0\n"); 4141 hdmi0 |= HDMI0_AZ_FORMAT_WTRIG_MASK; 4142 } 4143 if (rdev->irq.afmt[1]) { 4144 DRM_DEBUG("r600_irq_set: hdmi 0\n"); 4145 hdmi1 |= HDMI0_AZ_FORMAT_WTRIG_MASK; 4146 } 4147 4148 WREG32(CP_INT_CNTL, cp_int_cntl); 4149 WREG32(DMA_CNTL, dma_cntl); 4150 WREG32(DxMODE_INT_MASK, mode_int); 4151 WREG32(D1GRPH_INTERRUPT_CONTROL, d1grph); 4152 WREG32(D2GRPH_INTERRUPT_CONTROL, d2grph); 4153 WREG32(GRBM_INT_CNTL, grbm_int_cntl); 4154 if (ASIC_IS_DCE3(rdev)) { 4155 WREG32(DC_HPD1_INT_CONTROL, hpd1); 4156 WREG32(DC_HPD2_INT_CONTROL, hpd2); 4157 WREG32(DC_HPD3_INT_CONTROL, hpd3); 4158 WREG32(DC_HPD4_INT_CONTROL, hpd4); 4159 if (ASIC_IS_DCE32(rdev)) { 4160 WREG32(DC_HPD5_INT_CONTROL, hpd5); 4161 WREG32(DC_HPD6_INT_CONTROL, hpd6); 4162 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, hdmi0); 4163 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, hdmi1); 4164 } else { 4165 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0); 4166 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, hdmi1); 4167 } 4168 } else { 4169 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); 4170 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); 4171 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3); 4172 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0); 4173 WREG32(HDMI1_AUDIO_PACKET_CONTROL, hdmi1); 4174 } 4175 if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) { 4176 WREG32(CG_THERMAL_INT, thermal_int); 4177 } else if (rdev->family >= CHIP_RV770) { 4178 WREG32(RV770_CG_THERMAL_INT, thermal_int); 4179 } 4180 4181 return 0; 4182 } 4183 4184 static void r600_irq_ack(struct radeon_device *rdev) 4185 { 4186 u32 tmp; 4187 4188 if (ASIC_IS_DCE3(rdev)) { 4189 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS); 4190 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE); 4191 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2); 4192 if (ASIC_IS_DCE32(rdev)) { 4193 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0); 4194 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1); 4195 } else { 4196 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); 4197 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS); 4198 } 4199 } else { 4200 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS); 4201 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); 4202 rdev->irq.stat_regs.r600.disp_int_cont2 = 0; 4203 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); 4204 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS); 4205 } 4206 rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS); 4207 rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS); 4208 4209 if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED) 4210 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR); 4211 if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED) 4212 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR); 4213 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) 4214 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK); 4215 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) 4216 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK); 4217 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) 4218 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK); 4219 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) 4220 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK); 4221 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) { 4222 if (ASIC_IS_DCE3(rdev)) { 4223 tmp = RREG32(DC_HPD1_INT_CONTROL); 4224 tmp |= DC_HPDx_INT_ACK; 4225 WREG32(DC_HPD1_INT_CONTROL, tmp); 4226 } else { 4227 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); 4228 tmp |= DC_HPDx_INT_ACK; 4229 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 4230 } 4231 } 4232 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) { 4233 if (ASIC_IS_DCE3(rdev)) { 4234 tmp = RREG32(DC_HPD2_INT_CONTROL); 4235 tmp |= DC_HPDx_INT_ACK; 4236 WREG32(DC_HPD2_INT_CONTROL, tmp); 4237 } else { 4238 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); 4239 tmp |= DC_HPDx_INT_ACK; 4240 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 4241 } 4242 } 4243 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) { 4244 if (ASIC_IS_DCE3(rdev)) { 4245 tmp = RREG32(DC_HPD3_INT_CONTROL); 4246 tmp |= DC_HPDx_INT_ACK; 4247 WREG32(DC_HPD3_INT_CONTROL, tmp); 4248 } else { 4249 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); 4250 tmp |= DC_HPDx_INT_ACK; 4251 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); 4252 } 4253 } 4254 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) { 4255 tmp = RREG32(DC_HPD4_INT_CONTROL); 4256 tmp |= DC_HPDx_INT_ACK; 4257 WREG32(DC_HPD4_INT_CONTROL, tmp); 4258 } 4259 if (ASIC_IS_DCE32(rdev)) { 4260 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) { 4261 tmp = RREG32(DC_HPD5_INT_CONTROL); 4262 tmp |= DC_HPDx_INT_ACK; 4263 WREG32(DC_HPD5_INT_CONTROL, tmp); 4264 } 4265 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) { 4266 tmp = RREG32(DC_HPD5_INT_CONTROL); 4267 tmp |= DC_HPDx_INT_ACK; 4268 WREG32(DC_HPD6_INT_CONTROL, tmp); 4269 } 4270 if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG) { 4271 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0); 4272 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; 4273 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp); 4274 } 4275 if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG) { 4276 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1); 4277 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; 4278 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp); 4279 } 4280 } else { 4281 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) { 4282 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL); 4283 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; 4284 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); 4285 } 4286 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) { 4287 if (ASIC_IS_DCE3(rdev)) { 4288 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL); 4289 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; 4290 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp); 4291 } else { 4292 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL); 4293 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; 4294 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp); 4295 } 4296 } 4297 } 4298 } 4299 4300 void r600_irq_disable(struct radeon_device *rdev) 4301 { 4302 r600_disable_interrupts(rdev); 4303 /* Wait and acknowledge irq */ 4304 mdelay(1); 4305 r600_irq_ack(rdev); 4306 r600_disable_interrupt_state(rdev); 4307 } 4308 4309 static u32 r600_get_ih_wptr(struct radeon_device *rdev) 4310 { 4311 u32 wptr, tmp; 4312 4313 if (rdev->wb.enabled) 4314 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]); 4315 else 4316 wptr = RREG32(IH_RB_WPTR); 4317 4318 if (wptr & RB_OVERFLOW) { 4319 /* When a ring buffer overflow happen start parsing interrupt 4320 * from the last not overwritten vector (wptr + 16). Hopefully 4321 * this should allow us to catchup. 4322 */ 4323 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n", 4324 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask); 4325 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; 4326 tmp = RREG32(IH_RB_CNTL); 4327 tmp |= IH_WPTR_OVERFLOW_CLEAR; 4328 WREG32(IH_RB_CNTL, tmp); 4329 } 4330 return (wptr & rdev->ih.ptr_mask); 4331 } 4332 4333 /* r600 IV Ring 4334 * Each IV ring entry is 128 bits: 4335 * [7:0] - interrupt source id 4336 * [31:8] - reserved 4337 * [59:32] - interrupt source data 4338 * [127:60] - reserved 4339 * 4340 * The basic interrupt vector entries 4341 * are decoded as follows: 4342 * src_id src_data description 4343 * 1 0 D1 Vblank 4344 * 1 1 D1 Vline 4345 * 5 0 D2 Vblank 4346 * 5 1 D2 Vline 4347 * 19 0 FP Hot plug detection A 4348 * 19 1 FP Hot plug detection B 4349 * 19 2 DAC A auto-detection 4350 * 19 3 DAC B auto-detection 4351 * 21 4 HDMI block A 4352 * 21 5 HDMI block B 4353 * 176 - CP_INT RB 4354 * 177 - CP_INT IB1 4355 * 178 - CP_INT IB2 4356 * 181 - EOP Interrupt 4357 * 233 - GUI Idle 4358 * 4359 * Note, these are based on r600 and may need to be 4360 * adjusted or added to on newer asics 4361 */ 4362 4363 int r600_irq_process(struct radeon_device *rdev) 4364 { 4365 u32 wptr; 4366 u32 rptr; 4367 u32 src_id, src_data; 4368 u32 ring_index; 4369 bool queue_hotplug = false; 4370 bool queue_hdmi = false; 4371 bool queue_thermal = false; 4372 4373 if (!rdev->ih.enabled || rdev->shutdown) 4374 return IRQ_NONE; 4375 4376 /* No MSIs, need a dummy read to flush PCI DMAs */ 4377 if (!rdev->msi_enabled) 4378 RREG32(IH_RB_WPTR); 4379 4380 wptr = r600_get_ih_wptr(rdev); 4381 4382 restart_ih: 4383 /* is somebody else already processing irqs? */ 4384 if (atomic_xchg(&rdev->ih.lock, 1)) 4385 return IRQ_NONE; 4386 4387 rptr = rdev->ih.rptr; 4388 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr); 4389 4390 /* Order reading of wptr vs. reading of IH ring data */ 4391 rmb(); 4392 4393 /* display interrupts */ 4394 r600_irq_ack(rdev); 4395 4396 while (rptr != wptr) { 4397 /* wptr/rptr are in bytes! */ 4398 ring_index = rptr / 4; 4399 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff; 4400 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff; 4401 4402 switch (src_id) { 4403 case 1: /* D1 vblank/vline */ 4404 switch (src_data) { 4405 case 0: /* D1 vblank */ 4406 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) { 4407 if (rdev->irq.crtc_vblank_int[0]) { 4408 drm_handle_vblank(rdev->ddev, 0); 4409 rdev->pm.vblank_sync = true; 4410 wake_up(&rdev->irq.vblank_queue); 4411 } 4412 if (atomic_read(&rdev->irq.pflip[0])) 4413 radeon_crtc_handle_flip(rdev, 0); 4414 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT; 4415 DRM_DEBUG("IH: D1 vblank\n"); 4416 } 4417 break; 4418 case 1: /* D1 vline */ 4419 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) { 4420 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT; 4421 DRM_DEBUG("IH: D1 vline\n"); 4422 } 4423 break; 4424 default: 4425 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 4426 break; 4427 } 4428 break; 4429 case 5: /* D2 vblank/vline */ 4430 switch (src_data) { 4431 case 0: /* D2 vblank */ 4432 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) { 4433 if (rdev->irq.crtc_vblank_int[1]) { 4434 drm_handle_vblank(rdev->ddev, 1); 4435 rdev->pm.vblank_sync = true; 4436 wake_up(&rdev->irq.vblank_queue); 4437 } 4438 if (atomic_read(&rdev->irq.pflip[1])) 4439 radeon_crtc_handle_flip(rdev, 1); 4440 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT; 4441 DRM_DEBUG("IH: D2 vblank\n"); 4442 } 4443 break; 4444 case 1: /* D1 vline */ 4445 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) { 4446 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT; 4447 DRM_DEBUG("IH: D2 vline\n"); 4448 } 4449 break; 4450 default: 4451 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 4452 break; 4453 } 4454 break; 4455 case 19: /* HPD/DAC hotplug */ 4456 switch (src_data) { 4457 case 0: 4458 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) { 4459 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT; 4460 queue_hotplug = true; 4461 DRM_DEBUG("IH: HPD1\n"); 4462 } 4463 break; 4464 case 1: 4465 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) { 4466 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT; 4467 queue_hotplug = true; 4468 DRM_DEBUG("IH: HPD2\n"); 4469 } 4470 break; 4471 case 4: 4472 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) { 4473 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT; 4474 queue_hotplug = true; 4475 DRM_DEBUG("IH: HPD3\n"); 4476 } 4477 break; 4478 case 5: 4479 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) { 4480 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT; 4481 queue_hotplug = true; 4482 DRM_DEBUG("IH: HPD4\n"); 4483 } 4484 break; 4485 case 10: 4486 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) { 4487 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT; 4488 queue_hotplug = true; 4489 DRM_DEBUG("IH: HPD5\n"); 4490 } 4491 break; 4492 case 12: 4493 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) { 4494 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT; 4495 queue_hotplug = true; 4496 DRM_DEBUG("IH: HPD6\n"); 4497 } 4498 break; 4499 default: 4500 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 4501 break; 4502 } 4503 break; 4504 case 21: /* hdmi */ 4505 switch (src_data) { 4506 case 4: 4507 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) { 4508 rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG; 4509 queue_hdmi = true; 4510 DRM_DEBUG("IH: HDMI0\n"); 4511 } 4512 break; 4513 case 5: 4514 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) { 4515 rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG; 4516 queue_hdmi = true; 4517 DRM_DEBUG("IH: HDMI1\n"); 4518 } 4519 break; 4520 default: 4521 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); 4522 break; 4523 } 4524 break; 4525 case 176: /* CP_INT in ring buffer */ 4526 case 177: /* CP_INT in IB1 */ 4527 case 178: /* CP_INT in IB2 */ 4528 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data); 4529 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 4530 break; 4531 case 181: /* CP EOP event */ 4532 DRM_DEBUG("IH: CP EOP\n"); 4533 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 4534 break; 4535 case 224: /* DMA trap event */ 4536 DRM_DEBUG("IH: DMA trap\n"); 4537 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX); 4538 break; 4539 case 230: /* thermal low to high */ 4540 DRM_DEBUG("IH: thermal low to high\n"); 4541 rdev->pm.dpm.thermal.high_to_low = false; 4542 queue_thermal = true; 4543 break; 4544 case 231: /* thermal high to low */ 4545 DRM_DEBUG("IH: thermal high to low\n"); 4546 rdev->pm.dpm.thermal.high_to_low = true; 4547 queue_thermal = true; 4548 break; 4549 case 233: /* GUI IDLE */ 4550 DRM_DEBUG("IH: GUI idle\n"); 4551 break; 4552 default: 4553 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 4554 break; 4555 } 4556 4557 /* wptr/rptr are in bytes! */ 4558 rptr += 16; 4559 rptr &= rdev->ih.ptr_mask; 4560 } 4561 if (queue_hotplug) 4562 schedule_work(&rdev->hotplug_work); 4563 if (queue_hdmi) 4564 schedule_work(&rdev->audio_work); 4565 if (queue_thermal && rdev->pm.dpm_enabled) 4566 schedule_work(&rdev->pm.dpm.thermal.work); 4567 rdev->ih.rptr = rptr; 4568 WREG32(IH_RB_RPTR, rdev->ih.rptr); 4569 atomic_set(&rdev->ih.lock, 0); 4570 4571 /* make sure wptr hasn't changed while processing */ 4572 wptr = r600_get_ih_wptr(rdev); 4573 if (wptr != rptr) 4574 goto restart_ih; 4575 4576 return IRQ_HANDLED; 4577 } 4578 4579 /* 4580 * Debugfs info 4581 */ 4582 #if defined(CONFIG_DEBUG_FS) 4583 4584 static int r600_debugfs_mc_info(struct seq_file *m, void *data) 4585 { 4586 struct drm_info_node *node = (struct drm_info_node *) m->private; 4587 struct drm_device *dev = node->minor->dev; 4588 struct radeon_device *rdev = dev->dev_private; 4589 4590 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS); 4591 DREG32_SYS(m, rdev, VM_L2_STATUS); 4592 return 0; 4593 } 4594 4595 static struct drm_info_list r600_mc_info_list[] = { 4596 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL}, 4597 }; 4598 #endif 4599 4600 int r600_debugfs_mc_info_init(struct radeon_device *rdev) 4601 { 4602 #if defined(CONFIG_DEBUG_FS) 4603 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list)); 4604 #else 4605 return 0; 4606 #endif 4607 } 4608 4609 /** 4610 * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl 4611 * rdev: radeon device structure 4612 * bo: buffer object struct which userspace is waiting for idle 4613 * 4614 * Some R6XX/R7XX doesn't seems to take into account HDP flush performed 4615 * through ring buffer, this leads to corruption in rendering, see 4616 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we 4617 * directly perform HDP flush by writing register through MMIO. 4618 */ 4619 void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo) 4620 { 4621 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read 4622 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL. 4623 * This seems to cause problems on some AGP cards. Just use the old 4624 * method for them. 4625 */ 4626 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) && 4627 rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) { 4628 void __iomem *ptr = (void *)rdev->vram_scratch.ptr; 4629 u32 tmp; 4630 4631 WREG32(HDP_DEBUG1, 0); 4632 tmp = readl((void __iomem *)ptr); 4633 } else 4634 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); 4635 } 4636 4637 void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes) 4638 { 4639 u32 link_width_cntl, mask; 4640 4641 if (rdev->flags & RADEON_IS_IGP) 4642 return; 4643 4644 if (!(rdev->flags & RADEON_IS_PCIE)) 4645 return; 4646 4647 /* x2 cards have a special sequence */ 4648 if (ASIC_IS_X2(rdev)) 4649 return; 4650 4651 radeon_gui_idle(rdev); 4652 4653 switch (lanes) { 4654 case 0: 4655 mask = RADEON_PCIE_LC_LINK_WIDTH_X0; 4656 break; 4657 case 1: 4658 mask = RADEON_PCIE_LC_LINK_WIDTH_X1; 4659 break; 4660 case 2: 4661 mask = RADEON_PCIE_LC_LINK_WIDTH_X2; 4662 break; 4663 case 4: 4664 mask = RADEON_PCIE_LC_LINK_WIDTH_X4; 4665 break; 4666 case 8: 4667 mask = RADEON_PCIE_LC_LINK_WIDTH_X8; 4668 break; 4669 case 12: 4670 /* not actually supported */ 4671 mask = RADEON_PCIE_LC_LINK_WIDTH_X12; 4672 break; 4673 case 16: 4674 mask = RADEON_PCIE_LC_LINK_WIDTH_X16; 4675 break; 4676 default: 4677 DRM_ERROR("invalid pcie lane request: %d\n", lanes); 4678 return; 4679 } 4680 4681 link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 4682 link_width_cntl &= ~RADEON_PCIE_LC_LINK_WIDTH_MASK; 4683 link_width_cntl |= mask << RADEON_PCIE_LC_LINK_WIDTH_SHIFT; 4684 link_width_cntl |= (RADEON_PCIE_LC_RECONFIG_NOW | 4685 R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE); 4686 4687 WREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4688 } 4689 4690 int r600_get_pcie_lanes(struct radeon_device *rdev) 4691 { 4692 u32 link_width_cntl; 4693 4694 if (rdev->flags & RADEON_IS_IGP) 4695 return 0; 4696 4697 if (!(rdev->flags & RADEON_IS_PCIE)) 4698 return 0; 4699 4700 /* x2 cards have a special sequence */ 4701 if (ASIC_IS_X2(rdev)) 4702 return 0; 4703 4704 radeon_gui_idle(rdev); 4705 4706 link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 4707 4708 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) { 4709 case RADEON_PCIE_LC_LINK_WIDTH_X1: 4710 return 1; 4711 case RADEON_PCIE_LC_LINK_WIDTH_X2: 4712 return 2; 4713 case RADEON_PCIE_LC_LINK_WIDTH_X4: 4714 return 4; 4715 case RADEON_PCIE_LC_LINK_WIDTH_X8: 4716 return 8; 4717 case RADEON_PCIE_LC_LINK_WIDTH_X12: 4718 /* not actually supported */ 4719 return 12; 4720 case RADEON_PCIE_LC_LINK_WIDTH_X0: 4721 case RADEON_PCIE_LC_LINK_WIDTH_X16: 4722 default: 4723 return 16; 4724 } 4725 } 4726 4727 static void r600_pcie_gen2_enable(struct radeon_device *rdev) 4728 { 4729 u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp; 4730 u16 link_cntl2; 4731 4732 if (radeon_pcie_gen2 == 0) 4733 return; 4734 4735 if (rdev->flags & RADEON_IS_IGP) 4736 return; 4737 4738 if (!(rdev->flags & RADEON_IS_PCIE)) 4739 return; 4740 4741 /* x2 cards have a special sequence */ 4742 if (ASIC_IS_X2(rdev)) 4743 return; 4744 4745 /* only RV6xx+ chips are supported */ 4746 if (rdev->family <= CHIP_R600) 4747 return; 4748 4749 if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) && 4750 (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT)) 4751 return; 4752 4753 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 4754 if (speed_cntl & LC_CURRENT_DATA_RATE) { 4755 DRM_INFO("PCIE gen 2 link speeds already enabled\n"); 4756 return; 4757 } 4758 4759 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"); 4760 4761 /* 55 nm r6xx asics */ 4762 if ((rdev->family == CHIP_RV670) || 4763 (rdev->family == CHIP_RV620) || 4764 (rdev->family == CHIP_RV635)) { 4765 /* advertise upconfig capability */ 4766 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); 4767 link_width_cntl &= ~LC_UPCONFIGURE_DIS; 4768 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4769 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); 4770 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) { 4771 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; 4772 link_width_cntl &= ~(LC_LINK_WIDTH_MASK | 4773 LC_RECONFIG_ARC_MISSING_ESCAPE); 4774 link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN; 4775 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4776 } else { 4777 link_width_cntl |= LC_UPCONFIGURE_DIS; 4778 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4779 } 4780 } 4781 4782 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 4783 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) && 4784 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { 4785 4786 /* 55 nm r6xx asics */ 4787 if ((rdev->family == CHIP_RV670) || 4788 (rdev->family == CHIP_RV620) || 4789 (rdev->family == CHIP_RV635)) { 4790 WREG32(MM_CFGREGS_CNTL, 0x8); 4791 link_cntl2 = RREG32(0x4088); 4792 WREG32(MM_CFGREGS_CNTL, 0); 4793 /* not supported yet */ 4794 if (link_cntl2 & SELECTABLE_DEEMPHASIS) 4795 return; 4796 } 4797 4798 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK; 4799 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT); 4800 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK; 4801 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE; 4802 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE; 4803 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 4804 4805 tmp = RREG32(0x541c); 4806 WREG32(0x541c, tmp | 0x8); 4807 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN); 4808 link_cntl2 = RREG16(0x4088); 4809 link_cntl2 &= ~TARGET_LINK_SPEED_MASK; 4810 link_cntl2 |= 0x2; 4811 WREG16(0x4088, link_cntl2); 4812 WREG32(MM_CFGREGS_CNTL, 0); 4813 4814 if ((rdev->family == CHIP_RV670) || 4815 (rdev->family == CHIP_RV620) || 4816 (rdev->family == CHIP_RV635)) { 4817 training_cntl = RREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL); 4818 training_cntl &= ~LC_POINT_7_PLUS_EN; 4819 WREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL, training_cntl); 4820 } else { 4821 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 4822 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN; 4823 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 4824 } 4825 4826 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 4827 speed_cntl |= LC_GEN2_EN_STRAP; 4828 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 4829 4830 } else { 4831 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); 4832 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */ 4833 if (1) 4834 link_width_cntl |= LC_UPCONFIGURE_DIS; 4835 else 4836 link_width_cntl &= ~LC_UPCONFIGURE_DIS; 4837 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4838 } 4839 } 4840 4841 /** 4842 * r600_get_gpu_clock_counter - return GPU clock counter snapshot 4843 * 4844 * @rdev: radeon_device pointer 4845 * 4846 * Fetches a GPU clock counter snapshot (R6xx-cayman). 4847 * Returns the 64 bit clock counter snapshot. 4848 */ 4849 uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev) 4850 { 4851 uint64_t clock; 4852 4853 mutex_lock(&rdev->gpu_clock_mutex); 4854 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1); 4855 clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) | 4856 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 4857 mutex_unlock(&rdev->gpu_clock_mutex); 4858 return clock; 4859 } 4860