1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/slab.h> 29 #include <linux/seq_file.h> 30 #include <linux/firmware.h> 31 #include <linux/platform_device.h> 32 #include <linux/module.h> 33 #include <drm/drmP.h> 34 #include <drm/radeon_drm.h> 35 #include "radeon.h" 36 #include "radeon_asic.h" 37 #include "radeon_mode.h" 38 #include "r600d.h" 39 #include "atom.h" 40 #include "avivod.h" 41 42 #define PFP_UCODE_SIZE 576 43 #define PM4_UCODE_SIZE 1792 44 #define RLC_UCODE_SIZE 768 45 #define R700_PFP_UCODE_SIZE 848 46 #define R700_PM4_UCODE_SIZE 1360 47 #define R700_RLC_UCODE_SIZE 1024 48 #define EVERGREEN_PFP_UCODE_SIZE 1120 49 #define EVERGREEN_PM4_UCODE_SIZE 1376 50 #define EVERGREEN_RLC_UCODE_SIZE 768 51 #define CAYMAN_RLC_UCODE_SIZE 1024 52 #define ARUBA_RLC_UCODE_SIZE 1536 53 54 /* Firmware Names */ 55 MODULE_FIRMWARE("radeon/R600_pfp.bin"); 56 MODULE_FIRMWARE("radeon/R600_me.bin"); 57 MODULE_FIRMWARE("radeon/RV610_pfp.bin"); 58 MODULE_FIRMWARE("radeon/RV610_me.bin"); 59 MODULE_FIRMWARE("radeon/RV630_pfp.bin"); 60 MODULE_FIRMWARE("radeon/RV630_me.bin"); 61 MODULE_FIRMWARE("radeon/RV620_pfp.bin"); 62 MODULE_FIRMWARE("radeon/RV620_me.bin"); 63 MODULE_FIRMWARE("radeon/RV635_pfp.bin"); 64 MODULE_FIRMWARE("radeon/RV635_me.bin"); 65 MODULE_FIRMWARE("radeon/RV670_pfp.bin"); 66 MODULE_FIRMWARE("radeon/RV670_me.bin"); 67 MODULE_FIRMWARE("radeon/RS780_pfp.bin"); 68 MODULE_FIRMWARE("radeon/RS780_me.bin"); 69 MODULE_FIRMWARE("radeon/RV770_pfp.bin"); 70 MODULE_FIRMWARE("radeon/RV770_me.bin"); 71 MODULE_FIRMWARE("radeon/RV730_pfp.bin"); 72 MODULE_FIRMWARE("radeon/RV730_me.bin"); 73 MODULE_FIRMWARE("radeon/RV710_pfp.bin"); 74 MODULE_FIRMWARE("radeon/RV710_me.bin"); 75 MODULE_FIRMWARE("radeon/R600_rlc.bin"); 76 MODULE_FIRMWARE("radeon/R700_rlc.bin"); 77 MODULE_FIRMWARE("radeon/CEDAR_pfp.bin"); 78 MODULE_FIRMWARE("radeon/CEDAR_me.bin"); 79 MODULE_FIRMWARE("radeon/CEDAR_rlc.bin"); 80 MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin"); 81 MODULE_FIRMWARE("radeon/REDWOOD_me.bin"); 82 MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin"); 83 MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin"); 84 MODULE_FIRMWARE("radeon/JUNIPER_me.bin"); 85 MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin"); 86 MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin"); 87 MODULE_FIRMWARE("radeon/CYPRESS_me.bin"); 88 MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin"); 89 MODULE_FIRMWARE("radeon/PALM_pfp.bin"); 90 MODULE_FIRMWARE("radeon/PALM_me.bin"); 91 MODULE_FIRMWARE("radeon/SUMO_rlc.bin"); 92 MODULE_FIRMWARE("radeon/SUMO_pfp.bin"); 93 MODULE_FIRMWARE("radeon/SUMO_me.bin"); 94 MODULE_FIRMWARE("radeon/SUMO2_pfp.bin"); 95 MODULE_FIRMWARE("radeon/SUMO2_me.bin"); 96 97 int r600_debugfs_mc_info_init(struct radeon_device *rdev); 98 99 /* r600,rv610,rv630,rv620,rv635,rv670 */ 100 int r600_mc_wait_for_idle(struct radeon_device *rdev); 101 static void r600_gpu_init(struct radeon_device *rdev); 102 void r600_fini(struct radeon_device *rdev); 103 void r600_irq_disable(struct radeon_device *rdev); 104 static void r600_pcie_gen2_enable(struct radeon_device *rdev); 105 106 /* get temperature in millidegrees */ 107 int rv6xx_get_temp(struct radeon_device *rdev) 108 { 109 u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >> 110 ASIC_T_SHIFT; 111 int actual_temp = temp & 0xff; 112 113 if (temp & 0x100) 114 actual_temp -= 256; 115 116 return actual_temp * 1000; 117 } 118 119 void r600_pm_get_dynpm_state(struct radeon_device *rdev) 120 { 121 int i; 122 123 rdev->pm.dynpm_can_upclock = true; 124 rdev->pm.dynpm_can_downclock = true; 125 126 /* power state array is low to high, default is first */ 127 if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) { 128 int min_power_state_index = 0; 129 130 if (rdev->pm.num_power_states > 2) 131 min_power_state_index = 1; 132 133 switch (rdev->pm.dynpm_planned_action) { 134 case DYNPM_ACTION_MINIMUM: 135 rdev->pm.requested_power_state_index = min_power_state_index; 136 rdev->pm.requested_clock_mode_index = 0; 137 rdev->pm.dynpm_can_downclock = false; 138 break; 139 case DYNPM_ACTION_DOWNCLOCK: 140 if (rdev->pm.current_power_state_index == min_power_state_index) { 141 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 142 rdev->pm.dynpm_can_downclock = false; 143 } else { 144 if (rdev->pm.active_crtc_count > 1) { 145 for (i = 0; i < rdev->pm.num_power_states; i++) { 146 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 147 continue; 148 else if (i >= rdev->pm.current_power_state_index) { 149 rdev->pm.requested_power_state_index = 150 rdev->pm.current_power_state_index; 151 break; 152 } else { 153 rdev->pm.requested_power_state_index = i; 154 break; 155 } 156 } 157 } else { 158 if (rdev->pm.current_power_state_index == 0) 159 rdev->pm.requested_power_state_index = 160 rdev->pm.num_power_states - 1; 161 else 162 rdev->pm.requested_power_state_index = 163 rdev->pm.current_power_state_index - 1; 164 } 165 } 166 rdev->pm.requested_clock_mode_index = 0; 167 /* don't use the power state if crtcs are active and no display flag is set */ 168 if ((rdev->pm.active_crtc_count > 0) && 169 (rdev->pm.power_state[rdev->pm.requested_power_state_index]. 170 clock_info[rdev->pm.requested_clock_mode_index].flags & 171 RADEON_PM_MODE_NO_DISPLAY)) { 172 rdev->pm.requested_power_state_index++; 173 } 174 break; 175 case DYNPM_ACTION_UPCLOCK: 176 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) { 177 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 178 rdev->pm.dynpm_can_upclock = false; 179 } else { 180 if (rdev->pm.active_crtc_count > 1) { 181 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) { 182 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 183 continue; 184 else if (i <= rdev->pm.current_power_state_index) { 185 rdev->pm.requested_power_state_index = 186 rdev->pm.current_power_state_index; 187 break; 188 } else { 189 rdev->pm.requested_power_state_index = i; 190 break; 191 } 192 } 193 } else 194 rdev->pm.requested_power_state_index = 195 rdev->pm.current_power_state_index + 1; 196 } 197 rdev->pm.requested_clock_mode_index = 0; 198 break; 199 case DYNPM_ACTION_DEFAULT: 200 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; 201 rdev->pm.requested_clock_mode_index = 0; 202 rdev->pm.dynpm_can_upclock = false; 203 break; 204 case DYNPM_ACTION_NONE: 205 default: 206 DRM_ERROR("Requested mode for not defined action\n"); 207 return; 208 } 209 } else { 210 /* XXX select a power state based on AC/DC, single/dualhead, etc. */ 211 /* for now just select the first power state and switch between clock modes */ 212 /* power state array is low to high, default is first (0) */ 213 if (rdev->pm.active_crtc_count > 1) { 214 rdev->pm.requested_power_state_index = -1; 215 /* start at 1 as we don't want the default mode */ 216 for (i = 1; i < rdev->pm.num_power_states; i++) { 217 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 218 continue; 219 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) || 220 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) { 221 rdev->pm.requested_power_state_index = i; 222 break; 223 } 224 } 225 /* if nothing selected, grab the default state. */ 226 if (rdev->pm.requested_power_state_index == -1) 227 rdev->pm.requested_power_state_index = 0; 228 } else 229 rdev->pm.requested_power_state_index = 1; 230 231 switch (rdev->pm.dynpm_planned_action) { 232 case DYNPM_ACTION_MINIMUM: 233 rdev->pm.requested_clock_mode_index = 0; 234 rdev->pm.dynpm_can_downclock = false; 235 break; 236 case DYNPM_ACTION_DOWNCLOCK: 237 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) { 238 if (rdev->pm.current_clock_mode_index == 0) { 239 rdev->pm.requested_clock_mode_index = 0; 240 rdev->pm.dynpm_can_downclock = false; 241 } else 242 rdev->pm.requested_clock_mode_index = 243 rdev->pm.current_clock_mode_index - 1; 244 } else { 245 rdev->pm.requested_clock_mode_index = 0; 246 rdev->pm.dynpm_can_downclock = false; 247 } 248 /* don't use the power state if crtcs are active and no display flag is set */ 249 if ((rdev->pm.active_crtc_count > 0) && 250 (rdev->pm.power_state[rdev->pm.requested_power_state_index]. 251 clock_info[rdev->pm.requested_clock_mode_index].flags & 252 RADEON_PM_MODE_NO_DISPLAY)) { 253 rdev->pm.requested_clock_mode_index++; 254 } 255 break; 256 case DYNPM_ACTION_UPCLOCK: 257 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) { 258 if (rdev->pm.current_clock_mode_index == 259 (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) { 260 rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index; 261 rdev->pm.dynpm_can_upclock = false; 262 } else 263 rdev->pm.requested_clock_mode_index = 264 rdev->pm.current_clock_mode_index + 1; 265 } else { 266 rdev->pm.requested_clock_mode_index = 267 rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1; 268 rdev->pm.dynpm_can_upclock = false; 269 } 270 break; 271 case DYNPM_ACTION_DEFAULT: 272 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; 273 rdev->pm.requested_clock_mode_index = 0; 274 rdev->pm.dynpm_can_upclock = false; 275 break; 276 case DYNPM_ACTION_NONE: 277 default: 278 DRM_ERROR("Requested mode for not defined action\n"); 279 return; 280 } 281 } 282 283 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n", 284 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 285 clock_info[rdev->pm.requested_clock_mode_index].sclk, 286 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 287 clock_info[rdev->pm.requested_clock_mode_index].mclk, 288 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 289 pcie_lanes); 290 } 291 292 void rs780_pm_init_profile(struct radeon_device *rdev) 293 { 294 if (rdev->pm.num_power_states == 2) { 295 /* default */ 296 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 297 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 298 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 299 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 300 /* low sh */ 301 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; 302 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; 303 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 304 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 305 /* mid sh */ 306 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; 307 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0; 308 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 309 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 310 /* high sh */ 311 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; 312 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1; 313 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 314 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 315 /* low mh */ 316 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; 317 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0; 318 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 319 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 320 /* mid mh */ 321 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; 322 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0; 323 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 324 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 325 /* high mh */ 326 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; 327 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1; 328 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 329 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 330 } else if (rdev->pm.num_power_states == 3) { 331 /* default */ 332 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 333 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 334 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 335 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 336 /* low sh */ 337 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1; 338 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1; 339 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 340 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 341 /* mid sh */ 342 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1; 343 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; 344 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 345 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 346 /* high sh */ 347 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1; 348 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2; 349 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 350 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 351 /* low mh */ 352 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1; 353 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1; 354 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 355 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 356 /* mid mh */ 357 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1; 358 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1; 359 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 360 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 361 /* high mh */ 362 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1; 363 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2; 364 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 365 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 366 } else { 367 /* default */ 368 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 369 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 370 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 371 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 372 /* low sh */ 373 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2; 374 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2; 375 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 376 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 377 /* mid sh */ 378 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2; 379 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2; 380 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 381 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 382 /* high sh */ 383 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2; 384 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3; 385 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 386 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 387 /* low mh */ 388 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2; 389 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0; 390 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 391 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 392 /* mid mh */ 393 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2; 394 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0; 395 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 396 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 397 /* high mh */ 398 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2; 399 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3; 400 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 401 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 402 } 403 } 404 405 void r600_pm_init_profile(struct radeon_device *rdev) 406 { 407 int idx; 408 409 if (rdev->family == CHIP_R600) { 410 /* XXX */ 411 /* default */ 412 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 413 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 414 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 415 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 416 /* low sh */ 417 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 418 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 419 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 420 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 421 /* mid sh */ 422 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 423 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 424 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 425 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 426 /* high sh */ 427 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 428 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 429 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 430 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 431 /* low mh */ 432 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 433 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 434 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 435 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 436 /* mid mh */ 437 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 438 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 439 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 440 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 441 /* high mh */ 442 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 443 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 444 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 445 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 446 } else { 447 if (rdev->pm.num_power_states < 4) { 448 /* default */ 449 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 450 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 451 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 452 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; 453 /* low sh */ 454 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1; 455 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1; 456 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 457 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 458 /* mid sh */ 459 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1; 460 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; 461 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 462 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; 463 /* high sh */ 464 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1; 465 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1; 466 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 467 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; 468 /* low mh */ 469 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2; 470 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2; 471 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 472 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 473 /* low mh */ 474 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2; 475 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2; 476 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 477 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; 478 /* high mh */ 479 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2; 480 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2; 481 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 482 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; 483 } else { 484 /* default */ 485 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 486 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 487 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 488 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; 489 /* low sh */ 490 if (rdev->flags & RADEON_IS_MOBILITY) 491 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0); 492 else 493 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); 494 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx; 495 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx; 496 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 497 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 498 /* mid sh */ 499 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx; 500 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx; 501 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 502 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; 503 /* high sh */ 504 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); 505 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx; 506 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx; 507 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 508 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; 509 /* low mh */ 510 if (rdev->flags & RADEON_IS_MOBILITY) 511 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1); 512 else 513 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1); 514 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx; 515 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx; 516 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 517 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 518 /* mid mh */ 519 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx; 520 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx; 521 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 522 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; 523 /* high mh */ 524 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1); 525 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx; 526 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx; 527 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 528 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; 529 } 530 } 531 } 532 533 void r600_pm_misc(struct radeon_device *rdev) 534 { 535 int req_ps_idx = rdev->pm.requested_power_state_index; 536 int req_cm_idx = rdev->pm.requested_clock_mode_index; 537 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx]; 538 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage; 539 540 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) { 541 /* 0xff01 is a flag rather then an actual voltage */ 542 if (voltage->voltage == 0xff01) 543 return; 544 if (voltage->voltage != rdev->pm.current_vddc) { 545 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); 546 rdev->pm.current_vddc = voltage->voltage; 547 DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage); 548 } 549 } 550 } 551 552 bool r600_gui_idle(struct radeon_device *rdev) 553 { 554 if (RREG32(GRBM_STATUS) & GUI_ACTIVE) 555 return false; 556 else 557 return true; 558 } 559 560 /* hpd for digital panel detect/disconnect */ 561 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) 562 { 563 bool connected = false; 564 565 if (ASIC_IS_DCE3(rdev)) { 566 switch (hpd) { 567 case RADEON_HPD_1: 568 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE) 569 connected = true; 570 break; 571 case RADEON_HPD_2: 572 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE) 573 connected = true; 574 break; 575 case RADEON_HPD_3: 576 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE) 577 connected = true; 578 break; 579 case RADEON_HPD_4: 580 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE) 581 connected = true; 582 break; 583 /* DCE 3.2 */ 584 case RADEON_HPD_5: 585 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE) 586 connected = true; 587 break; 588 case RADEON_HPD_6: 589 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE) 590 connected = true; 591 break; 592 default: 593 break; 594 } 595 } else { 596 switch (hpd) { 597 case RADEON_HPD_1: 598 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) 599 connected = true; 600 break; 601 case RADEON_HPD_2: 602 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) 603 connected = true; 604 break; 605 case RADEON_HPD_3: 606 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) 607 connected = true; 608 break; 609 default: 610 break; 611 } 612 } 613 return connected; 614 } 615 616 void r600_hpd_set_polarity(struct radeon_device *rdev, 617 enum radeon_hpd_id hpd) 618 { 619 u32 tmp; 620 bool connected = r600_hpd_sense(rdev, hpd); 621 622 if (ASIC_IS_DCE3(rdev)) { 623 switch (hpd) { 624 case RADEON_HPD_1: 625 tmp = RREG32(DC_HPD1_INT_CONTROL); 626 if (connected) 627 tmp &= ~DC_HPDx_INT_POLARITY; 628 else 629 tmp |= DC_HPDx_INT_POLARITY; 630 WREG32(DC_HPD1_INT_CONTROL, tmp); 631 break; 632 case RADEON_HPD_2: 633 tmp = RREG32(DC_HPD2_INT_CONTROL); 634 if (connected) 635 tmp &= ~DC_HPDx_INT_POLARITY; 636 else 637 tmp |= DC_HPDx_INT_POLARITY; 638 WREG32(DC_HPD2_INT_CONTROL, tmp); 639 break; 640 case RADEON_HPD_3: 641 tmp = RREG32(DC_HPD3_INT_CONTROL); 642 if (connected) 643 tmp &= ~DC_HPDx_INT_POLARITY; 644 else 645 tmp |= DC_HPDx_INT_POLARITY; 646 WREG32(DC_HPD3_INT_CONTROL, tmp); 647 break; 648 case RADEON_HPD_4: 649 tmp = RREG32(DC_HPD4_INT_CONTROL); 650 if (connected) 651 tmp &= ~DC_HPDx_INT_POLARITY; 652 else 653 tmp |= DC_HPDx_INT_POLARITY; 654 WREG32(DC_HPD4_INT_CONTROL, tmp); 655 break; 656 case RADEON_HPD_5: 657 tmp = RREG32(DC_HPD5_INT_CONTROL); 658 if (connected) 659 tmp &= ~DC_HPDx_INT_POLARITY; 660 else 661 tmp |= DC_HPDx_INT_POLARITY; 662 WREG32(DC_HPD5_INT_CONTROL, tmp); 663 break; 664 /* DCE 3.2 */ 665 case RADEON_HPD_6: 666 tmp = RREG32(DC_HPD6_INT_CONTROL); 667 if (connected) 668 tmp &= ~DC_HPDx_INT_POLARITY; 669 else 670 tmp |= DC_HPDx_INT_POLARITY; 671 WREG32(DC_HPD6_INT_CONTROL, tmp); 672 break; 673 default: 674 break; 675 } 676 } else { 677 switch (hpd) { 678 case RADEON_HPD_1: 679 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); 680 if (connected) 681 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; 682 else 683 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; 684 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 685 break; 686 case RADEON_HPD_2: 687 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); 688 if (connected) 689 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; 690 else 691 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; 692 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 693 break; 694 case RADEON_HPD_3: 695 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); 696 if (connected) 697 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; 698 else 699 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; 700 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); 701 break; 702 default: 703 break; 704 } 705 } 706 } 707 708 void r600_hpd_init(struct radeon_device *rdev) 709 { 710 struct drm_device *dev = rdev->ddev; 711 struct drm_connector *connector; 712 unsigned enable = 0; 713 714 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 715 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 716 717 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || 718 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { 719 /* don't try to enable hpd on eDP or LVDS avoid breaking the 720 * aux dp channel on imac and help (but not completely fix) 721 * https://bugzilla.redhat.com/show_bug.cgi?id=726143 722 */ 723 continue; 724 } 725 if (ASIC_IS_DCE3(rdev)) { 726 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa); 727 if (ASIC_IS_DCE32(rdev)) 728 tmp |= DC_HPDx_EN; 729 730 switch (radeon_connector->hpd.hpd) { 731 case RADEON_HPD_1: 732 WREG32(DC_HPD1_CONTROL, tmp); 733 break; 734 case RADEON_HPD_2: 735 WREG32(DC_HPD2_CONTROL, tmp); 736 break; 737 case RADEON_HPD_3: 738 WREG32(DC_HPD3_CONTROL, tmp); 739 break; 740 case RADEON_HPD_4: 741 WREG32(DC_HPD4_CONTROL, tmp); 742 break; 743 /* DCE 3.2 */ 744 case RADEON_HPD_5: 745 WREG32(DC_HPD5_CONTROL, tmp); 746 break; 747 case RADEON_HPD_6: 748 WREG32(DC_HPD6_CONTROL, tmp); 749 break; 750 default: 751 break; 752 } 753 } else { 754 switch (radeon_connector->hpd.hpd) { 755 case RADEON_HPD_1: 756 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN); 757 break; 758 case RADEON_HPD_2: 759 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN); 760 break; 761 case RADEON_HPD_3: 762 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN); 763 break; 764 default: 765 break; 766 } 767 } 768 enable |= 1 << radeon_connector->hpd.hpd; 769 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); 770 } 771 radeon_irq_kms_enable_hpd(rdev, enable); 772 } 773 774 void r600_hpd_fini(struct radeon_device *rdev) 775 { 776 struct drm_device *dev = rdev->ddev; 777 struct drm_connector *connector; 778 unsigned disable = 0; 779 780 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 781 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 782 if (ASIC_IS_DCE3(rdev)) { 783 switch (radeon_connector->hpd.hpd) { 784 case RADEON_HPD_1: 785 WREG32(DC_HPD1_CONTROL, 0); 786 break; 787 case RADEON_HPD_2: 788 WREG32(DC_HPD2_CONTROL, 0); 789 break; 790 case RADEON_HPD_3: 791 WREG32(DC_HPD3_CONTROL, 0); 792 break; 793 case RADEON_HPD_4: 794 WREG32(DC_HPD4_CONTROL, 0); 795 break; 796 /* DCE 3.2 */ 797 case RADEON_HPD_5: 798 WREG32(DC_HPD5_CONTROL, 0); 799 break; 800 case RADEON_HPD_6: 801 WREG32(DC_HPD6_CONTROL, 0); 802 break; 803 default: 804 break; 805 } 806 } else { 807 switch (radeon_connector->hpd.hpd) { 808 case RADEON_HPD_1: 809 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0); 810 break; 811 case RADEON_HPD_2: 812 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0); 813 break; 814 case RADEON_HPD_3: 815 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0); 816 break; 817 default: 818 break; 819 } 820 } 821 disable |= 1 << radeon_connector->hpd.hpd; 822 } 823 radeon_irq_kms_disable_hpd(rdev, disable); 824 } 825 826 /* 827 * R600 PCIE GART 828 */ 829 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev) 830 { 831 unsigned i; 832 u32 tmp; 833 834 /* flush hdp cache so updates hit vram */ 835 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) && 836 !(rdev->flags & RADEON_IS_AGP)) { 837 void __iomem *ptr = (void *)rdev->gart.ptr; 838 u32 tmp; 839 840 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read 841 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL 842 * This seems to cause problems on some AGP cards. Just use the old 843 * method for them. 844 */ 845 WREG32(HDP_DEBUG1, 0); 846 tmp = readl((void __iomem *)ptr); 847 } else 848 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); 849 850 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12); 851 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12); 852 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1)); 853 for (i = 0; i < rdev->usec_timeout; i++) { 854 /* read MC_STATUS */ 855 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE); 856 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT; 857 if (tmp == 2) { 858 printk(KERN_WARNING "[drm] r600 flush TLB failed\n"); 859 return; 860 } 861 if (tmp) { 862 return; 863 } 864 udelay(1); 865 } 866 } 867 868 int r600_pcie_gart_init(struct radeon_device *rdev) 869 { 870 int r; 871 872 if (rdev->gart.robj) { 873 WARN(1, "R600 PCIE GART already initialized\n"); 874 return 0; 875 } 876 /* Initialize common gart structure */ 877 r = radeon_gart_init(rdev); 878 if (r) 879 return r; 880 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; 881 return radeon_gart_table_vram_alloc(rdev); 882 } 883 884 static int r600_pcie_gart_enable(struct radeon_device *rdev) 885 { 886 u32 tmp; 887 int r, i; 888 889 if (rdev->gart.robj == NULL) { 890 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 891 return -EINVAL; 892 } 893 r = radeon_gart_table_vram_pin(rdev); 894 if (r) 895 return r; 896 radeon_gart_restore(rdev); 897 898 /* Setup L2 cache */ 899 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 900 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 901 EFFECTIVE_L2_QUEUE_SIZE(7)); 902 WREG32(VM_L2_CNTL2, 0); 903 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); 904 /* Setup TLB control */ 905 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | 906 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 907 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | 908 ENABLE_WAIT_L2_QUERY; 909 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); 910 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); 911 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); 912 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); 913 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); 914 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); 915 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); 916 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); 917 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); 918 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); 919 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); 920 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); 921 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 922 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 923 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); 924 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); 925 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); 926 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | 927 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); 928 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 929 (u32)(rdev->dummy_page.addr >> 12)); 930 for (i = 1; i < 7; i++) 931 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 932 933 r600_pcie_gart_tlb_flush(rdev); 934 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 935 (unsigned)(rdev->mc.gtt_size >> 20), 936 (unsigned long long)rdev->gart.table_addr); 937 rdev->gart.ready = true; 938 return 0; 939 } 940 941 static void r600_pcie_gart_disable(struct radeon_device *rdev) 942 { 943 u32 tmp; 944 int i; 945 946 /* Disable all tables */ 947 for (i = 0; i < 7; i++) 948 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 949 950 /* Disable L2 cache */ 951 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | 952 EFFECTIVE_L2_QUEUE_SIZE(7)); 953 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); 954 /* Setup L1 TLB control */ 955 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | 956 ENABLE_WAIT_L2_QUERY; 957 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); 958 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); 959 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); 960 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); 961 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); 962 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); 963 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); 964 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); 965 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp); 966 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp); 967 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); 968 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); 969 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp); 970 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); 971 radeon_gart_table_vram_unpin(rdev); 972 } 973 974 static void r600_pcie_gart_fini(struct radeon_device *rdev) 975 { 976 radeon_gart_fini(rdev); 977 r600_pcie_gart_disable(rdev); 978 radeon_gart_table_vram_free(rdev); 979 } 980 981 static void r600_agp_enable(struct radeon_device *rdev) 982 { 983 u32 tmp; 984 int i; 985 986 /* Setup L2 cache */ 987 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 988 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 989 EFFECTIVE_L2_QUEUE_SIZE(7)); 990 WREG32(VM_L2_CNTL2, 0); 991 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); 992 /* Setup TLB control */ 993 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | 994 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 995 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | 996 ENABLE_WAIT_L2_QUERY; 997 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); 998 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); 999 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); 1000 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); 1001 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); 1002 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); 1003 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); 1004 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); 1005 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); 1006 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); 1007 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); 1008 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); 1009 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 1010 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 1011 for (i = 0; i < 7; i++) 1012 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 1013 } 1014 1015 int r600_mc_wait_for_idle(struct radeon_device *rdev) 1016 { 1017 unsigned i; 1018 u32 tmp; 1019 1020 for (i = 0; i < rdev->usec_timeout; i++) { 1021 /* read MC_STATUS */ 1022 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00; 1023 if (!tmp) 1024 return 0; 1025 udelay(1); 1026 } 1027 return -1; 1028 } 1029 1030 static void r600_mc_program(struct radeon_device *rdev) 1031 { 1032 struct rv515_mc_save save; 1033 u32 tmp; 1034 int i, j; 1035 1036 /* Initialize HDP */ 1037 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 1038 WREG32((0x2c14 + j), 0x00000000); 1039 WREG32((0x2c18 + j), 0x00000000); 1040 WREG32((0x2c1c + j), 0x00000000); 1041 WREG32((0x2c20 + j), 0x00000000); 1042 WREG32((0x2c24 + j), 0x00000000); 1043 } 1044 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); 1045 1046 rv515_mc_stop(rdev, &save); 1047 if (r600_mc_wait_for_idle(rdev)) { 1048 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1049 } 1050 /* Lockout access through VGA aperture (doesn't exist before R600) */ 1051 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); 1052 /* Update configuration */ 1053 if (rdev->flags & RADEON_IS_AGP) { 1054 if (rdev->mc.vram_start < rdev->mc.gtt_start) { 1055 /* VRAM before AGP */ 1056 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 1057 rdev->mc.vram_start >> 12); 1058 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 1059 rdev->mc.gtt_end >> 12); 1060 } else { 1061 /* VRAM after AGP */ 1062 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 1063 rdev->mc.gtt_start >> 12); 1064 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 1065 rdev->mc.vram_end >> 12); 1066 } 1067 } else { 1068 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12); 1069 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12); 1070 } 1071 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); 1072 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; 1073 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); 1074 WREG32(MC_VM_FB_LOCATION, tmp); 1075 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); 1076 WREG32(HDP_NONSURFACE_INFO, (2 << 7)); 1077 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); 1078 if (rdev->flags & RADEON_IS_AGP) { 1079 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22); 1080 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22); 1081 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); 1082 } else { 1083 WREG32(MC_VM_AGP_BASE, 0); 1084 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); 1085 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); 1086 } 1087 if (r600_mc_wait_for_idle(rdev)) { 1088 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1089 } 1090 rv515_mc_resume(rdev, &save); 1091 /* we need to own VRAM, so turn off the VGA renderer here 1092 * to stop it overwriting our objects */ 1093 rv515_vga_render_disable(rdev); 1094 } 1095 1096 /** 1097 * r600_vram_gtt_location - try to find VRAM & GTT location 1098 * @rdev: radeon device structure holding all necessary informations 1099 * @mc: memory controller structure holding memory informations 1100 * 1101 * Function will place try to place VRAM at same place as in CPU (PCI) 1102 * address space as some GPU seems to have issue when we reprogram at 1103 * different address space. 1104 * 1105 * If there is not enough space to fit the unvisible VRAM after the 1106 * aperture then we limit the VRAM size to the aperture. 1107 * 1108 * If we are using AGP then place VRAM adjacent to AGP aperture are we need 1109 * them to be in one from GPU point of view so that we can program GPU to 1110 * catch access outside them (weird GPU policy see ??). 1111 * 1112 * This function will never fails, worst case are limiting VRAM or GTT. 1113 * 1114 * Note: GTT start, end, size should be initialized before calling this 1115 * function on AGP platform. 1116 */ 1117 static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) 1118 { 1119 u64 size_bf, size_af; 1120 1121 if (mc->mc_vram_size > 0xE0000000) { 1122 /* leave room for at least 512M GTT */ 1123 dev_warn(rdev->dev, "limiting VRAM\n"); 1124 mc->real_vram_size = 0xE0000000; 1125 mc->mc_vram_size = 0xE0000000; 1126 } 1127 if (rdev->flags & RADEON_IS_AGP) { 1128 size_bf = mc->gtt_start; 1129 size_af = 0xFFFFFFFF - mc->gtt_end; 1130 if (size_bf > size_af) { 1131 if (mc->mc_vram_size > size_bf) { 1132 dev_warn(rdev->dev, "limiting VRAM\n"); 1133 mc->real_vram_size = size_bf; 1134 mc->mc_vram_size = size_bf; 1135 } 1136 mc->vram_start = mc->gtt_start - mc->mc_vram_size; 1137 } else { 1138 if (mc->mc_vram_size > size_af) { 1139 dev_warn(rdev->dev, "limiting VRAM\n"); 1140 mc->real_vram_size = size_af; 1141 mc->mc_vram_size = size_af; 1142 } 1143 mc->vram_start = mc->gtt_end + 1; 1144 } 1145 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 1146 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n", 1147 mc->mc_vram_size >> 20, mc->vram_start, 1148 mc->vram_end, mc->real_vram_size >> 20); 1149 } else { 1150 u64 base = 0; 1151 if (rdev->flags & RADEON_IS_IGP) { 1152 base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF; 1153 base <<= 24; 1154 } 1155 radeon_vram_location(rdev, &rdev->mc, base); 1156 rdev->mc.gtt_base_align = 0; 1157 radeon_gtt_location(rdev, mc); 1158 } 1159 } 1160 1161 static int r600_mc_init(struct radeon_device *rdev) 1162 { 1163 u32 tmp; 1164 int chansize, numchan; 1165 1166 /* Get VRAM informations */ 1167 rdev->mc.vram_is_ddr = true; 1168 tmp = RREG32(RAMCFG); 1169 if (tmp & CHANSIZE_OVERRIDE) { 1170 chansize = 16; 1171 } else if (tmp & CHANSIZE_MASK) { 1172 chansize = 64; 1173 } else { 1174 chansize = 32; 1175 } 1176 tmp = RREG32(CHMAP); 1177 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { 1178 case 0: 1179 default: 1180 numchan = 1; 1181 break; 1182 case 1: 1183 numchan = 2; 1184 break; 1185 case 2: 1186 numchan = 4; 1187 break; 1188 case 3: 1189 numchan = 8; 1190 break; 1191 } 1192 rdev->mc.vram_width = numchan * chansize; 1193 /* Could aper size report 0 ? */ 1194 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); 1195 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); 1196 /* Setup GPU memory space */ 1197 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); 1198 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); 1199 rdev->mc.visible_vram_size = rdev->mc.aper_size; 1200 r600_vram_gtt_location(rdev, &rdev->mc); 1201 1202 if (rdev->flags & RADEON_IS_IGP) { 1203 rs690_pm_info(rdev); 1204 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); 1205 } 1206 radeon_update_bandwidth_info(rdev); 1207 return 0; 1208 } 1209 1210 int r600_vram_scratch_init(struct radeon_device *rdev) 1211 { 1212 int r; 1213 1214 if (rdev->vram_scratch.robj == NULL) { 1215 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, 1216 PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM, 1217 NULL, &rdev->vram_scratch.robj); 1218 if (r) { 1219 return r; 1220 } 1221 } 1222 1223 r = radeon_bo_reserve(rdev->vram_scratch.robj, false); 1224 if (unlikely(r != 0)) 1225 return r; 1226 r = radeon_bo_pin(rdev->vram_scratch.robj, 1227 RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr); 1228 if (r) { 1229 radeon_bo_unreserve(rdev->vram_scratch.robj); 1230 return r; 1231 } 1232 r = radeon_bo_kmap(rdev->vram_scratch.robj, 1233 (void **)&rdev->vram_scratch.ptr); 1234 if (r) 1235 radeon_bo_unpin(rdev->vram_scratch.robj); 1236 radeon_bo_unreserve(rdev->vram_scratch.robj); 1237 1238 return r; 1239 } 1240 1241 void r600_vram_scratch_fini(struct radeon_device *rdev) 1242 { 1243 int r; 1244 1245 if (rdev->vram_scratch.robj == NULL) { 1246 return; 1247 } 1248 r = radeon_bo_reserve(rdev->vram_scratch.robj, false); 1249 if (likely(r == 0)) { 1250 radeon_bo_kunmap(rdev->vram_scratch.robj); 1251 radeon_bo_unpin(rdev->vram_scratch.robj); 1252 radeon_bo_unreserve(rdev->vram_scratch.robj); 1253 } 1254 radeon_bo_unref(&rdev->vram_scratch.robj); 1255 } 1256 1257 /* We doesn't check that the GPU really needs a reset we simply do the 1258 * reset, it's up to the caller to determine if the GPU needs one. We 1259 * might add an helper function to check that. 1260 */ 1261 static int r600_gpu_soft_reset(struct radeon_device *rdev) 1262 { 1263 struct rv515_mc_save save; 1264 u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) | 1265 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) | 1266 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) | 1267 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) | 1268 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) | 1269 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) | 1270 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) | 1271 S_008010_GUI_ACTIVE(1); 1272 u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) | 1273 S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) | 1274 S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) | 1275 S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) | 1276 S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) | 1277 S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) | 1278 S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) | 1279 S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1); 1280 u32 tmp; 1281 1282 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE)) 1283 return 0; 1284 1285 dev_info(rdev->dev, "GPU softreset \n"); 1286 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n", 1287 RREG32(R_008010_GRBM_STATUS)); 1288 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n", 1289 RREG32(R_008014_GRBM_STATUS2)); 1290 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n", 1291 RREG32(R_000E50_SRBM_STATUS)); 1292 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n", 1293 RREG32(CP_STALLED_STAT1)); 1294 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n", 1295 RREG32(CP_STALLED_STAT2)); 1296 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n", 1297 RREG32(CP_BUSY_STAT)); 1298 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n", 1299 RREG32(CP_STAT)); 1300 rv515_mc_stop(rdev, &save); 1301 if (r600_mc_wait_for_idle(rdev)) { 1302 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1303 } 1304 /* Disable CP parsing/prefetching */ 1305 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); 1306 /* Check if any of the rendering block is busy and reset it */ 1307 if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) || 1308 (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) { 1309 tmp = S_008020_SOFT_RESET_CR(1) | 1310 S_008020_SOFT_RESET_DB(1) | 1311 S_008020_SOFT_RESET_CB(1) | 1312 S_008020_SOFT_RESET_PA(1) | 1313 S_008020_SOFT_RESET_SC(1) | 1314 S_008020_SOFT_RESET_SMX(1) | 1315 S_008020_SOFT_RESET_SPI(1) | 1316 S_008020_SOFT_RESET_SX(1) | 1317 S_008020_SOFT_RESET_SH(1) | 1318 S_008020_SOFT_RESET_TC(1) | 1319 S_008020_SOFT_RESET_TA(1) | 1320 S_008020_SOFT_RESET_VC(1) | 1321 S_008020_SOFT_RESET_VGT(1); 1322 dev_info(rdev->dev, " R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp); 1323 WREG32(R_008020_GRBM_SOFT_RESET, tmp); 1324 RREG32(R_008020_GRBM_SOFT_RESET); 1325 mdelay(15); 1326 WREG32(R_008020_GRBM_SOFT_RESET, 0); 1327 } 1328 /* Reset CP (we always reset CP) */ 1329 tmp = S_008020_SOFT_RESET_CP(1); 1330 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp); 1331 WREG32(R_008020_GRBM_SOFT_RESET, tmp); 1332 RREG32(R_008020_GRBM_SOFT_RESET); 1333 mdelay(15); 1334 WREG32(R_008020_GRBM_SOFT_RESET, 0); 1335 /* Wait a little for things to settle down */ 1336 mdelay(1); 1337 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n", 1338 RREG32(R_008010_GRBM_STATUS)); 1339 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n", 1340 RREG32(R_008014_GRBM_STATUS2)); 1341 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n", 1342 RREG32(R_000E50_SRBM_STATUS)); 1343 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n", 1344 RREG32(CP_STALLED_STAT1)); 1345 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n", 1346 RREG32(CP_STALLED_STAT2)); 1347 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n", 1348 RREG32(CP_BUSY_STAT)); 1349 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n", 1350 RREG32(CP_STAT)); 1351 rv515_mc_resume(rdev, &save); 1352 return 0; 1353 } 1354 1355 bool r600_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 1356 { 1357 u32 srbm_status; 1358 u32 grbm_status; 1359 u32 grbm_status2; 1360 1361 srbm_status = RREG32(R_000E50_SRBM_STATUS); 1362 grbm_status = RREG32(R_008010_GRBM_STATUS); 1363 grbm_status2 = RREG32(R_008014_GRBM_STATUS2); 1364 if (!G_008010_GUI_ACTIVE(grbm_status)) { 1365 radeon_ring_lockup_update(ring); 1366 return false; 1367 } 1368 /* force CP activities */ 1369 radeon_ring_force_activity(rdev, ring); 1370 return radeon_ring_test_lockup(rdev, ring); 1371 } 1372 1373 /** 1374 * r600_dma_is_lockup - Check if the DMA engine is locked up 1375 * 1376 * @rdev: radeon_device pointer 1377 * @ring: radeon_ring structure holding ring information 1378 * 1379 * Check if the async DMA engine is locked up (r6xx-evergreen). 1380 * Returns true if the engine appears to be locked up, false if not. 1381 */ 1382 bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 1383 { 1384 u32 dma_status_reg; 1385 1386 dma_status_reg = RREG32(DMA_STATUS_REG); 1387 if (dma_status_reg & DMA_IDLE) { 1388 radeon_ring_lockup_update(ring); 1389 return false; 1390 } 1391 /* force ring activities */ 1392 radeon_ring_force_activity(rdev, ring); 1393 return radeon_ring_test_lockup(rdev, ring); 1394 } 1395 1396 int r600_asic_reset(struct radeon_device *rdev) 1397 { 1398 return r600_gpu_soft_reset(rdev); 1399 } 1400 1401 u32 r6xx_remap_render_backend(struct radeon_device *rdev, 1402 u32 tiling_pipe_num, 1403 u32 max_rb_num, 1404 u32 total_max_rb_num, 1405 u32 disabled_rb_mask) 1406 { 1407 u32 rendering_pipe_num, rb_num_width, req_rb_num; 1408 u32 pipe_rb_ratio, pipe_rb_remain; 1409 u32 data = 0, mask = 1 << (max_rb_num - 1); 1410 unsigned i, j; 1411 1412 /* mask out the RBs that don't exist on that asic */ 1413 disabled_rb_mask |= (0xff << max_rb_num) & 0xff; 1414 1415 rendering_pipe_num = 1 << tiling_pipe_num; 1416 req_rb_num = total_max_rb_num - r600_count_pipe_bits(disabled_rb_mask); 1417 BUG_ON(rendering_pipe_num < req_rb_num); 1418 1419 pipe_rb_ratio = rendering_pipe_num / req_rb_num; 1420 pipe_rb_remain = rendering_pipe_num - pipe_rb_ratio * req_rb_num; 1421 1422 if (rdev->family <= CHIP_RV740) { 1423 /* r6xx/r7xx */ 1424 rb_num_width = 2; 1425 } else { 1426 /* eg+ */ 1427 rb_num_width = 4; 1428 } 1429 1430 for (i = 0; i < max_rb_num; i++) { 1431 if (!(mask & disabled_rb_mask)) { 1432 for (j = 0; j < pipe_rb_ratio; j++) { 1433 data <<= rb_num_width; 1434 data |= max_rb_num - i - 1; 1435 } 1436 if (pipe_rb_remain) { 1437 data <<= rb_num_width; 1438 data |= max_rb_num - i - 1; 1439 pipe_rb_remain--; 1440 } 1441 } 1442 mask >>= 1; 1443 } 1444 1445 return data; 1446 } 1447 1448 int r600_count_pipe_bits(uint32_t val) 1449 { 1450 return hweight32(val); 1451 } 1452 1453 static void r600_gpu_init(struct radeon_device *rdev) 1454 { 1455 u32 tiling_config; 1456 u32 ramcfg; 1457 u32 cc_rb_backend_disable; 1458 u32 cc_gc_shader_pipe_config; 1459 u32 tmp; 1460 int i, j; 1461 u32 sq_config; 1462 u32 sq_gpr_resource_mgmt_1 = 0; 1463 u32 sq_gpr_resource_mgmt_2 = 0; 1464 u32 sq_thread_resource_mgmt = 0; 1465 u32 sq_stack_resource_mgmt_1 = 0; 1466 u32 sq_stack_resource_mgmt_2 = 0; 1467 u32 disabled_rb_mask; 1468 1469 rdev->config.r600.tiling_group_size = 256; 1470 switch (rdev->family) { 1471 case CHIP_R600: 1472 rdev->config.r600.max_pipes = 4; 1473 rdev->config.r600.max_tile_pipes = 8; 1474 rdev->config.r600.max_simds = 4; 1475 rdev->config.r600.max_backends = 4; 1476 rdev->config.r600.max_gprs = 256; 1477 rdev->config.r600.max_threads = 192; 1478 rdev->config.r600.max_stack_entries = 256; 1479 rdev->config.r600.max_hw_contexts = 8; 1480 rdev->config.r600.max_gs_threads = 16; 1481 rdev->config.r600.sx_max_export_size = 128; 1482 rdev->config.r600.sx_max_export_pos_size = 16; 1483 rdev->config.r600.sx_max_export_smx_size = 128; 1484 rdev->config.r600.sq_num_cf_insts = 2; 1485 break; 1486 case CHIP_RV630: 1487 case CHIP_RV635: 1488 rdev->config.r600.max_pipes = 2; 1489 rdev->config.r600.max_tile_pipes = 2; 1490 rdev->config.r600.max_simds = 3; 1491 rdev->config.r600.max_backends = 1; 1492 rdev->config.r600.max_gprs = 128; 1493 rdev->config.r600.max_threads = 192; 1494 rdev->config.r600.max_stack_entries = 128; 1495 rdev->config.r600.max_hw_contexts = 8; 1496 rdev->config.r600.max_gs_threads = 4; 1497 rdev->config.r600.sx_max_export_size = 128; 1498 rdev->config.r600.sx_max_export_pos_size = 16; 1499 rdev->config.r600.sx_max_export_smx_size = 128; 1500 rdev->config.r600.sq_num_cf_insts = 2; 1501 break; 1502 case CHIP_RV610: 1503 case CHIP_RV620: 1504 case CHIP_RS780: 1505 case CHIP_RS880: 1506 rdev->config.r600.max_pipes = 1; 1507 rdev->config.r600.max_tile_pipes = 1; 1508 rdev->config.r600.max_simds = 2; 1509 rdev->config.r600.max_backends = 1; 1510 rdev->config.r600.max_gprs = 128; 1511 rdev->config.r600.max_threads = 192; 1512 rdev->config.r600.max_stack_entries = 128; 1513 rdev->config.r600.max_hw_contexts = 4; 1514 rdev->config.r600.max_gs_threads = 4; 1515 rdev->config.r600.sx_max_export_size = 128; 1516 rdev->config.r600.sx_max_export_pos_size = 16; 1517 rdev->config.r600.sx_max_export_smx_size = 128; 1518 rdev->config.r600.sq_num_cf_insts = 1; 1519 break; 1520 case CHIP_RV670: 1521 rdev->config.r600.max_pipes = 4; 1522 rdev->config.r600.max_tile_pipes = 4; 1523 rdev->config.r600.max_simds = 4; 1524 rdev->config.r600.max_backends = 4; 1525 rdev->config.r600.max_gprs = 192; 1526 rdev->config.r600.max_threads = 192; 1527 rdev->config.r600.max_stack_entries = 256; 1528 rdev->config.r600.max_hw_contexts = 8; 1529 rdev->config.r600.max_gs_threads = 16; 1530 rdev->config.r600.sx_max_export_size = 128; 1531 rdev->config.r600.sx_max_export_pos_size = 16; 1532 rdev->config.r600.sx_max_export_smx_size = 128; 1533 rdev->config.r600.sq_num_cf_insts = 2; 1534 break; 1535 default: 1536 break; 1537 } 1538 1539 /* Initialize HDP */ 1540 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 1541 WREG32((0x2c14 + j), 0x00000000); 1542 WREG32((0x2c18 + j), 0x00000000); 1543 WREG32((0x2c1c + j), 0x00000000); 1544 WREG32((0x2c20 + j), 0x00000000); 1545 WREG32((0x2c24 + j), 0x00000000); 1546 } 1547 1548 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); 1549 1550 /* Setup tiling */ 1551 tiling_config = 0; 1552 ramcfg = RREG32(RAMCFG); 1553 switch (rdev->config.r600.max_tile_pipes) { 1554 case 1: 1555 tiling_config |= PIPE_TILING(0); 1556 break; 1557 case 2: 1558 tiling_config |= PIPE_TILING(1); 1559 break; 1560 case 4: 1561 tiling_config |= PIPE_TILING(2); 1562 break; 1563 case 8: 1564 tiling_config |= PIPE_TILING(3); 1565 break; 1566 default: 1567 break; 1568 } 1569 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes; 1570 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); 1571 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); 1572 tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT); 1573 1574 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT; 1575 if (tmp > 3) { 1576 tiling_config |= ROW_TILING(3); 1577 tiling_config |= SAMPLE_SPLIT(3); 1578 } else { 1579 tiling_config |= ROW_TILING(tmp); 1580 tiling_config |= SAMPLE_SPLIT(tmp); 1581 } 1582 tiling_config |= BANK_SWAPS(1); 1583 1584 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000; 1585 tmp = R6XX_MAX_BACKENDS - 1586 r600_count_pipe_bits((cc_rb_backend_disable >> 16) & R6XX_MAX_BACKENDS_MASK); 1587 if (tmp < rdev->config.r600.max_backends) { 1588 rdev->config.r600.max_backends = tmp; 1589 } 1590 1591 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0x00ffff00; 1592 tmp = R6XX_MAX_PIPES - 1593 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 8) & R6XX_MAX_PIPES_MASK); 1594 if (tmp < rdev->config.r600.max_pipes) { 1595 rdev->config.r600.max_pipes = tmp; 1596 } 1597 tmp = R6XX_MAX_SIMDS - 1598 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R6XX_MAX_SIMDS_MASK); 1599 if (tmp < rdev->config.r600.max_simds) { 1600 rdev->config.r600.max_simds = tmp; 1601 } 1602 1603 disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R6XX_MAX_BACKENDS_MASK; 1604 tmp = (tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT; 1605 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends, 1606 R6XX_MAX_BACKENDS, disabled_rb_mask); 1607 tiling_config |= tmp << 16; 1608 rdev->config.r600.backend_map = tmp; 1609 1610 rdev->config.r600.tile_config = tiling_config; 1611 WREG32(GB_TILING_CONFIG, tiling_config); 1612 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff); 1613 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff); 1614 WREG32(DMA_TILING_CONFIG, tiling_config & 0xffff); 1615 1616 tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8); 1617 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK); 1618 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK); 1619 1620 /* Setup some CP states */ 1621 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b))); 1622 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40))); 1623 1624 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT | 1625 SYNC_WALKER | SYNC_ALIGNER)); 1626 /* Setup various GPU states */ 1627 if (rdev->family == CHIP_RV670) 1628 WREG32(ARB_GDEC_RD_CNTL, 0x00000021); 1629 1630 tmp = RREG32(SX_DEBUG_1); 1631 tmp |= SMX_EVENT_RELEASE; 1632 if ((rdev->family > CHIP_R600)) 1633 tmp |= ENABLE_NEW_SMX_ADDRESS; 1634 WREG32(SX_DEBUG_1, tmp); 1635 1636 if (((rdev->family) == CHIP_R600) || 1637 ((rdev->family) == CHIP_RV630) || 1638 ((rdev->family) == CHIP_RV610) || 1639 ((rdev->family) == CHIP_RV620) || 1640 ((rdev->family) == CHIP_RS780) || 1641 ((rdev->family) == CHIP_RS880)) { 1642 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE); 1643 } else { 1644 WREG32(DB_DEBUG, 0); 1645 } 1646 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) | 1647 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4))); 1648 1649 WREG32(PA_SC_MULTI_CHIP_CNTL, 0); 1650 WREG32(VGT_NUM_INSTANCES, 0); 1651 1652 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0)); 1653 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0)); 1654 1655 tmp = RREG32(SQ_MS_FIFO_SIZES); 1656 if (((rdev->family) == CHIP_RV610) || 1657 ((rdev->family) == CHIP_RV620) || 1658 ((rdev->family) == CHIP_RS780) || 1659 ((rdev->family) == CHIP_RS880)) { 1660 tmp = (CACHE_FIFO_SIZE(0xa) | 1661 FETCH_FIFO_HIWATER(0xa) | 1662 DONE_FIFO_HIWATER(0xe0) | 1663 ALU_UPDATE_FIFO_HIWATER(0x8)); 1664 } else if (((rdev->family) == CHIP_R600) || 1665 ((rdev->family) == CHIP_RV630)) { 1666 tmp &= ~DONE_FIFO_HIWATER(0xff); 1667 tmp |= DONE_FIFO_HIWATER(0x4); 1668 } 1669 WREG32(SQ_MS_FIFO_SIZES, tmp); 1670 1671 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT 1672 * should be adjusted as needed by the 2D/3D drivers. This just sets default values 1673 */ 1674 sq_config = RREG32(SQ_CONFIG); 1675 sq_config &= ~(PS_PRIO(3) | 1676 VS_PRIO(3) | 1677 GS_PRIO(3) | 1678 ES_PRIO(3)); 1679 sq_config |= (DX9_CONSTS | 1680 VC_ENABLE | 1681 PS_PRIO(0) | 1682 VS_PRIO(1) | 1683 GS_PRIO(2) | 1684 ES_PRIO(3)); 1685 1686 if ((rdev->family) == CHIP_R600) { 1687 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) | 1688 NUM_VS_GPRS(124) | 1689 NUM_CLAUSE_TEMP_GPRS(4)); 1690 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) | 1691 NUM_ES_GPRS(0)); 1692 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) | 1693 NUM_VS_THREADS(48) | 1694 NUM_GS_THREADS(4) | 1695 NUM_ES_THREADS(4)); 1696 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) | 1697 NUM_VS_STACK_ENTRIES(128)); 1698 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) | 1699 NUM_ES_STACK_ENTRIES(0)); 1700 } else if (((rdev->family) == CHIP_RV610) || 1701 ((rdev->family) == CHIP_RV620) || 1702 ((rdev->family) == CHIP_RS780) || 1703 ((rdev->family) == CHIP_RS880)) { 1704 /* no vertex cache */ 1705 sq_config &= ~VC_ENABLE; 1706 1707 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | 1708 NUM_VS_GPRS(44) | 1709 NUM_CLAUSE_TEMP_GPRS(2)); 1710 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | 1711 NUM_ES_GPRS(17)); 1712 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | 1713 NUM_VS_THREADS(78) | 1714 NUM_GS_THREADS(4) | 1715 NUM_ES_THREADS(31)); 1716 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | 1717 NUM_VS_STACK_ENTRIES(40)); 1718 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | 1719 NUM_ES_STACK_ENTRIES(16)); 1720 } else if (((rdev->family) == CHIP_RV630) || 1721 ((rdev->family) == CHIP_RV635)) { 1722 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | 1723 NUM_VS_GPRS(44) | 1724 NUM_CLAUSE_TEMP_GPRS(2)); 1725 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) | 1726 NUM_ES_GPRS(18)); 1727 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | 1728 NUM_VS_THREADS(78) | 1729 NUM_GS_THREADS(4) | 1730 NUM_ES_THREADS(31)); 1731 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | 1732 NUM_VS_STACK_ENTRIES(40)); 1733 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | 1734 NUM_ES_STACK_ENTRIES(16)); 1735 } else if ((rdev->family) == CHIP_RV670) { 1736 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | 1737 NUM_VS_GPRS(44) | 1738 NUM_CLAUSE_TEMP_GPRS(2)); 1739 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | 1740 NUM_ES_GPRS(17)); 1741 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | 1742 NUM_VS_THREADS(78) | 1743 NUM_GS_THREADS(4) | 1744 NUM_ES_THREADS(31)); 1745 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) | 1746 NUM_VS_STACK_ENTRIES(64)); 1747 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) | 1748 NUM_ES_STACK_ENTRIES(64)); 1749 } 1750 1751 WREG32(SQ_CONFIG, sq_config); 1752 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1); 1753 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2); 1754 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); 1755 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1); 1756 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2); 1757 1758 if (((rdev->family) == CHIP_RV610) || 1759 ((rdev->family) == CHIP_RV620) || 1760 ((rdev->family) == CHIP_RS780) || 1761 ((rdev->family) == CHIP_RS880)) { 1762 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY)); 1763 } else { 1764 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC)); 1765 } 1766 1767 /* More default values. 2D/3D driver should adjust as needed */ 1768 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) | 1769 S1_X(0x4) | S1_Y(0xc))); 1770 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) | 1771 S1_X(0x2) | S1_Y(0x2) | 1772 S2_X(0xa) | S2_Y(0x6) | 1773 S3_X(0x6) | S3_Y(0xa))); 1774 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) | 1775 S1_X(0x4) | S1_Y(0xc) | 1776 S2_X(0x1) | S2_Y(0x6) | 1777 S3_X(0xa) | S3_Y(0xe))); 1778 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) | 1779 S5_X(0x0) | S5_Y(0x0) | 1780 S6_X(0xb) | S6_Y(0x4) | 1781 S7_X(0x7) | S7_Y(0x8))); 1782 1783 WREG32(VGT_STRMOUT_EN, 0); 1784 tmp = rdev->config.r600.max_pipes * 16; 1785 switch (rdev->family) { 1786 case CHIP_RV610: 1787 case CHIP_RV620: 1788 case CHIP_RS780: 1789 case CHIP_RS880: 1790 tmp += 32; 1791 break; 1792 case CHIP_RV670: 1793 tmp += 128; 1794 break; 1795 default: 1796 break; 1797 } 1798 if (tmp > 256) { 1799 tmp = 256; 1800 } 1801 WREG32(VGT_ES_PER_GS, 128); 1802 WREG32(VGT_GS_PER_ES, tmp); 1803 WREG32(VGT_GS_PER_VS, 2); 1804 WREG32(VGT_GS_VERTEX_REUSE, 16); 1805 1806 /* more default values. 2D/3D driver should adjust as needed */ 1807 WREG32(PA_SC_LINE_STIPPLE_STATE, 0); 1808 WREG32(VGT_STRMOUT_EN, 0); 1809 WREG32(SX_MISC, 0); 1810 WREG32(PA_SC_MODE_CNTL, 0); 1811 WREG32(PA_SC_AA_CONFIG, 0); 1812 WREG32(PA_SC_LINE_STIPPLE, 0); 1813 WREG32(SPI_INPUT_Z, 0); 1814 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2)); 1815 WREG32(CB_COLOR7_FRAG, 0); 1816 1817 /* Clear render buffer base addresses */ 1818 WREG32(CB_COLOR0_BASE, 0); 1819 WREG32(CB_COLOR1_BASE, 0); 1820 WREG32(CB_COLOR2_BASE, 0); 1821 WREG32(CB_COLOR3_BASE, 0); 1822 WREG32(CB_COLOR4_BASE, 0); 1823 WREG32(CB_COLOR5_BASE, 0); 1824 WREG32(CB_COLOR6_BASE, 0); 1825 WREG32(CB_COLOR7_BASE, 0); 1826 WREG32(CB_COLOR7_FRAG, 0); 1827 1828 switch (rdev->family) { 1829 case CHIP_RV610: 1830 case CHIP_RV620: 1831 case CHIP_RS780: 1832 case CHIP_RS880: 1833 tmp = TC_L2_SIZE(8); 1834 break; 1835 case CHIP_RV630: 1836 case CHIP_RV635: 1837 tmp = TC_L2_SIZE(4); 1838 break; 1839 case CHIP_R600: 1840 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT; 1841 break; 1842 default: 1843 tmp = TC_L2_SIZE(0); 1844 break; 1845 } 1846 WREG32(TC_CNTL, tmp); 1847 1848 tmp = RREG32(HDP_HOST_PATH_CNTL); 1849 WREG32(HDP_HOST_PATH_CNTL, tmp); 1850 1851 tmp = RREG32(ARB_POP); 1852 tmp |= ENABLE_TC128; 1853 WREG32(ARB_POP, tmp); 1854 1855 WREG32(PA_SC_MULTI_CHIP_CNTL, 0); 1856 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | 1857 NUM_CLIP_SEQ(3))); 1858 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095)); 1859 WREG32(VC_ENHANCE, 0); 1860 } 1861 1862 1863 /* 1864 * Indirect registers accessor 1865 */ 1866 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg) 1867 { 1868 u32 r; 1869 1870 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); 1871 (void)RREG32(PCIE_PORT_INDEX); 1872 r = RREG32(PCIE_PORT_DATA); 1873 return r; 1874 } 1875 1876 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v) 1877 { 1878 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); 1879 (void)RREG32(PCIE_PORT_INDEX); 1880 WREG32(PCIE_PORT_DATA, (v)); 1881 (void)RREG32(PCIE_PORT_DATA); 1882 } 1883 1884 /* 1885 * CP & Ring 1886 */ 1887 void r600_cp_stop(struct radeon_device *rdev) 1888 { 1889 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 1890 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); 1891 WREG32(SCRATCH_UMSK, 0); 1892 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 1893 } 1894 1895 int r600_init_microcode(struct radeon_device *rdev) 1896 { 1897 struct platform_device *pdev; 1898 const char *chip_name; 1899 const char *rlc_chip_name; 1900 size_t pfp_req_size, me_req_size, rlc_req_size; 1901 char fw_name[30]; 1902 int err; 1903 1904 DRM_DEBUG("\n"); 1905 1906 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0); 1907 err = IS_ERR(pdev); 1908 if (err) { 1909 printk(KERN_ERR "radeon_cp: Failed to register firmware\n"); 1910 return -EINVAL; 1911 } 1912 1913 switch (rdev->family) { 1914 case CHIP_R600: 1915 chip_name = "R600"; 1916 rlc_chip_name = "R600"; 1917 break; 1918 case CHIP_RV610: 1919 chip_name = "RV610"; 1920 rlc_chip_name = "R600"; 1921 break; 1922 case CHIP_RV630: 1923 chip_name = "RV630"; 1924 rlc_chip_name = "R600"; 1925 break; 1926 case CHIP_RV620: 1927 chip_name = "RV620"; 1928 rlc_chip_name = "R600"; 1929 break; 1930 case CHIP_RV635: 1931 chip_name = "RV635"; 1932 rlc_chip_name = "R600"; 1933 break; 1934 case CHIP_RV670: 1935 chip_name = "RV670"; 1936 rlc_chip_name = "R600"; 1937 break; 1938 case CHIP_RS780: 1939 case CHIP_RS880: 1940 chip_name = "RS780"; 1941 rlc_chip_name = "R600"; 1942 break; 1943 case CHIP_RV770: 1944 chip_name = "RV770"; 1945 rlc_chip_name = "R700"; 1946 break; 1947 case CHIP_RV730: 1948 case CHIP_RV740: 1949 chip_name = "RV730"; 1950 rlc_chip_name = "R700"; 1951 break; 1952 case CHIP_RV710: 1953 chip_name = "RV710"; 1954 rlc_chip_name = "R700"; 1955 break; 1956 case CHIP_CEDAR: 1957 chip_name = "CEDAR"; 1958 rlc_chip_name = "CEDAR"; 1959 break; 1960 case CHIP_REDWOOD: 1961 chip_name = "REDWOOD"; 1962 rlc_chip_name = "REDWOOD"; 1963 break; 1964 case CHIP_JUNIPER: 1965 chip_name = "JUNIPER"; 1966 rlc_chip_name = "JUNIPER"; 1967 break; 1968 case CHIP_CYPRESS: 1969 case CHIP_HEMLOCK: 1970 chip_name = "CYPRESS"; 1971 rlc_chip_name = "CYPRESS"; 1972 break; 1973 case CHIP_PALM: 1974 chip_name = "PALM"; 1975 rlc_chip_name = "SUMO"; 1976 break; 1977 case CHIP_SUMO: 1978 chip_name = "SUMO"; 1979 rlc_chip_name = "SUMO"; 1980 break; 1981 case CHIP_SUMO2: 1982 chip_name = "SUMO2"; 1983 rlc_chip_name = "SUMO"; 1984 break; 1985 default: BUG(); 1986 } 1987 1988 if (rdev->family >= CHIP_CEDAR) { 1989 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4; 1990 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4; 1991 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4; 1992 } else if (rdev->family >= CHIP_RV770) { 1993 pfp_req_size = R700_PFP_UCODE_SIZE * 4; 1994 me_req_size = R700_PM4_UCODE_SIZE * 4; 1995 rlc_req_size = R700_RLC_UCODE_SIZE * 4; 1996 } else { 1997 pfp_req_size = PFP_UCODE_SIZE * 4; 1998 me_req_size = PM4_UCODE_SIZE * 12; 1999 rlc_req_size = RLC_UCODE_SIZE * 4; 2000 } 2001 2002 DRM_INFO("Loading %s Microcode\n", chip_name); 2003 2004 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name); 2005 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev); 2006 if (err) 2007 goto out; 2008 if (rdev->pfp_fw->size != pfp_req_size) { 2009 printk(KERN_ERR 2010 "r600_cp: Bogus length %zu in firmware \"%s\"\n", 2011 rdev->pfp_fw->size, fw_name); 2012 err = -EINVAL; 2013 goto out; 2014 } 2015 2016 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name); 2017 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev); 2018 if (err) 2019 goto out; 2020 if (rdev->me_fw->size != me_req_size) { 2021 printk(KERN_ERR 2022 "r600_cp: Bogus length %zu in firmware \"%s\"\n", 2023 rdev->me_fw->size, fw_name); 2024 err = -EINVAL; 2025 } 2026 2027 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name); 2028 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev); 2029 if (err) 2030 goto out; 2031 if (rdev->rlc_fw->size != rlc_req_size) { 2032 printk(KERN_ERR 2033 "r600_rlc: Bogus length %zu in firmware \"%s\"\n", 2034 rdev->rlc_fw->size, fw_name); 2035 err = -EINVAL; 2036 } 2037 2038 out: 2039 platform_device_unregister(pdev); 2040 2041 if (err) { 2042 if (err != -EINVAL) 2043 printk(KERN_ERR 2044 "r600_cp: Failed to load firmware \"%s\"\n", 2045 fw_name); 2046 release_firmware(rdev->pfp_fw); 2047 rdev->pfp_fw = NULL; 2048 release_firmware(rdev->me_fw); 2049 rdev->me_fw = NULL; 2050 release_firmware(rdev->rlc_fw); 2051 rdev->rlc_fw = NULL; 2052 } 2053 return err; 2054 } 2055 2056 static int r600_cp_load_microcode(struct radeon_device *rdev) 2057 { 2058 const __be32 *fw_data; 2059 int i; 2060 2061 if (!rdev->me_fw || !rdev->pfp_fw) 2062 return -EINVAL; 2063 2064 r600_cp_stop(rdev); 2065 2066 WREG32(CP_RB_CNTL, 2067 #ifdef __BIG_ENDIAN 2068 BUF_SWAP_32BIT | 2069 #endif 2070 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); 2071 2072 /* Reset cp */ 2073 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); 2074 RREG32(GRBM_SOFT_RESET); 2075 mdelay(15); 2076 WREG32(GRBM_SOFT_RESET, 0); 2077 2078 WREG32(CP_ME_RAM_WADDR, 0); 2079 2080 fw_data = (const __be32 *)rdev->me_fw->data; 2081 WREG32(CP_ME_RAM_WADDR, 0); 2082 for (i = 0; i < PM4_UCODE_SIZE * 3; i++) 2083 WREG32(CP_ME_RAM_DATA, 2084 be32_to_cpup(fw_data++)); 2085 2086 fw_data = (const __be32 *)rdev->pfp_fw->data; 2087 WREG32(CP_PFP_UCODE_ADDR, 0); 2088 for (i = 0; i < PFP_UCODE_SIZE; i++) 2089 WREG32(CP_PFP_UCODE_DATA, 2090 be32_to_cpup(fw_data++)); 2091 2092 WREG32(CP_PFP_UCODE_ADDR, 0); 2093 WREG32(CP_ME_RAM_WADDR, 0); 2094 WREG32(CP_ME_RAM_RADDR, 0); 2095 return 0; 2096 } 2097 2098 int r600_cp_start(struct radeon_device *rdev) 2099 { 2100 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2101 int r; 2102 uint32_t cp_me; 2103 2104 r = radeon_ring_lock(rdev, ring, 7); 2105 if (r) { 2106 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 2107 return r; 2108 } 2109 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); 2110 radeon_ring_write(ring, 0x1); 2111 if (rdev->family >= CHIP_RV770) { 2112 radeon_ring_write(ring, 0x0); 2113 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1); 2114 } else { 2115 radeon_ring_write(ring, 0x3); 2116 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1); 2117 } 2118 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); 2119 radeon_ring_write(ring, 0); 2120 radeon_ring_write(ring, 0); 2121 radeon_ring_unlock_commit(rdev, ring); 2122 2123 cp_me = 0xff; 2124 WREG32(R_0086D8_CP_ME_CNTL, cp_me); 2125 return 0; 2126 } 2127 2128 int r600_cp_resume(struct radeon_device *rdev) 2129 { 2130 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2131 u32 tmp; 2132 u32 rb_bufsz; 2133 int r; 2134 2135 /* Reset cp */ 2136 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); 2137 RREG32(GRBM_SOFT_RESET); 2138 mdelay(15); 2139 WREG32(GRBM_SOFT_RESET, 0); 2140 2141 /* Set ring buffer size */ 2142 rb_bufsz = drm_order(ring->ring_size / 8); 2143 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2144 #ifdef __BIG_ENDIAN 2145 tmp |= BUF_SWAP_32BIT; 2146 #endif 2147 WREG32(CP_RB_CNTL, tmp); 2148 WREG32(CP_SEM_WAIT_TIMER, 0x0); 2149 2150 /* Set the write pointer delay */ 2151 WREG32(CP_RB_WPTR_DELAY, 0); 2152 2153 /* Initialize the ring buffer's read and write pointers */ 2154 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); 2155 WREG32(CP_RB_RPTR_WR, 0); 2156 ring->wptr = 0; 2157 WREG32(CP_RB_WPTR, ring->wptr); 2158 2159 /* set the wb address whether it's enabled or not */ 2160 WREG32(CP_RB_RPTR_ADDR, 2161 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC)); 2162 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); 2163 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); 2164 2165 if (rdev->wb.enabled) 2166 WREG32(SCRATCH_UMSK, 0xff); 2167 else { 2168 tmp |= RB_NO_UPDATE; 2169 WREG32(SCRATCH_UMSK, 0); 2170 } 2171 2172 mdelay(1); 2173 WREG32(CP_RB_CNTL, tmp); 2174 2175 WREG32(CP_RB_BASE, ring->gpu_addr >> 8); 2176 WREG32(CP_DEBUG, (1 << 27) | (1 << 28)); 2177 2178 ring->rptr = RREG32(CP_RB_RPTR); 2179 2180 r600_cp_start(rdev); 2181 ring->ready = true; 2182 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring); 2183 if (r) { 2184 ring->ready = false; 2185 return r; 2186 } 2187 return 0; 2188 } 2189 2190 void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size) 2191 { 2192 u32 rb_bufsz; 2193 int r; 2194 2195 /* Align ring size */ 2196 rb_bufsz = drm_order(ring_size / 8); 2197 ring_size = (1 << (rb_bufsz + 1)) * 4; 2198 ring->ring_size = ring_size; 2199 ring->align_mask = 16 - 1; 2200 2201 if (radeon_ring_supports_scratch_reg(rdev, ring)) { 2202 r = radeon_scratch_get(rdev, &ring->rptr_save_reg); 2203 if (r) { 2204 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r); 2205 ring->rptr_save_reg = 0; 2206 } 2207 } 2208 } 2209 2210 void r600_cp_fini(struct radeon_device *rdev) 2211 { 2212 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2213 r600_cp_stop(rdev); 2214 radeon_ring_fini(rdev, ring); 2215 radeon_scratch_free(rdev, ring->rptr_save_reg); 2216 } 2217 2218 /* 2219 * DMA 2220 * Starting with R600, the GPU has an asynchronous 2221 * DMA engine. The programming model is very similar 2222 * to the 3D engine (ring buffer, IBs, etc.), but the 2223 * DMA controller has it's own packet format that is 2224 * different form the PM4 format used by the 3D engine. 2225 * It supports copying data, writing embedded data, 2226 * solid fills, and a number of other things. It also 2227 * has support for tiling/detiling of buffers. 2228 */ 2229 /** 2230 * r600_dma_stop - stop the async dma engine 2231 * 2232 * @rdev: radeon_device pointer 2233 * 2234 * Stop the async dma engine (r6xx-evergreen). 2235 */ 2236 void r600_dma_stop(struct radeon_device *rdev) 2237 { 2238 u32 rb_cntl = RREG32(DMA_RB_CNTL); 2239 2240 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 2241 2242 rb_cntl &= ~DMA_RB_ENABLE; 2243 WREG32(DMA_RB_CNTL, rb_cntl); 2244 2245 rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false; 2246 } 2247 2248 /** 2249 * r600_dma_resume - setup and start the async dma engine 2250 * 2251 * @rdev: radeon_device pointer 2252 * 2253 * Set up the DMA ring buffer and enable it. (r6xx-evergreen). 2254 * Returns 0 for success, error for failure. 2255 */ 2256 int r600_dma_resume(struct radeon_device *rdev) 2257 { 2258 struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; 2259 u32 rb_cntl, dma_cntl; 2260 u32 rb_bufsz; 2261 int r; 2262 2263 /* Reset dma */ 2264 if (rdev->family >= CHIP_RV770) 2265 WREG32(SRBM_SOFT_RESET, RV770_SOFT_RESET_DMA); 2266 else 2267 WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA); 2268 RREG32(SRBM_SOFT_RESET); 2269 udelay(50); 2270 WREG32(SRBM_SOFT_RESET, 0); 2271 2272 WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL, 0); 2273 WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL, 0); 2274 2275 /* Set ring buffer size in dwords */ 2276 rb_bufsz = drm_order(ring->ring_size / 4); 2277 rb_cntl = rb_bufsz << 1; 2278 #ifdef __BIG_ENDIAN 2279 rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE; 2280 #endif 2281 WREG32(DMA_RB_CNTL, rb_cntl); 2282 2283 /* Initialize the ring buffer's read and write pointers */ 2284 WREG32(DMA_RB_RPTR, 0); 2285 WREG32(DMA_RB_WPTR, 0); 2286 2287 /* set the wb address whether it's enabled or not */ 2288 WREG32(DMA_RB_RPTR_ADDR_HI, 2289 upper_32_bits(rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFF); 2290 WREG32(DMA_RB_RPTR_ADDR_LO, 2291 ((rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFFFFFFFC)); 2292 2293 if (rdev->wb.enabled) 2294 rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE; 2295 2296 WREG32(DMA_RB_BASE, ring->gpu_addr >> 8); 2297 2298 /* enable DMA IBs */ 2299 WREG32(DMA_IB_CNTL, DMA_IB_ENABLE); 2300 2301 dma_cntl = RREG32(DMA_CNTL); 2302 dma_cntl &= ~CTXEMPTY_INT_ENABLE; 2303 WREG32(DMA_CNTL, dma_cntl); 2304 2305 if (rdev->family >= CHIP_RV770) 2306 WREG32(DMA_MODE, 1); 2307 2308 ring->wptr = 0; 2309 WREG32(DMA_RB_WPTR, ring->wptr << 2); 2310 2311 ring->rptr = RREG32(DMA_RB_RPTR) >> 2; 2312 2313 WREG32(DMA_RB_CNTL, rb_cntl | DMA_RB_ENABLE); 2314 2315 ring->ready = true; 2316 2317 r = radeon_ring_test(rdev, R600_RING_TYPE_DMA_INDEX, ring); 2318 if (r) { 2319 ring->ready = false; 2320 return r; 2321 } 2322 2323 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); 2324 2325 return 0; 2326 } 2327 2328 /** 2329 * r600_dma_fini - tear down the async dma engine 2330 * 2331 * @rdev: radeon_device pointer 2332 * 2333 * Stop the async dma engine and free the ring (r6xx-evergreen). 2334 */ 2335 void r600_dma_fini(struct radeon_device *rdev) 2336 { 2337 r600_dma_stop(rdev); 2338 radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]); 2339 } 2340 2341 /* 2342 * GPU scratch registers helpers function. 2343 */ 2344 void r600_scratch_init(struct radeon_device *rdev) 2345 { 2346 int i; 2347 2348 rdev->scratch.num_reg = 7; 2349 rdev->scratch.reg_base = SCRATCH_REG0; 2350 for (i = 0; i < rdev->scratch.num_reg; i++) { 2351 rdev->scratch.free[i] = true; 2352 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); 2353 } 2354 } 2355 2356 int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) 2357 { 2358 uint32_t scratch; 2359 uint32_t tmp = 0; 2360 unsigned i; 2361 int r; 2362 2363 r = radeon_scratch_get(rdev, &scratch); 2364 if (r) { 2365 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); 2366 return r; 2367 } 2368 WREG32(scratch, 0xCAFEDEAD); 2369 r = radeon_ring_lock(rdev, ring, 3); 2370 if (r) { 2371 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring->idx, r); 2372 radeon_scratch_free(rdev, scratch); 2373 return r; 2374 } 2375 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2376 radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); 2377 radeon_ring_write(ring, 0xDEADBEEF); 2378 radeon_ring_unlock_commit(rdev, ring); 2379 for (i = 0; i < rdev->usec_timeout; i++) { 2380 tmp = RREG32(scratch); 2381 if (tmp == 0xDEADBEEF) 2382 break; 2383 DRM_UDELAY(1); 2384 } 2385 if (i < rdev->usec_timeout) { 2386 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); 2387 } else { 2388 DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n", 2389 ring->idx, scratch, tmp); 2390 r = -EINVAL; 2391 } 2392 radeon_scratch_free(rdev, scratch); 2393 return r; 2394 } 2395 2396 /** 2397 * r600_dma_ring_test - simple async dma engine test 2398 * 2399 * @rdev: radeon_device pointer 2400 * @ring: radeon_ring structure holding ring information 2401 * 2402 * Test the DMA engine by writing using it to write an 2403 * value to memory. (r6xx-SI). 2404 * Returns 0 for success, error for failure. 2405 */ 2406 int r600_dma_ring_test(struct radeon_device *rdev, 2407 struct radeon_ring *ring) 2408 { 2409 unsigned i; 2410 int r; 2411 void __iomem *ptr = (void *)rdev->vram_scratch.ptr; 2412 u32 tmp; 2413 2414 if (!ptr) { 2415 DRM_ERROR("invalid vram scratch pointer\n"); 2416 return -EINVAL; 2417 } 2418 2419 tmp = 0xCAFEDEAD; 2420 writel(tmp, ptr); 2421 2422 r = radeon_ring_lock(rdev, ring, 4); 2423 if (r) { 2424 DRM_ERROR("radeon: dma failed to lock ring %d (%d).\n", ring->idx, r); 2425 return r; 2426 } 2427 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1)); 2428 radeon_ring_write(ring, rdev->vram_scratch.gpu_addr & 0xfffffffc); 2429 radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff); 2430 radeon_ring_write(ring, 0xDEADBEEF); 2431 radeon_ring_unlock_commit(rdev, ring); 2432 2433 for (i = 0; i < rdev->usec_timeout; i++) { 2434 tmp = readl(ptr); 2435 if (tmp == 0xDEADBEEF) 2436 break; 2437 DRM_UDELAY(1); 2438 } 2439 2440 if (i < rdev->usec_timeout) { 2441 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); 2442 } else { 2443 DRM_ERROR("radeon: ring %d test failed (0x%08X)\n", 2444 ring->idx, tmp); 2445 r = -EINVAL; 2446 } 2447 return r; 2448 } 2449 2450 /* 2451 * CP fences/semaphores 2452 */ 2453 2454 void r600_fence_ring_emit(struct radeon_device *rdev, 2455 struct radeon_fence *fence) 2456 { 2457 struct radeon_ring *ring = &rdev->ring[fence->ring]; 2458 2459 if (rdev->wb.use_event) { 2460 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; 2461 /* flush read cache over gart */ 2462 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 2463 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | 2464 PACKET3_VC_ACTION_ENA | 2465 PACKET3_SH_ACTION_ENA); 2466 radeon_ring_write(ring, 0xFFFFFFFF); 2467 radeon_ring_write(ring, 0); 2468 radeon_ring_write(ring, 10); /* poll interval */ 2469 /* EVENT_WRITE_EOP - flush caches, send int */ 2470 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 2471 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5)); 2472 radeon_ring_write(ring, addr & 0xffffffff); 2473 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); 2474 radeon_ring_write(ring, fence->seq); 2475 radeon_ring_write(ring, 0); 2476 } else { 2477 /* flush read cache over gart */ 2478 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 2479 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | 2480 PACKET3_VC_ACTION_ENA | 2481 PACKET3_SH_ACTION_ENA); 2482 radeon_ring_write(ring, 0xFFFFFFFF); 2483 radeon_ring_write(ring, 0); 2484 radeon_ring_write(ring, 10); /* poll interval */ 2485 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); 2486 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0)); 2487 /* wait for 3D idle clean */ 2488 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2489 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 2490 radeon_ring_write(ring, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit); 2491 /* Emit fence sequence & fire IRQ */ 2492 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2493 radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); 2494 radeon_ring_write(ring, fence->seq); 2495 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */ 2496 radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0)); 2497 radeon_ring_write(ring, RB_INT_STAT); 2498 } 2499 } 2500 2501 void r600_semaphore_ring_emit(struct radeon_device *rdev, 2502 struct radeon_ring *ring, 2503 struct radeon_semaphore *semaphore, 2504 bool emit_wait) 2505 { 2506 uint64_t addr = semaphore->gpu_addr; 2507 unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL; 2508 2509 if (rdev->family < CHIP_CAYMAN) 2510 sel |= PACKET3_SEM_WAIT_ON_SIGNAL; 2511 2512 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); 2513 radeon_ring_write(ring, addr & 0xffffffff); 2514 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel); 2515 } 2516 2517 /* 2518 * DMA fences/semaphores 2519 */ 2520 2521 /** 2522 * r600_dma_fence_ring_emit - emit a fence on the DMA ring 2523 * 2524 * @rdev: radeon_device pointer 2525 * @fence: radeon fence object 2526 * 2527 * Add a DMA fence packet to the ring to write 2528 * the fence seq number and DMA trap packet to generate 2529 * an interrupt if needed (r6xx-r7xx). 2530 */ 2531 void r600_dma_fence_ring_emit(struct radeon_device *rdev, 2532 struct radeon_fence *fence) 2533 { 2534 struct radeon_ring *ring = &rdev->ring[fence->ring]; 2535 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; 2536 2537 /* write the fence */ 2538 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0)); 2539 radeon_ring_write(ring, addr & 0xfffffffc); 2540 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff)); 2541 radeon_ring_write(ring, lower_32_bits(fence->seq)); 2542 /* generate an interrupt */ 2543 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0, 0)); 2544 } 2545 2546 /** 2547 * r600_dma_semaphore_ring_emit - emit a semaphore on the dma ring 2548 * 2549 * @rdev: radeon_device pointer 2550 * @ring: radeon_ring structure holding ring information 2551 * @semaphore: radeon semaphore object 2552 * @emit_wait: wait or signal semaphore 2553 * 2554 * Add a DMA semaphore packet to the ring wait on or signal 2555 * other rings (r6xx-SI). 2556 */ 2557 void r600_dma_semaphore_ring_emit(struct radeon_device *rdev, 2558 struct radeon_ring *ring, 2559 struct radeon_semaphore *semaphore, 2560 bool emit_wait) 2561 { 2562 u64 addr = semaphore->gpu_addr; 2563 u32 s = emit_wait ? 0 : 1; 2564 2565 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SEMAPHORE, 0, s, 0)); 2566 radeon_ring_write(ring, addr & 0xfffffffc); 2567 radeon_ring_write(ring, upper_32_bits(addr) & 0xff); 2568 } 2569 2570 int r600_copy_blit(struct radeon_device *rdev, 2571 uint64_t src_offset, 2572 uint64_t dst_offset, 2573 unsigned num_gpu_pages, 2574 struct radeon_fence **fence) 2575 { 2576 struct radeon_semaphore *sem = NULL; 2577 struct radeon_sa_bo *vb = NULL; 2578 int r; 2579 2580 r = r600_blit_prepare_copy(rdev, num_gpu_pages, fence, &vb, &sem); 2581 if (r) { 2582 return r; 2583 } 2584 r600_kms_blit_copy(rdev, src_offset, dst_offset, num_gpu_pages, vb); 2585 r600_blit_done_copy(rdev, fence, vb, sem); 2586 return 0; 2587 } 2588 2589 /** 2590 * r600_copy_dma - copy pages using the DMA engine 2591 * 2592 * @rdev: radeon_device pointer 2593 * @src_offset: src GPU address 2594 * @dst_offset: dst GPU address 2595 * @num_gpu_pages: number of GPU pages to xfer 2596 * @fence: radeon fence object 2597 * 2598 * Copy GPU paging using the DMA engine (r6xx-r7xx). 2599 * Used by the radeon ttm implementation to move pages if 2600 * registered as the asic copy callback. 2601 */ 2602 int r600_copy_dma(struct radeon_device *rdev, 2603 uint64_t src_offset, uint64_t dst_offset, 2604 unsigned num_gpu_pages, 2605 struct radeon_fence **fence) 2606 { 2607 struct radeon_semaphore *sem = NULL; 2608 int ring_index = rdev->asic->copy.dma_ring_index; 2609 struct radeon_ring *ring = &rdev->ring[ring_index]; 2610 u32 size_in_dw, cur_size_in_dw; 2611 int i, num_loops; 2612 int r = 0; 2613 2614 r = radeon_semaphore_create(rdev, &sem); 2615 if (r) { 2616 DRM_ERROR("radeon: moving bo (%d).\n", r); 2617 return r; 2618 } 2619 2620 size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4; 2621 num_loops = DIV_ROUND_UP(size_in_dw, 0xffff); 2622 r = radeon_ring_lock(rdev, ring, num_loops * 5 + 8); 2623 if (r) { 2624 DRM_ERROR("radeon: moving bo (%d).\n", r); 2625 radeon_semaphore_free(rdev, &sem, NULL); 2626 return r; 2627 } 2628 2629 if (radeon_fence_need_sync(*fence, ring->idx)) { 2630 radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring, 2631 ring->idx); 2632 radeon_fence_note_sync(*fence, ring->idx); 2633 } else { 2634 radeon_semaphore_free(rdev, &sem, NULL); 2635 } 2636 2637 for (i = 0; i < num_loops; i++) { 2638 cur_size_in_dw = size_in_dw; 2639 if (cur_size_in_dw > 0xFFFF) 2640 cur_size_in_dw = 0xFFFF; 2641 size_in_dw -= cur_size_in_dw; 2642 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw)); 2643 radeon_ring_write(ring, dst_offset & 0xfffffffc); 2644 radeon_ring_write(ring, src_offset & 0xfffffffc); 2645 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); 2646 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff); 2647 src_offset += cur_size_in_dw * 4; 2648 dst_offset += cur_size_in_dw * 4; 2649 } 2650 2651 r = radeon_fence_emit(rdev, fence, ring->idx); 2652 if (r) { 2653 radeon_ring_unlock_undo(rdev, ring); 2654 return r; 2655 } 2656 2657 radeon_ring_unlock_commit(rdev, ring); 2658 radeon_semaphore_free(rdev, &sem, *fence); 2659 2660 return r; 2661 } 2662 2663 int r600_set_surface_reg(struct radeon_device *rdev, int reg, 2664 uint32_t tiling_flags, uint32_t pitch, 2665 uint32_t offset, uint32_t obj_size) 2666 { 2667 /* FIXME: implement */ 2668 return 0; 2669 } 2670 2671 void r600_clear_surface_reg(struct radeon_device *rdev, int reg) 2672 { 2673 /* FIXME: implement */ 2674 } 2675 2676 static int r600_startup(struct radeon_device *rdev) 2677 { 2678 struct radeon_ring *ring; 2679 int r; 2680 2681 /* enable pcie gen2 link */ 2682 r600_pcie_gen2_enable(rdev); 2683 2684 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { 2685 r = r600_init_microcode(rdev); 2686 if (r) { 2687 DRM_ERROR("Failed to load firmware!\n"); 2688 return r; 2689 } 2690 } 2691 2692 r = r600_vram_scratch_init(rdev); 2693 if (r) 2694 return r; 2695 2696 r600_mc_program(rdev); 2697 if (rdev->flags & RADEON_IS_AGP) { 2698 r600_agp_enable(rdev); 2699 } else { 2700 r = r600_pcie_gart_enable(rdev); 2701 if (r) 2702 return r; 2703 } 2704 r600_gpu_init(rdev); 2705 r = r600_blit_init(rdev); 2706 if (r) { 2707 r600_blit_fini(rdev); 2708 rdev->asic->copy.copy = NULL; 2709 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); 2710 } 2711 2712 /* allocate wb buffer */ 2713 r = radeon_wb_init(rdev); 2714 if (r) 2715 return r; 2716 2717 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 2718 if (r) { 2719 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 2720 return r; 2721 } 2722 2723 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX); 2724 if (r) { 2725 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); 2726 return r; 2727 } 2728 2729 /* Enable IRQ */ 2730 r = r600_irq_init(rdev); 2731 if (r) { 2732 DRM_ERROR("radeon: IH init failed (%d).\n", r); 2733 radeon_irq_kms_fini(rdev); 2734 return r; 2735 } 2736 r600_irq_set(rdev); 2737 2738 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2739 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, 2740 R600_CP_RB_RPTR, R600_CP_RB_WPTR, 2741 0, 0xfffff, RADEON_CP_PACKET2); 2742 if (r) 2743 return r; 2744 2745 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; 2746 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, 2747 DMA_RB_RPTR, DMA_RB_WPTR, 2748 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); 2749 if (r) 2750 return r; 2751 2752 r = r600_cp_load_microcode(rdev); 2753 if (r) 2754 return r; 2755 r = r600_cp_resume(rdev); 2756 if (r) 2757 return r; 2758 2759 r = r600_dma_resume(rdev); 2760 if (r) 2761 return r; 2762 2763 r = radeon_ib_pool_init(rdev); 2764 if (r) { 2765 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 2766 return r; 2767 } 2768 2769 r = r600_audio_init(rdev); 2770 if (r) { 2771 DRM_ERROR("radeon: audio init failed\n"); 2772 return r; 2773 } 2774 2775 return 0; 2776 } 2777 2778 void r600_vga_set_state(struct radeon_device *rdev, bool state) 2779 { 2780 uint32_t temp; 2781 2782 temp = RREG32(CONFIG_CNTL); 2783 if (state == false) { 2784 temp &= ~(1<<0); 2785 temp |= (1<<1); 2786 } else { 2787 temp &= ~(1<<1); 2788 } 2789 WREG32(CONFIG_CNTL, temp); 2790 } 2791 2792 int r600_resume(struct radeon_device *rdev) 2793 { 2794 int r; 2795 2796 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw, 2797 * posting will perform necessary task to bring back GPU into good 2798 * shape. 2799 */ 2800 /* post card */ 2801 atom_asic_init(rdev->mode_info.atom_context); 2802 2803 rdev->accel_working = true; 2804 r = r600_startup(rdev); 2805 if (r) { 2806 DRM_ERROR("r600 startup failed on resume\n"); 2807 rdev->accel_working = false; 2808 return r; 2809 } 2810 2811 return r; 2812 } 2813 2814 int r600_suspend(struct radeon_device *rdev) 2815 { 2816 r600_audio_fini(rdev); 2817 r600_cp_stop(rdev); 2818 r600_dma_stop(rdev); 2819 r600_irq_suspend(rdev); 2820 radeon_wb_disable(rdev); 2821 r600_pcie_gart_disable(rdev); 2822 2823 return 0; 2824 } 2825 2826 /* Plan is to move initialization in that function and use 2827 * helper function so that radeon_device_init pretty much 2828 * do nothing more than calling asic specific function. This 2829 * should also allow to remove a bunch of callback function 2830 * like vram_info. 2831 */ 2832 int r600_init(struct radeon_device *rdev) 2833 { 2834 int r; 2835 2836 if (r600_debugfs_mc_info_init(rdev)) { 2837 DRM_ERROR("Failed to register debugfs file for mc !\n"); 2838 } 2839 /* Read BIOS */ 2840 if (!radeon_get_bios(rdev)) { 2841 if (ASIC_IS_AVIVO(rdev)) 2842 return -EINVAL; 2843 } 2844 /* Must be an ATOMBIOS */ 2845 if (!rdev->is_atom_bios) { 2846 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n"); 2847 return -EINVAL; 2848 } 2849 r = radeon_atombios_init(rdev); 2850 if (r) 2851 return r; 2852 /* Post card if necessary */ 2853 if (!radeon_card_posted(rdev)) { 2854 if (!rdev->bios) { 2855 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); 2856 return -EINVAL; 2857 } 2858 DRM_INFO("GPU not posted. posting now...\n"); 2859 atom_asic_init(rdev->mode_info.atom_context); 2860 } 2861 /* Initialize scratch registers */ 2862 r600_scratch_init(rdev); 2863 /* Initialize surface registers */ 2864 radeon_surface_init(rdev); 2865 /* Initialize clocks */ 2866 radeon_get_clock_info(rdev->ddev); 2867 /* Fence driver */ 2868 r = radeon_fence_driver_init(rdev); 2869 if (r) 2870 return r; 2871 if (rdev->flags & RADEON_IS_AGP) { 2872 r = radeon_agp_init(rdev); 2873 if (r) 2874 radeon_agp_disable(rdev); 2875 } 2876 r = r600_mc_init(rdev); 2877 if (r) 2878 return r; 2879 /* Memory manager */ 2880 r = radeon_bo_init(rdev); 2881 if (r) 2882 return r; 2883 2884 r = radeon_irq_kms_init(rdev); 2885 if (r) 2886 return r; 2887 2888 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL; 2889 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024); 2890 2891 rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL; 2892 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024); 2893 2894 rdev->ih.ring_obj = NULL; 2895 r600_ih_ring_init(rdev, 64 * 1024); 2896 2897 r = r600_pcie_gart_init(rdev); 2898 if (r) 2899 return r; 2900 2901 rdev->accel_working = true; 2902 r = r600_startup(rdev); 2903 if (r) { 2904 dev_err(rdev->dev, "disabling GPU acceleration\n"); 2905 r600_cp_fini(rdev); 2906 r600_dma_fini(rdev); 2907 r600_irq_fini(rdev); 2908 radeon_wb_fini(rdev); 2909 radeon_ib_pool_fini(rdev); 2910 radeon_irq_kms_fini(rdev); 2911 r600_pcie_gart_fini(rdev); 2912 rdev->accel_working = false; 2913 } 2914 2915 return 0; 2916 } 2917 2918 void r600_fini(struct radeon_device *rdev) 2919 { 2920 r600_audio_fini(rdev); 2921 r600_blit_fini(rdev); 2922 r600_cp_fini(rdev); 2923 r600_dma_fini(rdev); 2924 r600_irq_fini(rdev); 2925 radeon_wb_fini(rdev); 2926 radeon_ib_pool_fini(rdev); 2927 radeon_irq_kms_fini(rdev); 2928 r600_pcie_gart_fini(rdev); 2929 r600_vram_scratch_fini(rdev); 2930 radeon_agp_fini(rdev); 2931 radeon_gem_fini(rdev); 2932 radeon_fence_driver_fini(rdev); 2933 radeon_bo_fini(rdev); 2934 radeon_atombios_fini(rdev); 2935 kfree(rdev->bios); 2936 rdev->bios = NULL; 2937 } 2938 2939 2940 /* 2941 * CS stuff 2942 */ 2943 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 2944 { 2945 struct radeon_ring *ring = &rdev->ring[ib->ring]; 2946 u32 next_rptr; 2947 2948 if (ring->rptr_save_reg) { 2949 next_rptr = ring->wptr + 3 + 4; 2950 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2951 radeon_ring_write(ring, ((ring->rptr_save_reg - 2952 PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); 2953 radeon_ring_write(ring, next_rptr); 2954 } else if (rdev->wb.enabled) { 2955 next_rptr = ring->wptr + 5 + 4; 2956 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3)); 2957 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); 2958 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18)); 2959 radeon_ring_write(ring, next_rptr); 2960 radeon_ring_write(ring, 0); 2961 } 2962 2963 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 2964 radeon_ring_write(ring, 2965 #ifdef __BIG_ENDIAN 2966 (2 << 0) | 2967 #endif 2968 (ib->gpu_addr & 0xFFFFFFFC)); 2969 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF); 2970 radeon_ring_write(ring, ib->length_dw); 2971 } 2972 2973 int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) 2974 { 2975 struct radeon_ib ib; 2976 uint32_t scratch; 2977 uint32_t tmp = 0; 2978 unsigned i; 2979 int r; 2980 2981 r = radeon_scratch_get(rdev, &scratch); 2982 if (r) { 2983 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); 2984 return r; 2985 } 2986 WREG32(scratch, 0xCAFEDEAD); 2987 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256); 2988 if (r) { 2989 DRM_ERROR("radeon: failed to get ib (%d).\n", r); 2990 goto free_scratch; 2991 } 2992 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1); 2993 ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 2994 ib.ptr[2] = 0xDEADBEEF; 2995 ib.length_dw = 3; 2996 r = radeon_ib_schedule(rdev, &ib, NULL); 2997 if (r) { 2998 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); 2999 goto free_ib; 3000 } 3001 r = radeon_fence_wait(ib.fence, false); 3002 if (r) { 3003 DRM_ERROR("radeon: fence wait failed (%d).\n", r); 3004 goto free_ib; 3005 } 3006 for (i = 0; i < rdev->usec_timeout; i++) { 3007 tmp = RREG32(scratch); 3008 if (tmp == 0xDEADBEEF) 3009 break; 3010 DRM_UDELAY(1); 3011 } 3012 if (i < rdev->usec_timeout) { 3013 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i); 3014 } else { 3015 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n", 3016 scratch, tmp); 3017 r = -EINVAL; 3018 } 3019 free_ib: 3020 radeon_ib_free(rdev, &ib); 3021 free_scratch: 3022 radeon_scratch_free(rdev, scratch); 3023 return r; 3024 } 3025 3026 /** 3027 * r600_dma_ib_test - test an IB on the DMA engine 3028 * 3029 * @rdev: radeon_device pointer 3030 * @ring: radeon_ring structure holding ring information 3031 * 3032 * Test a simple IB in the DMA ring (r6xx-SI). 3033 * Returns 0 on success, error on failure. 3034 */ 3035 int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) 3036 { 3037 struct radeon_ib ib; 3038 unsigned i; 3039 int r; 3040 void __iomem *ptr = (void *)rdev->vram_scratch.ptr; 3041 u32 tmp = 0; 3042 3043 if (!ptr) { 3044 DRM_ERROR("invalid vram scratch pointer\n"); 3045 return -EINVAL; 3046 } 3047 3048 tmp = 0xCAFEDEAD; 3049 writel(tmp, ptr); 3050 3051 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256); 3052 if (r) { 3053 DRM_ERROR("radeon: failed to get ib (%d).\n", r); 3054 return r; 3055 } 3056 3057 ib.ptr[0] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1); 3058 ib.ptr[1] = rdev->vram_scratch.gpu_addr & 0xfffffffc; 3059 ib.ptr[2] = upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff; 3060 ib.ptr[3] = 0xDEADBEEF; 3061 ib.length_dw = 4; 3062 3063 r = radeon_ib_schedule(rdev, &ib, NULL); 3064 if (r) { 3065 radeon_ib_free(rdev, &ib); 3066 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); 3067 return r; 3068 } 3069 r = radeon_fence_wait(ib.fence, false); 3070 if (r) { 3071 DRM_ERROR("radeon: fence wait failed (%d).\n", r); 3072 return r; 3073 } 3074 for (i = 0; i < rdev->usec_timeout; i++) { 3075 tmp = readl(ptr); 3076 if (tmp == 0xDEADBEEF) 3077 break; 3078 DRM_UDELAY(1); 3079 } 3080 if (i < rdev->usec_timeout) { 3081 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i); 3082 } else { 3083 DRM_ERROR("radeon: ib test failed (0x%08X)\n", tmp); 3084 r = -EINVAL; 3085 } 3086 radeon_ib_free(rdev, &ib); 3087 return r; 3088 } 3089 3090 /** 3091 * r600_dma_ring_ib_execute - Schedule an IB on the DMA engine 3092 * 3093 * @rdev: radeon_device pointer 3094 * @ib: IB object to schedule 3095 * 3096 * Schedule an IB in the DMA ring (r6xx-r7xx). 3097 */ 3098 void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 3099 { 3100 struct radeon_ring *ring = &rdev->ring[ib->ring]; 3101 3102 if (rdev->wb.enabled) { 3103 u32 next_rptr = ring->wptr + 4; 3104 while ((next_rptr & 7) != 5) 3105 next_rptr++; 3106 next_rptr += 3; 3107 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1)); 3108 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); 3109 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff); 3110 radeon_ring_write(ring, next_rptr); 3111 } 3112 3113 /* The indirect buffer packet must end on an 8 DW boundary in the DMA ring. 3114 * Pad as necessary with NOPs. 3115 */ 3116 while ((ring->wptr & 7) != 5) 3117 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); 3118 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER, 0, 0, 0)); 3119 radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0)); 3120 radeon_ring_write(ring, (ib->length_dw << 16) | (upper_32_bits(ib->gpu_addr) & 0xFF)); 3121 3122 } 3123 3124 /* 3125 * Interrupts 3126 * 3127 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty 3128 * the same as the CP ring buffer, but in reverse. Rather than the CPU 3129 * writing to the ring and the GPU consuming, the GPU writes to the ring 3130 * and host consumes. As the host irq handler processes interrupts, it 3131 * increments the rptr. When the rptr catches up with the wptr, all the 3132 * current interrupts have been processed. 3133 */ 3134 3135 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size) 3136 { 3137 u32 rb_bufsz; 3138 3139 /* Align ring size */ 3140 rb_bufsz = drm_order(ring_size / 4); 3141 ring_size = (1 << rb_bufsz) * 4; 3142 rdev->ih.ring_size = ring_size; 3143 rdev->ih.ptr_mask = rdev->ih.ring_size - 1; 3144 rdev->ih.rptr = 0; 3145 } 3146 3147 int r600_ih_ring_alloc(struct radeon_device *rdev) 3148 { 3149 int r; 3150 3151 /* Allocate ring buffer */ 3152 if (rdev->ih.ring_obj == NULL) { 3153 r = radeon_bo_create(rdev, rdev->ih.ring_size, 3154 PAGE_SIZE, true, 3155 RADEON_GEM_DOMAIN_GTT, 3156 NULL, &rdev->ih.ring_obj); 3157 if (r) { 3158 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r); 3159 return r; 3160 } 3161 r = radeon_bo_reserve(rdev->ih.ring_obj, false); 3162 if (unlikely(r != 0)) 3163 return r; 3164 r = radeon_bo_pin(rdev->ih.ring_obj, 3165 RADEON_GEM_DOMAIN_GTT, 3166 &rdev->ih.gpu_addr); 3167 if (r) { 3168 radeon_bo_unreserve(rdev->ih.ring_obj); 3169 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r); 3170 return r; 3171 } 3172 r = radeon_bo_kmap(rdev->ih.ring_obj, 3173 (void **)&rdev->ih.ring); 3174 radeon_bo_unreserve(rdev->ih.ring_obj); 3175 if (r) { 3176 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r); 3177 return r; 3178 } 3179 } 3180 return 0; 3181 } 3182 3183 void r600_ih_ring_fini(struct radeon_device *rdev) 3184 { 3185 int r; 3186 if (rdev->ih.ring_obj) { 3187 r = radeon_bo_reserve(rdev->ih.ring_obj, false); 3188 if (likely(r == 0)) { 3189 radeon_bo_kunmap(rdev->ih.ring_obj); 3190 radeon_bo_unpin(rdev->ih.ring_obj); 3191 radeon_bo_unreserve(rdev->ih.ring_obj); 3192 } 3193 radeon_bo_unref(&rdev->ih.ring_obj); 3194 rdev->ih.ring = NULL; 3195 rdev->ih.ring_obj = NULL; 3196 } 3197 } 3198 3199 void r600_rlc_stop(struct radeon_device *rdev) 3200 { 3201 3202 if ((rdev->family >= CHIP_RV770) && 3203 (rdev->family <= CHIP_RV740)) { 3204 /* r7xx asics need to soft reset RLC before halting */ 3205 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC); 3206 RREG32(SRBM_SOFT_RESET); 3207 mdelay(15); 3208 WREG32(SRBM_SOFT_RESET, 0); 3209 RREG32(SRBM_SOFT_RESET); 3210 } 3211 3212 WREG32(RLC_CNTL, 0); 3213 } 3214 3215 static void r600_rlc_start(struct radeon_device *rdev) 3216 { 3217 WREG32(RLC_CNTL, RLC_ENABLE); 3218 } 3219 3220 static int r600_rlc_init(struct radeon_device *rdev) 3221 { 3222 u32 i; 3223 const __be32 *fw_data; 3224 3225 if (!rdev->rlc_fw) 3226 return -EINVAL; 3227 3228 r600_rlc_stop(rdev); 3229 3230 WREG32(RLC_HB_CNTL, 0); 3231 3232 if (rdev->family == CHIP_ARUBA) { 3233 WREG32(TN_RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); 3234 WREG32(TN_RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); 3235 } 3236 if (rdev->family <= CHIP_CAYMAN) { 3237 WREG32(RLC_HB_BASE, 0); 3238 WREG32(RLC_HB_RPTR, 0); 3239 WREG32(RLC_HB_WPTR, 0); 3240 } 3241 if (rdev->family <= CHIP_CAICOS) { 3242 WREG32(RLC_HB_WPTR_LSB_ADDR, 0); 3243 WREG32(RLC_HB_WPTR_MSB_ADDR, 0); 3244 } 3245 WREG32(RLC_MC_CNTL, 0); 3246 WREG32(RLC_UCODE_CNTL, 0); 3247 3248 fw_data = (const __be32 *)rdev->rlc_fw->data; 3249 if (rdev->family >= CHIP_ARUBA) { 3250 for (i = 0; i < ARUBA_RLC_UCODE_SIZE; i++) { 3251 WREG32(RLC_UCODE_ADDR, i); 3252 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); 3253 } 3254 } else if (rdev->family >= CHIP_CAYMAN) { 3255 for (i = 0; i < CAYMAN_RLC_UCODE_SIZE; i++) { 3256 WREG32(RLC_UCODE_ADDR, i); 3257 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); 3258 } 3259 } else if (rdev->family >= CHIP_CEDAR) { 3260 for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) { 3261 WREG32(RLC_UCODE_ADDR, i); 3262 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); 3263 } 3264 } else if (rdev->family >= CHIP_RV770) { 3265 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) { 3266 WREG32(RLC_UCODE_ADDR, i); 3267 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); 3268 } 3269 } else { 3270 for (i = 0; i < RLC_UCODE_SIZE; i++) { 3271 WREG32(RLC_UCODE_ADDR, i); 3272 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); 3273 } 3274 } 3275 WREG32(RLC_UCODE_ADDR, 0); 3276 3277 r600_rlc_start(rdev); 3278 3279 return 0; 3280 } 3281 3282 static void r600_enable_interrupts(struct radeon_device *rdev) 3283 { 3284 u32 ih_cntl = RREG32(IH_CNTL); 3285 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); 3286 3287 ih_cntl |= ENABLE_INTR; 3288 ih_rb_cntl |= IH_RB_ENABLE; 3289 WREG32(IH_CNTL, ih_cntl); 3290 WREG32(IH_RB_CNTL, ih_rb_cntl); 3291 rdev->ih.enabled = true; 3292 } 3293 3294 void r600_disable_interrupts(struct radeon_device *rdev) 3295 { 3296 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); 3297 u32 ih_cntl = RREG32(IH_CNTL); 3298 3299 ih_rb_cntl &= ~IH_RB_ENABLE; 3300 ih_cntl &= ~ENABLE_INTR; 3301 WREG32(IH_RB_CNTL, ih_rb_cntl); 3302 WREG32(IH_CNTL, ih_cntl); 3303 /* set rptr, wptr to 0 */ 3304 WREG32(IH_RB_RPTR, 0); 3305 WREG32(IH_RB_WPTR, 0); 3306 rdev->ih.enabled = false; 3307 rdev->ih.rptr = 0; 3308 } 3309 3310 static void r600_disable_interrupt_state(struct radeon_device *rdev) 3311 { 3312 u32 tmp; 3313 3314 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); 3315 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE; 3316 WREG32(DMA_CNTL, tmp); 3317 WREG32(GRBM_INT_CNTL, 0); 3318 WREG32(DxMODE_INT_MASK, 0); 3319 WREG32(D1GRPH_INTERRUPT_CONTROL, 0); 3320 WREG32(D2GRPH_INTERRUPT_CONTROL, 0); 3321 if (ASIC_IS_DCE3(rdev)) { 3322 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0); 3323 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0); 3324 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3325 WREG32(DC_HPD1_INT_CONTROL, tmp); 3326 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3327 WREG32(DC_HPD2_INT_CONTROL, tmp); 3328 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3329 WREG32(DC_HPD3_INT_CONTROL, tmp); 3330 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3331 WREG32(DC_HPD4_INT_CONTROL, tmp); 3332 if (ASIC_IS_DCE32(rdev)) { 3333 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3334 WREG32(DC_HPD5_INT_CONTROL, tmp); 3335 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3336 WREG32(DC_HPD6_INT_CONTROL, tmp); 3337 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3338 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp); 3339 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3340 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp); 3341 } else { 3342 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3343 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); 3344 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3345 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp); 3346 } 3347 } else { 3348 WREG32(DACA_AUTODETECT_INT_CONTROL, 0); 3349 WREG32(DACB_AUTODETECT_INT_CONTROL, 0); 3350 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; 3351 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 3352 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; 3353 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 3354 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; 3355 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); 3356 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3357 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); 3358 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3359 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp); 3360 } 3361 } 3362 3363 int r600_irq_init(struct radeon_device *rdev) 3364 { 3365 int ret = 0; 3366 int rb_bufsz; 3367 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; 3368 3369 /* allocate ring */ 3370 ret = r600_ih_ring_alloc(rdev); 3371 if (ret) 3372 return ret; 3373 3374 /* disable irqs */ 3375 r600_disable_interrupts(rdev); 3376 3377 /* init rlc */ 3378 ret = r600_rlc_init(rdev); 3379 if (ret) { 3380 r600_ih_ring_fini(rdev); 3381 return ret; 3382 } 3383 3384 /* setup interrupt control */ 3385 /* set dummy read address to ring address */ 3386 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8); 3387 interrupt_cntl = RREG32(INTERRUPT_CNTL); 3388 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi 3389 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN 3390 */ 3391 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE; 3392 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */ 3393 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN; 3394 WREG32(INTERRUPT_CNTL, interrupt_cntl); 3395 3396 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8); 3397 rb_bufsz = drm_order(rdev->ih.ring_size / 4); 3398 3399 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE | 3400 IH_WPTR_OVERFLOW_CLEAR | 3401 (rb_bufsz << 1)); 3402 3403 if (rdev->wb.enabled) 3404 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE; 3405 3406 /* set the writeback address whether it's enabled or not */ 3407 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC); 3408 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF); 3409 3410 WREG32(IH_RB_CNTL, ih_rb_cntl); 3411 3412 /* set rptr, wptr to 0 */ 3413 WREG32(IH_RB_RPTR, 0); 3414 WREG32(IH_RB_WPTR, 0); 3415 3416 /* Default settings for IH_CNTL (disabled at first) */ 3417 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10); 3418 /* RPTR_REARM only works if msi's are enabled */ 3419 if (rdev->msi_enabled) 3420 ih_cntl |= RPTR_REARM; 3421 WREG32(IH_CNTL, ih_cntl); 3422 3423 /* force the active interrupt state to all disabled */ 3424 if (rdev->family >= CHIP_CEDAR) 3425 evergreen_disable_interrupt_state(rdev); 3426 else 3427 r600_disable_interrupt_state(rdev); 3428 3429 /* at this point everything should be setup correctly to enable master */ 3430 pci_set_master(rdev->pdev); 3431 3432 /* enable irqs */ 3433 r600_enable_interrupts(rdev); 3434 3435 return ret; 3436 } 3437 3438 void r600_irq_suspend(struct radeon_device *rdev) 3439 { 3440 r600_irq_disable(rdev); 3441 r600_rlc_stop(rdev); 3442 } 3443 3444 void r600_irq_fini(struct radeon_device *rdev) 3445 { 3446 r600_irq_suspend(rdev); 3447 r600_ih_ring_fini(rdev); 3448 } 3449 3450 int r600_irq_set(struct radeon_device *rdev) 3451 { 3452 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; 3453 u32 mode_int = 0; 3454 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0; 3455 u32 grbm_int_cntl = 0; 3456 u32 hdmi0, hdmi1; 3457 u32 d1grph = 0, d2grph = 0; 3458 u32 dma_cntl; 3459 3460 if (!rdev->irq.installed) { 3461 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); 3462 return -EINVAL; 3463 } 3464 /* don't enable anything if the ih is disabled */ 3465 if (!rdev->ih.enabled) { 3466 r600_disable_interrupts(rdev); 3467 /* force the active interrupt state to all disabled */ 3468 r600_disable_interrupt_state(rdev); 3469 return 0; 3470 } 3471 3472 if (ASIC_IS_DCE3(rdev)) { 3473 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN; 3474 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN; 3475 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN; 3476 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN; 3477 if (ASIC_IS_DCE32(rdev)) { 3478 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; 3479 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN; 3480 hdmi0 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~AFMT_AZ_FORMAT_WTRIG_MASK; 3481 hdmi1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~AFMT_AZ_FORMAT_WTRIG_MASK; 3482 } else { 3483 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3484 hdmi1 = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3485 } 3486 } else { 3487 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN; 3488 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN; 3489 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN; 3490 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3491 hdmi1 = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3492 } 3493 dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE; 3494 3495 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { 3496 DRM_DEBUG("r600_irq_set: sw int\n"); 3497 cp_int_cntl |= RB_INT_ENABLE; 3498 cp_int_cntl |= TIME_STAMP_INT_ENABLE; 3499 } 3500 3501 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) { 3502 DRM_DEBUG("r600_irq_set: sw int dma\n"); 3503 dma_cntl |= TRAP_ENABLE; 3504 } 3505 3506 if (rdev->irq.crtc_vblank_int[0] || 3507 atomic_read(&rdev->irq.pflip[0])) { 3508 DRM_DEBUG("r600_irq_set: vblank 0\n"); 3509 mode_int |= D1MODE_VBLANK_INT_MASK; 3510 } 3511 if (rdev->irq.crtc_vblank_int[1] || 3512 atomic_read(&rdev->irq.pflip[1])) { 3513 DRM_DEBUG("r600_irq_set: vblank 1\n"); 3514 mode_int |= D2MODE_VBLANK_INT_MASK; 3515 } 3516 if (rdev->irq.hpd[0]) { 3517 DRM_DEBUG("r600_irq_set: hpd 1\n"); 3518 hpd1 |= DC_HPDx_INT_EN; 3519 } 3520 if (rdev->irq.hpd[1]) { 3521 DRM_DEBUG("r600_irq_set: hpd 2\n"); 3522 hpd2 |= DC_HPDx_INT_EN; 3523 } 3524 if (rdev->irq.hpd[2]) { 3525 DRM_DEBUG("r600_irq_set: hpd 3\n"); 3526 hpd3 |= DC_HPDx_INT_EN; 3527 } 3528 if (rdev->irq.hpd[3]) { 3529 DRM_DEBUG("r600_irq_set: hpd 4\n"); 3530 hpd4 |= DC_HPDx_INT_EN; 3531 } 3532 if (rdev->irq.hpd[4]) { 3533 DRM_DEBUG("r600_irq_set: hpd 5\n"); 3534 hpd5 |= DC_HPDx_INT_EN; 3535 } 3536 if (rdev->irq.hpd[5]) { 3537 DRM_DEBUG("r600_irq_set: hpd 6\n"); 3538 hpd6 |= DC_HPDx_INT_EN; 3539 } 3540 if (rdev->irq.afmt[0]) { 3541 DRM_DEBUG("r600_irq_set: hdmi 0\n"); 3542 hdmi0 |= HDMI0_AZ_FORMAT_WTRIG_MASK; 3543 } 3544 if (rdev->irq.afmt[1]) { 3545 DRM_DEBUG("r600_irq_set: hdmi 0\n"); 3546 hdmi1 |= HDMI0_AZ_FORMAT_WTRIG_MASK; 3547 } 3548 3549 WREG32(CP_INT_CNTL, cp_int_cntl); 3550 WREG32(DMA_CNTL, dma_cntl); 3551 WREG32(DxMODE_INT_MASK, mode_int); 3552 WREG32(D1GRPH_INTERRUPT_CONTROL, d1grph); 3553 WREG32(D2GRPH_INTERRUPT_CONTROL, d2grph); 3554 WREG32(GRBM_INT_CNTL, grbm_int_cntl); 3555 if (ASIC_IS_DCE3(rdev)) { 3556 WREG32(DC_HPD1_INT_CONTROL, hpd1); 3557 WREG32(DC_HPD2_INT_CONTROL, hpd2); 3558 WREG32(DC_HPD3_INT_CONTROL, hpd3); 3559 WREG32(DC_HPD4_INT_CONTROL, hpd4); 3560 if (ASIC_IS_DCE32(rdev)) { 3561 WREG32(DC_HPD5_INT_CONTROL, hpd5); 3562 WREG32(DC_HPD6_INT_CONTROL, hpd6); 3563 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, hdmi0); 3564 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, hdmi1); 3565 } else { 3566 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0); 3567 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, hdmi1); 3568 } 3569 } else { 3570 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); 3571 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); 3572 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3); 3573 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0); 3574 WREG32(HDMI1_AUDIO_PACKET_CONTROL, hdmi1); 3575 } 3576 3577 return 0; 3578 } 3579 3580 static void r600_irq_ack(struct radeon_device *rdev) 3581 { 3582 u32 tmp; 3583 3584 if (ASIC_IS_DCE3(rdev)) { 3585 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS); 3586 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE); 3587 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2); 3588 if (ASIC_IS_DCE32(rdev)) { 3589 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0); 3590 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1); 3591 } else { 3592 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); 3593 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS); 3594 } 3595 } else { 3596 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS); 3597 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); 3598 rdev->irq.stat_regs.r600.disp_int_cont2 = 0; 3599 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); 3600 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS); 3601 } 3602 rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS); 3603 rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS); 3604 3605 if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED) 3606 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR); 3607 if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED) 3608 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR); 3609 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) 3610 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK); 3611 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) 3612 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK); 3613 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) 3614 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK); 3615 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) 3616 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK); 3617 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) { 3618 if (ASIC_IS_DCE3(rdev)) { 3619 tmp = RREG32(DC_HPD1_INT_CONTROL); 3620 tmp |= DC_HPDx_INT_ACK; 3621 WREG32(DC_HPD1_INT_CONTROL, tmp); 3622 } else { 3623 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); 3624 tmp |= DC_HPDx_INT_ACK; 3625 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 3626 } 3627 } 3628 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) { 3629 if (ASIC_IS_DCE3(rdev)) { 3630 tmp = RREG32(DC_HPD2_INT_CONTROL); 3631 tmp |= DC_HPDx_INT_ACK; 3632 WREG32(DC_HPD2_INT_CONTROL, tmp); 3633 } else { 3634 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); 3635 tmp |= DC_HPDx_INT_ACK; 3636 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 3637 } 3638 } 3639 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) { 3640 if (ASIC_IS_DCE3(rdev)) { 3641 tmp = RREG32(DC_HPD3_INT_CONTROL); 3642 tmp |= DC_HPDx_INT_ACK; 3643 WREG32(DC_HPD3_INT_CONTROL, tmp); 3644 } else { 3645 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); 3646 tmp |= DC_HPDx_INT_ACK; 3647 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); 3648 } 3649 } 3650 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) { 3651 tmp = RREG32(DC_HPD4_INT_CONTROL); 3652 tmp |= DC_HPDx_INT_ACK; 3653 WREG32(DC_HPD4_INT_CONTROL, tmp); 3654 } 3655 if (ASIC_IS_DCE32(rdev)) { 3656 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) { 3657 tmp = RREG32(DC_HPD5_INT_CONTROL); 3658 tmp |= DC_HPDx_INT_ACK; 3659 WREG32(DC_HPD5_INT_CONTROL, tmp); 3660 } 3661 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) { 3662 tmp = RREG32(DC_HPD5_INT_CONTROL); 3663 tmp |= DC_HPDx_INT_ACK; 3664 WREG32(DC_HPD6_INT_CONTROL, tmp); 3665 } 3666 if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG) { 3667 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0); 3668 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; 3669 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp); 3670 } 3671 if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG) { 3672 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1); 3673 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; 3674 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp); 3675 } 3676 } else { 3677 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) { 3678 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL); 3679 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; 3680 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); 3681 } 3682 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) { 3683 if (ASIC_IS_DCE3(rdev)) { 3684 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL); 3685 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; 3686 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp); 3687 } else { 3688 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL); 3689 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; 3690 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp); 3691 } 3692 } 3693 } 3694 } 3695 3696 void r600_irq_disable(struct radeon_device *rdev) 3697 { 3698 r600_disable_interrupts(rdev); 3699 /* Wait and acknowledge irq */ 3700 mdelay(1); 3701 r600_irq_ack(rdev); 3702 r600_disable_interrupt_state(rdev); 3703 } 3704 3705 static u32 r600_get_ih_wptr(struct radeon_device *rdev) 3706 { 3707 u32 wptr, tmp; 3708 3709 if (rdev->wb.enabled) 3710 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]); 3711 else 3712 wptr = RREG32(IH_RB_WPTR); 3713 3714 if (wptr & RB_OVERFLOW) { 3715 /* When a ring buffer overflow happen start parsing interrupt 3716 * from the last not overwritten vector (wptr + 16). Hopefully 3717 * this should allow us to catchup. 3718 */ 3719 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n", 3720 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask); 3721 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; 3722 tmp = RREG32(IH_RB_CNTL); 3723 tmp |= IH_WPTR_OVERFLOW_CLEAR; 3724 WREG32(IH_RB_CNTL, tmp); 3725 } 3726 return (wptr & rdev->ih.ptr_mask); 3727 } 3728 3729 /* r600 IV Ring 3730 * Each IV ring entry is 128 bits: 3731 * [7:0] - interrupt source id 3732 * [31:8] - reserved 3733 * [59:32] - interrupt source data 3734 * [127:60] - reserved 3735 * 3736 * The basic interrupt vector entries 3737 * are decoded as follows: 3738 * src_id src_data description 3739 * 1 0 D1 Vblank 3740 * 1 1 D1 Vline 3741 * 5 0 D2 Vblank 3742 * 5 1 D2 Vline 3743 * 19 0 FP Hot plug detection A 3744 * 19 1 FP Hot plug detection B 3745 * 19 2 DAC A auto-detection 3746 * 19 3 DAC B auto-detection 3747 * 21 4 HDMI block A 3748 * 21 5 HDMI block B 3749 * 176 - CP_INT RB 3750 * 177 - CP_INT IB1 3751 * 178 - CP_INT IB2 3752 * 181 - EOP Interrupt 3753 * 233 - GUI Idle 3754 * 3755 * Note, these are based on r600 and may need to be 3756 * adjusted or added to on newer asics 3757 */ 3758 3759 int r600_irq_process(struct radeon_device *rdev) 3760 { 3761 u32 wptr; 3762 u32 rptr; 3763 u32 src_id, src_data; 3764 u32 ring_index; 3765 bool queue_hotplug = false; 3766 bool queue_hdmi = false; 3767 3768 if (!rdev->ih.enabled || rdev->shutdown) 3769 return IRQ_NONE; 3770 3771 /* No MSIs, need a dummy read to flush PCI DMAs */ 3772 if (!rdev->msi_enabled) 3773 RREG32(IH_RB_WPTR); 3774 3775 wptr = r600_get_ih_wptr(rdev); 3776 3777 restart_ih: 3778 /* is somebody else already processing irqs? */ 3779 if (atomic_xchg(&rdev->ih.lock, 1)) 3780 return IRQ_NONE; 3781 3782 rptr = rdev->ih.rptr; 3783 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr); 3784 3785 /* Order reading of wptr vs. reading of IH ring data */ 3786 rmb(); 3787 3788 /* display interrupts */ 3789 r600_irq_ack(rdev); 3790 3791 while (rptr != wptr) { 3792 /* wptr/rptr are in bytes! */ 3793 ring_index = rptr / 4; 3794 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff; 3795 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff; 3796 3797 switch (src_id) { 3798 case 1: /* D1 vblank/vline */ 3799 switch (src_data) { 3800 case 0: /* D1 vblank */ 3801 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) { 3802 if (rdev->irq.crtc_vblank_int[0]) { 3803 drm_handle_vblank(rdev->ddev, 0); 3804 rdev->pm.vblank_sync = true; 3805 wake_up(&rdev->irq.vblank_queue); 3806 } 3807 if (atomic_read(&rdev->irq.pflip[0])) 3808 radeon_crtc_handle_flip(rdev, 0); 3809 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT; 3810 DRM_DEBUG("IH: D1 vblank\n"); 3811 } 3812 break; 3813 case 1: /* D1 vline */ 3814 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) { 3815 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT; 3816 DRM_DEBUG("IH: D1 vline\n"); 3817 } 3818 break; 3819 default: 3820 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 3821 break; 3822 } 3823 break; 3824 case 5: /* D2 vblank/vline */ 3825 switch (src_data) { 3826 case 0: /* D2 vblank */ 3827 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) { 3828 if (rdev->irq.crtc_vblank_int[1]) { 3829 drm_handle_vblank(rdev->ddev, 1); 3830 rdev->pm.vblank_sync = true; 3831 wake_up(&rdev->irq.vblank_queue); 3832 } 3833 if (atomic_read(&rdev->irq.pflip[1])) 3834 radeon_crtc_handle_flip(rdev, 1); 3835 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT; 3836 DRM_DEBUG("IH: D2 vblank\n"); 3837 } 3838 break; 3839 case 1: /* D1 vline */ 3840 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) { 3841 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT; 3842 DRM_DEBUG("IH: D2 vline\n"); 3843 } 3844 break; 3845 default: 3846 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 3847 break; 3848 } 3849 break; 3850 case 19: /* HPD/DAC hotplug */ 3851 switch (src_data) { 3852 case 0: 3853 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) { 3854 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT; 3855 queue_hotplug = true; 3856 DRM_DEBUG("IH: HPD1\n"); 3857 } 3858 break; 3859 case 1: 3860 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) { 3861 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT; 3862 queue_hotplug = true; 3863 DRM_DEBUG("IH: HPD2\n"); 3864 } 3865 break; 3866 case 4: 3867 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) { 3868 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT; 3869 queue_hotplug = true; 3870 DRM_DEBUG("IH: HPD3\n"); 3871 } 3872 break; 3873 case 5: 3874 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) { 3875 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT; 3876 queue_hotplug = true; 3877 DRM_DEBUG("IH: HPD4\n"); 3878 } 3879 break; 3880 case 10: 3881 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) { 3882 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT; 3883 queue_hotplug = true; 3884 DRM_DEBUG("IH: HPD5\n"); 3885 } 3886 break; 3887 case 12: 3888 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) { 3889 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT; 3890 queue_hotplug = true; 3891 DRM_DEBUG("IH: HPD6\n"); 3892 } 3893 break; 3894 default: 3895 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 3896 break; 3897 } 3898 break; 3899 case 21: /* hdmi */ 3900 switch (src_data) { 3901 case 4: 3902 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) { 3903 rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG; 3904 queue_hdmi = true; 3905 DRM_DEBUG("IH: HDMI0\n"); 3906 } 3907 break; 3908 case 5: 3909 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) { 3910 rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG; 3911 queue_hdmi = true; 3912 DRM_DEBUG("IH: HDMI1\n"); 3913 } 3914 break; 3915 default: 3916 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); 3917 break; 3918 } 3919 break; 3920 case 176: /* CP_INT in ring buffer */ 3921 case 177: /* CP_INT in IB1 */ 3922 case 178: /* CP_INT in IB2 */ 3923 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data); 3924 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 3925 break; 3926 case 181: /* CP EOP event */ 3927 DRM_DEBUG("IH: CP EOP\n"); 3928 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 3929 break; 3930 case 224: /* DMA trap event */ 3931 DRM_DEBUG("IH: DMA trap\n"); 3932 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX); 3933 break; 3934 case 233: /* GUI IDLE */ 3935 DRM_DEBUG("IH: GUI idle\n"); 3936 break; 3937 default: 3938 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 3939 break; 3940 } 3941 3942 /* wptr/rptr are in bytes! */ 3943 rptr += 16; 3944 rptr &= rdev->ih.ptr_mask; 3945 } 3946 if (queue_hotplug) 3947 schedule_work(&rdev->hotplug_work); 3948 if (queue_hdmi) 3949 schedule_work(&rdev->audio_work); 3950 rdev->ih.rptr = rptr; 3951 WREG32(IH_RB_RPTR, rdev->ih.rptr); 3952 atomic_set(&rdev->ih.lock, 0); 3953 3954 /* make sure wptr hasn't changed while processing */ 3955 wptr = r600_get_ih_wptr(rdev); 3956 if (wptr != rptr) 3957 goto restart_ih; 3958 3959 return IRQ_HANDLED; 3960 } 3961 3962 /* 3963 * Debugfs info 3964 */ 3965 #if defined(CONFIG_DEBUG_FS) 3966 3967 static int r600_debugfs_mc_info(struct seq_file *m, void *data) 3968 { 3969 struct drm_info_node *node = (struct drm_info_node *) m->private; 3970 struct drm_device *dev = node->minor->dev; 3971 struct radeon_device *rdev = dev->dev_private; 3972 3973 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS); 3974 DREG32_SYS(m, rdev, VM_L2_STATUS); 3975 return 0; 3976 } 3977 3978 static struct drm_info_list r600_mc_info_list[] = { 3979 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL}, 3980 }; 3981 #endif 3982 3983 int r600_debugfs_mc_info_init(struct radeon_device *rdev) 3984 { 3985 #if defined(CONFIG_DEBUG_FS) 3986 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list)); 3987 #else 3988 return 0; 3989 #endif 3990 } 3991 3992 /** 3993 * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl 3994 * rdev: radeon device structure 3995 * bo: buffer object struct which userspace is waiting for idle 3996 * 3997 * Some R6XX/R7XX doesn't seems to take into account HDP flush performed 3998 * through ring buffer, this leads to corruption in rendering, see 3999 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we 4000 * directly perform HDP flush by writing register through MMIO. 4001 */ 4002 void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo) 4003 { 4004 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read 4005 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL. 4006 * This seems to cause problems on some AGP cards. Just use the old 4007 * method for them. 4008 */ 4009 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) && 4010 rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) { 4011 void __iomem *ptr = (void *)rdev->vram_scratch.ptr; 4012 u32 tmp; 4013 4014 WREG32(HDP_DEBUG1, 0); 4015 tmp = readl((void __iomem *)ptr); 4016 } else 4017 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); 4018 } 4019 4020 void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes) 4021 { 4022 u32 link_width_cntl, mask, target_reg; 4023 4024 if (rdev->flags & RADEON_IS_IGP) 4025 return; 4026 4027 if (!(rdev->flags & RADEON_IS_PCIE)) 4028 return; 4029 4030 /* x2 cards have a special sequence */ 4031 if (ASIC_IS_X2(rdev)) 4032 return; 4033 4034 /* FIXME wait for idle */ 4035 4036 switch (lanes) { 4037 case 0: 4038 mask = RADEON_PCIE_LC_LINK_WIDTH_X0; 4039 break; 4040 case 1: 4041 mask = RADEON_PCIE_LC_LINK_WIDTH_X1; 4042 break; 4043 case 2: 4044 mask = RADEON_PCIE_LC_LINK_WIDTH_X2; 4045 break; 4046 case 4: 4047 mask = RADEON_PCIE_LC_LINK_WIDTH_X4; 4048 break; 4049 case 8: 4050 mask = RADEON_PCIE_LC_LINK_WIDTH_X8; 4051 break; 4052 case 12: 4053 mask = RADEON_PCIE_LC_LINK_WIDTH_X12; 4054 break; 4055 case 16: 4056 default: 4057 mask = RADEON_PCIE_LC_LINK_WIDTH_X16; 4058 break; 4059 } 4060 4061 link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 4062 4063 if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) == 4064 (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT)) 4065 return; 4066 4067 if (link_width_cntl & R600_PCIE_LC_UPCONFIGURE_DIS) 4068 return; 4069 4070 link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK | 4071 RADEON_PCIE_LC_RECONFIG_NOW | 4072 R600_PCIE_LC_RENEGOTIATE_EN | 4073 R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE); 4074 link_width_cntl |= mask; 4075 4076 WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4077 4078 /* some northbridges can renegotiate the link rather than requiring 4079 * a complete re-config. 4080 * e.g., AMD 780/790 northbridges (pci ids: 0x5956, 0x5957, 0x5958, etc.) 4081 */ 4082 if (link_width_cntl & R600_PCIE_LC_RENEGOTIATION_SUPPORT) 4083 link_width_cntl |= R600_PCIE_LC_RENEGOTIATE_EN | R600_PCIE_LC_UPCONFIGURE_SUPPORT; 4084 else 4085 link_width_cntl |= R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE; 4086 4087 WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl | 4088 RADEON_PCIE_LC_RECONFIG_NOW)); 4089 4090 if (rdev->family >= CHIP_RV770) 4091 target_reg = R700_TARGET_AND_CURRENT_PROFILE_INDEX; 4092 else 4093 target_reg = R600_TARGET_AND_CURRENT_PROFILE_INDEX; 4094 4095 /* wait for lane set to complete */ 4096 link_width_cntl = RREG32(target_reg); 4097 while (link_width_cntl == 0xffffffff) 4098 link_width_cntl = RREG32(target_reg); 4099 4100 } 4101 4102 int r600_get_pcie_lanes(struct radeon_device *rdev) 4103 { 4104 u32 link_width_cntl; 4105 4106 if (rdev->flags & RADEON_IS_IGP) 4107 return 0; 4108 4109 if (!(rdev->flags & RADEON_IS_PCIE)) 4110 return 0; 4111 4112 /* x2 cards have a special sequence */ 4113 if (ASIC_IS_X2(rdev)) 4114 return 0; 4115 4116 /* FIXME wait for idle */ 4117 4118 link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 4119 4120 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) { 4121 case RADEON_PCIE_LC_LINK_WIDTH_X0: 4122 return 0; 4123 case RADEON_PCIE_LC_LINK_WIDTH_X1: 4124 return 1; 4125 case RADEON_PCIE_LC_LINK_WIDTH_X2: 4126 return 2; 4127 case RADEON_PCIE_LC_LINK_WIDTH_X4: 4128 return 4; 4129 case RADEON_PCIE_LC_LINK_WIDTH_X8: 4130 return 8; 4131 case RADEON_PCIE_LC_LINK_WIDTH_X16: 4132 default: 4133 return 16; 4134 } 4135 } 4136 4137 static void r600_pcie_gen2_enable(struct radeon_device *rdev) 4138 { 4139 u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp; 4140 u16 link_cntl2; 4141 u32 mask; 4142 int ret; 4143 4144 if (radeon_pcie_gen2 == 0) 4145 return; 4146 4147 if (rdev->flags & RADEON_IS_IGP) 4148 return; 4149 4150 if (!(rdev->flags & RADEON_IS_PCIE)) 4151 return; 4152 4153 /* x2 cards have a special sequence */ 4154 if (ASIC_IS_X2(rdev)) 4155 return; 4156 4157 /* only RV6xx+ chips are supported */ 4158 if (rdev->family <= CHIP_R600) 4159 return; 4160 4161 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); 4162 if (ret != 0) 4163 return; 4164 4165 if (!(mask & DRM_PCIE_SPEED_50)) 4166 return; 4167 4168 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 4169 if (speed_cntl & LC_CURRENT_DATA_RATE) { 4170 DRM_INFO("PCIE gen 2 link speeds already enabled\n"); 4171 return; 4172 } 4173 4174 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"); 4175 4176 /* 55 nm r6xx asics */ 4177 if ((rdev->family == CHIP_RV670) || 4178 (rdev->family == CHIP_RV620) || 4179 (rdev->family == CHIP_RV635)) { 4180 /* advertise upconfig capability */ 4181 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); 4182 link_width_cntl &= ~LC_UPCONFIGURE_DIS; 4183 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4184 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); 4185 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) { 4186 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; 4187 link_width_cntl &= ~(LC_LINK_WIDTH_MASK | 4188 LC_RECONFIG_ARC_MISSING_ESCAPE); 4189 link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN; 4190 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4191 } else { 4192 link_width_cntl |= LC_UPCONFIGURE_DIS; 4193 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4194 } 4195 } 4196 4197 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 4198 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) && 4199 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { 4200 4201 /* 55 nm r6xx asics */ 4202 if ((rdev->family == CHIP_RV670) || 4203 (rdev->family == CHIP_RV620) || 4204 (rdev->family == CHIP_RV635)) { 4205 WREG32(MM_CFGREGS_CNTL, 0x8); 4206 link_cntl2 = RREG32(0x4088); 4207 WREG32(MM_CFGREGS_CNTL, 0); 4208 /* not supported yet */ 4209 if (link_cntl2 & SELECTABLE_DEEMPHASIS) 4210 return; 4211 } 4212 4213 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK; 4214 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT); 4215 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK; 4216 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE; 4217 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE; 4218 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); 4219 4220 tmp = RREG32(0x541c); 4221 WREG32(0x541c, tmp | 0x8); 4222 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN); 4223 link_cntl2 = RREG16(0x4088); 4224 link_cntl2 &= ~TARGET_LINK_SPEED_MASK; 4225 link_cntl2 |= 0x2; 4226 WREG16(0x4088, link_cntl2); 4227 WREG32(MM_CFGREGS_CNTL, 0); 4228 4229 if ((rdev->family == CHIP_RV670) || 4230 (rdev->family == CHIP_RV620) || 4231 (rdev->family == CHIP_RV635)) { 4232 training_cntl = RREG32_PCIE_P(PCIE_LC_TRAINING_CNTL); 4233 training_cntl &= ~LC_POINT_7_PLUS_EN; 4234 WREG32_PCIE_P(PCIE_LC_TRAINING_CNTL, training_cntl); 4235 } else { 4236 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 4237 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN; 4238 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); 4239 } 4240 4241 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 4242 speed_cntl |= LC_GEN2_EN_STRAP; 4243 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); 4244 4245 } else { 4246 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); 4247 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */ 4248 if (1) 4249 link_width_cntl |= LC_UPCONFIGURE_DIS; 4250 else 4251 link_width_cntl &= ~LC_UPCONFIGURE_DIS; 4252 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4253 } 4254 } 4255 4256 /** 4257 * r600_get_gpu_clock - return GPU clock counter snapshot 4258 * 4259 * @rdev: radeon_device pointer 4260 * 4261 * Fetches a GPU clock counter snapshot (R6xx-cayman). 4262 * Returns the 64 bit clock counter snapshot. 4263 */ 4264 uint64_t r600_get_gpu_clock(struct radeon_device *rdev) 4265 { 4266 uint64_t clock; 4267 4268 mutex_lock(&rdev->gpu_clock_mutex); 4269 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1); 4270 clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) | 4271 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 4272 mutex_unlock(&rdev->gpu_clock_mutex); 4273 return clock; 4274 } 4275