1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include <linux/firmware.h> 30 #include <linux/module.h> 31 #include <linux/pci.h> 32 #include <linux/slab.h> 33 #include <linux/seq_file.h> 34 35 #include <drm/drm_device.h> 36 #include <drm/drm_vblank.h> 37 #include <drm/radeon_drm.h> 38 39 #include "atom.h" 40 #include "avivod.h" 41 #include "evergreen.h" 42 #include "r600.h" 43 #include "r600d.h" 44 #include "rv770.h" 45 #include "radeon.h" 46 #include "radeon_asic.h" 47 #include "radeon_audio.h" 48 #include "radeon_mode.h" 49 #include "radeon_ucode.h" 50 51 /* Firmware Names */ 52 MODULE_FIRMWARE("radeon/R600_pfp.bin"); 53 MODULE_FIRMWARE("radeon/R600_me.bin"); 54 MODULE_FIRMWARE("radeon/RV610_pfp.bin"); 55 MODULE_FIRMWARE("radeon/RV610_me.bin"); 56 MODULE_FIRMWARE("radeon/RV630_pfp.bin"); 57 MODULE_FIRMWARE("radeon/RV630_me.bin"); 58 MODULE_FIRMWARE("radeon/RV620_pfp.bin"); 59 MODULE_FIRMWARE("radeon/RV620_me.bin"); 60 MODULE_FIRMWARE("radeon/RV635_pfp.bin"); 61 MODULE_FIRMWARE("radeon/RV635_me.bin"); 62 MODULE_FIRMWARE("radeon/RV670_pfp.bin"); 63 MODULE_FIRMWARE("radeon/RV670_me.bin"); 64 MODULE_FIRMWARE("radeon/RS780_pfp.bin"); 65 MODULE_FIRMWARE("radeon/RS780_me.bin"); 66 MODULE_FIRMWARE("radeon/RV770_pfp.bin"); 67 MODULE_FIRMWARE("radeon/RV770_me.bin"); 68 MODULE_FIRMWARE("radeon/RV770_smc.bin"); 69 MODULE_FIRMWARE("radeon/RV730_pfp.bin"); 70 MODULE_FIRMWARE("radeon/RV730_me.bin"); 71 MODULE_FIRMWARE("radeon/RV730_smc.bin"); 72 MODULE_FIRMWARE("radeon/RV740_smc.bin"); 73 MODULE_FIRMWARE("radeon/RV710_pfp.bin"); 74 MODULE_FIRMWARE("radeon/RV710_me.bin"); 75 MODULE_FIRMWARE("radeon/RV710_smc.bin"); 76 MODULE_FIRMWARE("radeon/R600_rlc.bin"); 77 MODULE_FIRMWARE("radeon/R700_rlc.bin"); 78 MODULE_FIRMWARE("radeon/CEDAR_pfp.bin"); 79 MODULE_FIRMWARE("radeon/CEDAR_me.bin"); 80 MODULE_FIRMWARE("radeon/CEDAR_rlc.bin"); 81 MODULE_FIRMWARE("radeon/CEDAR_smc.bin"); 82 MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin"); 83 MODULE_FIRMWARE("radeon/REDWOOD_me.bin"); 84 MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin"); 85 MODULE_FIRMWARE("radeon/REDWOOD_smc.bin"); 86 MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin"); 87 MODULE_FIRMWARE("radeon/JUNIPER_me.bin"); 88 MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin"); 89 MODULE_FIRMWARE("radeon/JUNIPER_smc.bin"); 90 MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin"); 91 MODULE_FIRMWARE("radeon/CYPRESS_me.bin"); 92 MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin"); 93 MODULE_FIRMWARE("radeon/CYPRESS_smc.bin"); 94 MODULE_FIRMWARE("radeon/PALM_pfp.bin"); 95 MODULE_FIRMWARE("radeon/PALM_me.bin"); 96 MODULE_FIRMWARE("radeon/SUMO_rlc.bin"); 97 MODULE_FIRMWARE("radeon/SUMO_pfp.bin"); 98 MODULE_FIRMWARE("radeon/SUMO_me.bin"); 99 MODULE_FIRMWARE("radeon/SUMO2_pfp.bin"); 100 MODULE_FIRMWARE("radeon/SUMO2_me.bin"); 101 102 static const u32 crtc_offsets[2] = { 103 0, 104 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL 105 }; 106 107 static void r600_debugfs_mc_info_init(struct radeon_device *rdev); 108 109 /* r600,rv610,rv630,rv620,rv635,rv670 */ 110 int r600_mc_wait_for_idle(struct radeon_device *rdev); 111 static void r600_gpu_init(struct radeon_device *rdev); 112 void r600_fini(struct radeon_device *rdev); 113 void r600_irq_disable(struct radeon_device *rdev); 114 static void r600_pcie_gen2_enable(struct radeon_device *rdev); 115 116 /* 117 * Indirect registers accessor 118 */ 119 u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg) 120 { 121 unsigned long flags; 122 u32 r; 123 124 spin_lock_irqsave(&rdev->rcu_idx_lock, flags); 125 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); 126 r = RREG32(R600_RCU_DATA); 127 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags); 128 return r; 129 } 130 131 void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v) 132 { 133 unsigned long flags; 134 135 spin_lock_irqsave(&rdev->rcu_idx_lock, flags); 136 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); 137 WREG32(R600_RCU_DATA, (v)); 138 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags); 139 } 140 141 u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg) 142 { 143 unsigned long flags; 144 u32 r; 145 146 spin_lock_irqsave(&rdev->uvd_idx_lock, flags); 147 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); 148 r = RREG32(R600_UVD_CTX_DATA); 149 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags); 150 return r; 151 } 152 153 void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v) 154 { 155 unsigned long flags; 156 157 spin_lock_irqsave(&rdev->uvd_idx_lock, flags); 158 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); 159 WREG32(R600_UVD_CTX_DATA, (v)); 160 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags); 161 } 162 163 /** 164 * r600_get_allowed_info_register - fetch the register for the info ioctl 165 * 166 * @rdev: radeon_device pointer 167 * @reg: register offset in bytes 168 * @val: register value 169 * 170 * Returns 0 for success or -EINVAL for an invalid register 171 * 172 */ 173 int r600_get_allowed_info_register(struct radeon_device *rdev, 174 u32 reg, u32 *val) 175 { 176 switch (reg) { 177 case GRBM_STATUS: 178 case GRBM_STATUS2: 179 case R_000E50_SRBM_STATUS: 180 case DMA_STATUS_REG: 181 case UVD_STATUS: 182 *val = RREG32(reg); 183 return 0; 184 default: 185 return -EINVAL; 186 } 187 } 188 189 /** 190 * r600_get_xclk - get the xclk 191 * 192 * @rdev: radeon_device pointer 193 * 194 * Returns the reference clock used by the gfx engine 195 * (r6xx, IGPs, APUs). 196 */ 197 u32 r600_get_xclk(struct radeon_device *rdev) 198 { 199 return rdev->clock.spll.reference_freq; 200 } 201 202 int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) 203 { 204 unsigned fb_div = 0, ref_div, vclk_div = 0, dclk_div = 0; 205 int r; 206 207 /* bypass vclk and dclk with bclk */ 208 WREG32_P(CG_UPLL_FUNC_CNTL_2, 209 VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1), 210 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); 211 212 /* assert BYPASS_EN, deassert UPLL_RESET, UPLL_SLEEP and UPLL_CTLREQ */ 213 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~( 214 UPLL_RESET_MASK | UPLL_SLEEP_MASK | UPLL_CTLREQ_MASK)); 215 216 if (rdev->family >= CHIP_RS780) 217 WREG32_P(GFX_MACRO_BYPASS_CNTL, UPLL_BYPASS_CNTL, 218 ~UPLL_BYPASS_CNTL); 219 220 if (!vclk || !dclk) { 221 /* keep the Bypass mode, put PLL to sleep */ 222 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK); 223 return 0; 224 } 225 226 if (rdev->clock.spll.reference_freq == 10000) 227 ref_div = 34; 228 else 229 ref_div = 4; 230 231 r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000, 232 ref_div + 1, 0xFFF, 2, 30, ~0, 233 &fb_div, &vclk_div, &dclk_div); 234 if (r) 235 return r; 236 237 if (rdev->family >= CHIP_RV670 && rdev->family < CHIP_RS780) 238 fb_div >>= 1; 239 else 240 fb_div |= 1; 241 242 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); 243 if (r) 244 return r; 245 246 /* assert PLL_RESET */ 247 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK); 248 249 /* For RS780 we have to choose ref clk */ 250 if (rdev->family >= CHIP_RS780) 251 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_REFCLK_SRC_SEL_MASK, 252 ~UPLL_REFCLK_SRC_SEL_MASK); 253 254 /* set the required fb, ref and post divder values */ 255 WREG32_P(CG_UPLL_FUNC_CNTL, 256 UPLL_FB_DIV(fb_div) | 257 UPLL_REF_DIV(ref_div), 258 ~(UPLL_FB_DIV_MASK | UPLL_REF_DIV_MASK)); 259 WREG32_P(CG_UPLL_FUNC_CNTL_2, 260 UPLL_SW_HILEN(vclk_div >> 1) | 261 UPLL_SW_LOLEN((vclk_div >> 1) + (vclk_div & 1)) | 262 UPLL_SW_HILEN2(dclk_div >> 1) | 263 UPLL_SW_LOLEN2((dclk_div >> 1) + (dclk_div & 1)) | 264 UPLL_DIVEN_MASK | UPLL_DIVEN2_MASK, 265 ~UPLL_SW_MASK); 266 267 /* give the PLL some time to settle */ 268 mdelay(15); 269 270 /* deassert PLL_RESET */ 271 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); 272 273 mdelay(15); 274 275 /* deassert BYPASS EN */ 276 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK); 277 278 if (rdev->family >= CHIP_RS780) 279 WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~UPLL_BYPASS_CNTL); 280 281 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); 282 if (r) 283 return r; 284 285 /* switch VCLK and DCLK selection */ 286 WREG32_P(CG_UPLL_FUNC_CNTL_2, 287 VCLK_SRC_SEL(2) | DCLK_SRC_SEL(2), 288 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); 289 290 mdelay(100); 291 292 return 0; 293 } 294 295 void dce3_program_fmt(struct drm_encoder *encoder) 296 { 297 struct drm_device *dev = encoder->dev; 298 struct radeon_device *rdev = dev->dev_private; 299 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 300 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 301 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 302 int bpc = 0; 303 u32 tmp = 0; 304 enum radeon_connector_dither dither = RADEON_FMT_DITHER_DISABLE; 305 306 if (connector) { 307 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 308 bpc = radeon_get_monitor_bpc(connector); 309 dither = radeon_connector->dither; 310 } 311 312 /* LVDS FMT is set up by atom */ 313 if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) 314 return; 315 316 /* not needed for analog */ 317 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) || 318 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2)) 319 return; 320 321 if (bpc == 0) 322 return; 323 324 switch (bpc) { 325 case 6: 326 if (dither == RADEON_FMT_DITHER_ENABLE) 327 /* XXX sort out optimal dither settings */ 328 tmp |= FMT_SPATIAL_DITHER_EN; 329 else 330 tmp |= FMT_TRUNCATE_EN; 331 break; 332 case 8: 333 if (dither == RADEON_FMT_DITHER_ENABLE) 334 /* XXX sort out optimal dither settings */ 335 tmp |= (FMT_SPATIAL_DITHER_EN | FMT_SPATIAL_DITHER_DEPTH); 336 else 337 tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH); 338 break; 339 case 10: 340 default: 341 /* not needed */ 342 break; 343 } 344 345 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); 346 } 347 348 /* get temperature in millidegrees */ 349 int rv6xx_get_temp(struct radeon_device *rdev) 350 { 351 u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >> 352 ASIC_T_SHIFT; 353 int actual_temp = temp & 0xff; 354 355 if (temp & 0x100) 356 actual_temp -= 256; 357 358 return actual_temp * 1000; 359 } 360 361 void r600_pm_get_dynpm_state(struct radeon_device *rdev) 362 { 363 int i; 364 365 rdev->pm.dynpm_can_upclock = true; 366 rdev->pm.dynpm_can_downclock = true; 367 368 /* power state array is low to high, default is first */ 369 if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) { 370 int min_power_state_index = 0; 371 372 if (rdev->pm.num_power_states > 2) 373 min_power_state_index = 1; 374 375 switch (rdev->pm.dynpm_planned_action) { 376 case DYNPM_ACTION_MINIMUM: 377 rdev->pm.requested_power_state_index = min_power_state_index; 378 rdev->pm.requested_clock_mode_index = 0; 379 rdev->pm.dynpm_can_downclock = false; 380 break; 381 case DYNPM_ACTION_DOWNCLOCK: 382 if (rdev->pm.current_power_state_index == min_power_state_index) { 383 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 384 rdev->pm.dynpm_can_downclock = false; 385 } else { 386 if (rdev->pm.active_crtc_count > 1) { 387 for (i = 0; i < rdev->pm.num_power_states; i++) { 388 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 389 continue; 390 else if (i >= rdev->pm.current_power_state_index) { 391 rdev->pm.requested_power_state_index = 392 rdev->pm.current_power_state_index; 393 break; 394 } else { 395 rdev->pm.requested_power_state_index = i; 396 break; 397 } 398 } 399 } else { 400 if (rdev->pm.current_power_state_index == 0) 401 rdev->pm.requested_power_state_index = 402 rdev->pm.num_power_states - 1; 403 else 404 rdev->pm.requested_power_state_index = 405 rdev->pm.current_power_state_index - 1; 406 } 407 } 408 rdev->pm.requested_clock_mode_index = 0; 409 /* don't use the power state if crtcs are active and no display flag is set */ 410 if ((rdev->pm.active_crtc_count > 0) && 411 (rdev->pm.power_state[rdev->pm.requested_power_state_index]. 412 clock_info[rdev->pm.requested_clock_mode_index].flags & 413 RADEON_PM_MODE_NO_DISPLAY)) { 414 rdev->pm.requested_power_state_index++; 415 } 416 break; 417 case DYNPM_ACTION_UPCLOCK: 418 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) { 419 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 420 rdev->pm.dynpm_can_upclock = false; 421 } else { 422 if (rdev->pm.active_crtc_count > 1) { 423 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) { 424 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 425 continue; 426 else if (i <= rdev->pm.current_power_state_index) { 427 rdev->pm.requested_power_state_index = 428 rdev->pm.current_power_state_index; 429 break; 430 } else { 431 rdev->pm.requested_power_state_index = i; 432 break; 433 } 434 } 435 } else 436 rdev->pm.requested_power_state_index = 437 rdev->pm.current_power_state_index + 1; 438 } 439 rdev->pm.requested_clock_mode_index = 0; 440 break; 441 case DYNPM_ACTION_DEFAULT: 442 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; 443 rdev->pm.requested_clock_mode_index = 0; 444 rdev->pm.dynpm_can_upclock = false; 445 break; 446 case DYNPM_ACTION_NONE: 447 default: 448 DRM_ERROR("Requested mode for not defined action\n"); 449 return; 450 } 451 } else { 452 /* XXX select a power state based on AC/DC, single/dualhead, etc. */ 453 /* for now just select the first power state and switch between clock modes */ 454 /* power state array is low to high, default is first (0) */ 455 if (rdev->pm.active_crtc_count > 1) { 456 rdev->pm.requested_power_state_index = -1; 457 /* start at 1 as we don't want the default mode */ 458 for (i = 1; i < rdev->pm.num_power_states; i++) { 459 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 460 continue; 461 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) || 462 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) { 463 rdev->pm.requested_power_state_index = i; 464 break; 465 } 466 } 467 /* if nothing selected, grab the default state. */ 468 if (rdev->pm.requested_power_state_index == -1) 469 rdev->pm.requested_power_state_index = 0; 470 } else 471 rdev->pm.requested_power_state_index = 1; 472 473 switch (rdev->pm.dynpm_planned_action) { 474 case DYNPM_ACTION_MINIMUM: 475 rdev->pm.requested_clock_mode_index = 0; 476 rdev->pm.dynpm_can_downclock = false; 477 break; 478 case DYNPM_ACTION_DOWNCLOCK: 479 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) { 480 if (rdev->pm.current_clock_mode_index == 0) { 481 rdev->pm.requested_clock_mode_index = 0; 482 rdev->pm.dynpm_can_downclock = false; 483 } else 484 rdev->pm.requested_clock_mode_index = 485 rdev->pm.current_clock_mode_index - 1; 486 } else { 487 rdev->pm.requested_clock_mode_index = 0; 488 rdev->pm.dynpm_can_downclock = false; 489 } 490 /* don't use the power state if crtcs are active and no display flag is set */ 491 if ((rdev->pm.active_crtc_count > 0) && 492 (rdev->pm.power_state[rdev->pm.requested_power_state_index]. 493 clock_info[rdev->pm.requested_clock_mode_index].flags & 494 RADEON_PM_MODE_NO_DISPLAY)) { 495 rdev->pm.requested_clock_mode_index++; 496 } 497 break; 498 case DYNPM_ACTION_UPCLOCK: 499 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) { 500 if (rdev->pm.current_clock_mode_index == 501 (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) { 502 rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index; 503 rdev->pm.dynpm_can_upclock = false; 504 } else 505 rdev->pm.requested_clock_mode_index = 506 rdev->pm.current_clock_mode_index + 1; 507 } else { 508 rdev->pm.requested_clock_mode_index = 509 rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1; 510 rdev->pm.dynpm_can_upclock = false; 511 } 512 break; 513 case DYNPM_ACTION_DEFAULT: 514 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; 515 rdev->pm.requested_clock_mode_index = 0; 516 rdev->pm.dynpm_can_upclock = false; 517 break; 518 case DYNPM_ACTION_NONE: 519 default: 520 DRM_ERROR("Requested mode for not defined action\n"); 521 return; 522 } 523 } 524 525 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n", 526 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 527 clock_info[rdev->pm.requested_clock_mode_index].sclk, 528 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 529 clock_info[rdev->pm.requested_clock_mode_index].mclk, 530 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 531 pcie_lanes); 532 } 533 534 void rs780_pm_init_profile(struct radeon_device *rdev) 535 { 536 if (rdev->pm.num_power_states == 2) { 537 /* default */ 538 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 539 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 540 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 541 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 542 /* low sh */ 543 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; 544 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; 545 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 546 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 547 /* mid sh */ 548 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; 549 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0; 550 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 551 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 552 /* high sh */ 553 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; 554 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1; 555 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 556 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 557 /* low mh */ 558 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; 559 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0; 560 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 561 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 562 /* mid mh */ 563 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; 564 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0; 565 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 566 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 567 /* high mh */ 568 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; 569 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1; 570 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 571 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 572 } else if (rdev->pm.num_power_states == 3) { 573 /* default */ 574 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 575 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 576 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 577 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 578 /* low sh */ 579 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1; 580 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1; 581 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 582 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 583 /* mid sh */ 584 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1; 585 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; 586 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 587 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 588 /* high sh */ 589 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1; 590 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2; 591 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 592 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 593 /* low mh */ 594 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1; 595 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1; 596 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 597 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 598 /* mid mh */ 599 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1; 600 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1; 601 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 602 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 603 /* high mh */ 604 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1; 605 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2; 606 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 607 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 608 } else { 609 /* default */ 610 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 611 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 612 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 613 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 614 /* low sh */ 615 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2; 616 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2; 617 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 618 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 619 /* mid sh */ 620 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2; 621 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2; 622 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 623 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 624 /* high sh */ 625 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2; 626 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3; 627 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 628 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 629 /* low mh */ 630 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2; 631 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0; 632 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 633 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 634 /* mid mh */ 635 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2; 636 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0; 637 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 638 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 639 /* high mh */ 640 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2; 641 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3; 642 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 643 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 644 } 645 } 646 647 void r600_pm_init_profile(struct radeon_device *rdev) 648 { 649 int idx; 650 651 if (rdev->family == CHIP_R600) { 652 /* XXX */ 653 /* default */ 654 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 655 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 656 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 657 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 658 /* low sh */ 659 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 660 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 661 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 662 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 663 /* mid sh */ 664 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 665 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 666 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 667 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 668 /* high sh */ 669 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 670 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 671 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 672 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 673 /* low mh */ 674 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 675 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 676 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 677 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 678 /* mid mh */ 679 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 680 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 681 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 682 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 683 /* high mh */ 684 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 685 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 686 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 687 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 688 } else { 689 if (rdev->pm.num_power_states < 4) { 690 /* default */ 691 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 692 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 693 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 694 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; 695 /* low sh */ 696 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1; 697 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1; 698 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 699 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 700 /* mid sh */ 701 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1; 702 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; 703 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 704 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; 705 /* high sh */ 706 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1; 707 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1; 708 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 709 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; 710 /* low mh */ 711 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2; 712 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2; 713 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 714 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 715 /* low mh */ 716 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2; 717 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2; 718 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 719 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; 720 /* high mh */ 721 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2; 722 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2; 723 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 724 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; 725 } else { 726 /* default */ 727 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 728 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 729 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 730 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; 731 /* low sh */ 732 if (rdev->flags & RADEON_IS_MOBILITY) 733 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0); 734 else 735 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); 736 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx; 737 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx; 738 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 739 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 740 /* mid sh */ 741 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx; 742 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx; 743 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 744 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; 745 /* high sh */ 746 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); 747 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx; 748 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx; 749 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 750 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; 751 /* low mh */ 752 if (rdev->flags & RADEON_IS_MOBILITY) 753 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1); 754 else 755 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1); 756 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx; 757 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx; 758 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 759 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 760 /* mid mh */ 761 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx; 762 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx; 763 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 764 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; 765 /* high mh */ 766 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1); 767 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx; 768 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx; 769 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 770 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; 771 } 772 } 773 } 774 775 void r600_pm_misc(struct radeon_device *rdev) 776 { 777 int req_ps_idx = rdev->pm.requested_power_state_index; 778 int req_cm_idx = rdev->pm.requested_clock_mode_index; 779 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx]; 780 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage; 781 782 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) { 783 /* 0xff01 is a flag rather then an actual voltage */ 784 if (voltage->voltage == 0xff01) 785 return; 786 if (voltage->voltage != rdev->pm.current_vddc) { 787 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); 788 rdev->pm.current_vddc = voltage->voltage; 789 DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage); 790 } 791 } 792 } 793 794 bool r600_gui_idle(struct radeon_device *rdev) 795 { 796 if (RREG32(GRBM_STATUS) & GUI_ACTIVE) 797 return false; 798 else 799 return true; 800 } 801 802 /* hpd for digital panel detect/disconnect */ 803 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) 804 { 805 bool connected = false; 806 807 if (ASIC_IS_DCE3(rdev)) { 808 switch (hpd) { 809 case RADEON_HPD_1: 810 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE) 811 connected = true; 812 break; 813 case RADEON_HPD_2: 814 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE) 815 connected = true; 816 break; 817 case RADEON_HPD_3: 818 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE) 819 connected = true; 820 break; 821 case RADEON_HPD_4: 822 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE) 823 connected = true; 824 break; 825 /* DCE 3.2 */ 826 case RADEON_HPD_5: 827 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE) 828 connected = true; 829 break; 830 case RADEON_HPD_6: 831 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE) 832 connected = true; 833 break; 834 default: 835 break; 836 } 837 } else { 838 switch (hpd) { 839 case RADEON_HPD_1: 840 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) 841 connected = true; 842 break; 843 case RADEON_HPD_2: 844 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) 845 connected = true; 846 break; 847 case RADEON_HPD_3: 848 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) 849 connected = true; 850 break; 851 default: 852 break; 853 } 854 } 855 return connected; 856 } 857 858 void r600_hpd_set_polarity(struct radeon_device *rdev, 859 enum radeon_hpd_id hpd) 860 { 861 u32 tmp; 862 bool connected = r600_hpd_sense(rdev, hpd); 863 864 if (ASIC_IS_DCE3(rdev)) { 865 switch (hpd) { 866 case RADEON_HPD_1: 867 tmp = RREG32(DC_HPD1_INT_CONTROL); 868 if (connected) 869 tmp &= ~DC_HPDx_INT_POLARITY; 870 else 871 tmp |= DC_HPDx_INT_POLARITY; 872 WREG32(DC_HPD1_INT_CONTROL, tmp); 873 break; 874 case RADEON_HPD_2: 875 tmp = RREG32(DC_HPD2_INT_CONTROL); 876 if (connected) 877 tmp &= ~DC_HPDx_INT_POLARITY; 878 else 879 tmp |= DC_HPDx_INT_POLARITY; 880 WREG32(DC_HPD2_INT_CONTROL, tmp); 881 break; 882 case RADEON_HPD_3: 883 tmp = RREG32(DC_HPD3_INT_CONTROL); 884 if (connected) 885 tmp &= ~DC_HPDx_INT_POLARITY; 886 else 887 tmp |= DC_HPDx_INT_POLARITY; 888 WREG32(DC_HPD3_INT_CONTROL, tmp); 889 break; 890 case RADEON_HPD_4: 891 tmp = RREG32(DC_HPD4_INT_CONTROL); 892 if (connected) 893 tmp &= ~DC_HPDx_INT_POLARITY; 894 else 895 tmp |= DC_HPDx_INT_POLARITY; 896 WREG32(DC_HPD4_INT_CONTROL, tmp); 897 break; 898 case RADEON_HPD_5: 899 tmp = RREG32(DC_HPD5_INT_CONTROL); 900 if (connected) 901 tmp &= ~DC_HPDx_INT_POLARITY; 902 else 903 tmp |= DC_HPDx_INT_POLARITY; 904 WREG32(DC_HPD5_INT_CONTROL, tmp); 905 break; 906 /* DCE 3.2 */ 907 case RADEON_HPD_6: 908 tmp = RREG32(DC_HPD6_INT_CONTROL); 909 if (connected) 910 tmp &= ~DC_HPDx_INT_POLARITY; 911 else 912 tmp |= DC_HPDx_INT_POLARITY; 913 WREG32(DC_HPD6_INT_CONTROL, tmp); 914 break; 915 default: 916 break; 917 } 918 } else { 919 switch (hpd) { 920 case RADEON_HPD_1: 921 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); 922 if (connected) 923 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; 924 else 925 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; 926 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 927 break; 928 case RADEON_HPD_2: 929 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); 930 if (connected) 931 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; 932 else 933 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; 934 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 935 break; 936 case RADEON_HPD_3: 937 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); 938 if (connected) 939 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; 940 else 941 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; 942 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); 943 break; 944 default: 945 break; 946 } 947 } 948 } 949 950 void r600_hpd_init(struct radeon_device *rdev) 951 { 952 struct drm_device *dev = rdev->ddev; 953 struct drm_connector *connector; 954 unsigned enable = 0; 955 956 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 957 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 958 959 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || 960 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { 961 /* don't try to enable hpd on eDP or LVDS avoid breaking the 962 * aux dp channel on imac and help (but not completely fix) 963 * https://bugzilla.redhat.com/show_bug.cgi?id=726143 964 */ 965 continue; 966 } 967 if (ASIC_IS_DCE3(rdev)) { 968 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa); 969 if (ASIC_IS_DCE32(rdev)) 970 tmp |= DC_HPDx_EN; 971 972 switch (radeon_connector->hpd.hpd) { 973 case RADEON_HPD_1: 974 WREG32(DC_HPD1_CONTROL, tmp); 975 break; 976 case RADEON_HPD_2: 977 WREG32(DC_HPD2_CONTROL, tmp); 978 break; 979 case RADEON_HPD_3: 980 WREG32(DC_HPD3_CONTROL, tmp); 981 break; 982 case RADEON_HPD_4: 983 WREG32(DC_HPD4_CONTROL, tmp); 984 break; 985 /* DCE 3.2 */ 986 case RADEON_HPD_5: 987 WREG32(DC_HPD5_CONTROL, tmp); 988 break; 989 case RADEON_HPD_6: 990 WREG32(DC_HPD6_CONTROL, tmp); 991 break; 992 default: 993 break; 994 } 995 } else { 996 switch (radeon_connector->hpd.hpd) { 997 case RADEON_HPD_1: 998 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN); 999 break; 1000 case RADEON_HPD_2: 1001 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN); 1002 break; 1003 case RADEON_HPD_3: 1004 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN); 1005 break; 1006 default: 1007 break; 1008 } 1009 } 1010 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) 1011 enable |= 1 << radeon_connector->hpd.hpd; 1012 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); 1013 } 1014 radeon_irq_kms_enable_hpd(rdev, enable); 1015 } 1016 1017 void r600_hpd_fini(struct radeon_device *rdev) 1018 { 1019 struct drm_device *dev = rdev->ddev; 1020 struct drm_connector *connector; 1021 unsigned disable = 0; 1022 1023 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 1024 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1025 if (ASIC_IS_DCE3(rdev)) { 1026 switch (radeon_connector->hpd.hpd) { 1027 case RADEON_HPD_1: 1028 WREG32(DC_HPD1_CONTROL, 0); 1029 break; 1030 case RADEON_HPD_2: 1031 WREG32(DC_HPD2_CONTROL, 0); 1032 break; 1033 case RADEON_HPD_3: 1034 WREG32(DC_HPD3_CONTROL, 0); 1035 break; 1036 case RADEON_HPD_4: 1037 WREG32(DC_HPD4_CONTROL, 0); 1038 break; 1039 /* DCE 3.2 */ 1040 case RADEON_HPD_5: 1041 WREG32(DC_HPD5_CONTROL, 0); 1042 break; 1043 case RADEON_HPD_6: 1044 WREG32(DC_HPD6_CONTROL, 0); 1045 break; 1046 default: 1047 break; 1048 } 1049 } else { 1050 switch (radeon_connector->hpd.hpd) { 1051 case RADEON_HPD_1: 1052 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0); 1053 break; 1054 case RADEON_HPD_2: 1055 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0); 1056 break; 1057 case RADEON_HPD_3: 1058 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0); 1059 break; 1060 default: 1061 break; 1062 } 1063 } 1064 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) 1065 disable |= 1 << radeon_connector->hpd.hpd; 1066 } 1067 radeon_irq_kms_disable_hpd(rdev, disable); 1068 } 1069 1070 /* 1071 * R600 PCIE GART 1072 */ 1073 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev) 1074 { 1075 unsigned i; 1076 u32 tmp; 1077 1078 /* flush hdp cache so updates hit vram */ 1079 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) && 1080 !(rdev->flags & RADEON_IS_AGP)) { 1081 void __iomem *ptr = (void *)rdev->gart.ptr; 1082 1083 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read 1084 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL 1085 * This seems to cause problems on some AGP cards. Just use the old 1086 * method for them. 1087 */ 1088 WREG32(HDP_DEBUG1, 0); 1089 readl((void __iomem *)ptr); 1090 } else 1091 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); 1092 1093 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12); 1094 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12); 1095 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1)); 1096 for (i = 0; i < rdev->usec_timeout; i++) { 1097 /* read MC_STATUS */ 1098 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE); 1099 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT; 1100 if (tmp == 2) { 1101 pr_warn("[drm] r600 flush TLB failed\n"); 1102 return; 1103 } 1104 if (tmp) { 1105 return; 1106 } 1107 udelay(1); 1108 } 1109 } 1110 1111 int r600_pcie_gart_init(struct radeon_device *rdev) 1112 { 1113 int r; 1114 1115 if (rdev->gart.robj) { 1116 WARN(1, "R600 PCIE GART already initialized\n"); 1117 return 0; 1118 } 1119 /* Initialize common gart structure */ 1120 r = radeon_gart_init(rdev); 1121 if (r) 1122 return r; 1123 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; 1124 return radeon_gart_table_vram_alloc(rdev); 1125 } 1126 1127 static int r600_pcie_gart_enable(struct radeon_device *rdev) 1128 { 1129 u32 tmp; 1130 int r, i; 1131 1132 if (rdev->gart.robj == NULL) { 1133 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 1134 return -EINVAL; 1135 } 1136 r = radeon_gart_table_vram_pin(rdev); 1137 if (r) 1138 return r; 1139 1140 /* Setup L2 cache */ 1141 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 1142 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 1143 EFFECTIVE_L2_QUEUE_SIZE(7)); 1144 WREG32(VM_L2_CNTL2, 0); 1145 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); 1146 /* Setup TLB control */ 1147 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | 1148 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 1149 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | 1150 ENABLE_WAIT_L2_QUERY; 1151 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); 1152 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); 1153 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); 1154 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); 1155 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); 1156 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); 1157 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); 1158 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); 1159 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); 1160 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); 1161 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); 1162 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); 1163 WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp); 1164 WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp); 1165 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 1166 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 1167 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); 1168 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); 1169 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); 1170 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | 1171 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); 1172 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 1173 (u32)(rdev->dummy_page.addr >> 12)); 1174 for (i = 1; i < 7; i++) 1175 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 1176 1177 r600_pcie_gart_tlb_flush(rdev); 1178 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 1179 (unsigned)(rdev->mc.gtt_size >> 20), 1180 (unsigned long long)rdev->gart.table_addr); 1181 rdev->gart.ready = true; 1182 return 0; 1183 } 1184 1185 static void r600_pcie_gart_disable(struct radeon_device *rdev) 1186 { 1187 u32 tmp; 1188 int i; 1189 1190 /* Disable all tables */ 1191 for (i = 0; i < 7; i++) 1192 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 1193 1194 /* Disable L2 cache */ 1195 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | 1196 EFFECTIVE_L2_QUEUE_SIZE(7)); 1197 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); 1198 /* Setup L1 TLB control */ 1199 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | 1200 ENABLE_WAIT_L2_QUERY; 1201 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); 1202 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); 1203 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); 1204 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); 1205 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); 1206 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); 1207 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); 1208 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); 1209 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp); 1210 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp); 1211 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); 1212 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); 1213 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp); 1214 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); 1215 WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp); 1216 WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp); 1217 radeon_gart_table_vram_unpin(rdev); 1218 } 1219 1220 static void r600_pcie_gart_fini(struct radeon_device *rdev) 1221 { 1222 radeon_gart_fini(rdev); 1223 r600_pcie_gart_disable(rdev); 1224 radeon_gart_table_vram_free(rdev); 1225 } 1226 1227 static void r600_agp_enable(struct radeon_device *rdev) 1228 { 1229 u32 tmp; 1230 int i; 1231 1232 /* Setup L2 cache */ 1233 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 1234 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 1235 EFFECTIVE_L2_QUEUE_SIZE(7)); 1236 WREG32(VM_L2_CNTL2, 0); 1237 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); 1238 /* Setup TLB control */ 1239 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | 1240 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 1241 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | 1242 ENABLE_WAIT_L2_QUERY; 1243 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); 1244 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); 1245 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); 1246 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); 1247 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); 1248 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); 1249 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); 1250 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); 1251 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); 1252 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); 1253 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); 1254 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); 1255 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 1256 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 1257 for (i = 0; i < 7; i++) 1258 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 1259 } 1260 1261 int r600_mc_wait_for_idle(struct radeon_device *rdev) 1262 { 1263 unsigned i; 1264 u32 tmp; 1265 1266 for (i = 0; i < rdev->usec_timeout; i++) { 1267 /* read MC_STATUS */ 1268 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00; 1269 if (!tmp) 1270 return 0; 1271 udelay(1); 1272 } 1273 return -1; 1274 } 1275 1276 uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg) 1277 { 1278 unsigned long flags; 1279 uint32_t r; 1280 1281 spin_lock_irqsave(&rdev->mc_idx_lock, flags); 1282 WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg)); 1283 r = RREG32(R_0028FC_MC_DATA); 1284 WREG32(R_0028F8_MC_INDEX, ~C_0028F8_MC_IND_ADDR); 1285 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); 1286 return r; 1287 } 1288 1289 void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 1290 { 1291 unsigned long flags; 1292 1293 spin_lock_irqsave(&rdev->mc_idx_lock, flags); 1294 WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg) | 1295 S_0028F8_MC_IND_WR_EN(1)); 1296 WREG32(R_0028FC_MC_DATA, v); 1297 WREG32(R_0028F8_MC_INDEX, 0x7F); 1298 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); 1299 } 1300 1301 static void r600_mc_program(struct radeon_device *rdev) 1302 { 1303 struct rv515_mc_save save; 1304 u32 tmp; 1305 int i, j; 1306 1307 /* Initialize HDP */ 1308 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 1309 WREG32((0x2c14 + j), 0x00000000); 1310 WREG32((0x2c18 + j), 0x00000000); 1311 WREG32((0x2c1c + j), 0x00000000); 1312 WREG32((0x2c20 + j), 0x00000000); 1313 WREG32((0x2c24 + j), 0x00000000); 1314 } 1315 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); 1316 1317 rv515_mc_stop(rdev, &save); 1318 if (r600_mc_wait_for_idle(rdev)) { 1319 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1320 } 1321 /* Lockout access through VGA aperture (doesn't exist before R600) */ 1322 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); 1323 /* Update configuration */ 1324 if (rdev->flags & RADEON_IS_AGP) { 1325 if (rdev->mc.vram_start < rdev->mc.gtt_start) { 1326 /* VRAM before AGP */ 1327 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 1328 rdev->mc.vram_start >> 12); 1329 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 1330 rdev->mc.gtt_end >> 12); 1331 } else { 1332 /* VRAM after AGP */ 1333 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 1334 rdev->mc.gtt_start >> 12); 1335 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 1336 rdev->mc.vram_end >> 12); 1337 } 1338 } else { 1339 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12); 1340 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12); 1341 } 1342 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); 1343 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; 1344 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); 1345 WREG32(MC_VM_FB_LOCATION, tmp); 1346 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); 1347 WREG32(HDP_NONSURFACE_INFO, (2 << 7)); 1348 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); 1349 if (rdev->flags & RADEON_IS_AGP) { 1350 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22); 1351 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22); 1352 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); 1353 } else { 1354 WREG32(MC_VM_AGP_BASE, 0); 1355 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); 1356 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); 1357 } 1358 if (r600_mc_wait_for_idle(rdev)) { 1359 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1360 } 1361 rv515_mc_resume(rdev, &save); 1362 /* we need to own VRAM, so turn off the VGA renderer here 1363 * to stop it overwriting our objects */ 1364 rv515_vga_render_disable(rdev); 1365 } 1366 1367 /** 1368 * r600_vram_gtt_location - try to find VRAM & GTT location 1369 * @rdev: radeon device structure holding all necessary informations 1370 * @mc: memory controller structure holding memory informations 1371 * 1372 * Function will place try to place VRAM at same place as in CPU (PCI) 1373 * address space as some GPU seems to have issue when we reprogram at 1374 * different address space. 1375 * 1376 * If there is not enough space to fit the unvisible VRAM after the 1377 * aperture then we limit the VRAM size to the aperture. 1378 * 1379 * If we are using AGP then place VRAM adjacent to AGP aperture are we need 1380 * them to be in one from GPU point of view so that we can program GPU to 1381 * catch access outside them (weird GPU policy see ??). 1382 * 1383 * This function will never fails, worst case are limiting VRAM or GTT. 1384 * 1385 * Note: GTT start, end, size should be initialized before calling this 1386 * function on AGP platform. 1387 */ 1388 static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) 1389 { 1390 u64 size_bf, size_af; 1391 1392 if (mc->mc_vram_size > 0xE0000000) { 1393 /* leave room for at least 512M GTT */ 1394 dev_warn(rdev->dev, "limiting VRAM\n"); 1395 mc->real_vram_size = 0xE0000000; 1396 mc->mc_vram_size = 0xE0000000; 1397 } 1398 if (rdev->flags & RADEON_IS_AGP) { 1399 size_bf = mc->gtt_start; 1400 size_af = mc->mc_mask - mc->gtt_end; 1401 if (size_bf > size_af) { 1402 if (mc->mc_vram_size > size_bf) { 1403 dev_warn(rdev->dev, "limiting VRAM\n"); 1404 mc->real_vram_size = size_bf; 1405 mc->mc_vram_size = size_bf; 1406 } 1407 mc->vram_start = mc->gtt_start - mc->mc_vram_size; 1408 } else { 1409 if (mc->mc_vram_size > size_af) { 1410 dev_warn(rdev->dev, "limiting VRAM\n"); 1411 mc->real_vram_size = size_af; 1412 mc->mc_vram_size = size_af; 1413 } 1414 mc->vram_start = mc->gtt_end + 1; 1415 } 1416 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 1417 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n", 1418 mc->mc_vram_size >> 20, mc->vram_start, 1419 mc->vram_end, mc->real_vram_size >> 20); 1420 } else { 1421 u64 base = 0; 1422 if (rdev->flags & RADEON_IS_IGP) { 1423 base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF; 1424 base <<= 24; 1425 } 1426 radeon_vram_location(rdev, &rdev->mc, base); 1427 rdev->mc.gtt_base_align = 0; 1428 radeon_gtt_location(rdev, mc); 1429 } 1430 } 1431 1432 static int r600_mc_init(struct radeon_device *rdev) 1433 { 1434 u32 tmp; 1435 int chansize, numchan; 1436 uint32_t h_addr, l_addr; 1437 unsigned long long k8_addr; 1438 1439 /* Get VRAM informations */ 1440 rdev->mc.vram_is_ddr = true; 1441 tmp = RREG32(RAMCFG); 1442 if (tmp & CHANSIZE_OVERRIDE) { 1443 chansize = 16; 1444 } else if (tmp & CHANSIZE_MASK) { 1445 chansize = 64; 1446 } else { 1447 chansize = 32; 1448 } 1449 tmp = RREG32(CHMAP); 1450 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { 1451 case 0: 1452 default: 1453 numchan = 1; 1454 break; 1455 case 1: 1456 numchan = 2; 1457 break; 1458 case 2: 1459 numchan = 4; 1460 break; 1461 case 3: 1462 numchan = 8; 1463 break; 1464 } 1465 rdev->mc.vram_width = numchan * chansize; 1466 /* Could aper size report 0 ? */ 1467 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); 1468 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); 1469 /* Setup GPU memory space */ 1470 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); 1471 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); 1472 rdev->mc.visible_vram_size = rdev->mc.aper_size; 1473 r600_vram_gtt_location(rdev, &rdev->mc); 1474 1475 if (rdev->flags & RADEON_IS_IGP) { 1476 rs690_pm_info(rdev); 1477 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); 1478 1479 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) { 1480 /* Use K8 direct mapping for fast fb access. */ 1481 rdev->fastfb_working = false; 1482 h_addr = G_000012_K8_ADDR_EXT(RREG32_MC(R_000012_MC_MISC_UMA_CNTL)); 1483 l_addr = RREG32_MC(R_000011_K8_FB_LOCATION); 1484 k8_addr = ((unsigned long long)h_addr) << 32 | l_addr; 1485 #if defined(CONFIG_X86_32) && !defined(CONFIG_X86_PAE) 1486 if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL) 1487 #endif 1488 { 1489 /* FastFB shall be used with UMA memory. Here it is simply disabled when sideport 1490 * memory is present. 1491 */ 1492 if (rdev->mc.igp_sideport_enabled == false && radeon_fastfb == 1) { 1493 DRM_INFO("Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n", 1494 (unsigned long long)rdev->mc.aper_base, k8_addr); 1495 rdev->mc.aper_base = (resource_size_t)k8_addr; 1496 rdev->fastfb_working = true; 1497 } 1498 } 1499 } 1500 } 1501 1502 radeon_update_bandwidth_info(rdev); 1503 return 0; 1504 } 1505 1506 int r600_vram_scratch_init(struct radeon_device *rdev) 1507 { 1508 int r; 1509 1510 if (rdev->vram_scratch.robj == NULL) { 1511 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, 1512 PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM, 1513 0, NULL, NULL, &rdev->vram_scratch.robj); 1514 if (r) { 1515 return r; 1516 } 1517 } 1518 1519 r = radeon_bo_reserve(rdev->vram_scratch.robj, false); 1520 if (unlikely(r != 0)) 1521 return r; 1522 r = radeon_bo_pin(rdev->vram_scratch.robj, 1523 RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr); 1524 if (r) { 1525 radeon_bo_unreserve(rdev->vram_scratch.robj); 1526 return r; 1527 } 1528 r = radeon_bo_kmap(rdev->vram_scratch.robj, 1529 (void **)&rdev->vram_scratch.ptr); 1530 if (r) 1531 radeon_bo_unpin(rdev->vram_scratch.robj); 1532 radeon_bo_unreserve(rdev->vram_scratch.robj); 1533 1534 return r; 1535 } 1536 1537 void r600_vram_scratch_fini(struct radeon_device *rdev) 1538 { 1539 int r; 1540 1541 if (rdev->vram_scratch.robj == NULL) { 1542 return; 1543 } 1544 r = radeon_bo_reserve(rdev->vram_scratch.robj, false); 1545 if (likely(r == 0)) { 1546 radeon_bo_kunmap(rdev->vram_scratch.robj); 1547 radeon_bo_unpin(rdev->vram_scratch.robj); 1548 radeon_bo_unreserve(rdev->vram_scratch.robj); 1549 } 1550 radeon_bo_unref(&rdev->vram_scratch.robj); 1551 } 1552 1553 void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung) 1554 { 1555 u32 tmp = RREG32(R600_BIOS_3_SCRATCH); 1556 1557 if (hung) 1558 tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG; 1559 else 1560 tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG; 1561 1562 WREG32(R600_BIOS_3_SCRATCH, tmp); 1563 } 1564 1565 static void r600_print_gpu_status_regs(struct radeon_device *rdev) 1566 { 1567 dev_info(rdev->dev, " R_008010_GRBM_STATUS = 0x%08X\n", 1568 RREG32(R_008010_GRBM_STATUS)); 1569 dev_info(rdev->dev, " R_008014_GRBM_STATUS2 = 0x%08X\n", 1570 RREG32(R_008014_GRBM_STATUS2)); 1571 dev_info(rdev->dev, " R_000E50_SRBM_STATUS = 0x%08X\n", 1572 RREG32(R_000E50_SRBM_STATUS)); 1573 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n", 1574 RREG32(CP_STALLED_STAT1)); 1575 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n", 1576 RREG32(CP_STALLED_STAT2)); 1577 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n", 1578 RREG32(CP_BUSY_STAT)); 1579 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n", 1580 RREG32(CP_STAT)); 1581 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n", 1582 RREG32(DMA_STATUS_REG)); 1583 } 1584 1585 static bool r600_is_display_hung(struct radeon_device *rdev) 1586 { 1587 u32 crtc_hung = 0; 1588 u32 crtc_status[2]; 1589 u32 i, j, tmp; 1590 1591 for (i = 0; i < rdev->num_crtc; i++) { 1592 if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN) { 1593 crtc_status[i] = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]); 1594 crtc_hung |= (1 << i); 1595 } 1596 } 1597 1598 for (j = 0; j < 10; j++) { 1599 for (i = 0; i < rdev->num_crtc; i++) { 1600 if (crtc_hung & (1 << i)) { 1601 tmp = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]); 1602 if (tmp != crtc_status[i]) 1603 crtc_hung &= ~(1 << i); 1604 } 1605 } 1606 if (crtc_hung == 0) 1607 return false; 1608 udelay(100); 1609 } 1610 1611 return true; 1612 } 1613 1614 u32 r600_gpu_check_soft_reset(struct radeon_device *rdev) 1615 { 1616 u32 reset_mask = 0; 1617 u32 tmp; 1618 1619 /* GRBM_STATUS */ 1620 tmp = RREG32(R_008010_GRBM_STATUS); 1621 if (rdev->family >= CHIP_RV770) { 1622 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) | 1623 G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) | 1624 G_008010_TA_BUSY(tmp) | G_008010_VGT_BUSY(tmp) | 1625 G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) | 1626 G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp)) 1627 reset_mask |= RADEON_RESET_GFX; 1628 } else { 1629 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) | 1630 G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) | 1631 G_008010_TA03_BUSY(tmp) | G_008010_VGT_BUSY(tmp) | 1632 G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) | 1633 G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp)) 1634 reset_mask |= RADEON_RESET_GFX; 1635 } 1636 1637 if (G_008010_CF_RQ_PENDING(tmp) | G_008010_PF_RQ_PENDING(tmp) | 1638 G_008010_CP_BUSY(tmp) | G_008010_CP_COHERENCY_BUSY(tmp)) 1639 reset_mask |= RADEON_RESET_CP; 1640 1641 if (G_008010_GRBM_EE_BUSY(tmp)) 1642 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP; 1643 1644 /* DMA_STATUS_REG */ 1645 tmp = RREG32(DMA_STATUS_REG); 1646 if (!(tmp & DMA_IDLE)) 1647 reset_mask |= RADEON_RESET_DMA; 1648 1649 /* SRBM_STATUS */ 1650 tmp = RREG32(R_000E50_SRBM_STATUS); 1651 if (G_000E50_RLC_RQ_PENDING(tmp) | G_000E50_RLC_BUSY(tmp)) 1652 reset_mask |= RADEON_RESET_RLC; 1653 1654 if (G_000E50_IH_BUSY(tmp)) 1655 reset_mask |= RADEON_RESET_IH; 1656 1657 if (G_000E50_SEM_BUSY(tmp)) 1658 reset_mask |= RADEON_RESET_SEM; 1659 1660 if (G_000E50_GRBM_RQ_PENDING(tmp)) 1661 reset_mask |= RADEON_RESET_GRBM; 1662 1663 if (G_000E50_VMC_BUSY(tmp)) 1664 reset_mask |= RADEON_RESET_VMC; 1665 1666 if (G_000E50_MCB_BUSY(tmp) | G_000E50_MCDZ_BUSY(tmp) | 1667 G_000E50_MCDY_BUSY(tmp) | G_000E50_MCDX_BUSY(tmp) | 1668 G_000E50_MCDW_BUSY(tmp)) 1669 reset_mask |= RADEON_RESET_MC; 1670 1671 if (r600_is_display_hung(rdev)) 1672 reset_mask |= RADEON_RESET_DISPLAY; 1673 1674 /* Skip MC reset as it's mostly likely not hung, just busy */ 1675 if (reset_mask & RADEON_RESET_MC) { 1676 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask); 1677 reset_mask &= ~RADEON_RESET_MC; 1678 } 1679 1680 return reset_mask; 1681 } 1682 1683 static void r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) 1684 { 1685 struct rv515_mc_save save; 1686 u32 grbm_soft_reset = 0, srbm_soft_reset = 0; 1687 u32 tmp; 1688 1689 if (reset_mask == 0) 1690 return; 1691 1692 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask); 1693 1694 r600_print_gpu_status_regs(rdev); 1695 1696 /* Disable CP parsing/prefetching */ 1697 if (rdev->family >= CHIP_RV770) 1698 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1)); 1699 else 1700 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); 1701 1702 /* disable the RLC */ 1703 WREG32(RLC_CNTL, 0); 1704 1705 if (reset_mask & RADEON_RESET_DMA) { 1706 /* Disable DMA */ 1707 tmp = RREG32(DMA_RB_CNTL); 1708 tmp &= ~DMA_RB_ENABLE; 1709 WREG32(DMA_RB_CNTL, tmp); 1710 } 1711 1712 mdelay(50); 1713 1714 rv515_mc_stop(rdev, &save); 1715 if (r600_mc_wait_for_idle(rdev)) { 1716 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1717 } 1718 1719 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) { 1720 if (rdev->family >= CHIP_RV770) 1721 grbm_soft_reset |= S_008020_SOFT_RESET_DB(1) | 1722 S_008020_SOFT_RESET_CB(1) | 1723 S_008020_SOFT_RESET_PA(1) | 1724 S_008020_SOFT_RESET_SC(1) | 1725 S_008020_SOFT_RESET_SPI(1) | 1726 S_008020_SOFT_RESET_SX(1) | 1727 S_008020_SOFT_RESET_SH(1) | 1728 S_008020_SOFT_RESET_TC(1) | 1729 S_008020_SOFT_RESET_TA(1) | 1730 S_008020_SOFT_RESET_VC(1) | 1731 S_008020_SOFT_RESET_VGT(1); 1732 else 1733 grbm_soft_reset |= S_008020_SOFT_RESET_CR(1) | 1734 S_008020_SOFT_RESET_DB(1) | 1735 S_008020_SOFT_RESET_CB(1) | 1736 S_008020_SOFT_RESET_PA(1) | 1737 S_008020_SOFT_RESET_SC(1) | 1738 S_008020_SOFT_RESET_SMX(1) | 1739 S_008020_SOFT_RESET_SPI(1) | 1740 S_008020_SOFT_RESET_SX(1) | 1741 S_008020_SOFT_RESET_SH(1) | 1742 S_008020_SOFT_RESET_TC(1) | 1743 S_008020_SOFT_RESET_TA(1) | 1744 S_008020_SOFT_RESET_VC(1) | 1745 S_008020_SOFT_RESET_VGT(1); 1746 } 1747 1748 if (reset_mask & RADEON_RESET_CP) { 1749 grbm_soft_reset |= S_008020_SOFT_RESET_CP(1) | 1750 S_008020_SOFT_RESET_VGT(1); 1751 1752 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1); 1753 } 1754 1755 if (reset_mask & RADEON_RESET_DMA) { 1756 if (rdev->family >= CHIP_RV770) 1757 srbm_soft_reset |= RV770_SOFT_RESET_DMA; 1758 else 1759 srbm_soft_reset |= SOFT_RESET_DMA; 1760 } 1761 1762 if (reset_mask & RADEON_RESET_RLC) 1763 srbm_soft_reset |= S_000E60_SOFT_RESET_RLC(1); 1764 1765 if (reset_mask & RADEON_RESET_SEM) 1766 srbm_soft_reset |= S_000E60_SOFT_RESET_SEM(1); 1767 1768 if (reset_mask & RADEON_RESET_IH) 1769 srbm_soft_reset |= S_000E60_SOFT_RESET_IH(1); 1770 1771 if (reset_mask & RADEON_RESET_GRBM) 1772 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1); 1773 1774 if (!(rdev->flags & RADEON_IS_IGP)) { 1775 if (reset_mask & RADEON_RESET_MC) 1776 srbm_soft_reset |= S_000E60_SOFT_RESET_MC(1); 1777 } 1778 1779 if (reset_mask & RADEON_RESET_VMC) 1780 srbm_soft_reset |= S_000E60_SOFT_RESET_VMC(1); 1781 1782 if (grbm_soft_reset) { 1783 tmp = RREG32(R_008020_GRBM_SOFT_RESET); 1784 tmp |= grbm_soft_reset; 1785 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp); 1786 WREG32(R_008020_GRBM_SOFT_RESET, tmp); 1787 tmp = RREG32(R_008020_GRBM_SOFT_RESET); 1788 1789 udelay(50); 1790 1791 tmp &= ~grbm_soft_reset; 1792 WREG32(R_008020_GRBM_SOFT_RESET, tmp); 1793 tmp = RREG32(R_008020_GRBM_SOFT_RESET); 1794 } 1795 1796 if (srbm_soft_reset) { 1797 tmp = RREG32(SRBM_SOFT_RESET); 1798 tmp |= srbm_soft_reset; 1799 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1800 WREG32(SRBM_SOFT_RESET, tmp); 1801 tmp = RREG32(SRBM_SOFT_RESET); 1802 1803 udelay(50); 1804 1805 tmp &= ~srbm_soft_reset; 1806 WREG32(SRBM_SOFT_RESET, tmp); 1807 tmp = RREG32(SRBM_SOFT_RESET); 1808 } 1809 1810 /* Wait a little for things to settle down */ 1811 mdelay(1); 1812 1813 rv515_mc_resume(rdev, &save); 1814 udelay(50); 1815 1816 r600_print_gpu_status_regs(rdev); 1817 } 1818 1819 static void r600_gpu_pci_config_reset(struct radeon_device *rdev) 1820 { 1821 struct rv515_mc_save save; 1822 u32 tmp, i; 1823 1824 dev_info(rdev->dev, "GPU pci config reset\n"); 1825 1826 /* disable dpm? */ 1827 1828 /* Disable CP parsing/prefetching */ 1829 if (rdev->family >= CHIP_RV770) 1830 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1)); 1831 else 1832 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); 1833 1834 /* disable the RLC */ 1835 WREG32(RLC_CNTL, 0); 1836 1837 /* Disable DMA */ 1838 tmp = RREG32(DMA_RB_CNTL); 1839 tmp &= ~DMA_RB_ENABLE; 1840 WREG32(DMA_RB_CNTL, tmp); 1841 1842 mdelay(50); 1843 1844 /* set mclk/sclk to bypass */ 1845 if (rdev->family >= CHIP_RV770) 1846 rv770_set_clk_bypass_mode(rdev); 1847 /* disable BM */ 1848 pci_clear_master(rdev->pdev); 1849 /* disable mem access */ 1850 rv515_mc_stop(rdev, &save); 1851 if (r600_mc_wait_for_idle(rdev)) { 1852 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1853 } 1854 1855 /* BIF reset workaround. Not sure if this is needed on 6xx */ 1856 tmp = RREG32(BUS_CNTL); 1857 tmp |= VGA_COHE_SPEC_TIMER_DIS; 1858 WREG32(BUS_CNTL, tmp); 1859 1860 tmp = RREG32(BIF_SCRATCH0); 1861 1862 /* reset */ 1863 radeon_pci_config_reset(rdev); 1864 mdelay(1); 1865 1866 /* BIF reset workaround. Not sure if this is needed on 6xx */ 1867 tmp = SOFT_RESET_BIF; 1868 WREG32(SRBM_SOFT_RESET, tmp); 1869 mdelay(1); 1870 WREG32(SRBM_SOFT_RESET, 0); 1871 1872 /* wait for asic to come out of reset */ 1873 for (i = 0; i < rdev->usec_timeout; i++) { 1874 if (RREG32(CONFIG_MEMSIZE) != 0xffffffff) 1875 break; 1876 udelay(1); 1877 } 1878 } 1879 1880 int r600_asic_reset(struct radeon_device *rdev, bool hard) 1881 { 1882 u32 reset_mask; 1883 1884 if (hard) { 1885 r600_gpu_pci_config_reset(rdev); 1886 return 0; 1887 } 1888 1889 reset_mask = r600_gpu_check_soft_reset(rdev); 1890 1891 if (reset_mask) 1892 r600_set_bios_scratch_engine_hung(rdev, true); 1893 1894 /* try soft reset */ 1895 r600_gpu_soft_reset(rdev, reset_mask); 1896 1897 reset_mask = r600_gpu_check_soft_reset(rdev); 1898 1899 /* try pci config reset */ 1900 if (reset_mask && radeon_hard_reset) 1901 r600_gpu_pci_config_reset(rdev); 1902 1903 reset_mask = r600_gpu_check_soft_reset(rdev); 1904 1905 if (!reset_mask) 1906 r600_set_bios_scratch_engine_hung(rdev, false); 1907 1908 return 0; 1909 } 1910 1911 /** 1912 * r600_gfx_is_lockup - Check if the GFX engine is locked up 1913 * 1914 * @rdev: radeon_device pointer 1915 * @ring: radeon_ring structure holding ring information 1916 * 1917 * Check if the GFX engine is locked up. 1918 * Returns true if the engine appears to be locked up, false if not. 1919 */ 1920 bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 1921 { 1922 u32 reset_mask = r600_gpu_check_soft_reset(rdev); 1923 1924 if (!(reset_mask & (RADEON_RESET_GFX | 1925 RADEON_RESET_COMPUTE | 1926 RADEON_RESET_CP))) { 1927 radeon_ring_lockup_update(rdev, ring); 1928 return false; 1929 } 1930 return radeon_ring_test_lockup(rdev, ring); 1931 } 1932 1933 u32 r6xx_remap_render_backend(struct radeon_device *rdev, 1934 u32 tiling_pipe_num, 1935 u32 max_rb_num, 1936 u32 total_max_rb_num, 1937 u32 disabled_rb_mask) 1938 { 1939 u32 rendering_pipe_num, rb_num_width, req_rb_num; 1940 u32 pipe_rb_ratio, pipe_rb_remain, tmp; 1941 u32 data = 0, mask = 1 << (max_rb_num - 1); 1942 unsigned i, j; 1943 1944 /* mask out the RBs that don't exist on that asic */ 1945 tmp = disabled_rb_mask | ((0xff << max_rb_num) & 0xff); 1946 /* make sure at least one RB is available */ 1947 if ((tmp & 0xff) != 0xff) 1948 disabled_rb_mask = tmp; 1949 1950 rendering_pipe_num = 1 << tiling_pipe_num; 1951 req_rb_num = total_max_rb_num - r600_count_pipe_bits(disabled_rb_mask); 1952 BUG_ON(rendering_pipe_num < req_rb_num); 1953 1954 pipe_rb_ratio = rendering_pipe_num / req_rb_num; 1955 pipe_rb_remain = rendering_pipe_num - pipe_rb_ratio * req_rb_num; 1956 1957 if (rdev->family <= CHIP_RV740) { 1958 /* r6xx/r7xx */ 1959 rb_num_width = 2; 1960 } else { 1961 /* eg+ */ 1962 rb_num_width = 4; 1963 } 1964 1965 for (i = 0; i < max_rb_num; i++) { 1966 if (!(mask & disabled_rb_mask)) { 1967 for (j = 0; j < pipe_rb_ratio; j++) { 1968 data <<= rb_num_width; 1969 data |= max_rb_num - i - 1; 1970 } 1971 if (pipe_rb_remain) { 1972 data <<= rb_num_width; 1973 data |= max_rb_num - i - 1; 1974 pipe_rb_remain--; 1975 } 1976 } 1977 mask >>= 1; 1978 } 1979 1980 return data; 1981 } 1982 1983 int r600_count_pipe_bits(uint32_t val) 1984 { 1985 return hweight32(val); 1986 } 1987 1988 static void r600_gpu_init(struct radeon_device *rdev) 1989 { 1990 u32 tiling_config; 1991 u32 ramcfg; 1992 u32 cc_gc_shader_pipe_config; 1993 u32 tmp; 1994 int i, j; 1995 u32 sq_config; 1996 u32 sq_gpr_resource_mgmt_1 = 0; 1997 u32 sq_gpr_resource_mgmt_2 = 0; 1998 u32 sq_thread_resource_mgmt = 0; 1999 u32 sq_stack_resource_mgmt_1 = 0; 2000 u32 sq_stack_resource_mgmt_2 = 0; 2001 u32 disabled_rb_mask; 2002 2003 rdev->config.r600.tiling_group_size = 256; 2004 switch (rdev->family) { 2005 case CHIP_R600: 2006 rdev->config.r600.max_pipes = 4; 2007 rdev->config.r600.max_tile_pipes = 8; 2008 rdev->config.r600.max_simds = 4; 2009 rdev->config.r600.max_backends = 4; 2010 rdev->config.r600.max_gprs = 256; 2011 rdev->config.r600.max_threads = 192; 2012 rdev->config.r600.max_stack_entries = 256; 2013 rdev->config.r600.max_hw_contexts = 8; 2014 rdev->config.r600.max_gs_threads = 16; 2015 rdev->config.r600.sx_max_export_size = 128; 2016 rdev->config.r600.sx_max_export_pos_size = 16; 2017 rdev->config.r600.sx_max_export_smx_size = 128; 2018 rdev->config.r600.sq_num_cf_insts = 2; 2019 break; 2020 case CHIP_RV630: 2021 case CHIP_RV635: 2022 rdev->config.r600.max_pipes = 2; 2023 rdev->config.r600.max_tile_pipes = 2; 2024 rdev->config.r600.max_simds = 3; 2025 rdev->config.r600.max_backends = 1; 2026 rdev->config.r600.max_gprs = 128; 2027 rdev->config.r600.max_threads = 192; 2028 rdev->config.r600.max_stack_entries = 128; 2029 rdev->config.r600.max_hw_contexts = 8; 2030 rdev->config.r600.max_gs_threads = 4; 2031 rdev->config.r600.sx_max_export_size = 128; 2032 rdev->config.r600.sx_max_export_pos_size = 16; 2033 rdev->config.r600.sx_max_export_smx_size = 128; 2034 rdev->config.r600.sq_num_cf_insts = 2; 2035 break; 2036 case CHIP_RV610: 2037 case CHIP_RV620: 2038 case CHIP_RS780: 2039 case CHIP_RS880: 2040 rdev->config.r600.max_pipes = 1; 2041 rdev->config.r600.max_tile_pipes = 1; 2042 rdev->config.r600.max_simds = 2; 2043 rdev->config.r600.max_backends = 1; 2044 rdev->config.r600.max_gprs = 128; 2045 rdev->config.r600.max_threads = 192; 2046 rdev->config.r600.max_stack_entries = 128; 2047 rdev->config.r600.max_hw_contexts = 4; 2048 rdev->config.r600.max_gs_threads = 4; 2049 rdev->config.r600.sx_max_export_size = 128; 2050 rdev->config.r600.sx_max_export_pos_size = 16; 2051 rdev->config.r600.sx_max_export_smx_size = 128; 2052 rdev->config.r600.sq_num_cf_insts = 1; 2053 break; 2054 case CHIP_RV670: 2055 rdev->config.r600.max_pipes = 4; 2056 rdev->config.r600.max_tile_pipes = 4; 2057 rdev->config.r600.max_simds = 4; 2058 rdev->config.r600.max_backends = 4; 2059 rdev->config.r600.max_gprs = 192; 2060 rdev->config.r600.max_threads = 192; 2061 rdev->config.r600.max_stack_entries = 256; 2062 rdev->config.r600.max_hw_contexts = 8; 2063 rdev->config.r600.max_gs_threads = 16; 2064 rdev->config.r600.sx_max_export_size = 128; 2065 rdev->config.r600.sx_max_export_pos_size = 16; 2066 rdev->config.r600.sx_max_export_smx_size = 128; 2067 rdev->config.r600.sq_num_cf_insts = 2; 2068 break; 2069 default: 2070 break; 2071 } 2072 2073 /* Initialize HDP */ 2074 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 2075 WREG32((0x2c14 + j), 0x00000000); 2076 WREG32((0x2c18 + j), 0x00000000); 2077 WREG32((0x2c1c + j), 0x00000000); 2078 WREG32((0x2c20 + j), 0x00000000); 2079 WREG32((0x2c24 + j), 0x00000000); 2080 } 2081 2082 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); 2083 2084 /* Setup tiling */ 2085 tiling_config = 0; 2086 ramcfg = RREG32(RAMCFG); 2087 switch (rdev->config.r600.max_tile_pipes) { 2088 case 1: 2089 tiling_config |= PIPE_TILING(0); 2090 break; 2091 case 2: 2092 tiling_config |= PIPE_TILING(1); 2093 break; 2094 case 4: 2095 tiling_config |= PIPE_TILING(2); 2096 break; 2097 case 8: 2098 tiling_config |= PIPE_TILING(3); 2099 break; 2100 default: 2101 break; 2102 } 2103 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes; 2104 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); 2105 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); 2106 tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT); 2107 2108 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT; 2109 if (tmp > 3) { 2110 tiling_config |= ROW_TILING(3); 2111 tiling_config |= SAMPLE_SPLIT(3); 2112 } else { 2113 tiling_config |= ROW_TILING(tmp); 2114 tiling_config |= SAMPLE_SPLIT(tmp); 2115 } 2116 tiling_config |= BANK_SWAPS(1); 2117 2118 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0x00ffff00; 2119 tmp = rdev->config.r600.max_simds - 2120 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R6XX_MAX_SIMDS_MASK); 2121 rdev->config.r600.active_simds = tmp; 2122 2123 disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R6XX_MAX_BACKENDS_MASK; 2124 tmp = 0; 2125 for (i = 0; i < rdev->config.r600.max_backends; i++) 2126 tmp |= (1 << i); 2127 /* if all the backends are disabled, fix it up here */ 2128 if ((disabled_rb_mask & tmp) == tmp) { 2129 for (i = 0; i < rdev->config.r600.max_backends; i++) 2130 disabled_rb_mask &= ~(1 << i); 2131 } 2132 tmp = (tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT; 2133 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends, 2134 R6XX_MAX_BACKENDS, disabled_rb_mask); 2135 tiling_config |= tmp << 16; 2136 rdev->config.r600.backend_map = tmp; 2137 2138 rdev->config.r600.tile_config = tiling_config; 2139 WREG32(GB_TILING_CONFIG, tiling_config); 2140 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff); 2141 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff); 2142 WREG32(DMA_TILING_CONFIG, tiling_config & 0xffff); 2143 2144 tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8); 2145 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK); 2146 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK); 2147 2148 /* Setup some CP states */ 2149 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b))); 2150 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40))); 2151 2152 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT | 2153 SYNC_WALKER | SYNC_ALIGNER)); 2154 /* Setup various GPU states */ 2155 if (rdev->family == CHIP_RV670) 2156 WREG32(ARB_GDEC_RD_CNTL, 0x00000021); 2157 2158 tmp = RREG32(SX_DEBUG_1); 2159 tmp |= SMX_EVENT_RELEASE; 2160 if ((rdev->family > CHIP_R600)) 2161 tmp |= ENABLE_NEW_SMX_ADDRESS; 2162 WREG32(SX_DEBUG_1, tmp); 2163 2164 if (((rdev->family) == CHIP_R600) || 2165 ((rdev->family) == CHIP_RV630) || 2166 ((rdev->family) == CHIP_RV610) || 2167 ((rdev->family) == CHIP_RV620) || 2168 ((rdev->family) == CHIP_RS780) || 2169 ((rdev->family) == CHIP_RS880)) { 2170 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE); 2171 } else { 2172 WREG32(DB_DEBUG, 0); 2173 } 2174 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) | 2175 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4))); 2176 2177 WREG32(PA_SC_MULTI_CHIP_CNTL, 0); 2178 WREG32(VGT_NUM_INSTANCES, 0); 2179 2180 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0)); 2181 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0)); 2182 2183 tmp = RREG32(SQ_MS_FIFO_SIZES); 2184 if (((rdev->family) == CHIP_RV610) || 2185 ((rdev->family) == CHIP_RV620) || 2186 ((rdev->family) == CHIP_RS780) || 2187 ((rdev->family) == CHIP_RS880)) { 2188 tmp = (CACHE_FIFO_SIZE(0xa) | 2189 FETCH_FIFO_HIWATER(0xa) | 2190 DONE_FIFO_HIWATER(0xe0) | 2191 ALU_UPDATE_FIFO_HIWATER(0x8)); 2192 } else if (((rdev->family) == CHIP_R600) || 2193 ((rdev->family) == CHIP_RV630)) { 2194 tmp &= ~DONE_FIFO_HIWATER(0xff); 2195 tmp |= DONE_FIFO_HIWATER(0x4); 2196 } 2197 WREG32(SQ_MS_FIFO_SIZES, tmp); 2198 2199 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT 2200 * should be adjusted as needed by the 2D/3D drivers. This just sets default values 2201 */ 2202 sq_config = RREG32(SQ_CONFIG); 2203 sq_config &= ~(PS_PRIO(3) | 2204 VS_PRIO(3) | 2205 GS_PRIO(3) | 2206 ES_PRIO(3)); 2207 sq_config |= (DX9_CONSTS | 2208 VC_ENABLE | 2209 PS_PRIO(0) | 2210 VS_PRIO(1) | 2211 GS_PRIO(2) | 2212 ES_PRIO(3)); 2213 2214 if ((rdev->family) == CHIP_R600) { 2215 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) | 2216 NUM_VS_GPRS(124) | 2217 NUM_CLAUSE_TEMP_GPRS(4)); 2218 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) | 2219 NUM_ES_GPRS(0)); 2220 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) | 2221 NUM_VS_THREADS(48) | 2222 NUM_GS_THREADS(4) | 2223 NUM_ES_THREADS(4)); 2224 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) | 2225 NUM_VS_STACK_ENTRIES(128)); 2226 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) | 2227 NUM_ES_STACK_ENTRIES(0)); 2228 } else if (((rdev->family) == CHIP_RV610) || 2229 ((rdev->family) == CHIP_RV620) || 2230 ((rdev->family) == CHIP_RS780) || 2231 ((rdev->family) == CHIP_RS880)) { 2232 /* no vertex cache */ 2233 sq_config &= ~VC_ENABLE; 2234 2235 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | 2236 NUM_VS_GPRS(44) | 2237 NUM_CLAUSE_TEMP_GPRS(2)); 2238 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | 2239 NUM_ES_GPRS(17)); 2240 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | 2241 NUM_VS_THREADS(78) | 2242 NUM_GS_THREADS(4) | 2243 NUM_ES_THREADS(31)); 2244 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | 2245 NUM_VS_STACK_ENTRIES(40)); 2246 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | 2247 NUM_ES_STACK_ENTRIES(16)); 2248 } else if (((rdev->family) == CHIP_RV630) || 2249 ((rdev->family) == CHIP_RV635)) { 2250 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | 2251 NUM_VS_GPRS(44) | 2252 NUM_CLAUSE_TEMP_GPRS(2)); 2253 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) | 2254 NUM_ES_GPRS(18)); 2255 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | 2256 NUM_VS_THREADS(78) | 2257 NUM_GS_THREADS(4) | 2258 NUM_ES_THREADS(31)); 2259 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | 2260 NUM_VS_STACK_ENTRIES(40)); 2261 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | 2262 NUM_ES_STACK_ENTRIES(16)); 2263 } else if ((rdev->family) == CHIP_RV670) { 2264 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | 2265 NUM_VS_GPRS(44) | 2266 NUM_CLAUSE_TEMP_GPRS(2)); 2267 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | 2268 NUM_ES_GPRS(17)); 2269 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | 2270 NUM_VS_THREADS(78) | 2271 NUM_GS_THREADS(4) | 2272 NUM_ES_THREADS(31)); 2273 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) | 2274 NUM_VS_STACK_ENTRIES(64)); 2275 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) | 2276 NUM_ES_STACK_ENTRIES(64)); 2277 } 2278 2279 WREG32(SQ_CONFIG, sq_config); 2280 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1); 2281 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2); 2282 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); 2283 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1); 2284 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2); 2285 2286 if (((rdev->family) == CHIP_RV610) || 2287 ((rdev->family) == CHIP_RV620) || 2288 ((rdev->family) == CHIP_RS780) || 2289 ((rdev->family) == CHIP_RS880)) { 2290 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY)); 2291 } else { 2292 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC)); 2293 } 2294 2295 /* More default values. 2D/3D driver should adjust as needed */ 2296 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) | 2297 S1_X(0x4) | S1_Y(0xc))); 2298 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) | 2299 S1_X(0x2) | S1_Y(0x2) | 2300 S2_X(0xa) | S2_Y(0x6) | 2301 S3_X(0x6) | S3_Y(0xa))); 2302 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) | 2303 S1_X(0x4) | S1_Y(0xc) | 2304 S2_X(0x1) | S2_Y(0x6) | 2305 S3_X(0xa) | S3_Y(0xe))); 2306 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) | 2307 S5_X(0x0) | S5_Y(0x0) | 2308 S6_X(0xb) | S6_Y(0x4) | 2309 S7_X(0x7) | S7_Y(0x8))); 2310 2311 WREG32(VGT_STRMOUT_EN, 0); 2312 tmp = rdev->config.r600.max_pipes * 16; 2313 switch (rdev->family) { 2314 case CHIP_RV610: 2315 case CHIP_RV620: 2316 case CHIP_RS780: 2317 case CHIP_RS880: 2318 tmp += 32; 2319 break; 2320 case CHIP_RV670: 2321 tmp += 128; 2322 break; 2323 default: 2324 break; 2325 } 2326 if (tmp > 256) { 2327 tmp = 256; 2328 } 2329 WREG32(VGT_ES_PER_GS, 128); 2330 WREG32(VGT_GS_PER_ES, tmp); 2331 WREG32(VGT_GS_PER_VS, 2); 2332 WREG32(VGT_GS_VERTEX_REUSE, 16); 2333 2334 /* more default values. 2D/3D driver should adjust as needed */ 2335 WREG32(PA_SC_LINE_STIPPLE_STATE, 0); 2336 WREG32(VGT_STRMOUT_EN, 0); 2337 WREG32(SX_MISC, 0); 2338 WREG32(PA_SC_MODE_CNTL, 0); 2339 WREG32(PA_SC_AA_CONFIG, 0); 2340 WREG32(PA_SC_LINE_STIPPLE, 0); 2341 WREG32(SPI_INPUT_Z, 0); 2342 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2)); 2343 WREG32(CB_COLOR7_FRAG, 0); 2344 2345 /* Clear render buffer base addresses */ 2346 WREG32(CB_COLOR0_BASE, 0); 2347 WREG32(CB_COLOR1_BASE, 0); 2348 WREG32(CB_COLOR2_BASE, 0); 2349 WREG32(CB_COLOR3_BASE, 0); 2350 WREG32(CB_COLOR4_BASE, 0); 2351 WREG32(CB_COLOR5_BASE, 0); 2352 WREG32(CB_COLOR6_BASE, 0); 2353 WREG32(CB_COLOR7_BASE, 0); 2354 WREG32(CB_COLOR7_FRAG, 0); 2355 2356 switch (rdev->family) { 2357 case CHIP_RV610: 2358 case CHIP_RV620: 2359 case CHIP_RS780: 2360 case CHIP_RS880: 2361 tmp = TC_L2_SIZE(8); 2362 break; 2363 case CHIP_RV630: 2364 case CHIP_RV635: 2365 tmp = TC_L2_SIZE(4); 2366 break; 2367 case CHIP_R600: 2368 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT; 2369 break; 2370 default: 2371 tmp = TC_L2_SIZE(0); 2372 break; 2373 } 2374 WREG32(TC_CNTL, tmp); 2375 2376 tmp = RREG32(HDP_HOST_PATH_CNTL); 2377 WREG32(HDP_HOST_PATH_CNTL, tmp); 2378 2379 tmp = RREG32(ARB_POP); 2380 tmp |= ENABLE_TC128; 2381 WREG32(ARB_POP, tmp); 2382 2383 WREG32(PA_SC_MULTI_CHIP_CNTL, 0); 2384 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | 2385 NUM_CLIP_SEQ(3))); 2386 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095)); 2387 WREG32(VC_ENHANCE, 0); 2388 } 2389 2390 2391 /* 2392 * Indirect registers accessor 2393 */ 2394 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg) 2395 { 2396 unsigned long flags; 2397 u32 r; 2398 2399 spin_lock_irqsave(&rdev->pciep_idx_lock, flags); 2400 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); 2401 (void)RREG32(PCIE_PORT_INDEX); 2402 r = RREG32(PCIE_PORT_DATA); 2403 spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags); 2404 return r; 2405 } 2406 2407 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2408 { 2409 unsigned long flags; 2410 2411 spin_lock_irqsave(&rdev->pciep_idx_lock, flags); 2412 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); 2413 (void)RREG32(PCIE_PORT_INDEX); 2414 WREG32(PCIE_PORT_DATA, (v)); 2415 (void)RREG32(PCIE_PORT_DATA); 2416 spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags); 2417 } 2418 2419 /* 2420 * CP & Ring 2421 */ 2422 void r600_cp_stop(struct radeon_device *rdev) 2423 { 2424 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX) 2425 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 2426 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); 2427 WREG32(SCRATCH_UMSK, 0); 2428 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 2429 } 2430 2431 int r600_init_microcode(struct radeon_device *rdev) 2432 { 2433 const char *chip_name; 2434 const char *rlc_chip_name; 2435 const char *smc_chip_name = "RV770"; 2436 size_t pfp_req_size, me_req_size, rlc_req_size, smc_req_size = 0; 2437 char fw_name[30]; 2438 int err; 2439 2440 DRM_DEBUG("\n"); 2441 2442 switch (rdev->family) { 2443 case CHIP_R600: 2444 chip_name = "R600"; 2445 rlc_chip_name = "R600"; 2446 break; 2447 case CHIP_RV610: 2448 chip_name = "RV610"; 2449 rlc_chip_name = "R600"; 2450 break; 2451 case CHIP_RV630: 2452 chip_name = "RV630"; 2453 rlc_chip_name = "R600"; 2454 break; 2455 case CHIP_RV620: 2456 chip_name = "RV620"; 2457 rlc_chip_name = "R600"; 2458 break; 2459 case CHIP_RV635: 2460 chip_name = "RV635"; 2461 rlc_chip_name = "R600"; 2462 break; 2463 case CHIP_RV670: 2464 chip_name = "RV670"; 2465 rlc_chip_name = "R600"; 2466 break; 2467 case CHIP_RS780: 2468 case CHIP_RS880: 2469 chip_name = "RS780"; 2470 rlc_chip_name = "R600"; 2471 break; 2472 case CHIP_RV770: 2473 chip_name = "RV770"; 2474 rlc_chip_name = "R700"; 2475 smc_chip_name = "RV770"; 2476 smc_req_size = ALIGN(RV770_SMC_UCODE_SIZE, 4); 2477 break; 2478 case CHIP_RV730: 2479 chip_name = "RV730"; 2480 rlc_chip_name = "R700"; 2481 smc_chip_name = "RV730"; 2482 smc_req_size = ALIGN(RV730_SMC_UCODE_SIZE, 4); 2483 break; 2484 case CHIP_RV710: 2485 chip_name = "RV710"; 2486 rlc_chip_name = "R700"; 2487 smc_chip_name = "RV710"; 2488 smc_req_size = ALIGN(RV710_SMC_UCODE_SIZE, 4); 2489 break; 2490 case CHIP_RV740: 2491 chip_name = "RV730"; 2492 rlc_chip_name = "R700"; 2493 smc_chip_name = "RV740"; 2494 smc_req_size = ALIGN(RV740_SMC_UCODE_SIZE, 4); 2495 break; 2496 case CHIP_CEDAR: 2497 chip_name = "CEDAR"; 2498 rlc_chip_name = "CEDAR"; 2499 smc_chip_name = "CEDAR"; 2500 smc_req_size = ALIGN(CEDAR_SMC_UCODE_SIZE, 4); 2501 break; 2502 case CHIP_REDWOOD: 2503 chip_name = "REDWOOD"; 2504 rlc_chip_name = "REDWOOD"; 2505 smc_chip_name = "REDWOOD"; 2506 smc_req_size = ALIGN(REDWOOD_SMC_UCODE_SIZE, 4); 2507 break; 2508 case CHIP_JUNIPER: 2509 chip_name = "JUNIPER"; 2510 rlc_chip_name = "JUNIPER"; 2511 smc_chip_name = "JUNIPER"; 2512 smc_req_size = ALIGN(JUNIPER_SMC_UCODE_SIZE, 4); 2513 break; 2514 case CHIP_CYPRESS: 2515 case CHIP_HEMLOCK: 2516 chip_name = "CYPRESS"; 2517 rlc_chip_name = "CYPRESS"; 2518 smc_chip_name = "CYPRESS"; 2519 smc_req_size = ALIGN(CYPRESS_SMC_UCODE_SIZE, 4); 2520 break; 2521 case CHIP_PALM: 2522 chip_name = "PALM"; 2523 rlc_chip_name = "SUMO"; 2524 break; 2525 case CHIP_SUMO: 2526 chip_name = "SUMO"; 2527 rlc_chip_name = "SUMO"; 2528 break; 2529 case CHIP_SUMO2: 2530 chip_name = "SUMO2"; 2531 rlc_chip_name = "SUMO"; 2532 break; 2533 default: BUG(); 2534 } 2535 2536 if (rdev->family >= CHIP_CEDAR) { 2537 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4; 2538 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4; 2539 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4; 2540 } else if (rdev->family >= CHIP_RV770) { 2541 pfp_req_size = R700_PFP_UCODE_SIZE * 4; 2542 me_req_size = R700_PM4_UCODE_SIZE * 4; 2543 rlc_req_size = R700_RLC_UCODE_SIZE * 4; 2544 } else { 2545 pfp_req_size = R600_PFP_UCODE_SIZE * 4; 2546 me_req_size = R600_PM4_UCODE_SIZE * 12; 2547 rlc_req_size = R600_RLC_UCODE_SIZE * 4; 2548 } 2549 2550 DRM_INFO("Loading %s Microcode\n", chip_name); 2551 2552 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name); 2553 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev); 2554 if (err) 2555 goto out; 2556 if (rdev->pfp_fw->size != pfp_req_size) { 2557 pr_err("r600_cp: Bogus length %zu in firmware \"%s\"\n", 2558 rdev->pfp_fw->size, fw_name); 2559 err = -EINVAL; 2560 goto out; 2561 } 2562 2563 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name); 2564 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev); 2565 if (err) 2566 goto out; 2567 if (rdev->me_fw->size != me_req_size) { 2568 pr_err("r600_cp: Bogus length %zu in firmware \"%s\"\n", 2569 rdev->me_fw->size, fw_name); 2570 err = -EINVAL; 2571 goto out; 2572 } 2573 2574 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name); 2575 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev); 2576 if (err) 2577 goto out; 2578 if (rdev->rlc_fw->size != rlc_req_size) { 2579 pr_err("r600_rlc: Bogus length %zu in firmware \"%s\"\n", 2580 rdev->rlc_fw->size, fw_name); 2581 err = -EINVAL; 2582 goto out; 2583 } 2584 2585 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_HEMLOCK)) { 2586 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", smc_chip_name); 2587 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev); 2588 if (err) { 2589 pr_err("smc: error loading firmware \"%s\"\n", fw_name); 2590 release_firmware(rdev->smc_fw); 2591 rdev->smc_fw = NULL; 2592 err = 0; 2593 } else if (rdev->smc_fw->size != smc_req_size) { 2594 pr_err("smc: Bogus length %zu in firmware \"%s\"\n", 2595 rdev->smc_fw->size, fw_name); 2596 err = -EINVAL; 2597 } 2598 } 2599 2600 out: 2601 if (err) { 2602 if (err != -EINVAL) 2603 pr_err("r600_cp: Failed to load firmware \"%s\"\n", 2604 fw_name); 2605 release_firmware(rdev->pfp_fw); 2606 rdev->pfp_fw = NULL; 2607 release_firmware(rdev->me_fw); 2608 rdev->me_fw = NULL; 2609 release_firmware(rdev->rlc_fw); 2610 rdev->rlc_fw = NULL; 2611 release_firmware(rdev->smc_fw); 2612 rdev->smc_fw = NULL; 2613 } 2614 return err; 2615 } 2616 2617 u32 r600_gfx_get_rptr(struct radeon_device *rdev, 2618 struct radeon_ring *ring) 2619 { 2620 u32 rptr; 2621 2622 if (rdev->wb.enabled) 2623 rptr = rdev->wb.wb[ring->rptr_offs/4]; 2624 else 2625 rptr = RREG32(R600_CP_RB_RPTR); 2626 2627 return rptr; 2628 } 2629 2630 u32 r600_gfx_get_wptr(struct radeon_device *rdev, 2631 struct radeon_ring *ring) 2632 { 2633 return RREG32(R600_CP_RB_WPTR); 2634 } 2635 2636 void r600_gfx_set_wptr(struct radeon_device *rdev, 2637 struct radeon_ring *ring) 2638 { 2639 WREG32(R600_CP_RB_WPTR, ring->wptr); 2640 (void)RREG32(R600_CP_RB_WPTR); 2641 } 2642 2643 static int r600_cp_load_microcode(struct radeon_device *rdev) 2644 { 2645 const __be32 *fw_data; 2646 int i; 2647 2648 if (!rdev->me_fw || !rdev->pfp_fw) 2649 return -EINVAL; 2650 2651 r600_cp_stop(rdev); 2652 2653 WREG32(CP_RB_CNTL, 2654 #ifdef __BIG_ENDIAN 2655 BUF_SWAP_32BIT | 2656 #endif 2657 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); 2658 2659 /* Reset cp */ 2660 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); 2661 RREG32(GRBM_SOFT_RESET); 2662 mdelay(15); 2663 WREG32(GRBM_SOFT_RESET, 0); 2664 2665 WREG32(CP_ME_RAM_WADDR, 0); 2666 2667 fw_data = (const __be32 *)rdev->me_fw->data; 2668 WREG32(CP_ME_RAM_WADDR, 0); 2669 for (i = 0; i < R600_PM4_UCODE_SIZE * 3; i++) 2670 WREG32(CP_ME_RAM_DATA, 2671 be32_to_cpup(fw_data++)); 2672 2673 fw_data = (const __be32 *)rdev->pfp_fw->data; 2674 WREG32(CP_PFP_UCODE_ADDR, 0); 2675 for (i = 0; i < R600_PFP_UCODE_SIZE; i++) 2676 WREG32(CP_PFP_UCODE_DATA, 2677 be32_to_cpup(fw_data++)); 2678 2679 WREG32(CP_PFP_UCODE_ADDR, 0); 2680 WREG32(CP_ME_RAM_WADDR, 0); 2681 WREG32(CP_ME_RAM_RADDR, 0); 2682 return 0; 2683 } 2684 2685 int r600_cp_start(struct radeon_device *rdev) 2686 { 2687 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2688 int r; 2689 uint32_t cp_me; 2690 2691 r = radeon_ring_lock(rdev, ring, 7); 2692 if (r) { 2693 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 2694 return r; 2695 } 2696 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); 2697 radeon_ring_write(ring, 0x1); 2698 if (rdev->family >= CHIP_RV770) { 2699 radeon_ring_write(ring, 0x0); 2700 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1); 2701 } else { 2702 radeon_ring_write(ring, 0x3); 2703 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1); 2704 } 2705 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); 2706 radeon_ring_write(ring, 0); 2707 radeon_ring_write(ring, 0); 2708 radeon_ring_unlock_commit(rdev, ring, false); 2709 2710 cp_me = 0xff; 2711 WREG32(R_0086D8_CP_ME_CNTL, cp_me); 2712 return 0; 2713 } 2714 2715 int r600_cp_resume(struct radeon_device *rdev) 2716 { 2717 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2718 u32 tmp; 2719 u32 rb_bufsz; 2720 int r; 2721 2722 /* Reset cp */ 2723 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); 2724 RREG32(GRBM_SOFT_RESET); 2725 mdelay(15); 2726 WREG32(GRBM_SOFT_RESET, 0); 2727 2728 /* Set ring buffer size */ 2729 rb_bufsz = order_base_2(ring->ring_size / 8); 2730 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2731 #ifdef __BIG_ENDIAN 2732 tmp |= BUF_SWAP_32BIT; 2733 #endif 2734 WREG32(CP_RB_CNTL, tmp); 2735 WREG32(CP_SEM_WAIT_TIMER, 0x0); 2736 2737 /* Set the write pointer delay */ 2738 WREG32(CP_RB_WPTR_DELAY, 0); 2739 2740 /* Initialize the ring buffer's read and write pointers */ 2741 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); 2742 WREG32(CP_RB_RPTR_WR, 0); 2743 ring->wptr = 0; 2744 WREG32(CP_RB_WPTR, ring->wptr); 2745 2746 /* set the wb address whether it's enabled or not */ 2747 WREG32(CP_RB_RPTR_ADDR, 2748 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC)); 2749 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); 2750 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); 2751 2752 if (rdev->wb.enabled) 2753 WREG32(SCRATCH_UMSK, 0xff); 2754 else { 2755 tmp |= RB_NO_UPDATE; 2756 WREG32(SCRATCH_UMSK, 0); 2757 } 2758 2759 mdelay(1); 2760 WREG32(CP_RB_CNTL, tmp); 2761 2762 WREG32(CP_RB_BASE, ring->gpu_addr >> 8); 2763 WREG32(CP_DEBUG, (1 << 27) | (1 << 28)); 2764 2765 r600_cp_start(rdev); 2766 ring->ready = true; 2767 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring); 2768 if (r) { 2769 ring->ready = false; 2770 return r; 2771 } 2772 2773 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX) 2774 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); 2775 2776 return 0; 2777 } 2778 2779 void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size) 2780 { 2781 u32 rb_bufsz; 2782 int r; 2783 2784 /* Align ring size */ 2785 rb_bufsz = order_base_2(ring_size / 8); 2786 ring_size = (1 << (rb_bufsz + 1)) * 4; 2787 ring->ring_size = ring_size; 2788 ring->align_mask = 16 - 1; 2789 2790 if (radeon_ring_supports_scratch_reg(rdev, ring)) { 2791 r = radeon_scratch_get(rdev, &ring->rptr_save_reg); 2792 if (r) { 2793 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r); 2794 ring->rptr_save_reg = 0; 2795 } 2796 } 2797 } 2798 2799 void r600_cp_fini(struct radeon_device *rdev) 2800 { 2801 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2802 r600_cp_stop(rdev); 2803 radeon_ring_fini(rdev, ring); 2804 radeon_scratch_free(rdev, ring->rptr_save_reg); 2805 } 2806 2807 /* 2808 * GPU scratch registers helpers function. 2809 */ 2810 void r600_scratch_init(struct radeon_device *rdev) 2811 { 2812 int i; 2813 2814 rdev->scratch.num_reg = 7; 2815 rdev->scratch.reg_base = SCRATCH_REG0; 2816 for (i = 0; i < rdev->scratch.num_reg; i++) { 2817 rdev->scratch.free[i] = true; 2818 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); 2819 } 2820 } 2821 2822 int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) 2823 { 2824 uint32_t scratch; 2825 uint32_t tmp = 0; 2826 unsigned i; 2827 int r; 2828 2829 r = radeon_scratch_get(rdev, &scratch); 2830 if (r) { 2831 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); 2832 return r; 2833 } 2834 WREG32(scratch, 0xCAFEDEAD); 2835 r = radeon_ring_lock(rdev, ring, 3); 2836 if (r) { 2837 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring->idx, r); 2838 radeon_scratch_free(rdev, scratch); 2839 return r; 2840 } 2841 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2842 radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); 2843 radeon_ring_write(ring, 0xDEADBEEF); 2844 radeon_ring_unlock_commit(rdev, ring, false); 2845 for (i = 0; i < rdev->usec_timeout; i++) { 2846 tmp = RREG32(scratch); 2847 if (tmp == 0xDEADBEEF) 2848 break; 2849 udelay(1); 2850 } 2851 if (i < rdev->usec_timeout) { 2852 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); 2853 } else { 2854 DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n", 2855 ring->idx, scratch, tmp); 2856 r = -EINVAL; 2857 } 2858 radeon_scratch_free(rdev, scratch); 2859 return r; 2860 } 2861 2862 /* 2863 * CP fences/semaphores 2864 */ 2865 2866 void r600_fence_ring_emit(struct radeon_device *rdev, 2867 struct radeon_fence *fence) 2868 { 2869 struct radeon_ring *ring = &rdev->ring[fence->ring]; 2870 u32 cp_coher_cntl = PACKET3_TC_ACTION_ENA | PACKET3_VC_ACTION_ENA | 2871 PACKET3_SH_ACTION_ENA; 2872 2873 if (rdev->family >= CHIP_RV770) 2874 cp_coher_cntl |= PACKET3_FULL_CACHE_ENA; 2875 2876 if (rdev->wb.use_event) { 2877 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; 2878 /* flush read cache over gart */ 2879 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 2880 radeon_ring_write(ring, cp_coher_cntl); 2881 radeon_ring_write(ring, 0xFFFFFFFF); 2882 radeon_ring_write(ring, 0); 2883 radeon_ring_write(ring, 10); /* poll interval */ 2884 /* EVENT_WRITE_EOP - flush caches, send int */ 2885 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 2886 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5)); 2887 radeon_ring_write(ring, lower_32_bits(addr)); 2888 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); 2889 radeon_ring_write(ring, fence->seq); 2890 radeon_ring_write(ring, 0); 2891 } else { 2892 /* flush read cache over gart */ 2893 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 2894 radeon_ring_write(ring, cp_coher_cntl); 2895 radeon_ring_write(ring, 0xFFFFFFFF); 2896 radeon_ring_write(ring, 0); 2897 radeon_ring_write(ring, 10); /* poll interval */ 2898 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); 2899 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0)); 2900 /* wait for 3D idle clean */ 2901 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2902 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 2903 radeon_ring_write(ring, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit); 2904 /* Emit fence sequence & fire IRQ */ 2905 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2906 radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); 2907 radeon_ring_write(ring, fence->seq); 2908 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */ 2909 radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0)); 2910 radeon_ring_write(ring, RB_INT_STAT); 2911 } 2912 } 2913 2914 /** 2915 * r600_semaphore_ring_emit - emit a semaphore on the CP ring 2916 * 2917 * @rdev: radeon_device pointer 2918 * @ring: radeon ring buffer object 2919 * @semaphore: radeon semaphore object 2920 * @emit_wait: Is this a semaphore wait? 2921 * 2922 * Emits a semaphore signal/wait packet to the CP ring and prevents the PFP 2923 * from running ahead of semaphore waits. 2924 */ 2925 bool r600_semaphore_ring_emit(struct radeon_device *rdev, 2926 struct radeon_ring *ring, 2927 struct radeon_semaphore *semaphore, 2928 bool emit_wait) 2929 { 2930 uint64_t addr = semaphore->gpu_addr; 2931 unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL; 2932 2933 if (rdev->family < CHIP_CAYMAN) 2934 sel |= PACKET3_SEM_WAIT_ON_SIGNAL; 2935 2936 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); 2937 radeon_ring_write(ring, lower_32_bits(addr)); 2938 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel); 2939 2940 /* PFP_SYNC_ME packet only exists on 7xx+, only enable it on eg+ */ 2941 if (emit_wait && (rdev->family >= CHIP_CEDAR)) { 2942 /* Prevent the PFP from running ahead of the semaphore wait */ 2943 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 2944 radeon_ring_write(ring, 0x0); 2945 } 2946 2947 return true; 2948 } 2949 2950 /** 2951 * r600_copy_cpdma - copy pages using the CP DMA engine 2952 * 2953 * @rdev: radeon_device pointer 2954 * @src_offset: src GPU address 2955 * @dst_offset: dst GPU address 2956 * @num_gpu_pages: number of GPU pages to xfer 2957 * @resv: DMA reservation object to manage fences 2958 * 2959 * Copy GPU paging using the CP DMA engine (r6xx+). 2960 * Used by the radeon ttm implementation to move pages if 2961 * registered as the asic copy callback. 2962 */ 2963 struct radeon_fence *r600_copy_cpdma(struct radeon_device *rdev, 2964 uint64_t src_offset, uint64_t dst_offset, 2965 unsigned num_gpu_pages, 2966 struct dma_resv *resv) 2967 { 2968 struct radeon_fence *fence; 2969 struct radeon_sync sync; 2970 int ring_index = rdev->asic->copy.blit_ring_index; 2971 struct radeon_ring *ring = &rdev->ring[ring_index]; 2972 u32 size_in_bytes, cur_size_in_bytes, tmp; 2973 int i, num_loops; 2974 int r = 0; 2975 2976 radeon_sync_create(&sync); 2977 2978 size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT); 2979 num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff); 2980 r = radeon_ring_lock(rdev, ring, num_loops * 6 + 24); 2981 if (r) { 2982 DRM_ERROR("radeon: moving bo (%d).\n", r); 2983 radeon_sync_free(rdev, &sync, NULL); 2984 return ERR_PTR(r); 2985 } 2986 2987 radeon_sync_resv(rdev, &sync, resv, false); 2988 radeon_sync_rings(rdev, &sync, ring->idx); 2989 2990 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2991 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 2992 radeon_ring_write(ring, WAIT_3D_IDLE_bit); 2993 for (i = 0; i < num_loops; i++) { 2994 cur_size_in_bytes = size_in_bytes; 2995 if (cur_size_in_bytes > 0x1fffff) 2996 cur_size_in_bytes = 0x1fffff; 2997 size_in_bytes -= cur_size_in_bytes; 2998 tmp = upper_32_bits(src_offset) & 0xff; 2999 if (size_in_bytes == 0) 3000 tmp |= PACKET3_CP_DMA_CP_SYNC; 3001 radeon_ring_write(ring, PACKET3(PACKET3_CP_DMA, 4)); 3002 radeon_ring_write(ring, lower_32_bits(src_offset)); 3003 radeon_ring_write(ring, tmp); 3004 radeon_ring_write(ring, lower_32_bits(dst_offset)); 3005 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); 3006 radeon_ring_write(ring, cur_size_in_bytes); 3007 src_offset += cur_size_in_bytes; 3008 dst_offset += cur_size_in_bytes; 3009 } 3010 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 3011 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 3012 radeon_ring_write(ring, WAIT_CP_DMA_IDLE_bit); 3013 3014 r = radeon_fence_emit(rdev, &fence, ring->idx); 3015 if (r) { 3016 radeon_ring_unlock_undo(rdev, ring); 3017 radeon_sync_free(rdev, &sync, NULL); 3018 return ERR_PTR(r); 3019 } 3020 3021 radeon_ring_unlock_commit(rdev, ring, false); 3022 radeon_sync_free(rdev, &sync, fence); 3023 3024 return fence; 3025 } 3026 3027 int r600_set_surface_reg(struct radeon_device *rdev, int reg, 3028 uint32_t tiling_flags, uint32_t pitch, 3029 uint32_t offset, uint32_t obj_size) 3030 { 3031 /* FIXME: implement */ 3032 return 0; 3033 } 3034 3035 void r600_clear_surface_reg(struct radeon_device *rdev, int reg) 3036 { 3037 /* FIXME: implement */ 3038 } 3039 3040 static void r600_uvd_init(struct radeon_device *rdev) 3041 { 3042 int r; 3043 3044 if (!rdev->has_uvd) 3045 return; 3046 3047 r = radeon_uvd_init(rdev); 3048 if (r) { 3049 dev_err(rdev->dev, "failed UVD (%d) init.\n", r); 3050 /* 3051 * At this point rdev->uvd.vcpu_bo is NULL which trickles down 3052 * to early fails uvd_v1_0_resume() and thus nothing happens 3053 * there. So it is pointless to try to go through that code 3054 * hence why we disable uvd here. 3055 */ 3056 rdev->has_uvd = false; 3057 return; 3058 } 3059 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL; 3060 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], 4096); 3061 } 3062 3063 static void r600_uvd_start(struct radeon_device *rdev) 3064 { 3065 int r; 3066 3067 if (!rdev->has_uvd) 3068 return; 3069 3070 r = uvd_v1_0_resume(rdev); 3071 if (r) { 3072 dev_err(rdev->dev, "failed UVD resume (%d).\n", r); 3073 goto error; 3074 } 3075 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_UVD_INDEX); 3076 if (r) { 3077 dev_err(rdev->dev, "failed initializing UVD fences (%d).\n", r); 3078 goto error; 3079 } 3080 return; 3081 3082 error: 3083 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0; 3084 } 3085 3086 static void r600_uvd_resume(struct radeon_device *rdev) 3087 { 3088 struct radeon_ring *ring; 3089 int r; 3090 3091 if (!rdev->has_uvd || !rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size) 3092 return; 3093 3094 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; 3095 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, PACKET0(UVD_NO_OP, 0)); 3096 if (r) { 3097 dev_err(rdev->dev, "failed initializing UVD ring (%d).\n", r); 3098 return; 3099 } 3100 r = uvd_v1_0_init(rdev); 3101 if (r) { 3102 dev_err(rdev->dev, "failed initializing UVD (%d).\n", r); 3103 return; 3104 } 3105 } 3106 3107 static int r600_startup(struct radeon_device *rdev) 3108 { 3109 struct radeon_ring *ring; 3110 int r; 3111 3112 /* enable pcie gen2 link */ 3113 r600_pcie_gen2_enable(rdev); 3114 3115 /* scratch needs to be initialized before MC */ 3116 r = r600_vram_scratch_init(rdev); 3117 if (r) 3118 return r; 3119 3120 r600_mc_program(rdev); 3121 3122 if (rdev->flags & RADEON_IS_AGP) { 3123 r600_agp_enable(rdev); 3124 } else { 3125 r = r600_pcie_gart_enable(rdev); 3126 if (r) 3127 return r; 3128 } 3129 r600_gpu_init(rdev); 3130 3131 /* allocate wb buffer */ 3132 r = radeon_wb_init(rdev); 3133 if (r) 3134 return r; 3135 3136 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 3137 if (r) { 3138 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 3139 return r; 3140 } 3141 3142 r600_uvd_start(rdev); 3143 3144 /* Enable IRQ */ 3145 if (!rdev->irq.installed) { 3146 r = radeon_irq_kms_init(rdev); 3147 if (r) 3148 return r; 3149 } 3150 3151 r = r600_irq_init(rdev); 3152 if (r) { 3153 DRM_ERROR("radeon: IH init failed (%d).\n", r); 3154 radeon_irq_kms_fini(rdev); 3155 return r; 3156 } 3157 r600_irq_set(rdev); 3158 3159 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 3160 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, 3161 RADEON_CP_PACKET2); 3162 if (r) 3163 return r; 3164 3165 r = r600_cp_load_microcode(rdev); 3166 if (r) 3167 return r; 3168 r = r600_cp_resume(rdev); 3169 if (r) 3170 return r; 3171 3172 r600_uvd_resume(rdev); 3173 3174 r = radeon_ib_pool_init(rdev); 3175 if (r) { 3176 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 3177 return r; 3178 } 3179 3180 r = radeon_audio_init(rdev); 3181 if (r) { 3182 DRM_ERROR("radeon: audio init failed\n"); 3183 return r; 3184 } 3185 3186 return 0; 3187 } 3188 3189 void r600_vga_set_state(struct radeon_device *rdev, bool state) 3190 { 3191 uint32_t temp; 3192 3193 temp = RREG32(CONFIG_CNTL); 3194 if (!state) { 3195 temp &= ~(1<<0); 3196 temp |= (1<<1); 3197 } else { 3198 temp &= ~(1<<1); 3199 } 3200 WREG32(CONFIG_CNTL, temp); 3201 } 3202 3203 int r600_resume(struct radeon_device *rdev) 3204 { 3205 int r; 3206 3207 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw, 3208 * posting will perform necessary task to bring back GPU into good 3209 * shape. 3210 */ 3211 /* post card */ 3212 atom_asic_init(rdev->mode_info.atom_context); 3213 3214 if (rdev->pm.pm_method == PM_METHOD_DPM) 3215 radeon_pm_resume(rdev); 3216 3217 rdev->accel_working = true; 3218 r = r600_startup(rdev); 3219 if (r) { 3220 DRM_ERROR("r600 startup failed on resume\n"); 3221 rdev->accel_working = false; 3222 return r; 3223 } 3224 3225 return r; 3226 } 3227 3228 int r600_suspend(struct radeon_device *rdev) 3229 { 3230 radeon_pm_suspend(rdev); 3231 radeon_audio_fini(rdev); 3232 r600_cp_stop(rdev); 3233 if (rdev->has_uvd) { 3234 radeon_uvd_suspend(rdev); 3235 uvd_v1_0_fini(rdev); 3236 } 3237 r600_irq_suspend(rdev); 3238 radeon_wb_disable(rdev); 3239 r600_pcie_gart_disable(rdev); 3240 3241 return 0; 3242 } 3243 3244 /* Plan is to move initialization in that function and use 3245 * helper function so that radeon_device_init pretty much 3246 * do nothing more than calling asic specific function. This 3247 * should also allow to remove a bunch of callback function 3248 * like vram_info. 3249 */ 3250 int r600_init(struct radeon_device *rdev) 3251 { 3252 int r; 3253 3254 r600_debugfs_mc_info_init(rdev); 3255 /* Read BIOS */ 3256 if (!radeon_get_bios(rdev)) { 3257 if (ASIC_IS_AVIVO(rdev)) 3258 return -EINVAL; 3259 } 3260 /* Must be an ATOMBIOS */ 3261 if (!rdev->is_atom_bios) { 3262 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n"); 3263 return -EINVAL; 3264 } 3265 r = radeon_atombios_init(rdev); 3266 if (r) 3267 return r; 3268 /* Post card if necessary */ 3269 if (!radeon_card_posted(rdev)) { 3270 if (!rdev->bios) { 3271 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); 3272 return -EINVAL; 3273 } 3274 DRM_INFO("GPU not posted. posting now...\n"); 3275 atom_asic_init(rdev->mode_info.atom_context); 3276 } 3277 /* Initialize scratch registers */ 3278 r600_scratch_init(rdev); 3279 /* Initialize surface registers */ 3280 radeon_surface_init(rdev); 3281 /* Initialize clocks */ 3282 radeon_get_clock_info(rdev->ddev); 3283 /* Fence driver */ 3284 radeon_fence_driver_init(rdev); 3285 if (rdev->flags & RADEON_IS_AGP) { 3286 r = radeon_agp_init(rdev); 3287 if (r) 3288 radeon_agp_disable(rdev); 3289 } 3290 r = r600_mc_init(rdev); 3291 if (r) 3292 return r; 3293 /* Memory manager */ 3294 r = radeon_bo_init(rdev); 3295 if (r) 3296 return r; 3297 3298 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { 3299 r = r600_init_microcode(rdev); 3300 if (r) { 3301 DRM_ERROR("Failed to load firmware!\n"); 3302 return r; 3303 } 3304 } 3305 3306 /* Initialize power management */ 3307 radeon_pm_init(rdev); 3308 3309 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL; 3310 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024); 3311 3312 r600_uvd_init(rdev); 3313 3314 rdev->ih.ring_obj = NULL; 3315 r600_ih_ring_init(rdev, 64 * 1024); 3316 3317 r = r600_pcie_gart_init(rdev); 3318 if (r) 3319 return r; 3320 3321 rdev->accel_working = true; 3322 r = r600_startup(rdev); 3323 if (r) { 3324 dev_err(rdev->dev, "disabling GPU acceleration\n"); 3325 r600_cp_fini(rdev); 3326 r600_irq_fini(rdev); 3327 radeon_wb_fini(rdev); 3328 radeon_ib_pool_fini(rdev); 3329 radeon_irq_kms_fini(rdev); 3330 r600_pcie_gart_fini(rdev); 3331 rdev->accel_working = false; 3332 } 3333 3334 return 0; 3335 } 3336 3337 void r600_fini(struct radeon_device *rdev) 3338 { 3339 radeon_pm_fini(rdev); 3340 radeon_audio_fini(rdev); 3341 r600_cp_fini(rdev); 3342 r600_irq_fini(rdev); 3343 if (rdev->has_uvd) { 3344 uvd_v1_0_fini(rdev); 3345 radeon_uvd_fini(rdev); 3346 } 3347 radeon_wb_fini(rdev); 3348 radeon_ib_pool_fini(rdev); 3349 radeon_irq_kms_fini(rdev); 3350 r600_pcie_gart_fini(rdev); 3351 r600_vram_scratch_fini(rdev); 3352 radeon_agp_fini(rdev); 3353 radeon_gem_fini(rdev); 3354 radeon_fence_driver_fini(rdev); 3355 radeon_bo_fini(rdev); 3356 radeon_atombios_fini(rdev); 3357 kfree(rdev->bios); 3358 rdev->bios = NULL; 3359 } 3360 3361 3362 /* 3363 * CS stuff 3364 */ 3365 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 3366 { 3367 struct radeon_ring *ring = &rdev->ring[ib->ring]; 3368 u32 next_rptr; 3369 3370 if (ring->rptr_save_reg) { 3371 next_rptr = ring->wptr + 3 + 4; 3372 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 3373 radeon_ring_write(ring, ((ring->rptr_save_reg - 3374 PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); 3375 radeon_ring_write(ring, next_rptr); 3376 } else if (rdev->wb.enabled) { 3377 next_rptr = ring->wptr + 5 + 4; 3378 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3)); 3379 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); 3380 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18)); 3381 radeon_ring_write(ring, next_rptr); 3382 radeon_ring_write(ring, 0); 3383 } 3384 3385 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 3386 radeon_ring_write(ring, 3387 #ifdef __BIG_ENDIAN 3388 (2 << 0) | 3389 #endif 3390 (ib->gpu_addr & 0xFFFFFFFC)); 3391 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF); 3392 radeon_ring_write(ring, ib->length_dw); 3393 } 3394 3395 int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) 3396 { 3397 struct radeon_ib ib; 3398 uint32_t scratch; 3399 uint32_t tmp = 0; 3400 unsigned i; 3401 int r; 3402 3403 r = radeon_scratch_get(rdev, &scratch); 3404 if (r) { 3405 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); 3406 return r; 3407 } 3408 WREG32(scratch, 0xCAFEDEAD); 3409 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256); 3410 if (r) { 3411 DRM_ERROR("radeon: failed to get ib (%d).\n", r); 3412 goto free_scratch; 3413 } 3414 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1); 3415 ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 3416 ib.ptr[2] = 0xDEADBEEF; 3417 ib.length_dw = 3; 3418 r = radeon_ib_schedule(rdev, &ib, NULL, false); 3419 if (r) { 3420 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); 3421 goto free_ib; 3422 } 3423 r = radeon_fence_wait_timeout(ib.fence, false, usecs_to_jiffies( 3424 RADEON_USEC_IB_TEST_TIMEOUT)); 3425 if (r < 0) { 3426 DRM_ERROR("radeon: fence wait failed (%d).\n", r); 3427 goto free_ib; 3428 } else if (r == 0) { 3429 DRM_ERROR("radeon: fence wait timed out.\n"); 3430 r = -ETIMEDOUT; 3431 goto free_ib; 3432 } 3433 r = 0; 3434 for (i = 0; i < rdev->usec_timeout; i++) { 3435 tmp = RREG32(scratch); 3436 if (tmp == 0xDEADBEEF) 3437 break; 3438 udelay(1); 3439 } 3440 if (i < rdev->usec_timeout) { 3441 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i); 3442 } else { 3443 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n", 3444 scratch, tmp); 3445 r = -EINVAL; 3446 } 3447 free_ib: 3448 radeon_ib_free(rdev, &ib); 3449 free_scratch: 3450 radeon_scratch_free(rdev, scratch); 3451 return r; 3452 } 3453 3454 /* 3455 * Interrupts 3456 * 3457 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty 3458 * the same as the CP ring buffer, but in reverse. Rather than the CPU 3459 * writing to the ring and the GPU consuming, the GPU writes to the ring 3460 * and host consumes. As the host irq handler processes interrupts, it 3461 * increments the rptr. When the rptr catches up with the wptr, all the 3462 * current interrupts have been processed. 3463 */ 3464 3465 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size) 3466 { 3467 u32 rb_bufsz; 3468 3469 /* Align ring size */ 3470 rb_bufsz = order_base_2(ring_size / 4); 3471 ring_size = (1 << rb_bufsz) * 4; 3472 rdev->ih.ring_size = ring_size; 3473 rdev->ih.ptr_mask = rdev->ih.ring_size - 1; 3474 rdev->ih.rptr = 0; 3475 } 3476 3477 int r600_ih_ring_alloc(struct radeon_device *rdev) 3478 { 3479 int r; 3480 3481 /* Allocate ring buffer */ 3482 if (rdev->ih.ring_obj == NULL) { 3483 r = radeon_bo_create(rdev, rdev->ih.ring_size, 3484 PAGE_SIZE, true, 3485 RADEON_GEM_DOMAIN_GTT, 0, 3486 NULL, NULL, &rdev->ih.ring_obj); 3487 if (r) { 3488 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r); 3489 return r; 3490 } 3491 r = radeon_bo_reserve(rdev->ih.ring_obj, false); 3492 if (unlikely(r != 0)) 3493 return r; 3494 r = radeon_bo_pin(rdev->ih.ring_obj, 3495 RADEON_GEM_DOMAIN_GTT, 3496 &rdev->ih.gpu_addr); 3497 if (r) { 3498 radeon_bo_unreserve(rdev->ih.ring_obj); 3499 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r); 3500 return r; 3501 } 3502 r = radeon_bo_kmap(rdev->ih.ring_obj, 3503 (void **)&rdev->ih.ring); 3504 radeon_bo_unreserve(rdev->ih.ring_obj); 3505 if (r) { 3506 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r); 3507 return r; 3508 } 3509 } 3510 return 0; 3511 } 3512 3513 void r600_ih_ring_fini(struct radeon_device *rdev) 3514 { 3515 int r; 3516 if (rdev->ih.ring_obj) { 3517 r = radeon_bo_reserve(rdev->ih.ring_obj, false); 3518 if (likely(r == 0)) { 3519 radeon_bo_kunmap(rdev->ih.ring_obj); 3520 radeon_bo_unpin(rdev->ih.ring_obj); 3521 radeon_bo_unreserve(rdev->ih.ring_obj); 3522 } 3523 radeon_bo_unref(&rdev->ih.ring_obj); 3524 rdev->ih.ring = NULL; 3525 rdev->ih.ring_obj = NULL; 3526 } 3527 } 3528 3529 void r600_rlc_stop(struct radeon_device *rdev) 3530 { 3531 3532 if ((rdev->family >= CHIP_RV770) && 3533 (rdev->family <= CHIP_RV740)) { 3534 /* r7xx asics need to soft reset RLC before halting */ 3535 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC); 3536 RREG32(SRBM_SOFT_RESET); 3537 mdelay(15); 3538 WREG32(SRBM_SOFT_RESET, 0); 3539 RREG32(SRBM_SOFT_RESET); 3540 } 3541 3542 WREG32(RLC_CNTL, 0); 3543 } 3544 3545 static void r600_rlc_start(struct radeon_device *rdev) 3546 { 3547 WREG32(RLC_CNTL, RLC_ENABLE); 3548 } 3549 3550 static int r600_rlc_resume(struct radeon_device *rdev) 3551 { 3552 u32 i; 3553 const __be32 *fw_data; 3554 3555 if (!rdev->rlc_fw) 3556 return -EINVAL; 3557 3558 r600_rlc_stop(rdev); 3559 3560 WREG32(RLC_HB_CNTL, 0); 3561 3562 WREG32(RLC_HB_BASE, 0); 3563 WREG32(RLC_HB_RPTR, 0); 3564 WREG32(RLC_HB_WPTR, 0); 3565 WREG32(RLC_HB_WPTR_LSB_ADDR, 0); 3566 WREG32(RLC_HB_WPTR_MSB_ADDR, 0); 3567 WREG32(RLC_MC_CNTL, 0); 3568 WREG32(RLC_UCODE_CNTL, 0); 3569 3570 fw_data = (const __be32 *)rdev->rlc_fw->data; 3571 if (rdev->family >= CHIP_RV770) { 3572 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) { 3573 WREG32(RLC_UCODE_ADDR, i); 3574 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); 3575 } 3576 } else { 3577 for (i = 0; i < R600_RLC_UCODE_SIZE; i++) { 3578 WREG32(RLC_UCODE_ADDR, i); 3579 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); 3580 } 3581 } 3582 WREG32(RLC_UCODE_ADDR, 0); 3583 3584 r600_rlc_start(rdev); 3585 3586 return 0; 3587 } 3588 3589 static void r600_enable_interrupts(struct radeon_device *rdev) 3590 { 3591 u32 ih_cntl = RREG32(IH_CNTL); 3592 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); 3593 3594 ih_cntl |= ENABLE_INTR; 3595 ih_rb_cntl |= IH_RB_ENABLE; 3596 WREG32(IH_CNTL, ih_cntl); 3597 WREG32(IH_RB_CNTL, ih_rb_cntl); 3598 rdev->ih.enabled = true; 3599 } 3600 3601 void r600_disable_interrupts(struct radeon_device *rdev) 3602 { 3603 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); 3604 u32 ih_cntl = RREG32(IH_CNTL); 3605 3606 ih_rb_cntl &= ~IH_RB_ENABLE; 3607 ih_cntl &= ~ENABLE_INTR; 3608 WREG32(IH_RB_CNTL, ih_rb_cntl); 3609 WREG32(IH_CNTL, ih_cntl); 3610 /* set rptr, wptr to 0 */ 3611 WREG32(IH_RB_RPTR, 0); 3612 WREG32(IH_RB_WPTR, 0); 3613 rdev->ih.enabled = false; 3614 rdev->ih.rptr = 0; 3615 } 3616 3617 static void r600_disable_interrupt_state(struct radeon_device *rdev) 3618 { 3619 u32 tmp; 3620 3621 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); 3622 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE; 3623 WREG32(DMA_CNTL, tmp); 3624 WREG32(GRBM_INT_CNTL, 0); 3625 WREG32(DxMODE_INT_MASK, 0); 3626 WREG32(D1GRPH_INTERRUPT_CONTROL, 0); 3627 WREG32(D2GRPH_INTERRUPT_CONTROL, 0); 3628 if (ASIC_IS_DCE3(rdev)) { 3629 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0); 3630 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0); 3631 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3632 WREG32(DC_HPD1_INT_CONTROL, tmp); 3633 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3634 WREG32(DC_HPD2_INT_CONTROL, tmp); 3635 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3636 WREG32(DC_HPD3_INT_CONTROL, tmp); 3637 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3638 WREG32(DC_HPD4_INT_CONTROL, tmp); 3639 if (ASIC_IS_DCE32(rdev)) { 3640 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3641 WREG32(DC_HPD5_INT_CONTROL, tmp); 3642 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3643 WREG32(DC_HPD6_INT_CONTROL, tmp); 3644 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3645 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp); 3646 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3647 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp); 3648 } else { 3649 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3650 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); 3651 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3652 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp); 3653 } 3654 } else { 3655 WREG32(DACA_AUTODETECT_INT_CONTROL, 0); 3656 WREG32(DACB_AUTODETECT_INT_CONTROL, 0); 3657 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; 3658 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 3659 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; 3660 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 3661 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; 3662 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); 3663 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3664 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); 3665 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3666 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp); 3667 } 3668 } 3669 3670 int r600_irq_init(struct radeon_device *rdev) 3671 { 3672 int ret = 0; 3673 int rb_bufsz; 3674 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; 3675 3676 /* allocate ring */ 3677 ret = r600_ih_ring_alloc(rdev); 3678 if (ret) 3679 return ret; 3680 3681 /* disable irqs */ 3682 r600_disable_interrupts(rdev); 3683 3684 /* init rlc */ 3685 if (rdev->family >= CHIP_CEDAR) 3686 ret = evergreen_rlc_resume(rdev); 3687 else 3688 ret = r600_rlc_resume(rdev); 3689 if (ret) { 3690 r600_ih_ring_fini(rdev); 3691 return ret; 3692 } 3693 3694 /* setup interrupt control */ 3695 /* set dummy read address to dummy page address */ 3696 WREG32(INTERRUPT_CNTL2, rdev->dummy_page.addr >> 8); 3697 interrupt_cntl = RREG32(INTERRUPT_CNTL); 3698 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi 3699 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN 3700 */ 3701 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE; 3702 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */ 3703 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN; 3704 WREG32(INTERRUPT_CNTL, interrupt_cntl); 3705 3706 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8); 3707 rb_bufsz = order_base_2(rdev->ih.ring_size / 4); 3708 3709 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE | 3710 IH_WPTR_OVERFLOW_CLEAR | 3711 (rb_bufsz << 1)); 3712 3713 if (rdev->wb.enabled) 3714 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE; 3715 3716 /* set the writeback address whether it's enabled or not */ 3717 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC); 3718 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF); 3719 3720 WREG32(IH_RB_CNTL, ih_rb_cntl); 3721 3722 /* set rptr, wptr to 0 */ 3723 WREG32(IH_RB_RPTR, 0); 3724 WREG32(IH_RB_WPTR, 0); 3725 3726 /* Default settings for IH_CNTL (disabled at first) */ 3727 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10); 3728 /* RPTR_REARM only works if msi's are enabled */ 3729 if (rdev->msi_enabled) 3730 ih_cntl |= RPTR_REARM; 3731 WREG32(IH_CNTL, ih_cntl); 3732 3733 /* force the active interrupt state to all disabled */ 3734 if (rdev->family >= CHIP_CEDAR) 3735 evergreen_disable_interrupt_state(rdev); 3736 else 3737 r600_disable_interrupt_state(rdev); 3738 3739 /* at this point everything should be setup correctly to enable master */ 3740 pci_set_master(rdev->pdev); 3741 3742 /* enable irqs */ 3743 r600_enable_interrupts(rdev); 3744 3745 return ret; 3746 } 3747 3748 void r600_irq_suspend(struct radeon_device *rdev) 3749 { 3750 r600_irq_disable(rdev); 3751 r600_rlc_stop(rdev); 3752 } 3753 3754 void r600_irq_fini(struct radeon_device *rdev) 3755 { 3756 r600_irq_suspend(rdev); 3757 r600_ih_ring_fini(rdev); 3758 } 3759 3760 int r600_irq_set(struct radeon_device *rdev) 3761 { 3762 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; 3763 u32 mode_int = 0; 3764 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0; 3765 u32 grbm_int_cntl = 0; 3766 u32 hdmi0, hdmi1; 3767 u32 dma_cntl; 3768 u32 thermal_int = 0; 3769 3770 if (!rdev->irq.installed) { 3771 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); 3772 return -EINVAL; 3773 } 3774 /* don't enable anything if the ih is disabled */ 3775 if (!rdev->ih.enabled) { 3776 r600_disable_interrupts(rdev); 3777 /* force the active interrupt state to all disabled */ 3778 r600_disable_interrupt_state(rdev); 3779 return 0; 3780 } 3781 3782 if (ASIC_IS_DCE3(rdev)) { 3783 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN; 3784 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN; 3785 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN; 3786 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN; 3787 if (ASIC_IS_DCE32(rdev)) { 3788 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; 3789 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN; 3790 hdmi0 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~AFMT_AZ_FORMAT_WTRIG_MASK; 3791 hdmi1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~AFMT_AZ_FORMAT_WTRIG_MASK; 3792 } else { 3793 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3794 hdmi1 = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3795 } 3796 } else { 3797 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN; 3798 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN; 3799 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN; 3800 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3801 hdmi1 = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3802 } 3803 3804 dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE; 3805 3806 if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) { 3807 thermal_int = RREG32(CG_THERMAL_INT) & 3808 ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); 3809 } else if (rdev->family >= CHIP_RV770) { 3810 thermal_int = RREG32(RV770_CG_THERMAL_INT) & 3811 ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); 3812 } 3813 if (rdev->irq.dpm_thermal) { 3814 DRM_DEBUG("dpm thermal\n"); 3815 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW; 3816 } 3817 3818 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { 3819 DRM_DEBUG("r600_irq_set: sw int\n"); 3820 cp_int_cntl |= RB_INT_ENABLE; 3821 cp_int_cntl |= TIME_STAMP_INT_ENABLE; 3822 } 3823 3824 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) { 3825 DRM_DEBUG("r600_irq_set: sw int dma\n"); 3826 dma_cntl |= TRAP_ENABLE; 3827 } 3828 3829 if (rdev->irq.crtc_vblank_int[0] || 3830 atomic_read(&rdev->irq.pflip[0])) { 3831 DRM_DEBUG("r600_irq_set: vblank 0\n"); 3832 mode_int |= D1MODE_VBLANK_INT_MASK; 3833 } 3834 if (rdev->irq.crtc_vblank_int[1] || 3835 atomic_read(&rdev->irq.pflip[1])) { 3836 DRM_DEBUG("r600_irq_set: vblank 1\n"); 3837 mode_int |= D2MODE_VBLANK_INT_MASK; 3838 } 3839 if (rdev->irq.hpd[0]) { 3840 DRM_DEBUG("r600_irq_set: hpd 1\n"); 3841 hpd1 |= DC_HPDx_INT_EN; 3842 } 3843 if (rdev->irq.hpd[1]) { 3844 DRM_DEBUG("r600_irq_set: hpd 2\n"); 3845 hpd2 |= DC_HPDx_INT_EN; 3846 } 3847 if (rdev->irq.hpd[2]) { 3848 DRM_DEBUG("r600_irq_set: hpd 3\n"); 3849 hpd3 |= DC_HPDx_INT_EN; 3850 } 3851 if (rdev->irq.hpd[3]) { 3852 DRM_DEBUG("r600_irq_set: hpd 4\n"); 3853 hpd4 |= DC_HPDx_INT_EN; 3854 } 3855 if (rdev->irq.hpd[4]) { 3856 DRM_DEBUG("r600_irq_set: hpd 5\n"); 3857 hpd5 |= DC_HPDx_INT_EN; 3858 } 3859 if (rdev->irq.hpd[5]) { 3860 DRM_DEBUG("r600_irq_set: hpd 6\n"); 3861 hpd6 |= DC_HPDx_INT_EN; 3862 } 3863 if (rdev->irq.afmt[0]) { 3864 DRM_DEBUG("r600_irq_set: hdmi 0\n"); 3865 hdmi0 |= HDMI0_AZ_FORMAT_WTRIG_MASK; 3866 } 3867 if (rdev->irq.afmt[1]) { 3868 DRM_DEBUG("r600_irq_set: hdmi 0\n"); 3869 hdmi1 |= HDMI0_AZ_FORMAT_WTRIG_MASK; 3870 } 3871 3872 WREG32(CP_INT_CNTL, cp_int_cntl); 3873 WREG32(DMA_CNTL, dma_cntl); 3874 WREG32(DxMODE_INT_MASK, mode_int); 3875 WREG32(D1GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK); 3876 WREG32(D2GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK); 3877 WREG32(GRBM_INT_CNTL, grbm_int_cntl); 3878 if (ASIC_IS_DCE3(rdev)) { 3879 WREG32(DC_HPD1_INT_CONTROL, hpd1); 3880 WREG32(DC_HPD2_INT_CONTROL, hpd2); 3881 WREG32(DC_HPD3_INT_CONTROL, hpd3); 3882 WREG32(DC_HPD4_INT_CONTROL, hpd4); 3883 if (ASIC_IS_DCE32(rdev)) { 3884 WREG32(DC_HPD5_INT_CONTROL, hpd5); 3885 WREG32(DC_HPD6_INT_CONTROL, hpd6); 3886 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, hdmi0); 3887 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, hdmi1); 3888 } else { 3889 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0); 3890 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, hdmi1); 3891 } 3892 } else { 3893 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); 3894 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); 3895 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3); 3896 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0); 3897 WREG32(HDMI1_AUDIO_PACKET_CONTROL, hdmi1); 3898 } 3899 if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) { 3900 WREG32(CG_THERMAL_INT, thermal_int); 3901 } else if (rdev->family >= CHIP_RV770) { 3902 WREG32(RV770_CG_THERMAL_INT, thermal_int); 3903 } 3904 3905 /* posting read */ 3906 RREG32(R_000E50_SRBM_STATUS); 3907 3908 return 0; 3909 } 3910 3911 static void r600_irq_ack(struct radeon_device *rdev) 3912 { 3913 u32 tmp; 3914 3915 if (ASIC_IS_DCE3(rdev)) { 3916 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS); 3917 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE); 3918 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2); 3919 if (ASIC_IS_DCE32(rdev)) { 3920 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0); 3921 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1); 3922 } else { 3923 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); 3924 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS); 3925 } 3926 } else { 3927 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS); 3928 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); 3929 rdev->irq.stat_regs.r600.disp_int_cont2 = 0; 3930 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); 3931 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS); 3932 } 3933 rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS); 3934 rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS); 3935 3936 if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED) 3937 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR); 3938 if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED) 3939 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR); 3940 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) 3941 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK); 3942 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) 3943 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK); 3944 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) 3945 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK); 3946 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) 3947 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK); 3948 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) { 3949 if (ASIC_IS_DCE3(rdev)) { 3950 tmp = RREG32(DC_HPD1_INT_CONTROL); 3951 tmp |= DC_HPDx_INT_ACK; 3952 WREG32(DC_HPD1_INT_CONTROL, tmp); 3953 } else { 3954 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); 3955 tmp |= DC_HPDx_INT_ACK; 3956 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 3957 } 3958 } 3959 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) { 3960 if (ASIC_IS_DCE3(rdev)) { 3961 tmp = RREG32(DC_HPD2_INT_CONTROL); 3962 tmp |= DC_HPDx_INT_ACK; 3963 WREG32(DC_HPD2_INT_CONTROL, tmp); 3964 } else { 3965 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); 3966 tmp |= DC_HPDx_INT_ACK; 3967 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 3968 } 3969 } 3970 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) { 3971 if (ASIC_IS_DCE3(rdev)) { 3972 tmp = RREG32(DC_HPD3_INT_CONTROL); 3973 tmp |= DC_HPDx_INT_ACK; 3974 WREG32(DC_HPD3_INT_CONTROL, tmp); 3975 } else { 3976 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); 3977 tmp |= DC_HPDx_INT_ACK; 3978 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); 3979 } 3980 } 3981 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) { 3982 tmp = RREG32(DC_HPD4_INT_CONTROL); 3983 tmp |= DC_HPDx_INT_ACK; 3984 WREG32(DC_HPD4_INT_CONTROL, tmp); 3985 } 3986 if (ASIC_IS_DCE32(rdev)) { 3987 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) { 3988 tmp = RREG32(DC_HPD5_INT_CONTROL); 3989 tmp |= DC_HPDx_INT_ACK; 3990 WREG32(DC_HPD5_INT_CONTROL, tmp); 3991 } 3992 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) { 3993 tmp = RREG32(DC_HPD6_INT_CONTROL); 3994 tmp |= DC_HPDx_INT_ACK; 3995 WREG32(DC_HPD6_INT_CONTROL, tmp); 3996 } 3997 if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG) { 3998 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0); 3999 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; 4000 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp); 4001 } 4002 if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG) { 4003 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1); 4004 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; 4005 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp); 4006 } 4007 } else { 4008 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) { 4009 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL); 4010 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; 4011 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); 4012 } 4013 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) { 4014 if (ASIC_IS_DCE3(rdev)) { 4015 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL); 4016 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; 4017 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp); 4018 } else { 4019 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL); 4020 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; 4021 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp); 4022 } 4023 } 4024 } 4025 } 4026 4027 void r600_irq_disable(struct radeon_device *rdev) 4028 { 4029 r600_disable_interrupts(rdev); 4030 /* Wait and acknowledge irq */ 4031 mdelay(1); 4032 r600_irq_ack(rdev); 4033 r600_disable_interrupt_state(rdev); 4034 } 4035 4036 static u32 r600_get_ih_wptr(struct radeon_device *rdev) 4037 { 4038 u32 wptr, tmp; 4039 4040 if (rdev->wb.enabled) 4041 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]); 4042 else 4043 wptr = RREG32(IH_RB_WPTR); 4044 4045 if (wptr & RB_OVERFLOW) { 4046 wptr &= ~RB_OVERFLOW; 4047 /* When a ring buffer overflow happen start parsing interrupt 4048 * from the last not overwritten vector (wptr + 16). Hopefully 4049 * this should allow us to catchup. 4050 */ 4051 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n", 4052 wptr, rdev->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask); 4053 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; 4054 tmp = RREG32(IH_RB_CNTL); 4055 tmp |= IH_WPTR_OVERFLOW_CLEAR; 4056 WREG32(IH_RB_CNTL, tmp); 4057 } 4058 return (wptr & rdev->ih.ptr_mask); 4059 } 4060 4061 /* r600 IV Ring 4062 * Each IV ring entry is 128 bits: 4063 * [7:0] - interrupt source id 4064 * [31:8] - reserved 4065 * [59:32] - interrupt source data 4066 * [127:60] - reserved 4067 * 4068 * The basic interrupt vector entries 4069 * are decoded as follows: 4070 * src_id src_data description 4071 * 1 0 D1 Vblank 4072 * 1 1 D1 Vline 4073 * 5 0 D2 Vblank 4074 * 5 1 D2 Vline 4075 * 19 0 FP Hot plug detection A 4076 * 19 1 FP Hot plug detection B 4077 * 19 2 DAC A auto-detection 4078 * 19 3 DAC B auto-detection 4079 * 21 4 HDMI block A 4080 * 21 5 HDMI block B 4081 * 176 - CP_INT RB 4082 * 177 - CP_INT IB1 4083 * 178 - CP_INT IB2 4084 * 181 - EOP Interrupt 4085 * 233 - GUI Idle 4086 * 4087 * Note, these are based on r600 and may need to be 4088 * adjusted or added to on newer asics 4089 */ 4090 4091 int r600_irq_process(struct radeon_device *rdev) 4092 { 4093 u32 wptr; 4094 u32 rptr; 4095 u32 src_id, src_data; 4096 u32 ring_index; 4097 bool queue_hotplug = false; 4098 bool queue_hdmi = false; 4099 bool queue_thermal = false; 4100 4101 if (!rdev->ih.enabled || rdev->shutdown) 4102 return IRQ_NONE; 4103 4104 /* No MSIs, need a dummy read to flush PCI DMAs */ 4105 if (!rdev->msi_enabled) 4106 RREG32(IH_RB_WPTR); 4107 4108 wptr = r600_get_ih_wptr(rdev); 4109 4110 restart_ih: 4111 /* is somebody else already processing irqs? */ 4112 if (atomic_xchg(&rdev->ih.lock, 1)) 4113 return IRQ_NONE; 4114 4115 rptr = rdev->ih.rptr; 4116 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr); 4117 4118 /* Order reading of wptr vs. reading of IH ring data */ 4119 rmb(); 4120 4121 /* display interrupts */ 4122 r600_irq_ack(rdev); 4123 4124 while (rptr != wptr) { 4125 /* wptr/rptr are in bytes! */ 4126 ring_index = rptr / 4; 4127 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff; 4128 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff; 4129 4130 switch (src_id) { 4131 case 1: /* D1 vblank/vline */ 4132 switch (src_data) { 4133 case 0: /* D1 vblank */ 4134 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)) 4135 DRM_DEBUG("IH: D1 vblank - IH event w/o asserted irq bit?\n"); 4136 4137 if (rdev->irq.crtc_vblank_int[0]) { 4138 drm_handle_vblank(rdev->ddev, 0); 4139 rdev->pm.vblank_sync = true; 4140 wake_up(&rdev->irq.vblank_queue); 4141 } 4142 if (atomic_read(&rdev->irq.pflip[0])) 4143 radeon_crtc_handle_vblank(rdev, 0); 4144 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT; 4145 DRM_DEBUG("IH: D1 vblank\n"); 4146 4147 break; 4148 case 1: /* D1 vline */ 4149 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT)) 4150 DRM_DEBUG("IH: D1 vline - IH event w/o asserted irq bit?\n"); 4151 4152 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT; 4153 DRM_DEBUG("IH: D1 vline\n"); 4154 4155 break; 4156 default: 4157 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 4158 break; 4159 } 4160 break; 4161 case 5: /* D2 vblank/vline */ 4162 switch (src_data) { 4163 case 0: /* D2 vblank */ 4164 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT)) 4165 DRM_DEBUG("IH: D2 vblank - IH event w/o asserted irq bit?\n"); 4166 4167 if (rdev->irq.crtc_vblank_int[1]) { 4168 drm_handle_vblank(rdev->ddev, 1); 4169 rdev->pm.vblank_sync = true; 4170 wake_up(&rdev->irq.vblank_queue); 4171 } 4172 if (atomic_read(&rdev->irq.pflip[1])) 4173 radeon_crtc_handle_vblank(rdev, 1); 4174 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT; 4175 DRM_DEBUG("IH: D2 vblank\n"); 4176 4177 break; 4178 case 1: /* D1 vline */ 4179 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT)) 4180 DRM_DEBUG("IH: D2 vline - IH event w/o asserted irq bit?\n"); 4181 4182 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT; 4183 DRM_DEBUG("IH: D2 vline\n"); 4184 4185 break; 4186 default: 4187 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 4188 break; 4189 } 4190 break; 4191 case 9: /* D1 pflip */ 4192 DRM_DEBUG("IH: D1 flip\n"); 4193 if (radeon_use_pflipirq > 0) 4194 radeon_crtc_handle_flip(rdev, 0); 4195 break; 4196 case 11: /* D2 pflip */ 4197 DRM_DEBUG("IH: D2 flip\n"); 4198 if (radeon_use_pflipirq > 0) 4199 radeon_crtc_handle_flip(rdev, 1); 4200 break; 4201 case 19: /* HPD/DAC hotplug */ 4202 switch (src_data) { 4203 case 0: 4204 if (!(rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT)) 4205 DRM_DEBUG("IH: HPD1 - IH event w/o asserted irq bit?\n"); 4206 4207 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT; 4208 queue_hotplug = true; 4209 DRM_DEBUG("IH: HPD1\n"); 4210 break; 4211 case 1: 4212 if (!(rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT)) 4213 DRM_DEBUG("IH: HPD2 - IH event w/o asserted irq bit?\n"); 4214 4215 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT; 4216 queue_hotplug = true; 4217 DRM_DEBUG("IH: HPD2\n"); 4218 break; 4219 case 4: 4220 if (!(rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT)) 4221 DRM_DEBUG("IH: HPD3 - IH event w/o asserted irq bit?\n"); 4222 4223 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT; 4224 queue_hotplug = true; 4225 DRM_DEBUG("IH: HPD3\n"); 4226 break; 4227 case 5: 4228 if (!(rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT)) 4229 DRM_DEBUG("IH: HPD4 - IH event w/o asserted irq bit?\n"); 4230 4231 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT; 4232 queue_hotplug = true; 4233 DRM_DEBUG("IH: HPD4\n"); 4234 break; 4235 case 10: 4236 if (!(rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT)) 4237 DRM_DEBUG("IH: HPD5 - IH event w/o asserted irq bit?\n"); 4238 4239 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT; 4240 queue_hotplug = true; 4241 DRM_DEBUG("IH: HPD5\n"); 4242 break; 4243 case 12: 4244 if (!(rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT)) 4245 DRM_DEBUG("IH: HPD6 - IH event w/o asserted irq bit?\n"); 4246 4247 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT; 4248 queue_hotplug = true; 4249 DRM_DEBUG("IH: HPD6\n"); 4250 4251 break; 4252 default: 4253 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 4254 break; 4255 } 4256 break; 4257 case 21: /* hdmi */ 4258 switch (src_data) { 4259 case 4: 4260 if (!(rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG)) 4261 DRM_DEBUG("IH: HDMI0 - IH event w/o asserted irq bit?\n"); 4262 4263 rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG; 4264 queue_hdmi = true; 4265 DRM_DEBUG("IH: HDMI0\n"); 4266 4267 break; 4268 case 5: 4269 if (!(rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG)) 4270 DRM_DEBUG("IH: HDMI1 - IH event w/o asserted irq bit?\n"); 4271 4272 rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG; 4273 queue_hdmi = true; 4274 DRM_DEBUG("IH: HDMI1\n"); 4275 4276 break; 4277 default: 4278 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); 4279 break; 4280 } 4281 break; 4282 case 124: /* UVD */ 4283 DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data); 4284 radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX); 4285 break; 4286 case 176: /* CP_INT in ring buffer */ 4287 case 177: /* CP_INT in IB1 */ 4288 case 178: /* CP_INT in IB2 */ 4289 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data); 4290 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 4291 break; 4292 case 181: /* CP EOP event */ 4293 DRM_DEBUG("IH: CP EOP\n"); 4294 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 4295 break; 4296 case 224: /* DMA trap event */ 4297 DRM_DEBUG("IH: DMA trap\n"); 4298 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX); 4299 break; 4300 case 230: /* thermal low to high */ 4301 DRM_DEBUG("IH: thermal low to high\n"); 4302 rdev->pm.dpm.thermal.high_to_low = false; 4303 queue_thermal = true; 4304 break; 4305 case 231: /* thermal high to low */ 4306 DRM_DEBUG("IH: thermal high to low\n"); 4307 rdev->pm.dpm.thermal.high_to_low = true; 4308 queue_thermal = true; 4309 break; 4310 case 233: /* GUI IDLE */ 4311 DRM_DEBUG("IH: GUI idle\n"); 4312 break; 4313 default: 4314 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 4315 break; 4316 } 4317 4318 /* wptr/rptr are in bytes! */ 4319 rptr += 16; 4320 rptr &= rdev->ih.ptr_mask; 4321 WREG32(IH_RB_RPTR, rptr); 4322 } 4323 if (queue_hotplug) 4324 schedule_delayed_work(&rdev->hotplug_work, 0); 4325 if (queue_hdmi) 4326 schedule_work(&rdev->audio_work); 4327 if (queue_thermal && rdev->pm.dpm_enabled) 4328 schedule_work(&rdev->pm.dpm.thermal.work); 4329 rdev->ih.rptr = rptr; 4330 atomic_set(&rdev->ih.lock, 0); 4331 4332 /* make sure wptr hasn't changed while processing */ 4333 wptr = r600_get_ih_wptr(rdev); 4334 if (wptr != rptr) 4335 goto restart_ih; 4336 4337 return IRQ_HANDLED; 4338 } 4339 4340 /* 4341 * Debugfs info 4342 */ 4343 #if defined(CONFIG_DEBUG_FS) 4344 4345 static int r600_debugfs_mc_info_show(struct seq_file *m, void *unused) 4346 { 4347 struct radeon_device *rdev = m->private; 4348 4349 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS); 4350 DREG32_SYS(m, rdev, VM_L2_STATUS); 4351 return 0; 4352 } 4353 4354 DEFINE_SHOW_ATTRIBUTE(r600_debugfs_mc_info); 4355 #endif 4356 4357 static void r600_debugfs_mc_info_init(struct radeon_device *rdev) 4358 { 4359 #if defined(CONFIG_DEBUG_FS) 4360 struct dentry *root = rdev->ddev->primary->debugfs_root; 4361 4362 debugfs_create_file("r600_mc_info", 0444, root, rdev, 4363 &r600_debugfs_mc_info_fops); 4364 4365 #endif 4366 } 4367 4368 /** 4369 * r600_mmio_hdp_flush - flush Host Data Path cache via MMIO 4370 * @rdev: radeon device structure 4371 * 4372 * Some R6XX/R7XX don't seem to take into account HDP flushes performed 4373 * through the ring buffer. This leads to corruption in rendering, see 4374 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 . To avoid this, we 4375 * directly perform the HDP flush by writing the register through MMIO. 4376 */ 4377 void r600_mmio_hdp_flush(struct radeon_device *rdev) 4378 { 4379 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read 4380 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL. 4381 * This seems to cause problems on some AGP cards. Just use the old 4382 * method for them. 4383 */ 4384 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) && 4385 rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) { 4386 void __iomem *ptr = (void *)rdev->vram_scratch.ptr; 4387 4388 WREG32(HDP_DEBUG1, 0); 4389 readl((void __iomem *)ptr); 4390 } else 4391 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); 4392 } 4393 4394 void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes) 4395 { 4396 u32 link_width_cntl, mask; 4397 4398 if (rdev->flags & RADEON_IS_IGP) 4399 return; 4400 4401 if (!(rdev->flags & RADEON_IS_PCIE)) 4402 return; 4403 4404 /* x2 cards have a special sequence */ 4405 if (ASIC_IS_X2(rdev)) 4406 return; 4407 4408 radeon_gui_idle(rdev); 4409 4410 switch (lanes) { 4411 case 0: 4412 mask = RADEON_PCIE_LC_LINK_WIDTH_X0; 4413 break; 4414 case 1: 4415 mask = RADEON_PCIE_LC_LINK_WIDTH_X1; 4416 break; 4417 case 2: 4418 mask = RADEON_PCIE_LC_LINK_WIDTH_X2; 4419 break; 4420 case 4: 4421 mask = RADEON_PCIE_LC_LINK_WIDTH_X4; 4422 break; 4423 case 8: 4424 mask = RADEON_PCIE_LC_LINK_WIDTH_X8; 4425 break; 4426 case 12: 4427 /* not actually supported */ 4428 mask = RADEON_PCIE_LC_LINK_WIDTH_X12; 4429 break; 4430 case 16: 4431 mask = RADEON_PCIE_LC_LINK_WIDTH_X16; 4432 break; 4433 default: 4434 DRM_ERROR("invalid pcie lane request: %d\n", lanes); 4435 return; 4436 } 4437 4438 link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 4439 link_width_cntl &= ~RADEON_PCIE_LC_LINK_WIDTH_MASK; 4440 link_width_cntl |= mask << RADEON_PCIE_LC_LINK_WIDTH_SHIFT; 4441 link_width_cntl |= (RADEON_PCIE_LC_RECONFIG_NOW | 4442 R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE); 4443 4444 WREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4445 } 4446 4447 int r600_get_pcie_lanes(struct radeon_device *rdev) 4448 { 4449 u32 link_width_cntl; 4450 4451 if (rdev->flags & RADEON_IS_IGP) 4452 return 0; 4453 4454 if (!(rdev->flags & RADEON_IS_PCIE)) 4455 return 0; 4456 4457 /* x2 cards have a special sequence */ 4458 if (ASIC_IS_X2(rdev)) 4459 return 0; 4460 4461 radeon_gui_idle(rdev); 4462 4463 link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 4464 4465 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) { 4466 case RADEON_PCIE_LC_LINK_WIDTH_X1: 4467 return 1; 4468 case RADEON_PCIE_LC_LINK_WIDTH_X2: 4469 return 2; 4470 case RADEON_PCIE_LC_LINK_WIDTH_X4: 4471 return 4; 4472 case RADEON_PCIE_LC_LINK_WIDTH_X8: 4473 return 8; 4474 case RADEON_PCIE_LC_LINK_WIDTH_X12: 4475 /* not actually supported */ 4476 return 12; 4477 case RADEON_PCIE_LC_LINK_WIDTH_X0: 4478 case RADEON_PCIE_LC_LINK_WIDTH_X16: 4479 default: 4480 return 16; 4481 } 4482 } 4483 4484 static void r600_pcie_gen2_enable(struct radeon_device *rdev) 4485 { 4486 u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp; 4487 u16 link_cntl2; 4488 4489 if (radeon_pcie_gen2 == 0) 4490 return; 4491 4492 if (rdev->flags & RADEON_IS_IGP) 4493 return; 4494 4495 if (!(rdev->flags & RADEON_IS_PCIE)) 4496 return; 4497 4498 /* x2 cards have a special sequence */ 4499 if (ASIC_IS_X2(rdev)) 4500 return; 4501 4502 /* only RV6xx+ chips are supported */ 4503 if (rdev->family <= CHIP_R600) 4504 return; 4505 4506 if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) && 4507 (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT)) 4508 return; 4509 4510 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 4511 if (speed_cntl & LC_CURRENT_DATA_RATE) { 4512 DRM_INFO("PCIE gen 2 link speeds already enabled\n"); 4513 return; 4514 } 4515 4516 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"); 4517 4518 /* 55 nm r6xx asics */ 4519 if ((rdev->family == CHIP_RV670) || 4520 (rdev->family == CHIP_RV620) || 4521 (rdev->family == CHIP_RV635)) { 4522 /* advertise upconfig capability */ 4523 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); 4524 link_width_cntl &= ~LC_UPCONFIGURE_DIS; 4525 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4526 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); 4527 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) { 4528 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; 4529 link_width_cntl &= ~(LC_LINK_WIDTH_MASK | 4530 LC_RECONFIG_ARC_MISSING_ESCAPE); 4531 link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN; 4532 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4533 } else { 4534 link_width_cntl |= LC_UPCONFIGURE_DIS; 4535 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4536 } 4537 } 4538 4539 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 4540 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) && 4541 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { 4542 4543 /* 55 nm r6xx asics */ 4544 if ((rdev->family == CHIP_RV670) || 4545 (rdev->family == CHIP_RV620) || 4546 (rdev->family == CHIP_RV635)) { 4547 WREG32(MM_CFGREGS_CNTL, 0x8); 4548 link_cntl2 = RREG32(0x4088); 4549 WREG32(MM_CFGREGS_CNTL, 0); 4550 /* not supported yet */ 4551 if (link_cntl2 & SELECTABLE_DEEMPHASIS) 4552 return; 4553 } 4554 4555 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK; 4556 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT); 4557 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK; 4558 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE; 4559 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE; 4560 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 4561 4562 tmp = RREG32(0x541c); 4563 WREG32(0x541c, tmp | 0x8); 4564 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN); 4565 link_cntl2 = RREG16(0x4088); 4566 link_cntl2 &= ~TARGET_LINK_SPEED_MASK; 4567 link_cntl2 |= 0x2; 4568 WREG16(0x4088, link_cntl2); 4569 WREG32(MM_CFGREGS_CNTL, 0); 4570 4571 if ((rdev->family == CHIP_RV670) || 4572 (rdev->family == CHIP_RV620) || 4573 (rdev->family == CHIP_RV635)) { 4574 training_cntl = RREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL); 4575 training_cntl &= ~LC_POINT_7_PLUS_EN; 4576 WREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL, training_cntl); 4577 } else { 4578 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 4579 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN; 4580 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 4581 } 4582 4583 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 4584 speed_cntl |= LC_GEN2_EN_STRAP; 4585 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 4586 4587 } else { 4588 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); 4589 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */ 4590 if (1) 4591 link_width_cntl |= LC_UPCONFIGURE_DIS; 4592 else 4593 link_width_cntl &= ~LC_UPCONFIGURE_DIS; 4594 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4595 } 4596 } 4597 4598 /** 4599 * r600_get_gpu_clock_counter - return GPU clock counter snapshot 4600 * 4601 * @rdev: radeon_device pointer 4602 * 4603 * Fetches a GPU clock counter snapshot (R6xx-cayman). 4604 * Returns the 64 bit clock counter snapshot. 4605 */ 4606 uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev) 4607 { 4608 uint64_t clock; 4609 4610 mutex_lock(&rdev->gpu_clock_mutex); 4611 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1); 4612 clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) | 4613 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 4614 mutex_unlock(&rdev->gpu_clock_mutex); 4615 return clock; 4616 } 4617