1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include "drmP.h" 29 #include "radeon.h" 30 #include "atom.h" 31 #include "r520d.h" 32 33 /* This files gather functions specifics to: r520,rv530,rv560,rv570,r580 */ 34 35 static int r520_mc_wait_for_idle(struct radeon_device *rdev) 36 { 37 unsigned i; 38 uint32_t tmp; 39 40 for (i = 0; i < rdev->usec_timeout; i++) { 41 /* read MC_STATUS */ 42 tmp = RREG32_MC(R520_MC_STATUS); 43 if (tmp & R520_MC_STATUS_IDLE) { 44 return 0; 45 } 46 DRM_UDELAY(1); 47 } 48 return -1; 49 } 50 51 static void r520_gpu_init(struct radeon_device *rdev) 52 { 53 unsigned pipe_select_current, gb_pipe_select, tmp; 54 55 r100_hdp_reset(rdev); 56 rv515_vga_render_disable(rdev); 57 /* 58 * DST_PIPE_CONFIG 0x170C 59 * GB_TILE_CONFIG 0x4018 60 * GB_FIFO_SIZE 0x4024 61 * GB_PIPE_SELECT 0x402C 62 * GB_PIPE_SELECT2 0x4124 63 * Z_PIPE_SHIFT 0 64 * Z_PIPE_MASK 0x000000003 65 * GB_FIFO_SIZE2 0x4128 66 * SC_SFIFO_SIZE_SHIFT 0 67 * SC_SFIFO_SIZE_MASK 0x000000003 68 * SC_MFIFO_SIZE_SHIFT 2 69 * SC_MFIFO_SIZE_MASK 0x00000000C 70 * FG_SFIFO_SIZE_SHIFT 4 71 * FG_SFIFO_SIZE_MASK 0x000000030 72 * ZB_MFIFO_SIZE_SHIFT 6 73 * ZB_MFIFO_SIZE_MASK 0x0000000C0 74 * GA_ENHANCE 0x4274 75 * SU_REG_DEST 0x42C8 76 */ 77 /* workaround for RV530 */ 78 if (rdev->family == CHIP_RV530) { 79 WREG32(0x4128, 0xFF); 80 } 81 r420_pipes_init(rdev); 82 gb_pipe_select = RREG32(0x402C); 83 tmp = RREG32(0x170C); 84 pipe_select_current = (tmp >> 2) & 3; 85 tmp = (1 << pipe_select_current) | 86 (((gb_pipe_select >> 8) & 0xF) << 4); 87 WREG32_PLL(0x000D, tmp); 88 if (r520_mc_wait_for_idle(rdev)) { 89 printk(KERN_WARNING "Failed to wait MC idle while " 90 "programming pipes. Bad things might happen.\n"); 91 } 92 } 93 94 static void r520_vram_get_type(struct radeon_device *rdev) 95 { 96 uint32_t tmp; 97 98 rdev->mc.vram_width = 128; 99 rdev->mc.vram_is_ddr = true; 100 tmp = RREG32_MC(R520_MC_CNTL0); 101 switch ((tmp & R520_MEM_NUM_CHANNELS_MASK) >> R520_MEM_NUM_CHANNELS_SHIFT) { 102 case 0: 103 rdev->mc.vram_width = 32; 104 break; 105 case 1: 106 rdev->mc.vram_width = 64; 107 break; 108 case 2: 109 rdev->mc.vram_width = 128; 110 break; 111 case 3: 112 rdev->mc.vram_width = 256; 113 break; 114 default: 115 rdev->mc.vram_width = 128; 116 break; 117 } 118 if (tmp & R520_MC_CHANNEL_SIZE) 119 rdev->mc.vram_width *= 2; 120 } 121 122 void r520_mc_init(struct radeon_device *rdev) 123 { 124 fixed20_12 a; 125 126 r520_vram_get_type(rdev); 127 r100_vram_init_sizes(rdev); 128 radeon_vram_location(rdev, &rdev->mc, 0); 129 if (!(rdev->flags & RADEON_IS_AGP)) 130 radeon_gtt_location(rdev, &rdev->mc); 131 /* FIXME: we should enforce default clock in case GPU is not in 132 * default setup 133 */ 134 a.full = rfixed_const(100); 135 rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk); 136 rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); 137 } 138 139 void r520_mc_program(struct radeon_device *rdev) 140 { 141 struct rv515_mc_save save; 142 143 /* Stops all mc clients */ 144 rv515_mc_stop(rdev, &save); 145 146 /* Wait for mc idle */ 147 if (r520_mc_wait_for_idle(rdev)) 148 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); 149 /* Write VRAM size in case we are limiting it */ 150 WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size); 151 /* Program MC, should be a 32bits limited address space */ 152 WREG32_MC(R_000004_MC_FB_LOCATION, 153 S_000004_MC_FB_START(rdev->mc.vram_start >> 16) | 154 S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16)); 155 WREG32(R_000134_HDP_FB_LOCATION, 156 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); 157 if (rdev->flags & RADEON_IS_AGP) { 158 WREG32_MC(R_000005_MC_AGP_LOCATION, 159 S_000005_MC_AGP_START(rdev->mc.gtt_start >> 16) | 160 S_000005_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); 161 WREG32_MC(R_000006_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); 162 WREG32_MC(R_000007_AGP_BASE_2, 163 S_000007_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base))); 164 } else { 165 WREG32_MC(R_000005_MC_AGP_LOCATION, 0xFFFFFFFF); 166 WREG32_MC(R_000006_AGP_BASE, 0); 167 WREG32_MC(R_000007_AGP_BASE_2, 0); 168 } 169 170 rv515_mc_resume(rdev, &save); 171 } 172 173 static int r520_startup(struct radeon_device *rdev) 174 { 175 int r; 176 177 r520_mc_program(rdev); 178 /* Resume clock */ 179 rv515_clock_startup(rdev); 180 /* Initialize GPU configuration (# pipes, ...) */ 181 r520_gpu_init(rdev); 182 /* Initialize GART (initialize after TTM so we can allocate 183 * memory through TTM but finalize after TTM) */ 184 if (rdev->flags & RADEON_IS_PCIE) { 185 r = rv370_pcie_gart_enable(rdev); 186 if (r) 187 return r; 188 } 189 /* Enable IRQ */ 190 rs600_irq_set(rdev); 191 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 192 /* 1M ring buffer */ 193 r = r100_cp_init(rdev, 1024 * 1024); 194 if (r) { 195 dev_err(rdev->dev, "failled initializing CP (%d).\n", r); 196 return r; 197 } 198 r = r100_wb_init(rdev); 199 if (r) 200 dev_err(rdev->dev, "failled initializing WB (%d).\n", r); 201 r = r100_ib_init(rdev); 202 if (r) { 203 dev_err(rdev->dev, "failled initializing IB (%d).\n", r); 204 return r; 205 } 206 return 0; 207 } 208 209 int r520_resume(struct radeon_device *rdev) 210 { 211 /* Make sur GART are not working */ 212 if (rdev->flags & RADEON_IS_PCIE) 213 rv370_pcie_gart_disable(rdev); 214 /* Resume clock before doing reset */ 215 rv515_clock_startup(rdev); 216 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 217 if (radeon_gpu_reset(rdev)) { 218 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 219 RREG32(R_000E40_RBBM_STATUS), 220 RREG32(R_0007C0_CP_STAT)); 221 } 222 /* post */ 223 atom_asic_init(rdev->mode_info.atom_context); 224 /* Resume clock after posting */ 225 rv515_clock_startup(rdev); 226 /* Initialize surface registers */ 227 radeon_surface_init(rdev); 228 return r520_startup(rdev); 229 } 230 231 int r520_init(struct radeon_device *rdev) 232 { 233 int r; 234 235 /* Initialize scratch registers */ 236 radeon_scratch_init(rdev); 237 /* Initialize surface registers */ 238 radeon_surface_init(rdev); 239 /* TODO: disable VGA need to use VGA request */ 240 /* BIOS*/ 241 if (!radeon_get_bios(rdev)) { 242 if (ASIC_IS_AVIVO(rdev)) 243 return -EINVAL; 244 } 245 if (rdev->is_atom_bios) { 246 r = radeon_atombios_init(rdev); 247 if (r) 248 return r; 249 } else { 250 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n"); 251 return -EINVAL; 252 } 253 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 254 if (radeon_gpu_reset(rdev)) { 255 dev_warn(rdev->dev, 256 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 257 RREG32(R_000E40_RBBM_STATUS), 258 RREG32(R_0007C0_CP_STAT)); 259 } 260 /* check if cards are posted or not */ 261 if (radeon_boot_test_post_card(rdev) == false) 262 return -EINVAL; 263 264 if (!radeon_card_posted(rdev) && rdev->bios) { 265 DRM_INFO("GPU not posted. posting now...\n"); 266 atom_asic_init(rdev->mode_info.atom_context); 267 } 268 /* Initialize clocks */ 269 radeon_get_clock_info(rdev->ddev); 270 /* Initialize power management */ 271 radeon_pm_init(rdev); 272 /* initialize AGP */ 273 if (rdev->flags & RADEON_IS_AGP) { 274 r = radeon_agp_init(rdev); 275 if (r) { 276 radeon_agp_disable(rdev); 277 } 278 } 279 /* initialize memory controller */ 280 r520_mc_init(rdev); 281 rv515_debugfs(rdev); 282 /* Fence driver */ 283 r = radeon_fence_driver_init(rdev); 284 if (r) 285 return r; 286 r = radeon_irq_kms_init(rdev); 287 if (r) 288 return r; 289 /* Memory manager */ 290 r = radeon_bo_init(rdev); 291 if (r) 292 return r; 293 r = rv370_pcie_gart_init(rdev); 294 if (r) 295 return r; 296 rv515_set_safe_registers(rdev); 297 rdev->accel_working = true; 298 r = r520_startup(rdev); 299 if (r) { 300 /* Somethings want wront with the accel init stop accel */ 301 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 302 r100_cp_fini(rdev); 303 r100_wb_fini(rdev); 304 r100_ib_fini(rdev); 305 radeon_irq_kms_fini(rdev); 306 rv370_pcie_gart_fini(rdev); 307 radeon_agp_fini(rdev); 308 rdev->accel_working = false; 309 } 310 return 0; 311 } 312