1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include "drmP.h" 29 #include "radeon.h" 30 #include "radeon_asic.h" 31 #include "atom.h" 32 #include "r520d.h" 33 34 /* This files gather functions specifics to: r520,rv530,rv560,rv570,r580 */ 35 36 static int r520_mc_wait_for_idle(struct radeon_device *rdev) 37 { 38 unsigned i; 39 uint32_t tmp; 40 41 for (i = 0; i < rdev->usec_timeout; i++) { 42 /* read MC_STATUS */ 43 tmp = RREG32_MC(R520_MC_STATUS); 44 if (tmp & R520_MC_STATUS_IDLE) { 45 return 0; 46 } 47 DRM_UDELAY(1); 48 } 49 return -1; 50 } 51 52 static void r520_gpu_init(struct radeon_device *rdev) 53 { 54 unsigned pipe_select_current, gb_pipe_select, tmp; 55 56 r100_hdp_reset(rdev); 57 rv515_vga_render_disable(rdev); 58 /* 59 * DST_PIPE_CONFIG 0x170C 60 * GB_TILE_CONFIG 0x4018 61 * GB_FIFO_SIZE 0x4024 62 * GB_PIPE_SELECT 0x402C 63 * GB_PIPE_SELECT2 0x4124 64 * Z_PIPE_SHIFT 0 65 * Z_PIPE_MASK 0x000000003 66 * GB_FIFO_SIZE2 0x4128 67 * SC_SFIFO_SIZE_SHIFT 0 68 * SC_SFIFO_SIZE_MASK 0x000000003 69 * SC_MFIFO_SIZE_SHIFT 2 70 * SC_MFIFO_SIZE_MASK 0x00000000C 71 * FG_SFIFO_SIZE_SHIFT 4 72 * FG_SFIFO_SIZE_MASK 0x000000030 73 * ZB_MFIFO_SIZE_SHIFT 6 74 * ZB_MFIFO_SIZE_MASK 0x0000000C0 75 * GA_ENHANCE 0x4274 76 * SU_REG_DEST 0x42C8 77 */ 78 /* workaround for RV530 */ 79 if (rdev->family == CHIP_RV530) { 80 WREG32(0x4128, 0xFF); 81 } 82 r420_pipes_init(rdev); 83 gb_pipe_select = RREG32(0x402C); 84 tmp = RREG32(0x170C); 85 pipe_select_current = (tmp >> 2) & 3; 86 tmp = (1 << pipe_select_current) | 87 (((gb_pipe_select >> 8) & 0xF) << 4); 88 WREG32_PLL(0x000D, tmp); 89 if (r520_mc_wait_for_idle(rdev)) { 90 printk(KERN_WARNING "Failed to wait MC idle while " 91 "programming pipes. Bad things might happen.\n"); 92 } 93 } 94 95 static void r520_vram_get_type(struct radeon_device *rdev) 96 { 97 uint32_t tmp; 98 99 rdev->mc.vram_width = 128; 100 rdev->mc.vram_is_ddr = true; 101 tmp = RREG32_MC(R520_MC_CNTL0); 102 switch ((tmp & R520_MEM_NUM_CHANNELS_MASK) >> R520_MEM_NUM_CHANNELS_SHIFT) { 103 case 0: 104 rdev->mc.vram_width = 32; 105 break; 106 case 1: 107 rdev->mc.vram_width = 64; 108 break; 109 case 2: 110 rdev->mc.vram_width = 128; 111 break; 112 case 3: 113 rdev->mc.vram_width = 256; 114 break; 115 default: 116 rdev->mc.vram_width = 128; 117 break; 118 } 119 if (tmp & R520_MC_CHANNEL_SIZE) 120 rdev->mc.vram_width *= 2; 121 } 122 123 void r520_mc_init(struct radeon_device *rdev) 124 { 125 fixed20_12 a; 126 127 r520_vram_get_type(rdev); 128 r100_vram_init_sizes(rdev); 129 radeon_vram_location(rdev, &rdev->mc, 0); 130 if (!(rdev->flags & RADEON_IS_AGP)) 131 radeon_gtt_location(rdev, &rdev->mc); 132 /* FIXME: we should enforce default clock in case GPU is not in 133 * default setup 134 */ 135 a.full = rfixed_const(100); 136 rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk); 137 rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); 138 } 139 140 void r520_mc_program(struct radeon_device *rdev) 141 { 142 struct rv515_mc_save save; 143 144 /* Stops all mc clients */ 145 rv515_mc_stop(rdev, &save); 146 147 /* Wait for mc idle */ 148 if (r520_mc_wait_for_idle(rdev)) 149 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); 150 /* Write VRAM size in case we are limiting it */ 151 WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size); 152 /* Program MC, should be a 32bits limited address space */ 153 WREG32_MC(R_000004_MC_FB_LOCATION, 154 S_000004_MC_FB_START(rdev->mc.vram_start >> 16) | 155 S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16)); 156 WREG32(R_000134_HDP_FB_LOCATION, 157 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); 158 if (rdev->flags & RADEON_IS_AGP) { 159 WREG32_MC(R_000005_MC_AGP_LOCATION, 160 S_000005_MC_AGP_START(rdev->mc.gtt_start >> 16) | 161 S_000005_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); 162 WREG32_MC(R_000006_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); 163 WREG32_MC(R_000007_AGP_BASE_2, 164 S_000007_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base))); 165 } else { 166 WREG32_MC(R_000005_MC_AGP_LOCATION, 0xFFFFFFFF); 167 WREG32_MC(R_000006_AGP_BASE, 0); 168 WREG32_MC(R_000007_AGP_BASE_2, 0); 169 } 170 171 rv515_mc_resume(rdev, &save); 172 } 173 174 static int r520_startup(struct radeon_device *rdev) 175 { 176 int r; 177 178 r520_mc_program(rdev); 179 /* Resume clock */ 180 rv515_clock_startup(rdev); 181 /* Initialize GPU configuration (# pipes, ...) */ 182 r520_gpu_init(rdev); 183 /* Initialize GART (initialize after TTM so we can allocate 184 * memory through TTM but finalize after TTM) */ 185 if (rdev->flags & RADEON_IS_PCIE) { 186 r = rv370_pcie_gart_enable(rdev); 187 if (r) 188 return r; 189 } 190 /* Enable IRQ */ 191 rs600_irq_set(rdev); 192 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 193 /* 1M ring buffer */ 194 r = r100_cp_init(rdev, 1024 * 1024); 195 if (r) { 196 dev_err(rdev->dev, "failled initializing CP (%d).\n", r); 197 return r; 198 } 199 r = r100_wb_init(rdev); 200 if (r) 201 dev_err(rdev->dev, "failled initializing WB (%d).\n", r); 202 r = r100_ib_init(rdev); 203 if (r) { 204 dev_err(rdev->dev, "failled initializing IB (%d).\n", r); 205 return r; 206 } 207 return 0; 208 } 209 210 int r520_resume(struct radeon_device *rdev) 211 { 212 /* Make sur GART are not working */ 213 if (rdev->flags & RADEON_IS_PCIE) 214 rv370_pcie_gart_disable(rdev); 215 /* Resume clock before doing reset */ 216 rv515_clock_startup(rdev); 217 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 218 if (radeon_gpu_reset(rdev)) { 219 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 220 RREG32(R_000E40_RBBM_STATUS), 221 RREG32(R_0007C0_CP_STAT)); 222 } 223 /* post */ 224 atom_asic_init(rdev->mode_info.atom_context); 225 /* Resume clock after posting */ 226 rv515_clock_startup(rdev); 227 /* Initialize surface registers */ 228 radeon_surface_init(rdev); 229 return r520_startup(rdev); 230 } 231 232 int r520_init(struct radeon_device *rdev) 233 { 234 int r; 235 236 /* Initialize scratch registers */ 237 radeon_scratch_init(rdev); 238 /* Initialize surface registers */ 239 radeon_surface_init(rdev); 240 /* TODO: disable VGA need to use VGA request */ 241 /* BIOS*/ 242 if (!radeon_get_bios(rdev)) { 243 if (ASIC_IS_AVIVO(rdev)) 244 return -EINVAL; 245 } 246 if (rdev->is_atom_bios) { 247 r = radeon_atombios_init(rdev); 248 if (r) 249 return r; 250 } else { 251 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n"); 252 return -EINVAL; 253 } 254 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 255 if (radeon_gpu_reset(rdev)) { 256 dev_warn(rdev->dev, 257 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 258 RREG32(R_000E40_RBBM_STATUS), 259 RREG32(R_0007C0_CP_STAT)); 260 } 261 /* check if cards are posted or not */ 262 if (radeon_boot_test_post_card(rdev) == false) 263 return -EINVAL; 264 265 if (!radeon_card_posted(rdev) && rdev->bios) { 266 DRM_INFO("GPU not posted. posting now...\n"); 267 atom_asic_init(rdev->mode_info.atom_context); 268 } 269 /* Initialize clocks */ 270 radeon_get_clock_info(rdev->ddev); 271 /* Initialize power management */ 272 radeon_pm_init(rdev); 273 /* initialize AGP */ 274 if (rdev->flags & RADEON_IS_AGP) { 275 r = radeon_agp_init(rdev); 276 if (r) { 277 radeon_agp_disable(rdev); 278 } 279 } 280 /* initialize memory controller */ 281 r520_mc_init(rdev); 282 rv515_debugfs(rdev); 283 /* Fence driver */ 284 r = radeon_fence_driver_init(rdev); 285 if (r) 286 return r; 287 r = radeon_irq_kms_init(rdev); 288 if (r) 289 return r; 290 /* Memory manager */ 291 r = radeon_bo_init(rdev); 292 if (r) 293 return r; 294 r = rv370_pcie_gart_init(rdev); 295 if (r) 296 return r; 297 rv515_set_safe_registers(rdev); 298 rdev->accel_working = true; 299 r = r520_startup(rdev); 300 if (r) { 301 /* Somethings want wront with the accel init stop accel */ 302 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 303 r100_cp_fini(rdev); 304 r100_wb_fini(rdev); 305 r100_ib_fini(rdev); 306 radeon_irq_kms_fini(rdev); 307 rv370_pcie_gart_fini(rdev); 308 radeon_agp_fini(rdev); 309 rdev->accel_working = false; 310 } 311 return 0; 312 } 313