1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __R500_REG_H__ 29 #define __R500_REG_H__ 30 31 /* pipe config regs */ 32 #define R300_GA_POLY_MODE 0x4288 33 # define R300_FRONT_PTYPE_POINT (0 << 4) 34 # define R300_FRONT_PTYPE_LINE (1 << 4) 35 # define R300_FRONT_PTYPE_TRIANGE (2 << 4) 36 # define R300_BACK_PTYPE_POINT (0 << 7) 37 # define R300_BACK_PTYPE_LINE (1 << 7) 38 # define R300_BACK_PTYPE_TRIANGE (2 << 7) 39 #define R300_GA_ROUND_MODE 0x428c 40 # define R300_GEOMETRY_ROUND_TRUNC (0 << 0) 41 # define R300_GEOMETRY_ROUND_NEAREST (1 << 0) 42 # define R300_COLOR_ROUND_TRUNC (0 << 2) 43 # define R300_COLOR_ROUND_NEAREST (1 << 2) 44 #define R300_GB_MSPOS0 0x4010 45 # define R300_MS_X0_SHIFT 0 46 # define R300_MS_Y0_SHIFT 4 47 # define R300_MS_X1_SHIFT 8 48 # define R300_MS_Y1_SHIFT 12 49 # define R300_MS_X2_SHIFT 16 50 # define R300_MS_Y2_SHIFT 20 51 # define R300_MSBD0_Y_SHIFT 24 52 # define R300_MSBD0_X_SHIFT 28 53 #define R300_GB_MSPOS1 0x4014 54 # define R300_MS_X3_SHIFT 0 55 # define R300_MS_Y3_SHIFT 4 56 # define R300_MS_X4_SHIFT 8 57 # define R300_MS_Y4_SHIFT 12 58 # define R300_MS_X5_SHIFT 16 59 # define R300_MS_Y5_SHIFT 20 60 # define R300_MSBD1_SHIFT 24 61 62 #define R300_GA_ENHANCE 0x4274 63 # define R300_GA_DEADLOCK_CNTL (1 << 0) 64 # define R300_GA_FASTSYNC_CNTL (1 << 1) 65 #define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c 66 # define R300_RB3D_DC_FLUSH (2 << 0) 67 # define R300_RB3D_DC_FREE (2 << 2) 68 # define R300_RB3D_DC_FINISH (1 << 4) 69 #define R300_RB3D_ZCACHE_CTLSTAT 0x4f18 70 # define R300_ZC_FLUSH (1 << 0) 71 # define R300_ZC_FREE (1 << 1) 72 # define R300_ZC_FLUSH_ALL 0x3 73 #define R400_GB_PIPE_SELECT 0x402c 74 #define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */ 75 #define R500_SU_REG_DEST 0x42c8 76 #define R300_GB_TILE_CONFIG 0x4018 77 # define R300_ENABLE_TILING (1 << 0) 78 # define R300_PIPE_COUNT_RV350 (0 << 1) 79 # define R300_PIPE_COUNT_R300 (3 << 1) 80 # define R300_PIPE_COUNT_R420_3P (6 << 1) 81 # define R300_PIPE_COUNT_R420 (7 << 1) 82 # define R300_TILE_SIZE_8 (0 << 4) 83 # define R300_TILE_SIZE_16 (1 << 4) 84 # define R300_TILE_SIZE_32 (2 << 4) 85 # define R300_SUBPIXEL_1_12 (0 << 16) 86 # define R300_SUBPIXEL_1_16 (1 << 16) 87 #define R300_DST_PIPE_CONFIG 0x170c 88 # define R300_PIPE_AUTO_CONFIG (1 << 31) 89 #define R300_RB2D_DSTCACHE_MODE 0x3428 90 # define R300_DC_AUTOFLUSH_ENABLE (1 << 8) 91 # define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17) 92 93 #define RADEON_CP_STAT 0x7C0 94 #define RADEON_RBBM_CMDFIFO_ADDR 0xE70 95 #define RADEON_RBBM_CMDFIFO_DATA 0xE74 96 #define RADEON_ISYNC_CNTL 0x1724 97 # define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0) 98 # define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1) 99 # define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2) 100 # define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3) 101 # define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4) 102 # define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5) 103 104 #define RS480_NB_MC_INDEX 0x168 105 # define RS480_NB_MC_IND_WR_EN (1 << 8) 106 #define RS480_NB_MC_DATA 0x16c 107 108 /* 109 * RS690 110 */ 111 #define RS690_MCCFG_FB_LOCATION 0x100 112 #define RS690_MC_FB_START_MASK 0x0000FFFF 113 #define RS690_MC_FB_START_SHIFT 0 114 #define RS690_MC_FB_TOP_MASK 0xFFFF0000 115 #define RS690_MC_FB_TOP_SHIFT 16 116 #define RS690_MCCFG_AGP_LOCATION 0x101 117 #define RS690_MC_AGP_START_MASK 0x0000FFFF 118 #define RS690_MC_AGP_START_SHIFT 0 119 #define RS690_MC_AGP_TOP_MASK 0xFFFF0000 120 #define RS690_MC_AGP_TOP_SHIFT 16 121 #define RS690_MCCFG_AGP_BASE 0x102 122 #define RS690_MCCFG_AGP_BASE_2 0x103 123 #define RS690_MC_INIT_MISC_LAT_TIMER 0x104 124 #define RS690_HDP_FB_LOCATION 0x0134 125 #define RS690_MC_INDEX 0x78 126 # define RS690_MC_INDEX_MASK 0x1ff 127 # define RS690_MC_INDEX_WR_EN (1 << 9) 128 # define RS690_MC_INDEX_WR_ACK 0x7f 129 #define RS690_MC_DATA 0x7c 130 #define RS690_MC_STATUS 0x90 131 #define RS690_MC_STATUS_IDLE (1 << 0) 132 #define RS480_AGP_BASE_2 0x0164 133 #define RS480_MC_MISC_CNTL 0x18 134 # define RS480_DISABLE_GTW (1 << 1) 135 # define RS480_GART_INDEX_REG_EN (1 << 12) 136 # define RS690_BLOCK_GFX_D3_EN (1 << 14) 137 #define RS480_GART_FEATURE_ID 0x2b 138 # define RS480_HANG_EN (1 << 11) 139 # define RS480_TLB_ENABLE (1 << 18) 140 # define RS480_P2P_ENABLE (1 << 19) 141 # define RS480_GTW_LAC_EN (1 << 25) 142 # define RS480_2LEVEL_GART (0 << 30) 143 # define RS480_1LEVEL_GART (1 << 30) 144 # define RS480_PDC_EN (1 << 31) 145 #define RS480_GART_BASE 0x2c 146 #define RS480_GART_CACHE_CNTRL 0x2e 147 # define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */ 148 #define RS480_AGP_ADDRESS_SPACE_SIZE 0x38 149 # define RS480_GART_EN (1 << 0) 150 # define RS480_VA_SIZE_32MB (0 << 1) 151 # define RS480_VA_SIZE_64MB (1 << 1) 152 # define RS480_VA_SIZE_128MB (2 << 1) 153 # define RS480_VA_SIZE_256MB (3 << 1) 154 # define RS480_VA_SIZE_512MB (4 << 1) 155 # define RS480_VA_SIZE_1GB (5 << 1) 156 # define RS480_VA_SIZE_2GB (6 << 1) 157 #define RS480_AGP_MODE_CNTL 0x39 158 # define RS480_POST_GART_Q_SIZE (1 << 18) 159 # define RS480_NONGART_SNOOP (1 << 19) 160 # define RS480_AGP_RD_BUF_SIZE (1 << 20) 161 # define RS480_REQ_TYPE_SNOOP_SHIFT 22 162 # define RS480_REQ_TYPE_SNOOP_MASK 0x3 163 # define RS480_REQ_TYPE_SNOOP_DIS (1 << 24) 164 165 #define RS690_AIC_CTRL_SCRATCH 0x3A 166 # define RS690_DIS_OUT_OF_PCI_GART_ACCESS (1 << 1) 167 168 /* 169 * RS600 170 */ 171 #define RS600_MC_STATUS 0x0 172 #define RS600_MC_STATUS_IDLE (1 << 0) 173 #define RS600_MC_INDEX 0x70 174 # define RS600_MC_ADDR_MASK 0xffff 175 # define RS600_MC_IND_SEQ_RBS_0 (1 << 16) 176 # define RS600_MC_IND_SEQ_RBS_1 (1 << 17) 177 # define RS600_MC_IND_SEQ_RBS_2 (1 << 18) 178 # define RS600_MC_IND_SEQ_RBS_3 (1 << 19) 179 # define RS600_MC_IND_AIC_RBS (1 << 20) 180 # define RS600_MC_IND_CITF_ARB0 (1 << 21) 181 # define RS600_MC_IND_CITF_ARB1 (1 << 22) 182 # define RS600_MC_IND_WR_EN (1 << 23) 183 #define RS600_MC_DATA 0x74 184 #define RS600_MC_STATUS 0x0 185 # define RS600_MC_IDLE (1 << 1) 186 #define RS600_MC_FB_LOCATION 0x4 187 #define RS600_MC_FB_START_MASK 0x0000FFFF 188 #define RS600_MC_FB_START_SHIFT 0 189 #define RS600_MC_FB_TOP_MASK 0xFFFF0000 190 #define RS600_MC_FB_TOP_SHIFT 16 191 #define RS600_MC_AGP_LOCATION 0x5 192 #define RS600_MC_AGP_START_MASK 0x0000FFFF 193 #define RS600_MC_AGP_START_SHIFT 0 194 #define RS600_MC_AGP_TOP_MASK 0xFFFF0000 195 #define RS600_MC_AGP_TOP_SHIFT 16 196 #define RS600_MC_AGP_BASE 0x6 197 #define RS600_MC_AGP_BASE_2 0x7 198 #define RS600_MC_CNTL1 0x9 199 # define RS600_ENABLE_PAGE_TABLES (1 << 26) 200 #define RS600_MC_PT0_CNTL 0x100 201 # define RS600_ENABLE_PT (1 << 0) 202 # define RS600_EFFECTIVE_L2_CACHE_SIZE(x) ((x) << 15) 203 # define RS600_EFFECTIVE_L2_QUEUE_SIZE(x) ((x) << 21) 204 # define RS600_INVALIDATE_ALL_L1_TLBS (1 << 28) 205 # define RS600_INVALIDATE_L2_CACHE (1 << 29) 206 #define RS600_MC_PT0_CONTEXT0_CNTL 0x102 207 # define RS600_ENABLE_PAGE_TABLE (1 << 0) 208 # define RS600_PAGE_TABLE_TYPE_FLAT (0 << 1) 209 #define RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR 0x112 210 #define RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR 0x114 211 #define RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR 0x11c 212 #define RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR 0x12c 213 #define RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR 0x13c 214 #define RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR 0x14c 215 #define RS600_MC_PT0_CLIENT0_CNTL 0x16c 216 # define RS600_ENABLE_TRANSLATION_MODE_OVERRIDE (1 << 0) 217 # define RS600_TRANSLATION_MODE_OVERRIDE (1 << 1) 218 # define RS600_SYSTEM_ACCESS_MODE_MASK (3 << 8) 219 # define RS600_SYSTEM_ACCESS_MODE_PA_ONLY (0 << 8) 220 # define RS600_SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 8) 221 # define RS600_SYSTEM_ACCESS_MODE_IN_SYS (2 << 8) 222 # define RS600_SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 8) 223 # define RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASSTHROUGH (0 << 10) 224 # define RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 10) 225 # define RS600_EFFECTIVE_L1_CACHE_SIZE(x) ((x) << 11) 226 # define RS600_ENABLE_FRAGMENT_PROCESSING (1 << 14) 227 # define RS600_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 15) 228 # define RS600_INVALIDATE_L1_TLB (1 << 20) 229 /* rs600/rs690/rs740 */ 230 # define RS600_BUS_MASTER_DIS (1 << 14) 231 # define RS600_MSI_REARM (1 << 20) 232 /* see RS400_MSI_REARM in AIC_CNTL for rs480 */ 233 234 235 236 #define RV515_MC_FB_LOCATION 0x01 237 #define RV515_MC_FB_START_MASK 0x0000FFFF 238 #define RV515_MC_FB_START_SHIFT 0 239 #define RV515_MC_FB_TOP_MASK 0xFFFF0000 240 #define RV515_MC_FB_TOP_SHIFT 16 241 #define RV515_MC_AGP_LOCATION 0x02 242 #define RV515_MC_AGP_START_MASK 0x0000FFFF 243 #define RV515_MC_AGP_START_SHIFT 0 244 #define RV515_MC_AGP_TOP_MASK 0xFFFF0000 245 #define RV515_MC_AGP_TOP_SHIFT 16 246 #define RV515_MC_AGP_BASE 0x03 247 #define RV515_MC_AGP_BASE_2 0x04 248 249 #define R520_MC_FB_LOCATION 0x04 250 #define R520_MC_FB_START_MASK 0x0000FFFF 251 #define R520_MC_FB_START_SHIFT 0 252 #define R520_MC_FB_TOP_MASK 0xFFFF0000 253 #define R520_MC_FB_TOP_SHIFT 16 254 #define R520_MC_AGP_LOCATION 0x05 255 #define R520_MC_AGP_START_MASK 0x0000FFFF 256 #define R520_MC_AGP_START_SHIFT 0 257 #define R520_MC_AGP_TOP_MASK 0xFFFF0000 258 #define R520_MC_AGP_TOP_SHIFT 16 259 #define R520_MC_AGP_BASE 0x06 260 #define R520_MC_AGP_BASE_2 0x07 261 262 263 #define AVIVO_MC_INDEX 0x0070 264 #define R520_MC_STATUS 0x00 265 #define R520_MC_STATUS_IDLE (1<<1) 266 #define RV515_MC_STATUS 0x08 267 #define RV515_MC_STATUS_IDLE (1<<4) 268 #define RV515_MC_INIT_MISC_LAT_TIMER 0x09 269 #define AVIVO_MC_DATA 0x0074 270 271 #define R520_MC_IND_INDEX 0x70 272 #define R520_MC_IND_WR_EN (1 << 24) 273 #define R520_MC_IND_DATA 0x74 274 275 #define RV515_MC_CNTL 0x5 276 # define RV515_MEM_NUM_CHANNELS_MASK 0x3 277 #define R520_MC_CNTL0 0x8 278 # define R520_MEM_NUM_CHANNELS_MASK (0x3 << 24) 279 # define R520_MEM_NUM_CHANNELS_SHIFT 24 280 # define R520_MC_CHANNEL_SIZE (1 << 23) 281 282 #define AVIVO_CP_DYN_CNTL 0x000f /* PLL */ 283 # define AVIVO_CP_FORCEON (1 << 0) 284 #define AVIVO_E2_DYN_CNTL 0x0011 /* PLL */ 285 # define AVIVO_E2_FORCEON (1 << 0) 286 #define AVIVO_IDCT_DYN_CNTL 0x0013 /* PLL */ 287 # define AVIVO_IDCT_FORCEON (1 << 0) 288 289 #define AVIVO_HDP_FB_LOCATION 0x134 290 291 #define AVIVO_VGA_RENDER_CONTROL 0x0300 292 # define AVIVO_VGA_VSTATUS_CNTL_MASK (3 << 16) 293 #define AVIVO_D1VGA_CONTROL 0x0330 294 # define AVIVO_DVGA_CONTROL_MODE_ENABLE (1<<0) 295 # define AVIVO_DVGA_CONTROL_TIMING_SELECT (1<<8) 296 # define AVIVO_DVGA_CONTROL_SYNC_POLARITY_SELECT (1<<9) 297 # define AVIVO_DVGA_CONTROL_OVERSCAN_TIMING_SELECT (1<<10) 298 # define AVIVO_DVGA_CONTROL_OVERSCAN_COLOR_EN (1<<16) 299 # define AVIVO_DVGA_CONTROL_ROTATE (1<<24) 300 #define AVIVO_D2VGA_CONTROL 0x0338 301 302 #define AVIVO_EXT1_PPLL_REF_DIV_SRC 0x400 303 #define AVIVO_EXT1_PPLL_REF_DIV 0x404 304 #define AVIVO_EXT1_PPLL_UPDATE_LOCK 0x408 305 #define AVIVO_EXT1_PPLL_UPDATE_CNTL 0x40c 306 307 #define AVIVO_EXT2_PPLL_REF_DIV_SRC 0x410 308 #define AVIVO_EXT2_PPLL_REF_DIV 0x414 309 #define AVIVO_EXT2_PPLL_UPDATE_LOCK 0x418 310 #define AVIVO_EXT2_PPLL_UPDATE_CNTL 0x41c 311 312 #define AVIVO_EXT1_PPLL_FB_DIV 0x430 313 #define AVIVO_EXT2_PPLL_FB_DIV 0x434 314 315 #define AVIVO_EXT1_PPLL_POST_DIV_SRC 0x438 316 #define AVIVO_EXT1_PPLL_POST_DIV 0x43c 317 318 #define AVIVO_EXT2_PPLL_POST_DIV_SRC 0x440 319 #define AVIVO_EXT2_PPLL_POST_DIV 0x444 320 321 #define AVIVO_EXT1_PPLL_CNTL 0x448 322 #define AVIVO_EXT2_PPLL_CNTL 0x44c 323 324 #define AVIVO_P1PLL_CNTL 0x450 325 #define AVIVO_P2PLL_CNTL 0x454 326 #define AVIVO_P1PLL_INT_SS_CNTL 0x458 327 #define AVIVO_P2PLL_INT_SS_CNTL 0x45c 328 #define AVIVO_P1PLL_TMDSA_CNTL 0x460 329 #define AVIVO_P2PLL_LVTMA_CNTL 0x464 330 331 #define AVIVO_PCLK_CRTC1_CNTL 0x480 332 #define AVIVO_PCLK_CRTC2_CNTL 0x484 333 334 #define AVIVO_D1CRTC_H_TOTAL 0x6000 335 #define AVIVO_D1CRTC_H_BLANK_START_END 0x6004 336 #define AVIVO_D1CRTC_H_SYNC_A 0x6008 337 #define AVIVO_D1CRTC_H_SYNC_A_CNTL 0x600c 338 #define AVIVO_D1CRTC_H_SYNC_B 0x6010 339 #define AVIVO_D1CRTC_H_SYNC_B_CNTL 0x6014 340 341 #define AVIVO_D1CRTC_V_TOTAL 0x6020 342 #define AVIVO_D1CRTC_V_BLANK_START_END 0x6024 343 #define AVIVO_D1CRTC_V_SYNC_A 0x6028 344 #define AVIVO_D1CRTC_V_SYNC_A_CNTL 0x602c 345 #define AVIVO_D1CRTC_V_SYNC_B 0x6030 346 #define AVIVO_D1CRTC_V_SYNC_B_CNTL 0x6034 347 348 #define AVIVO_D1CRTC_CONTROL 0x6080 349 # define AVIVO_CRTC_EN (1 << 0) 350 #define AVIVO_D1CRTC_BLANK_CONTROL 0x6084 351 #define AVIVO_D1CRTC_INTERLACE_CONTROL 0x6088 352 #define AVIVO_D1CRTC_INTERLACE_STATUS 0x608c 353 #define AVIVO_D1CRTC_FRAME_COUNT 0x60a4 354 #define AVIVO_D1CRTC_STEREO_CONTROL 0x60c4 355 356 /* master controls */ 357 #define AVIVO_DC_CRTC_MASTER_EN 0x60f8 358 #define AVIVO_DC_CRTC_TV_CONTROL 0x60fc 359 360 #define AVIVO_D1GRPH_ENABLE 0x6100 361 #define AVIVO_D1GRPH_CONTROL 0x6104 362 # define AVIVO_D1GRPH_CONTROL_DEPTH_8BPP (0 << 0) 363 # define AVIVO_D1GRPH_CONTROL_DEPTH_16BPP (1 << 0) 364 # define AVIVO_D1GRPH_CONTROL_DEPTH_32BPP (2 << 0) 365 # define AVIVO_D1GRPH_CONTROL_DEPTH_64BPP (3 << 0) 366 367 # define AVIVO_D1GRPH_CONTROL_8BPP_INDEXED (0 << 8) 368 369 # define AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555 (0 << 8) 370 # define AVIVO_D1GRPH_CONTROL_16BPP_RGB565 (1 << 8) 371 # define AVIVO_D1GRPH_CONTROL_16BPP_ARGB4444 (2 << 8) 372 # define AVIVO_D1GRPH_CONTROL_16BPP_AI88 (3 << 8) 373 # define AVIVO_D1GRPH_CONTROL_16BPP_MONO16 (4 << 8) 374 375 # define AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888 (0 << 8) 376 # define AVIVO_D1GRPH_CONTROL_32BPP_ARGB2101010 (1 << 8) 377 # define AVIVO_D1GRPH_CONTROL_32BPP_DIGITAL (2 << 8) 378 # define AVIVO_D1GRPH_CONTROL_32BPP_8B_ARGB2101010 (3 << 8) 379 380 381 # define AVIVO_D1GRPH_CONTROL_64BPP_ARGB16161616 (0 << 8) 382 383 # define AVIVO_D1GRPH_SWAP_RB (1 << 16) 384 # define AVIVO_D1GRPH_TILED (1 << 20) 385 # define AVIVO_D1GRPH_MACRO_ADDRESS_MODE (1 << 21) 386 387 /* The R7xx *_HIGH surface regs are backwards; the D1 regs are in the D2 388 * block and vice versa. This applies to GRPH, CUR, etc. 389 */ 390 #define AVIVO_D1GRPH_LUT_SEL 0x6108 391 #define AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110 392 #define R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6914 393 #define R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6114 394 #define AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118 395 #define R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x691c 396 #define R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x611c 397 #define AVIVO_D1GRPH_PITCH 0x6120 398 #define AVIVO_D1GRPH_SURFACE_OFFSET_X 0x6124 399 #define AVIVO_D1GRPH_SURFACE_OFFSET_Y 0x6128 400 #define AVIVO_D1GRPH_X_START 0x612c 401 #define AVIVO_D1GRPH_Y_START 0x6130 402 #define AVIVO_D1GRPH_X_END 0x6134 403 #define AVIVO_D1GRPH_Y_END 0x6138 404 #define AVIVO_D1GRPH_UPDATE 0x6144 405 # define AVIVO_D1GRPH_UPDATE_LOCK (1 << 16) 406 #define AVIVO_D1GRPH_FLIP_CONTROL 0x6148 407 408 #define AVIVO_D1CUR_CONTROL 0x6400 409 # define AVIVO_D1CURSOR_EN (1 << 0) 410 # define AVIVO_D1CURSOR_MODE_SHIFT 8 411 # define AVIVO_D1CURSOR_MODE_MASK (3 << 8) 412 # define AVIVO_D1CURSOR_MODE_24BPP 2 413 #define AVIVO_D1CUR_SURFACE_ADDRESS 0x6408 414 #define R700_D1CUR_SURFACE_ADDRESS_HIGH 0x6c0c 415 #define R700_D2CUR_SURFACE_ADDRESS_HIGH 0x640c 416 #define AVIVO_D1CUR_SIZE 0x6410 417 #define AVIVO_D1CUR_POSITION 0x6414 418 #define AVIVO_D1CUR_HOT_SPOT 0x6418 419 #define AVIVO_D1CUR_UPDATE 0x6424 420 # define AVIVO_D1CURSOR_UPDATE_LOCK (1 << 16) 421 422 #define AVIVO_DC_LUT_RW_SELECT 0x6480 423 #define AVIVO_DC_LUT_RW_MODE 0x6484 424 #define AVIVO_DC_LUT_RW_INDEX 0x6488 425 #define AVIVO_DC_LUT_SEQ_COLOR 0x648c 426 #define AVIVO_DC_LUT_PWL_DATA 0x6490 427 #define AVIVO_DC_LUT_30_COLOR 0x6494 428 #define AVIVO_DC_LUT_READ_PIPE_SELECT 0x6498 429 #define AVIVO_DC_LUT_WRITE_EN_MASK 0x649c 430 #define AVIVO_DC_LUT_AUTOFILL 0x64a0 431 432 #define AVIVO_DC_LUTA_CONTROL 0x64c0 433 #define AVIVO_DC_LUTA_BLACK_OFFSET_BLUE 0x64c4 434 #define AVIVO_DC_LUTA_BLACK_OFFSET_GREEN 0x64c8 435 #define AVIVO_DC_LUTA_BLACK_OFFSET_RED 0x64cc 436 #define AVIVO_DC_LUTA_WHITE_OFFSET_BLUE 0x64d0 437 #define AVIVO_DC_LUTA_WHITE_OFFSET_GREEN 0x64d4 438 #define AVIVO_DC_LUTA_WHITE_OFFSET_RED 0x64d8 439 440 #define AVIVO_DC_LB_MEMORY_SPLIT 0x6520 441 # define AVIVO_DC_LB_MEMORY_SPLIT_MASK 0x3 442 # define AVIVO_DC_LB_MEMORY_SPLIT_SHIFT 0 443 # define AVIVO_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF 0 444 # define AVIVO_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q 1 445 # define AVIVO_DC_LB_MEMORY_SPLIT_D1_ONLY 2 446 # define AVIVO_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q 3 447 # define AVIVO_DC_LB_MEMORY_SPLIT_SHIFT_MODE (1 << 2) 448 # define AVIVO_DC_LB_DISP1_END_ADR_SHIFT 4 449 # define AVIVO_DC_LB_DISP1_END_ADR_MASK 0x7ff 450 451 #define AVIVO_D1MODE_DATA_FORMAT 0x6528 452 # define AVIVO_D1MODE_INTERLEAVE_EN (1 << 0) 453 #define AVIVO_D1MODE_DESKTOP_HEIGHT 0x652C 454 #define AVIVO_D1MODE_VBLANK_STATUS 0x6534 455 # define AVIVO_VBLANK_ACK (1 << 4) 456 #define AVIVO_D1MODE_VLINE_START_END 0x6538 457 #define AVIVO_D1MODE_VLINE_STATUS 0x653c 458 # define AVIVO_D1MODE_VLINE_STAT (1 << 12) 459 #define AVIVO_DxMODE_INT_MASK 0x6540 460 # define AVIVO_D1MODE_INT_MASK (1 << 0) 461 # define AVIVO_D2MODE_INT_MASK (1 << 8) 462 #define AVIVO_D1MODE_VIEWPORT_START 0x6580 463 #define AVIVO_D1MODE_VIEWPORT_SIZE 0x6584 464 #define AVIVO_D1MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6588 465 #define AVIVO_D1MODE_EXT_OVERSCAN_TOP_BOTTOM 0x658c 466 467 #define AVIVO_D1SCL_SCALER_ENABLE 0x6590 468 #define AVIVO_D1SCL_SCALER_TAP_CONTROL 0x6594 469 #define AVIVO_D1SCL_UPDATE 0x65cc 470 # define AVIVO_D1SCL_UPDATE_LOCK (1 << 16) 471 472 /* second crtc */ 473 #define AVIVO_D2CRTC_H_TOTAL 0x6800 474 #define AVIVO_D2CRTC_H_BLANK_START_END 0x6804 475 #define AVIVO_D2CRTC_H_SYNC_A 0x6808 476 #define AVIVO_D2CRTC_H_SYNC_A_CNTL 0x680c 477 #define AVIVO_D2CRTC_H_SYNC_B 0x6810 478 #define AVIVO_D2CRTC_H_SYNC_B_CNTL 0x6814 479 480 #define AVIVO_D2CRTC_V_TOTAL 0x6820 481 #define AVIVO_D2CRTC_V_BLANK_START_END 0x6824 482 #define AVIVO_D2CRTC_V_SYNC_A 0x6828 483 #define AVIVO_D2CRTC_V_SYNC_A_CNTL 0x682c 484 #define AVIVO_D2CRTC_V_SYNC_B 0x6830 485 #define AVIVO_D2CRTC_V_SYNC_B_CNTL 0x6834 486 487 #define AVIVO_D2CRTC_CONTROL 0x6880 488 #define AVIVO_D2CRTC_BLANK_CONTROL 0x6884 489 #define AVIVO_D2CRTC_INTERLACE_CONTROL 0x6888 490 #define AVIVO_D2CRTC_INTERLACE_STATUS 0x688c 491 #define AVIVO_D2CRTC_FRAME_COUNT 0x68a4 492 #define AVIVO_D2CRTC_STEREO_CONTROL 0x68c4 493 494 #define AVIVO_D2GRPH_ENABLE 0x6900 495 #define AVIVO_D2GRPH_CONTROL 0x6904 496 #define AVIVO_D2GRPH_LUT_SEL 0x6908 497 #define AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS 0x6910 498 #define AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS 0x6918 499 #define AVIVO_D2GRPH_PITCH 0x6920 500 #define AVIVO_D2GRPH_SURFACE_OFFSET_X 0x6924 501 #define AVIVO_D2GRPH_SURFACE_OFFSET_Y 0x6928 502 #define AVIVO_D2GRPH_X_START 0x692c 503 #define AVIVO_D2GRPH_Y_START 0x6930 504 #define AVIVO_D2GRPH_X_END 0x6934 505 #define AVIVO_D2GRPH_Y_END 0x6938 506 #define AVIVO_D2GRPH_UPDATE 0x6944 507 #define AVIVO_D2GRPH_FLIP_CONTROL 0x6948 508 509 #define AVIVO_D2CUR_CONTROL 0x6c00 510 #define AVIVO_D2CUR_SURFACE_ADDRESS 0x6c08 511 #define AVIVO_D2CUR_SIZE 0x6c10 512 #define AVIVO_D2CUR_POSITION 0x6c14 513 514 #define AVIVO_D2MODE_VBLANK_STATUS 0x6d34 515 #define AVIVO_D2MODE_VLINE_START_END 0x6d38 516 #define AVIVO_D2MODE_VLINE_STATUS 0x6d3c 517 #define AVIVO_D2MODE_VIEWPORT_START 0x6d80 518 #define AVIVO_D2MODE_VIEWPORT_SIZE 0x6d84 519 #define AVIVO_D2MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6d88 520 #define AVIVO_D2MODE_EXT_OVERSCAN_TOP_BOTTOM 0x6d8c 521 522 #define AVIVO_D2SCL_SCALER_ENABLE 0x6d90 523 #define AVIVO_D2SCL_SCALER_TAP_CONTROL 0x6d94 524 525 #define AVIVO_DDIA_BIT_DEPTH_CONTROL 0x7214 526 527 #define AVIVO_DACA_ENABLE 0x7800 528 # define AVIVO_DAC_ENABLE (1 << 0) 529 #define AVIVO_DACA_SOURCE_SELECT 0x7804 530 # define AVIVO_DAC_SOURCE_CRTC1 (0 << 0) 531 # define AVIVO_DAC_SOURCE_CRTC2 (1 << 0) 532 # define AVIVO_DAC_SOURCE_TV (2 << 0) 533 534 #define AVIVO_DACA_FORCE_OUTPUT_CNTL 0x783c 535 # define AVIVO_DACA_FORCE_OUTPUT_CNTL_FORCE_DATA_EN (1 << 0) 536 # define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT (8) 537 # define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE (1 << 0) 538 # define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN (1 << 1) 539 # define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_RED (1 << 2) 540 # define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY (1 << 24) 541 #define AVIVO_DACA_POWERDOWN 0x7850 542 # define AVIVO_DACA_POWERDOWN_POWERDOWN (1 << 0) 543 # define AVIVO_DACA_POWERDOWN_BLUE (1 << 8) 544 # define AVIVO_DACA_POWERDOWN_GREEN (1 << 16) 545 # define AVIVO_DACA_POWERDOWN_RED (1 << 24) 546 547 #define AVIVO_DACB_ENABLE 0x7a00 548 #define AVIVO_DACB_SOURCE_SELECT 0x7a04 549 #define AVIVO_DACB_FORCE_OUTPUT_CNTL 0x7a3c 550 # define AVIVO_DACB_FORCE_OUTPUT_CNTL_FORCE_DATA_EN (1 << 0) 551 # define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT (8) 552 # define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE (1 << 0) 553 # define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN (1 << 1) 554 # define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_RED (1 << 2) 555 # define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY (1 << 24) 556 #define AVIVO_DACB_POWERDOWN 0x7a50 557 # define AVIVO_DACB_POWERDOWN_POWERDOWN (1 << 0) 558 # define AVIVO_DACB_POWERDOWN_BLUE (1 << 8) 559 # define AVIVO_DACB_POWERDOWN_GREEN (1 << 16) 560 # define AVIVO_DACB_POWERDOWN_RED 561 562 #define AVIVO_TMDSA_CNTL 0x7880 563 # define AVIVO_TMDSA_CNTL_ENABLE (1 << 0) 564 # define AVIVO_TMDSA_CNTL_HPD_MASK (1 << 4) 565 # define AVIVO_TMDSA_CNTL_HPD_SELECT (1 << 8) 566 # define AVIVO_TMDSA_CNTL_SYNC_PHASE (1 << 12) 567 # define AVIVO_TMDSA_CNTL_PIXEL_ENCODING (1 << 16) 568 # define AVIVO_TMDSA_CNTL_DUAL_LINK_ENABLE (1 << 24) 569 # define AVIVO_TMDSA_CNTL_SWAP (1 << 28) 570 #define AVIVO_TMDSA_SOURCE_SELECT 0x7884 571 /* 78a8 appears to be some kind of (reasonably tolerant) clock? 572 * 78d0 definitely hits the transmitter, definitely clock. */ 573 /* MYSTERY1 This appears to control dithering? */ 574 #define AVIVO_TMDSA_BIT_DEPTH_CONTROL 0x7894 575 # define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN (1 << 0) 576 # define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH (1 << 4) 577 # define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN (1 << 8) 578 # define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH (1 << 12) 579 # define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN (1 << 16) 580 # define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 << 20) 581 # define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL (1 << 24) 582 # define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 << 26) 583 #define AVIVO_TMDSA_DCBALANCER_CONTROL 0x78d0 584 # define AVIVO_TMDSA_DCBALANCER_CONTROL_EN (1 << 0) 585 # define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_EN (1 << 8) 586 # define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_IN_SHIFT (16) 587 # define AVIVO_TMDSA_DCBALANCER_CONTROL_FORCE (1 << 24) 588 #define AVIVO_TMDSA_DATA_SYNCHRONIZATION 0x78d8 589 # define AVIVO_TMDSA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0) 590 # define AVIVO_TMDSA_DATA_SYNCHRONIZATION_PFREQCHG (1 << 8) 591 #define AVIVO_TMDSA_CLOCK_ENABLE 0x7900 592 #define AVIVO_TMDSA_TRANSMITTER_ENABLE 0x7904 593 # define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX0_ENABLE (1 << 0) 594 # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKC0EN (1 << 1) 595 # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD00EN (1 << 2) 596 # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD01EN (1 << 3) 597 # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD02EN (1 << 4) 598 # define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX1_ENABLE (1 << 8) 599 # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD10EN (1 << 10) 600 # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD11EN (1 << 11) 601 # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD12EN (1 << 12) 602 # define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX_ENABLE_HPD_MASK (1 << 16) 603 # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 << 17) 604 # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 << 18) 605 606 #define AVIVO_TMDSA_TRANSMITTER_CONTROL 0x7910 607 # define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_ENABLE (1 << 0) 608 # define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_RESET (1 << 1) 609 # define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT (2) 610 # define AVIVO_TMDSA_TRANSMITTER_CONTROL_IDSCKSEL (1 << 4) 611 # define AVIVO_TMDSA_TRANSMITTER_CONTROL_BGSLEEP (1 << 5) 612 # define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN (1 << 6) 613 # define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK (1 << 8) 614 # define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS (1 << 13) 615 # define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK (1 << 14) 616 # define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS (1 << 15) 617 # define AVIVO_TMDSA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16) 618 # define AVIVO_TMDSA_TRANSMITTER_CONTROL_BYPASS_PLL (1 << 28) 619 # define AVIVO_TMDSA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29) 620 # define AVIVO_TMDSA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31) 621 622 #define AVIVO_LVTMA_CNTL 0x7a80 623 # define AVIVO_LVTMA_CNTL_ENABLE (1 << 0) 624 # define AVIVO_LVTMA_CNTL_HPD_MASK (1 << 4) 625 # define AVIVO_LVTMA_CNTL_HPD_SELECT (1 << 8) 626 # define AVIVO_LVTMA_CNTL_SYNC_PHASE (1 << 12) 627 # define AVIVO_LVTMA_CNTL_PIXEL_ENCODING (1 << 16) 628 # define AVIVO_LVTMA_CNTL_DUAL_LINK_ENABLE (1 << 24) 629 # define AVIVO_LVTMA_CNTL_SWAP (1 << 28) 630 #define AVIVO_LVTMA_SOURCE_SELECT 0x7a84 631 #define AVIVO_LVTMA_COLOR_FORMAT 0x7a88 632 #define AVIVO_LVTMA_BIT_DEPTH_CONTROL 0x7a94 633 # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN (1 << 0) 634 # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH (1 << 4) 635 # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN (1 << 8) 636 # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH (1 << 12) 637 # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN (1 << 16) 638 # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 << 20) 639 # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL (1 << 24) 640 # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 << 26) 641 642 643 644 #define AVIVO_LVTMA_DCBALANCER_CONTROL 0x7ad0 645 # define AVIVO_LVTMA_DCBALANCER_CONTROL_EN (1 << 0) 646 # define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_EN (1 << 8) 647 # define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_IN_SHIFT (16) 648 # define AVIVO_LVTMA_DCBALANCER_CONTROL_FORCE (1 << 24) 649 650 #define AVIVO_LVTMA_DATA_SYNCHRONIZATION 0x78d8 651 # define AVIVO_LVTMA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0) 652 # define AVIVO_LVTMA_DATA_SYNCHRONIZATION_PFREQCHG (1 << 8) 653 #define R500_LVTMA_CLOCK_ENABLE 0x7b00 654 #define R600_LVTMA_CLOCK_ENABLE 0x7b04 655 656 #define R500_LVTMA_TRANSMITTER_ENABLE 0x7b04 657 #define R600_LVTMA_TRANSMITTER_ENABLE 0x7b08 658 # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC0EN (1 << 1) 659 # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD00EN (1 << 2) 660 # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD01EN (1 << 3) 661 # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD02EN (1 << 4) 662 # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD03EN (1 << 5) 663 # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC1EN (1 << 9) 664 # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD10EN (1 << 10) 665 # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD11EN (1 << 11) 666 # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD12EN (1 << 12) 667 # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 << 17) 668 # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 << 18) 669 670 #define R500_LVTMA_TRANSMITTER_CONTROL 0x7b10 671 #define R600_LVTMA_TRANSMITTER_CONTROL 0x7b14 672 # define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_ENABLE (1 << 0) 673 # define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_RESET (1 << 1) 674 # define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT (2) 675 # define AVIVO_LVTMA_TRANSMITTER_CONTROL_IDSCKSEL (1 << 4) 676 # define AVIVO_LVTMA_TRANSMITTER_CONTROL_BGSLEEP (1 << 5) 677 # define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN (1 << 6) 678 # define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK (1 << 8) 679 # define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS (1 << 13) 680 # define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK (1 << 14) 681 # define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS (1 << 15) 682 # define AVIVO_LVTMA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16) 683 # define AVIVO_LVTMA_TRANSMITTER_CONTROL_BYPASS_PLL (1 << 28) 684 # define AVIVO_LVTMA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29) 685 # define AVIVO_LVTMA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31) 686 687 #define R500_LVTMA_PWRSEQ_CNTL 0x7af0 688 #define R600_LVTMA_PWRSEQ_CNTL 0x7af4 689 # define AVIVO_LVTMA_PWRSEQ_EN (1 << 0) 690 # define AVIVO_LVTMA_PWRSEQ_PLL_ENABLE_MASK (1 << 2) 691 # define AVIVO_LVTMA_PWRSEQ_PLL_RESET_MASK (1 << 3) 692 # define AVIVO_LVTMA_PWRSEQ_TARGET_STATE (1 << 4) 693 # define AVIVO_LVTMA_SYNCEN (1 << 8) 694 # define AVIVO_LVTMA_SYNCEN_OVRD (1 << 9) 695 # define AVIVO_LVTMA_SYNCEN_POL (1 << 10) 696 # define AVIVO_LVTMA_DIGON (1 << 16) 697 # define AVIVO_LVTMA_DIGON_OVRD (1 << 17) 698 # define AVIVO_LVTMA_DIGON_POL (1 << 18) 699 # define AVIVO_LVTMA_BLON (1 << 24) 700 # define AVIVO_LVTMA_BLON_OVRD (1 << 25) 701 # define AVIVO_LVTMA_BLON_POL (1 << 26) 702 703 #define R500_LVTMA_PWRSEQ_STATE 0x7af4 704 #define R600_LVTMA_PWRSEQ_STATE 0x7af8 705 # define AVIVO_LVTMA_PWRSEQ_STATE_TARGET_STATE_R (1 << 0) 706 # define AVIVO_LVTMA_PWRSEQ_STATE_DIGON (1 << 1) 707 # define AVIVO_LVTMA_PWRSEQ_STATE_SYNCEN (1 << 2) 708 # define AVIVO_LVTMA_PWRSEQ_STATE_BLON (1 << 3) 709 # define AVIVO_LVTMA_PWRSEQ_STATE_DONE (1 << 4) 710 # define AVIVO_LVTMA_PWRSEQ_STATE_STATUS_SHIFT (8) 711 712 #define AVIVO_LVDS_BACKLIGHT_CNTL 0x7af8 713 # define AVIVO_LVDS_BACKLIGHT_CNTL_EN (1 << 0) 714 # define AVIVO_LVDS_BACKLIGHT_LEVEL_MASK 0x0000ff00 715 # define AVIVO_LVDS_BACKLIGHT_LEVEL_SHIFT 8 716 717 #define AVIVO_DVOA_BIT_DEPTH_CONTROL 0x7988 718 719 #define AVIVO_DC_GPIO_HPD_A 0x7e94 720 721 #define AVIVO_GPIO_0 0x7e30 722 #define AVIVO_GPIO_1 0x7e40 723 #define AVIVO_GPIO_2 0x7e50 724 #define AVIVO_GPIO_3 0x7e60 725 726 #define AVIVO_DC_GPIO_HPD_Y 0x7e9c 727 728 #define AVIVO_I2C_STATUS 0x7d30 729 # define AVIVO_I2C_STATUS_DONE (1 << 0) 730 # define AVIVO_I2C_STATUS_NACK (1 << 1) 731 # define AVIVO_I2C_STATUS_HALT (1 << 2) 732 # define AVIVO_I2C_STATUS_GO (1 << 3) 733 # define AVIVO_I2C_STATUS_MASK 0x7 734 /* If radeon_mm_i2c is to be believed, this is HALT, NACK, and maybe 735 * DONE? */ 736 # define AVIVO_I2C_STATUS_CMD_RESET 0x7 737 # define AVIVO_I2C_STATUS_CMD_WAIT (1 << 3) 738 #define AVIVO_I2C_STOP 0x7d34 739 #define AVIVO_I2C_START_CNTL 0x7d38 740 # define AVIVO_I2C_START (1 << 8) 741 # define AVIVO_I2C_CONNECTOR0 (0 << 16) 742 # define AVIVO_I2C_CONNECTOR1 (1 << 16) 743 #define R520_I2C_START (1<<0) 744 #define R520_I2C_STOP (1<<1) 745 #define R520_I2C_RX (1<<2) 746 #define R520_I2C_EN (1<<8) 747 #define R520_I2C_DDC1 (0<<16) 748 #define R520_I2C_DDC2 (1<<16) 749 #define R520_I2C_DDC3 (2<<16) 750 #define R520_I2C_DDC_MASK (3<<16) 751 #define AVIVO_I2C_CONTROL2 0x7d3c 752 # define AVIVO_I2C_7D3C_SIZE_SHIFT 8 753 # define AVIVO_I2C_7D3C_SIZE_MASK (0xf << 8) 754 #define AVIVO_I2C_CONTROL3 0x7d40 755 /* Reading is done 4 bytes at a time: read the bottom 8 bits from 756 * 7d44, four times in a row. 757 * Writing is a little more complex. First write DATA with 758 * 0xnnnnnnzz, then 0xnnnnnnyy, where nnnnnn is some non-deterministic 759 * magic number, zz is, I think, the slave address, and yy is the byte 760 * you want to write. */ 761 #define AVIVO_I2C_DATA 0x7d44 762 #define R520_I2C_ADDR_COUNT_MASK (0x7) 763 #define R520_I2C_DATA_COUNT_SHIFT (8) 764 #define R520_I2C_DATA_COUNT_MASK (0xF00) 765 #define AVIVO_I2C_CNTL 0x7d50 766 # define AVIVO_I2C_EN (1 << 0) 767 # define AVIVO_I2C_RESET (1 << 8) 768 769 #define AVIVO_DISP_INTERRUPT_STATUS 0x7edc 770 # define AVIVO_D1_VBLANK_INTERRUPT (1 << 4) 771 # define AVIVO_D2_VBLANK_INTERRUPT (1 << 5) 772 773 #endif 774