1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/seq_file.h> 29 #include <linux/slab.h> 30 #include <drm/drmP.h> 31 #include <drm/drm.h> 32 #include <drm/drm_crtc_helper.h> 33 #include "radeon_reg.h" 34 #include "radeon.h" 35 #include "radeon_asic.h" 36 #include <drm/radeon_drm.h> 37 #include "r100_track.h" 38 #include "r300d.h" 39 #include "rv350d.h" 40 #include "r300_reg_safe.h" 41 42 /* This files gather functions specifics to: r300,r350,rv350,rv370,rv380 43 * 44 * GPU Errata: 45 * - HOST_PATH_CNTL: r300 family seems to dislike write to HOST_PATH_CNTL 46 * using MMIO to flush host path read cache, this lead to HARDLOCKUP. 47 * However, scheduling such write to the ring seems harmless, i suspect 48 * the CP read collide with the flush somehow, or maybe the MC, hard to 49 * tell. (Jerome Glisse) 50 */ 51 52 /* 53 * Indirect registers accessor 54 */ 55 uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) 56 { 57 unsigned long flags; 58 uint32_t r; 59 60 spin_lock_irqsave(&rdev->pcie_idx_lock, flags); 61 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 62 r = RREG32(RADEON_PCIE_DATA); 63 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags); 64 return r; 65 } 66 67 void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 68 { 69 unsigned long flags; 70 71 spin_lock_irqsave(&rdev->pcie_idx_lock, flags); 72 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 73 WREG32(RADEON_PCIE_DATA, (v)); 74 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags); 75 } 76 77 /* 78 * rv370,rv380 PCIE GART 79 */ 80 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev); 81 82 void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev) 83 { 84 uint32_t tmp; 85 int i; 86 87 /* Workaround HW bug do flush 2 times */ 88 for (i = 0; i < 2; i++) { 89 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 90 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB); 91 (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 92 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); 93 } 94 mb(); 95 } 96 97 #define R300_PTE_UNSNOOPED (1 << 0) 98 #define R300_PTE_WRITEABLE (1 << 2) 99 #define R300_PTE_READABLE (1 << 3) 100 101 uint64_t rv370_pcie_gart_get_page_entry(uint64_t addr, uint32_t flags) 102 { 103 addr = (lower_32_bits(addr) >> 8) | 104 ((upper_32_bits(addr) & 0xff) << 24); 105 if (flags & RADEON_GART_PAGE_READ) 106 addr |= R300_PTE_READABLE; 107 if (flags & RADEON_GART_PAGE_WRITE) 108 addr |= R300_PTE_WRITEABLE; 109 if (!(flags & RADEON_GART_PAGE_SNOOP)) 110 addr |= R300_PTE_UNSNOOPED; 111 return addr; 112 } 113 114 void rv370_pcie_gart_set_page(struct radeon_device *rdev, unsigned i, 115 uint64_t entry) 116 { 117 void __iomem *ptr = rdev->gart.ptr; 118 119 /* on x86 we want this to be CPU endian, on powerpc 120 * on powerpc without HW swappers, it'll get swapped on way 121 * into VRAM - so no need for cpu_to_le32 on VRAM tables */ 122 writel(entry, ((void __iomem *)ptr) + (i * 4)); 123 } 124 125 int rv370_pcie_gart_init(struct radeon_device *rdev) 126 { 127 int r; 128 129 if (rdev->gart.robj) { 130 WARN(1, "RV370 PCIE GART already initialized\n"); 131 return 0; 132 } 133 /* Initialize common gart structure */ 134 r = radeon_gart_init(rdev); 135 if (r) 136 return r; 137 r = rv370_debugfs_pcie_gart_info_init(rdev); 138 if (r) 139 DRM_ERROR("Failed to register debugfs file for PCIE gart !\n"); 140 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; 141 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush; 142 rdev->asic->gart.get_page_entry = &rv370_pcie_gart_get_page_entry; 143 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page; 144 return radeon_gart_table_vram_alloc(rdev); 145 } 146 147 int rv370_pcie_gart_enable(struct radeon_device *rdev) 148 { 149 uint32_t table_addr; 150 uint32_t tmp; 151 int r; 152 153 if (rdev->gart.robj == NULL) { 154 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 155 return -EINVAL; 156 } 157 r = radeon_gart_table_vram_pin(rdev); 158 if (r) 159 return r; 160 /* discard memory request outside of configured range */ 161 tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; 162 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); 163 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start); 164 tmp = rdev->mc.gtt_end & ~RADEON_GPU_PAGE_MASK; 165 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp); 166 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0); 167 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0); 168 table_addr = rdev->gart.table_addr; 169 WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr); 170 /* FIXME: setup default page */ 171 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start); 172 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0); 173 /* Clear error */ 174 WREG32_PCIE(RADEON_PCIE_TX_GART_ERROR, 0); 175 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 176 tmp |= RADEON_PCIE_TX_GART_EN; 177 tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; 178 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); 179 rv370_pcie_gart_tlb_flush(rdev); 180 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 181 (unsigned)(rdev->mc.gtt_size >> 20), 182 (unsigned long long)table_addr); 183 rdev->gart.ready = true; 184 return 0; 185 } 186 187 void rv370_pcie_gart_disable(struct radeon_device *rdev) 188 { 189 u32 tmp; 190 191 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, 0); 192 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, 0); 193 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0); 194 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0); 195 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 196 tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; 197 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN); 198 radeon_gart_table_vram_unpin(rdev); 199 } 200 201 void rv370_pcie_gart_fini(struct radeon_device *rdev) 202 { 203 radeon_gart_fini(rdev); 204 rv370_pcie_gart_disable(rdev); 205 radeon_gart_table_vram_free(rdev); 206 } 207 208 void r300_fence_ring_emit(struct radeon_device *rdev, 209 struct radeon_fence *fence) 210 { 211 struct radeon_ring *ring = &rdev->ring[fence->ring]; 212 213 /* Who ever call radeon_fence_emit should call ring_lock and ask 214 * for enough space (today caller are ib schedule and buffer move) */ 215 /* Write SC register so SC & US assert idle */ 216 radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_TL, 0)); 217 radeon_ring_write(ring, 0); 218 radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_BR, 0)); 219 radeon_ring_write(ring, 0); 220 /* Flush 3D cache */ 221 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 222 radeon_ring_write(ring, R300_RB3D_DC_FLUSH); 223 radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); 224 radeon_ring_write(ring, R300_ZC_FLUSH); 225 /* Wait until IDLE & CLEAN */ 226 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); 227 radeon_ring_write(ring, (RADEON_WAIT_3D_IDLECLEAN | 228 RADEON_WAIT_2D_IDLECLEAN | 229 RADEON_WAIT_DMA_GUI_IDLE)); 230 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); 231 radeon_ring_write(ring, rdev->config.r300.hdp_cntl | 232 RADEON_HDP_READ_BUFFER_INVALIDATE); 233 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); 234 radeon_ring_write(ring, rdev->config.r300.hdp_cntl); 235 /* Emit fence sequence & fire IRQ */ 236 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0)); 237 radeon_ring_write(ring, fence->seq); 238 radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0)); 239 radeon_ring_write(ring, RADEON_SW_INT_FIRE); 240 } 241 242 void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring) 243 { 244 unsigned gb_tile_config; 245 int r; 246 247 /* Sub pixel 1/12 so we can have 4K rendering according to doc */ 248 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16); 249 switch(rdev->num_gb_pipes) { 250 case 2: 251 gb_tile_config |= R300_PIPE_COUNT_R300; 252 break; 253 case 3: 254 gb_tile_config |= R300_PIPE_COUNT_R420_3P; 255 break; 256 case 4: 257 gb_tile_config |= R300_PIPE_COUNT_R420; 258 break; 259 case 1: 260 default: 261 gb_tile_config |= R300_PIPE_COUNT_RV350; 262 break; 263 } 264 265 r = radeon_ring_lock(rdev, ring, 64); 266 if (r) { 267 return; 268 } 269 radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0)); 270 radeon_ring_write(ring, 271 RADEON_ISYNC_ANY2D_IDLE3D | 272 RADEON_ISYNC_ANY3D_IDLE2D | 273 RADEON_ISYNC_WAIT_IDLEGUI | 274 RADEON_ISYNC_CPSCRATCH_IDLEGUI); 275 radeon_ring_write(ring, PACKET0(R300_GB_TILE_CONFIG, 0)); 276 radeon_ring_write(ring, gb_tile_config); 277 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); 278 radeon_ring_write(ring, 279 RADEON_WAIT_2D_IDLECLEAN | 280 RADEON_WAIT_3D_IDLECLEAN); 281 radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0)); 282 radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG); 283 radeon_ring_write(ring, PACKET0(R300_GB_SELECT, 0)); 284 radeon_ring_write(ring, 0); 285 radeon_ring_write(ring, PACKET0(R300_GB_ENABLE, 0)); 286 radeon_ring_write(ring, 0); 287 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 288 radeon_ring_write(ring, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); 289 radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); 290 radeon_ring_write(ring, R300_ZC_FLUSH | R300_ZC_FREE); 291 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); 292 radeon_ring_write(ring, 293 RADEON_WAIT_2D_IDLECLEAN | 294 RADEON_WAIT_3D_IDLECLEAN); 295 radeon_ring_write(ring, PACKET0(R300_GB_AA_CONFIG, 0)); 296 radeon_ring_write(ring, 0); 297 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 298 radeon_ring_write(ring, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); 299 radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); 300 radeon_ring_write(ring, R300_ZC_FLUSH | R300_ZC_FREE); 301 radeon_ring_write(ring, PACKET0(R300_GB_MSPOS0, 0)); 302 radeon_ring_write(ring, 303 ((6 << R300_MS_X0_SHIFT) | 304 (6 << R300_MS_Y0_SHIFT) | 305 (6 << R300_MS_X1_SHIFT) | 306 (6 << R300_MS_Y1_SHIFT) | 307 (6 << R300_MS_X2_SHIFT) | 308 (6 << R300_MS_Y2_SHIFT) | 309 (6 << R300_MSBD0_Y_SHIFT) | 310 (6 << R300_MSBD0_X_SHIFT))); 311 radeon_ring_write(ring, PACKET0(R300_GB_MSPOS1, 0)); 312 radeon_ring_write(ring, 313 ((6 << R300_MS_X3_SHIFT) | 314 (6 << R300_MS_Y3_SHIFT) | 315 (6 << R300_MS_X4_SHIFT) | 316 (6 << R300_MS_Y4_SHIFT) | 317 (6 << R300_MS_X5_SHIFT) | 318 (6 << R300_MS_Y5_SHIFT) | 319 (6 << R300_MSBD1_SHIFT))); 320 radeon_ring_write(ring, PACKET0(R300_GA_ENHANCE, 0)); 321 radeon_ring_write(ring, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL); 322 radeon_ring_write(ring, PACKET0(R300_GA_POLY_MODE, 0)); 323 radeon_ring_write(ring, 324 R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE); 325 radeon_ring_write(ring, PACKET0(R300_GA_ROUND_MODE, 0)); 326 radeon_ring_write(ring, 327 R300_GEOMETRY_ROUND_NEAREST | 328 R300_COLOR_ROUND_NEAREST); 329 radeon_ring_unlock_commit(rdev, ring, false); 330 } 331 332 static void r300_errata(struct radeon_device *rdev) 333 { 334 rdev->pll_errata = 0; 335 336 if (rdev->family == CHIP_R300 && 337 (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) { 338 rdev->pll_errata |= CHIP_ERRATA_R300_CG; 339 } 340 } 341 342 int r300_mc_wait_for_idle(struct radeon_device *rdev) 343 { 344 unsigned i; 345 uint32_t tmp; 346 347 for (i = 0; i < rdev->usec_timeout; i++) { 348 /* read MC_STATUS */ 349 tmp = RREG32(RADEON_MC_STATUS); 350 if (tmp & R300_MC_IDLE) { 351 return 0; 352 } 353 DRM_UDELAY(1); 354 } 355 return -1; 356 } 357 358 static void r300_gpu_init(struct radeon_device *rdev) 359 { 360 uint32_t gb_tile_config, tmp; 361 362 if ((rdev->family == CHIP_R300 && rdev->pdev->device != 0x4144) || 363 (rdev->family == CHIP_R350 && rdev->pdev->device != 0x4148)) { 364 /* r300,r350 */ 365 rdev->num_gb_pipes = 2; 366 } else { 367 /* rv350,rv370,rv380,r300 AD, r350 AH */ 368 rdev->num_gb_pipes = 1; 369 } 370 rdev->num_z_pipes = 1; 371 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16); 372 switch (rdev->num_gb_pipes) { 373 case 2: 374 gb_tile_config |= R300_PIPE_COUNT_R300; 375 break; 376 case 3: 377 gb_tile_config |= R300_PIPE_COUNT_R420_3P; 378 break; 379 case 4: 380 gb_tile_config |= R300_PIPE_COUNT_R420; 381 break; 382 default: 383 case 1: 384 gb_tile_config |= R300_PIPE_COUNT_RV350; 385 break; 386 } 387 WREG32(R300_GB_TILE_CONFIG, gb_tile_config); 388 389 if (r100_gui_wait_for_idle(rdev)) { 390 pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n"); 391 } 392 393 tmp = RREG32(R300_DST_PIPE_CONFIG); 394 WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG); 395 396 WREG32(R300_RB2D_DSTCACHE_MODE, 397 R300_DC_AUTOFLUSH_ENABLE | 398 R300_DC_DC_DISABLE_IGNORE_PE); 399 400 if (r100_gui_wait_for_idle(rdev)) { 401 pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n"); 402 } 403 if (r300_mc_wait_for_idle(rdev)) { 404 pr_warn("Failed to wait MC idle while programming pipes. Bad things might happen.\n"); 405 } 406 DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized\n", 407 rdev->num_gb_pipes, rdev->num_z_pipes); 408 } 409 410 int r300_asic_reset(struct radeon_device *rdev, bool hard) 411 { 412 struct r100_mc_save save; 413 u32 status, tmp; 414 int ret = 0; 415 416 status = RREG32(R_000E40_RBBM_STATUS); 417 if (!G_000E40_GUI_ACTIVE(status)) { 418 return 0; 419 } 420 r100_mc_stop(rdev, &save); 421 status = RREG32(R_000E40_RBBM_STATUS); 422 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 423 /* stop CP */ 424 WREG32(RADEON_CP_CSQ_CNTL, 0); 425 tmp = RREG32(RADEON_CP_RB_CNTL); 426 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); 427 WREG32(RADEON_CP_RB_RPTR_WR, 0); 428 WREG32(RADEON_CP_RB_WPTR, 0); 429 WREG32(RADEON_CP_RB_CNTL, tmp); 430 /* save PCI state */ 431 pci_save_state(rdev->pdev); 432 /* disable bus mastering */ 433 r100_bm_disable(rdev); 434 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) | 435 S_0000F0_SOFT_RESET_GA(1)); 436 RREG32(R_0000F0_RBBM_SOFT_RESET); 437 mdelay(500); 438 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 439 mdelay(1); 440 status = RREG32(R_000E40_RBBM_STATUS); 441 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 442 /* resetting the CP seems to be problematic sometimes it end up 443 * hard locking the computer, but it's necessary for successful 444 * reset more test & playing is needed on R3XX/R4XX to find a 445 * reliable (if any solution) 446 */ 447 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); 448 RREG32(R_0000F0_RBBM_SOFT_RESET); 449 mdelay(500); 450 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 451 mdelay(1); 452 status = RREG32(R_000E40_RBBM_STATUS); 453 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 454 /* restore PCI & busmastering */ 455 pci_restore_state(rdev->pdev); 456 r100_enable_bm(rdev); 457 /* Check if GPU is idle */ 458 if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) { 459 dev_err(rdev->dev, "failed to reset GPU\n"); 460 ret = -1; 461 } else 462 dev_info(rdev->dev, "GPU reset succeed\n"); 463 r100_mc_resume(rdev, &save); 464 return ret; 465 } 466 467 /* 468 * r300,r350,rv350,rv380 VRAM info 469 */ 470 void r300_mc_init(struct radeon_device *rdev) 471 { 472 u64 base; 473 u32 tmp; 474 475 /* DDR for all card after R300 & IGP */ 476 rdev->mc.vram_is_ddr = true; 477 tmp = RREG32(RADEON_MEM_CNTL); 478 tmp &= R300_MEM_NUM_CHANNELS_MASK; 479 switch (tmp) { 480 case 0: rdev->mc.vram_width = 64; break; 481 case 1: rdev->mc.vram_width = 128; break; 482 case 2: rdev->mc.vram_width = 256; break; 483 default: rdev->mc.vram_width = 128; break; 484 } 485 r100_vram_init_sizes(rdev); 486 base = rdev->mc.aper_base; 487 if (rdev->flags & RADEON_IS_IGP) 488 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; 489 radeon_vram_location(rdev, &rdev->mc, base); 490 rdev->mc.gtt_base_align = 0; 491 if (!(rdev->flags & RADEON_IS_AGP)) 492 radeon_gtt_location(rdev, &rdev->mc); 493 radeon_update_bandwidth_info(rdev); 494 } 495 496 void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes) 497 { 498 uint32_t link_width_cntl, mask; 499 500 if (rdev->flags & RADEON_IS_IGP) 501 return; 502 503 if (!(rdev->flags & RADEON_IS_PCIE)) 504 return; 505 506 /* FIXME wait for idle */ 507 508 switch (lanes) { 509 case 0: 510 mask = RADEON_PCIE_LC_LINK_WIDTH_X0; 511 break; 512 case 1: 513 mask = RADEON_PCIE_LC_LINK_WIDTH_X1; 514 break; 515 case 2: 516 mask = RADEON_PCIE_LC_LINK_WIDTH_X2; 517 break; 518 case 4: 519 mask = RADEON_PCIE_LC_LINK_WIDTH_X4; 520 break; 521 case 8: 522 mask = RADEON_PCIE_LC_LINK_WIDTH_X8; 523 break; 524 case 12: 525 mask = RADEON_PCIE_LC_LINK_WIDTH_X12; 526 break; 527 case 16: 528 default: 529 mask = RADEON_PCIE_LC_LINK_WIDTH_X16; 530 break; 531 } 532 533 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 534 535 if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) == 536 (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT)) 537 return; 538 539 link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK | 540 RADEON_PCIE_LC_RECONFIG_NOW | 541 RADEON_PCIE_LC_RECONFIG_LATER | 542 RADEON_PCIE_LC_SHORT_RECONFIG_EN); 543 link_width_cntl |= mask; 544 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 545 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl | 546 RADEON_PCIE_LC_RECONFIG_NOW)); 547 548 /* wait for lane set to complete */ 549 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 550 while (link_width_cntl == 0xffffffff) 551 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 552 553 } 554 555 int rv370_get_pcie_lanes(struct radeon_device *rdev) 556 { 557 u32 link_width_cntl; 558 559 if (rdev->flags & RADEON_IS_IGP) 560 return 0; 561 562 if (!(rdev->flags & RADEON_IS_PCIE)) 563 return 0; 564 565 /* FIXME wait for idle */ 566 567 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 568 569 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) { 570 case RADEON_PCIE_LC_LINK_WIDTH_X0: 571 return 0; 572 case RADEON_PCIE_LC_LINK_WIDTH_X1: 573 return 1; 574 case RADEON_PCIE_LC_LINK_WIDTH_X2: 575 return 2; 576 case RADEON_PCIE_LC_LINK_WIDTH_X4: 577 return 4; 578 case RADEON_PCIE_LC_LINK_WIDTH_X8: 579 return 8; 580 case RADEON_PCIE_LC_LINK_WIDTH_X16: 581 default: 582 return 16; 583 } 584 } 585 586 #if defined(CONFIG_DEBUG_FS) 587 static int rv370_debugfs_pcie_gart_info(struct seq_file *m, void *data) 588 { 589 struct drm_info_node *node = (struct drm_info_node *) m->private; 590 struct drm_device *dev = node->minor->dev; 591 struct radeon_device *rdev = dev->dev_private; 592 uint32_t tmp; 593 594 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 595 seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp); 596 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE); 597 seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp); 598 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO); 599 seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp); 600 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI); 601 seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp); 602 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO); 603 seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp); 604 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI); 605 seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp); 606 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR); 607 seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp); 608 return 0; 609 } 610 611 static struct drm_info_list rv370_pcie_gart_info_list[] = { 612 {"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info, 0, NULL}, 613 }; 614 #endif 615 616 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev) 617 { 618 #if defined(CONFIG_DEBUG_FS) 619 return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1); 620 #else 621 return 0; 622 #endif 623 } 624 625 static int r300_packet0_check(struct radeon_cs_parser *p, 626 struct radeon_cs_packet *pkt, 627 unsigned idx, unsigned reg) 628 { 629 struct radeon_bo_list *reloc; 630 struct r100_cs_track *track; 631 volatile uint32_t *ib; 632 uint32_t tmp, tile_flags = 0; 633 unsigned i; 634 int r; 635 u32 idx_value; 636 637 ib = p->ib.ptr; 638 track = (struct r100_cs_track *)p->track; 639 idx_value = radeon_get_ib_value(p, idx); 640 641 switch(reg) { 642 case AVIVO_D1MODE_VLINE_START_END: 643 case RADEON_CRTC_GUI_TRIG_VLINE: 644 r = r100_cs_packet_parse_vline(p); 645 if (r) { 646 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 647 idx, reg); 648 radeon_cs_dump_packet(p, pkt); 649 return r; 650 } 651 break; 652 case RADEON_DST_PITCH_OFFSET: 653 case RADEON_SRC_PITCH_OFFSET: 654 r = r100_reloc_pitch_offset(p, pkt, idx, reg); 655 if (r) 656 return r; 657 break; 658 case R300_RB3D_COLOROFFSET0: 659 case R300_RB3D_COLOROFFSET1: 660 case R300_RB3D_COLOROFFSET2: 661 case R300_RB3D_COLOROFFSET3: 662 i = (reg - R300_RB3D_COLOROFFSET0) >> 2; 663 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 664 if (r) { 665 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 666 idx, reg); 667 radeon_cs_dump_packet(p, pkt); 668 return r; 669 } 670 track->cb[i].robj = reloc->robj; 671 track->cb[i].offset = idx_value; 672 track->cb_dirty = true; 673 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 674 break; 675 case R300_ZB_DEPTHOFFSET: 676 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 677 if (r) { 678 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 679 idx, reg); 680 radeon_cs_dump_packet(p, pkt); 681 return r; 682 } 683 track->zb.robj = reloc->robj; 684 track->zb.offset = idx_value; 685 track->zb_dirty = true; 686 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 687 break; 688 case R300_TX_OFFSET_0: 689 case R300_TX_OFFSET_0+4: 690 case R300_TX_OFFSET_0+8: 691 case R300_TX_OFFSET_0+12: 692 case R300_TX_OFFSET_0+16: 693 case R300_TX_OFFSET_0+20: 694 case R300_TX_OFFSET_0+24: 695 case R300_TX_OFFSET_0+28: 696 case R300_TX_OFFSET_0+32: 697 case R300_TX_OFFSET_0+36: 698 case R300_TX_OFFSET_0+40: 699 case R300_TX_OFFSET_0+44: 700 case R300_TX_OFFSET_0+48: 701 case R300_TX_OFFSET_0+52: 702 case R300_TX_OFFSET_0+56: 703 case R300_TX_OFFSET_0+60: 704 i = (reg - R300_TX_OFFSET_0) >> 2; 705 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 706 if (r) { 707 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 708 idx, reg); 709 radeon_cs_dump_packet(p, pkt); 710 return r; 711 } 712 713 if (p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) { 714 ib[idx] = (idx_value & 31) | /* keep the 1st 5 bits */ 715 ((idx_value & ~31) + (u32)reloc->gpu_offset); 716 } else { 717 if (reloc->tiling_flags & RADEON_TILING_MACRO) 718 tile_flags |= R300_TXO_MACRO_TILE; 719 if (reloc->tiling_flags & RADEON_TILING_MICRO) 720 tile_flags |= R300_TXO_MICRO_TILE; 721 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) 722 tile_flags |= R300_TXO_MICRO_TILE_SQUARE; 723 724 tmp = idx_value + ((u32)reloc->gpu_offset); 725 tmp |= tile_flags; 726 ib[idx] = tmp; 727 } 728 track->textures[i].robj = reloc->robj; 729 track->tex_dirty = true; 730 break; 731 /* Tracked registers */ 732 case 0x2084: 733 /* VAP_VF_CNTL */ 734 track->vap_vf_cntl = idx_value; 735 break; 736 case 0x20B4: 737 /* VAP_VTX_SIZE */ 738 track->vtx_size = idx_value & 0x7F; 739 break; 740 case 0x2134: 741 /* VAP_VF_MAX_VTX_INDX */ 742 track->max_indx = idx_value & 0x00FFFFFFUL; 743 break; 744 case 0x2088: 745 /* VAP_ALT_NUM_VERTICES - only valid on r500 */ 746 if (p->rdev->family < CHIP_RV515) 747 goto fail; 748 track->vap_alt_nverts = idx_value & 0xFFFFFF; 749 break; 750 case 0x43E4: 751 /* SC_SCISSOR1 */ 752 track->maxy = ((idx_value >> 13) & 0x1FFF) + 1; 753 if (p->rdev->family < CHIP_RV515) { 754 track->maxy -= 1440; 755 } 756 track->cb_dirty = true; 757 track->zb_dirty = true; 758 break; 759 case 0x4E00: 760 /* RB3D_CCTL */ 761 if ((idx_value & (1 << 10)) && /* CMASK_ENABLE */ 762 p->rdev->cmask_filp != p->filp) { 763 DRM_ERROR("Invalid RB3D_CCTL: Cannot enable CMASK.\n"); 764 return -EINVAL; 765 } 766 track->num_cb = ((idx_value >> 5) & 0x3) + 1; 767 track->cb_dirty = true; 768 break; 769 case 0x4E38: 770 case 0x4E3C: 771 case 0x4E40: 772 case 0x4E44: 773 /* RB3D_COLORPITCH0 */ 774 /* RB3D_COLORPITCH1 */ 775 /* RB3D_COLORPITCH2 */ 776 /* RB3D_COLORPITCH3 */ 777 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 778 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 779 if (r) { 780 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 781 idx, reg); 782 radeon_cs_dump_packet(p, pkt); 783 return r; 784 } 785 786 if (reloc->tiling_flags & RADEON_TILING_MACRO) 787 tile_flags |= R300_COLOR_TILE_ENABLE; 788 if (reloc->tiling_flags & RADEON_TILING_MICRO) 789 tile_flags |= R300_COLOR_MICROTILE_ENABLE; 790 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) 791 tile_flags |= R300_COLOR_MICROTILE_SQUARE_ENABLE; 792 793 tmp = idx_value & ~(0x7 << 16); 794 tmp |= tile_flags; 795 ib[idx] = tmp; 796 } 797 i = (reg - 0x4E38) >> 2; 798 track->cb[i].pitch = idx_value & 0x3FFE; 799 switch (((idx_value >> 21) & 0xF)) { 800 case 9: 801 case 11: 802 case 12: 803 track->cb[i].cpp = 1; 804 break; 805 case 3: 806 case 4: 807 case 13: 808 case 15: 809 track->cb[i].cpp = 2; 810 break; 811 case 5: 812 if (p->rdev->family < CHIP_RV515) { 813 DRM_ERROR("Invalid color buffer format (%d)!\n", 814 ((idx_value >> 21) & 0xF)); 815 return -EINVAL; 816 } 817 /* Pass through. */ 818 case 6: 819 track->cb[i].cpp = 4; 820 break; 821 case 10: 822 track->cb[i].cpp = 8; 823 break; 824 case 7: 825 track->cb[i].cpp = 16; 826 break; 827 default: 828 DRM_ERROR("Invalid color buffer format (%d) !\n", 829 ((idx_value >> 21) & 0xF)); 830 return -EINVAL; 831 } 832 track->cb_dirty = true; 833 break; 834 case 0x4F00: 835 /* ZB_CNTL */ 836 if (idx_value & 2) { 837 track->z_enabled = true; 838 } else { 839 track->z_enabled = false; 840 } 841 track->zb_dirty = true; 842 break; 843 case 0x4F10: 844 /* ZB_FORMAT */ 845 switch ((idx_value & 0xF)) { 846 case 0: 847 case 1: 848 track->zb.cpp = 2; 849 break; 850 case 2: 851 track->zb.cpp = 4; 852 break; 853 default: 854 DRM_ERROR("Invalid z buffer format (%d) !\n", 855 (idx_value & 0xF)); 856 return -EINVAL; 857 } 858 track->zb_dirty = true; 859 break; 860 case 0x4F24: 861 /* ZB_DEPTHPITCH */ 862 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 863 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 864 if (r) { 865 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 866 idx, reg); 867 radeon_cs_dump_packet(p, pkt); 868 return r; 869 } 870 871 if (reloc->tiling_flags & RADEON_TILING_MACRO) 872 tile_flags |= R300_DEPTHMACROTILE_ENABLE; 873 if (reloc->tiling_flags & RADEON_TILING_MICRO) 874 tile_flags |= R300_DEPTHMICROTILE_TILED; 875 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) 876 tile_flags |= R300_DEPTHMICROTILE_TILED_SQUARE; 877 878 tmp = idx_value & ~(0x7 << 16); 879 tmp |= tile_flags; 880 ib[idx] = tmp; 881 } 882 track->zb.pitch = idx_value & 0x3FFC; 883 track->zb_dirty = true; 884 break; 885 case 0x4104: 886 /* TX_ENABLE */ 887 for (i = 0; i < 16; i++) { 888 bool enabled; 889 890 enabled = !!(idx_value & (1 << i)); 891 track->textures[i].enabled = enabled; 892 } 893 track->tex_dirty = true; 894 break; 895 case 0x44C0: 896 case 0x44C4: 897 case 0x44C8: 898 case 0x44CC: 899 case 0x44D0: 900 case 0x44D4: 901 case 0x44D8: 902 case 0x44DC: 903 case 0x44E0: 904 case 0x44E4: 905 case 0x44E8: 906 case 0x44EC: 907 case 0x44F0: 908 case 0x44F4: 909 case 0x44F8: 910 case 0x44FC: 911 /* TX_FORMAT1_[0-15] */ 912 i = (reg - 0x44C0) >> 2; 913 tmp = (idx_value >> 25) & 0x3; 914 track->textures[i].tex_coord_type = tmp; 915 switch ((idx_value & 0x1F)) { 916 case R300_TX_FORMAT_X8: 917 case R300_TX_FORMAT_Y4X4: 918 case R300_TX_FORMAT_Z3Y3X2: 919 track->textures[i].cpp = 1; 920 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 921 break; 922 case R300_TX_FORMAT_X16: 923 case R300_TX_FORMAT_FL_I16: 924 case R300_TX_FORMAT_Y8X8: 925 case R300_TX_FORMAT_Z5Y6X5: 926 case R300_TX_FORMAT_Z6Y5X5: 927 case R300_TX_FORMAT_W4Z4Y4X4: 928 case R300_TX_FORMAT_W1Z5Y5X5: 929 case R300_TX_FORMAT_D3DMFT_CxV8U8: 930 case R300_TX_FORMAT_B8G8_B8G8: 931 case R300_TX_FORMAT_G8R8_G8B8: 932 track->textures[i].cpp = 2; 933 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 934 break; 935 case R300_TX_FORMAT_Y16X16: 936 case R300_TX_FORMAT_FL_I16A16: 937 case R300_TX_FORMAT_Z11Y11X10: 938 case R300_TX_FORMAT_Z10Y11X11: 939 case R300_TX_FORMAT_W8Z8Y8X8: 940 case R300_TX_FORMAT_W2Z10Y10X10: 941 case 0x17: 942 case R300_TX_FORMAT_FL_I32: 943 case 0x1e: 944 track->textures[i].cpp = 4; 945 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 946 break; 947 case R300_TX_FORMAT_W16Z16Y16X16: 948 case R300_TX_FORMAT_FL_R16G16B16A16: 949 case R300_TX_FORMAT_FL_I32A32: 950 track->textures[i].cpp = 8; 951 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 952 break; 953 case R300_TX_FORMAT_FL_R32G32B32A32: 954 track->textures[i].cpp = 16; 955 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 956 break; 957 case R300_TX_FORMAT_DXT1: 958 track->textures[i].cpp = 1; 959 track->textures[i].compress_format = R100_TRACK_COMP_DXT1; 960 break; 961 case R300_TX_FORMAT_ATI2N: 962 if (p->rdev->family < CHIP_R420) { 963 DRM_ERROR("Invalid texture format %u\n", 964 (idx_value & 0x1F)); 965 return -EINVAL; 966 } 967 /* The same rules apply as for DXT3/5. */ 968 /* Pass through. */ 969 case R300_TX_FORMAT_DXT3: 970 case R300_TX_FORMAT_DXT5: 971 track->textures[i].cpp = 1; 972 track->textures[i].compress_format = R100_TRACK_COMP_DXT35; 973 break; 974 default: 975 DRM_ERROR("Invalid texture format %u\n", 976 (idx_value & 0x1F)); 977 return -EINVAL; 978 } 979 track->tex_dirty = true; 980 break; 981 case 0x4400: 982 case 0x4404: 983 case 0x4408: 984 case 0x440C: 985 case 0x4410: 986 case 0x4414: 987 case 0x4418: 988 case 0x441C: 989 case 0x4420: 990 case 0x4424: 991 case 0x4428: 992 case 0x442C: 993 case 0x4430: 994 case 0x4434: 995 case 0x4438: 996 case 0x443C: 997 /* TX_FILTER0_[0-15] */ 998 i = (reg - 0x4400) >> 2; 999 tmp = idx_value & 0x7; 1000 if (tmp == 2 || tmp == 4 || tmp == 6) { 1001 track->textures[i].roundup_w = false; 1002 } 1003 tmp = (idx_value >> 3) & 0x7; 1004 if (tmp == 2 || tmp == 4 || tmp == 6) { 1005 track->textures[i].roundup_h = false; 1006 } 1007 track->tex_dirty = true; 1008 break; 1009 case 0x4500: 1010 case 0x4504: 1011 case 0x4508: 1012 case 0x450C: 1013 case 0x4510: 1014 case 0x4514: 1015 case 0x4518: 1016 case 0x451C: 1017 case 0x4520: 1018 case 0x4524: 1019 case 0x4528: 1020 case 0x452C: 1021 case 0x4530: 1022 case 0x4534: 1023 case 0x4538: 1024 case 0x453C: 1025 /* TX_FORMAT2_[0-15] */ 1026 i = (reg - 0x4500) >> 2; 1027 tmp = idx_value & 0x3FFF; 1028 track->textures[i].pitch = tmp + 1; 1029 if (p->rdev->family >= CHIP_RV515) { 1030 tmp = ((idx_value >> 15) & 1) << 11; 1031 track->textures[i].width_11 = tmp; 1032 tmp = ((idx_value >> 16) & 1) << 11; 1033 track->textures[i].height_11 = tmp; 1034 1035 /* ATI1N */ 1036 if (idx_value & (1 << 14)) { 1037 /* The same rules apply as for DXT1. */ 1038 track->textures[i].compress_format = 1039 R100_TRACK_COMP_DXT1; 1040 } 1041 } else if (idx_value & (1 << 14)) { 1042 DRM_ERROR("Forbidden bit TXFORMAT_MSB\n"); 1043 return -EINVAL; 1044 } 1045 track->tex_dirty = true; 1046 break; 1047 case 0x4480: 1048 case 0x4484: 1049 case 0x4488: 1050 case 0x448C: 1051 case 0x4490: 1052 case 0x4494: 1053 case 0x4498: 1054 case 0x449C: 1055 case 0x44A0: 1056 case 0x44A4: 1057 case 0x44A8: 1058 case 0x44AC: 1059 case 0x44B0: 1060 case 0x44B4: 1061 case 0x44B8: 1062 case 0x44BC: 1063 /* TX_FORMAT0_[0-15] */ 1064 i = (reg - 0x4480) >> 2; 1065 tmp = idx_value & 0x7FF; 1066 track->textures[i].width = tmp + 1; 1067 tmp = (idx_value >> 11) & 0x7FF; 1068 track->textures[i].height = tmp + 1; 1069 tmp = (idx_value >> 26) & 0xF; 1070 track->textures[i].num_levels = tmp; 1071 tmp = idx_value & (1 << 31); 1072 track->textures[i].use_pitch = !!tmp; 1073 tmp = (idx_value >> 22) & 0xF; 1074 track->textures[i].txdepth = tmp; 1075 track->tex_dirty = true; 1076 break; 1077 case R300_ZB_ZPASS_ADDR: 1078 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1079 if (r) { 1080 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1081 idx, reg); 1082 radeon_cs_dump_packet(p, pkt); 1083 return r; 1084 } 1085 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1086 break; 1087 case 0x4e0c: 1088 /* RB3D_COLOR_CHANNEL_MASK */ 1089 track->color_channel_mask = idx_value; 1090 track->cb_dirty = true; 1091 break; 1092 case 0x43a4: 1093 /* SC_HYPERZ_EN */ 1094 /* r300c emits this register - we need to disable hyperz for it 1095 * without complaining */ 1096 if (p->rdev->hyperz_filp != p->filp) { 1097 if (idx_value & 0x1) 1098 ib[idx] = idx_value & ~1; 1099 } 1100 break; 1101 case 0x4f1c: 1102 /* ZB_BW_CNTL */ 1103 track->zb_cb_clear = !!(idx_value & (1 << 5)); 1104 track->cb_dirty = true; 1105 track->zb_dirty = true; 1106 if (p->rdev->hyperz_filp != p->filp) { 1107 if (idx_value & (R300_HIZ_ENABLE | 1108 R300_RD_COMP_ENABLE | 1109 R300_WR_COMP_ENABLE | 1110 R300_FAST_FILL_ENABLE)) 1111 goto fail; 1112 } 1113 break; 1114 case 0x4e04: 1115 /* RB3D_BLENDCNTL */ 1116 track->blend_read_enable = !!(idx_value & (1 << 2)); 1117 track->cb_dirty = true; 1118 break; 1119 case R300_RB3D_AARESOLVE_OFFSET: 1120 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1121 if (r) { 1122 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1123 idx, reg); 1124 radeon_cs_dump_packet(p, pkt); 1125 return r; 1126 } 1127 track->aa.robj = reloc->robj; 1128 track->aa.offset = idx_value; 1129 track->aa_dirty = true; 1130 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1131 break; 1132 case R300_RB3D_AARESOLVE_PITCH: 1133 track->aa.pitch = idx_value & 0x3FFE; 1134 track->aa_dirty = true; 1135 break; 1136 case R300_RB3D_AARESOLVE_CTL: 1137 track->aaresolve = idx_value & 0x1; 1138 track->aa_dirty = true; 1139 break; 1140 case 0x4f30: /* ZB_MASK_OFFSET */ 1141 case 0x4f34: /* ZB_ZMASK_PITCH */ 1142 case 0x4f44: /* ZB_HIZ_OFFSET */ 1143 case 0x4f54: /* ZB_HIZ_PITCH */ 1144 if (idx_value && (p->rdev->hyperz_filp != p->filp)) 1145 goto fail; 1146 break; 1147 case 0x4028: 1148 if (idx_value && (p->rdev->hyperz_filp != p->filp)) 1149 goto fail; 1150 /* GB_Z_PEQ_CONFIG */ 1151 if (p->rdev->family >= CHIP_RV350) 1152 break; 1153 goto fail; 1154 break; 1155 case 0x4be8: 1156 /* valid register only on RV530 */ 1157 if (p->rdev->family == CHIP_RV530) 1158 break; 1159 /* fallthrough do not move */ 1160 default: 1161 goto fail; 1162 } 1163 return 0; 1164 fail: 1165 pr_err("Forbidden register 0x%04X in cs at %d (val=%08x)\n", 1166 reg, idx, idx_value); 1167 return -EINVAL; 1168 } 1169 1170 static int r300_packet3_check(struct radeon_cs_parser *p, 1171 struct radeon_cs_packet *pkt) 1172 { 1173 struct radeon_bo_list *reloc; 1174 struct r100_cs_track *track; 1175 volatile uint32_t *ib; 1176 unsigned idx; 1177 int r; 1178 1179 ib = p->ib.ptr; 1180 idx = pkt->idx + 1; 1181 track = (struct r100_cs_track *)p->track; 1182 switch(pkt->opcode) { 1183 case PACKET3_3D_LOAD_VBPNTR: 1184 r = r100_packet3_load_vbpntr(p, pkt, idx); 1185 if (r) 1186 return r; 1187 break; 1188 case PACKET3_INDX_BUFFER: 1189 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1190 if (r) { 1191 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); 1192 radeon_cs_dump_packet(p, pkt); 1193 return r; 1194 } 1195 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); 1196 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); 1197 if (r) { 1198 return r; 1199 } 1200 break; 1201 /* Draw packet */ 1202 case PACKET3_3D_DRAW_IMMD: 1203 /* Number of dwords is vtx_size * (num_vertices - 1) 1204 * PRIM_WALK must be equal to 3 vertex data in embedded 1205 * in cmd stream */ 1206 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) { 1207 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1208 return -EINVAL; 1209 } 1210 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1211 track->immd_dwords = pkt->count - 1; 1212 r = r100_cs_track_check(p->rdev, track); 1213 if (r) { 1214 return r; 1215 } 1216 break; 1217 case PACKET3_3D_DRAW_IMMD_2: 1218 /* Number of dwords is vtx_size * (num_vertices - 1) 1219 * PRIM_WALK must be equal to 3 vertex data in embedded 1220 * in cmd stream */ 1221 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) { 1222 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1223 return -EINVAL; 1224 } 1225 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1226 track->immd_dwords = pkt->count; 1227 r = r100_cs_track_check(p->rdev, track); 1228 if (r) { 1229 return r; 1230 } 1231 break; 1232 case PACKET3_3D_DRAW_VBUF: 1233 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1234 r = r100_cs_track_check(p->rdev, track); 1235 if (r) { 1236 return r; 1237 } 1238 break; 1239 case PACKET3_3D_DRAW_VBUF_2: 1240 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1241 r = r100_cs_track_check(p->rdev, track); 1242 if (r) { 1243 return r; 1244 } 1245 break; 1246 case PACKET3_3D_DRAW_INDX: 1247 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1248 r = r100_cs_track_check(p->rdev, track); 1249 if (r) { 1250 return r; 1251 } 1252 break; 1253 case PACKET3_3D_DRAW_INDX_2: 1254 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1255 r = r100_cs_track_check(p->rdev, track); 1256 if (r) { 1257 return r; 1258 } 1259 break; 1260 case PACKET3_3D_CLEAR_HIZ: 1261 case PACKET3_3D_CLEAR_ZMASK: 1262 if (p->rdev->hyperz_filp != p->filp) 1263 return -EINVAL; 1264 break; 1265 case PACKET3_3D_CLEAR_CMASK: 1266 if (p->rdev->cmask_filp != p->filp) 1267 return -EINVAL; 1268 break; 1269 case PACKET3_NOP: 1270 break; 1271 default: 1272 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); 1273 return -EINVAL; 1274 } 1275 return 0; 1276 } 1277 1278 int r300_cs_parse(struct radeon_cs_parser *p) 1279 { 1280 struct radeon_cs_packet pkt; 1281 struct r100_cs_track *track; 1282 int r; 1283 1284 track = kzalloc(sizeof(*track), GFP_KERNEL); 1285 if (track == NULL) 1286 return -ENOMEM; 1287 r100_cs_track_clear(p->rdev, track); 1288 p->track = track; 1289 do { 1290 r = radeon_cs_packet_parse(p, &pkt, p->idx); 1291 if (r) { 1292 return r; 1293 } 1294 p->idx += pkt.count + 2; 1295 switch (pkt.type) { 1296 case RADEON_PACKET_TYPE0: 1297 r = r100_cs_parse_packet0(p, &pkt, 1298 p->rdev->config.r300.reg_safe_bm, 1299 p->rdev->config.r300.reg_safe_bm_size, 1300 &r300_packet0_check); 1301 break; 1302 case RADEON_PACKET_TYPE2: 1303 break; 1304 case RADEON_PACKET_TYPE3: 1305 r = r300_packet3_check(p, &pkt); 1306 break; 1307 default: 1308 DRM_ERROR("Unknown packet type %d !\n", pkt.type); 1309 return -EINVAL; 1310 } 1311 if (r) { 1312 return r; 1313 } 1314 } while (p->idx < p->chunk_ib->length_dw); 1315 return 0; 1316 } 1317 1318 void r300_set_reg_safe(struct radeon_device *rdev) 1319 { 1320 rdev->config.r300.reg_safe_bm = r300_reg_safe_bm; 1321 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm); 1322 } 1323 1324 void r300_mc_program(struct radeon_device *rdev) 1325 { 1326 struct r100_mc_save save; 1327 int r; 1328 1329 r = r100_debugfs_mc_info_init(rdev); 1330 if (r) { 1331 dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n"); 1332 } 1333 1334 /* Stops all mc clients */ 1335 r100_mc_stop(rdev, &save); 1336 if (rdev->flags & RADEON_IS_AGP) { 1337 WREG32(R_00014C_MC_AGP_LOCATION, 1338 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) | 1339 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); 1340 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); 1341 WREG32(R_00015C_AGP_BASE_2, 1342 upper_32_bits(rdev->mc.agp_base) & 0xff); 1343 } else { 1344 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF); 1345 WREG32(R_000170_AGP_BASE, 0); 1346 WREG32(R_00015C_AGP_BASE_2, 0); 1347 } 1348 /* Wait for mc idle */ 1349 if (r300_mc_wait_for_idle(rdev)) 1350 DRM_INFO("Failed to wait MC idle before programming MC.\n"); 1351 /* Program MC, should be a 32bits limited address space */ 1352 WREG32(R_000148_MC_FB_LOCATION, 1353 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | 1354 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); 1355 r100_mc_resume(rdev, &save); 1356 } 1357 1358 void r300_clock_startup(struct radeon_device *rdev) 1359 { 1360 u32 tmp; 1361 1362 if (radeon_dynclks != -1 && radeon_dynclks) 1363 radeon_legacy_set_clock_gating(rdev, 1); 1364 /* We need to force on some of the block */ 1365 tmp = RREG32_PLL(R_00000D_SCLK_CNTL); 1366 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); 1367 if ((rdev->family == CHIP_RV350) || (rdev->family == CHIP_RV380)) 1368 tmp |= S_00000D_FORCE_VAP(1); 1369 WREG32_PLL(R_00000D_SCLK_CNTL, tmp); 1370 } 1371 1372 static int r300_startup(struct radeon_device *rdev) 1373 { 1374 int r; 1375 1376 /* set common regs */ 1377 r100_set_common_regs(rdev); 1378 /* program mc */ 1379 r300_mc_program(rdev); 1380 /* Resume clock */ 1381 r300_clock_startup(rdev); 1382 /* Initialize GPU configuration (# pipes, ...) */ 1383 r300_gpu_init(rdev); 1384 /* Initialize GART (initialize after TTM so we can allocate 1385 * memory through TTM but finalize after TTM) */ 1386 if (rdev->flags & RADEON_IS_PCIE) { 1387 r = rv370_pcie_gart_enable(rdev); 1388 if (r) 1389 return r; 1390 } 1391 1392 if (rdev->family == CHIP_R300 || 1393 rdev->family == CHIP_R350 || 1394 rdev->family == CHIP_RV350) 1395 r100_enable_bm(rdev); 1396 1397 if (rdev->flags & RADEON_IS_PCI) { 1398 r = r100_pci_gart_enable(rdev); 1399 if (r) 1400 return r; 1401 } 1402 1403 /* allocate wb buffer */ 1404 r = radeon_wb_init(rdev); 1405 if (r) 1406 return r; 1407 1408 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 1409 if (r) { 1410 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 1411 return r; 1412 } 1413 1414 /* Enable IRQ */ 1415 if (!rdev->irq.installed) { 1416 r = radeon_irq_kms_init(rdev); 1417 if (r) 1418 return r; 1419 } 1420 1421 r100_irq_set(rdev); 1422 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 1423 /* 1M ring buffer */ 1424 r = r100_cp_init(rdev, 1024 * 1024); 1425 if (r) { 1426 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 1427 return r; 1428 } 1429 1430 r = radeon_ib_pool_init(rdev); 1431 if (r) { 1432 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 1433 return r; 1434 } 1435 1436 return 0; 1437 } 1438 1439 int r300_resume(struct radeon_device *rdev) 1440 { 1441 int r; 1442 1443 /* Make sur GART are not working */ 1444 if (rdev->flags & RADEON_IS_PCIE) 1445 rv370_pcie_gart_disable(rdev); 1446 if (rdev->flags & RADEON_IS_PCI) 1447 r100_pci_gart_disable(rdev); 1448 /* Resume clock before doing reset */ 1449 r300_clock_startup(rdev); 1450 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 1451 if (radeon_asic_reset(rdev)) { 1452 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 1453 RREG32(R_000E40_RBBM_STATUS), 1454 RREG32(R_0007C0_CP_STAT)); 1455 } 1456 /* post */ 1457 radeon_combios_asic_init(rdev->ddev); 1458 /* Resume clock after posting */ 1459 r300_clock_startup(rdev); 1460 /* Initialize surface registers */ 1461 radeon_surface_init(rdev); 1462 1463 rdev->accel_working = true; 1464 r = r300_startup(rdev); 1465 if (r) { 1466 rdev->accel_working = false; 1467 } 1468 return r; 1469 } 1470 1471 int r300_suspend(struct radeon_device *rdev) 1472 { 1473 radeon_pm_suspend(rdev); 1474 r100_cp_disable(rdev); 1475 radeon_wb_disable(rdev); 1476 r100_irq_disable(rdev); 1477 if (rdev->flags & RADEON_IS_PCIE) 1478 rv370_pcie_gart_disable(rdev); 1479 if (rdev->flags & RADEON_IS_PCI) 1480 r100_pci_gart_disable(rdev); 1481 return 0; 1482 } 1483 1484 void r300_fini(struct radeon_device *rdev) 1485 { 1486 radeon_pm_fini(rdev); 1487 r100_cp_fini(rdev); 1488 radeon_wb_fini(rdev); 1489 radeon_ib_pool_fini(rdev); 1490 radeon_gem_fini(rdev); 1491 if (rdev->flags & RADEON_IS_PCIE) 1492 rv370_pcie_gart_fini(rdev); 1493 if (rdev->flags & RADEON_IS_PCI) 1494 r100_pci_gart_fini(rdev); 1495 radeon_agp_fini(rdev); 1496 radeon_irq_kms_fini(rdev); 1497 radeon_fence_driver_fini(rdev); 1498 radeon_bo_fini(rdev); 1499 radeon_atombios_fini(rdev); 1500 kfree(rdev->bios); 1501 rdev->bios = NULL; 1502 } 1503 1504 int r300_init(struct radeon_device *rdev) 1505 { 1506 int r; 1507 1508 /* Disable VGA */ 1509 r100_vga_render_disable(rdev); 1510 /* Initialize scratch registers */ 1511 radeon_scratch_init(rdev); 1512 /* Initialize surface registers */ 1513 radeon_surface_init(rdev); 1514 /* TODO: disable VGA need to use VGA request */ 1515 /* restore some register to sane defaults */ 1516 r100_restore_sanity(rdev); 1517 /* BIOS*/ 1518 if (!radeon_get_bios(rdev)) { 1519 if (ASIC_IS_AVIVO(rdev)) 1520 return -EINVAL; 1521 } 1522 if (rdev->is_atom_bios) { 1523 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); 1524 return -EINVAL; 1525 } else { 1526 r = radeon_combios_init(rdev); 1527 if (r) 1528 return r; 1529 } 1530 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 1531 if (radeon_asic_reset(rdev)) { 1532 dev_warn(rdev->dev, 1533 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 1534 RREG32(R_000E40_RBBM_STATUS), 1535 RREG32(R_0007C0_CP_STAT)); 1536 } 1537 /* check if cards are posted or not */ 1538 if (radeon_boot_test_post_card(rdev) == false) 1539 return -EINVAL; 1540 /* Set asic errata */ 1541 r300_errata(rdev); 1542 /* Initialize clocks */ 1543 radeon_get_clock_info(rdev->ddev); 1544 /* initialize AGP */ 1545 if (rdev->flags & RADEON_IS_AGP) { 1546 r = radeon_agp_init(rdev); 1547 if (r) { 1548 radeon_agp_disable(rdev); 1549 } 1550 } 1551 /* initialize memory controller */ 1552 r300_mc_init(rdev); 1553 /* Fence driver */ 1554 r = radeon_fence_driver_init(rdev); 1555 if (r) 1556 return r; 1557 /* Memory manager */ 1558 r = radeon_bo_init(rdev); 1559 if (r) 1560 return r; 1561 if (rdev->flags & RADEON_IS_PCIE) { 1562 r = rv370_pcie_gart_init(rdev); 1563 if (r) 1564 return r; 1565 } 1566 if (rdev->flags & RADEON_IS_PCI) { 1567 r = r100_pci_gart_init(rdev); 1568 if (r) 1569 return r; 1570 } 1571 r300_set_reg_safe(rdev); 1572 1573 /* Initialize power management */ 1574 radeon_pm_init(rdev); 1575 1576 rdev->accel_working = true; 1577 r = r300_startup(rdev); 1578 if (r) { 1579 /* Something went wrong with the accel init, so stop accel */ 1580 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 1581 r100_cp_fini(rdev); 1582 radeon_wb_fini(rdev); 1583 radeon_ib_pool_fini(rdev); 1584 radeon_irq_kms_fini(rdev); 1585 if (rdev->flags & RADEON_IS_PCIE) 1586 rv370_pcie_gart_fini(rdev); 1587 if (rdev->flags & RADEON_IS_PCI) 1588 r100_pci_gart_fini(rdev); 1589 radeon_agp_fini(rdev); 1590 rdev->accel_working = false; 1591 } 1592 return 0; 1593 } 1594