1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/seq_file.h> 29 #include <linux/slab.h> 30 #include <drm/drmP.h> 31 #include <drm/drm.h> 32 #include <drm/drm_crtc_helper.h> 33 #include "radeon_reg.h" 34 #include "radeon.h" 35 #include "radeon_asic.h" 36 #include "radeon_drm.h" 37 #include "r100_track.h" 38 #include "r300d.h" 39 #include "rv350d.h" 40 #include "r300_reg_safe.h" 41 42 /* This files gather functions specifics to: r300,r350,rv350,rv370,rv380 43 * 44 * GPU Errata: 45 * - HOST_PATH_CNTL: r300 family seems to dislike write to HOST_PATH_CNTL 46 * using MMIO to flush host path read cache, this lead to HARDLOCKUP. 47 * However, scheduling such write to the ring seems harmless, i suspect 48 * the CP read collide with the flush somehow, or maybe the MC, hard to 49 * tell. (Jerome Glisse) 50 */ 51 52 /* 53 * rv370,rv380 PCIE GART 54 */ 55 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev); 56 57 void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev) 58 { 59 uint32_t tmp; 60 int i; 61 62 /* Workaround HW bug do flush 2 times */ 63 for (i = 0; i < 2; i++) { 64 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 65 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB); 66 (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 67 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); 68 } 69 mb(); 70 } 71 72 int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) 73 { 74 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr; 75 76 if (i < 0 || i > rdev->gart.num_gpu_pages) { 77 return -EINVAL; 78 } 79 addr = (lower_32_bits(addr) >> 8) | 80 ((upper_32_bits(addr) & 0xff) << 24) | 81 0xc; 82 /* on x86 we want this to be CPU endian, on powerpc 83 * on powerpc without HW swappers, it'll get swapped on way 84 * into VRAM - so no need for cpu_to_le32 on VRAM tables */ 85 writel(addr, ((void __iomem *)ptr) + (i * 4)); 86 return 0; 87 } 88 89 int rv370_pcie_gart_init(struct radeon_device *rdev) 90 { 91 int r; 92 93 if (rdev->gart.table.vram.robj) { 94 WARN(1, "RV370 PCIE GART already initialized\n"); 95 return 0; 96 } 97 /* Initialize common gart structure */ 98 r = radeon_gart_init(rdev); 99 if (r) 100 return r; 101 r = rv370_debugfs_pcie_gart_info_init(rdev); 102 if (r) 103 DRM_ERROR("Failed to register debugfs file for PCIE gart !\n"); 104 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; 105 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush; 106 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page; 107 return radeon_gart_table_vram_alloc(rdev); 108 } 109 110 int rv370_pcie_gart_enable(struct radeon_device *rdev) 111 { 112 uint32_t table_addr; 113 uint32_t tmp; 114 int r; 115 116 if (rdev->gart.table.vram.robj == NULL) { 117 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 118 return -EINVAL; 119 } 120 r = radeon_gart_table_vram_pin(rdev); 121 if (r) 122 return r; 123 radeon_gart_restore(rdev); 124 /* discard memory request outside of configured range */ 125 tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; 126 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); 127 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start); 128 tmp = rdev->mc.gtt_end & ~RADEON_GPU_PAGE_MASK; 129 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp); 130 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0); 131 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0); 132 table_addr = rdev->gart.table_addr; 133 WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr); 134 /* FIXME: setup default page */ 135 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start); 136 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0); 137 /* Clear error */ 138 WREG32_PCIE(0x18, 0); 139 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 140 tmp |= RADEON_PCIE_TX_GART_EN; 141 tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; 142 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); 143 rv370_pcie_gart_tlb_flush(rdev); 144 DRM_INFO("PCIE GART of %uM enabled (table at 0x%08X).\n", 145 (unsigned)(rdev->mc.gtt_size >> 20), table_addr); 146 rdev->gart.ready = true; 147 return 0; 148 } 149 150 void rv370_pcie_gart_disable(struct radeon_device *rdev) 151 { 152 u32 tmp; 153 int r; 154 155 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, 0); 156 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, 0); 157 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0); 158 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0); 159 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 160 tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; 161 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN); 162 if (rdev->gart.table.vram.robj) { 163 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false); 164 if (likely(r == 0)) { 165 radeon_bo_kunmap(rdev->gart.table.vram.robj); 166 radeon_bo_unpin(rdev->gart.table.vram.robj); 167 radeon_bo_unreserve(rdev->gart.table.vram.robj); 168 } 169 } 170 } 171 172 void rv370_pcie_gart_fini(struct radeon_device *rdev) 173 { 174 radeon_gart_fini(rdev); 175 rv370_pcie_gart_disable(rdev); 176 radeon_gart_table_vram_free(rdev); 177 } 178 179 void r300_fence_ring_emit(struct radeon_device *rdev, 180 struct radeon_fence *fence) 181 { 182 /* Who ever call radeon_fence_emit should call ring_lock and ask 183 * for enough space (today caller are ib schedule and buffer move) */ 184 /* Write SC register so SC & US assert idle */ 185 radeon_ring_write(rdev, PACKET0(R300_RE_SCISSORS_TL, 0)); 186 radeon_ring_write(rdev, 0); 187 radeon_ring_write(rdev, PACKET0(R300_RE_SCISSORS_BR, 0)); 188 radeon_ring_write(rdev, 0); 189 /* Flush 3D cache */ 190 radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 191 radeon_ring_write(rdev, R300_RB3D_DC_FLUSH); 192 radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); 193 radeon_ring_write(rdev, R300_ZC_FLUSH); 194 /* Wait until IDLE & CLEAN */ 195 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); 196 radeon_ring_write(rdev, (RADEON_WAIT_3D_IDLECLEAN | 197 RADEON_WAIT_2D_IDLECLEAN | 198 RADEON_WAIT_DMA_GUI_IDLE)); 199 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0)); 200 radeon_ring_write(rdev, rdev->config.r300.hdp_cntl | 201 RADEON_HDP_READ_BUFFER_INVALIDATE); 202 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0)); 203 radeon_ring_write(rdev, rdev->config.r300.hdp_cntl); 204 /* Emit fence sequence & fire IRQ */ 205 radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0)); 206 radeon_ring_write(rdev, fence->seq); 207 radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0)); 208 radeon_ring_write(rdev, RADEON_SW_INT_FIRE); 209 } 210 211 void r300_ring_start(struct radeon_device *rdev) 212 { 213 unsigned gb_tile_config; 214 int r; 215 216 /* Sub pixel 1/12 so we can have 4K rendering according to doc */ 217 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16); 218 switch(rdev->num_gb_pipes) { 219 case 2: 220 gb_tile_config |= R300_PIPE_COUNT_R300; 221 break; 222 case 3: 223 gb_tile_config |= R300_PIPE_COUNT_R420_3P; 224 break; 225 case 4: 226 gb_tile_config |= R300_PIPE_COUNT_R420; 227 break; 228 case 1: 229 default: 230 gb_tile_config |= R300_PIPE_COUNT_RV350; 231 break; 232 } 233 234 r = radeon_ring_lock(rdev, 64); 235 if (r) { 236 return; 237 } 238 radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0)); 239 radeon_ring_write(rdev, 240 RADEON_ISYNC_ANY2D_IDLE3D | 241 RADEON_ISYNC_ANY3D_IDLE2D | 242 RADEON_ISYNC_WAIT_IDLEGUI | 243 RADEON_ISYNC_CPSCRATCH_IDLEGUI); 244 radeon_ring_write(rdev, PACKET0(R300_GB_TILE_CONFIG, 0)); 245 radeon_ring_write(rdev, gb_tile_config); 246 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); 247 radeon_ring_write(rdev, 248 RADEON_WAIT_2D_IDLECLEAN | 249 RADEON_WAIT_3D_IDLECLEAN); 250 radeon_ring_write(rdev, PACKET0(R300_DST_PIPE_CONFIG, 0)); 251 radeon_ring_write(rdev, R300_PIPE_AUTO_CONFIG); 252 radeon_ring_write(rdev, PACKET0(R300_GB_SELECT, 0)); 253 radeon_ring_write(rdev, 0); 254 radeon_ring_write(rdev, PACKET0(R300_GB_ENABLE, 0)); 255 radeon_ring_write(rdev, 0); 256 radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 257 radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); 258 radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); 259 radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE); 260 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); 261 radeon_ring_write(rdev, 262 RADEON_WAIT_2D_IDLECLEAN | 263 RADEON_WAIT_3D_IDLECLEAN); 264 radeon_ring_write(rdev, PACKET0(R300_GB_AA_CONFIG, 0)); 265 radeon_ring_write(rdev, 0); 266 radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 267 radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); 268 radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); 269 radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE); 270 radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS0, 0)); 271 radeon_ring_write(rdev, 272 ((6 << R300_MS_X0_SHIFT) | 273 (6 << R300_MS_Y0_SHIFT) | 274 (6 << R300_MS_X1_SHIFT) | 275 (6 << R300_MS_Y1_SHIFT) | 276 (6 << R300_MS_X2_SHIFT) | 277 (6 << R300_MS_Y2_SHIFT) | 278 (6 << R300_MSBD0_Y_SHIFT) | 279 (6 << R300_MSBD0_X_SHIFT))); 280 radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS1, 0)); 281 radeon_ring_write(rdev, 282 ((6 << R300_MS_X3_SHIFT) | 283 (6 << R300_MS_Y3_SHIFT) | 284 (6 << R300_MS_X4_SHIFT) | 285 (6 << R300_MS_Y4_SHIFT) | 286 (6 << R300_MS_X5_SHIFT) | 287 (6 << R300_MS_Y5_SHIFT) | 288 (6 << R300_MSBD1_SHIFT))); 289 radeon_ring_write(rdev, PACKET0(R300_GA_ENHANCE, 0)); 290 radeon_ring_write(rdev, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL); 291 radeon_ring_write(rdev, PACKET0(R300_GA_POLY_MODE, 0)); 292 radeon_ring_write(rdev, 293 R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE); 294 radeon_ring_write(rdev, PACKET0(R300_GA_ROUND_MODE, 0)); 295 radeon_ring_write(rdev, 296 R300_GEOMETRY_ROUND_NEAREST | 297 R300_COLOR_ROUND_NEAREST); 298 radeon_ring_unlock_commit(rdev); 299 } 300 301 void r300_errata(struct radeon_device *rdev) 302 { 303 rdev->pll_errata = 0; 304 305 if (rdev->family == CHIP_R300 && 306 (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) { 307 rdev->pll_errata |= CHIP_ERRATA_R300_CG; 308 } 309 } 310 311 int r300_mc_wait_for_idle(struct radeon_device *rdev) 312 { 313 unsigned i; 314 uint32_t tmp; 315 316 for (i = 0; i < rdev->usec_timeout; i++) { 317 /* read MC_STATUS */ 318 tmp = RREG32(RADEON_MC_STATUS); 319 if (tmp & R300_MC_IDLE) { 320 return 0; 321 } 322 DRM_UDELAY(1); 323 } 324 return -1; 325 } 326 327 void r300_gpu_init(struct radeon_device *rdev) 328 { 329 uint32_t gb_tile_config, tmp; 330 331 if ((rdev->family == CHIP_R300 && rdev->pdev->device != 0x4144) || 332 (rdev->family == CHIP_R350 && rdev->pdev->device != 0x4148)) { 333 /* r300,r350 */ 334 rdev->num_gb_pipes = 2; 335 } else { 336 /* rv350,rv370,rv380,r300 AD, r350 AH */ 337 rdev->num_gb_pipes = 1; 338 } 339 rdev->num_z_pipes = 1; 340 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16); 341 switch (rdev->num_gb_pipes) { 342 case 2: 343 gb_tile_config |= R300_PIPE_COUNT_R300; 344 break; 345 case 3: 346 gb_tile_config |= R300_PIPE_COUNT_R420_3P; 347 break; 348 case 4: 349 gb_tile_config |= R300_PIPE_COUNT_R420; 350 break; 351 default: 352 case 1: 353 gb_tile_config |= R300_PIPE_COUNT_RV350; 354 break; 355 } 356 WREG32(R300_GB_TILE_CONFIG, gb_tile_config); 357 358 if (r100_gui_wait_for_idle(rdev)) { 359 printk(KERN_WARNING "Failed to wait GUI idle while " 360 "programming pipes. Bad things might happen.\n"); 361 } 362 363 tmp = RREG32(R300_DST_PIPE_CONFIG); 364 WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG); 365 366 WREG32(R300_RB2D_DSTCACHE_MODE, 367 R300_DC_AUTOFLUSH_ENABLE | 368 R300_DC_DC_DISABLE_IGNORE_PE); 369 370 if (r100_gui_wait_for_idle(rdev)) { 371 printk(KERN_WARNING "Failed to wait GUI idle while " 372 "programming pipes. Bad things might happen.\n"); 373 } 374 if (r300_mc_wait_for_idle(rdev)) { 375 printk(KERN_WARNING "Failed to wait MC idle while " 376 "programming pipes. Bad things might happen.\n"); 377 } 378 DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n", 379 rdev->num_gb_pipes, rdev->num_z_pipes); 380 } 381 382 bool r300_gpu_is_lockup(struct radeon_device *rdev) 383 { 384 u32 rbbm_status; 385 int r; 386 387 rbbm_status = RREG32(R_000E40_RBBM_STATUS); 388 if (!G_000E40_GUI_ACTIVE(rbbm_status)) { 389 r100_gpu_lockup_update(&rdev->config.r300.lockup, &rdev->cp); 390 return false; 391 } 392 /* force CP activities */ 393 r = radeon_ring_lock(rdev, 2); 394 if (!r) { 395 /* PACKET2 NOP */ 396 radeon_ring_write(rdev, 0x80000000); 397 radeon_ring_write(rdev, 0x80000000); 398 radeon_ring_unlock_commit(rdev); 399 } 400 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR); 401 return r100_gpu_cp_is_lockup(rdev, &rdev->config.r300.lockup, &rdev->cp); 402 } 403 404 int r300_asic_reset(struct radeon_device *rdev) 405 { 406 struct r100_mc_save save; 407 u32 status, tmp; 408 int ret = 0; 409 410 status = RREG32(R_000E40_RBBM_STATUS); 411 if (!G_000E40_GUI_ACTIVE(status)) { 412 return 0; 413 } 414 r100_mc_stop(rdev, &save); 415 status = RREG32(R_000E40_RBBM_STATUS); 416 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 417 /* stop CP */ 418 WREG32(RADEON_CP_CSQ_CNTL, 0); 419 tmp = RREG32(RADEON_CP_RB_CNTL); 420 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); 421 WREG32(RADEON_CP_RB_RPTR_WR, 0); 422 WREG32(RADEON_CP_RB_WPTR, 0); 423 WREG32(RADEON_CP_RB_CNTL, tmp); 424 /* save PCI state */ 425 pci_save_state(rdev->pdev); 426 /* disable bus mastering */ 427 r100_bm_disable(rdev); 428 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) | 429 S_0000F0_SOFT_RESET_GA(1)); 430 RREG32(R_0000F0_RBBM_SOFT_RESET); 431 mdelay(500); 432 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 433 mdelay(1); 434 status = RREG32(R_000E40_RBBM_STATUS); 435 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 436 /* resetting the CP seems to be problematic sometimes it end up 437 * hard locking the computer, but it's necessary for successfull 438 * reset more test & playing is needed on R3XX/R4XX to find a 439 * reliable (if any solution) 440 */ 441 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); 442 RREG32(R_0000F0_RBBM_SOFT_RESET); 443 mdelay(500); 444 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 445 mdelay(1); 446 status = RREG32(R_000E40_RBBM_STATUS); 447 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 448 /* restore PCI & busmastering */ 449 pci_restore_state(rdev->pdev); 450 r100_enable_bm(rdev); 451 /* Check if GPU is idle */ 452 if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) { 453 dev_err(rdev->dev, "failed to reset GPU\n"); 454 rdev->gpu_lockup = true; 455 ret = -1; 456 } else 457 dev_info(rdev->dev, "GPU reset succeed\n"); 458 r100_mc_resume(rdev, &save); 459 return ret; 460 } 461 462 /* 463 * r300,r350,rv350,rv380 VRAM info 464 */ 465 void r300_mc_init(struct radeon_device *rdev) 466 { 467 u64 base; 468 u32 tmp; 469 470 /* DDR for all card after R300 & IGP */ 471 rdev->mc.vram_is_ddr = true; 472 tmp = RREG32(RADEON_MEM_CNTL); 473 tmp &= R300_MEM_NUM_CHANNELS_MASK; 474 switch (tmp) { 475 case 0: rdev->mc.vram_width = 64; break; 476 case 1: rdev->mc.vram_width = 128; break; 477 case 2: rdev->mc.vram_width = 256; break; 478 default: rdev->mc.vram_width = 128; break; 479 } 480 r100_vram_init_sizes(rdev); 481 base = rdev->mc.aper_base; 482 if (rdev->flags & RADEON_IS_IGP) 483 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; 484 radeon_vram_location(rdev, &rdev->mc, base); 485 rdev->mc.gtt_base_align = 0; 486 if (!(rdev->flags & RADEON_IS_AGP)) 487 radeon_gtt_location(rdev, &rdev->mc); 488 radeon_update_bandwidth_info(rdev); 489 } 490 491 void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes) 492 { 493 uint32_t link_width_cntl, mask; 494 495 if (rdev->flags & RADEON_IS_IGP) 496 return; 497 498 if (!(rdev->flags & RADEON_IS_PCIE)) 499 return; 500 501 /* FIXME wait for idle */ 502 503 switch (lanes) { 504 case 0: 505 mask = RADEON_PCIE_LC_LINK_WIDTH_X0; 506 break; 507 case 1: 508 mask = RADEON_PCIE_LC_LINK_WIDTH_X1; 509 break; 510 case 2: 511 mask = RADEON_PCIE_LC_LINK_WIDTH_X2; 512 break; 513 case 4: 514 mask = RADEON_PCIE_LC_LINK_WIDTH_X4; 515 break; 516 case 8: 517 mask = RADEON_PCIE_LC_LINK_WIDTH_X8; 518 break; 519 case 12: 520 mask = RADEON_PCIE_LC_LINK_WIDTH_X12; 521 break; 522 case 16: 523 default: 524 mask = RADEON_PCIE_LC_LINK_WIDTH_X16; 525 break; 526 } 527 528 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 529 530 if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) == 531 (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT)) 532 return; 533 534 link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK | 535 RADEON_PCIE_LC_RECONFIG_NOW | 536 RADEON_PCIE_LC_RECONFIG_LATER | 537 RADEON_PCIE_LC_SHORT_RECONFIG_EN); 538 link_width_cntl |= mask; 539 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 540 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl | 541 RADEON_PCIE_LC_RECONFIG_NOW)); 542 543 /* wait for lane set to complete */ 544 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 545 while (link_width_cntl == 0xffffffff) 546 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 547 548 } 549 550 int rv370_get_pcie_lanes(struct radeon_device *rdev) 551 { 552 u32 link_width_cntl; 553 554 if (rdev->flags & RADEON_IS_IGP) 555 return 0; 556 557 if (!(rdev->flags & RADEON_IS_PCIE)) 558 return 0; 559 560 /* FIXME wait for idle */ 561 562 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 563 564 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) { 565 case RADEON_PCIE_LC_LINK_WIDTH_X0: 566 return 0; 567 case RADEON_PCIE_LC_LINK_WIDTH_X1: 568 return 1; 569 case RADEON_PCIE_LC_LINK_WIDTH_X2: 570 return 2; 571 case RADEON_PCIE_LC_LINK_WIDTH_X4: 572 return 4; 573 case RADEON_PCIE_LC_LINK_WIDTH_X8: 574 return 8; 575 case RADEON_PCIE_LC_LINK_WIDTH_X16: 576 default: 577 return 16; 578 } 579 } 580 581 #if defined(CONFIG_DEBUG_FS) 582 static int rv370_debugfs_pcie_gart_info(struct seq_file *m, void *data) 583 { 584 struct drm_info_node *node = (struct drm_info_node *) m->private; 585 struct drm_device *dev = node->minor->dev; 586 struct radeon_device *rdev = dev->dev_private; 587 uint32_t tmp; 588 589 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 590 seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp); 591 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE); 592 seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp); 593 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO); 594 seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp); 595 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI); 596 seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp); 597 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO); 598 seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp); 599 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI); 600 seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp); 601 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR); 602 seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp); 603 return 0; 604 } 605 606 static struct drm_info_list rv370_pcie_gart_info_list[] = { 607 {"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info, 0, NULL}, 608 }; 609 #endif 610 611 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev) 612 { 613 #if defined(CONFIG_DEBUG_FS) 614 return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1); 615 #else 616 return 0; 617 #endif 618 } 619 620 static int r300_packet0_check(struct radeon_cs_parser *p, 621 struct radeon_cs_packet *pkt, 622 unsigned idx, unsigned reg) 623 { 624 struct radeon_cs_reloc *reloc; 625 struct r100_cs_track *track; 626 volatile uint32_t *ib; 627 uint32_t tmp, tile_flags = 0; 628 unsigned i; 629 int r; 630 u32 idx_value; 631 632 ib = p->ib->ptr; 633 track = (struct r100_cs_track *)p->track; 634 idx_value = radeon_get_ib_value(p, idx); 635 636 switch(reg) { 637 case AVIVO_D1MODE_VLINE_START_END: 638 case RADEON_CRTC_GUI_TRIG_VLINE: 639 r = r100_cs_packet_parse_vline(p); 640 if (r) { 641 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 642 idx, reg); 643 r100_cs_dump_packet(p, pkt); 644 return r; 645 } 646 break; 647 case RADEON_DST_PITCH_OFFSET: 648 case RADEON_SRC_PITCH_OFFSET: 649 r = r100_reloc_pitch_offset(p, pkt, idx, reg); 650 if (r) 651 return r; 652 break; 653 case R300_RB3D_COLOROFFSET0: 654 case R300_RB3D_COLOROFFSET1: 655 case R300_RB3D_COLOROFFSET2: 656 case R300_RB3D_COLOROFFSET3: 657 i = (reg - R300_RB3D_COLOROFFSET0) >> 2; 658 r = r100_cs_packet_next_reloc(p, &reloc); 659 if (r) { 660 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 661 idx, reg); 662 r100_cs_dump_packet(p, pkt); 663 return r; 664 } 665 track->cb[i].robj = reloc->robj; 666 track->cb[i].offset = idx_value; 667 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 668 break; 669 case R300_ZB_DEPTHOFFSET: 670 r = r100_cs_packet_next_reloc(p, &reloc); 671 if (r) { 672 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 673 idx, reg); 674 r100_cs_dump_packet(p, pkt); 675 return r; 676 } 677 track->zb.robj = reloc->robj; 678 track->zb.offset = idx_value; 679 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 680 break; 681 case R300_TX_OFFSET_0: 682 case R300_TX_OFFSET_0+4: 683 case R300_TX_OFFSET_0+8: 684 case R300_TX_OFFSET_0+12: 685 case R300_TX_OFFSET_0+16: 686 case R300_TX_OFFSET_0+20: 687 case R300_TX_OFFSET_0+24: 688 case R300_TX_OFFSET_0+28: 689 case R300_TX_OFFSET_0+32: 690 case R300_TX_OFFSET_0+36: 691 case R300_TX_OFFSET_0+40: 692 case R300_TX_OFFSET_0+44: 693 case R300_TX_OFFSET_0+48: 694 case R300_TX_OFFSET_0+52: 695 case R300_TX_OFFSET_0+56: 696 case R300_TX_OFFSET_0+60: 697 i = (reg - R300_TX_OFFSET_0) >> 2; 698 r = r100_cs_packet_next_reloc(p, &reloc); 699 if (r) { 700 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 701 idx, reg); 702 r100_cs_dump_packet(p, pkt); 703 return r; 704 } 705 706 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 707 tile_flags |= R300_TXO_MACRO_TILE; 708 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) 709 tile_flags |= R300_TXO_MICRO_TILE; 710 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE) 711 tile_flags |= R300_TXO_MICRO_TILE_SQUARE; 712 713 tmp = idx_value + ((u32)reloc->lobj.gpu_offset); 714 tmp |= tile_flags; 715 ib[idx] = tmp; 716 track->textures[i].robj = reloc->robj; 717 break; 718 /* Tracked registers */ 719 case 0x2084: 720 /* VAP_VF_CNTL */ 721 track->vap_vf_cntl = idx_value; 722 break; 723 case 0x20B4: 724 /* VAP_VTX_SIZE */ 725 track->vtx_size = idx_value & 0x7F; 726 break; 727 case 0x2134: 728 /* VAP_VF_MAX_VTX_INDX */ 729 track->max_indx = idx_value & 0x00FFFFFFUL; 730 break; 731 case 0x2088: 732 /* VAP_ALT_NUM_VERTICES - only valid on r500 */ 733 if (p->rdev->family < CHIP_RV515) 734 goto fail; 735 track->vap_alt_nverts = idx_value & 0xFFFFFF; 736 break; 737 case 0x43E4: 738 /* SC_SCISSOR1 */ 739 track->maxy = ((idx_value >> 13) & 0x1FFF) + 1; 740 if (p->rdev->family < CHIP_RV515) { 741 track->maxy -= 1440; 742 } 743 break; 744 case 0x4E00: 745 /* RB3D_CCTL */ 746 if ((idx_value & (1 << 10)) && /* CMASK_ENABLE */ 747 p->rdev->cmask_filp != p->filp) { 748 DRM_ERROR("Invalid RB3D_CCTL: Cannot enable CMASK.\n"); 749 return -EINVAL; 750 } 751 track->num_cb = ((idx_value >> 5) & 0x3) + 1; 752 break; 753 case 0x4E38: 754 case 0x4E3C: 755 case 0x4E40: 756 case 0x4E44: 757 /* RB3D_COLORPITCH0 */ 758 /* RB3D_COLORPITCH1 */ 759 /* RB3D_COLORPITCH2 */ 760 /* RB3D_COLORPITCH3 */ 761 r = r100_cs_packet_next_reloc(p, &reloc); 762 if (r) { 763 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 764 idx, reg); 765 r100_cs_dump_packet(p, pkt); 766 return r; 767 } 768 769 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 770 tile_flags |= R300_COLOR_TILE_ENABLE; 771 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) 772 tile_flags |= R300_COLOR_MICROTILE_ENABLE; 773 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE) 774 tile_flags |= R300_COLOR_MICROTILE_SQUARE_ENABLE; 775 776 tmp = idx_value & ~(0x7 << 16); 777 tmp |= tile_flags; 778 ib[idx] = tmp; 779 i = (reg - 0x4E38) >> 2; 780 track->cb[i].pitch = idx_value & 0x3FFE; 781 switch (((idx_value >> 21) & 0xF)) { 782 case 9: 783 case 11: 784 case 12: 785 track->cb[i].cpp = 1; 786 break; 787 case 3: 788 case 4: 789 case 13: 790 case 15: 791 track->cb[i].cpp = 2; 792 break; 793 case 5: 794 if (p->rdev->family < CHIP_RV515) { 795 DRM_ERROR("Invalid color buffer format (%d)!\n", 796 ((idx_value >> 21) & 0xF)); 797 return -EINVAL; 798 } 799 /* Pass through. */ 800 case 6: 801 track->cb[i].cpp = 4; 802 break; 803 case 10: 804 track->cb[i].cpp = 8; 805 break; 806 case 7: 807 track->cb[i].cpp = 16; 808 break; 809 default: 810 DRM_ERROR("Invalid color buffer format (%d) !\n", 811 ((idx_value >> 21) & 0xF)); 812 return -EINVAL; 813 } 814 break; 815 case 0x4F00: 816 /* ZB_CNTL */ 817 if (idx_value & 2) { 818 track->z_enabled = true; 819 } else { 820 track->z_enabled = false; 821 } 822 break; 823 case 0x4F10: 824 /* ZB_FORMAT */ 825 switch ((idx_value & 0xF)) { 826 case 0: 827 case 1: 828 track->zb.cpp = 2; 829 break; 830 case 2: 831 track->zb.cpp = 4; 832 break; 833 default: 834 DRM_ERROR("Invalid z buffer format (%d) !\n", 835 (idx_value & 0xF)); 836 return -EINVAL; 837 } 838 break; 839 case 0x4F24: 840 /* ZB_DEPTHPITCH */ 841 r = r100_cs_packet_next_reloc(p, &reloc); 842 if (r) { 843 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 844 idx, reg); 845 r100_cs_dump_packet(p, pkt); 846 return r; 847 } 848 849 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 850 tile_flags |= R300_DEPTHMACROTILE_ENABLE; 851 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) 852 tile_flags |= R300_DEPTHMICROTILE_TILED; 853 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE) 854 tile_flags |= R300_DEPTHMICROTILE_TILED_SQUARE; 855 856 tmp = idx_value & ~(0x7 << 16); 857 tmp |= tile_flags; 858 ib[idx] = tmp; 859 860 track->zb.pitch = idx_value & 0x3FFC; 861 break; 862 case 0x4104: 863 for (i = 0; i < 16; i++) { 864 bool enabled; 865 866 enabled = !!(idx_value & (1 << i)); 867 track->textures[i].enabled = enabled; 868 } 869 break; 870 case 0x44C0: 871 case 0x44C4: 872 case 0x44C8: 873 case 0x44CC: 874 case 0x44D0: 875 case 0x44D4: 876 case 0x44D8: 877 case 0x44DC: 878 case 0x44E0: 879 case 0x44E4: 880 case 0x44E8: 881 case 0x44EC: 882 case 0x44F0: 883 case 0x44F4: 884 case 0x44F8: 885 case 0x44FC: 886 /* TX_FORMAT1_[0-15] */ 887 i = (reg - 0x44C0) >> 2; 888 tmp = (idx_value >> 25) & 0x3; 889 track->textures[i].tex_coord_type = tmp; 890 switch ((idx_value & 0x1F)) { 891 case R300_TX_FORMAT_X8: 892 case R300_TX_FORMAT_Y4X4: 893 case R300_TX_FORMAT_Z3Y3X2: 894 track->textures[i].cpp = 1; 895 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 896 break; 897 case R300_TX_FORMAT_X16: 898 case R300_TX_FORMAT_Y8X8: 899 case R300_TX_FORMAT_Z5Y6X5: 900 case R300_TX_FORMAT_Z6Y5X5: 901 case R300_TX_FORMAT_W4Z4Y4X4: 902 case R300_TX_FORMAT_W1Z5Y5X5: 903 case R300_TX_FORMAT_D3DMFT_CxV8U8: 904 case R300_TX_FORMAT_B8G8_B8G8: 905 case R300_TX_FORMAT_G8R8_G8B8: 906 track->textures[i].cpp = 2; 907 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 908 break; 909 case R300_TX_FORMAT_Y16X16: 910 case R300_TX_FORMAT_Z11Y11X10: 911 case R300_TX_FORMAT_Z10Y11X11: 912 case R300_TX_FORMAT_W8Z8Y8X8: 913 case R300_TX_FORMAT_W2Z10Y10X10: 914 case 0x17: 915 case R300_TX_FORMAT_FL_I32: 916 case 0x1e: 917 track->textures[i].cpp = 4; 918 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 919 break; 920 case R300_TX_FORMAT_W16Z16Y16X16: 921 case R300_TX_FORMAT_FL_R16G16B16A16: 922 case R300_TX_FORMAT_FL_I32A32: 923 track->textures[i].cpp = 8; 924 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 925 break; 926 case R300_TX_FORMAT_FL_R32G32B32A32: 927 track->textures[i].cpp = 16; 928 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 929 break; 930 case R300_TX_FORMAT_DXT1: 931 track->textures[i].cpp = 1; 932 track->textures[i].compress_format = R100_TRACK_COMP_DXT1; 933 break; 934 case R300_TX_FORMAT_ATI2N: 935 if (p->rdev->family < CHIP_R420) { 936 DRM_ERROR("Invalid texture format %u\n", 937 (idx_value & 0x1F)); 938 return -EINVAL; 939 } 940 /* The same rules apply as for DXT3/5. */ 941 /* Pass through. */ 942 case R300_TX_FORMAT_DXT3: 943 case R300_TX_FORMAT_DXT5: 944 track->textures[i].cpp = 1; 945 track->textures[i].compress_format = R100_TRACK_COMP_DXT35; 946 break; 947 default: 948 DRM_ERROR("Invalid texture format %u\n", 949 (idx_value & 0x1F)); 950 return -EINVAL; 951 break; 952 } 953 break; 954 case 0x4400: 955 case 0x4404: 956 case 0x4408: 957 case 0x440C: 958 case 0x4410: 959 case 0x4414: 960 case 0x4418: 961 case 0x441C: 962 case 0x4420: 963 case 0x4424: 964 case 0x4428: 965 case 0x442C: 966 case 0x4430: 967 case 0x4434: 968 case 0x4438: 969 case 0x443C: 970 /* TX_FILTER0_[0-15] */ 971 i = (reg - 0x4400) >> 2; 972 tmp = idx_value & 0x7; 973 if (tmp == 2 || tmp == 4 || tmp == 6) { 974 track->textures[i].roundup_w = false; 975 } 976 tmp = (idx_value >> 3) & 0x7; 977 if (tmp == 2 || tmp == 4 || tmp == 6) { 978 track->textures[i].roundup_h = false; 979 } 980 break; 981 case 0x4500: 982 case 0x4504: 983 case 0x4508: 984 case 0x450C: 985 case 0x4510: 986 case 0x4514: 987 case 0x4518: 988 case 0x451C: 989 case 0x4520: 990 case 0x4524: 991 case 0x4528: 992 case 0x452C: 993 case 0x4530: 994 case 0x4534: 995 case 0x4538: 996 case 0x453C: 997 /* TX_FORMAT2_[0-15] */ 998 i = (reg - 0x4500) >> 2; 999 tmp = idx_value & 0x3FFF; 1000 track->textures[i].pitch = tmp + 1; 1001 if (p->rdev->family >= CHIP_RV515) { 1002 tmp = ((idx_value >> 15) & 1) << 11; 1003 track->textures[i].width_11 = tmp; 1004 tmp = ((idx_value >> 16) & 1) << 11; 1005 track->textures[i].height_11 = tmp; 1006 1007 /* ATI1N */ 1008 if (idx_value & (1 << 14)) { 1009 /* The same rules apply as for DXT1. */ 1010 track->textures[i].compress_format = 1011 R100_TRACK_COMP_DXT1; 1012 } 1013 } else if (idx_value & (1 << 14)) { 1014 DRM_ERROR("Forbidden bit TXFORMAT_MSB\n"); 1015 return -EINVAL; 1016 } 1017 break; 1018 case 0x4480: 1019 case 0x4484: 1020 case 0x4488: 1021 case 0x448C: 1022 case 0x4490: 1023 case 0x4494: 1024 case 0x4498: 1025 case 0x449C: 1026 case 0x44A0: 1027 case 0x44A4: 1028 case 0x44A8: 1029 case 0x44AC: 1030 case 0x44B0: 1031 case 0x44B4: 1032 case 0x44B8: 1033 case 0x44BC: 1034 /* TX_FORMAT0_[0-15] */ 1035 i = (reg - 0x4480) >> 2; 1036 tmp = idx_value & 0x7FF; 1037 track->textures[i].width = tmp + 1; 1038 tmp = (idx_value >> 11) & 0x7FF; 1039 track->textures[i].height = tmp + 1; 1040 tmp = (idx_value >> 26) & 0xF; 1041 track->textures[i].num_levels = tmp; 1042 tmp = idx_value & (1 << 31); 1043 track->textures[i].use_pitch = !!tmp; 1044 tmp = (idx_value >> 22) & 0xF; 1045 track->textures[i].txdepth = tmp; 1046 break; 1047 case R300_ZB_ZPASS_ADDR: 1048 r = r100_cs_packet_next_reloc(p, &reloc); 1049 if (r) { 1050 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1051 idx, reg); 1052 r100_cs_dump_packet(p, pkt); 1053 return r; 1054 } 1055 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1056 break; 1057 case 0x4e0c: 1058 /* RB3D_COLOR_CHANNEL_MASK */ 1059 track->color_channel_mask = idx_value; 1060 break; 1061 case 0x43a4: 1062 /* SC_HYPERZ_EN */ 1063 /* r300c emits this register - we need to disable hyperz for it 1064 * without complaining */ 1065 if (p->rdev->hyperz_filp != p->filp) { 1066 if (idx_value & 0x1) 1067 ib[idx] = idx_value & ~1; 1068 } 1069 break; 1070 case 0x4f1c: 1071 /* ZB_BW_CNTL */ 1072 track->zb_cb_clear = !!(idx_value & (1 << 5)); 1073 if (p->rdev->hyperz_filp != p->filp) { 1074 if (idx_value & (R300_HIZ_ENABLE | 1075 R300_RD_COMP_ENABLE | 1076 R300_WR_COMP_ENABLE | 1077 R300_FAST_FILL_ENABLE)) 1078 goto fail; 1079 } 1080 break; 1081 case 0x4e04: 1082 /* RB3D_BLENDCNTL */ 1083 track->blend_read_enable = !!(idx_value & (1 << 2)); 1084 break; 1085 case 0x4f28: /* ZB_DEPTHCLEARVALUE */ 1086 break; 1087 case 0x4f30: /* ZB_MASK_OFFSET */ 1088 case 0x4f34: /* ZB_ZMASK_PITCH */ 1089 case 0x4f44: /* ZB_HIZ_OFFSET */ 1090 case 0x4f54: /* ZB_HIZ_PITCH */ 1091 if (idx_value && (p->rdev->hyperz_filp != p->filp)) 1092 goto fail; 1093 break; 1094 case 0x4028: 1095 if (idx_value && (p->rdev->hyperz_filp != p->filp)) 1096 goto fail; 1097 /* GB_Z_PEQ_CONFIG */ 1098 if (p->rdev->family >= CHIP_RV350) 1099 break; 1100 goto fail; 1101 break; 1102 case 0x4be8: 1103 /* valid register only on RV530 */ 1104 if (p->rdev->family == CHIP_RV530) 1105 break; 1106 /* fallthrough do not move */ 1107 default: 1108 goto fail; 1109 } 1110 return 0; 1111 fail: 1112 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d (val=%08x)\n", 1113 reg, idx, idx_value); 1114 return -EINVAL; 1115 } 1116 1117 static int r300_packet3_check(struct radeon_cs_parser *p, 1118 struct radeon_cs_packet *pkt) 1119 { 1120 struct radeon_cs_reloc *reloc; 1121 struct r100_cs_track *track; 1122 volatile uint32_t *ib; 1123 unsigned idx; 1124 int r; 1125 1126 ib = p->ib->ptr; 1127 idx = pkt->idx + 1; 1128 track = (struct r100_cs_track *)p->track; 1129 switch(pkt->opcode) { 1130 case PACKET3_3D_LOAD_VBPNTR: 1131 r = r100_packet3_load_vbpntr(p, pkt, idx); 1132 if (r) 1133 return r; 1134 break; 1135 case PACKET3_INDX_BUFFER: 1136 r = r100_cs_packet_next_reloc(p, &reloc); 1137 if (r) { 1138 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); 1139 r100_cs_dump_packet(p, pkt); 1140 return r; 1141 } 1142 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset); 1143 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); 1144 if (r) { 1145 return r; 1146 } 1147 break; 1148 /* Draw packet */ 1149 case PACKET3_3D_DRAW_IMMD: 1150 /* Number of dwords is vtx_size * (num_vertices - 1) 1151 * PRIM_WALK must be equal to 3 vertex data in embedded 1152 * in cmd stream */ 1153 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) { 1154 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1155 return -EINVAL; 1156 } 1157 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1158 track->immd_dwords = pkt->count - 1; 1159 r = r100_cs_track_check(p->rdev, track); 1160 if (r) { 1161 return r; 1162 } 1163 break; 1164 case PACKET3_3D_DRAW_IMMD_2: 1165 /* Number of dwords is vtx_size * (num_vertices - 1) 1166 * PRIM_WALK must be equal to 3 vertex data in embedded 1167 * in cmd stream */ 1168 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) { 1169 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1170 return -EINVAL; 1171 } 1172 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1173 track->immd_dwords = pkt->count; 1174 r = r100_cs_track_check(p->rdev, track); 1175 if (r) { 1176 return r; 1177 } 1178 break; 1179 case PACKET3_3D_DRAW_VBUF: 1180 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1181 r = r100_cs_track_check(p->rdev, track); 1182 if (r) { 1183 return r; 1184 } 1185 break; 1186 case PACKET3_3D_DRAW_VBUF_2: 1187 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1188 r = r100_cs_track_check(p->rdev, track); 1189 if (r) { 1190 return r; 1191 } 1192 break; 1193 case PACKET3_3D_DRAW_INDX: 1194 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1195 r = r100_cs_track_check(p->rdev, track); 1196 if (r) { 1197 return r; 1198 } 1199 break; 1200 case PACKET3_3D_DRAW_INDX_2: 1201 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1202 r = r100_cs_track_check(p->rdev, track); 1203 if (r) { 1204 return r; 1205 } 1206 break; 1207 case PACKET3_3D_CLEAR_HIZ: 1208 case PACKET3_3D_CLEAR_ZMASK: 1209 if (p->rdev->hyperz_filp != p->filp) 1210 return -EINVAL; 1211 break; 1212 case PACKET3_3D_CLEAR_CMASK: 1213 if (p->rdev->cmask_filp != p->filp) 1214 return -EINVAL; 1215 break; 1216 case PACKET3_NOP: 1217 break; 1218 default: 1219 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); 1220 return -EINVAL; 1221 } 1222 return 0; 1223 } 1224 1225 int r300_cs_parse(struct radeon_cs_parser *p) 1226 { 1227 struct radeon_cs_packet pkt; 1228 struct r100_cs_track *track; 1229 int r; 1230 1231 track = kzalloc(sizeof(*track), GFP_KERNEL); 1232 if (track == NULL) 1233 return -ENOMEM; 1234 r100_cs_track_clear(p->rdev, track); 1235 p->track = track; 1236 do { 1237 r = r100_cs_packet_parse(p, &pkt, p->idx); 1238 if (r) { 1239 return r; 1240 } 1241 p->idx += pkt.count + 2; 1242 switch (pkt.type) { 1243 case PACKET_TYPE0: 1244 r = r100_cs_parse_packet0(p, &pkt, 1245 p->rdev->config.r300.reg_safe_bm, 1246 p->rdev->config.r300.reg_safe_bm_size, 1247 &r300_packet0_check); 1248 break; 1249 case PACKET_TYPE2: 1250 break; 1251 case PACKET_TYPE3: 1252 r = r300_packet3_check(p, &pkt); 1253 break; 1254 default: 1255 DRM_ERROR("Unknown packet type %d !\n", pkt.type); 1256 return -EINVAL; 1257 } 1258 if (r) { 1259 return r; 1260 } 1261 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw); 1262 return 0; 1263 } 1264 1265 void r300_set_reg_safe(struct radeon_device *rdev) 1266 { 1267 rdev->config.r300.reg_safe_bm = r300_reg_safe_bm; 1268 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm); 1269 } 1270 1271 void r300_mc_program(struct radeon_device *rdev) 1272 { 1273 struct r100_mc_save save; 1274 int r; 1275 1276 r = r100_debugfs_mc_info_init(rdev); 1277 if (r) { 1278 dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n"); 1279 } 1280 1281 /* Stops all mc clients */ 1282 r100_mc_stop(rdev, &save); 1283 if (rdev->flags & RADEON_IS_AGP) { 1284 WREG32(R_00014C_MC_AGP_LOCATION, 1285 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) | 1286 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); 1287 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); 1288 WREG32(R_00015C_AGP_BASE_2, 1289 upper_32_bits(rdev->mc.agp_base) & 0xff); 1290 } else { 1291 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF); 1292 WREG32(R_000170_AGP_BASE, 0); 1293 WREG32(R_00015C_AGP_BASE_2, 0); 1294 } 1295 /* Wait for mc idle */ 1296 if (r300_mc_wait_for_idle(rdev)) 1297 DRM_INFO("Failed to wait MC idle before programming MC.\n"); 1298 /* Program MC, should be a 32bits limited address space */ 1299 WREG32(R_000148_MC_FB_LOCATION, 1300 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | 1301 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); 1302 r100_mc_resume(rdev, &save); 1303 } 1304 1305 void r300_clock_startup(struct radeon_device *rdev) 1306 { 1307 u32 tmp; 1308 1309 if (radeon_dynclks != -1 && radeon_dynclks) 1310 radeon_legacy_set_clock_gating(rdev, 1); 1311 /* We need to force on some of the block */ 1312 tmp = RREG32_PLL(R_00000D_SCLK_CNTL); 1313 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); 1314 if ((rdev->family == CHIP_RV350) || (rdev->family == CHIP_RV380)) 1315 tmp |= S_00000D_FORCE_VAP(1); 1316 WREG32_PLL(R_00000D_SCLK_CNTL, tmp); 1317 } 1318 1319 static int r300_startup(struct radeon_device *rdev) 1320 { 1321 int r; 1322 1323 /* set common regs */ 1324 r100_set_common_regs(rdev); 1325 /* program mc */ 1326 r300_mc_program(rdev); 1327 /* Resume clock */ 1328 r300_clock_startup(rdev); 1329 /* Initialize GPU configuration (# pipes, ...) */ 1330 r300_gpu_init(rdev); 1331 /* Initialize GART (initialize after TTM so we can allocate 1332 * memory through TTM but finalize after TTM) */ 1333 if (rdev->flags & RADEON_IS_PCIE) { 1334 r = rv370_pcie_gart_enable(rdev); 1335 if (r) 1336 return r; 1337 } 1338 1339 if (rdev->family == CHIP_R300 || 1340 rdev->family == CHIP_R350 || 1341 rdev->family == CHIP_RV350) 1342 r100_enable_bm(rdev); 1343 1344 if (rdev->flags & RADEON_IS_PCI) { 1345 r = r100_pci_gart_enable(rdev); 1346 if (r) 1347 return r; 1348 } 1349 1350 /* allocate wb buffer */ 1351 r = radeon_wb_init(rdev); 1352 if (r) 1353 return r; 1354 1355 /* Enable IRQ */ 1356 r100_irq_set(rdev); 1357 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 1358 /* 1M ring buffer */ 1359 r = r100_cp_init(rdev, 1024 * 1024); 1360 if (r) { 1361 dev_err(rdev->dev, "failled initializing CP (%d).\n", r); 1362 return r; 1363 } 1364 r = r100_ib_init(rdev); 1365 if (r) { 1366 dev_err(rdev->dev, "failled initializing IB (%d).\n", r); 1367 return r; 1368 } 1369 return 0; 1370 } 1371 1372 int r300_resume(struct radeon_device *rdev) 1373 { 1374 /* Make sur GART are not working */ 1375 if (rdev->flags & RADEON_IS_PCIE) 1376 rv370_pcie_gart_disable(rdev); 1377 if (rdev->flags & RADEON_IS_PCI) 1378 r100_pci_gart_disable(rdev); 1379 /* Resume clock before doing reset */ 1380 r300_clock_startup(rdev); 1381 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 1382 if (radeon_asic_reset(rdev)) { 1383 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 1384 RREG32(R_000E40_RBBM_STATUS), 1385 RREG32(R_0007C0_CP_STAT)); 1386 } 1387 /* post */ 1388 radeon_combios_asic_init(rdev->ddev); 1389 /* Resume clock after posting */ 1390 r300_clock_startup(rdev); 1391 /* Initialize surface registers */ 1392 radeon_surface_init(rdev); 1393 return r300_startup(rdev); 1394 } 1395 1396 int r300_suspend(struct radeon_device *rdev) 1397 { 1398 r100_cp_disable(rdev); 1399 radeon_wb_disable(rdev); 1400 r100_irq_disable(rdev); 1401 if (rdev->flags & RADEON_IS_PCIE) 1402 rv370_pcie_gart_disable(rdev); 1403 if (rdev->flags & RADEON_IS_PCI) 1404 r100_pci_gart_disable(rdev); 1405 return 0; 1406 } 1407 1408 void r300_fini(struct radeon_device *rdev) 1409 { 1410 r100_cp_fini(rdev); 1411 radeon_wb_fini(rdev); 1412 r100_ib_fini(rdev); 1413 radeon_gem_fini(rdev); 1414 if (rdev->flags & RADEON_IS_PCIE) 1415 rv370_pcie_gart_fini(rdev); 1416 if (rdev->flags & RADEON_IS_PCI) 1417 r100_pci_gart_fini(rdev); 1418 radeon_agp_fini(rdev); 1419 radeon_irq_kms_fini(rdev); 1420 radeon_fence_driver_fini(rdev); 1421 radeon_bo_fini(rdev); 1422 radeon_atombios_fini(rdev); 1423 kfree(rdev->bios); 1424 rdev->bios = NULL; 1425 } 1426 1427 int r300_init(struct radeon_device *rdev) 1428 { 1429 int r; 1430 1431 /* Disable VGA */ 1432 r100_vga_render_disable(rdev); 1433 /* Initialize scratch registers */ 1434 radeon_scratch_init(rdev); 1435 /* Initialize surface registers */ 1436 radeon_surface_init(rdev); 1437 /* TODO: disable VGA need to use VGA request */ 1438 /* restore some register to sane defaults */ 1439 r100_restore_sanity(rdev); 1440 /* BIOS*/ 1441 if (!radeon_get_bios(rdev)) { 1442 if (ASIC_IS_AVIVO(rdev)) 1443 return -EINVAL; 1444 } 1445 if (rdev->is_atom_bios) { 1446 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); 1447 return -EINVAL; 1448 } else { 1449 r = radeon_combios_init(rdev); 1450 if (r) 1451 return r; 1452 } 1453 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 1454 if (radeon_asic_reset(rdev)) { 1455 dev_warn(rdev->dev, 1456 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 1457 RREG32(R_000E40_RBBM_STATUS), 1458 RREG32(R_0007C0_CP_STAT)); 1459 } 1460 /* check if cards are posted or not */ 1461 if (radeon_boot_test_post_card(rdev) == false) 1462 return -EINVAL; 1463 /* Set asic errata */ 1464 r300_errata(rdev); 1465 /* Initialize clocks */ 1466 radeon_get_clock_info(rdev->ddev); 1467 /* initialize AGP */ 1468 if (rdev->flags & RADEON_IS_AGP) { 1469 r = radeon_agp_init(rdev); 1470 if (r) { 1471 radeon_agp_disable(rdev); 1472 } 1473 } 1474 /* initialize memory controller */ 1475 r300_mc_init(rdev); 1476 /* Fence driver */ 1477 r = radeon_fence_driver_init(rdev); 1478 if (r) 1479 return r; 1480 r = radeon_irq_kms_init(rdev); 1481 if (r) 1482 return r; 1483 /* Memory manager */ 1484 r = radeon_bo_init(rdev); 1485 if (r) 1486 return r; 1487 if (rdev->flags & RADEON_IS_PCIE) { 1488 r = rv370_pcie_gart_init(rdev); 1489 if (r) 1490 return r; 1491 } 1492 if (rdev->flags & RADEON_IS_PCI) { 1493 r = r100_pci_gart_init(rdev); 1494 if (r) 1495 return r; 1496 } 1497 r300_set_reg_safe(rdev); 1498 rdev->accel_working = true; 1499 r = r300_startup(rdev); 1500 if (r) { 1501 /* Somethings want wront with the accel init stop accel */ 1502 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 1503 r100_cp_fini(rdev); 1504 radeon_wb_fini(rdev); 1505 r100_ib_fini(rdev); 1506 radeon_irq_kms_fini(rdev); 1507 if (rdev->flags & RADEON_IS_PCIE) 1508 rv370_pcie_gart_fini(rdev); 1509 if (rdev->flags & RADEON_IS_PCI) 1510 r100_pci_gart_fini(rdev); 1511 radeon_agp_fini(rdev); 1512 rdev->accel_working = false; 1513 } 1514 return 0; 1515 } 1516