1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/seq_file.h> 29 #include "drmP.h" 30 #include "drm.h" 31 #include "radeon_reg.h" 32 #include "radeon.h" 33 #include "radeon_drm.h" 34 #include "r100_track.h" 35 #include "r300d.h" 36 37 #include "r300_reg_safe.h" 38 39 /* r300,r350,rv350,rv370,rv380 depends on : */ 40 void r100_hdp_reset(struct radeon_device *rdev); 41 int r100_cp_reset(struct radeon_device *rdev); 42 int r100_rb2d_reset(struct radeon_device *rdev); 43 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); 44 int r100_pci_gart_enable(struct radeon_device *rdev); 45 void r100_mc_setup(struct radeon_device *rdev); 46 void r100_mc_disable_clients(struct radeon_device *rdev); 47 int r100_gui_wait_for_idle(struct radeon_device *rdev); 48 int r100_cs_packet_parse(struct radeon_cs_parser *p, 49 struct radeon_cs_packet *pkt, 50 unsigned idx); 51 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p); 52 int r100_cs_parse_packet0(struct radeon_cs_parser *p, 53 struct radeon_cs_packet *pkt, 54 const unsigned *auth, unsigned n, 55 radeon_packet0_check_t check); 56 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, 57 struct radeon_cs_packet *pkt, 58 struct radeon_object *robj); 59 60 /* This files gather functions specifics to: 61 * r300,r350,rv350,rv370,rv380 62 * 63 * Some of these functions might be used by newer ASICs. 64 */ 65 void r300_gpu_init(struct radeon_device *rdev); 66 int r300_mc_wait_for_idle(struct radeon_device *rdev); 67 int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev); 68 69 70 /* 71 * rv370,rv380 PCIE GART 72 */ 73 void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev) 74 { 75 uint32_t tmp; 76 int i; 77 78 /* Workaround HW bug do flush 2 times */ 79 for (i = 0; i < 2; i++) { 80 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 81 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB); 82 (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 83 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); 84 } 85 mb(); 86 } 87 88 int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) 89 { 90 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr; 91 92 if (i < 0 || i > rdev->gart.num_gpu_pages) { 93 return -EINVAL; 94 } 95 addr = (lower_32_bits(addr) >> 8) | 96 ((upper_32_bits(addr) & 0xff) << 24) | 97 0xc; 98 /* on x86 we want this to be CPU endian, on powerpc 99 * on powerpc without HW swappers, it'll get swapped on way 100 * into VRAM - so no need for cpu_to_le32 on VRAM tables */ 101 writel(addr, ((void __iomem *)ptr) + (i * 4)); 102 return 0; 103 } 104 105 int rv370_pcie_gart_init(struct radeon_device *rdev) 106 { 107 int r; 108 109 if (rdev->gart.table.vram.robj) { 110 WARN(1, "RV370 PCIE GART already initialized.\n"); 111 return 0; 112 } 113 /* Initialize common gart structure */ 114 r = radeon_gart_init(rdev); 115 if (r) 116 return r; 117 r = rv370_debugfs_pcie_gart_info_init(rdev); 118 if (r) 119 DRM_ERROR("Failed to register debugfs file for PCIE gart !\n"); 120 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; 121 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush; 122 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page; 123 return radeon_gart_table_vram_alloc(rdev); 124 } 125 126 int rv370_pcie_gart_enable(struct radeon_device *rdev) 127 { 128 uint32_t table_addr; 129 uint32_t tmp; 130 int r; 131 132 if (rdev->gart.table.vram.robj == NULL) { 133 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 134 return -EINVAL; 135 } 136 r = radeon_gart_table_vram_pin(rdev); 137 if (r) 138 return r; 139 /* discard memory request outside of configured range */ 140 tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; 141 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); 142 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_location); 143 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 4096; 144 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp); 145 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0); 146 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0); 147 table_addr = rdev->gart.table_addr; 148 WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr); 149 /* FIXME: setup default page */ 150 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_location); 151 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0); 152 /* Clear error */ 153 WREG32_PCIE(0x18, 0); 154 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 155 tmp |= RADEON_PCIE_TX_GART_EN; 156 tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; 157 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); 158 rv370_pcie_gart_tlb_flush(rdev); 159 DRM_INFO("PCIE GART of %uM enabled (table at 0x%08X).\n", 160 (unsigned)(rdev->mc.gtt_size >> 20), table_addr); 161 rdev->gart.ready = true; 162 return 0; 163 } 164 165 void rv370_pcie_gart_disable(struct radeon_device *rdev) 166 { 167 uint32_t tmp; 168 169 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 170 tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; 171 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN); 172 if (rdev->gart.table.vram.robj) { 173 radeon_object_kunmap(rdev->gart.table.vram.robj); 174 radeon_object_unpin(rdev->gart.table.vram.robj); 175 } 176 } 177 178 void rv370_pcie_gart_fini(struct radeon_device *rdev) 179 { 180 rv370_pcie_gart_disable(rdev); 181 radeon_gart_table_vram_free(rdev); 182 radeon_gart_fini(rdev); 183 } 184 185 /* 186 * MC 187 */ 188 int r300_mc_init(struct radeon_device *rdev) 189 { 190 int r; 191 192 if (r100_debugfs_rbbm_init(rdev)) { 193 DRM_ERROR("Failed to register debugfs file for RBBM !\n"); 194 } 195 196 r300_gpu_init(rdev); 197 r100_pci_gart_disable(rdev); 198 if (rdev->flags & RADEON_IS_PCIE) { 199 rv370_pcie_gart_disable(rdev); 200 } 201 202 /* Setup GPU memory space */ 203 rdev->mc.vram_location = 0xFFFFFFFFUL; 204 rdev->mc.gtt_location = 0xFFFFFFFFUL; 205 if (rdev->flags & RADEON_IS_AGP) { 206 r = radeon_agp_init(rdev); 207 if (r) { 208 printk(KERN_WARNING "[drm] Disabling AGP\n"); 209 rdev->flags &= ~RADEON_IS_AGP; 210 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; 211 } else { 212 rdev->mc.gtt_location = rdev->mc.agp_base; 213 } 214 } 215 r = radeon_mc_setup(rdev); 216 if (r) { 217 return r; 218 } 219 220 /* Program GPU memory space */ 221 r100_mc_disable_clients(rdev); 222 if (r300_mc_wait_for_idle(rdev)) { 223 printk(KERN_WARNING "Failed to wait MC idle while " 224 "programming pipes. Bad things might happen.\n"); 225 } 226 r100_mc_setup(rdev); 227 return 0; 228 } 229 230 void r300_mc_fini(struct radeon_device *rdev) 231 { 232 } 233 234 235 /* 236 * Fence emission 237 */ 238 void r300_fence_ring_emit(struct radeon_device *rdev, 239 struct radeon_fence *fence) 240 { 241 /* Who ever call radeon_fence_emit should call ring_lock and ask 242 * for enough space (today caller are ib schedule and buffer move) */ 243 /* Write SC register so SC & US assert idle */ 244 radeon_ring_write(rdev, PACKET0(0x43E0, 0)); 245 radeon_ring_write(rdev, 0); 246 radeon_ring_write(rdev, PACKET0(0x43E4, 0)); 247 radeon_ring_write(rdev, 0); 248 /* Flush 3D cache */ 249 radeon_ring_write(rdev, PACKET0(0x4E4C, 0)); 250 radeon_ring_write(rdev, (2 << 0)); 251 radeon_ring_write(rdev, PACKET0(0x4F18, 0)); 252 radeon_ring_write(rdev, (1 << 0)); 253 /* Wait until IDLE & CLEAN */ 254 radeon_ring_write(rdev, PACKET0(0x1720, 0)); 255 radeon_ring_write(rdev, (1 << 17) | (1 << 16) | (1 << 9)); 256 /* Emit fence sequence & fire IRQ */ 257 radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0)); 258 radeon_ring_write(rdev, fence->seq); 259 radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0)); 260 radeon_ring_write(rdev, RADEON_SW_INT_FIRE); 261 } 262 263 264 /* 265 * Global GPU functions 266 */ 267 int r300_copy_dma(struct radeon_device *rdev, 268 uint64_t src_offset, 269 uint64_t dst_offset, 270 unsigned num_pages, 271 struct radeon_fence *fence) 272 { 273 uint32_t size; 274 uint32_t cur_size; 275 int i, num_loops; 276 int r = 0; 277 278 /* radeon pitch is /64 */ 279 size = num_pages << PAGE_SHIFT; 280 num_loops = DIV_ROUND_UP(size, 0x1FFFFF); 281 r = radeon_ring_lock(rdev, num_loops * 4 + 64); 282 if (r) { 283 DRM_ERROR("radeon: moving bo (%d).\n", r); 284 return r; 285 } 286 /* Must wait for 2D idle & clean before DMA or hangs might happen */ 287 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0 )); 288 radeon_ring_write(rdev, (1 << 16)); 289 for (i = 0; i < num_loops; i++) { 290 cur_size = size; 291 if (cur_size > 0x1FFFFF) { 292 cur_size = 0x1FFFFF; 293 } 294 size -= cur_size; 295 radeon_ring_write(rdev, PACKET0(0x720, 2)); 296 radeon_ring_write(rdev, src_offset); 297 radeon_ring_write(rdev, dst_offset); 298 radeon_ring_write(rdev, cur_size | (1 << 31) | (1 << 30)); 299 src_offset += cur_size; 300 dst_offset += cur_size; 301 } 302 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); 303 radeon_ring_write(rdev, RADEON_WAIT_DMA_GUI_IDLE); 304 if (fence) { 305 r = radeon_fence_emit(rdev, fence); 306 } 307 radeon_ring_unlock_commit(rdev); 308 return r; 309 } 310 311 void r300_ring_start(struct radeon_device *rdev) 312 { 313 unsigned gb_tile_config; 314 int r; 315 316 /* Sub pixel 1/12 so we can have 4K rendering according to doc */ 317 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16); 318 switch(rdev->num_gb_pipes) { 319 case 2: 320 gb_tile_config |= R300_PIPE_COUNT_R300; 321 break; 322 case 3: 323 gb_tile_config |= R300_PIPE_COUNT_R420_3P; 324 break; 325 case 4: 326 gb_tile_config |= R300_PIPE_COUNT_R420; 327 break; 328 case 1: 329 default: 330 gb_tile_config |= R300_PIPE_COUNT_RV350; 331 break; 332 } 333 334 r = radeon_ring_lock(rdev, 64); 335 if (r) { 336 return; 337 } 338 radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0)); 339 radeon_ring_write(rdev, 340 RADEON_ISYNC_ANY2D_IDLE3D | 341 RADEON_ISYNC_ANY3D_IDLE2D | 342 RADEON_ISYNC_WAIT_IDLEGUI | 343 RADEON_ISYNC_CPSCRATCH_IDLEGUI); 344 radeon_ring_write(rdev, PACKET0(R300_GB_TILE_CONFIG, 0)); 345 radeon_ring_write(rdev, gb_tile_config); 346 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); 347 radeon_ring_write(rdev, 348 RADEON_WAIT_2D_IDLECLEAN | 349 RADEON_WAIT_3D_IDLECLEAN); 350 radeon_ring_write(rdev, PACKET0(0x170C, 0)); 351 radeon_ring_write(rdev, 1 << 31); 352 radeon_ring_write(rdev, PACKET0(R300_GB_SELECT, 0)); 353 radeon_ring_write(rdev, 0); 354 radeon_ring_write(rdev, PACKET0(R300_GB_ENABLE, 0)); 355 radeon_ring_write(rdev, 0); 356 radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 357 radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); 358 radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); 359 radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE); 360 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); 361 radeon_ring_write(rdev, 362 RADEON_WAIT_2D_IDLECLEAN | 363 RADEON_WAIT_3D_IDLECLEAN); 364 radeon_ring_write(rdev, PACKET0(R300_GB_AA_CONFIG, 0)); 365 radeon_ring_write(rdev, 0); 366 radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 367 radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); 368 radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); 369 radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE); 370 radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS0, 0)); 371 radeon_ring_write(rdev, 372 ((6 << R300_MS_X0_SHIFT) | 373 (6 << R300_MS_Y0_SHIFT) | 374 (6 << R300_MS_X1_SHIFT) | 375 (6 << R300_MS_Y1_SHIFT) | 376 (6 << R300_MS_X2_SHIFT) | 377 (6 << R300_MS_Y2_SHIFT) | 378 (6 << R300_MSBD0_Y_SHIFT) | 379 (6 << R300_MSBD0_X_SHIFT))); 380 radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS1, 0)); 381 radeon_ring_write(rdev, 382 ((6 << R300_MS_X3_SHIFT) | 383 (6 << R300_MS_Y3_SHIFT) | 384 (6 << R300_MS_X4_SHIFT) | 385 (6 << R300_MS_Y4_SHIFT) | 386 (6 << R300_MS_X5_SHIFT) | 387 (6 << R300_MS_Y5_SHIFT) | 388 (6 << R300_MSBD1_SHIFT))); 389 radeon_ring_write(rdev, PACKET0(R300_GA_ENHANCE, 0)); 390 radeon_ring_write(rdev, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL); 391 radeon_ring_write(rdev, PACKET0(R300_GA_POLY_MODE, 0)); 392 radeon_ring_write(rdev, 393 R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE); 394 radeon_ring_write(rdev, PACKET0(R300_GA_ROUND_MODE, 0)); 395 radeon_ring_write(rdev, 396 R300_GEOMETRY_ROUND_NEAREST | 397 R300_COLOR_ROUND_NEAREST); 398 radeon_ring_unlock_commit(rdev); 399 } 400 401 void r300_errata(struct radeon_device *rdev) 402 { 403 rdev->pll_errata = 0; 404 405 if (rdev->family == CHIP_R300 && 406 (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) { 407 rdev->pll_errata |= CHIP_ERRATA_R300_CG; 408 } 409 } 410 411 int r300_mc_wait_for_idle(struct radeon_device *rdev) 412 { 413 unsigned i; 414 uint32_t tmp; 415 416 for (i = 0; i < rdev->usec_timeout; i++) { 417 /* read MC_STATUS */ 418 tmp = RREG32(0x0150); 419 if (tmp & (1 << 4)) { 420 return 0; 421 } 422 DRM_UDELAY(1); 423 } 424 return -1; 425 } 426 427 void r300_gpu_init(struct radeon_device *rdev) 428 { 429 uint32_t gb_tile_config, tmp; 430 431 r100_hdp_reset(rdev); 432 /* FIXME: rv380 one pipes ? */ 433 if ((rdev->family == CHIP_R300) || (rdev->family == CHIP_R350)) { 434 /* r300,r350 */ 435 rdev->num_gb_pipes = 2; 436 } else { 437 /* rv350,rv370,rv380 */ 438 rdev->num_gb_pipes = 1; 439 } 440 rdev->num_z_pipes = 1; 441 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16); 442 switch (rdev->num_gb_pipes) { 443 case 2: 444 gb_tile_config |= R300_PIPE_COUNT_R300; 445 break; 446 case 3: 447 gb_tile_config |= R300_PIPE_COUNT_R420_3P; 448 break; 449 case 4: 450 gb_tile_config |= R300_PIPE_COUNT_R420; 451 break; 452 default: 453 case 1: 454 gb_tile_config |= R300_PIPE_COUNT_RV350; 455 break; 456 } 457 WREG32(R300_GB_TILE_CONFIG, gb_tile_config); 458 459 if (r100_gui_wait_for_idle(rdev)) { 460 printk(KERN_WARNING "Failed to wait GUI idle while " 461 "programming pipes. Bad things might happen.\n"); 462 } 463 464 tmp = RREG32(0x170C); 465 WREG32(0x170C, tmp | (1 << 31)); 466 467 WREG32(R300_RB2D_DSTCACHE_MODE, 468 R300_DC_AUTOFLUSH_ENABLE | 469 R300_DC_DC_DISABLE_IGNORE_PE); 470 471 if (r100_gui_wait_for_idle(rdev)) { 472 printk(KERN_WARNING "Failed to wait GUI idle while " 473 "programming pipes. Bad things might happen.\n"); 474 } 475 if (r300_mc_wait_for_idle(rdev)) { 476 printk(KERN_WARNING "Failed to wait MC idle while " 477 "programming pipes. Bad things might happen.\n"); 478 } 479 DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n", 480 rdev->num_gb_pipes, rdev->num_z_pipes); 481 } 482 483 int r300_ga_reset(struct radeon_device *rdev) 484 { 485 uint32_t tmp; 486 bool reinit_cp; 487 int i; 488 489 reinit_cp = rdev->cp.ready; 490 rdev->cp.ready = false; 491 for (i = 0; i < rdev->usec_timeout; i++) { 492 WREG32(RADEON_CP_CSQ_MODE, 0); 493 WREG32(RADEON_CP_CSQ_CNTL, 0); 494 WREG32(RADEON_RBBM_SOFT_RESET, 0x32005); 495 (void)RREG32(RADEON_RBBM_SOFT_RESET); 496 udelay(200); 497 WREG32(RADEON_RBBM_SOFT_RESET, 0); 498 /* Wait to prevent race in RBBM_STATUS */ 499 mdelay(1); 500 tmp = RREG32(RADEON_RBBM_STATUS); 501 if (tmp & ((1 << 20) | (1 << 26))) { 502 DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)", tmp); 503 /* GA still busy soft reset it */ 504 WREG32(0x429C, 0x200); 505 WREG32(R300_VAP_PVS_STATE_FLUSH_REG, 0); 506 WREG32(0x43E0, 0); 507 WREG32(0x43E4, 0); 508 WREG32(0x24AC, 0); 509 } 510 /* Wait to prevent race in RBBM_STATUS */ 511 mdelay(1); 512 tmp = RREG32(RADEON_RBBM_STATUS); 513 if (!(tmp & ((1 << 20) | (1 << 26)))) { 514 break; 515 } 516 } 517 for (i = 0; i < rdev->usec_timeout; i++) { 518 tmp = RREG32(RADEON_RBBM_STATUS); 519 if (!(tmp & ((1 << 20) | (1 << 26)))) { 520 DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n", 521 tmp); 522 if (reinit_cp) { 523 return r100_cp_init(rdev, rdev->cp.ring_size); 524 } 525 return 0; 526 } 527 DRM_UDELAY(1); 528 } 529 tmp = RREG32(RADEON_RBBM_STATUS); 530 DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp); 531 return -1; 532 } 533 534 int r300_gpu_reset(struct radeon_device *rdev) 535 { 536 uint32_t status; 537 538 /* reset order likely matter */ 539 status = RREG32(RADEON_RBBM_STATUS); 540 /* reset HDP */ 541 r100_hdp_reset(rdev); 542 /* reset rb2d */ 543 if (status & ((1 << 17) | (1 << 18) | (1 << 27))) { 544 r100_rb2d_reset(rdev); 545 } 546 /* reset GA */ 547 if (status & ((1 << 20) | (1 << 26))) { 548 r300_ga_reset(rdev); 549 } 550 /* reset CP */ 551 status = RREG32(RADEON_RBBM_STATUS); 552 if (status & (1 << 16)) { 553 r100_cp_reset(rdev); 554 } 555 /* Check if GPU is idle */ 556 status = RREG32(RADEON_RBBM_STATUS); 557 if (status & (1 << 31)) { 558 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status); 559 return -1; 560 } 561 DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status); 562 return 0; 563 } 564 565 566 /* 567 * r300,r350,rv350,rv380 VRAM info 568 */ 569 void r300_vram_info(struct radeon_device *rdev) 570 { 571 uint32_t tmp; 572 573 /* DDR for all card after R300 & IGP */ 574 rdev->mc.vram_is_ddr = true; 575 tmp = RREG32(RADEON_MEM_CNTL); 576 if (tmp & R300_MEM_NUM_CHANNELS_MASK) { 577 rdev->mc.vram_width = 128; 578 } else { 579 rdev->mc.vram_width = 64; 580 } 581 582 r100_vram_init_sizes(rdev); 583 } 584 585 586 /* 587 * PCIE Lanes 588 */ 589 590 void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes) 591 { 592 uint32_t link_width_cntl, mask; 593 594 if (rdev->flags & RADEON_IS_IGP) 595 return; 596 597 if (!(rdev->flags & RADEON_IS_PCIE)) 598 return; 599 600 /* FIXME wait for idle */ 601 602 switch (lanes) { 603 case 0: 604 mask = RADEON_PCIE_LC_LINK_WIDTH_X0; 605 break; 606 case 1: 607 mask = RADEON_PCIE_LC_LINK_WIDTH_X1; 608 break; 609 case 2: 610 mask = RADEON_PCIE_LC_LINK_WIDTH_X2; 611 break; 612 case 4: 613 mask = RADEON_PCIE_LC_LINK_WIDTH_X4; 614 break; 615 case 8: 616 mask = RADEON_PCIE_LC_LINK_WIDTH_X8; 617 break; 618 case 12: 619 mask = RADEON_PCIE_LC_LINK_WIDTH_X12; 620 break; 621 case 16: 622 default: 623 mask = RADEON_PCIE_LC_LINK_WIDTH_X16; 624 break; 625 } 626 627 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 628 629 if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) == 630 (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT)) 631 return; 632 633 link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK | 634 RADEON_PCIE_LC_RECONFIG_NOW | 635 RADEON_PCIE_LC_RECONFIG_LATER | 636 RADEON_PCIE_LC_SHORT_RECONFIG_EN); 637 link_width_cntl |= mask; 638 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 639 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl | 640 RADEON_PCIE_LC_RECONFIG_NOW)); 641 642 /* wait for lane set to complete */ 643 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 644 while (link_width_cntl == 0xffffffff) 645 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 646 647 } 648 649 650 /* 651 * Debugfs info 652 */ 653 #if defined(CONFIG_DEBUG_FS) 654 static int rv370_debugfs_pcie_gart_info(struct seq_file *m, void *data) 655 { 656 struct drm_info_node *node = (struct drm_info_node *) m->private; 657 struct drm_device *dev = node->minor->dev; 658 struct radeon_device *rdev = dev->dev_private; 659 uint32_t tmp; 660 661 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 662 seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp); 663 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE); 664 seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp); 665 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO); 666 seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp); 667 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI); 668 seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp); 669 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO); 670 seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp); 671 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI); 672 seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp); 673 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR); 674 seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp); 675 return 0; 676 } 677 678 static struct drm_info_list rv370_pcie_gart_info_list[] = { 679 {"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info, 0, NULL}, 680 }; 681 #endif 682 683 int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev) 684 { 685 #if defined(CONFIG_DEBUG_FS) 686 return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1); 687 #else 688 return 0; 689 #endif 690 } 691 692 693 /* 694 * CS functions 695 */ 696 static int r300_packet0_check(struct radeon_cs_parser *p, 697 struct radeon_cs_packet *pkt, 698 unsigned idx, unsigned reg) 699 { 700 struct radeon_cs_reloc *reloc; 701 struct r100_cs_track *track; 702 volatile uint32_t *ib; 703 uint32_t tmp, tile_flags = 0; 704 unsigned i; 705 int r; 706 u32 idx_value; 707 708 ib = p->ib->ptr; 709 track = (struct r100_cs_track *)p->track; 710 idx_value = radeon_get_ib_value(p, idx); 711 712 switch(reg) { 713 case AVIVO_D1MODE_VLINE_START_END: 714 case RADEON_CRTC_GUI_TRIG_VLINE: 715 r = r100_cs_packet_parse_vline(p); 716 if (r) { 717 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 718 idx, reg); 719 r100_cs_dump_packet(p, pkt); 720 return r; 721 } 722 break; 723 case RADEON_DST_PITCH_OFFSET: 724 case RADEON_SRC_PITCH_OFFSET: 725 r = r100_reloc_pitch_offset(p, pkt, idx, reg); 726 if (r) 727 return r; 728 break; 729 case R300_RB3D_COLOROFFSET0: 730 case R300_RB3D_COLOROFFSET1: 731 case R300_RB3D_COLOROFFSET2: 732 case R300_RB3D_COLOROFFSET3: 733 i = (reg - R300_RB3D_COLOROFFSET0) >> 2; 734 r = r100_cs_packet_next_reloc(p, &reloc); 735 if (r) { 736 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 737 idx, reg); 738 r100_cs_dump_packet(p, pkt); 739 return r; 740 } 741 track->cb[i].robj = reloc->robj; 742 track->cb[i].offset = idx_value; 743 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 744 break; 745 case R300_ZB_DEPTHOFFSET: 746 r = r100_cs_packet_next_reloc(p, &reloc); 747 if (r) { 748 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 749 idx, reg); 750 r100_cs_dump_packet(p, pkt); 751 return r; 752 } 753 track->zb.robj = reloc->robj; 754 track->zb.offset = idx_value; 755 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 756 break; 757 case R300_TX_OFFSET_0: 758 case R300_TX_OFFSET_0+4: 759 case R300_TX_OFFSET_0+8: 760 case R300_TX_OFFSET_0+12: 761 case R300_TX_OFFSET_0+16: 762 case R300_TX_OFFSET_0+20: 763 case R300_TX_OFFSET_0+24: 764 case R300_TX_OFFSET_0+28: 765 case R300_TX_OFFSET_0+32: 766 case R300_TX_OFFSET_0+36: 767 case R300_TX_OFFSET_0+40: 768 case R300_TX_OFFSET_0+44: 769 case R300_TX_OFFSET_0+48: 770 case R300_TX_OFFSET_0+52: 771 case R300_TX_OFFSET_0+56: 772 case R300_TX_OFFSET_0+60: 773 i = (reg - R300_TX_OFFSET_0) >> 2; 774 r = r100_cs_packet_next_reloc(p, &reloc); 775 if (r) { 776 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 777 idx, reg); 778 r100_cs_dump_packet(p, pkt); 779 return r; 780 } 781 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 782 track->textures[i].robj = reloc->robj; 783 break; 784 /* Tracked registers */ 785 case 0x2084: 786 /* VAP_VF_CNTL */ 787 track->vap_vf_cntl = idx_value; 788 break; 789 case 0x20B4: 790 /* VAP_VTX_SIZE */ 791 track->vtx_size = idx_value & 0x7F; 792 break; 793 case 0x2134: 794 /* VAP_VF_MAX_VTX_INDX */ 795 track->max_indx = idx_value & 0x00FFFFFFUL; 796 break; 797 case 0x43E4: 798 /* SC_SCISSOR1 */ 799 track->maxy = ((idx_value >> 13) & 0x1FFF) + 1; 800 if (p->rdev->family < CHIP_RV515) { 801 track->maxy -= 1440; 802 } 803 break; 804 case 0x4E00: 805 /* RB3D_CCTL */ 806 track->num_cb = ((idx_value >> 5) & 0x3) + 1; 807 break; 808 case 0x4E38: 809 case 0x4E3C: 810 case 0x4E40: 811 case 0x4E44: 812 /* RB3D_COLORPITCH0 */ 813 /* RB3D_COLORPITCH1 */ 814 /* RB3D_COLORPITCH2 */ 815 /* RB3D_COLORPITCH3 */ 816 r = r100_cs_packet_next_reloc(p, &reloc); 817 if (r) { 818 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 819 idx, reg); 820 r100_cs_dump_packet(p, pkt); 821 return r; 822 } 823 824 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 825 tile_flags |= R300_COLOR_TILE_ENABLE; 826 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) 827 tile_flags |= R300_COLOR_MICROTILE_ENABLE; 828 829 tmp = idx_value & ~(0x7 << 16); 830 tmp |= tile_flags; 831 ib[idx] = tmp; 832 833 i = (reg - 0x4E38) >> 2; 834 track->cb[i].pitch = idx_value & 0x3FFE; 835 switch (((idx_value >> 21) & 0xF)) { 836 case 9: 837 case 11: 838 case 12: 839 track->cb[i].cpp = 1; 840 break; 841 case 3: 842 case 4: 843 case 13: 844 case 15: 845 track->cb[i].cpp = 2; 846 break; 847 case 6: 848 track->cb[i].cpp = 4; 849 break; 850 case 10: 851 track->cb[i].cpp = 8; 852 break; 853 case 7: 854 track->cb[i].cpp = 16; 855 break; 856 default: 857 DRM_ERROR("Invalid color buffer format (%d) !\n", 858 ((idx_value >> 21) & 0xF)); 859 return -EINVAL; 860 } 861 break; 862 case 0x4F00: 863 /* ZB_CNTL */ 864 if (idx_value & 2) { 865 track->z_enabled = true; 866 } else { 867 track->z_enabled = false; 868 } 869 break; 870 case 0x4F10: 871 /* ZB_FORMAT */ 872 switch ((idx_value & 0xF)) { 873 case 0: 874 case 1: 875 track->zb.cpp = 2; 876 break; 877 case 2: 878 track->zb.cpp = 4; 879 break; 880 default: 881 DRM_ERROR("Invalid z buffer format (%d) !\n", 882 (idx_value & 0xF)); 883 return -EINVAL; 884 } 885 break; 886 case 0x4F24: 887 /* ZB_DEPTHPITCH */ 888 r = r100_cs_packet_next_reloc(p, &reloc); 889 if (r) { 890 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 891 idx, reg); 892 r100_cs_dump_packet(p, pkt); 893 return r; 894 } 895 896 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 897 tile_flags |= R300_DEPTHMACROTILE_ENABLE; 898 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) 899 tile_flags |= R300_DEPTHMICROTILE_TILED;; 900 901 tmp = idx_value & ~(0x7 << 16); 902 tmp |= tile_flags; 903 ib[idx] = tmp; 904 905 track->zb.pitch = idx_value & 0x3FFC; 906 break; 907 case 0x4104: 908 for (i = 0; i < 16; i++) { 909 bool enabled; 910 911 enabled = !!(idx_value & (1 << i)); 912 track->textures[i].enabled = enabled; 913 } 914 break; 915 case 0x44C0: 916 case 0x44C4: 917 case 0x44C8: 918 case 0x44CC: 919 case 0x44D0: 920 case 0x44D4: 921 case 0x44D8: 922 case 0x44DC: 923 case 0x44E0: 924 case 0x44E4: 925 case 0x44E8: 926 case 0x44EC: 927 case 0x44F0: 928 case 0x44F4: 929 case 0x44F8: 930 case 0x44FC: 931 /* TX_FORMAT1_[0-15] */ 932 i = (reg - 0x44C0) >> 2; 933 tmp = (idx_value >> 25) & 0x3; 934 track->textures[i].tex_coord_type = tmp; 935 switch ((idx_value & 0x1F)) { 936 case R300_TX_FORMAT_X8: 937 case R300_TX_FORMAT_Y4X4: 938 case R300_TX_FORMAT_Z3Y3X2: 939 track->textures[i].cpp = 1; 940 break; 941 case R300_TX_FORMAT_X16: 942 case R300_TX_FORMAT_Y8X8: 943 case R300_TX_FORMAT_Z5Y6X5: 944 case R300_TX_FORMAT_Z6Y5X5: 945 case R300_TX_FORMAT_W4Z4Y4X4: 946 case R300_TX_FORMAT_W1Z5Y5X5: 947 case R300_TX_FORMAT_DXT1: 948 case R300_TX_FORMAT_D3DMFT_CxV8U8: 949 case R300_TX_FORMAT_B8G8_B8G8: 950 case R300_TX_FORMAT_G8R8_G8B8: 951 track->textures[i].cpp = 2; 952 break; 953 case R300_TX_FORMAT_Y16X16: 954 case R300_TX_FORMAT_Z11Y11X10: 955 case R300_TX_FORMAT_Z10Y11X11: 956 case R300_TX_FORMAT_W8Z8Y8X8: 957 case R300_TX_FORMAT_W2Z10Y10X10: 958 case 0x17: 959 case R300_TX_FORMAT_FL_I32: 960 case 0x1e: 961 case R300_TX_FORMAT_DXT3: 962 case R300_TX_FORMAT_DXT5: 963 track->textures[i].cpp = 4; 964 break; 965 case R300_TX_FORMAT_W16Z16Y16X16: 966 case R300_TX_FORMAT_FL_R16G16B16A16: 967 case R300_TX_FORMAT_FL_I32A32: 968 track->textures[i].cpp = 8; 969 break; 970 case R300_TX_FORMAT_FL_R32G32B32A32: 971 track->textures[i].cpp = 16; 972 break; 973 default: 974 DRM_ERROR("Invalid texture format %u\n", 975 (idx_value & 0x1F)); 976 return -EINVAL; 977 break; 978 } 979 break; 980 case 0x4400: 981 case 0x4404: 982 case 0x4408: 983 case 0x440C: 984 case 0x4410: 985 case 0x4414: 986 case 0x4418: 987 case 0x441C: 988 case 0x4420: 989 case 0x4424: 990 case 0x4428: 991 case 0x442C: 992 case 0x4430: 993 case 0x4434: 994 case 0x4438: 995 case 0x443C: 996 /* TX_FILTER0_[0-15] */ 997 i = (reg - 0x4400) >> 2; 998 tmp = idx_value & 0x7; 999 if (tmp == 2 || tmp == 4 || tmp == 6) { 1000 track->textures[i].roundup_w = false; 1001 } 1002 tmp = (idx_value >> 3) & 0x7; 1003 if (tmp == 2 || tmp == 4 || tmp == 6) { 1004 track->textures[i].roundup_h = false; 1005 } 1006 break; 1007 case 0x4500: 1008 case 0x4504: 1009 case 0x4508: 1010 case 0x450C: 1011 case 0x4510: 1012 case 0x4514: 1013 case 0x4518: 1014 case 0x451C: 1015 case 0x4520: 1016 case 0x4524: 1017 case 0x4528: 1018 case 0x452C: 1019 case 0x4530: 1020 case 0x4534: 1021 case 0x4538: 1022 case 0x453C: 1023 /* TX_FORMAT2_[0-15] */ 1024 i = (reg - 0x4500) >> 2; 1025 tmp = idx_value & 0x3FFF; 1026 track->textures[i].pitch = tmp + 1; 1027 if (p->rdev->family >= CHIP_RV515) { 1028 tmp = ((idx_value >> 15) & 1) << 11; 1029 track->textures[i].width_11 = tmp; 1030 tmp = ((idx_value >> 16) & 1) << 11; 1031 track->textures[i].height_11 = tmp; 1032 } 1033 break; 1034 case 0x4480: 1035 case 0x4484: 1036 case 0x4488: 1037 case 0x448C: 1038 case 0x4490: 1039 case 0x4494: 1040 case 0x4498: 1041 case 0x449C: 1042 case 0x44A0: 1043 case 0x44A4: 1044 case 0x44A8: 1045 case 0x44AC: 1046 case 0x44B0: 1047 case 0x44B4: 1048 case 0x44B8: 1049 case 0x44BC: 1050 /* TX_FORMAT0_[0-15] */ 1051 i = (reg - 0x4480) >> 2; 1052 tmp = idx_value & 0x7FF; 1053 track->textures[i].width = tmp + 1; 1054 tmp = (idx_value >> 11) & 0x7FF; 1055 track->textures[i].height = tmp + 1; 1056 tmp = (idx_value >> 26) & 0xF; 1057 track->textures[i].num_levels = tmp; 1058 tmp = idx_value & (1 << 31); 1059 track->textures[i].use_pitch = !!tmp; 1060 tmp = (idx_value >> 22) & 0xF; 1061 track->textures[i].txdepth = tmp; 1062 break; 1063 case R300_ZB_ZPASS_ADDR: 1064 r = r100_cs_packet_next_reloc(p, &reloc); 1065 if (r) { 1066 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1067 idx, reg); 1068 r100_cs_dump_packet(p, pkt); 1069 return r; 1070 } 1071 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1072 break; 1073 case 0x4be8: 1074 /* valid register only on RV530 */ 1075 if (p->rdev->family == CHIP_RV530) 1076 break; 1077 /* fallthrough do not move */ 1078 default: 1079 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n", 1080 reg, idx); 1081 return -EINVAL; 1082 } 1083 return 0; 1084 } 1085 1086 static int r300_packet3_check(struct radeon_cs_parser *p, 1087 struct radeon_cs_packet *pkt) 1088 { 1089 struct radeon_cs_reloc *reloc; 1090 struct r100_cs_track *track; 1091 volatile uint32_t *ib; 1092 unsigned idx; 1093 int r; 1094 1095 ib = p->ib->ptr; 1096 idx = pkt->idx + 1; 1097 track = (struct r100_cs_track *)p->track; 1098 switch(pkt->opcode) { 1099 case PACKET3_3D_LOAD_VBPNTR: 1100 r = r100_packet3_load_vbpntr(p, pkt, idx); 1101 if (r) 1102 return r; 1103 break; 1104 case PACKET3_INDX_BUFFER: 1105 r = r100_cs_packet_next_reloc(p, &reloc); 1106 if (r) { 1107 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); 1108 r100_cs_dump_packet(p, pkt); 1109 return r; 1110 } 1111 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset); 1112 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); 1113 if (r) { 1114 return r; 1115 } 1116 break; 1117 /* Draw packet */ 1118 case PACKET3_3D_DRAW_IMMD: 1119 /* Number of dwords is vtx_size * (num_vertices - 1) 1120 * PRIM_WALK must be equal to 3 vertex data in embedded 1121 * in cmd stream */ 1122 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) { 1123 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1124 return -EINVAL; 1125 } 1126 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1127 track->immd_dwords = pkt->count - 1; 1128 r = r100_cs_track_check(p->rdev, track); 1129 if (r) { 1130 return r; 1131 } 1132 break; 1133 case PACKET3_3D_DRAW_IMMD_2: 1134 /* Number of dwords is vtx_size * (num_vertices - 1) 1135 * PRIM_WALK must be equal to 3 vertex data in embedded 1136 * in cmd stream */ 1137 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) { 1138 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1139 return -EINVAL; 1140 } 1141 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1142 track->immd_dwords = pkt->count; 1143 r = r100_cs_track_check(p->rdev, track); 1144 if (r) { 1145 return r; 1146 } 1147 break; 1148 case PACKET3_3D_DRAW_VBUF: 1149 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1150 r = r100_cs_track_check(p->rdev, track); 1151 if (r) { 1152 return r; 1153 } 1154 break; 1155 case PACKET3_3D_DRAW_VBUF_2: 1156 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1157 r = r100_cs_track_check(p->rdev, track); 1158 if (r) { 1159 return r; 1160 } 1161 break; 1162 case PACKET3_3D_DRAW_INDX: 1163 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1164 r = r100_cs_track_check(p->rdev, track); 1165 if (r) { 1166 return r; 1167 } 1168 break; 1169 case PACKET3_3D_DRAW_INDX_2: 1170 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1171 r = r100_cs_track_check(p->rdev, track); 1172 if (r) { 1173 return r; 1174 } 1175 break; 1176 case PACKET3_NOP: 1177 break; 1178 default: 1179 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); 1180 return -EINVAL; 1181 } 1182 return 0; 1183 } 1184 1185 int r300_cs_parse(struct radeon_cs_parser *p) 1186 { 1187 struct radeon_cs_packet pkt; 1188 struct r100_cs_track *track; 1189 int r; 1190 1191 track = kzalloc(sizeof(*track), GFP_KERNEL); 1192 r100_cs_track_clear(p->rdev, track); 1193 p->track = track; 1194 do { 1195 r = r100_cs_packet_parse(p, &pkt, p->idx); 1196 if (r) { 1197 return r; 1198 } 1199 p->idx += pkt.count + 2; 1200 switch (pkt.type) { 1201 case PACKET_TYPE0: 1202 r = r100_cs_parse_packet0(p, &pkt, 1203 p->rdev->config.r300.reg_safe_bm, 1204 p->rdev->config.r300.reg_safe_bm_size, 1205 &r300_packet0_check); 1206 break; 1207 case PACKET_TYPE2: 1208 break; 1209 case PACKET_TYPE3: 1210 r = r300_packet3_check(p, &pkt); 1211 break; 1212 default: 1213 DRM_ERROR("Unknown packet type %d !\n", pkt.type); 1214 return -EINVAL; 1215 } 1216 if (r) { 1217 return r; 1218 } 1219 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw); 1220 return 0; 1221 } 1222 1223 void r300_set_reg_safe(struct radeon_device *rdev) 1224 { 1225 rdev->config.r300.reg_safe_bm = r300_reg_safe_bm; 1226 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm); 1227 } 1228 1229 int r300_init(struct radeon_device *rdev) 1230 { 1231 r300_set_reg_safe(rdev); 1232 return 0; 1233 } 1234 1235 void r300_mc_program(struct radeon_device *rdev) 1236 { 1237 struct r100_mc_save save; 1238 int r; 1239 1240 r = r100_debugfs_mc_info_init(rdev); 1241 if (r) { 1242 dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n"); 1243 } 1244 1245 /* Stops all mc clients */ 1246 r100_mc_stop(rdev, &save); 1247 if (rdev->flags & RADEON_IS_AGP) { 1248 WREG32(R_00014C_MC_AGP_LOCATION, 1249 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) | 1250 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); 1251 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); 1252 WREG32(R_00015C_AGP_BASE_2, 1253 upper_32_bits(rdev->mc.agp_base) & 0xff); 1254 } else { 1255 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF); 1256 WREG32(R_000170_AGP_BASE, 0); 1257 WREG32(R_00015C_AGP_BASE_2, 0); 1258 } 1259 /* Wait for mc idle */ 1260 if (r300_mc_wait_for_idle(rdev)) 1261 DRM_INFO("Failed to wait MC idle before programming MC.\n"); 1262 /* Program MC, should be a 32bits limited address space */ 1263 WREG32(R_000148_MC_FB_LOCATION, 1264 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | 1265 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); 1266 r100_mc_resume(rdev, &save); 1267 } 1268