1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/seq_file.h> 29 #include <linux/slab.h> 30 #include "drmP.h" 31 #include "drm.h" 32 #include "radeon_drm.h" 33 #include "radeon_reg.h" 34 #include "radeon.h" 35 #include "radeon_asic.h" 36 #include "r100d.h" 37 #include "rs100d.h" 38 #include "rv200d.h" 39 #include "rv250d.h" 40 #include "atom.h" 41 42 #include <linux/firmware.h> 43 #include <linux/platform_device.h> 44 #include <linux/module.h> 45 46 #include "r100_reg_safe.h" 47 #include "rn50_reg_safe.h" 48 49 /* Firmware Names */ 50 #define FIRMWARE_R100 "radeon/R100_cp.bin" 51 #define FIRMWARE_R200 "radeon/R200_cp.bin" 52 #define FIRMWARE_R300 "radeon/R300_cp.bin" 53 #define FIRMWARE_R420 "radeon/R420_cp.bin" 54 #define FIRMWARE_RS690 "radeon/RS690_cp.bin" 55 #define FIRMWARE_RS600 "radeon/RS600_cp.bin" 56 #define FIRMWARE_R520 "radeon/R520_cp.bin" 57 58 MODULE_FIRMWARE(FIRMWARE_R100); 59 MODULE_FIRMWARE(FIRMWARE_R200); 60 MODULE_FIRMWARE(FIRMWARE_R300); 61 MODULE_FIRMWARE(FIRMWARE_R420); 62 MODULE_FIRMWARE(FIRMWARE_RS690); 63 MODULE_FIRMWARE(FIRMWARE_RS600); 64 MODULE_FIRMWARE(FIRMWARE_R520); 65 66 #include "r100_track.h" 67 68 /* This files gather functions specifics to: 69 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 70 */ 71 72 int r100_reloc_pitch_offset(struct radeon_cs_parser *p, 73 struct radeon_cs_packet *pkt, 74 unsigned idx, 75 unsigned reg) 76 { 77 int r; 78 u32 tile_flags = 0; 79 u32 tmp; 80 struct radeon_cs_reloc *reloc; 81 u32 value; 82 83 r = r100_cs_packet_next_reloc(p, &reloc); 84 if (r) { 85 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 86 idx, reg); 87 r100_cs_dump_packet(p, pkt); 88 return r; 89 } 90 value = radeon_get_ib_value(p, idx); 91 tmp = value & 0x003fffff; 92 tmp += (((u32)reloc->lobj.gpu_offset) >> 10); 93 94 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 95 tile_flags |= RADEON_DST_TILE_MACRO; 96 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) { 97 if (reg == RADEON_SRC_PITCH_OFFSET) { 98 DRM_ERROR("Cannot src blit from microtiled surface\n"); 99 r100_cs_dump_packet(p, pkt); 100 return -EINVAL; 101 } 102 tile_flags |= RADEON_DST_TILE_MICRO; 103 } 104 105 tmp |= tile_flags; 106 p->ib->ptr[idx] = (value & 0x3fc00000) | tmp; 107 return 0; 108 } 109 110 int r100_packet3_load_vbpntr(struct radeon_cs_parser *p, 111 struct radeon_cs_packet *pkt, 112 int idx) 113 { 114 unsigned c, i; 115 struct radeon_cs_reloc *reloc; 116 struct r100_cs_track *track; 117 int r = 0; 118 volatile uint32_t *ib; 119 u32 idx_value; 120 121 ib = p->ib->ptr; 122 track = (struct r100_cs_track *)p->track; 123 c = radeon_get_ib_value(p, idx++) & 0x1F; 124 if (c > 16) { 125 DRM_ERROR("Only 16 vertex buffers are allowed %d\n", 126 pkt->opcode); 127 r100_cs_dump_packet(p, pkt); 128 return -EINVAL; 129 } 130 track->num_arrays = c; 131 for (i = 0; i < (c - 1); i+=2, idx+=3) { 132 r = r100_cs_packet_next_reloc(p, &reloc); 133 if (r) { 134 DRM_ERROR("No reloc for packet3 %d\n", 135 pkt->opcode); 136 r100_cs_dump_packet(p, pkt); 137 return r; 138 } 139 idx_value = radeon_get_ib_value(p, idx); 140 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset); 141 142 track->arrays[i + 0].esize = idx_value >> 8; 143 track->arrays[i + 0].robj = reloc->robj; 144 track->arrays[i + 0].esize &= 0x7F; 145 r = r100_cs_packet_next_reloc(p, &reloc); 146 if (r) { 147 DRM_ERROR("No reloc for packet3 %d\n", 148 pkt->opcode); 149 r100_cs_dump_packet(p, pkt); 150 return r; 151 } 152 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset); 153 track->arrays[i + 1].robj = reloc->robj; 154 track->arrays[i + 1].esize = idx_value >> 24; 155 track->arrays[i + 1].esize &= 0x7F; 156 } 157 if (c & 1) { 158 r = r100_cs_packet_next_reloc(p, &reloc); 159 if (r) { 160 DRM_ERROR("No reloc for packet3 %d\n", 161 pkt->opcode); 162 r100_cs_dump_packet(p, pkt); 163 return r; 164 } 165 idx_value = radeon_get_ib_value(p, idx); 166 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset); 167 track->arrays[i + 0].robj = reloc->robj; 168 track->arrays[i + 0].esize = idx_value >> 8; 169 track->arrays[i + 0].esize &= 0x7F; 170 } 171 return r; 172 } 173 174 void r100_pre_page_flip(struct radeon_device *rdev, int crtc) 175 { 176 /* enable the pflip int */ 177 radeon_irq_kms_pflip_irq_get(rdev, crtc); 178 } 179 180 void r100_post_page_flip(struct radeon_device *rdev, int crtc) 181 { 182 /* disable the pflip int */ 183 radeon_irq_kms_pflip_irq_put(rdev, crtc); 184 } 185 186 u32 r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) 187 { 188 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 189 u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK; 190 191 /* Lock the graphics update lock */ 192 /* update the scanout addresses */ 193 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); 194 195 /* Wait for update_pending to go high. */ 196 while (!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET)); 197 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); 198 199 /* Unlock the lock, so double-buffering can take place inside vblank */ 200 tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK; 201 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); 202 203 /* Return current update_pending status: */ 204 return RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET; 205 } 206 207 void r100_pm_get_dynpm_state(struct radeon_device *rdev) 208 { 209 int i; 210 rdev->pm.dynpm_can_upclock = true; 211 rdev->pm.dynpm_can_downclock = true; 212 213 switch (rdev->pm.dynpm_planned_action) { 214 case DYNPM_ACTION_MINIMUM: 215 rdev->pm.requested_power_state_index = 0; 216 rdev->pm.dynpm_can_downclock = false; 217 break; 218 case DYNPM_ACTION_DOWNCLOCK: 219 if (rdev->pm.current_power_state_index == 0) { 220 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 221 rdev->pm.dynpm_can_downclock = false; 222 } else { 223 if (rdev->pm.active_crtc_count > 1) { 224 for (i = 0; i < rdev->pm.num_power_states; i++) { 225 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 226 continue; 227 else if (i >= rdev->pm.current_power_state_index) { 228 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 229 break; 230 } else { 231 rdev->pm.requested_power_state_index = i; 232 break; 233 } 234 } 235 } else 236 rdev->pm.requested_power_state_index = 237 rdev->pm.current_power_state_index - 1; 238 } 239 /* don't use the power state if crtcs are active and no display flag is set */ 240 if ((rdev->pm.active_crtc_count > 0) && 241 (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags & 242 RADEON_PM_MODE_NO_DISPLAY)) { 243 rdev->pm.requested_power_state_index++; 244 } 245 break; 246 case DYNPM_ACTION_UPCLOCK: 247 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) { 248 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 249 rdev->pm.dynpm_can_upclock = false; 250 } else { 251 if (rdev->pm.active_crtc_count > 1) { 252 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) { 253 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 254 continue; 255 else if (i <= rdev->pm.current_power_state_index) { 256 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 257 break; 258 } else { 259 rdev->pm.requested_power_state_index = i; 260 break; 261 } 262 } 263 } else 264 rdev->pm.requested_power_state_index = 265 rdev->pm.current_power_state_index + 1; 266 } 267 break; 268 case DYNPM_ACTION_DEFAULT: 269 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; 270 rdev->pm.dynpm_can_upclock = false; 271 break; 272 case DYNPM_ACTION_NONE: 273 default: 274 DRM_ERROR("Requested mode for not defined action\n"); 275 return; 276 } 277 /* only one clock mode per power state */ 278 rdev->pm.requested_clock_mode_index = 0; 279 280 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n", 281 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 282 clock_info[rdev->pm.requested_clock_mode_index].sclk, 283 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 284 clock_info[rdev->pm.requested_clock_mode_index].mclk, 285 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 286 pcie_lanes); 287 } 288 289 void r100_pm_init_profile(struct radeon_device *rdev) 290 { 291 /* default */ 292 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 293 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 294 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 295 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 296 /* low sh */ 297 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; 298 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; 299 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 300 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 301 /* mid sh */ 302 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; 303 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0; 304 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 305 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 306 /* high sh */ 307 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; 308 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 309 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 310 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 311 /* low mh */ 312 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; 313 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 314 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 315 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 316 /* mid mh */ 317 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; 318 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 319 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 320 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 321 /* high mh */ 322 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; 323 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 324 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 325 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 326 } 327 328 void r100_pm_misc(struct radeon_device *rdev) 329 { 330 int requested_index = rdev->pm.requested_power_state_index; 331 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index]; 332 struct radeon_voltage *voltage = &ps->clock_info[0].voltage; 333 u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl; 334 335 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) { 336 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) { 337 tmp = RREG32(voltage->gpio.reg); 338 if (voltage->active_high) 339 tmp |= voltage->gpio.mask; 340 else 341 tmp &= ~(voltage->gpio.mask); 342 WREG32(voltage->gpio.reg, tmp); 343 if (voltage->delay) 344 udelay(voltage->delay); 345 } else { 346 tmp = RREG32(voltage->gpio.reg); 347 if (voltage->active_high) 348 tmp &= ~voltage->gpio.mask; 349 else 350 tmp |= voltage->gpio.mask; 351 WREG32(voltage->gpio.reg, tmp); 352 if (voltage->delay) 353 udelay(voltage->delay); 354 } 355 } 356 357 sclk_cntl = RREG32_PLL(SCLK_CNTL); 358 sclk_cntl2 = RREG32_PLL(SCLK_CNTL2); 359 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3); 360 sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL); 361 sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3); 362 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) { 363 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN; 364 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE) 365 sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE; 366 else 367 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE; 368 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) 369 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0); 370 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) 371 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2); 372 } else 373 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN; 374 375 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) { 376 sclk_more_cntl |= IO_CG_VOLTAGE_DROP; 377 if (voltage->delay) { 378 sclk_more_cntl |= VOLTAGE_DROP_SYNC; 379 switch (voltage->delay) { 380 case 33: 381 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0); 382 break; 383 case 66: 384 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1); 385 break; 386 case 99: 387 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2); 388 break; 389 case 132: 390 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3); 391 break; 392 } 393 } else 394 sclk_more_cntl &= ~VOLTAGE_DROP_SYNC; 395 } else 396 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP; 397 398 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN) 399 sclk_cntl &= ~FORCE_HDP; 400 else 401 sclk_cntl |= FORCE_HDP; 402 403 WREG32_PLL(SCLK_CNTL, sclk_cntl); 404 WREG32_PLL(SCLK_CNTL2, sclk_cntl2); 405 WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl); 406 407 /* set pcie lanes */ 408 if ((rdev->flags & RADEON_IS_PCIE) && 409 !(rdev->flags & RADEON_IS_IGP) && 410 rdev->asic->set_pcie_lanes && 411 (ps->pcie_lanes != 412 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) { 413 radeon_set_pcie_lanes(rdev, 414 ps->pcie_lanes); 415 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes); 416 } 417 } 418 419 void r100_pm_prepare(struct radeon_device *rdev) 420 { 421 struct drm_device *ddev = rdev->ddev; 422 struct drm_crtc *crtc; 423 struct radeon_crtc *radeon_crtc; 424 u32 tmp; 425 426 /* disable any active CRTCs */ 427 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { 428 radeon_crtc = to_radeon_crtc(crtc); 429 if (radeon_crtc->enabled) { 430 if (radeon_crtc->crtc_id) { 431 tmp = RREG32(RADEON_CRTC2_GEN_CNTL); 432 tmp |= RADEON_CRTC2_DISP_REQ_EN_B; 433 WREG32(RADEON_CRTC2_GEN_CNTL, tmp); 434 } else { 435 tmp = RREG32(RADEON_CRTC_GEN_CNTL); 436 tmp |= RADEON_CRTC_DISP_REQ_EN_B; 437 WREG32(RADEON_CRTC_GEN_CNTL, tmp); 438 } 439 } 440 } 441 } 442 443 void r100_pm_finish(struct radeon_device *rdev) 444 { 445 struct drm_device *ddev = rdev->ddev; 446 struct drm_crtc *crtc; 447 struct radeon_crtc *radeon_crtc; 448 u32 tmp; 449 450 /* enable any active CRTCs */ 451 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { 452 radeon_crtc = to_radeon_crtc(crtc); 453 if (radeon_crtc->enabled) { 454 if (radeon_crtc->crtc_id) { 455 tmp = RREG32(RADEON_CRTC2_GEN_CNTL); 456 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B; 457 WREG32(RADEON_CRTC2_GEN_CNTL, tmp); 458 } else { 459 tmp = RREG32(RADEON_CRTC_GEN_CNTL); 460 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B; 461 WREG32(RADEON_CRTC_GEN_CNTL, tmp); 462 } 463 } 464 } 465 } 466 467 bool r100_gui_idle(struct radeon_device *rdev) 468 { 469 if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE) 470 return false; 471 else 472 return true; 473 } 474 475 /* hpd for digital panel detect/disconnect */ 476 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) 477 { 478 bool connected = false; 479 480 switch (hpd) { 481 case RADEON_HPD_1: 482 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE) 483 connected = true; 484 break; 485 case RADEON_HPD_2: 486 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE) 487 connected = true; 488 break; 489 default: 490 break; 491 } 492 return connected; 493 } 494 495 void r100_hpd_set_polarity(struct radeon_device *rdev, 496 enum radeon_hpd_id hpd) 497 { 498 u32 tmp; 499 bool connected = r100_hpd_sense(rdev, hpd); 500 501 switch (hpd) { 502 case RADEON_HPD_1: 503 tmp = RREG32(RADEON_FP_GEN_CNTL); 504 if (connected) 505 tmp &= ~RADEON_FP_DETECT_INT_POL; 506 else 507 tmp |= RADEON_FP_DETECT_INT_POL; 508 WREG32(RADEON_FP_GEN_CNTL, tmp); 509 break; 510 case RADEON_HPD_2: 511 tmp = RREG32(RADEON_FP2_GEN_CNTL); 512 if (connected) 513 tmp &= ~RADEON_FP2_DETECT_INT_POL; 514 else 515 tmp |= RADEON_FP2_DETECT_INT_POL; 516 WREG32(RADEON_FP2_GEN_CNTL, tmp); 517 break; 518 default: 519 break; 520 } 521 } 522 523 void r100_hpd_init(struct radeon_device *rdev) 524 { 525 struct drm_device *dev = rdev->ddev; 526 struct drm_connector *connector; 527 528 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 529 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 530 switch (radeon_connector->hpd.hpd) { 531 case RADEON_HPD_1: 532 rdev->irq.hpd[0] = true; 533 break; 534 case RADEON_HPD_2: 535 rdev->irq.hpd[1] = true; 536 break; 537 default: 538 break; 539 } 540 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); 541 } 542 if (rdev->irq.installed) 543 r100_irq_set(rdev); 544 } 545 546 void r100_hpd_fini(struct radeon_device *rdev) 547 { 548 struct drm_device *dev = rdev->ddev; 549 struct drm_connector *connector; 550 551 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 552 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 553 switch (radeon_connector->hpd.hpd) { 554 case RADEON_HPD_1: 555 rdev->irq.hpd[0] = false; 556 break; 557 case RADEON_HPD_2: 558 rdev->irq.hpd[1] = false; 559 break; 560 default: 561 break; 562 } 563 } 564 } 565 566 /* 567 * PCI GART 568 */ 569 void r100_pci_gart_tlb_flush(struct radeon_device *rdev) 570 { 571 /* TODO: can we do somethings here ? */ 572 /* It seems hw only cache one entry so we should discard this 573 * entry otherwise if first GPU GART read hit this entry it 574 * could end up in wrong address. */ 575 } 576 577 int r100_pci_gart_init(struct radeon_device *rdev) 578 { 579 int r; 580 581 if (rdev->gart.ptr) { 582 WARN(1, "R100 PCI GART already initialized\n"); 583 return 0; 584 } 585 /* Initialize common gart structure */ 586 r = radeon_gart_init(rdev); 587 if (r) 588 return r; 589 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; 590 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush; 591 rdev->asic->gart_set_page = &r100_pci_gart_set_page; 592 return radeon_gart_table_ram_alloc(rdev); 593 } 594 595 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */ 596 void r100_enable_bm(struct radeon_device *rdev) 597 { 598 uint32_t tmp; 599 /* Enable bus mastering */ 600 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; 601 WREG32(RADEON_BUS_CNTL, tmp); 602 } 603 604 int r100_pci_gart_enable(struct radeon_device *rdev) 605 { 606 uint32_t tmp; 607 608 radeon_gart_restore(rdev); 609 /* discard memory request outside of configured range */ 610 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; 611 WREG32(RADEON_AIC_CNTL, tmp); 612 /* set address range for PCI address translate */ 613 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start); 614 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end); 615 /* set PCI GART page-table base address */ 616 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr); 617 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN; 618 WREG32(RADEON_AIC_CNTL, tmp); 619 r100_pci_gart_tlb_flush(rdev); 620 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 621 (unsigned)(rdev->mc.gtt_size >> 20), 622 (unsigned long long)rdev->gart.table_addr); 623 rdev->gart.ready = true; 624 return 0; 625 } 626 627 void r100_pci_gart_disable(struct radeon_device *rdev) 628 { 629 uint32_t tmp; 630 631 /* discard memory request outside of configured range */ 632 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; 633 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN); 634 WREG32(RADEON_AIC_LO_ADDR, 0); 635 WREG32(RADEON_AIC_HI_ADDR, 0); 636 } 637 638 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) 639 { 640 u32 *gtt = rdev->gart.ptr; 641 642 if (i < 0 || i > rdev->gart.num_gpu_pages) { 643 return -EINVAL; 644 } 645 gtt[i] = cpu_to_le32(lower_32_bits(addr)); 646 return 0; 647 } 648 649 void r100_pci_gart_fini(struct radeon_device *rdev) 650 { 651 radeon_gart_fini(rdev); 652 r100_pci_gart_disable(rdev); 653 radeon_gart_table_ram_free(rdev); 654 } 655 656 int r100_irq_set(struct radeon_device *rdev) 657 { 658 uint32_t tmp = 0; 659 660 if (!rdev->irq.installed) { 661 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); 662 WREG32(R_000040_GEN_INT_CNTL, 0); 663 return -EINVAL; 664 } 665 if (rdev->irq.sw_int) { 666 tmp |= RADEON_SW_INT_ENABLE; 667 } 668 if (rdev->irq.gui_idle) { 669 tmp |= RADEON_GUI_IDLE_MASK; 670 } 671 if (rdev->irq.crtc_vblank_int[0] || 672 rdev->irq.pflip[0]) { 673 tmp |= RADEON_CRTC_VBLANK_MASK; 674 } 675 if (rdev->irq.crtc_vblank_int[1] || 676 rdev->irq.pflip[1]) { 677 tmp |= RADEON_CRTC2_VBLANK_MASK; 678 } 679 if (rdev->irq.hpd[0]) { 680 tmp |= RADEON_FP_DETECT_MASK; 681 } 682 if (rdev->irq.hpd[1]) { 683 tmp |= RADEON_FP2_DETECT_MASK; 684 } 685 WREG32(RADEON_GEN_INT_CNTL, tmp); 686 return 0; 687 } 688 689 void r100_irq_disable(struct radeon_device *rdev) 690 { 691 u32 tmp; 692 693 WREG32(R_000040_GEN_INT_CNTL, 0); 694 /* Wait and acknowledge irq */ 695 mdelay(1); 696 tmp = RREG32(R_000044_GEN_INT_STATUS); 697 WREG32(R_000044_GEN_INT_STATUS, tmp); 698 } 699 700 static uint32_t r100_irq_ack(struct radeon_device *rdev) 701 { 702 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS); 703 uint32_t irq_mask = RADEON_SW_INT_TEST | 704 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT | 705 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT; 706 707 /* the interrupt works, but the status bit is permanently asserted */ 708 if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) { 709 if (!rdev->irq.gui_idle_acked) 710 irq_mask |= RADEON_GUI_IDLE_STAT; 711 } 712 713 if (irqs) { 714 WREG32(RADEON_GEN_INT_STATUS, irqs); 715 } 716 return irqs & irq_mask; 717 } 718 719 int r100_irq_process(struct radeon_device *rdev) 720 { 721 uint32_t status, msi_rearm; 722 bool queue_hotplug = false; 723 724 /* reset gui idle ack. the status bit is broken */ 725 rdev->irq.gui_idle_acked = false; 726 727 status = r100_irq_ack(rdev); 728 if (!status) { 729 return IRQ_NONE; 730 } 731 if (rdev->shutdown) { 732 return IRQ_NONE; 733 } 734 while (status) { 735 /* SW interrupt */ 736 if (status & RADEON_SW_INT_TEST) { 737 radeon_fence_process(rdev); 738 } 739 /* gui idle interrupt */ 740 if (status & RADEON_GUI_IDLE_STAT) { 741 rdev->irq.gui_idle_acked = true; 742 rdev->pm.gui_idle = true; 743 wake_up(&rdev->irq.idle_queue); 744 } 745 /* Vertical blank interrupts */ 746 if (status & RADEON_CRTC_VBLANK_STAT) { 747 if (rdev->irq.crtc_vblank_int[0]) { 748 drm_handle_vblank(rdev->ddev, 0); 749 rdev->pm.vblank_sync = true; 750 wake_up(&rdev->irq.vblank_queue); 751 } 752 if (rdev->irq.pflip[0]) 753 radeon_crtc_handle_flip(rdev, 0); 754 } 755 if (status & RADEON_CRTC2_VBLANK_STAT) { 756 if (rdev->irq.crtc_vblank_int[1]) { 757 drm_handle_vblank(rdev->ddev, 1); 758 rdev->pm.vblank_sync = true; 759 wake_up(&rdev->irq.vblank_queue); 760 } 761 if (rdev->irq.pflip[1]) 762 radeon_crtc_handle_flip(rdev, 1); 763 } 764 if (status & RADEON_FP_DETECT_STAT) { 765 queue_hotplug = true; 766 DRM_DEBUG("HPD1\n"); 767 } 768 if (status & RADEON_FP2_DETECT_STAT) { 769 queue_hotplug = true; 770 DRM_DEBUG("HPD2\n"); 771 } 772 status = r100_irq_ack(rdev); 773 } 774 /* reset gui idle ack. the status bit is broken */ 775 rdev->irq.gui_idle_acked = false; 776 if (queue_hotplug) 777 schedule_work(&rdev->hotplug_work); 778 if (rdev->msi_enabled) { 779 switch (rdev->family) { 780 case CHIP_RS400: 781 case CHIP_RS480: 782 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM; 783 WREG32(RADEON_AIC_CNTL, msi_rearm); 784 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM); 785 break; 786 default: 787 msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN; 788 WREG32(RADEON_MSI_REARM_EN, msi_rearm); 789 WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN); 790 break; 791 } 792 } 793 return IRQ_HANDLED; 794 } 795 796 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc) 797 { 798 if (crtc == 0) 799 return RREG32(RADEON_CRTC_CRNT_FRAME); 800 else 801 return RREG32(RADEON_CRTC2_CRNT_FRAME); 802 } 803 804 /* Who ever call radeon_fence_emit should call ring_lock and ask 805 * for enough space (today caller are ib schedule and buffer move) */ 806 void r100_fence_ring_emit(struct radeon_device *rdev, 807 struct radeon_fence *fence) 808 { 809 /* We have to make sure that caches are flushed before 810 * CPU might read something from VRAM. */ 811 radeon_ring_write(rdev, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); 812 radeon_ring_write(rdev, RADEON_RB3D_DC_FLUSH_ALL); 813 radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); 814 radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL); 815 /* Wait until IDLE & CLEAN */ 816 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); 817 radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); 818 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0)); 819 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl | 820 RADEON_HDP_READ_BUFFER_INVALIDATE); 821 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0)); 822 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl); 823 /* Emit fence sequence & fire IRQ */ 824 radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0)); 825 radeon_ring_write(rdev, fence->seq); 826 radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0)); 827 radeon_ring_write(rdev, RADEON_SW_INT_FIRE); 828 } 829 830 int r100_copy_blit(struct radeon_device *rdev, 831 uint64_t src_offset, 832 uint64_t dst_offset, 833 unsigned num_gpu_pages, 834 struct radeon_fence *fence) 835 { 836 uint32_t cur_pages; 837 uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE; 838 uint32_t pitch; 839 uint32_t stride_pixels; 840 unsigned ndw; 841 int num_loops; 842 int r = 0; 843 844 /* radeon limited to 16k stride */ 845 stride_bytes &= 0x3fff; 846 /* radeon pitch is /64 */ 847 pitch = stride_bytes / 64; 848 stride_pixels = stride_bytes / 4; 849 num_loops = DIV_ROUND_UP(num_gpu_pages, 8191); 850 851 /* Ask for enough room for blit + flush + fence */ 852 ndw = 64 + (10 * num_loops); 853 r = radeon_ring_lock(rdev, ndw); 854 if (r) { 855 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw); 856 return -EINVAL; 857 } 858 while (num_gpu_pages > 0) { 859 cur_pages = num_gpu_pages; 860 if (cur_pages > 8191) { 861 cur_pages = 8191; 862 } 863 num_gpu_pages -= cur_pages; 864 865 /* pages are in Y direction - height 866 page width in X direction - width */ 867 radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8)); 868 radeon_ring_write(rdev, 869 RADEON_GMC_SRC_PITCH_OFFSET_CNTL | 870 RADEON_GMC_DST_PITCH_OFFSET_CNTL | 871 RADEON_GMC_SRC_CLIPPING | 872 RADEON_GMC_DST_CLIPPING | 873 RADEON_GMC_BRUSH_NONE | 874 (RADEON_COLOR_FORMAT_ARGB8888 << 8) | 875 RADEON_GMC_SRC_DATATYPE_COLOR | 876 RADEON_ROP3_S | 877 RADEON_DP_SRC_SOURCE_MEMORY | 878 RADEON_GMC_CLR_CMP_CNTL_DIS | 879 RADEON_GMC_WR_MSK_DIS); 880 radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10)); 881 radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10)); 882 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16)); 883 radeon_ring_write(rdev, 0); 884 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16)); 885 radeon_ring_write(rdev, num_gpu_pages); 886 radeon_ring_write(rdev, num_gpu_pages); 887 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16)); 888 } 889 radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0)); 890 radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL); 891 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); 892 radeon_ring_write(rdev, 893 RADEON_WAIT_2D_IDLECLEAN | 894 RADEON_WAIT_HOST_IDLECLEAN | 895 RADEON_WAIT_DMA_GUI_IDLE); 896 if (fence) { 897 r = radeon_fence_emit(rdev, fence); 898 } 899 radeon_ring_unlock_commit(rdev); 900 return r; 901 } 902 903 static int r100_cp_wait_for_idle(struct radeon_device *rdev) 904 { 905 unsigned i; 906 u32 tmp; 907 908 for (i = 0; i < rdev->usec_timeout; i++) { 909 tmp = RREG32(R_000E40_RBBM_STATUS); 910 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) { 911 return 0; 912 } 913 udelay(1); 914 } 915 return -1; 916 } 917 918 void r100_ring_start(struct radeon_device *rdev) 919 { 920 int r; 921 922 r = radeon_ring_lock(rdev, 2); 923 if (r) { 924 return; 925 } 926 radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0)); 927 radeon_ring_write(rdev, 928 RADEON_ISYNC_ANY2D_IDLE3D | 929 RADEON_ISYNC_ANY3D_IDLE2D | 930 RADEON_ISYNC_WAIT_IDLEGUI | 931 RADEON_ISYNC_CPSCRATCH_IDLEGUI); 932 radeon_ring_unlock_commit(rdev); 933 } 934 935 936 /* Load the microcode for the CP */ 937 static int r100_cp_init_microcode(struct radeon_device *rdev) 938 { 939 struct platform_device *pdev; 940 const char *fw_name = NULL; 941 int err; 942 943 DRM_DEBUG_KMS("\n"); 944 945 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0); 946 err = IS_ERR(pdev); 947 if (err) { 948 printk(KERN_ERR "radeon_cp: Failed to register firmware\n"); 949 return -EINVAL; 950 } 951 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) || 952 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) || 953 (rdev->family == CHIP_RS200)) { 954 DRM_INFO("Loading R100 Microcode\n"); 955 fw_name = FIRMWARE_R100; 956 } else if ((rdev->family == CHIP_R200) || 957 (rdev->family == CHIP_RV250) || 958 (rdev->family == CHIP_RV280) || 959 (rdev->family == CHIP_RS300)) { 960 DRM_INFO("Loading R200 Microcode\n"); 961 fw_name = FIRMWARE_R200; 962 } else if ((rdev->family == CHIP_R300) || 963 (rdev->family == CHIP_R350) || 964 (rdev->family == CHIP_RV350) || 965 (rdev->family == CHIP_RV380) || 966 (rdev->family == CHIP_RS400) || 967 (rdev->family == CHIP_RS480)) { 968 DRM_INFO("Loading R300 Microcode\n"); 969 fw_name = FIRMWARE_R300; 970 } else if ((rdev->family == CHIP_R420) || 971 (rdev->family == CHIP_R423) || 972 (rdev->family == CHIP_RV410)) { 973 DRM_INFO("Loading R400 Microcode\n"); 974 fw_name = FIRMWARE_R420; 975 } else if ((rdev->family == CHIP_RS690) || 976 (rdev->family == CHIP_RS740)) { 977 DRM_INFO("Loading RS690/RS740 Microcode\n"); 978 fw_name = FIRMWARE_RS690; 979 } else if (rdev->family == CHIP_RS600) { 980 DRM_INFO("Loading RS600 Microcode\n"); 981 fw_name = FIRMWARE_RS600; 982 } else if ((rdev->family == CHIP_RV515) || 983 (rdev->family == CHIP_R520) || 984 (rdev->family == CHIP_RV530) || 985 (rdev->family == CHIP_R580) || 986 (rdev->family == CHIP_RV560) || 987 (rdev->family == CHIP_RV570)) { 988 DRM_INFO("Loading R500 Microcode\n"); 989 fw_name = FIRMWARE_R520; 990 } 991 992 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev); 993 platform_device_unregister(pdev); 994 if (err) { 995 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n", 996 fw_name); 997 } else if (rdev->me_fw->size % 8) { 998 printk(KERN_ERR 999 "radeon_cp: Bogus length %zu in firmware \"%s\"\n", 1000 rdev->me_fw->size, fw_name); 1001 err = -EINVAL; 1002 release_firmware(rdev->me_fw); 1003 rdev->me_fw = NULL; 1004 } 1005 return err; 1006 } 1007 1008 static void r100_cp_load_microcode(struct radeon_device *rdev) 1009 { 1010 const __be32 *fw_data; 1011 int i, size; 1012 1013 if (r100_gui_wait_for_idle(rdev)) { 1014 printk(KERN_WARNING "Failed to wait GUI idle while " 1015 "programming pipes. Bad things might happen.\n"); 1016 } 1017 1018 if (rdev->me_fw) { 1019 size = rdev->me_fw->size / 4; 1020 fw_data = (const __be32 *)&rdev->me_fw->data[0]; 1021 WREG32(RADEON_CP_ME_RAM_ADDR, 0); 1022 for (i = 0; i < size; i += 2) { 1023 WREG32(RADEON_CP_ME_RAM_DATAH, 1024 be32_to_cpup(&fw_data[i])); 1025 WREG32(RADEON_CP_ME_RAM_DATAL, 1026 be32_to_cpup(&fw_data[i + 1])); 1027 } 1028 } 1029 } 1030 1031 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size) 1032 { 1033 unsigned rb_bufsz; 1034 unsigned rb_blksz; 1035 unsigned max_fetch; 1036 unsigned pre_write_timer; 1037 unsigned pre_write_limit; 1038 unsigned indirect2_start; 1039 unsigned indirect1_start; 1040 uint32_t tmp; 1041 int r; 1042 1043 if (r100_debugfs_cp_init(rdev)) { 1044 DRM_ERROR("Failed to register debugfs file for CP !\n"); 1045 } 1046 if (!rdev->me_fw) { 1047 r = r100_cp_init_microcode(rdev); 1048 if (r) { 1049 DRM_ERROR("Failed to load firmware!\n"); 1050 return r; 1051 } 1052 } 1053 1054 /* Align ring size */ 1055 rb_bufsz = drm_order(ring_size / 8); 1056 ring_size = (1 << (rb_bufsz + 1)) * 4; 1057 r100_cp_load_microcode(rdev); 1058 r = radeon_ring_init(rdev, ring_size); 1059 if (r) { 1060 return r; 1061 } 1062 /* Each time the cp read 1024 bytes (16 dword/quadword) update 1063 * the rptr copy in system ram */ 1064 rb_blksz = 9; 1065 /* cp will read 128bytes at a time (4 dwords) */ 1066 max_fetch = 1; 1067 rdev->cp.align_mask = 16 - 1; 1068 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */ 1069 pre_write_timer = 64; 1070 /* Force CP_RB_WPTR write if written more than one time before the 1071 * delay expire 1072 */ 1073 pre_write_limit = 0; 1074 /* Setup the cp cache like this (cache size is 96 dwords) : 1075 * RING 0 to 15 1076 * INDIRECT1 16 to 79 1077 * INDIRECT2 80 to 95 1078 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords)) 1079 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords)) 1080 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords)) 1081 * Idea being that most of the gpu cmd will be through indirect1 buffer 1082 * so it gets the bigger cache. 1083 */ 1084 indirect2_start = 80; 1085 indirect1_start = 16; 1086 /* cp setup */ 1087 WREG32(0x718, pre_write_timer | (pre_write_limit << 28)); 1088 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) | 1089 REG_SET(RADEON_RB_BLKSZ, rb_blksz) | 1090 REG_SET(RADEON_MAX_FETCH, max_fetch)); 1091 #ifdef __BIG_ENDIAN 1092 tmp |= RADEON_BUF_SWAP_32BIT; 1093 #endif 1094 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE); 1095 1096 /* Set ring address */ 1097 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr); 1098 WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr); 1099 /* Force read & write ptr to 0 */ 1100 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE); 1101 WREG32(RADEON_CP_RB_RPTR_WR, 0); 1102 rdev->cp.wptr = 0; 1103 WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr); 1104 1105 /* set the wb address whether it's enabled or not */ 1106 WREG32(R_00070C_CP_RB_RPTR_ADDR, 1107 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2)); 1108 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET); 1109 1110 if (rdev->wb.enabled) 1111 WREG32(R_000770_SCRATCH_UMSK, 0xff); 1112 else { 1113 tmp |= RADEON_RB_NO_UPDATE; 1114 WREG32(R_000770_SCRATCH_UMSK, 0); 1115 } 1116 1117 WREG32(RADEON_CP_RB_CNTL, tmp); 1118 udelay(10); 1119 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR); 1120 /* Set cp mode to bus mastering & enable cp*/ 1121 WREG32(RADEON_CP_CSQ_MODE, 1122 REG_SET(RADEON_INDIRECT2_START, indirect2_start) | 1123 REG_SET(RADEON_INDIRECT1_START, indirect1_start)); 1124 WREG32(RADEON_CP_RB_WPTR_DELAY, 0); 1125 WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D); 1126 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM); 1127 radeon_ring_start(rdev); 1128 r = radeon_ring_test(rdev); 1129 if (r) { 1130 DRM_ERROR("radeon: cp isn't working (%d).\n", r); 1131 return r; 1132 } 1133 rdev->cp.ready = true; 1134 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); 1135 return 0; 1136 } 1137 1138 void r100_cp_fini(struct radeon_device *rdev) 1139 { 1140 if (r100_cp_wait_for_idle(rdev)) { 1141 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n"); 1142 } 1143 /* Disable ring */ 1144 r100_cp_disable(rdev); 1145 radeon_ring_fini(rdev); 1146 DRM_INFO("radeon: cp finalized\n"); 1147 } 1148 1149 void r100_cp_disable(struct radeon_device *rdev) 1150 { 1151 /* Disable ring */ 1152 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 1153 rdev->cp.ready = false; 1154 WREG32(RADEON_CP_CSQ_MODE, 0); 1155 WREG32(RADEON_CP_CSQ_CNTL, 0); 1156 WREG32(R_000770_SCRATCH_UMSK, 0); 1157 if (r100_gui_wait_for_idle(rdev)) { 1158 printk(KERN_WARNING "Failed to wait GUI idle while " 1159 "programming pipes. Bad things might happen.\n"); 1160 } 1161 } 1162 1163 void r100_cp_commit(struct radeon_device *rdev) 1164 { 1165 WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr); 1166 (void)RREG32(RADEON_CP_RB_WPTR); 1167 } 1168 1169 1170 /* 1171 * CS functions 1172 */ 1173 int r100_cs_parse_packet0(struct radeon_cs_parser *p, 1174 struct radeon_cs_packet *pkt, 1175 const unsigned *auth, unsigned n, 1176 radeon_packet0_check_t check) 1177 { 1178 unsigned reg; 1179 unsigned i, j, m; 1180 unsigned idx; 1181 int r; 1182 1183 idx = pkt->idx + 1; 1184 reg = pkt->reg; 1185 /* Check that register fall into register range 1186 * determined by the number of entry (n) in the 1187 * safe register bitmap. 1188 */ 1189 if (pkt->one_reg_wr) { 1190 if ((reg >> 7) > n) { 1191 return -EINVAL; 1192 } 1193 } else { 1194 if (((reg + (pkt->count << 2)) >> 7) > n) { 1195 return -EINVAL; 1196 } 1197 } 1198 for (i = 0; i <= pkt->count; i++, idx++) { 1199 j = (reg >> 7); 1200 m = 1 << ((reg >> 2) & 31); 1201 if (auth[j] & m) { 1202 r = check(p, pkt, idx, reg); 1203 if (r) { 1204 return r; 1205 } 1206 } 1207 if (pkt->one_reg_wr) { 1208 if (!(auth[j] & m)) { 1209 break; 1210 } 1211 } else { 1212 reg += 4; 1213 } 1214 } 1215 return 0; 1216 } 1217 1218 void r100_cs_dump_packet(struct radeon_cs_parser *p, 1219 struct radeon_cs_packet *pkt) 1220 { 1221 volatile uint32_t *ib; 1222 unsigned i; 1223 unsigned idx; 1224 1225 ib = p->ib->ptr; 1226 idx = pkt->idx; 1227 for (i = 0; i <= (pkt->count + 1); i++, idx++) { 1228 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]); 1229 } 1230 } 1231 1232 /** 1233 * r100_cs_packet_parse() - parse cp packet and point ib index to next packet 1234 * @parser: parser structure holding parsing context. 1235 * @pkt: where to store packet informations 1236 * 1237 * Assume that chunk_ib_index is properly set. Will return -EINVAL 1238 * if packet is bigger than remaining ib size. or if packets is unknown. 1239 **/ 1240 int r100_cs_packet_parse(struct radeon_cs_parser *p, 1241 struct radeon_cs_packet *pkt, 1242 unsigned idx) 1243 { 1244 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx]; 1245 uint32_t header; 1246 1247 if (idx >= ib_chunk->length_dw) { 1248 DRM_ERROR("Can not parse packet at %d after CS end %d !\n", 1249 idx, ib_chunk->length_dw); 1250 return -EINVAL; 1251 } 1252 header = radeon_get_ib_value(p, idx); 1253 pkt->idx = idx; 1254 pkt->type = CP_PACKET_GET_TYPE(header); 1255 pkt->count = CP_PACKET_GET_COUNT(header); 1256 switch (pkt->type) { 1257 case PACKET_TYPE0: 1258 pkt->reg = CP_PACKET0_GET_REG(header); 1259 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header); 1260 break; 1261 case PACKET_TYPE3: 1262 pkt->opcode = CP_PACKET3_GET_OPCODE(header); 1263 break; 1264 case PACKET_TYPE2: 1265 pkt->count = -1; 1266 break; 1267 default: 1268 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx); 1269 return -EINVAL; 1270 } 1271 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) { 1272 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n", 1273 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw); 1274 return -EINVAL; 1275 } 1276 return 0; 1277 } 1278 1279 /** 1280 * r100_cs_packet_next_vline() - parse userspace VLINE packet 1281 * @parser: parser structure holding parsing context. 1282 * 1283 * Userspace sends a special sequence for VLINE waits. 1284 * PACKET0 - VLINE_START_END + value 1285 * PACKET0 - WAIT_UNTIL +_value 1286 * RELOC (P3) - crtc_id in reloc. 1287 * 1288 * This function parses this and relocates the VLINE START END 1289 * and WAIT UNTIL packets to the correct crtc. 1290 * It also detects a switched off crtc and nulls out the 1291 * wait in that case. 1292 */ 1293 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p) 1294 { 1295 struct drm_mode_object *obj; 1296 struct drm_crtc *crtc; 1297 struct radeon_crtc *radeon_crtc; 1298 struct radeon_cs_packet p3reloc, waitreloc; 1299 int crtc_id; 1300 int r; 1301 uint32_t header, h_idx, reg; 1302 volatile uint32_t *ib; 1303 1304 ib = p->ib->ptr; 1305 1306 /* parse the wait until */ 1307 r = r100_cs_packet_parse(p, &waitreloc, p->idx); 1308 if (r) 1309 return r; 1310 1311 /* check its a wait until and only 1 count */ 1312 if (waitreloc.reg != RADEON_WAIT_UNTIL || 1313 waitreloc.count != 0) { 1314 DRM_ERROR("vline wait had illegal wait until segment\n"); 1315 return -EINVAL; 1316 } 1317 1318 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) { 1319 DRM_ERROR("vline wait had illegal wait until\n"); 1320 return -EINVAL; 1321 } 1322 1323 /* jump over the NOP */ 1324 r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2); 1325 if (r) 1326 return r; 1327 1328 h_idx = p->idx - 2; 1329 p->idx += waitreloc.count + 2; 1330 p->idx += p3reloc.count + 2; 1331 1332 header = radeon_get_ib_value(p, h_idx); 1333 crtc_id = radeon_get_ib_value(p, h_idx + 5); 1334 reg = CP_PACKET0_GET_REG(header); 1335 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC); 1336 if (!obj) { 1337 DRM_ERROR("cannot find crtc %d\n", crtc_id); 1338 return -EINVAL; 1339 } 1340 crtc = obj_to_crtc(obj); 1341 radeon_crtc = to_radeon_crtc(crtc); 1342 crtc_id = radeon_crtc->crtc_id; 1343 1344 if (!crtc->enabled) { 1345 /* if the CRTC isn't enabled - we need to nop out the wait until */ 1346 ib[h_idx + 2] = PACKET2(0); 1347 ib[h_idx + 3] = PACKET2(0); 1348 } else if (crtc_id == 1) { 1349 switch (reg) { 1350 case AVIVO_D1MODE_VLINE_START_END: 1351 header &= ~R300_CP_PACKET0_REG_MASK; 1352 header |= AVIVO_D2MODE_VLINE_START_END >> 2; 1353 break; 1354 case RADEON_CRTC_GUI_TRIG_VLINE: 1355 header &= ~R300_CP_PACKET0_REG_MASK; 1356 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2; 1357 break; 1358 default: 1359 DRM_ERROR("unknown crtc reloc\n"); 1360 return -EINVAL; 1361 } 1362 ib[h_idx] = header; 1363 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1; 1364 } 1365 1366 return 0; 1367 } 1368 1369 /** 1370 * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3 1371 * @parser: parser structure holding parsing context. 1372 * @data: pointer to relocation data 1373 * @offset_start: starting offset 1374 * @offset_mask: offset mask (to align start offset on) 1375 * @reloc: reloc informations 1376 * 1377 * Check next packet is relocation packet3, do bo validation and compute 1378 * GPU offset using the provided start. 1379 **/ 1380 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p, 1381 struct radeon_cs_reloc **cs_reloc) 1382 { 1383 struct radeon_cs_chunk *relocs_chunk; 1384 struct radeon_cs_packet p3reloc; 1385 unsigned idx; 1386 int r; 1387 1388 if (p->chunk_relocs_idx == -1) { 1389 DRM_ERROR("No relocation chunk !\n"); 1390 return -EINVAL; 1391 } 1392 *cs_reloc = NULL; 1393 relocs_chunk = &p->chunks[p->chunk_relocs_idx]; 1394 r = r100_cs_packet_parse(p, &p3reloc, p->idx); 1395 if (r) { 1396 return r; 1397 } 1398 p->idx += p3reloc.count + 2; 1399 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) { 1400 DRM_ERROR("No packet3 for relocation for packet at %d.\n", 1401 p3reloc.idx); 1402 r100_cs_dump_packet(p, &p3reloc); 1403 return -EINVAL; 1404 } 1405 idx = radeon_get_ib_value(p, p3reloc.idx + 1); 1406 if (idx >= relocs_chunk->length_dw) { 1407 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n", 1408 idx, relocs_chunk->length_dw); 1409 r100_cs_dump_packet(p, &p3reloc); 1410 return -EINVAL; 1411 } 1412 /* FIXME: we assume reloc size is 4 dwords */ 1413 *cs_reloc = p->relocs_ptr[(idx / 4)]; 1414 return 0; 1415 } 1416 1417 static int r100_get_vtx_size(uint32_t vtx_fmt) 1418 { 1419 int vtx_size; 1420 vtx_size = 2; 1421 /* ordered according to bits in spec */ 1422 if (vtx_fmt & RADEON_SE_VTX_FMT_W0) 1423 vtx_size++; 1424 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR) 1425 vtx_size += 3; 1426 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA) 1427 vtx_size++; 1428 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR) 1429 vtx_size++; 1430 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC) 1431 vtx_size += 3; 1432 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG) 1433 vtx_size++; 1434 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC) 1435 vtx_size++; 1436 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0) 1437 vtx_size += 2; 1438 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1) 1439 vtx_size += 2; 1440 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1) 1441 vtx_size++; 1442 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2) 1443 vtx_size += 2; 1444 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2) 1445 vtx_size++; 1446 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3) 1447 vtx_size += 2; 1448 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3) 1449 vtx_size++; 1450 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0) 1451 vtx_size++; 1452 /* blend weight */ 1453 if (vtx_fmt & (0x7 << 15)) 1454 vtx_size += (vtx_fmt >> 15) & 0x7; 1455 if (vtx_fmt & RADEON_SE_VTX_FMT_N0) 1456 vtx_size += 3; 1457 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1) 1458 vtx_size += 2; 1459 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1) 1460 vtx_size++; 1461 if (vtx_fmt & RADEON_SE_VTX_FMT_W1) 1462 vtx_size++; 1463 if (vtx_fmt & RADEON_SE_VTX_FMT_N1) 1464 vtx_size++; 1465 if (vtx_fmt & RADEON_SE_VTX_FMT_Z) 1466 vtx_size++; 1467 return vtx_size; 1468 } 1469 1470 static int r100_packet0_check(struct radeon_cs_parser *p, 1471 struct radeon_cs_packet *pkt, 1472 unsigned idx, unsigned reg) 1473 { 1474 struct radeon_cs_reloc *reloc; 1475 struct r100_cs_track *track; 1476 volatile uint32_t *ib; 1477 uint32_t tmp; 1478 int r; 1479 int i, face; 1480 u32 tile_flags = 0; 1481 u32 idx_value; 1482 1483 ib = p->ib->ptr; 1484 track = (struct r100_cs_track *)p->track; 1485 1486 idx_value = radeon_get_ib_value(p, idx); 1487 1488 switch (reg) { 1489 case RADEON_CRTC_GUI_TRIG_VLINE: 1490 r = r100_cs_packet_parse_vline(p); 1491 if (r) { 1492 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1493 idx, reg); 1494 r100_cs_dump_packet(p, pkt); 1495 return r; 1496 } 1497 break; 1498 /* FIXME: only allow PACKET3 blit? easier to check for out of 1499 * range access */ 1500 case RADEON_DST_PITCH_OFFSET: 1501 case RADEON_SRC_PITCH_OFFSET: 1502 r = r100_reloc_pitch_offset(p, pkt, idx, reg); 1503 if (r) 1504 return r; 1505 break; 1506 case RADEON_RB3D_DEPTHOFFSET: 1507 r = r100_cs_packet_next_reloc(p, &reloc); 1508 if (r) { 1509 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1510 idx, reg); 1511 r100_cs_dump_packet(p, pkt); 1512 return r; 1513 } 1514 track->zb.robj = reloc->robj; 1515 track->zb.offset = idx_value; 1516 track->zb_dirty = true; 1517 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1518 break; 1519 case RADEON_RB3D_COLOROFFSET: 1520 r = r100_cs_packet_next_reloc(p, &reloc); 1521 if (r) { 1522 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1523 idx, reg); 1524 r100_cs_dump_packet(p, pkt); 1525 return r; 1526 } 1527 track->cb[0].robj = reloc->robj; 1528 track->cb[0].offset = idx_value; 1529 track->cb_dirty = true; 1530 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1531 break; 1532 case RADEON_PP_TXOFFSET_0: 1533 case RADEON_PP_TXOFFSET_1: 1534 case RADEON_PP_TXOFFSET_2: 1535 i = (reg - RADEON_PP_TXOFFSET_0) / 24; 1536 r = r100_cs_packet_next_reloc(p, &reloc); 1537 if (r) { 1538 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1539 idx, reg); 1540 r100_cs_dump_packet(p, pkt); 1541 return r; 1542 } 1543 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1544 track->textures[i].robj = reloc->robj; 1545 track->tex_dirty = true; 1546 break; 1547 case RADEON_PP_CUBIC_OFFSET_T0_0: 1548 case RADEON_PP_CUBIC_OFFSET_T0_1: 1549 case RADEON_PP_CUBIC_OFFSET_T0_2: 1550 case RADEON_PP_CUBIC_OFFSET_T0_3: 1551 case RADEON_PP_CUBIC_OFFSET_T0_4: 1552 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4; 1553 r = r100_cs_packet_next_reloc(p, &reloc); 1554 if (r) { 1555 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1556 idx, reg); 1557 r100_cs_dump_packet(p, pkt); 1558 return r; 1559 } 1560 track->textures[0].cube_info[i].offset = idx_value; 1561 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1562 track->textures[0].cube_info[i].robj = reloc->robj; 1563 track->tex_dirty = true; 1564 break; 1565 case RADEON_PP_CUBIC_OFFSET_T1_0: 1566 case RADEON_PP_CUBIC_OFFSET_T1_1: 1567 case RADEON_PP_CUBIC_OFFSET_T1_2: 1568 case RADEON_PP_CUBIC_OFFSET_T1_3: 1569 case RADEON_PP_CUBIC_OFFSET_T1_4: 1570 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4; 1571 r = r100_cs_packet_next_reloc(p, &reloc); 1572 if (r) { 1573 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1574 idx, reg); 1575 r100_cs_dump_packet(p, pkt); 1576 return r; 1577 } 1578 track->textures[1].cube_info[i].offset = idx_value; 1579 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1580 track->textures[1].cube_info[i].robj = reloc->robj; 1581 track->tex_dirty = true; 1582 break; 1583 case RADEON_PP_CUBIC_OFFSET_T2_0: 1584 case RADEON_PP_CUBIC_OFFSET_T2_1: 1585 case RADEON_PP_CUBIC_OFFSET_T2_2: 1586 case RADEON_PP_CUBIC_OFFSET_T2_3: 1587 case RADEON_PP_CUBIC_OFFSET_T2_4: 1588 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4; 1589 r = r100_cs_packet_next_reloc(p, &reloc); 1590 if (r) { 1591 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1592 idx, reg); 1593 r100_cs_dump_packet(p, pkt); 1594 return r; 1595 } 1596 track->textures[2].cube_info[i].offset = idx_value; 1597 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1598 track->textures[2].cube_info[i].robj = reloc->robj; 1599 track->tex_dirty = true; 1600 break; 1601 case RADEON_RE_WIDTH_HEIGHT: 1602 track->maxy = ((idx_value >> 16) & 0x7FF); 1603 track->cb_dirty = true; 1604 track->zb_dirty = true; 1605 break; 1606 case RADEON_RB3D_COLORPITCH: 1607 r = r100_cs_packet_next_reloc(p, &reloc); 1608 if (r) { 1609 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1610 idx, reg); 1611 r100_cs_dump_packet(p, pkt); 1612 return r; 1613 } 1614 1615 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 1616 tile_flags |= RADEON_COLOR_TILE_ENABLE; 1617 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) 1618 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE; 1619 1620 tmp = idx_value & ~(0x7 << 16); 1621 tmp |= tile_flags; 1622 ib[idx] = tmp; 1623 1624 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK; 1625 track->cb_dirty = true; 1626 break; 1627 case RADEON_RB3D_DEPTHPITCH: 1628 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK; 1629 track->zb_dirty = true; 1630 break; 1631 case RADEON_RB3D_CNTL: 1632 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) { 1633 case 7: 1634 case 8: 1635 case 9: 1636 case 11: 1637 case 12: 1638 track->cb[0].cpp = 1; 1639 break; 1640 case 3: 1641 case 4: 1642 case 15: 1643 track->cb[0].cpp = 2; 1644 break; 1645 case 6: 1646 track->cb[0].cpp = 4; 1647 break; 1648 default: 1649 DRM_ERROR("Invalid color buffer format (%d) !\n", 1650 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f)); 1651 return -EINVAL; 1652 } 1653 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE); 1654 track->cb_dirty = true; 1655 track->zb_dirty = true; 1656 break; 1657 case RADEON_RB3D_ZSTENCILCNTL: 1658 switch (idx_value & 0xf) { 1659 case 0: 1660 track->zb.cpp = 2; 1661 break; 1662 case 2: 1663 case 3: 1664 case 4: 1665 case 5: 1666 case 9: 1667 case 11: 1668 track->zb.cpp = 4; 1669 break; 1670 default: 1671 break; 1672 } 1673 track->zb_dirty = true; 1674 break; 1675 case RADEON_RB3D_ZPASS_ADDR: 1676 r = r100_cs_packet_next_reloc(p, &reloc); 1677 if (r) { 1678 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1679 idx, reg); 1680 r100_cs_dump_packet(p, pkt); 1681 return r; 1682 } 1683 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1684 break; 1685 case RADEON_PP_CNTL: 1686 { 1687 uint32_t temp = idx_value >> 4; 1688 for (i = 0; i < track->num_texture; i++) 1689 track->textures[i].enabled = !!(temp & (1 << i)); 1690 track->tex_dirty = true; 1691 } 1692 break; 1693 case RADEON_SE_VF_CNTL: 1694 track->vap_vf_cntl = idx_value; 1695 break; 1696 case RADEON_SE_VTX_FMT: 1697 track->vtx_size = r100_get_vtx_size(idx_value); 1698 break; 1699 case RADEON_PP_TEX_SIZE_0: 1700 case RADEON_PP_TEX_SIZE_1: 1701 case RADEON_PP_TEX_SIZE_2: 1702 i = (reg - RADEON_PP_TEX_SIZE_0) / 8; 1703 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1; 1704 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1; 1705 track->tex_dirty = true; 1706 break; 1707 case RADEON_PP_TEX_PITCH_0: 1708 case RADEON_PP_TEX_PITCH_1: 1709 case RADEON_PP_TEX_PITCH_2: 1710 i = (reg - RADEON_PP_TEX_PITCH_0) / 8; 1711 track->textures[i].pitch = idx_value + 32; 1712 track->tex_dirty = true; 1713 break; 1714 case RADEON_PP_TXFILTER_0: 1715 case RADEON_PP_TXFILTER_1: 1716 case RADEON_PP_TXFILTER_2: 1717 i = (reg - RADEON_PP_TXFILTER_0) / 24; 1718 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK) 1719 >> RADEON_MAX_MIP_LEVEL_SHIFT); 1720 tmp = (idx_value >> 23) & 0x7; 1721 if (tmp == 2 || tmp == 6) 1722 track->textures[i].roundup_w = false; 1723 tmp = (idx_value >> 27) & 0x7; 1724 if (tmp == 2 || tmp == 6) 1725 track->textures[i].roundup_h = false; 1726 track->tex_dirty = true; 1727 break; 1728 case RADEON_PP_TXFORMAT_0: 1729 case RADEON_PP_TXFORMAT_1: 1730 case RADEON_PP_TXFORMAT_2: 1731 i = (reg - RADEON_PP_TXFORMAT_0) / 24; 1732 if (idx_value & RADEON_TXFORMAT_NON_POWER2) { 1733 track->textures[i].use_pitch = 1; 1734 } else { 1735 track->textures[i].use_pitch = 0; 1736 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK); 1737 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK); 1738 } 1739 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE) 1740 track->textures[i].tex_coord_type = 2; 1741 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) { 1742 case RADEON_TXFORMAT_I8: 1743 case RADEON_TXFORMAT_RGB332: 1744 case RADEON_TXFORMAT_Y8: 1745 track->textures[i].cpp = 1; 1746 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 1747 break; 1748 case RADEON_TXFORMAT_AI88: 1749 case RADEON_TXFORMAT_ARGB1555: 1750 case RADEON_TXFORMAT_RGB565: 1751 case RADEON_TXFORMAT_ARGB4444: 1752 case RADEON_TXFORMAT_VYUY422: 1753 case RADEON_TXFORMAT_YVYU422: 1754 case RADEON_TXFORMAT_SHADOW16: 1755 case RADEON_TXFORMAT_LDUDV655: 1756 case RADEON_TXFORMAT_DUDV88: 1757 track->textures[i].cpp = 2; 1758 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 1759 break; 1760 case RADEON_TXFORMAT_ARGB8888: 1761 case RADEON_TXFORMAT_RGBA8888: 1762 case RADEON_TXFORMAT_SHADOW32: 1763 case RADEON_TXFORMAT_LDUDUV8888: 1764 track->textures[i].cpp = 4; 1765 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 1766 break; 1767 case RADEON_TXFORMAT_DXT1: 1768 track->textures[i].cpp = 1; 1769 track->textures[i].compress_format = R100_TRACK_COMP_DXT1; 1770 break; 1771 case RADEON_TXFORMAT_DXT23: 1772 case RADEON_TXFORMAT_DXT45: 1773 track->textures[i].cpp = 1; 1774 track->textures[i].compress_format = R100_TRACK_COMP_DXT35; 1775 break; 1776 } 1777 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf); 1778 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf); 1779 track->tex_dirty = true; 1780 break; 1781 case RADEON_PP_CUBIC_FACES_0: 1782 case RADEON_PP_CUBIC_FACES_1: 1783 case RADEON_PP_CUBIC_FACES_2: 1784 tmp = idx_value; 1785 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4; 1786 for (face = 0; face < 4; face++) { 1787 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf); 1788 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf); 1789 } 1790 track->tex_dirty = true; 1791 break; 1792 default: 1793 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n", 1794 reg, idx); 1795 return -EINVAL; 1796 } 1797 return 0; 1798 } 1799 1800 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, 1801 struct radeon_cs_packet *pkt, 1802 struct radeon_bo *robj) 1803 { 1804 unsigned idx; 1805 u32 value; 1806 idx = pkt->idx + 1; 1807 value = radeon_get_ib_value(p, idx + 2); 1808 if ((value + 1) > radeon_bo_size(robj)) { 1809 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER " 1810 "(need %u have %lu) !\n", 1811 value + 1, 1812 radeon_bo_size(robj)); 1813 return -EINVAL; 1814 } 1815 return 0; 1816 } 1817 1818 static int r100_packet3_check(struct radeon_cs_parser *p, 1819 struct radeon_cs_packet *pkt) 1820 { 1821 struct radeon_cs_reloc *reloc; 1822 struct r100_cs_track *track; 1823 unsigned idx; 1824 volatile uint32_t *ib; 1825 int r; 1826 1827 ib = p->ib->ptr; 1828 idx = pkt->idx + 1; 1829 track = (struct r100_cs_track *)p->track; 1830 switch (pkt->opcode) { 1831 case PACKET3_3D_LOAD_VBPNTR: 1832 r = r100_packet3_load_vbpntr(p, pkt, idx); 1833 if (r) 1834 return r; 1835 break; 1836 case PACKET3_INDX_BUFFER: 1837 r = r100_cs_packet_next_reloc(p, &reloc); 1838 if (r) { 1839 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); 1840 r100_cs_dump_packet(p, pkt); 1841 return r; 1842 } 1843 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset); 1844 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); 1845 if (r) { 1846 return r; 1847 } 1848 break; 1849 case 0x23: 1850 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */ 1851 r = r100_cs_packet_next_reloc(p, &reloc); 1852 if (r) { 1853 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); 1854 r100_cs_dump_packet(p, pkt); 1855 return r; 1856 } 1857 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset); 1858 track->num_arrays = 1; 1859 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2)); 1860 1861 track->arrays[0].robj = reloc->robj; 1862 track->arrays[0].esize = track->vtx_size; 1863 1864 track->max_indx = radeon_get_ib_value(p, idx+1); 1865 1866 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3); 1867 track->immd_dwords = pkt->count - 1; 1868 r = r100_cs_track_check(p->rdev, track); 1869 if (r) 1870 return r; 1871 break; 1872 case PACKET3_3D_DRAW_IMMD: 1873 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) { 1874 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1875 return -EINVAL; 1876 } 1877 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0)); 1878 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1879 track->immd_dwords = pkt->count - 1; 1880 r = r100_cs_track_check(p->rdev, track); 1881 if (r) 1882 return r; 1883 break; 1884 /* triggers drawing using in-packet vertex data */ 1885 case PACKET3_3D_DRAW_IMMD_2: 1886 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) { 1887 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1888 return -EINVAL; 1889 } 1890 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1891 track->immd_dwords = pkt->count; 1892 r = r100_cs_track_check(p->rdev, track); 1893 if (r) 1894 return r; 1895 break; 1896 /* triggers drawing using in-packet vertex data */ 1897 case PACKET3_3D_DRAW_VBUF_2: 1898 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1899 r = r100_cs_track_check(p->rdev, track); 1900 if (r) 1901 return r; 1902 break; 1903 /* triggers drawing of vertex buffers setup elsewhere */ 1904 case PACKET3_3D_DRAW_INDX_2: 1905 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1906 r = r100_cs_track_check(p->rdev, track); 1907 if (r) 1908 return r; 1909 break; 1910 /* triggers drawing using indices to vertex buffer */ 1911 case PACKET3_3D_DRAW_VBUF: 1912 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1913 r = r100_cs_track_check(p->rdev, track); 1914 if (r) 1915 return r; 1916 break; 1917 /* triggers drawing of vertex buffers setup elsewhere */ 1918 case PACKET3_3D_DRAW_INDX: 1919 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1920 r = r100_cs_track_check(p->rdev, track); 1921 if (r) 1922 return r; 1923 break; 1924 /* triggers drawing using indices to vertex buffer */ 1925 case PACKET3_3D_CLEAR_HIZ: 1926 case PACKET3_3D_CLEAR_ZMASK: 1927 if (p->rdev->hyperz_filp != p->filp) 1928 return -EINVAL; 1929 break; 1930 case PACKET3_NOP: 1931 break; 1932 default: 1933 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); 1934 return -EINVAL; 1935 } 1936 return 0; 1937 } 1938 1939 int r100_cs_parse(struct radeon_cs_parser *p) 1940 { 1941 struct radeon_cs_packet pkt; 1942 struct r100_cs_track *track; 1943 int r; 1944 1945 track = kzalloc(sizeof(*track), GFP_KERNEL); 1946 r100_cs_track_clear(p->rdev, track); 1947 p->track = track; 1948 do { 1949 r = r100_cs_packet_parse(p, &pkt, p->idx); 1950 if (r) { 1951 return r; 1952 } 1953 p->idx += pkt.count + 2; 1954 switch (pkt.type) { 1955 case PACKET_TYPE0: 1956 if (p->rdev->family >= CHIP_R200) 1957 r = r100_cs_parse_packet0(p, &pkt, 1958 p->rdev->config.r100.reg_safe_bm, 1959 p->rdev->config.r100.reg_safe_bm_size, 1960 &r200_packet0_check); 1961 else 1962 r = r100_cs_parse_packet0(p, &pkt, 1963 p->rdev->config.r100.reg_safe_bm, 1964 p->rdev->config.r100.reg_safe_bm_size, 1965 &r100_packet0_check); 1966 break; 1967 case PACKET_TYPE2: 1968 break; 1969 case PACKET_TYPE3: 1970 r = r100_packet3_check(p, &pkt); 1971 break; 1972 default: 1973 DRM_ERROR("Unknown packet type %d !\n", 1974 pkt.type); 1975 return -EINVAL; 1976 } 1977 if (r) { 1978 return r; 1979 } 1980 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw); 1981 return 0; 1982 } 1983 1984 1985 /* 1986 * Global GPU functions 1987 */ 1988 void r100_errata(struct radeon_device *rdev) 1989 { 1990 rdev->pll_errata = 0; 1991 1992 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) { 1993 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS; 1994 } 1995 1996 if (rdev->family == CHIP_RV100 || 1997 rdev->family == CHIP_RS100 || 1998 rdev->family == CHIP_RS200) { 1999 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY; 2000 } 2001 } 2002 2003 /* Wait for vertical sync on primary CRTC */ 2004 void r100_gpu_wait_for_vsync(struct radeon_device *rdev) 2005 { 2006 uint32_t crtc_gen_cntl, tmp; 2007 int i; 2008 2009 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL); 2010 if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) || 2011 !(crtc_gen_cntl & RADEON_CRTC_EN)) { 2012 return; 2013 } 2014 /* Clear the CRTC_VBLANK_SAVE bit */ 2015 WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR); 2016 for (i = 0; i < rdev->usec_timeout; i++) { 2017 tmp = RREG32(RADEON_CRTC_STATUS); 2018 if (tmp & RADEON_CRTC_VBLANK_SAVE) { 2019 return; 2020 } 2021 DRM_UDELAY(1); 2022 } 2023 } 2024 2025 /* Wait for vertical sync on secondary CRTC */ 2026 void r100_gpu_wait_for_vsync2(struct radeon_device *rdev) 2027 { 2028 uint32_t crtc2_gen_cntl, tmp; 2029 int i; 2030 2031 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); 2032 if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) || 2033 !(crtc2_gen_cntl & RADEON_CRTC2_EN)) 2034 return; 2035 2036 /* Clear the CRTC_VBLANK_SAVE bit */ 2037 WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR); 2038 for (i = 0; i < rdev->usec_timeout; i++) { 2039 tmp = RREG32(RADEON_CRTC2_STATUS); 2040 if (tmp & RADEON_CRTC2_VBLANK_SAVE) { 2041 return; 2042 } 2043 DRM_UDELAY(1); 2044 } 2045 } 2046 2047 int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n) 2048 { 2049 unsigned i; 2050 uint32_t tmp; 2051 2052 for (i = 0; i < rdev->usec_timeout; i++) { 2053 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK; 2054 if (tmp >= n) { 2055 return 0; 2056 } 2057 DRM_UDELAY(1); 2058 } 2059 return -1; 2060 } 2061 2062 int r100_gui_wait_for_idle(struct radeon_device *rdev) 2063 { 2064 unsigned i; 2065 uint32_t tmp; 2066 2067 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) { 2068 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !" 2069 " Bad things might happen.\n"); 2070 } 2071 for (i = 0; i < rdev->usec_timeout; i++) { 2072 tmp = RREG32(RADEON_RBBM_STATUS); 2073 if (!(tmp & RADEON_RBBM_ACTIVE)) { 2074 return 0; 2075 } 2076 DRM_UDELAY(1); 2077 } 2078 return -1; 2079 } 2080 2081 int r100_mc_wait_for_idle(struct radeon_device *rdev) 2082 { 2083 unsigned i; 2084 uint32_t tmp; 2085 2086 for (i = 0; i < rdev->usec_timeout; i++) { 2087 /* read MC_STATUS */ 2088 tmp = RREG32(RADEON_MC_STATUS); 2089 if (tmp & RADEON_MC_IDLE) { 2090 return 0; 2091 } 2092 DRM_UDELAY(1); 2093 } 2094 return -1; 2095 } 2096 2097 void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_cp *cp) 2098 { 2099 lockup->last_cp_rptr = cp->rptr; 2100 lockup->last_jiffies = jiffies; 2101 } 2102 2103 /** 2104 * r100_gpu_cp_is_lockup() - check if CP is lockup by recording information 2105 * @rdev: radeon device structure 2106 * @lockup: r100_gpu_lockup structure holding CP lockup tracking informations 2107 * @cp: radeon_cp structure holding CP information 2108 * 2109 * We don't need to initialize the lockup tracking information as we will either 2110 * have CP rptr to a different value of jiffies wrap around which will force 2111 * initialization of the lockup tracking informations. 2112 * 2113 * A possible false positivie is if we get call after while and last_cp_rptr == 2114 * the current CP rptr, even if it's unlikely it might happen. To avoid this 2115 * if the elapsed time since last call is bigger than 2 second than we return 2116 * false and update the tracking information. Due to this the caller must call 2117 * r100_gpu_cp_is_lockup several time in less than 2sec for lockup to be reported 2118 * the fencing code should be cautious about that. 2119 * 2120 * Caller should write to the ring to force CP to do something so we don't get 2121 * false positive when CP is just gived nothing to do. 2122 * 2123 **/ 2124 bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_cp *cp) 2125 { 2126 unsigned long cjiffies, elapsed; 2127 2128 cjiffies = jiffies; 2129 if (!time_after(cjiffies, lockup->last_jiffies)) { 2130 /* likely a wrap around */ 2131 lockup->last_cp_rptr = cp->rptr; 2132 lockup->last_jiffies = jiffies; 2133 return false; 2134 } 2135 if (cp->rptr != lockup->last_cp_rptr) { 2136 /* CP is still working no lockup */ 2137 lockup->last_cp_rptr = cp->rptr; 2138 lockup->last_jiffies = jiffies; 2139 return false; 2140 } 2141 elapsed = jiffies_to_msecs(cjiffies - lockup->last_jiffies); 2142 if (elapsed >= 10000) { 2143 dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed); 2144 return true; 2145 } 2146 /* give a chance to the GPU ... */ 2147 return false; 2148 } 2149 2150 bool r100_gpu_is_lockup(struct radeon_device *rdev) 2151 { 2152 u32 rbbm_status; 2153 int r; 2154 2155 rbbm_status = RREG32(R_000E40_RBBM_STATUS); 2156 if (!G_000E40_GUI_ACTIVE(rbbm_status)) { 2157 r100_gpu_lockup_update(&rdev->config.r100.lockup, &rdev->cp); 2158 return false; 2159 } 2160 /* force CP activities */ 2161 r = radeon_ring_lock(rdev, 2); 2162 if (!r) { 2163 /* PACKET2 NOP */ 2164 radeon_ring_write(rdev, 0x80000000); 2165 radeon_ring_write(rdev, 0x80000000); 2166 radeon_ring_unlock_commit(rdev); 2167 } 2168 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR); 2169 return r100_gpu_cp_is_lockup(rdev, &rdev->config.r100.lockup, &rdev->cp); 2170 } 2171 2172 void r100_bm_disable(struct radeon_device *rdev) 2173 { 2174 u32 tmp; 2175 2176 /* disable bus mastering */ 2177 tmp = RREG32(R_000030_BUS_CNTL); 2178 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044); 2179 mdelay(1); 2180 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042); 2181 mdelay(1); 2182 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040); 2183 tmp = RREG32(RADEON_BUS_CNTL); 2184 mdelay(1); 2185 pci_read_config_word(rdev->pdev, 0x4, (u16*)&tmp); 2186 pci_write_config_word(rdev->pdev, 0x4, tmp & 0xFFFB); 2187 mdelay(1); 2188 } 2189 2190 int r100_asic_reset(struct radeon_device *rdev) 2191 { 2192 struct r100_mc_save save; 2193 u32 status, tmp; 2194 int ret = 0; 2195 2196 status = RREG32(R_000E40_RBBM_STATUS); 2197 if (!G_000E40_GUI_ACTIVE(status)) { 2198 return 0; 2199 } 2200 r100_mc_stop(rdev, &save); 2201 status = RREG32(R_000E40_RBBM_STATUS); 2202 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 2203 /* stop CP */ 2204 WREG32(RADEON_CP_CSQ_CNTL, 0); 2205 tmp = RREG32(RADEON_CP_RB_CNTL); 2206 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); 2207 WREG32(RADEON_CP_RB_RPTR_WR, 0); 2208 WREG32(RADEON_CP_RB_WPTR, 0); 2209 WREG32(RADEON_CP_RB_CNTL, tmp); 2210 /* save PCI state */ 2211 pci_save_state(rdev->pdev); 2212 /* disable bus mastering */ 2213 r100_bm_disable(rdev); 2214 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) | 2215 S_0000F0_SOFT_RESET_RE(1) | 2216 S_0000F0_SOFT_RESET_PP(1) | 2217 S_0000F0_SOFT_RESET_RB(1)); 2218 RREG32(R_0000F0_RBBM_SOFT_RESET); 2219 mdelay(500); 2220 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 2221 mdelay(1); 2222 status = RREG32(R_000E40_RBBM_STATUS); 2223 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 2224 /* reset CP */ 2225 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); 2226 RREG32(R_0000F0_RBBM_SOFT_RESET); 2227 mdelay(500); 2228 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 2229 mdelay(1); 2230 status = RREG32(R_000E40_RBBM_STATUS); 2231 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 2232 /* restore PCI & busmastering */ 2233 pci_restore_state(rdev->pdev); 2234 r100_enable_bm(rdev); 2235 /* Check if GPU is idle */ 2236 if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) || 2237 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) { 2238 dev_err(rdev->dev, "failed to reset GPU\n"); 2239 rdev->gpu_lockup = true; 2240 ret = -1; 2241 } else 2242 dev_info(rdev->dev, "GPU reset succeed\n"); 2243 r100_mc_resume(rdev, &save); 2244 return ret; 2245 } 2246 2247 void r100_set_common_regs(struct radeon_device *rdev) 2248 { 2249 struct drm_device *dev = rdev->ddev; 2250 bool force_dac2 = false; 2251 u32 tmp; 2252 2253 /* set these so they don't interfere with anything */ 2254 WREG32(RADEON_OV0_SCALE_CNTL, 0); 2255 WREG32(RADEON_SUBPIC_CNTL, 0); 2256 WREG32(RADEON_VIPH_CONTROL, 0); 2257 WREG32(RADEON_I2C_CNTL_1, 0); 2258 WREG32(RADEON_DVI_I2C_CNTL_1, 0); 2259 WREG32(RADEON_CAP0_TRIG_CNTL, 0); 2260 WREG32(RADEON_CAP1_TRIG_CNTL, 0); 2261 2262 /* always set up dac2 on rn50 and some rv100 as lots 2263 * of servers seem to wire it up to a VGA port but 2264 * don't report it in the bios connector 2265 * table. 2266 */ 2267 switch (dev->pdev->device) { 2268 /* RN50 */ 2269 case 0x515e: 2270 case 0x5969: 2271 force_dac2 = true; 2272 break; 2273 /* RV100*/ 2274 case 0x5159: 2275 case 0x515a: 2276 /* DELL triple head servers */ 2277 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) && 2278 ((dev->pdev->subsystem_device == 0x016c) || 2279 (dev->pdev->subsystem_device == 0x016d) || 2280 (dev->pdev->subsystem_device == 0x016e) || 2281 (dev->pdev->subsystem_device == 0x016f) || 2282 (dev->pdev->subsystem_device == 0x0170) || 2283 (dev->pdev->subsystem_device == 0x017d) || 2284 (dev->pdev->subsystem_device == 0x017e) || 2285 (dev->pdev->subsystem_device == 0x0183) || 2286 (dev->pdev->subsystem_device == 0x018a) || 2287 (dev->pdev->subsystem_device == 0x019a))) 2288 force_dac2 = true; 2289 break; 2290 } 2291 2292 if (force_dac2) { 2293 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG); 2294 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); 2295 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2); 2296 2297 /* For CRT on DAC2, don't turn it on if BIOS didn't 2298 enable it, even it's detected. 2299 */ 2300 2301 /* force it to crtc0 */ 2302 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL; 2303 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL; 2304 disp_hw_debug |= RADEON_CRT2_DISP1_SEL; 2305 2306 /* set up the TV DAC */ 2307 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL | 2308 RADEON_TV_DAC_STD_MASK | 2309 RADEON_TV_DAC_RDACPD | 2310 RADEON_TV_DAC_GDACPD | 2311 RADEON_TV_DAC_BDACPD | 2312 RADEON_TV_DAC_BGADJ_MASK | 2313 RADEON_TV_DAC_DACADJ_MASK); 2314 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK | 2315 RADEON_TV_DAC_NHOLD | 2316 RADEON_TV_DAC_STD_PS2 | 2317 (0x58 << 16)); 2318 2319 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); 2320 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug); 2321 WREG32(RADEON_DAC_CNTL2, dac2_cntl); 2322 } 2323 2324 /* switch PM block to ACPI mode */ 2325 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL); 2326 tmp &= ~RADEON_PM_MODE_SEL; 2327 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp); 2328 2329 } 2330 2331 /* 2332 * VRAM info 2333 */ 2334 static void r100_vram_get_type(struct radeon_device *rdev) 2335 { 2336 uint32_t tmp; 2337 2338 rdev->mc.vram_is_ddr = false; 2339 if (rdev->flags & RADEON_IS_IGP) 2340 rdev->mc.vram_is_ddr = true; 2341 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR) 2342 rdev->mc.vram_is_ddr = true; 2343 if ((rdev->family == CHIP_RV100) || 2344 (rdev->family == CHIP_RS100) || 2345 (rdev->family == CHIP_RS200)) { 2346 tmp = RREG32(RADEON_MEM_CNTL); 2347 if (tmp & RV100_HALF_MODE) { 2348 rdev->mc.vram_width = 32; 2349 } else { 2350 rdev->mc.vram_width = 64; 2351 } 2352 if (rdev->flags & RADEON_SINGLE_CRTC) { 2353 rdev->mc.vram_width /= 4; 2354 rdev->mc.vram_is_ddr = true; 2355 } 2356 } else if (rdev->family <= CHIP_RV280) { 2357 tmp = RREG32(RADEON_MEM_CNTL); 2358 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) { 2359 rdev->mc.vram_width = 128; 2360 } else { 2361 rdev->mc.vram_width = 64; 2362 } 2363 } else { 2364 /* newer IGPs */ 2365 rdev->mc.vram_width = 128; 2366 } 2367 } 2368 2369 static u32 r100_get_accessible_vram(struct radeon_device *rdev) 2370 { 2371 u32 aper_size; 2372 u8 byte; 2373 2374 aper_size = RREG32(RADEON_CONFIG_APER_SIZE); 2375 2376 /* Set HDP_APER_CNTL only on cards that are known not to be broken, 2377 * that is has the 2nd generation multifunction PCI interface 2378 */ 2379 if (rdev->family == CHIP_RV280 || 2380 rdev->family >= CHIP_RV350) { 2381 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL, 2382 ~RADEON_HDP_APER_CNTL); 2383 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n"); 2384 return aper_size * 2; 2385 } 2386 2387 /* Older cards have all sorts of funny issues to deal with. First 2388 * check if it's a multifunction card by reading the PCI config 2389 * header type... Limit those to one aperture size 2390 */ 2391 pci_read_config_byte(rdev->pdev, 0xe, &byte); 2392 if (byte & 0x80) { 2393 DRM_INFO("Generation 1 PCI interface in multifunction mode\n"); 2394 DRM_INFO("Limiting VRAM to one aperture\n"); 2395 return aper_size; 2396 } 2397 2398 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS 2399 * have set it up. We don't write this as it's broken on some ASICs but 2400 * we expect the BIOS to have done the right thing (might be too optimistic...) 2401 */ 2402 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL) 2403 return aper_size * 2; 2404 return aper_size; 2405 } 2406 2407 void r100_vram_init_sizes(struct radeon_device *rdev) 2408 { 2409 u64 config_aper_size; 2410 2411 /* work out accessible VRAM */ 2412 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); 2413 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); 2414 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev); 2415 /* FIXME we don't use the second aperture yet when we could use it */ 2416 if (rdev->mc.visible_vram_size > rdev->mc.aper_size) 2417 rdev->mc.visible_vram_size = rdev->mc.aper_size; 2418 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE); 2419 if (rdev->flags & RADEON_IS_IGP) { 2420 uint32_t tom; 2421 /* read NB_TOM to get the amount of ram stolen for the GPU */ 2422 tom = RREG32(RADEON_NB_TOM); 2423 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16); 2424 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); 2425 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 2426 } else { 2427 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); 2428 /* Some production boards of m6 will report 0 2429 * if it's 8 MB 2430 */ 2431 if (rdev->mc.real_vram_size == 0) { 2432 rdev->mc.real_vram_size = 8192 * 1024; 2433 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); 2434 } 2435 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM - 2436 * Novell bug 204882 + along with lots of ubuntu ones 2437 */ 2438 if (rdev->mc.aper_size > config_aper_size) 2439 config_aper_size = rdev->mc.aper_size; 2440 2441 if (config_aper_size > rdev->mc.real_vram_size) 2442 rdev->mc.mc_vram_size = config_aper_size; 2443 else 2444 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 2445 } 2446 } 2447 2448 void r100_vga_set_state(struct radeon_device *rdev, bool state) 2449 { 2450 uint32_t temp; 2451 2452 temp = RREG32(RADEON_CONFIG_CNTL); 2453 if (state == false) { 2454 temp &= ~RADEON_CFG_VGA_RAM_EN; 2455 temp |= RADEON_CFG_VGA_IO_DIS; 2456 } else { 2457 temp &= ~RADEON_CFG_VGA_IO_DIS; 2458 } 2459 WREG32(RADEON_CONFIG_CNTL, temp); 2460 } 2461 2462 void r100_mc_init(struct radeon_device *rdev) 2463 { 2464 u64 base; 2465 2466 r100_vram_get_type(rdev); 2467 r100_vram_init_sizes(rdev); 2468 base = rdev->mc.aper_base; 2469 if (rdev->flags & RADEON_IS_IGP) 2470 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; 2471 radeon_vram_location(rdev, &rdev->mc, base); 2472 rdev->mc.gtt_base_align = 0; 2473 if (!(rdev->flags & RADEON_IS_AGP)) 2474 radeon_gtt_location(rdev, &rdev->mc); 2475 radeon_update_bandwidth_info(rdev); 2476 } 2477 2478 2479 /* 2480 * Indirect registers accessor 2481 */ 2482 void r100_pll_errata_after_index(struct radeon_device *rdev) 2483 { 2484 if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) { 2485 (void)RREG32(RADEON_CLOCK_CNTL_DATA); 2486 (void)RREG32(RADEON_CRTC_GEN_CNTL); 2487 } 2488 } 2489 2490 static void r100_pll_errata_after_data(struct radeon_device *rdev) 2491 { 2492 /* This workarounds is necessary on RV100, RS100 and RS200 chips 2493 * or the chip could hang on a subsequent access 2494 */ 2495 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) { 2496 udelay(5000); 2497 } 2498 2499 /* This function is required to workaround a hardware bug in some (all?) 2500 * revisions of the R300. This workaround should be called after every 2501 * CLOCK_CNTL_INDEX register access. If not, register reads afterward 2502 * may not be correct. 2503 */ 2504 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) { 2505 uint32_t save, tmp; 2506 2507 save = RREG32(RADEON_CLOCK_CNTL_INDEX); 2508 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 2509 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp); 2510 tmp = RREG32(RADEON_CLOCK_CNTL_DATA); 2511 WREG32(RADEON_CLOCK_CNTL_INDEX, save); 2512 } 2513 } 2514 2515 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg) 2516 { 2517 uint32_t data; 2518 2519 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f); 2520 r100_pll_errata_after_index(rdev); 2521 data = RREG32(RADEON_CLOCK_CNTL_DATA); 2522 r100_pll_errata_after_data(rdev); 2523 return data; 2524 } 2525 2526 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 2527 { 2528 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN)); 2529 r100_pll_errata_after_index(rdev); 2530 WREG32(RADEON_CLOCK_CNTL_DATA, v); 2531 r100_pll_errata_after_data(rdev); 2532 } 2533 2534 void r100_set_safe_registers(struct radeon_device *rdev) 2535 { 2536 if (ASIC_IS_RN50(rdev)) { 2537 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm; 2538 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm); 2539 } else if (rdev->family < CHIP_R200) { 2540 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm; 2541 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm); 2542 } else { 2543 r200_set_safe_registers(rdev); 2544 } 2545 } 2546 2547 /* 2548 * Debugfs info 2549 */ 2550 #if defined(CONFIG_DEBUG_FS) 2551 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data) 2552 { 2553 struct drm_info_node *node = (struct drm_info_node *) m->private; 2554 struct drm_device *dev = node->minor->dev; 2555 struct radeon_device *rdev = dev->dev_private; 2556 uint32_t reg, value; 2557 unsigned i; 2558 2559 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS)); 2560 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C)); 2561 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); 2562 for (i = 0; i < 64; i++) { 2563 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100); 2564 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2; 2565 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i); 2566 value = RREG32(RADEON_RBBM_CMDFIFO_DATA); 2567 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value); 2568 } 2569 return 0; 2570 } 2571 2572 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data) 2573 { 2574 struct drm_info_node *node = (struct drm_info_node *) m->private; 2575 struct drm_device *dev = node->minor->dev; 2576 struct radeon_device *rdev = dev->dev_private; 2577 uint32_t rdp, wdp; 2578 unsigned count, i, j; 2579 2580 radeon_ring_free_size(rdev); 2581 rdp = RREG32(RADEON_CP_RB_RPTR); 2582 wdp = RREG32(RADEON_CP_RB_WPTR); 2583 count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask; 2584 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); 2585 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp); 2586 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp); 2587 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw); 2588 seq_printf(m, "%u dwords in ring\n", count); 2589 for (j = 0; j <= count; j++) { 2590 i = (rdp + j) & rdev->cp.ptr_mask; 2591 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]); 2592 } 2593 return 0; 2594 } 2595 2596 2597 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data) 2598 { 2599 struct drm_info_node *node = (struct drm_info_node *) m->private; 2600 struct drm_device *dev = node->minor->dev; 2601 struct radeon_device *rdev = dev->dev_private; 2602 uint32_t csq_stat, csq2_stat, tmp; 2603 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr; 2604 unsigned i; 2605 2606 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); 2607 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE)); 2608 csq_stat = RREG32(RADEON_CP_CSQ_STAT); 2609 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT); 2610 r_rptr = (csq_stat >> 0) & 0x3ff; 2611 r_wptr = (csq_stat >> 10) & 0x3ff; 2612 ib1_rptr = (csq_stat >> 20) & 0x3ff; 2613 ib1_wptr = (csq2_stat >> 0) & 0x3ff; 2614 ib2_rptr = (csq2_stat >> 10) & 0x3ff; 2615 ib2_wptr = (csq2_stat >> 20) & 0x3ff; 2616 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat); 2617 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat); 2618 seq_printf(m, "Ring rptr %u\n", r_rptr); 2619 seq_printf(m, "Ring wptr %u\n", r_wptr); 2620 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr); 2621 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr); 2622 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr); 2623 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr); 2624 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms 2625 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */ 2626 seq_printf(m, "Ring fifo:\n"); 2627 for (i = 0; i < 256; i++) { 2628 WREG32(RADEON_CP_CSQ_ADDR, i << 2); 2629 tmp = RREG32(RADEON_CP_CSQ_DATA); 2630 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp); 2631 } 2632 seq_printf(m, "Indirect1 fifo:\n"); 2633 for (i = 256; i <= 512; i++) { 2634 WREG32(RADEON_CP_CSQ_ADDR, i << 2); 2635 tmp = RREG32(RADEON_CP_CSQ_DATA); 2636 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp); 2637 } 2638 seq_printf(m, "Indirect2 fifo:\n"); 2639 for (i = 640; i < ib1_wptr; i++) { 2640 WREG32(RADEON_CP_CSQ_ADDR, i << 2); 2641 tmp = RREG32(RADEON_CP_CSQ_DATA); 2642 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp); 2643 } 2644 return 0; 2645 } 2646 2647 static int r100_debugfs_mc_info(struct seq_file *m, void *data) 2648 { 2649 struct drm_info_node *node = (struct drm_info_node *) m->private; 2650 struct drm_device *dev = node->minor->dev; 2651 struct radeon_device *rdev = dev->dev_private; 2652 uint32_t tmp; 2653 2654 tmp = RREG32(RADEON_CONFIG_MEMSIZE); 2655 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp); 2656 tmp = RREG32(RADEON_MC_FB_LOCATION); 2657 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp); 2658 tmp = RREG32(RADEON_BUS_CNTL); 2659 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp); 2660 tmp = RREG32(RADEON_MC_AGP_LOCATION); 2661 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp); 2662 tmp = RREG32(RADEON_AGP_BASE); 2663 seq_printf(m, "AGP_BASE 0x%08x\n", tmp); 2664 tmp = RREG32(RADEON_HOST_PATH_CNTL); 2665 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp); 2666 tmp = RREG32(0x01D0); 2667 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp); 2668 tmp = RREG32(RADEON_AIC_LO_ADDR); 2669 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp); 2670 tmp = RREG32(RADEON_AIC_HI_ADDR); 2671 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp); 2672 tmp = RREG32(0x01E4); 2673 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp); 2674 return 0; 2675 } 2676 2677 static struct drm_info_list r100_debugfs_rbbm_list[] = { 2678 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL}, 2679 }; 2680 2681 static struct drm_info_list r100_debugfs_cp_list[] = { 2682 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL}, 2683 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL}, 2684 }; 2685 2686 static struct drm_info_list r100_debugfs_mc_info_list[] = { 2687 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL}, 2688 }; 2689 #endif 2690 2691 int r100_debugfs_rbbm_init(struct radeon_device *rdev) 2692 { 2693 #if defined(CONFIG_DEBUG_FS) 2694 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1); 2695 #else 2696 return 0; 2697 #endif 2698 } 2699 2700 int r100_debugfs_cp_init(struct radeon_device *rdev) 2701 { 2702 #if defined(CONFIG_DEBUG_FS) 2703 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2); 2704 #else 2705 return 0; 2706 #endif 2707 } 2708 2709 int r100_debugfs_mc_info_init(struct radeon_device *rdev) 2710 { 2711 #if defined(CONFIG_DEBUG_FS) 2712 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1); 2713 #else 2714 return 0; 2715 #endif 2716 } 2717 2718 int r100_set_surface_reg(struct radeon_device *rdev, int reg, 2719 uint32_t tiling_flags, uint32_t pitch, 2720 uint32_t offset, uint32_t obj_size) 2721 { 2722 int surf_index = reg * 16; 2723 int flags = 0; 2724 2725 if (rdev->family <= CHIP_RS200) { 2726 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) 2727 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) 2728 flags |= RADEON_SURF_TILE_COLOR_BOTH; 2729 if (tiling_flags & RADEON_TILING_MACRO) 2730 flags |= RADEON_SURF_TILE_COLOR_MACRO; 2731 } else if (rdev->family <= CHIP_RV280) { 2732 if (tiling_flags & (RADEON_TILING_MACRO)) 2733 flags |= R200_SURF_TILE_COLOR_MACRO; 2734 if (tiling_flags & RADEON_TILING_MICRO) 2735 flags |= R200_SURF_TILE_COLOR_MICRO; 2736 } else { 2737 if (tiling_flags & RADEON_TILING_MACRO) 2738 flags |= R300_SURF_TILE_MACRO; 2739 if (tiling_flags & RADEON_TILING_MICRO) 2740 flags |= R300_SURF_TILE_MICRO; 2741 } 2742 2743 if (tiling_flags & RADEON_TILING_SWAP_16BIT) 2744 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP; 2745 if (tiling_flags & RADEON_TILING_SWAP_32BIT) 2746 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP; 2747 2748 /* when we aren't tiling the pitch seems to needs to be furtherdivided down. - tested on power5 + rn50 server */ 2749 if (tiling_flags & (RADEON_TILING_SWAP_16BIT | RADEON_TILING_SWAP_32BIT)) { 2750 if (!(tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) 2751 if (ASIC_IS_RN50(rdev)) 2752 pitch /= 16; 2753 } 2754 2755 /* r100/r200 divide by 16 */ 2756 if (rdev->family < CHIP_R300) 2757 flags |= pitch / 16; 2758 else 2759 flags |= pitch / 8; 2760 2761 2762 DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1); 2763 WREG32(RADEON_SURFACE0_INFO + surf_index, flags); 2764 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset); 2765 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1); 2766 return 0; 2767 } 2768 2769 void r100_clear_surface_reg(struct radeon_device *rdev, int reg) 2770 { 2771 int surf_index = reg * 16; 2772 WREG32(RADEON_SURFACE0_INFO + surf_index, 0); 2773 } 2774 2775 void r100_bandwidth_update(struct radeon_device *rdev) 2776 { 2777 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff; 2778 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff; 2779 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff; 2780 uint32_t temp, data, mem_trcd, mem_trp, mem_tras; 2781 fixed20_12 memtcas_ff[8] = { 2782 dfixed_init(1), 2783 dfixed_init(2), 2784 dfixed_init(3), 2785 dfixed_init(0), 2786 dfixed_init_half(1), 2787 dfixed_init_half(2), 2788 dfixed_init(0), 2789 }; 2790 fixed20_12 memtcas_rs480_ff[8] = { 2791 dfixed_init(0), 2792 dfixed_init(1), 2793 dfixed_init(2), 2794 dfixed_init(3), 2795 dfixed_init(0), 2796 dfixed_init_half(1), 2797 dfixed_init_half(2), 2798 dfixed_init_half(3), 2799 }; 2800 fixed20_12 memtcas2_ff[8] = { 2801 dfixed_init(0), 2802 dfixed_init(1), 2803 dfixed_init(2), 2804 dfixed_init(3), 2805 dfixed_init(4), 2806 dfixed_init(5), 2807 dfixed_init(6), 2808 dfixed_init(7), 2809 }; 2810 fixed20_12 memtrbs[8] = { 2811 dfixed_init(1), 2812 dfixed_init_half(1), 2813 dfixed_init(2), 2814 dfixed_init_half(2), 2815 dfixed_init(3), 2816 dfixed_init_half(3), 2817 dfixed_init(4), 2818 dfixed_init_half(4) 2819 }; 2820 fixed20_12 memtrbs_r4xx[8] = { 2821 dfixed_init(4), 2822 dfixed_init(5), 2823 dfixed_init(6), 2824 dfixed_init(7), 2825 dfixed_init(8), 2826 dfixed_init(9), 2827 dfixed_init(10), 2828 dfixed_init(11) 2829 }; 2830 fixed20_12 min_mem_eff; 2831 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1; 2832 fixed20_12 cur_latency_mclk, cur_latency_sclk; 2833 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate, 2834 disp_drain_rate2, read_return_rate; 2835 fixed20_12 time_disp1_drop_priority; 2836 int c; 2837 int cur_size = 16; /* in octawords */ 2838 int critical_point = 0, critical_point2; 2839 /* uint32_t read_return_rate, time_disp1_drop_priority; */ 2840 int stop_req, max_stop_req; 2841 struct drm_display_mode *mode1 = NULL; 2842 struct drm_display_mode *mode2 = NULL; 2843 uint32_t pixel_bytes1 = 0; 2844 uint32_t pixel_bytes2 = 0; 2845 2846 radeon_update_display_priority(rdev); 2847 2848 if (rdev->mode_info.crtcs[0]->base.enabled) { 2849 mode1 = &rdev->mode_info.crtcs[0]->base.mode; 2850 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8; 2851 } 2852 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 2853 if (rdev->mode_info.crtcs[1]->base.enabled) { 2854 mode2 = &rdev->mode_info.crtcs[1]->base.mode; 2855 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8; 2856 } 2857 } 2858 2859 min_mem_eff.full = dfixed_const_8(0); 2860 /* get modes */ 2861 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) { 2862 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER); 2863 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT); 2864 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT); 2865 /* check crtc enables */ 2866 if (mode2) 2867 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT); 2868 if (mode1) 2869 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT); 2870 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer); 2871 } 2872 2873 /* 2874 * determine is there is enough bw for current mode 2875 */ 2876 sclk_ff = rdev->pm.sclk; 2877 mclk_ff = rdev->pm.mclk; 2878 2879 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1); 2880 temp_ff.full = dfixed_const(temp); 2881 mem_bw.full = dfixed_mul(mclk_ff, temp_ff); 2882 2883 pix_clk.full = 0; 2884 pix_clk2.full = 0; 2885 peak_disp_bw.full = 0; 2886 if (mode1) { 2887 temp_ff.full = dfixed_const(1000); 2888 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */ 2889 pix_clk.full = dfixed_div(pix_clk, temp_ff); 2890 temp_ff.full = dfixed_const(pixel_bytes1); 2891 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff); 2892 } 2893 if (mode2) { 2894 temp_ff.full = dfixed_const(1000); 2895 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */ 2896 pix_clk2.full = dfixed_div(pix_clk2, temp_ff); 2897 temp_ff.full = dfixed_const(pixel_bytes2); 2898 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff); 2899 } 2900 2901 mem_bw.full = dfixed_mul(mem_bw, min_mem_eff); 2902 if (peak_disp_bw.full >= mem_bw.full) { 2903 DRM_ERROR("You may not have enough display bandwidth for current mode\n" 2904 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n"); 2905 } 2906 2907 /* Get values from the EXT_MEM_CNTL register...converting its contents. */ 2908 temp = RREG32(RADEON_MEM_TIMING_CNTL); 2909 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */ 2910 mem_trcd = ((temp >> 2) & 0x3) + 1; 2911 mem_trp = ((temp & 0x3)) + 1; 2912 mem_tras = ((temp & 0x70) >> 4) + 1; 2913 } else if (rdev->family == CHIP_R300 || 2914 rdev->family == CHIP_R350) { /* r300, r350 */ 2915 mem_trcd = (temp & 0x7) + 1; 2916 mem_trp = ((temp >> 8) & 0x7) + 1; 2917 mem_tras = ((temp >> 11) & 0xf) + 4; 2918 } else if (rdev->family == CHIP_RV350 || 2919 rdev->family <= CHIP_RV380) { 2920 /* rv3x0 */ 2921 mem_trcd = (temp & 0x7) + 3; 2922 mem_trp = ((temp >> 8) & 0x7) + 3; 2923 mem_tras = ((temp >> 11) & 0xf) + 6; 2924 } else if (rdev->family == CHIP_R420 || 2925 rdev->family == CHIP_R423 || 2926 rdev->family == CHIP_RV410) { 2927 /* r4xx */ 2928 mem_trcd = (temp & 0xf) + 3; 2929 if (mem_trcd > 15) 2930 mem_trcd = 15; 2931 mem_trp = ((temp >> 8) & 0xf) + 3; 2932 if (mem_trp > 15) 2933 mem_trp = 15; 2934 mem_tras = ((temp >> 12) & 0x1f) + 6; 2935 if (mem_tras > 31) 2936 mem_tras = 31; 2937 } else { /* RV200, R200 */ 2938 mem_trcd = (temp & 0x7) + 1; 2939 mem_trp = ((temp >> 8) & 0x7) + 1; 2940 mem_tras = ((temp >> 12) & 0xf) + 4; 2941 } 2942 /* convert to FF */ 2943 trcd_ff.full = dfixed_const(mem_trcd); 2944 trp_ff.full = dfixed_const(mem_trp); 2945 tras_ff.full = dfixed_const(mem_tras); 2946 2947 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */ 2948 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG); 2949 data = (temp & (7 << 20)) >> 20; 2950 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) { 2951 if (rdev->family == CHIP_RS480) /* don't think rs400 */ 2952 tcas_ff = memtcas_rs480_ff[data]; 2953 else 2954 tcas_ff = memtcas_ff[data]; 2955 } else 2956 tcas_ff = memtcas2_ff[data]; 2957 2958 if (rdev->family == CHIP_RS400 || 2959 rdev->family == CHIP_RS480) { 2960 /* extra cas latency stored in bits 23-25 0-4 clocks */ 2961 data = (temp >> 23) & 0x7; 2962 if (data < 5) 2963 tcas_ff.full += dfixed_const(data); 2964 } 2965 2966 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) { 2967 /* on the R300, Tcas is included in Trbs. 2968 */ 2969 temp = RREG32(RADEON_MEM_CNTL); 2970 data = (R300_MEM_NUM_CHANNELS_MASK & temp); 2971 if (data == 1) { 2972 if (R300_MEM_USE_CD_CH_ONLY & temp) { 2973 temp = RREG32(R300_MC_IND_INDEX); 2974 temp &= ~R300_MC_IND_ADDR_MASK; 2975 temp |= R300_MC_READ_CNTL_CD_mcind; 2976 WREG32(R300_MC_IND_INDEX, temp); 2977 temp = RREG32(R300_MC_IND_DATA); 2978 data = (R300_MEM_RBS_POSITION_C_MASK & temp); 2979 } else { 2980 temp = RREG32(R300_MC_READ_CNTL_AB); 2981 data = (R300_MEM_RBS_POSITION_A_MASK & temp); 2982 } 2983 } else { 2984 temp = RREG32(R300_MC_READ_CNTL_AB); 2985 data = (R300_MEM_RBS_POSITION_A_MASK & temp); 2986 } 2987 if (rdev->family == CHIP_RV410 || 2988 rdev->family == CHIP_R420 || 2989 rdev->family == CHIP_R423) 2990 trbs_ff = memtrbs_r4xx[data]; 2991 else 2992 trbs_ff = memtrbs[data]; 2993 tcas_ff.full += trbs_ff.full; 2994 } 2995 2996 sclk_eff_ff.full = sclk_ff.full; 2997 2998 if (rdev->flags & RADEON_IS_AGP) { 2999 fixed20_12 agpmode_ff; 3000 agpmode_ff.full = dfixed_const(radeon_agpmode); 3001 temp_ff.full = dfixed_const_666(16); 3002 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff); 3003 } 3004 /* TODO PCIE lanes may affect this - agpmode == 16?? */ 3005 3006 if (ASIC_IS_R300(rdev)) { 3007 sclk_delay_ff.full = dfixed_const(250); 3008 } else { 3009 if ((rdev->family == CHIP_RV100) || 3010 rdev->flags & RADEON_IS_IGP) { 3011 if (rdev->mc.vram_is_ddr) 3012 sclk_delay_ff.full = dfixed_const(41); 3013 else 3014 sclk_delay_ff.full = dfixed_const(33); 3015 } else { 3016 if (rdev->mc.vram_width == 128) 3017 sclk_delay_ff.full = dfixed_const(57); 3018 else 3019 sclk_delay_ff.full = dfixed_const(41); 3020 } 3021 } 3022 3023 mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff); 3024 3025 if (rdev->mc.vram_is_ddr) { 3026 if (rdev->mc.vram_width == 32) { 3027 k1.full = dfixed_const(40); 3028 c = 3; 3029 } else { 3030 k1.full = dfixed_const(20); 3031 c = 1; 3032 } 3033 } else { 3034 k1.full = dfixed_const(40); 3035 c = 3; 3036 } 3037 3038 temp_ff.full = dfixed_const(2); 3039 mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff); 3040 temp_ff.full = dfixed_const(c); 3041 mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff); 3042 temp_ff.full = dfixed_const(4); 3043 mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff); 3044 mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff); 3045 mc_latency_mclk.full += k1.full; 3046 3047 mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff); 3048 mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff); 3049 3050 /* 3051 HW cursor time assuming worst case of full size colour cursor. 3052 */ 3053 temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1)))); 3054 temp_ff.full += trcd_ff.full; 3055 if (temp_ff.full < tras_ff.full) 3056 temp_ff.full = tras_ff.full; 3057 cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff); 3058 3059 temp_ff.full = dfixed_const(cur_size); 3060 cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff); 3061 /* 3062 Find the total latency for the display data. 3063 */ 3064 disp_latency_overhead.full = dfixed_const(8); 3065 disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff); 3066 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full; 3067 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full; 3068 3069 if (mc_latency_mclk.full > mc_latency_sclk.full) 3070 disp_latency.full = mc_latency_mclk.full; 3071 else 3072 disp_latency.full = mc_latency_sclk.full; 3073 3074 /* setup Max GRPH_STOP_REQ default value */ 3075 if (ASIC_IS_RV100(rdev)) 3076 max_stop_req = 0x5c; 3077 else 3078 max_stop_req = 0x7c; 3079 3080 if (mode1) { 3081 /* CRTC1 3082 Set GRPH_BUFFER_CNTL register using h/w defined optimal values. 3083 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ] 3084 */ 3085 stop_req = mode1->hdisplay * pixel_bytes1 / 16; 3086 3087 if (stop_req > max_stop_req) 3088 stop_req = max_stop_req; 3089 3090 /* 3091 Find the drain rate of the display buffer. 3092 */ 3093 temp_ff.full = dfixed_const((16/pixel_bytes1)); 3094 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff); 3095 3096 /* 3097 Find the critical point of the display buffer. 3098 */ 3099 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency); 3100 crit_point_ff.full += dfixed_const_half(0); 3101 3102 critical_point = dfixed_trunc(crit_point_ff); 3103 3104 if (rdev->disp_priority == 2) { 3105 critical_point = 0; 3106 } 3107 3108 /* 3109 The critical point should never be above max_stop_req-4. Setting 3110 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time. 3111 */ 3112 if (max_stop_req - critical_point < 4) 3113 critical_point = 0; 3114 3115 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) { 3116 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/ 3117 critical_point = 0x10; 3118 } 3119 3120 temp = RREG32(RADEON_GRPH_BUFFER_CNTL); 3121 temp &= ~(RADEON_GRPH_STOP_REQ_MASK); 3122 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); 3123 temp &= ~(RADEON_GRPH_START_REQ_MASK); 3124 if ((rdev->family == CHIP_R350) && 3125 (stop_req > 0x15)) { 3126 stop_req -= 0x10; 3127 } 3128 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); 3129 temp |= RADEON_GRPH_BUFFER_SIZE; 3130 temp &= ~(RADEON_GRPH_CRITICAL_CNTL | 3131 RADEON_GRPH_CRITICAL_AT_SOF | 3132 RADEON_GRPH_STOP_CNTL); 3133 /* 3134 Write the result into the register. 3135 */ 3136 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) | 3137 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT))); 3138 3139 #if 0 3140 if ((rdev->family == CHIP_RS400) || 3141 (rdev->family == CHIP_RS480)) { 3142 /* attempt to program RS400 disp regs correctly ??? */ 3143 temp = RREG32(RS400_DISP1_REG_CNTL); 3144 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK | 3145 RS400_DISP1_STOP_REQ_LEVEL_MASK); 3146 WREG32(RS400_DISP1_REQ_CNTL1, (temp | 3147 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) | 3148 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); 3149 temp = RREG32(RS400_DMIF_MEM_CNTL1); 3150 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK | 3151 RS400_DISP1_CRITICAL_POINT_STOP_MASK); 3152 WREG32(RS400_DMIF_MEM_CNTL1, (temp | 3153 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) | 3154 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT))); 3155 } 3156 #endif 3157 3158 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n", 3159 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */ 3160 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL)); 3161 } 3162 3163 if (mode2) { 3164 u32 grph2_cntl; 3165 stop_req = mode2->hdisplay * pixel_bytes2 / 16; 3166 3167 if (stop_req > max_stop_req) 3168 stop_req = max_stop_req; 3169 3170 /* 3171 Find the drain rate of the display buffer. 3172 */ 3173 temp_ff.full = dfixed_const((16/pixel_bytes2)); 3174 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff); 3175 3176 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL); 3177 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK); 3178 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); 3179 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK); 3180 if ((rdev->family == CHIP_R350) && 3181 (stop_req > 0x15)) { 3182 stop_req -= 0x10; 3183 } 3184 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); 3185 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE; 3186 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL | 3187 RADEON_GRPH_CRITICAL_AT_SOF | 3188 RADEON_GRPH_STOP_CNTL); 3189 3190 if ((rdev->family == CHIP_RS100) || 3191 (rdev->family == CHIP_RS200)) 3192 critical_point2 = 0; 3193 else { 3194 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128; 3195 temp_ff.full = dfixed_const(temp); 3196 temp_ff.full = dfixed_mul(mclk_ff, temp_ff); 3197 if (sclk_ff.full < temp_ff.full) 3198 temp_ff.full = sclk_ff.full; 3199 3200 read_return_rate.full = temp_ff.full; 3201 3202 if (mode1) { 3203 temp_ff.full = read_return_rate.full - disp_drain_rate.full; 3204 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff); 3205 } else { 3206 time_disp1_drop_priority.full = 0; 3207 } 3208 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full; 3209 crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2); 3210 crit_point_ff.full += dfixed_const_half(0); 3211 3212 critical_point2 = dfixed_trunc(crit_point_ff); 3213 3214 if (rdev->disp_priority == 2) { 3215 critical_point2 = 0; 3216 } 3217 3218 if (max_stop_req - critical_point2 < 4) 3219 critical_point2 = 0; 3220 3221 } 3222 3223 if (critical_point2 == 0 && rdev->family == CHIP_R300) { 3224 /* some R300 cards have problem with this set to 0 */ 3225 critical_point2 = 0x10; 3226 } 3227 3228 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) | 3229 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT))); 3230 3231 if ((rdev->family == CHIP_RS400) || 3232 (rdev->family == CHIP_RS480)) { 3233 #if 0 3234 /* attempt to program RS400 disp2 regs correctly ??? */ 3235 temp = RREG32(RS400_DISP2_REQ_CNTL1); 3236 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK | 3237 RS400_DISP2_STOP_REQ_LEVEL_MASK); 3238 WREG32(RS400_DISP2_REQ_CNTL1, (temp | 3239 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) | 3240 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); 3241 temp = RREG32(RS400_DISP2_REQ_CNTL2); 3242 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK | 3243 RS400_DISP2_CRITICAL_POINT_STOP_MASK); 3244 WREG32(RS400_DISP2_REQ_CNTL2, (temp | 3245 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) | 3246 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT))); 3247 #endif 3248 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC); 3249 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000); 3250 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC); 3251 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC); 3252 } 3253 3254 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n", 3255 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL)); 3256 } 3257 } 3258 3259 static void r100_cs_track_texture_print(struct r100_cs_track_texture *t) 3260 { 3261 DRM_ERROR("pitch %d\n", t->pitch); 3262 DRM_ERROR("use_pitch %d\n", t->use_pitch); 3263 DRM_ERROR("width %d\n", t->width); 3264 DRM_ERROR("width_11 %d\n", t->width_11); 3265 DRM_ERROR("height %d\n", t->height); 3266 DRM_ERROR("height_11 %d\n", t->height_11); 3267 DRM_ERROR("num levels %d\n", t->num_levels); 3268 DRM_ERROR("depth %d\n", t->txdepth); 3269 DRM_ERROR("bpp %d\n", t->cpp); 3270 DRM_ERROR("coordinate type %d\n", t->tex_coord_type); 3271 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w); 3272 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h); 3273 DRM_ERROR("compress format %d\n", t->compress_format); 3274 } 3275 3276 static int r100_track_compress_size(int compress_format, int w, int h) 3277 { 3278 int block_width, block_height, block_bytes; 3279 int wblocks, hblocks; 3280 int min_wblocks; 3281 int sz; 3282 3283 block_width = 4; 3284 block_height = 4; 3285 3286 switch (compress_format) { 3287 case R100_TRACK_COMP_DXT1: 3288 block_bytes = 8; 3289 min_wblocks = 4; 3290 break; 3291 default: 3292 case R100_TRACK_COMP_DXT35: 3293 block_bytes = 16; 3294 min_wblocks = 2; 3295 break; 3296 } 3297 3298 hblocks = (h + block_height - 1) / block_height; 3299 wblocks = (w + block_width - 1) / block_width; 3300 if (wblocks < min_wblocks) 3301 wblocks = min_wblocks; 3302 sz = wblocks * hblocks * block_bytes; 3303 return sz; 3304 } 3305 3306 static int r100_cs_track_cube(struct radeon_device *rdev, 3307 struct r100_cs_track *track, unsigned idx) 3308 { 3309 unsigned face, w, h; 3310 struct radeon_bo *cube_robj; 3311 unsigned long size; 3312 unsigned compress_format = track->textures[idx].compress_format; 3313 3314 for (face = 0; face < 5; face++) { 3315 cube_robj = track->textures[idx].cube_info[face].robj; 3316 w = track->textures[idx].cube_info[face].width; 3317 h = track->textures[idx].cube_info[face].height; 3318 3319 if (compress_format) { 3320 size = r100_track_compress_size(compress_format, w, h); 3321 } else 3322 size = w * h; 3323 size *= track->textures[idx].cpp; 3324 3325 size += track->textures[idx].cube_info[face].offset; 3326 3327 if (size > radeon_bo_size(cube_robj)) { 3328 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n", 3329 size, radeon_bo_size(cube_robj)); 3330 r100_cs_track_texture_print(&track->textures[idx]); 3331 return -1; 3332 } 3333 } 3334 return 0; 3335 } 3336 3337 static int r100_cs_track_texture_check(struct radeon_device *rdev, 3338 struct r100_cs_track *track) 3339 { 3340 struct radeon_bo *robj; 3341 unsigned long size; 3342 unsigned u, i, w, h, d; 3343 int ret; 3344 3345 for (u = 0; u < track->num_texture; u++) { 3346 if (!track->textures[u].enabled) 3347 continue; 3348 if (track->textures[u].lookup_disable) 3349 continue; 3350 robj = track->textures[u].robj; 3351 if (robj == NULL) { 3352 DRM_ERROR("No texture bound to unit %u\n", u); 3353 return -EINVAL; 3354 } 3355 size = 0; 3356 for (i = 0; i <= track->textures[u].num_levels; i++) { 3357 if (track->textures[u].use_pitch) { 3358 if (rdev->family < CHIP_R300) 3359 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i); 3360 else 3361 w = track->textures[u].pitch / (1 << i); 3362 } else { 3363 w = track->textures[u].width; 3364 if (rdev->family >= CHIP_RV515) 3365 w |= track->textures[u].width_11; 3366 w = w / (1 << i); 3367 if (track->textures[u].roundup_w) 3368 w = roundup_pow_of_two(w); 3369 } 3370 h = track->textures[u].height; 3371 if (rdev->family >= CHIP_RV515) 3372 h |= track->textures[u].height_11; 3373 h = h / (1 << i); 3374 if (track->textures[u].roundup_h) 3375 h = roundup_pow_of_two(h); 3376 if (track->textures[u].tex_coord_type == 1) { 3377 d = (1 << track->textures[u].txdepth) / (1 << i); 3378 if (!d) 3379 d = 1; 3380 } else { 3381 d = 1; 3382 } 3383 if (track->textures[u].compress_format) { 3384 3385 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d; 3386 /* compressed textures are block based */ 3387 } else 3388 size += w * h * d; 3389 } 3390 size *= track->textures[u].cpp; 3391 3392 switch (track->textures[u].tex_coord_type) { 3393 case 0: 3394 case 1: 3395 break; 3396 case 2: 3397 if (track->separate_cube) { 3398 ret = r100_cs_track_cube(rdev, track, u); 3399 if (ret) 3400 return ret; 3401 } else 3402 size *= 6; 3403 break; 3404 default: 3405 DRM_ERROR("Invalid texture coordinate type %u for unit " 3406 "%u\n", track->textures[u].tex_coord_type, u); 3407 return -EINVAL; 3408 } 3409 if (size > radeon_bo_size(robj)) { 3410 DRM_ERROR("Texture of unit %u needs %lu bytes but is " 3411 "%lu\n", u, size, radeon_bo_size(robj)); 3412 r100_cs_track_texture_print(&track->textures[u]); 3413 return -EINVAL; 3414 } 3415 } 3416 return 0; 3417 } 3418 3419 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track) 3420 { 3421 unsigned i; 3422 unsigned long size; 3423 unsigned prim_walk; 3424 unsigned nverts; 3425 unsigned num_cb = track->cb_dirty ? track->num_cb : 0; 3426 3427 if (num_cb && !track->zb_cb_clear && !track->color_channel_mask && 3428 !track->blend_read_enable) 3429 num_cb = 0; 3430 3431 for (i = 0; i < num_cb; i++) { 3432 if (track->cb[i].robj == NULL) { 3433 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i); 3434 return -EINVAL; 3435 } 3436 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy; 3437 size += track->cb[i].offset; 3438 if (size > radeon_bo_size(track->cb[i].robj)) { 3439 DRM_ERROR("[drm] Buffer too small for color buffer %d " 3440 "(need %lu have %lu) !\n", i, size, 3441 radeon_bo_size(track->cb[i].robj)); 3442 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n", 3443 i, track->cb[i].pitch, track->cb[i].cpp, 3444 track->cb[i].offset, track->maxy); 3445 return -EINVAL; 3446 } 3447 } 3448 track->cb_dirty = false; 3449 3450 if (track->zb_dirty && track->z_enabled) { 3451 if (track->zb.robj == NULL) { 3452 DRM_ERROR("[drm] No buffer for z buffer !\n"); 3453 return -EINVAL; 3454 } 3455 size = track->zb.pitch * track->zb.cpp * track->maxy; 3456 size += track->zb.offset; 3457 if (size > radeon_bo_size(track->zb.robj)) { 3458 DRM_ERROR("[drm] Buffer too small for z buffer " 3459 "(need %lu have %lu) !\n", size, 3460 radeon_bo_size(track->zb.robj)); 3461 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n", 3462 track->zb.pitch, track->zb.cpp, 3463 track->zb.offset, track->maxy); 3464 return -EINVAL; 3465 } 3466 } 3467 track->zb_dirty = false; 3468 3469 if (track->aa_dirty && track->aaresolve) { 3470 if (track->aa.robj == NULL) { 3471 DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i); 3472 return -EINVAL; 3473 } 3474 /* I believe the format comes from colorbuffer0. */ 3475 size = track->aa.pitch * track->cb[0].cpp * track->maxy; 3476 size += track->aa.offset; 3477 if (size > radeon_bo_size(track->aa.robj)) { 3478 DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d " 3479 "(need %lu have %lu) !\n", i, size, 3480 radeon_bo_size(track->aa.robj)); 3481 DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n", 3482 i, track->aa.pitch, track->cb[0].cpp, 3483 track->aa.offset, track->maxy); 3484 return -EINVAL; 3485 } 3486 } 3487 track->aa_dirty = false; 3488 3489 prim_walk = (track->vap_vf_cntl >> 4) & 0x3; 3490 if (track->vap_vf_cntl & (1 << 14)) { 3491 nverts = track->vap_alt_nverts; 3492 } else { 3493 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF; 3494 } 3495 switch (prim_walk) { 3496 case 1: 3497 for (i = 0; i < track->num_arrays; i++) { 3498 size = track->arrays[i].esize * track->max_indx * 4; 3499 if (track->arrays[i].robj == NULL) { 3500 DRM_ERROR("(PW %u) Vertex array %u no buffer " 3501 "bound\n", prim_walk, i); 3502 return -EINVAL; 3503 } 3504 if (size > radeon_bo_size(track->arrays[i].robj)) { 3505 dev_err(rdev->dev, "(PW %u) Vertex array %u " 3506 "need %lu dwords have %lu dwords\n", 3507 prim_walk, i, size >> 2, 3508 radeon_bo_size(track->arrays[i].robj) 3509 >> 2); 3510 DRM_ERROR("Max indices %u\n", track->max_indx); 3511 return -EINVAL; 3512 } 3513 } 3514 break; 3515 case 2: 3516 for (i = 0; i < track->num_arrays; i++) { 3517 size = track->arrays[i].esize * (nverts - 1) * 4; 3518 if (track->arrays[i].robj == NULL) { 3519 DRM_ERROR("(PW %u) Vertex array %u no buffer " 3520 "bound\n", prim_walk, i); 3521 return -EINVAL; 3522 } 3523 if (size > radeon_bo_size(track->arrays[i].robj)) { 3524 dev_err(rdev->dev, "(PW %u) Vertex array %u " 3525 "need %lu dwords have %lu dwords\n", 3526 prim_walk, i, size >> 2, 3527 radeon_bo_size(track->arrays[i].robj) 3528 >> 2); 3529 return -EINVAL; 3530 } 3531 } 3532 break; 3533 case 3: 3534 size = track->vtx_size * nverts; 3535 if (size != track->immd_dwords) { 3536 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n", 3537 track->immd_dwords, size); 3538 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n", 3539 nverts, track->vtx_size); 3540 return -EINVAL; 3541 } 3542 break; 3543 default: 3544 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n", 3545 prim_walk); 3546 return -EINVAL; 3547 } 3548 3549 if (track->tex_dirty) { 3550 track->tex_dirty = false; 3551 return r100_cs_track_texture_check(rdev, track); 3552 } 3553 return 0; 3554 } 3555 3556 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track) 3557 { 3558 unsigned i, face; 3559 3560 track->cb_dirty = true; 3561 track->zb_dirty = true; 3562 track->tex_dirty = true; 3563 track->aa_dirty = true; 3564 3565 if (rdev->family < CHIP_R300) { 3566 track->num_cb = 1; 3567 if (rdev->family <= CHIP_RS200) 3568 track->num_texture = 3; 3569 else 3570 track->num_texture = 6; 3571 track->maxy = 2048; 3572 track->separate_cube = 1; 3573 } else { 3574 track->num_cb = 4; 3575 track->num_texture = 16; 3576 track->maxy = 4096; 3577 track->separate_cube = 0; 3578 track->aaresolve = false; 3579 track->aa.robj = NULL; 3580 } 3581 3582 for (i = 0; i < track->num_cb; i++) { 3583 track->cb[i].robj = NULL; 3584 track->cb[i].pitch = 8192; 3585 track->cb[i].cpp = 16; 3586 track->cb[i].offset = 0; 3587 } 3588 track->z_enabled = true; 3589 track->zb.robj = NULL; 3590 track->zb.pitch = 8192; 3591 track->zb.cpp = 4; 3592 track->zb.offset = 0; 3593 track->vtx_size = 0x7F; 3594 track->immd_dwords = 0xFFFFFFFFUL; 3595 track->num_arrays = 11; 3596 track->max_indx = 0x00FFFFFFUL; 3597 for (i = 0; i < track->num_arrays; i++) { 3598 track->arrays[i].robj = NULL; 3599 track->arrays[i].esize = 0x7F; 3600 } 3601 for (i = 0; i < track->num_texture; i++) { 3602 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 3603 track->textures[i].pitch = 16536; 3604 track->textures[i].width = 16536; 3605 track->textures[i].height = 16536; 3606 track->textures[i].width_11 = 1 << 11; 3607 track->textures[i].height_11 = 1 << 11; 3608 track->textures[i].num_levels = 12; 3609 if (rdev->family <= CHIP_RS200) { 3610 track->textures[i].tex_coord_type = 0; 3611 track->textures[i].txdepth = 0; 3612 } else { 3613 track->textures[i].txdepth = 16; 3614 track->textures[i].tex_coord_type = 1; 3615 } 3616 track->textures[i].cpp = 64; 3617 track->textures[i].robj = NULL; 3618 /* CS IB emission code makes sure texture unit are disabled */ 3619 track->textures[i].enabled = false; 3620 track->textures[i].lookup_disable = false; 3621 track->textures[i].roundup_w = true; 3622 track->textures[i].roundup_h = true; 3623 if (track->separate_cube) 3624 for (face = 0; face < 5; face++) { 3625 track->textures[i].cube_info[face].robj = NULL; 3626 track->textures[i].cube_info[face].width = 16536; 3627 track->textures[i].cube_info[face].height = 16536; 3628 track->textures[i].cube_info[face].offset = 0; 3629 } 3630 } 3631 } 3632 3633 int r100_ring_test(struct radeon_device *rdev) 3634 { 3635 uint32_t scratch; 3636 uint32_t tmp = 0; 3637 unsigned i; 3638 int r; 3639 3640 r = radeon_scratch_get(rdev, &scratch); 3641 if (r) { 3642 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); 3643 return r; 3644 } 3645 WREG32(scratch, 0xCAFEDEAD); 3646 r = radeon_ring_lock(rdev, 2); 3647 if (r) { 3648 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 3649 radeon_scratch_free(rdev, scratch); 3650 return r; 3651 } 3652 radeon_ring_write(rdev, PACKET0(scratch, 0)); 3653 radeon_ring_write(rdev, 0xDEADBEEF); 3654 radeon_ring_unlock_commit(rdev); 3655 for (i = 0; i < rdev->usec_timeout; i++) { 3656 tmp = RREG32(scratch); 3657 if (tmp == 0xDEADBEEF) { 3658 break; 3659 } 3660 DRM_UDELAY(1); 3661 } 3662 if (i < rdev->usec_timeout) { 3663 DRM_INFO("ring test succeeded in %d usecs\n", i); 3664 } else { 3665 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n", 3666 scratch, tmp); 3667 r = -EINVAL; 3668 } 3669 radeon_scratch_free(rdev, scratch); 3670 return r; 3671 } 3672 3673 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 3674 { 3675 radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1)); 3676 radeon_ring_write(rdev, ib->gpu_addr); 3677 radeon_ring_write(rdev, ib->length_dw); 3678 } 3679 3680 int r100_ib_test(struct radeon_device *rdev) 3681 { 3682 struct radeon_ib *ib; 3683 uint32_t scratch; 3684 uint32_t tmp = 0; 3685 unsigned i; 3686 int r; 3687 3688 r = radeon_scratch_get(rdev, &scratch); 3689 if (r) { 3690 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); 3691 return r; 3692 } 3693 WREG32(scratch, 0xCAFEDEAD); 3694 r = radeon_ib_get(rdev, &ib); 3695 if (r) { 3696 return r; 3697 } 3698 ib->ptr[0] = PACKET0(scratch, 0); 3699 ib->ptr[1] = 0xDEADBEEF; 3700 ib->ptr[2] = PACKET2(0); 3701 ib->ptr[3] = PACKET2(0); 3702 ib->ptr[4] = PACKET2(0); 3703 ib->ptr[5] = PACKET2(0); 3704 ib->ptr[6] = PACKET2(0); 3705 ib->ptr[7] = PACKET2(0); 3706 ib->length_dw = 8; 3707 r = radeon_ib_schedule(rdev, ib); 3708 if (r) { 3709 radeon_scratch_free(rdev, scratch); 3710 radeon_ib_free(rdev, &ib); 3711 return r; 3712 } 3713 r = radeon_fence_wait(ib->fence, false); 3714 if (r) { 3715 return r; 3716 } 3717 for (i = 0; i < rdev->usec_timeout; i++) { 3718 tmp = RREG32(scratch); 3719 if (tmp == 0xDEADBEEF) { 3720 break; 3721 } 3722 DRM_UDELAY(1); 3723 } 3724 if (i < rdev->usec_timeout) { 3725 DRM_INFO("ib test succeeded in %u usecs\n", i); 3726 } else { 3727 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n", 3728 scratch, tmp); 3729 r = -EINVAL; 3730 } 3731 radeon_scratch_free(rdev, scratch); 3732 radeon_ib_free(rdev, &ib); 3733 return r; 3734 } 3735 3736 void r100_ib_fini(struct radeon_device *rdev) 3737 { 3738 radeon_ib_pool_fini(rdev); 3739 } 3740 3741 int r100_ib_init(struct radeon_device *rdev) 3742 { 3743 int r; 3744 3745 r = radeon_ib_pool_init(rdev); 3746 if (r) { 3747 dev_err(rdev->dev, "failed initializing IB pool (%d).\n", r); 3748 r100_ib_fini(rdev); 3749 return r; 3750 } 3751 r = r100_ib_test(rdev); 3752 if (r) { 3753 dev_err(rdev->dev, "failed testing IB (%d).\n", r); 3754 r100_ib_fini(rdev); 3755 return r; 3756 } 3757 return 0; 3758 } 3759 3760 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save) 3761 { 3762 /* Shutdown CP we shouldn't need to do that but better be safe than 3763 * sorry 3764 */ 3765 rdev->cp.ready = false; 3766 WREG32(R_000740_CP_CSQ_CNTL, 0); 3767 3768 /* Save few CRTC registers */ 3769 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT); 3770 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL); 3771 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL); 3772 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET); 3773 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3774 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL); 3775 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET); 3776 } 3777 3778 /* Disable VGA aperture access */ 3779 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT); 3780 /* Disable cursor, overlay, crtc */ 3781 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1)); 3782 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL | 3783 S_000054_CRTC_DISPLAY_DIS(1)); 3784 WREG32(R_000050_CRTC_GEN_CNTL, 3785 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) | 3786 S_000050_CRTC_DISP_REQ_EN_B(1)); 3787 WREG32(R_000420_OV0_SCALE_CNTL, 3788 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL)); 3789 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET); 3790 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3791 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET | 3792 S_000360_CUR2_LOCK(1)); 3793 WREG32(R_0003F8_CRTC2_GEN_CNTL, 3794 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) | 3795 S_0003F8_CRTC2_DISPLAY_DIS(1) | 3796 S_0003F8_CRTC2_DISP_REQ_EN_B(1)); 3797 WREG32(R_000360_CUR2_OFFSET, 3798 C_000360_CUR2_LOCK & save->CUR2_OFFSET); 3799 } 3800 } 3801 3802 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save) 3803 { 3804 /* Update base address for crtc */ 3805 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start); 3806 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3807 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start); 3808 } 3809 /* Restore CRTC registers */ 3810 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT); 3811 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL); 3812 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL); 3813 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3814 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL); 3815 } 3816 } 3817 3818 void r100_vga_render_disable(struct radeon_device *rdev) 3819 { 3820 u32 tmp; 3821 3822 tmp = RREG8(R_0003C2_GENMO_WT); 3823 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp); 3824 } 3825 3826 static void r100_debugfs(struct radeon_device *rdev) 3827 { 3828 int r; 3829 3830 r = r100_debugfs_mc_info_init(rdev); 3831 if (r) 3832 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n"); 3833 } 3834 3835 static void r100_mc_program(struct radeon_device *rdev) 3836 { 3837 struct r100_mc_save save; 3838 3839 /* Stops all mc clients */ 3840 r100_mc_stop(rdev, &save); 3841 if (rdev->flags & RADEON_IS_AGP) { 3842 WREG32(R_00014C_MC_AGP_LOCATION, 3843 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) | 3844 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); 3845 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); 3846 if (rdev->family > CHIP_RV200) 3847 WREG32(R_00015C_AGP_BASE_2, 3848 upper_32_bits(rdev->mc.agp_base) & 0xff); 3849 } else { 3850 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF); 3851 WREG32(R_000170_AGP_BASE, 0); 3852 if (rdev->family > CHIP_RV200) 3853 WREG32(R_00015C_AGP_BASE_2, 0); 3854 } 3855 /* Wait for mc idle */ 3856 if (r100_mc_wait_for_idle(rdev)) 3857 dev_warn(rdev->dev, "Wait for MC idle timeout.\n"); 3858 /* Program MC, should be a 32bits limited address space */ 3859 WREG32(R_000148_MC_FB_LOCATION, 3860 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | 3861 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); 3862 r100_mc_resume(rdev, &save); 3863 } 3864 3865 void r100_clock_startup(struct radeon_device *rdev) 3866 { 3867 u32 tmp; 3868 3869 if (radeon_dynclks != -1 && radeon_dynclks) 3870 radeon_legacy_set_clock_gating(rdev, 1); 3871 /* We need to force on some of the block */ 3872 tmp = RREG32_PLL(R_00000D_SCLK_CNTL); 3873 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); 3874 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280)) 3875 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1); 3876 WREG32_PLL(R_00000D_SCLK_CNTL, tmp); 3877 } 3878 3879 static int r100_startup(struct radeon_device *rdev) 3880 { 3881 int r; 3882 3883 /* set common regs */ 3884 r100_set_common_regs(rdev); 3885 /* program mc */ 3886 r100_mc_program(rdev); 3887 /* Resume clock */ 3888 r100_clock_startup(rdev); 3889 /* Initialize GART (initialize after TTM so we can allocate 3890 * memory through TTM but finalize after TTM) */ 3891 r100_enable_bm(rdev); 3892 if (rdev->flags & RADEON_IS_PCI) { 3893 r = r100_pci_gart_enable(rdev); 3894 if (r) 3895 return r; 3896 } 3897 3898 /* allocate wb buffer */ 3899 r = radeon_wb_init(rdev); 3900 if (r) 3901 return r; 3902 3903 /* Enable IRQ */ 3904 r100_irq_set(rdev); 3905 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 3906 /* 1M ring buffer */ 3907 r = r100_cp_init(rdev, 1024 * 1024); 3908 if (r) { 3909 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 3910 return r; 3911 } 3912 r = r100_ib_init(rdev); 3913 if (r) { 3914 dev_err(rdev->dev, "failed initializing IB (%d).\n", r); 3915 return r; 3916 } 3917 return 0; 3918 } 3919 3920 int r100_resume(struct radeon_device *rdev) 3921 { 3922 /* Make sur GART are not working */ 3923 if (rdev->flags & RADEON_IS_PCI) 3924 r100_pci_gart_disable(rdev); 3925 /* Resume clock before doing reset */ 3926 r100_clock_startup(rdev); 3927 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 3928 if (radeon_asic_reset(rdev)) { 3929 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 3930 RREG32(R_000E40_RBBM_STATUS), 3931 RREG32(R_0007C0_CP_STAT)); 3932 } 3933 /* post */ 3934 radeon_combios_asic_init(rdev->ddev); 3935 /* Resume clock after posting */ 3936 r100_clock_startup(rdev); 3937 /* Initialize surface registers */ 3938 radeon_surface_init(rdev); 3939 return r100_startup(rdev); 3940 } 3941 3942 int r100_suspend(struct radeon_device *rdev) 3943 { 3944 r100_cp_disable(rdev); 3945 radeon_wb_disable(rdev); 3946 r100_irq_disable(rdev); 3947 if (rdev->flags & RADEON_IS_PCI) 3948 r100_pci_gart_disable(rdev); 3949 return 0; 3950 } 3951 3952 void r100_fini(struct radeon_device *rdev) 3953 { 3954 r100_cp_fini(rdev); 3955 radeon_wb_fini(rdev); 3956 r100_ib_fini(rdev); 3957 radeon_gem_fini(rdev); 3958 if (rdev->flags & RADEON_IS_PCI) 3959 r100_pci_gart_fini(rdev); 3960 radeon_agp_fini(rdev); 3961 radeon_irq_kms_fini(rdev); 3962 radeon_fence_driver_fini(rdev); 3963 radeon_bo_fini(rdev); 3964 radeon_atombios_fini(rdev); 3965 kfree(rdev->bios); 3966 rdev->bios = NULL; 3967 } 3968 3969 /* 3970 * Due to how kexec works, it can leave the hw fully initialised when it 3971 * boots the new kernel. However doing our init sequence with the CP and 3972 * WB stuff setup causes GPU hangs on the RN50 at least. So at startup 3973 * do some quick sanity checks and restore sane values to avoid this 3974 * problem. 3975 */ 3976 void r100_restore_sanity(struct radeon_device *rdev) 3977 { 3978 u32 tmp; 3979 3980 tmp = RREG32(RADEON_CP_CSQ_CNTL); 3981 if (tmp) { 3982 WREG32(RADEON_CP_CSQ_CNTL, 0); 3983 } 3984 tmp = RREG32(RADEON_CP_RB_CNTL); 3985 if (tmp) { 3986 WREG32(RADEON_CP_RB_CNTL, 0); 3987 } 3988 tmp = RREG32(RADEON_SCRATCH_UMSK); 3989 if (tmp) { 3990 WREG32(RADEON_SCRATCH_UMSK, 0); 3991 } 3992 } 3993 3994 int r100_init(struct radeon_device *rdev) 3995 { 3996 int r; 3997 3998 /* Register debugfs file specific to this group of asics */ 3999 r100_debugfs(rdev); 4000 /* Disable VGA */ 4001 r100_vga_render_disable(rdev); 4002 /* Initialize scratch registers */ 4003 radeon_scratch_init(rdev); 4004 /* Initialize surface registers */ 4005 radeon_surface_init(rdev); 4006 /* sanity check some register to avoid hangs like after kexec */ 4007 r100_restore_sanity(rdev); 4008 /* TODO: disable VGA need to use VGA request */ 4009 /* BIOS*/ 4010 if (!radeon_get_bios(rdev)) { 4011 if (ASIC_IS_AVIVO(rdev)) 4012 return -EINVAL; 4013 } 4014 if (rdev->is_atom_bios) { 4015 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); 4016 return -EINVAL; 4017 } else { 4018 r = radeon_combios_init(rdev); 4019 if (r) 4020 return r; 4021 } 4022 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 4023 if (radeon_asic_reset(rdev)) { 4024 dev_warn(rdev->dev, 4025 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 4026 RREG32(R_000E40_RBBM_STATUS), 4027 RREG32(R_0007C0_CP_STAT)); 4028 } 4029 /* check if cards are posted or not */ 4030 if (radeon_boot_test_post_card(rdev) == false) 4031 return -EINVAL; 4032 /* Set asic errata */ 4033 r100_errata(rdev); 4034 /* Initialize clocks */ 4035 radeon_get_clock_info(rdev->ddev); 4036 /* initialize AGP */ 4037 if (rdev->flags & RADEON_IS_AGP) { 4038 r = radeon_agp_init(rdev); 4039 if (r) { 4040 radeon_agp_disable(rdev); 4041 } 4042 } 4043 /* initialize VRAM */ 4044 r100_mc_init(rdev); 4045 /* Fence driver */ 4046 r = radeon_fence_driver_init(rdev); 4047 if (r) 4048 return r; 4049 r = radeon_irq_kms_init(rdev); 4050 if (r) 4051 return r; 4052 /* Memory manager */ 4053 r = radeon_bo_init(rdev); 4054 if (r) 4055 return r; 4056 if (rdev->flags & RADEON_IS_PCI) { 4057 r = r100_pci_gart_init(rdev); 4058 if (r) 4059 return r; 4060 } 4061 r100_set_safe_registers(rdev); 4062 rdev->accel_working = true; 4063 r = r100_startup(rdev); 4064 if (r) { 4065 /* Somethings want wront with the accel init stop accel */ 4066 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 4067 r100_cp_fini(rdev); 4068 radeon_wb_fini(rdev); 4069 r100_ib_fini(rdev); 4070 radeon_irq_kms_fini(rdev); 4071 if (rdev->flags & RADEON_IS_PCI) 4072 r100_pci_gart_fini(rdev); 4073 rdev->accel_working = false; 4074 } 4075 return 0; 4076 } 4077 4078 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg) 4079 { 4080 if (reg < rdev->rmmio_size) 4081 return readl(((void __iomem *)rdev->rmmio) + reg); 4082 else { 4083 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); 4084 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); 4085 } 4086 } 4087 4088 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 4089 { 4090 if (reg < rdev->rmmio_size) 4091 writel(v, ((void __iomem *)rdev->rmmio) + reg); 4092 else { 4093 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); 4094 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); 4095 } 4096 } 4097 4098 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg) 4099 { 4100 if (reg < rdev->rio_mem_size) 4101 return ioread32(rdev->rio_mem + reg); 4102 else { 4103 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX); 4104 return ioread32(rdev->rio_mem + RADEON_MM_DATA); 4105 } 4106 } 4107 4108 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v) 4109 { 4110 if (reg < rdev->rio_mem_size) 4111 iowrite32(v, rdev->rio_mem + reg); 4112 else { 4113 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX); 4114 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA); 4115 } 4116 } 4117