1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/seq_file.h> 29 #include <linux/slab.h> 30 #include "drmP.h" 31 #include "drm.h" 32 #include "radeon_drm.h" 33 #include "radeon_reg.h" 34 #include "radeon.h" 35 #include "radeon_asic.h" 36 #include "r100d.h" 37 #include "rs100d.h" 38 #include "rv200d.h" 39 #include "rv250d.h" 40 #include "atom.h" 41 42 #include <linux/firmware.h> 43 #include <linux/platform_device.h> 44 #include <linux/module.h> 45 46 #include "r100_reg_safe.h" 47 #include "rn50_reg_safe.h" 48 49 /* Firmware Names */ 50 #define FIRMWARE_R100 "radeon/R100_cp.bin" 51 #define FIRMWARE_R200 "radeon/R200_cp.bin" 52 #define FIRMWARE_R300 "radeon/R300_cp.bin" 53 #define FIRMWARE_R420 "radeon/R420_cp.bin" 54 #define FIRMWARE_RS690 "radeon/RS690_cp.bin" 55 #define FIRMWARE_RS600 "radeon/RS600_cp.bin" 56 #define FIRMWARE_R520 "radeon/R520_cp.bin" 57 58 MODULE_FIRMWARE(FIRMWARE_R100); 59 MODULE_FIRMWARE(FIRMWARE_R200); 60 MODULE_FIRMWARE(FIRMWARE_R300); 61 MODULE_FIRMWARE(FIRMWARE_R420); 62 MODULE_FIRMWARE(FIRMWARE_RS690); 63 MODULE_FIRMWARE(FIRMWARE_RS600); 64 MODULE_FIRMWARE(FIRMWARE_R520); 65 66 #include "r100_track.h" 67 68 void r100_wait_for_vblank(struct radeon_device *rdev, int crtc) 69 { 70 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc]; 71 int i; 72 73 if (radeon_crtc->crtc_id == 0) { 74 if (RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN) { 75 for (i = 0; i < rdev->usec_timeout; i++) { 76 if (!(RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR)) 77 break; 78 udelay(1); 79 } 80 for (i = 0; i < rdev->usec_timeout; i++) { 81 if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR) 82 break; 83 udelay(1); 84 } 85 } 86 } else { 87 if (RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN) { 88 for (i = 0; i < rdev->usec_timeout; i++) { 89 if (!(RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR)) 90 break; 91 udelay(1); 92 } 93 for (i = 0; i < rdev->usec_timeout; i++) { 94 if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR) 95 break; 96 udelay(1); 97 } 98 } 99 } 100 } 101 102 /* This files gather functions specifics to: 103 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 104 */ 105 106 int r100_reloc_pitch_offset(struct radeon_cs_parser *p, 107 struct radeon_cs_packet *pkt, 108 unsigned idx, 109 unsigned reg) 110 { 111 int r; 112 u32 tile_flags = 0; 113 u32 tmp; 114 struct radeon_cs_reloc *reloc; 115 u32 value; 116 117 r = r100_cs_packet_next_reloc(p, &reloc); 118 if (r) { 119 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 120 idx, reg); 121 r100_cs_dump_packet(p, pkt); 122 return r; 123 } 124 125 value = radeon_get_ib_value(p, idx); 126 tmp = value & 0x003fffff; 127 tmp += (((u32)reloc->lobj.gpu_offset) >> 10); 128 129 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 130 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 131 tile_flags |= RADEON_DST_TILE_MACRO; 132 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) { 133 if (reg == RADEON_SRC_PITCH_OFFSET) { 134 DRM_ERROR("Cannot src blit from microtiled surface\n"); 135 r100_cs_dump_packet(p, pkt); 136 return -EINVAL; 137 } 138 tile_flags |= RADEON_DST_TILE_MICRO; 139 } 140 141 tmp |= tile_flags; 142 p->ib.ptr[idx] = (value & 0x3fc00000) | tmp; 143 } else 144 p->ib.ptr[idx] = (value & 0xffc00000) | tmp; 145 return 0; 146 } 147 148 int r100_packet3_load_vbpntr(struct radeon_cs_parser *p, 149 struct radeon_cs_packet *pkt, 150 int idx) 151 { 152 unsigned c, i; 153 struct radeon_cs_reloc *reloc; 154 struct r100_cs_track *track; 155 int r = 0; 156 volatile uint32_t *ib; 157 u32 idx_value; 158 159 ib = p->ib.ptr; 160 track = (struct r100_cs_track *)p->track; 161 c = radeon_get_ib_value(p, idx++) & 0x1F; 162 if (c > 16) { 163 DRM_ERROR("Only 16 vertex buffers are allowed %d\n", 164 pkt->opcode); 165 r100_cs_dump_packet(p, pkt); 166 return -EINVAL; 167 } 168 track->num_arrays = c; 169 for (i = 0; i < (c - 1); i+=2, idx+=3) { 170 r = r100_cs_packet_next_reloc(p, &reloc); 171 if (r) { 172 DRM_ERROR("No reloc for packet3 %d\n", 173 pkt->opcode); 174 r100_cs_dump_packet(p, pkt); 175 return r; 176 } 177 idx_value = radeon_get_ib_value(p, idx); 178 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset); 179 180 track->arrays[i + 0].esize = idx_value >> 8; 181 track->arrays[i + 0].robj = reloc->robj; 182 track->arrays[i + 0].esize &= 0x7F; 183 r = r100_cs_packet_next_reloc(p, &reloc); 184 if (r) { 185 DRM_ERROR("No reloc for packet3 %d\n", 186 pkt->opcode); 187 r100_cs_dump_packet(p, pkt); 188 return r; 189 } 190 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset); 191 track->arrays[i + 1].robj = reloc->robj; 192 track->arrays[i + 1].esize = idx_value >> 24; 193 track->arrays[i + 1].esize &= 0x7F; 194 } 195 if (c & 1) { 196 r = r100_cs_packet_next_reloc(p, &reloc); 197 if (r) { 198 DRM_ERROR("No reloc for packet3 %d\n", 199 pkt->opcode); 200 r100_cs_dump_packet(p, pkt); 201 return r; 202 } 203 idx_value = radeon_get_ib_value(p, idx); 204 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset); 205 track->arrays[i + 0].robj = reloc->robj; 206 track->arrays[i + 0].esize = idx_value >> 8; 207 track->arrays[i + 0].esize &= 0x7F; 208 } 209 return r; 210 } 211 212 void r100_pre_page_flip(struct radeon_device *rdev, int crtc) 213 { 214 /* enable the pflip int */ 215 radeon_irq_kms_pflip_irq_get(rdev, crtc); 216 } 217 218 void r100_post_page_flip(struct radeon_device *rdev, int crtc) 219 { 220 /* disable the pflip int */ 221 radeon_irq_kms_pflip_irq_put(rdev, crtc); 222 } 223 224 u32 r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) 225 { 226 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 227 u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK; 228 int i; 229 230 /* Lock the graphics update lock */ 231 /* update the scanout addresses */ 232 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); 233 234 /* Wait for update_pending to go high. */ 235 for (i = 0; i < rdev->usec_timeout; i++) { 236 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET) 237 break; 238 udelay(1); 239 } 240 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); 241 242 /* Unlock the lock, so double-buffering can take place inside vblank */ 243 tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK; 244 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); 245 246 /* Return current update_pending status: */ 247 return RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET; 248 } 249 250 void r100_pm_get_dynpm_state(struct radeon_device *rdev) 251 { 252 int i; 253 rdev->pm.dynpm_can_upclock = true; 254 rdev->pm.dynpm_can_downclock = true; 255 256 switch (rdev->pm.dynpm_planned_action) { 257 case DYNPM_ACTION_MINIMUM: 258 rdev->pm.requested_power_state_index = 0; 259 rdev->pm.dynpm_can_downclock = false; 260 break; 261 case DYNPM_ACTION_DOWNCLOCK: 262 if (rdev->pm.current_power_state_index == 0) { 263 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 264 rdev->pm.dynpm_can_downclock = false; 265 } else { 266 if (rdev->pm.active_crtc_count > 1) { 267 for (i = 0; i < rdev->pm.num_power_states; i++) { 268 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 269 continue; 270 else if (i >= rdev->pm.current_power_state_index) { 271 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 272 break; 273 } else { 274 rdev->pm.requested_power_state_index = i; 275 break; 276 } 277 } 278 } else 279 rdev->pm.requested_power_state_index = 280 rdev->pm.current_power_state_index - 1; 281 } 282 /* don't use the power state if crtcs are active and no display flag is set */ 283 if ((rdev->pm.active_crtc_count > 0) && 284 (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags & 285 RADEON_PM_MODE_NO_DISPLAY)) { 286 rdev->pm.requested_power_state_index++; 287 } 288 break; 289 case DYNPM_ACTION_UPCLOCK: 290 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) { 291 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 292 rdev->pm.dynpm_can_upclock = false; 293 } else { 294 if (rdev->pm.active_crtc_count > 1) { 295 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) { 296 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 297 continue; 298 else if (i <= rdev->pm.current_power_state_index) { 299 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 300 break; 301 } else { 302 rdev->pm.requested_power_state_index = i; 303 break; 304 } 305 } 306 } else 307 rdev->pm.requested_power_state_index = 308 rdev->pm.current_power_state_index + 1; 309 } 310 break; 311 case DYNPM_ACTION_DEFAULT: 312 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; 313 rdev->pm.dynpm_can_upclock = false; 314 break; 315 case DYNPM_ACTION_NONE: 316 default: 317 DRM_ERROR("Requested mode for not defined action\n"); 318 return; 319 } 320 /* only one clock mode per power state */ 321 rdev->pm.requested_clock_mode_index = 0; 322 323 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n", 324 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 325 clock_info[rdev->pm.requested_clock_mode_index].sclk, 326 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 327 clock_info[rdev->pm.requested_clock_mode_index].mclk, 328 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 329 pcie_lanes); 330 } 331 332 void r100_pm_init_profile(struct radeon_device *rdev) 333 { 334 /* default */ 335 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 336 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 337 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 338 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 339 /* low sh */ 340 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; 341 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; 342 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 343 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 344 /* mid sh */ 345 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; 346 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0; 347 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 348 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 349 /* high sh */ 350 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; 351 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 352 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 353 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 354 /* low mh */ 355 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; 356 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 357 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 358 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 359 /* mid mh */ 360 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; 361 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 362 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 363 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 364 /* high mh */ 365 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; 366 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 367 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 368 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 369 } 370 371 void r100_pm_misc(struct radeon_device *rdev) 372 { 373 int requested_index = rdev->pm.requested_power_state_index; 374 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index]; 375 struct radeon_voltage *voltage = &ps->clock_info[0].voltage; 376 u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl; 377 378 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) { 379 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) { 380 tmp = RREG32(voltage->gpio.reg); 381 if (voltage->active_high) 382 tmp |= voltage->gpio.mask; 383 else 384 tmp &= ~(voltage->gpio.mask); 385 WREG32(voltage->gpio.reg, tmp); 386 if (voltage->delay) 387 udelay(voltage->delay); 388 } else { 389 tmp = RREG32(voltage->gpio.reg); 390 if (voltage->active_high) 391 tmp &= ~voltage->gpio.mask; 392 else 393 tmp |= voltage->gpio.mask; 394 WREG32(voltage->gpio.reg, tmp); 395 if (voltage->delay) 396 udelay(voltage->delay); 397 } 398 } 399 400 sclk_cntl = RREG32_PLL(SCLK_CNTL); 401 sclk_cntl2 = RREG32_PLL(SCLK_CNTL2); 402 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3); 403 sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL); 404 sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3); 405 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) { 406 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN; 407 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE) 408 sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE; 409 else 410 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE; 411 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) 412 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0); 413 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) 414 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2); 415 } else 416 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN; 417 418 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) { 419 sclk_more_cntl |= IO_CG_VOLTAGE_DROP; 420 if (voltage->delay) { 421 sclk_more_cntl |= VOLTAGE_DROP_SYNC; 422 switch (voltage->delay) { 423 case 33: 424 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0); 425 break; 426 case 66: 427 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1); 428 break; 429 case 99: 430 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2); 431 break; 432 case 132: 433 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3); 434 break; 435 } 436 } else 437 sclk_more_cntl &= ~VOLTAGE_DROP_SYNC; 438 } else 439 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP; 440 441 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN) 442 sclk_cntl &= ~FORCE_HDP; 443 else 444 sclk_cntl |= FORCE_HDP; 445 446 WREG32_PLL(SCLK_CNTL, sclk_cntl); 447 WREG32_PLL(SCLK_CNTL2, sclk_cntl2); 448 WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl); 449 450 /* set pcie lanes */ 451 if ((rdev->flags & RADEON_IS_PCIE) && 452 !(rdev->flags & RADEON_IS_IGP) && 453 rdev->asic->pm.set_pcie_lanes && 454 (ps->pcie_lanes != 455 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) { 456 radeon_set_pcie_lanes(rdev, 457 ps->pcie_lanes); 458 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes); 459 } 460 } 461 462 void r100_pm_prepare(struct radeon_device *rdev) 463 { 464 struct drm_device *ddev = rdev->ddev; 465 struct drm_crtc *crtc; 466 struct radeon_crtc *radeon_crtc; 467 u32 tmp; 468 469 /* disable any active CRTCs */ 470 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { 471 radeon_crtc = to_radeon_crtc(crtc); 472 if (radeon_crtc->enabled) { 473 if (radeon_crtc->crtc_id) { 474 tmp = RREG32(RADEON_CRTC2_GEN_CNTL); 475 tmp |= RADEON_CRTC2_DISP_REQ_EN_B; 476 WREG32(RADEON_CRTC2_GEN_CNTL, tmp); 477 } else { 478 tmp = RREG32(RADEON_CRTC_GEN_CNTL); 479 tmp |= RADEON_CRTC_DISP_REQ_EN_B; 480 WREG32(RADEON_CRTC_GEN_CNTL, tmp); 481 } 482 } 483 } 484 } 485 486 void r100_pm_finish(struct radeon_device *rdev) 487 { 488 struct drm_device *ddev = rdev->ddev; 489 struct drm_crtc *crtc; 490 struct radeon_crtc *radeon_crtc; 491 u32 tmp; 492 493 /* enable any active CRTCs */ 494 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { 495 radeon_crtc = to_radeon_crtc(crtc); 496 if (radeon_crtc->enabled) { 497 if (radeon_crtc->crtc_id) { 498 tmp = RREG32(RADEON_CRTC2_GEN_CNTL); 499 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B; 500 WREG32(RADEON_CRTC2_GEN_CNTL, tmp); 501 } else { 502 tmp = RREG32(RADEON_CRTC_GEN_CNTL); 503 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B; 504 WREG32(RADEON_CRTC_GEN_CNTL, tmp); 505 } 506 } 507 } 508 } 509 510 bool r100_gui_idle(struct radeon_device *rdev) 511 { 512 if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE) 513 return false; 514 else 515 return true; 516 } 517 518 /* hpd for digital panel detect/disconnect */ 519 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) 520 { 521 bool connected = false; 522 523 switch (hpd) { 524 case RADEON_HPD_1: 525 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE) 526 connected = true; 527 break; 528 case RADEON_HPD_2: 529 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE) 530 connected = true; 531 break; 532 default: 533 break; 534 } 535 return connected; 536 } 537 538 void r100_hpd_set_polarity(struct radeon_device *rdev, 539 enum radeon_hpd_id hpd) 540 { 541 u32 tmp; 542 bool connected = r100_hpd_sense(rdev, hpd); 543 544 switch (hpd) { 545 case RADEON_HPD_1: 546 tmp = RREG32(RADEON_FP_GEN_CNTL); 547 if (connected) 548 tmp &= ~RADEON_FP_DETECT_INT_POL; 549 else 550 tmp |= RADEON_FP_DETECT_INT_POL; 551 WREG32(RADEON_FP_GEN_CNTL, tmp); 552 break; 553 case RADEON_HPD_2: 554 tmp = RREG32(RADEON_FP2_GEN_CNTL); 555 if (connected) 556 tmp &= ~RADEON_FP2_DETECT_INT_POL; 557 else 558 tmp |= RADEON_FP2_DETECT_INT_POL; 559 WREG32(RADEON_FP2_GEN_CNTL, tmp); 560 break; 561 default: 562 break; 563 } 564 } 565 566 void r100_hpd_init(struct radeon_device *rdev) 567 { 568 struct drm_device *dev = rdev->ddev; 569 struct drm_connector *connector; 570 571 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 572 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 573 switch (radeon_connector->hpd.hpd) { 574 case RADEON_HPD_1: 575 rdev->irq.hpd[0] = true; 576 break; 577 case RADEON_HPD_2: 578 rdev->irq.hpd[1] = true; 579 break; 580 default: 581 break; 582 } 583 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); 584 } 585 if (rdev->irq.installed) 586 r100_irq_set(rdev); 587 } 588 589 void r100_hpd_fini(struct radeon_device *rdev) 590 { 591 struct drm_device *dev = rdev->ddev; 592 struct drm_connector *connector; 593 594 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 595 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 596 switch (radeon_connector->hpd.hpd) { 597 case RADEON_HPD_1: 598 rdev->irq.hpd[0] = false; 599 break; 600 case RADEON_HPD_2: 601 rdev->irq.hpd[1] = false; 602 break; 603 default: 604 break; 605 } 606 } 607 } 608 609 /* 610 * PCI GART 611 */ 612 void r100_pci_gart_tlb_flush(struct radeon_device *rdev) 613 { 614 /* TODO: can we do somethings here ? */ 615 /* It seems hw only cache one entry so we should discard this 616 * entry otherwise if first GPU GART read hit this entry it 617 * could end up in wrong address. */ 618 } 619 620 int r100_pci_gart_init(struct radeon_device *rdev) 621 { 622 int r; 623 624 if (rdev->gart.ptr) { 625 WARN(1, "R100 PCI GART already initialized\n"); 626 return 0; 627 } 628 /* Initialize common gart structure */ 629 r = radeon_gart_init(rdev); 630 if (r) 631 return r; 632 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; 633 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush; 634 rdev->asic->gart.set_page = &r100_pci_gart_set_page; 635 return radeon_gart_table_ram_alloc(rdev); 636 } 637 638 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */ 639 void r100_enable_bm(struct radeon_device *rdev) 640 { 641 uint32_t tmp; 642 /* Enable bus mastering */ 643 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; 644 WREG32(RADEON_BUS_CNTL, tmp); 645 } 646 647 int r100_pci_gart_enable(struct radeon_device *rdev) 648 { 649 uint32_t tmp; 650 651 radeon_gart_restore(rdev); 652 /* discard memory request outside of configured range */ 653 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; 654 WREG32(RADEON_AIC_CNTL, tmp); 655 /* set address range for PCI address translate */ 656 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start); 657 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end); 658 /* set PCI GART page-table base address */ 659 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr); 660 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN; 661 WREG32(RADEON_AIC_CNTL, tmp); 662 r100_pci_gart_tlb_flush(rdev); 663 DRM_INFO("PCI GART of %uM enabled (table at 0x%016llX).\n", 664 (unsigned)(rdev->mc.gtt_size >> 20), 665 (unsigned long long)rdev->gart.table_addr); 666 rdev->gart.ready = true; 667 return 0; 668 } 669 670 void r100_pci_gart_disable(struct radeon_device *rdev) 671 { 672 uint32_t tmp; 673 674 /* discard memory request outside of configured range */ 675 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; 676 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN); 677 WREG32(RADEON_AIC_LO_ADDR, 0); 678 WREG32(RADEON_AIC_HI_ADDR, 0); 679 } 680 681 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) 682 { 683 u32 *gtt = rdev->gart.ptr; 684 685 if (i < 0 || i > rdev->gart.num_gpu_pages) { 686 return -EINVAL; 687 } 688 gtt[i] = cpu_to_le32(lower_32_bits(addr)); 689 return 0; 690 } 691 692 void r100_pci_gart_fini(struct radeon_device *rdev) 693 { 694 radeon_gart_fini(rdev); 695 r100_pci_gart_disable(rdev); 696 radeon_gart_table_ram_free(rdev); 697 } 698 699 int r100_irq_set(struct radeon_device *rdev) 700 { 701 uint32_t tmp = 0; 702 703 if (!rdev->irq.installed) { 704 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); 705 WREG32(R_000040_GEN_INT_CNTL, 0); 706 return -EINVAL; 707 } 708 if (rdev->irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) { 709 tmp |= RADEON_SW_INT_ENABLE; 710 } 711 if (rdev->irq.gui_idle) { 712 tmp |= RADEON_GUI_IDLE_MASK; 713 } 714 if (rdev->irq.crtc_vblank_int[0] || 715 rdev->irq.pflip[0]) { 716 tmp |= RADEON_CRTC_VBLANK_MASK; 717 } 718 if (rdev->irq.crtc_vblank_int[1] || 719 rdev->irq.pflip[1]) { 720 tmp |= RADEON_CRTC2_VBLANK_MASK; 721 } 722 if (rdev->irq.hpd[0]) { 723 tmp |= RADEON_FP_DETECT_MASK; 724 } 725 if (rdev->irq.hpd[1]) { 726 tmp |= RADEON_FP2_DETECT_MASK; 727 } 728 WREG32(RADEON_GEN_INT_CNTL, tmp); 729 return 0; 730 } 731 732 void r100_irq_disable(struct radeon_device *rdev) 733 { 734 u32 tmp; 735 736 WREG32(R_000040_GEN_INT_CNTL, 0); 737 /* Wait and acknowledge irq */ 738 mdelay(1); 739 tmp = RREG32(R_000044_GEN_INT_STATUS); 740 WREG32(R_000044_GEN_INT_STATUS, tmp); 741 } 742 743 static uint32_t r100_irq_ack(struct radeon_device *rdev) 744 { 745 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS); 746 uint32_t irq_mask = RADEON_SW_INT_TEST | 747 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT | 748 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT; 749 750 /* the interrupt works, but the status bit is permanently asserted */ 751 if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) { 752 if (!rdev->irq.gui_idle_acked) 753 irq_mask |= RADEON_GUI_IDLE_STAT; 754 } 755 756 if (irqs) { 757 WREG32(RADEON_GEN_INT_STATUS, irqs); 758 } 759 return irqs & irq_mask; 760 } 761 762 int r100_irq_process(struct radeon_device *rdev) 763 { 764 uint32_t status, msi_rearm; 765 bool queue_hotplug = false; 766 767 /* reset gui idle ack. the status bit is broken */ 768 rdev->irq.gui_idle_acked = false; 769 770 status = r100_irq_ack(rdev); 771 if (!status) { 772 return IRQ_NONE; 773 } 774 if (rdev->shutdown) { 775 return IRQ_NONE; 776 } 777 while (status) { 778 /* SW interrupt */ 779 if (status & RADEON_SW_INT_TEST) { 780 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 781 } 782 /* gui idle interrupt */ 783 if (status & RADEON_GUI_IDLE_STAT) { 784 rdev->irq.gui_idle_acked = true; 785 rdev->pm.gui_idle = true; 786 wake_up(&rdev->irq.idle_queue); 787 } 788 /* Vertical blank interrupts */ 789 if (status & RADEON_CRTC_VBLANK_STAT) { 790 if (rdev->irq.crtc_vblank_int[0]) { 791 drm_handle_vblank(rdev->ddev, 0); 792 rdev->pm.vblank_sync = true; 793 wake_up(&rdev->irq.vblank_queue); 794 } 795 if (rdev->irq.pflip[0]) 796 radeon_crtc_handle_flip(rdev, 0); 797 } 798 if (status & RADEON_CRTC2_VBLANK_STAT) { 799 if (rdev->irq.crtc_vblank_int[1]) { 800 drm_handle_vblank(rdev->ddev, 1); 801 rdev->pm.vblank_sync = true; 802 wake_up(&rdev->irq.vblank_queue); 803 } 804 if (rdev->irq.pflip[1]) 805 radeon_crtc_handle_flip(rdev, 1); 806 } 807 if (status & RADEON_FP_DETECT_STAT) { 808 queue_hotplug = true; 809 DRM_DEBUG("HPD1\n"); 810 } 811 if (status & RADEON_FP2_DETECT_STAT) { 812 queue_hotplug = true; 813 DRM_DEBUG("HPD2\n"); 814 } 815 status = r100_irq_ack(rdev); 816 } 817 /* reset gui idle ack. the status bit is broken */ 818 rdev->irq.gui_idle_acked = false; 819 if (queue_hotplug) 820 schedule_work(&rdev->hotplug_work); 821 if (rdev->msi_enabled) { 822 switch (rdev->family) { 823 case CHIP_RS400: 824 case CHIP_RS480: 825 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM; 826 WREG32(RADEON_AIC_CNTL, msi_rearm); 827 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM); 828 break; 829 default: 830 WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN); 831 break; 832 } 833 } 834 return IRQ_HANDLED; 835 } 836 837 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc) 838 { 839 if (crtc == 0) 840 return RREG32(RADEON_CRTC_CRNT_FRAME); 841 else 842 return RREG32(RADEON_CRTC2_CRNT_FRAME); 843 } 844 845 /* Who ever call radeon_fence_emit should call ring_lock and ask 846 * for enough space (today caller are ib schedule and buffer move) */ 847 void r100_fence_ring_emit(struct radeon_device *rdev, 848 struct radeon_fence *fence) 849 { 850 struct radeon_ring *ring = &rdev->ring[fence->ring]; 851 852 /* We have to make sure that caches are flushed before 853 * CPU might read something from VRAM. */ 854 radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); 855 radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL); 856 radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); 857 radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL); 858 /* Wait until IDLE & CLEAN */ 859 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); 860 radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); 861 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); 862 radeon_ring_write(ring, rdev->config.r100.hdp_cntl | 863 RADEON_HDP_READ_BUFFER_INVALIDATE); 864 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); 865 radeon_ring_write(ring, rdev->config.r100.hdp_cntl); 866 /* Emit fence sequence & fire IRQ */ 867 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0)); 868 radeon_ring_write(ring, fence->seq); 869 radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0)); 870 radeon_ring_write(ring, RADEON_SW_INT_FIRE); 871 } 872 873 void r100_semaphore_ring_emit(struct radeon_device *rdev, 874 struct radeon_ring *ring, 875 struct radeon_semaphore *semaphore, 876 bool emit_wait) 877 { 878 /* Unused on older asics, since we don't have semaphores or multiple rings */ 879 BUG(); 880 } 881 882 int r100_copy_blit(struct radeon_device *rdev, 883 uint64_t src_offset, 884 uint64_t dst_offset, 885 unsigned num_gpu_pages, 886 struct radeon_fence *fence) 887 { 888 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 889 uint32_t cur_pages; 890 uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE; 891 uint32_t pitch; 892 uint32_t stride_pixels; 893 unsigned ndw; 894 int num_loops; 895 int r = 0; 896 897 /* radeon limited to 16k stride */ 898 stride_bytes &= 0x3fff; 899 /* radeon pitch is /64 */ 900 pitch = stride_bytes / 64; 901 stride_pixels = stride_bytes / 4; 902 num_loops = DIV_ROUND_UP(num_gpu_pages, 8191); 903 904 /* Ask for enough room for blit + flush + fence */ 905 ndw = 64 + (10 * num_loops); 906 r = radeon_ring_lock(rdev, ring, ndw); 907 if (r) { 908 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw); 909 return -EINVAL; 910 } 911 while (num_gpu_pages > 0) { 912 cur_pages = num_gpu_pages; 913 if (cur_pages > 8191) { 914 cur_pages = 8191; 915 } 916 num_gpu_pages -= cur_pages; 917 918 /* pages are in Y direction - height 919 page width in X direction - width */ 920 radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8)); 921 radeon_ring_write(ring, 922 RADEON_GMC_SRC_PITCH_OFFSET_CNTL | 923 RADEON_GMC_DST_PITCH_OFFSET_CNTL | 924 RADEON_GMC_SRC_CLIPPING | 925 RADEON_GMC_DST_CLIPPING | 926 RADEON_GMC_BRUSH_NONE | 927 (RADEON_COLOR_FORMAT_ARGB8888 << 8) | 928 RADEON_GMC_SRC_DATATYPE_COLOR | 929 RADEON_ROP3_S | 930 RADEON_DP_SRC_SOURCE_MEMORY | 931 RADEON_GMC_CLR_CMP_CNTL_DIS | 932 RADEON_GMC_WR_MSK_DIS); 933 radeon_ring_write(ring, (pitch << 22) | (src_offset >> 10)); 934 radeon_ring_write(ring, (pitch << 22) | (dst_offset >> 10)); 935 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16)); 936 radeon_ring_write(ring, 0); 937 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16)); 938 radeon_ring_write(ring, num_gpu_pages); 939 radeon_ring_write(ring, num_gpu_pages); 940 radeon_ring_write(ring, cur_pages | (stride_pixels << 16)); 941 } 942 radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0)); 943 radeon_ring_write(ring, RADEON_RB2D_DC_FLUSH_ALL); 944 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); 945 radeon_ring_write(ring, 946 RADEON_WAIT_2D_IDLECLEAN | 947 RADEON_WAIT_HOST_IDLECLEAN | 948 RADEON_WAIT_DMA_GUI_IDLE); 949 if (fence) { 950 r = radeon_fence_emit(rdev, fence); 951 } 952 radeon_ring_unlock_commit(rdev, ring); 953 return r; 954 } 955 956 static int r100_cp_wait_for_idle(struct radeon_device *rdev) 957 { 958 unsigned i; 959 u32 tmp; 960 961 for (i = 0; i < rdev->usec_timeout; i++) { 962 tmp = RREG32(R_000E40_RBBM_STATUS); 963 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) { 964 return 0; 965 } 966 udelay(1); 967 } 968 return -1; 969 } 970 971 void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring) 972 { 973 int r; 974 975 r = radeon_ring_lock(rdev, ring, 2); 976 if (r) { 977 return; 978 } 979 radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0)); 980 radeon_ring_write(ring, 981 RADEON_ISYNC_ANY2D_IDLE3D | 982 RADEON_ISYNC_ANY3D_IDLE2D | 983 RADEON_ISYNC_WAIT_IDLEGUI | 984 RADEON_ISYNC_CPSCRATCH_IDLEGUI); 985 radeon_ring_unlock_commit(rdev, ring); 986 } 987 988 989 /* Load the microcode for the CP */ 990 static int r100_cp_init_microcode(struct radeon_device *rdev) 991 { 992 struct platform_device *pdev; 993 const char *fw_name = NULL; 994 int err; 995 996 DRM_DEBUG_KMS("\n"); 997 998 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0); 999 err = IS_ERR(pdev); 1000 if (err) { 1001 printk(KERN_ERR "radeon_cp: Failed to register firmware\n"); 1002 return -EINVAL; 1003 } 1004 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) || 1005 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) || 1006 (rdev->family == CHIP_RS200)) { 1007 DRM_INFO("Loading R100 Microcode\n"); 1008 fw_name = FIRMWARE_R100; 1009 } else if ((rdev->family == CHIP_R200) || 1010 (rdev->family == CHIP_RV250) || 1011 (rdev->family == CHIP_RV280) || 1012 (rdev->family == CHIP_RS300)) { 1013 DRM_INFO("Loading R200 Microcode\n"); 1014 fw_name = FIRMWARE_R200; 1015 } else if ((rdev->family == CHIP_R300) || 1016 (rdev->family == CHIP_R350) || 1017 (rdev->family == CHIP_RV350) || 1018 (rdev->family == CHIP_RV380) || 1019 (rdev->family == CHIP_RS400) || 1020 (rdev->family == CHIP_RS480)) { 1021 DRM_INFO("Loading R300 Microcode\n"); 1022 fw_name = FIRMWARE_R300; 1023 } else if ((rdev->family == CHIP_R420) || 1024 (rdev->family == CHIP_R423) || 1025 (rdev->family == CHIP_RV410)) { 1026 DRM_INFO("Loading R400 Microcode\n"); 1027 fw_name = FIRMWARE_R420; 1028 } else if ((rdev->family == CHIP_RS690) || 1029 (rdev->family == CHIP_RS740)) { 1030 DRM_INFO("Loading RS690/RS740 Microcode\n"); 1031 fw_name = FIRMWARE_RS690; 1032 } else if (rdev->family == CHIP_RS600) { 1033 DRM_INFO("Loading RS600 Microcode\n"); 1034 fw_name = FIRMWARE_RS600; 1035 } else if ((rdev->family == CHIP_RV515) || 1036 (rdev->family == CHIP_R520) || 1037 (rdev->family == CHIP_RV530) || 1038 (rdev->family == CHIP_R580) || 1039 (rdev->family == CHIP_RV560) || 1040 (rdev->family == CHIP_RV570)) { 1041 DRM_INFO("Loading R500 Microcode\n"); 1042 fw_name = FIRMWARE_R520; 1043 } 1044 1045 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev); 1046 platform_device_unregister(pdev); 1047 if (err) { 1048 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n", 1049 fw_name); 1050 } else if (rdev->me_fw->size % 8) { 1051 printk(KERN_ERR 1052 "radeon_cp: Bogus length %zu in firmware \"%s\"\n", 1053 rdev->me_fw->size, fw_name); 1054 err = -EINVAL; 1055 release_firmware(rdev->me_fw); 1056 rdev->me_fw = NULL; 1057 } 1058 return err; 1059 } 1060 1061 static void r100_cp_load_microcode(struct radeon_device *rdev) 1062 { 1063 const __be32 *fw_data; 1064 int i, size; 1065 1066 if (r100_gui_wait_for_idle(rdev)) { 1067 printk(KERN_WARNING "Failed to wait GUI idle while " 1068 "programming pipes. Bad things might happen.\n"); 1069 } 1070 1071 if (rdev->me_fw) { 1072 size = rdev->me_fw->size / 4; 1073 fw_data = (const __be32 *)&rdev->me_fw->data[0]; 1074 WREG32(RADEON_CP_ME_RAM_ADDR, 0); 1075 for (i = 0; i < size; i += 2) { 1076 WREG32(RADEON_CP_ME_RAM_DATAH, 1077 be32_to_cpup(&fw_data[i])); 1078 WREG32(RADEON_CP_ME_RAM_DATAL, 1079 be32_to_cpup(&fw_data[i + 1])); 1080 } 1081 } 1082 } 1083 1084 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size) 1085 { 1086 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 1087 unsigned rb_bufsz; 1088 unsigned rb_blksz; 1089 unsigned max_fetch; 1090 unsigned pre_write_timer; 1091 unsigned pre_write_limit; 1092 unsigned indirect2_start; 1093 unsigned indirect1_start; 1094 uint32_t tmp; 1095 int r; 1096 1097 if (r100_debugfs_cp_init(rdev)) { 1098 DRM_ERROR("Failed to register debugfs file for CP !\n"); 1099 } 1100 if (!rdev->me_fw) { 1101 r = r100_cp_init_microcode(rdev); 1102 if (r) { 1103 DRM_ERROR("Failed to load firmware!\n"); 1104 return r; 1105 } 1106 } 1107 1108 /* Align ring size */ 1109 rb_bufsz = drm_order(ring_size / 8); 1110 ring_size = (1 << (rb_bufsz + 1)) * 4; 1111 r100_cp_load_microcode(rdev); 1112 r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET, 1113 RADEON_CP_RB_RPTR, RADEON_CP_RB_WPTR, 1114 0, 0x7fffff, RADEON_CP_PACKET2); 1115 if (r) { 1116 return r; 1117 } 1118 /* Each time the cp read 1024 bytes (16 dword/quadword) update 1119 * the rptr copy in system ram */ 1120 rb_blksz = 9; 1121 /* cp will read 128bytes at a time (4 dwords) */ 1122 max_fetch = 1; 1123 ring->align_mask = 16 - 1; 1124 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */ 1125 pre_write_timer = 64; 1126 /* Force CP_RB_WPTR write if written more than one time before the 1127 * delay expire 1128 */ 1129 pre_write_limit = 0; 1130 /* Setup the cp cache like this (cache size is 96 dwords) : 1131 * RING 0 to 15 1132 * INDIRECT1 16 to 79 1133 * INDIRECT2 80 to 95 1134 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords)) 1135 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords)) 1136 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords)) 1137 * Idea being that most of the gpu cmd will be through indirect1 buffer 1138 * so it gets the bigger cache. 1139 */ 1140 indirect2_start = 80; 1141 indirect1_start = 16; 1142 /* cp setup */ 1143 WREG32(0x718, pre_write_timer | (pre_write_limit << 28)); 1144 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) | 1145 REG_SET(RADEON_RB_BLKSZ, rb_blksz) | 1146 REG_SET(RADEON_MAX_FETCH, max_fetch)); 1147 #ifdef __BIG_ENDIAN 1148 tmp |= RADEON_BUF_SWAP_32BIT; 1149 #endif 1150 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE); 1151 1152 /* Set ring address */ 1153 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr); 1154 WREG32(RADEON_CP_RB_BASE, ring->gpu_addr); 1155 /* Force read & write ptr to 0 */ 1156 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE); 1157 WREG32(RADEON_CP_RB_RPTR_WR, 0); 1158 ring->wptr = 0; 1159 WREG32(RADEON_CP_RB_WPTR, ring->wptr); 1160 1161 /* set the wb address whether it's enabled or not */ 1162 WREG32(R_00070C_CP_RB_RPTR_ADDR, 1163 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2)); 1164 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET); 1165 1166 if (rdev->wb.enabled) 1167 WREG32(R_000770_SCRATCH_UMSK, 0xff); 1168 else { 1169 tmp |= RADEON_RB_NO_UPDATE; 1170 WREG32(R_000770_SCRATCH_UMSK, 0); 1171 } 1172 1173 WREG32(RADEON_CP_RB_CNTL, tmp); 1174 udelay(10); 1175 ring->rptr = RREG32(RADEON_CP_RB_RPTR); 1176 /* Set cp mode to bus mastering & enable cp*/ 1177 WREG32(RADEON_CP_CSQ_MODE, 1178 REG_SET(RADEON_INDIRECT2_START, indirect2_start) | 1179 REG_SET(RADEON_INDIRECT1_START, indirect1_start)); 1180 WREG32(RADEON_CP_RB_WPTR_DELAY, 0); 1181 WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D); 1182 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM); 1183 1184 /* at this point everything should be setup correctly to enable master */ 1185 pci_set_master(rdev->pdev); 1186 1187 radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); 1188 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring); 1189 if (r) { 1190 DRM_ERROR("radeon: cp isn't working (%d).\n", r); 1191 return r; 1192 } 1193 ring->ready = true; 1194 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); 1195 return 0; 1196 } 1197 1198 void r100_cp_fini(struct radeon_device *rdev) 1199 { 1200 if (r100_cp_wait_for_idle(rdev)) { 1201 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n"); 1202 } 1203 /* Disable ring */ 1204 r100_cp_disable(rdev); 1205 radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); 1206 DRM_INFO("radeon: cp finalized\n"); 1207 } 1208 1209 void r100_cp_disable(struct radeon_device *rdev) 1210 { 1211 /* Disable ring */ 1212 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 1213 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 1214 WREG32(RADEON_CP_CSQ_MODE, 0); 1215 WREG32(RADEON_CP_CSQ_CNTL, 0); 1216 WREG32(R_000770_SCRATCH_UMSK, 0); 1217 if (r100_gui_wait_for_idle(rdev)) { 1218 printk(KERN_WARNING "Failed to wait GUI idle while " 1219 "programming pipes. Bad things might happen.\n"); 1220 } 1221 } 1222 1223 /* 1224 * CS functions 1225 */ 1226 int r100_cs_parse_packet0(struct radeon_cs_parser *p, 1227 struct radeon_cs_packet *pkt, 1228 const unsigned *auth, unsigned n, 1229 radeon_packet0_check_t check) 1230 { 1231 unsigned reg; 1232 unsigned i, j, m; 1233 unsigned idx; 1234 int r; 1235 1236 idx = pkt->idx + 1; 1237 reg = pkt->reg; 1238 /* Check that register fall into register range 1239 * determined by the number of entry (n) in the 1240 * safe register bitmap. 1241 */ 1242 if (pkt->one_reg_wr) { 1243 if ((reg >> 7) > n) { 1244 return -EINVAL; 1245 } 1246 } else { 1247 if (((reg + (pkt->count << 2)) >> 7) > n) { 1248 return -EINVAL; 1249 } 1250 } 1251 for (i = 0; i <= pkt->count; i++, idx++) { 1252 j = (reg >> 7); 1253 m = 1 << ((reg >> 2) & 31); 1254 if (auth[j] & m) { 1255 r = check(p, pkt, idx, reg); 1256 if (r) { 1257 return r; 1258 } 1259 } 1260 if (pkt->one_reg_wr) { 1261 if (!(auth[j] & m)) { 1262 break; 1263 } 1264 } else { 1265 reg += 4; 1266 } 1267 } 1268 return 0; 1269 } 1270 1271 void r100_cs_dump_packet(struct radeon_cs_parser *p, 1272 struct radeon_cs_packet *pkt) 1273 { 1274 volatile uint32_t *ib; 1275 unsigned i; 1276 unsigned idx; 1277 1278 ib = p->ib.ptr; 1279 idx = pkt->idx; 1280 for (i = 0; i <= (pkt->count + 1); i++, idx++) { 1281 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]); 1282 } 1283 } 1284 1285 /** 1286 * r100_cs_packet_parse() - parse cp packet and point ib index to next packet 1287 * @parser: parser structure holding parsing context. 1288 * @pkt: where to store packet informations 1289 * 1290 * Assume that chunk_ib_index is properly set. Will return -EINVAL 1291 * if packet is bigger than remaining ib size. or if packets is unknown. 1292 **/ 1293 int r100_cs_packet_parse(struct radeon_cs_parser *p, 1294 struct radeon_cs_packet *pkt, 1295 unsigned idx) 1296 { 1297 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx]; 1298 uint32_t header; 1299 1300 if (idx >= ib_chunk->length_dw) { 1301 DRM_ERROR("Can not parse packet at %d after CS end %d !\n", 1302 idx, ib_chunk->length_dw); 1303 return -EINVAL; 1304 } 1305 header = radeon_get_ib_value(p, idx); 1306 pkt->idx = idx; 1307 pkt->type = CP_PACKET_GET_TYPE(header); 1308 pkt->count = CP_PACKET_GET_COUNT(header); 1309 switch (pkt->type) { 1310 case PACKET_TYPE0: 1311 pkt->reg = CP_PACKET0_GET_REG(header); 1312 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header); 1313 break; 1314 case PACKET_TYPE3: 1315 pkt->opcode = CP_PACKET3_GET_OPCODE(header); 1316 break; 1317 case PACKET_TYPE2: 1318 pkt->count = -1; 1319 break; 1320 default: 1321 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx); 1322 return -EINVAL; 1323 } 1324 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) { 1325 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n", 1326 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw); 1327 return -EINVAL; 1328 } 1329 return 0; 1330 } 1331 1332 /** 1333 * r100_cs_packet_next_vline() - parse userspace VLINE packet 1334 * @parser: parser structure holding parsing context. 1335 * 1336 * Userspace sends a special sequence for VLINE waits. 1337 * PACKET0 - VLINE_START_END + value 1338 * PACKET0 - WAIT_UNTIL +_value 1339 * RELOC (P3) - crtc_id in reloc. 1340 * 1341 * This function parses this and relocates the VLINE START END 1342 * and WAIT UNTIL packets to the correct crtc. 1343 * It also detects a switched off crtc and nulls out the 1344 * wait in that case. 1345 */ 1346 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p) 1347 { 1348 struct drm_mode_object *obj; 1349 struct drm_crtc *crtc; 1350 struct radeon_crtc *radeon_crtc; 1351 struct radeon_cs_packet p3reloc, waitreloc; 1352 int crtc_id; 1353 int r; 1354 uint32_t header, h_idx, reg; 1355 volatile uint32_t *ib; 1356 1357 ib = p->ib.ptr; 1358 1359 /* parse the wait until */ 1360 r = r100_cs_packet_parse(p, &waitreloc, p->idx); 1361 if (r) 1362 return r; 1363 1364 /* check its a wait until and only 1 count */ 1365 if (waitreloc.reg != RADEON_WAIT_UNTIL || 1366 waitreloc.count != 0) { 1367 DRM_ERROR("vline wait had illegal wait until segment\n"); 1368 return -EINVAL; 1369 } 1370 1371 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) { 1372 DRM_ERROR("vline wait had illegal wait until\n"); 1373 return -EINVAL; 1374 } 1375 1376 /* jump over the NOP */ 1377 r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2); 1378 if (r) 1379 return r; 1380 1381 h_idx = p->idx - 2; 1382 p->idx += waitreloc.count + 2; 1383 p->idx += p3reloc.count + 2; 1384 1385 header = radeon_get_ib_value(p, h_idx); 1386 crtc_id = radeon_get_ib_value(p, h_idx + 5); 1387 reg = CP_PACKET0_GET_REG(header); 1388 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC); 1389 if (!obj) { 1390 DRM_ERROR("cannot find crtc %d\n", crtc_id); 1391 return -EINVAL; 1392 } 1393 crtc = obj_to_crtc(obj); 1394 radeon_crtc = to_radeon_crtc(crtc); 1395 crtc_id = radeon_crtc->crtc_id; 1396 1397 if (!crtc->enabled) { 1398 /* if the CRTC isn't enabled - we need to nop out the wait until */ 1399 ib[h_idx + 2] = PACKET2(0); 1400 ib[h_idx + 3] = PACKET2(0); 1401 } else if (crtc_id == 1) { 1402 switch (reg) { 1403 case AVIVO_D1MODE_VLINE_START_END: 1404 header &= ~R300_CP_PACKET0_REG_MASK; 1405 header |= AVIVO_D2MODE_VLINE_START_END >> 2; 1406 break; 1407 case RADEON_CRTC_GUI_TRIG_VLINE: 1408 header &= ~R300_CP_PACKET0_REG_MASK; 1409 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2; 1410 break; 1411 default: 1412 DRM_ERROR("unknown crtc reloc\n"); 1413 return -EINVAL; 1414 } 1415 ib[h_idx] = header; 1416 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1; 1417 } 1418 1419 return 0; 1420 } 1421 1422 /** 1423 * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3 1424 * @parser: parser structure holding parsing context. 1425 * @data: pointer to relocation data 1426 * @offset_start: starting offset 1427 * @offset_mask: offset mask (to align start offset on) 1428 * @reloc: reloc informations 1429 * 1430 * Check next packet is relocation packet3, do bo validation and compute 1431 * GPU offset using the provided start. 1432 **/ 1433 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p, 1434 struct radeon_cs_reloc **cs_reloc) 1435 { 1436 struct radeon_cs_chunk *relocs_chunk; 1437 struct radeon_cs_packet p3reloc; 1438 unsigned idx; 1439 int r; 1440 1441 if (p->chunk_relocs_idx == -1) { 1442 DRM_ERROR("No relocation chunk !\n"); 1443 return -EINVAL; 1444 } 1445 *cs_reloc = NULL; 1446 relocs_chunk = &p->chunks[p->chunk_relocs_idx]; 1447 r = r100_cs_packet_parse(p, &p3reloc, p->idx); 1448 if (r) { 1449 return r; 1450 } 1451 p->idx += p3reloc.count + 2; 1452 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) { 1453 DRM_ERROR("No packet3 for relocation for packet at %d.\n", 1454 p3reloc.idx); 1455 r100_cs_dump_packet(p, &p3reloc); 1456 return -EINVAL; 1457 } 1458 idx = radeon_get_ib_value(p, p3reloc.idx + 1); 1459 if (idx >= relocs_chunk->length_dw) { 1460 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n", 1461 idx, relocs_chunk->length_dw); 1462 r100_cs_dump_packet(p, &p3reloc); 1463 return -EINVAL; 1464 } 1465 /* FIXME: we assume reloc size is 4 dwords */ 1466 *cs_reloc = p->relocs_ptr[(idx / 4)]; 1467 return 0; 1468 } 1469 1470 static int r100_get_vtx_size(uint32_t vtx_fmt) 1471 { 1472 int vtx_size; 1473 vtx_size = 2; 1474 /* ordered according to bits in spec */ 1475 if (vtx_fmt & RADEON_SE_VTX_FMT_W0) 1476 vtx_size++; 1477 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR) 1478 vtx_size += 3; 1479 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA) 1480 vtx_size++; 1481 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR) 1482 vtx_size++; 1483 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC) 1484 vtx_size += 3; 1485 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG) 1486 vtx_size++; 1487 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC) 1488 vtx_size++; 1489 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0) 1490 vtx_size += 2; 1491 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1) 1492 vtx_size += 2; 1493 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1) 1494 vtx_size++; 1495 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2) 1496 vtx_size += 2; 1497 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2) 1498 vtx_size++; 1499 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3) 1500 vtx_size += 2; 1501 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3) 1502 vtx_size++; 1503 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0) 1504 vtx_size++; 1505 /* blend weight */ 1506 if (vtx_fmt & (0x7 << 15)) 1507 vtx_size += (vtx_fmt >> 15) & 0x7; 1508 if (vtx_fmt & RADEON_SE_VTX_FMT_N0) 1509 vtx_size += 3; 1510 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1) 1511 vtx_size += 2; 1512 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1) 1513 vtx_size++; 1514 if (vtx_fmt & RADEON_SE_VTX_FMT_W1) 1515 vtx_size++; 1516 if (vtx_fmt & RADEON_SE_VTX_FMT_N1) 1517 vtx_size++; 1518 if (vtx_fmt & RADEON_SE_VTX_FMT_Z) 1519 vtx_size++; 1520 return vtx_size; 1521 } 1522 1523 static int r100_packet0_check(struct radeon_cs_parser *p, 1524 struct radeon_cs_packet *pkt, 1525 unsigned idx, unsigned reg) 1526 { 1527 struct radeon_cs_reloc *reloc; 1528 struct r100_cs_track *track; 1529 volatile uint32_t *ib; 1530 uint32_t tmp; 1531 int r; 1532 int i, face; 1533 u32 tile_flags = 0; 1534 u32 idx_value; 1535 1536 ib = p->ib.ptr; 1537 track = (struct r100_cs_track *)p->track; 1538 1539 idx_value = radeon_get_ib_value(p, idx); 1540 1541 switch (reg) { 1542 case RADEON_CRTC_GUI_TRIG_VLINE: 1543 r = r100_cs_packet_parse_vline(p); 1544 if (r) { 1545 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1546 idx, reg); 1547 r100_cs_dump_packet(p, pkt); 1548 return r; 1549 } 1550 break; 1551 /* FIXME: only allow PACKET3 blit? easier to check for out of 1552 * range access */ 1553 case RADEON_DST_PITCH_OFFSET: 1554 case RADEON_SRC_PITCH_OFFSET: 1555 r = r100_reloc_pitch_offset(p, pkt, idx, reg); 1556 if (r) 1557 return r; 1558 break; 1559 case RADEON_RB3D_DEPTHOFFSET: 1560 r = r100_cs_packet_next_reloc(p, &reloc); 1561 if (r) { 1562 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1563 idx, reg); 1564 r100_cs_dump_packet(p, pkt); 1565 return r; 1566 } 1567 track->zb.robj = reloc->robj; 1568 track->zb.offset = idx_value; 1569 track->zb_dirty = true; 1570 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1571 break; 1572 case RADEON_RB3D_COLOROFFSET: 1573 r = r100_cs_packet_next_reloc(p, &reloc); 1574 if (r) { 1575 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1576 idx, reg); 1577 r100_cs_dump_packet(p, pkt); 1578 return r; 1579 } 1580 track->cb[0].robj = reloc->robj; 1581 track->cb[0].offset = idx_value; 1582 track->cb_dirty = true; 1583 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1584 break; 1585 case RADEON_PP_TXOFFSET_0: 1586 case RADEON_PP_TXOFFSET_1: 1587 case RADEON_PP_TXOFFSET_2: 1588 i = (reg - RADEON_PP_TXOFFSET_0) / 24; 1589 r = r100_cs_packet_next_reloc(p, &reloc); 1590 if (r) { 1591 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1592 idx, reg); 1593 r100_cs_dump_packet(p, pkt); 1594 return r; 1595 } 1596 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1597 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 1598 tile_flags |= RADEON_TXO_MACRO_TILE; 1599 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) 1600 tile_flags |= RADEON_TXO_MICRO_TILE_X2; 1601 1602 tmp = idx_value & ~(0x7 << 2); 1603 tmp |= tile_flags; 1604 ib[idx] = tmp + ((u32)reloc->lobj.gpu_offset); 1605 } else 1606 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1607 track->textures[i].robj = reloc->robj; 1608 track->tex_dirty = true; 1609 break; 1610 case RADEON_PP_CUBIC_OFFSET_T0_0: 1611 case RADEON_PP_CUBIC_OFFSET_T0_1: 1612 case RADEON_PP_CUBIC_OFFSET_T0_2: 1613 case RADEON_PP_CUBIC_OFFSET_T0_3: 1614 case RADEON_PP_CUBIC_OFFSET_T0_4: 1615 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4; 1616 r = r100_cs_packet_next_reloc(p, &reloc); 1617 if (r) { 1618 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1619 idx, reg); 1620 r100_cs_dump_packet(p, pkt); 1621 return r; 1622 } 1623 track->textures[0].cube_info[i].offset = idx_value; 1624 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1625 track->textures[0].cube_info[i].robj = reloc->robj; 1626 track->tex_dirty = true; 1627 break; 1628 case RADEON_PP_CUBIC_OFFSET_T1_0: 1629 case RADEON_PP_CUBIC_OFFSET_T1_1: 1630 case RADEON_PP_CUBIC_OFFSET_T1_2: 1631 case RADEON_PP_CUBIC_OFFSET_T1_3: 1632 case RADEON_PP_CUBIC_OFFSET_T1_4: 1633 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4; 1634 r = r100_cs_packet_next_reloc(p, &reloc); 1635 if (r) { 1636 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1637 idx, reg); 1638 r100_cs_dump_packet(p, pkt); 1639 return r; 1640 } 1641 track->textures[1].cube_info[i].offset = idx_value; 1642 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1643 track->textures[1].cube_info[i].robj = reloc->robj; 1644 track->tex_dirty = true; 1645 break; 1646 case RADEON_PP_CUBIC_OFFSET_T2_0: 1647 case RADEON_PP_CUBIC_OFFSET_T2_1: 1648 case RADEON_PP_CUBIC_OFFSET_T2_2: 1649 case RADEON_PP_CUBIC_OFFSET_T2_3: 1650 case RADEON_PP_CUBIC_OFFSET_T2_4: 1651 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4; 1652 r = r100_cs_packet_next_reloc(p, &reloc); 1653 if (r) { 1654 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1655 idx, reg); 1656 r100_cs_dump_packet(p, pkt); 1657 return r; 1658 } 1659 track->textures[2].cube_info[i].offset = idx_value; 1660 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1661 track->textures[2].cube_info[i].robj = reloc->robj; 1662 track->tex_dirty = true; 1663 break; 1664 case RADEON_RE_WIDTH_HEIGHT: 1665 track->maxy = ((idx_value >> 16) & 0x7FF); 1666 track->cb_dirty = true; 1667 track->zb_dirty = true; 1668 break; 1669 case RADEON_RB3D_COLORPITCH: 1670 r = r100_cs_packet_next_reloc(p, &reloc); 1671 if (r) { 1672 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1673 idx, reg); 1674 r100_cs_dump_packet(p, pkt); 1675 return r; 1676 } 1677 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1678 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 1679 tile_flags |= RADEON_COLOR_TILE_ENABLE; 1680 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) 1681 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE; 1682 1683 tmp = idx_value & ~(0x7 << 16); 1684 tmp |= tile_flags; 1685 ib[idx] = tmp; 1686 } else 1687 ib[idx] = idx_value; 1688 1689 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK; 1690 track->cb_dirty = true; 1691 break; 1692 case RADEON_RB3D_DEPTHPITCH: 1693 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK; 1694 track->zb_dirty = true; 1695 break; 1696 case RADEON_RB3D_CNTL: 1697 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) { 1698 case 7: 1699 case 8: 1700 case 9: 1701 case 11: 1702 case 12: 1703 track->cb[0].cpp = 1; 1704 break; 1705 case 3: 1706 case 4: 1707 case 15: 1708 track->cb[0].cpp = 2; 1709 break; 1710 case 6: 1711 track->cb[0].cpp = 4; 1712 break; 1713 default: 1714 DRM_ERROR("Invalid color buffer format (%d) !\n", 1715 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f)); 1716 return -EINVAL; 1717 } 1718 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE); 1719 track->cb_dirty = true; 1720 track->zb_dirty = true; 1721 break; 1722 case RADEON_RB3D_ZSTENCILCNTL: 1723 switch (idx_value & 0xf) { 1724 case 0: 1725 track->zb.cpp = 2; 1726 break; 1727 case 2: 1728 case 3: 1729 case 4: 1730 case 5: 1731 case 9: 1732 case 11: 1733 track->zb.cpp = 4; 1734 break; 1735 default: 1736 break; 1737 } 1738 track->zb_dirty = true; 1739 break; 1740 case RADEON_RB3D_ZPASS_ADDR: 1741 r = r100_cs_packet_next_reloc(p, &reloc); 1742 if (r) { 1743 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1744 idx, reg); 1745 r100_cs_dump_packet(p, pkt); 1746 return r; 1747 } 1748 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1749 break; 1750 case RADEON_PP_CNTL: 1751 { 1752 uint32_t temp = idx_value >> 4; 1753 for (i = 0; i < track->num_texture; i++) 1754 track->textures[i].enabled = !!(temp & (1 << i)); 1755 track->tex_dirty = true; 1756 } 1757 break; 1758 case RADEON_SE_VF_CNTL: 1759 track->vap_vf_cntl = idx_value; 1760 break; 1761 case RADEON_SE_VTX_FMT: 1762 track->vtx_size = r100_get_vtx_size(idx_value); 1763 break; 1764 case RADEON_PP_TEX_SIZE_0: 1765 case RADEON_PP_TEX_SIZE_1: 1766 case RADEON_PP_TEX_SIZE_2: 1767 i = (reg - RADEON_PP_TEX_SIZE_0) / 8; 1768 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1; 1769 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1; 1770 track->tex_dirty = true; 1771 break; 1772 case RADEON_PP_TEX_PITCH_0: 1773 case RADEON_PP_TEX_PITCH_1: 1774 case RADEON_PP_TEX_PITCH_2: 1775 i = (reg - RADEON_PP_TEX_PITCH_0) / 8; 1776 track->textures[i].pitch = idx_value + 32; 1777 track->tex_dirty = true; 1778 break; 1779 case RADEON_PP_TXFILTER_0: 1780 case RADEON_PP_TXFILTER_1: 1781 case RADEON_PP_TXFILTER_2: 1782 i = (reg - RADEON_PP_TXFILTER_0) / 24; 1783 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK) 1784 >> RADEON_MAX_MIP_LEVEL_SHIFT); 1785 tmp = (idx_value >> 23) & 0x7; 1786 if (tmp == 2 || tmp == 6) 1787 track->textures[i].roundup_w = false; 1788 tmp = (idx_value >> 27) & 0x7; 1789 if (tmp == 2 || tmp == 6) 1790 track->textures[i].roundup_h = false; 1791 track->tex_dirty = true; 1792 break; 1793 case RADEON_PP_TXFORMAT_0: 1794 case RADEON_PP_TXFORMAT_1: 1795 case RADEON_PP_TXFORMAT_2: 1796 i = (reg - RADEON_PP_TXFORMAT_0) / 24; 1797 if (idx_value & RADEON_TXFORMAT_NON_POWER2) { 1798 track->textures[i].use_pitch = 1; 1799 } else { 1800 track->textures[i].use_pitch = 0; 1801 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK); 1802 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK); 1803 } 1804 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE) 1805 track->textures[i].tex_coord_type = 2; 1806 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) { 1807 case RADEON_TXFORMAT_I8: 1808 case RADEON_TXFORMAT_RGB332: 1809 case RADEON_TXFORMAT_Y8: 1810 track->textures[i].cpp = 1; 1811 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 1812 break; 1813 case RADEON_TXFORMAT_AI88: 1814 case RADEON_TXFORMAT_ARGB1555: 1815 case RADEON_TXFORMAT_RGB565: 1816 case RADEON_TXFORMAT_ARGB4444: 1817 case RADEON_TXFORMAT_VYUY422: 1818 case RADEON_TXFORMAT_YVYU422: 1819 case RADEON_TXFORMAT_SHADOW16: 1820 case RADEON_TXFORMAT_LDUDV655: 1821 case RADEON_TXFORMAT_DUDV88: 1822 track->textures[i].cpp = 2; 1823 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 1824 break; 1825 case RADEON_TXFORMAT_ARGB8888: 1826 case RADEON_TXFORMAT_RGBA8888: 1827 case RADEON_TXFORMAT_SHADOW32: 1828 case RADEON_TXFORMAT_LDUDUV8888: 1829 track->textures[i].cpp = 4; 1830 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 1831 break; 1832 case RADEON_TXFORMAT_DXT1: 1833 track->textures[i].cpp = 1; 1834 track->textures[i].compress_format = R100_TRACK_COMP_DXT1; 1835 break; 1836 case RADEON_TXFORMAT_DXT23: 1837 case RADEON_TXFORMAT_DXT45: 1838 track->textures[i].cpp = 1; 1839 track->textures[i].compress_format = R100_TRACK_COMP_DXT35; 1840 break; 1841 } 1842 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf); 1843 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf); 1844 track->tex_dirty = true; 1845 break; 1846 case RADEON_PP_CUBIC_FACES_0: 1847 case RADEON_PP_CUBIC_FACES_1: 1848 case RADEON_PP_CUBIC_FACES_2: 1849 tmp = idx_value; 1850 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4; 1851 for (face = 0; face < 4; face++) { 1852 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf); 1853 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf); 1854 } 1855 track->tex_dirty = true; 1856 break; 1857 default: 1858 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n", 1859 reg, idx); 1860 return -EINVAL; 1861 } 1862 return 0; 1863 } 1864 1865 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, 1866 struct radeon_cs_packet *pkt, 1867 struct radeon_bo *robj) 1868 { 1869 unsigned idx; 1870 u32 value; 1871 idx = pkt->idx + 1; 1872 value = radeon_get_ib_value(p, idx + 2); 1873 if ((value + 1) > radeon_bo_size(robj)) { 1874 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER " 1875 "(need %u have %lu) !\n", 1876 value + 1, 1877 radeon_bo_size(robj)); 1878 return -EINVAL; 1879 } 1880 return 0; 1881 } 1882 1883 static int r100_packet3_check(struct radeon_cs_parser *p, 1884 struct radeon_cs_packet *pkt) 1885 { 1886 struct radeon_cs_reloc *reloc; 1887 struct r100_cs_track *track; 1888 unsigned idx; 1889 volatile uint32_t *ib; 1890 int r; 1891 1892 ib = p->ib.ptr; 1893 idx = pkt->idx + 1; 1894 track = (struct r100_cs_track *)p->track; 1895 switch (pkt->opcode) { 1896 case PACKET3_3D_LOAD_VBPNTR: 1897 r = r100_packet3_load_vbpntr(p, pkt, idx); 1898 if (r) 1899 return r; 1900 break; 1901 case PACKET3_INDX_BUFFER: 1902 r = r100_cs_packet_next_reloc(p, &reloc); 1903 if (r) { 1904 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); 1905 r100_cs_dump_packet(p, pkt); 1906 return r; 1907 } 1908 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset); 1909 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); 1910 if (r) { 1911 return r; 1912 } 1913 break; 1914 case 0x23: 1915 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */ 1916 r = r100_cs_packet_next_reloc(p, &reloc); 1917 if (r) { 1918 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); 1919 r100_cs_dump_packet(p, pkt); 1920 return r; 1921 } 1922 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset); 1923 track->num_arrays = 1; 1924 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2)); 1925 1926 track->arrays[0].robj = reloc->robj; 1927 track->arrays[0].esize = track->vtx_size; 1928 1929 track->max_indx = radeon_get_ib_value(p, idx+1); 1930 1931 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3); 1932 track->immd_dwords = pkt->count - 1; 1933 r = r100_cs_track_check(p->rdev, track); 1934 if (r) 1935 return r; 1936 break; 1937 case PACKET3_3D_DRAW_IMMD: 1938 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) { 1939 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1940 return -EINVAL; 1941 } 1942 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0)); 1943 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1944 track->immd_dwords = pkt->count - 1; 1945 r = r100_cs_track_check(p->rdev, track); 1946 if (r) 1947 return r; 1948 break; 1949 /* triggers drawing using in-packet vertex data */ 1950 case PACKET3_3D_DRAW_IMMD_2: 1951 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) { 1952 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1953 return -EINVAL; 1954 } 1955 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1956 track->immd_dwords = pkt->count; 1957 r = r100_cs_track_check(p->rdev, track); 1958 if (r) 1959 return r; 1960 break; 1961 /* triggers drawing using in-packet vertex data */ 1962 case PACKET3_3D_DRAW_VBUF_2: 1963 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1964 r = r100_cs_track_check(p->rdev, track); 1965 if (r) 1966 return r; 1967 break; 1968 /* triggers drawing of vertex buffers setup elsewhere */ 1969 case PACKET3_3D_DRAW_INDX_2: 1970 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1971 r = r100_cs_track_check(p->rdev, track); 1972 if (r) 1973 return r; 1974 break; 1975 /* triggers drawing using indices to vertex buffer */ 1976 case PACKET3_3D_DRAW_VBUF: 1977 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1978 r = r100_cs_track_check(p->rdev, track); 1979 if (r) 1980 return r; 1981 break; 1982 /* triggers drawing of vertex buffers setup elsewhere */ 1983 case PACKET3_3D_DRAW_INDX: 1984 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1985 r = r100_cs_track_check(p->rdev, track); 1986 if (r) 1987 return r; 1988 break; 1989 /* triggers drawing using indices to vertex buffer */ 1990 case PACKET3_3D_CLEAR_HIZ: 1991 case PACKET3_3D_CLEAR_ZMASK: 1992 if (p->rdev->hyperz_filp != p->filp) 1993 return -EINVAL; 1994 break; 1995 case PACKET3_NOP: 1996 break; 1997 default: 1998 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); 1999 return -EINVAL; 2000 } 2001 return 0; 2002 } 2003 2004 int r100_cs_parse(struct radeon_cs_parser *p) 2005 { 2006 struct radeon_cs_packet pkt; 2007 struct r100_cs_track *track; 2008 int r; 2009 2010 track = kzalloc(sizeof(*track), GFP_KERNEL); 2011 if (!track) 2012 return -ENOMEM; 2013 r100_cs_track_clear(p->rdev, track); 2014 p->track = track; 2015 do { 2016 r = r100_cs_packet_parse(p, &pkt, p->idx); 2017 if (r) { 2018 return r; 2019 } 2020 p->idx += pkt.count + 2; 2021 switch (pkt.type) { 2022 case PACKET_TYPE0: 2023 if (p->rdev->family >= CHIP_R200) 2024 r = r100_cs_parse_packet0(p, &pkt, 2025 p->rdev->config.r100.reg_safe_bm, 2026 p->rdev->config.r100.reg_safe_bm_size, 2027 &r200_packet0_check); 2028 else 2029 r = r100_cs_parse_packet0(p, &pkt, 2030 p->rdev->config.r100.reg_safe_bm, 2031 p->rdev->config.r100.reg_safe_bm_size, 2032 &r100_packet0_check); 2033 break; 2034 case PACKET_TYPE2: 2035 break; 2036 case PACKET_TYPE3: 2037 r = r100_packet3_check(p, &pkt); 2038 break; 2039 default: 2040 DRM_ERROR("Unknown packet type %d !\n", 2041 pkt.type); 2042 return -EINVAL; 2043 } 2044 if (r) { 2045 return r; 2046 } 2047 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw); 2048 return 0; 2049 } 2050 2051 2052 /* 2053 * Global GPU functions 2054 */ 2055 void r100_errata(struct radeon_device *rdev) 2056 { 2057 rdev->pll_errata = 0; 2058 2059 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) { 2060 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS; 2061 } 2062 2063 if (rdev->family == CHIP_RV100 || 2064 rdev->family == CHIP_RS100 || 2065 rdev->family == CHIP_RS200) { 2066 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY; 2067 } 2068 } 2069 2070 /* Wait for vertical sync on primary CRTC */ 2071 void r100_gpu_wait_for_vsync(struct radeon_device *rdev) 2072 { 2073 uint32_t crtc_gen_cntl, tmp; 2074 int i; 2075 2076 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL); 2077 if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) || 2078 !(crtc_gen_cntl & RADEON_CRTC_EN)) { 2079 return; 2080 } 2081 /* Clear the CRTC_VBLANK_SAVE bit */ 2082 WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR); 2083 for (i = 0; i < rdev->usec_timeout; i++) { 2084 tmp = RREG32(RADEON_CRTC_STATUS); 2085 if (tmp & RADEON_CRTC_VBLANK_SAVE) { 2086 return; 2087 } 2088 DRM_UDELAY(1); 2089 } 2090 } 2091 2092 /* Wait for vertical sync on secondary CRTC */ 2093 void r100_gpu_wait_for_vsync2(struct radeon_device *rdev) 2094 { 2095 uint32_t crtc2_gen_cntl, tmp; 2096 int i; 2097 2098 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); 2099 if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) || 2100 !(crtc2_gen_cntl & RADEON_CRTC2_EN)) 2101 return; 2102 2103 /* Clear the CRTC_VBLANK_SAVE bit */ 2104 WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR); 2105 for (i = 0; i < rdev->usec_timeout; i++) { 2106 tmp = RREG32(RADEON_CRTC2_STATUS); 2107 if (tmp & RADEON_CRTC2_VBLANK_SAVE) { 2108 return; 2109 } 2110 DRM_UDELAY(1); 2111 } 2112 } 2113 2114 int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n) 2115 { 2116 unsigned i; 2117 uint32_t tmp; 2118 2119 for (i = 0; i < rdev->usec_timeout; i++) { 2120 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK; 2121 if (tmp >= n) { 2122 return 0; 2123 } 2124 DRM_UDELAY(1); 2125 } 2126 return -1; 2127 } 2128 2129 int r100_gui_wait_for_idle(struct radeon_device *rdev) 2130 { 2131 unsigned i; 2132 uint32_t tmp; 2133 2134 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) { 2135 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !" 2136 " Bad things might happen.\n"); 2137 } 2138 for (i = 0; i < rdev->usec_timeout; i++) { 2139 tmp = RREG32(RADEON_RBBM_STATUS); 2140 if (!(tmp & RADEON_RBBM_ACTIVE)) { 2141 return 0; 2142 } 2143 DRM_UDELAY(1); 2144 } 2145 return -1; 2146 } 2147 2148 int r100_mc_wait_for_idle(struct radeon_device *rdev) 2149 { 2150 unsigned i; 2151 uint32_t tmp; 2152 2153 for (i = 0; i < rdev->usec_timeout; i++) { 2154 /* read MC_STATUS */ 2155 tmp = RREG32(RADEON_MC_STATUS); 2156 if (tmp & RADEON_MC_IDLE) { 2157 return 0; 2158 } 2159 DRM_UDELAY(1); 2160 } 2161 return -1; 2162 } 2163 2164 bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 2165 { 2166 u32 rbbm_status; 2167 2168 rbbm_status = RREG32(R_000E40_RBBM_STATUS); 2169 if (!G_000E40_GUI_ACTIVE(rbbm_status)) { 2170 radeon_ring_lockup_update(ring); 2171 return false; 2172 } 2173 /* force CP activities */ 2174 radeon_ring_force_activity(rdev, ring); 2175 return radeon_ring_test_lockup(rdev, ring); 2176 } 2177 2178 void r100_bm_disable(struct radeon_device *rdev) 2179 { 2180 u32 tmp; 2181 2182 /* disable bus mastering */ 2183 tmp = RREG32(R_000030_BUS_CNTL); 2184 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044); 2185 mdelay(1); 2186 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042); 2187 mdelay(1); 2188 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040); 2189 tmp = RREG32(RADEON_BUS_CNTL); 2190 mdelay(1); 2191 pci_clear_master(rdev->pdev); 2192 mdelay(1); 2193 } 2194 2195 int r100_asic_reset(struct radeon_device *rdev) 2196 { 2197 struct r100_mc_save save; 2198 u32 status, tmp; 2199 int ret = 0; 2200 2201 status = RREG32(R_000E40_RBBM_STATUS); 2202 if (!G_000E40_GUI_ACTIVE(status)) { 2203 return 0; 2204 } 2205 r100_mc_stop(rdev, &save); 2206 status = RREG32(R_000E40_RBBM_STATUS); 2207 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 2208 /* stop CP */ 2209 WREG32(RADEON_CP_CSQ_CNTL, 0); 2210 tmp = RREG32(RADEON_CP_RB_CNTL); 2211 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); 2212 WREG32(RADEON_CP_RB_RPTR_WR, 0); 2213 WREG32(RADEON_CP_RB_WPTR, 0); 2214 WREG32(RADEON_CP_RB_CNTL, tmp); 2215 /* save PCI state */ 2216 pci_save_state(rdev->pdev); 2217 /* disable bus mastering */ 2218 r100_bm_disable(rdev); 2219 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) | 2220 S_0000F0_SOFT_RESET_RE(1) | 2221 S_0000F0_SOFT_RESET_PP(1) | 2222 S_0000F0_SOFT_RESET_RB(1)); 2223 RREG32(R_0000F0_RBBM_SOFT_RESET); 2224 mdelay(500); 2225 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 2226 mdelay(1); 2227 status = RREG32(R_000E40_RBBM_STATUS); 2228 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 2229 /* reset CP */ 2230 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); 2231 RREG32(R_0000F0_RBBM_SOFT_RESET); 2232 mdelay(500); 2233 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 2234 mdelay(1); 2235 status = RREG32(R_000E40_RBBM_STATUS); 2236 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 2237 /* restore PCI & busmastering */ 2238 pci_restore_state(rdev->pdev); 2239 r100_enable_bm(rdev); 2240 /* Check if GPU is idle */ 2241 if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) || 2242 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) { 2243 dev_err(rdev->dev, "failed to reset GPU\n"); 2244 ret = -1; 2245 } else 2246 dev_info(rdev->dev, "GPU reset succeed\n"); 2247 r100_mc_resume(rdev, &save); 2248 return ret; 2249 } 2250 2251 void r100_set_common_regs(struct radeon_device *rdev) 2252 { 2253 struct drm_device *dev = rdev->ddev; 2254 bool force_dac2 = false; 2255 u32 tmp; 2256 2257 /* set these so they don't interfere with anything */ 2258 WREG32(RADEON_OV0_SCALE_CNTL, 0); 2259 WREG32(RADEON_SUBPIC_CNTL, 0); 2260 WREG32(RADEON_VIPH_CONTROL, 0); 2261 WREG32(RADEON_I2C_CNTL_1, 0); 2262 WREG32(RADEON_DVI_I2C_CNTL_1, 0); 2263 WREG32(RADEON_CAP0_TRIG_CNTL, 0); 2264 WREG32(RADEON_CAP1_TRIG_CNTL, 0); 2265 2266 /* always set up dac2 on rn50 and some rv100 as lots 2267 * of servers seem to wire it up to a VGA port but 2268 * don't report it in the bios connector 2269 * table. 2270 */ 2271 switch (dev->pdev->device) { 2272 /* RN50 */ 2273 case 0x515e: 2274 case 0x5969: 2275 force_dac2 = true; 2276 break; 2277 /* RV100*/ 2278 case 0x5159: 2279 case 0x515a: 2280 /* DELL triple head servers */ 2281 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) && 2282 ((dev->pdev->subsystem_device == 0x016c) || 2283 (dev->pdev->subsystem_device == 0x016d) || 2284 (dev->pdev->subsystem_device == 0x016e) || 2285 (dev->pdev->subsystem_device == 0x016f) || 2286 (dev->pdev->subsystem_device == 0x0170) || 2287 (dev->pdev->subsystem_device == 0x017d) || 2288 (dev->pdev->subsystem_device == 0x017e) || 2289 (dev->pdev->subsystem_device == 0x0183) || 2290 (dev->pdev->subsystem_device == 0x018a) || 2291 (dev->pdev->subsystem_device == 0x019a))) 2292 force_dac2 = true; 2293 break; 2294 } 2295 2296 if (force_dac2) { 2297 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG); 2298 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); 2299 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2); 2300 2301 /* For CRT on DAC2, don't turn it on if BIOS didn't 2302 enable it, even it's detected. 2303 */ 2304 2305 /* force it to crtc0 */ 2306 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL; 2307 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL; 2308 disp_hw_debug |= RADEON_CRT2_DISP1_SEL; 2309 2310 /* set up the TV DAC */ 2311 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL | 2312 RADEON_TV_DAC_STD_MASK | 2313 RADEON_TV_DAC_RDACPD | 2314 RADEON_TV_DAC_GDACPD | 2315 RADEON_TV_DAC_BDACPD | 2316 RADEON_TV_DAC_BGADJ_MASK | 2317 RADEON_TV_DAC_DACADJ_MASK); 2318 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK | 2319 RADEON_TV_DAC_NHOLD | 2320 RADEON_TV_DAC_STD_PS2 | 2321 (0x58 << 16)); 2322 2323 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); 2324 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug); 2325 WREG32(RADEON_DAC_CNTL2, dac2_cntl); 2326 } 2327 2328 /* switch PM block to ACPI mode */ 2329 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL); 2330 tmp &= ~RADEON_PM_MODE_SEL; 2331 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp); 2332 2333 } 2334 2335 /* 2336 * VRAM info 2337 */ 2338 static void r100_vram_get_type(struct radeon_device *rdev) 2339 { 2340 uint32_t tmp; 2341 2342 rdev->mc.vram_is_ddr = false; 2343 if (rdev->flags & RADEON_IS_IGP) 2344 rdev->mc.vram_is_ddr = true; 2345 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR) 2346 rdev->mc.vram_is_ddr = true; 2347 if ((rdev->family == CHIP_RV100) || 2348 (rdev->family == CHIP_RS100) || 2349 (rdev->family == CHIP_RS200)) { 2350 tmp = RREG32(RADEON_MEM_CNTL); 2351 if (tmp & RV100_HALF_MODE) { 2352 rdev->mc.vram_width = 32; 2353 } else { 2354 rdev->mc.vram_width = 64; 2355 } 2356 if (rdev->flags & RADEON_SINGLE_CRTC) { 2357 rdev->mc.vram_width /= 4; 2358 rdev->mc.vram_is_ddr = true; 2359 } 2360 } else if (rdev->family <= CHIP_RV280) { 2361 tmp = RREG32(RADEON_MEM_CNTL); 2362 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) { 2363 rdev->mc.vram_width = 128; 2364 } else { 2365 rdev->mc.vram_width = 64; 2366 } 2367 } else { 2368 /* newer IGPs */ 2369 rdev->mc.vram_width = 128; 2370 } 2371 } 2372 2373 static u32 r100_get_accessible_vram(struct radeon_device *rdev) 2374 { 2375 u32 aper_size; 2376 u8 byte; 2377 2378 aper_size = RREG32(RADEON_CONFIG_APER_SIZE); 2379 2380 /* Set HDP_APER_CNTL only on cards that are known not to be broken, 2381 * that is has the 2nd generation multifunction PCI interface 2382 */ 2383 if (rdev->family == CHIP_RV280 || 2384 rdev->family >= CHIP_RV350) { 2385 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL, 2386 ~RADEON_HDP_APER_CNTL); 2387 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n"); 2388 return aper_size * 2; 2389 } 2390 2391 /* Older cards have all sorts of funny issues to deal with. First 2392 * check if it's a multifunction card by reading the PCI config 2393 * header type... Limit those to one aperture size 2394 */ 2395 pci_read_config_byte(rdev->pdev, 0xe, &byte); 2396 if (byte & 0x80) { 2397 DRM_INFO("Generation 1 PCI interface in multifunction mode\n"); 2398 DRM_INFO("Limiting VRAM to one aperture\n"); 2399 return aper_size; 2400 } 2401 2402 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS 2403 * have set it up. We don't write this as it's broken on some ASICs but 2404 * we expect the BIOS to have done the right thing (might be too optimistic...) 2405 */ 2406 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL) 2407 return aper_size * 2; 2408 return aper_size; 2409 } 2410 2411 void r100_vram_init_sizes(struct radeon_device *rdev) 2412 { 2413 u64 config_aper_size; 2414 2415 /* work out accessible VRAM */ 2416 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); 2417 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); 2418 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev); 2419 /* FIXME we don't use the second aperture yet when we could use it */ 2420 if (rdev->mc.visible_vram_size > rdev->mc.aper_size) 2421 rdev->mc.visible_vram_size = rdev->mc.aper_size; 2422 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE); 2423 if (rdev->flags & RADEON_IS_IGP) { 2424 uint32_t tom; 2425 /* read NB_TOM to get the amount of ram stolen for the GPU */ 2426 tom = RREG32(RADEON_NB_TOM); 2427 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16); 2428 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); 2429 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 2430 } else { 2431 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); 2432 /* Some production boards of m6 will report 0 2433 * if it's 8 MB 2434 */ 2435 if (rdev->mc.real_vram_size == 0) { 2436 rdev->mc.real_vram_size = 8192 * 1024; 2437 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); 2438 } 2439 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM - 2440 * Novell bug 204882 + along with lots of ubuntu ones 2441 */ 2442 if (rdev->mc.aper_size > config_aper_size) 2443 config_aper_size = rdev->mc.aper_size; 2444 2445 if (config_aper_size > rdev->mc.real_vram_size) 2446 rdev->mc.mc_vram_size = config_aper_size; 2447 else 2448 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 2449 } 2450 } 2451 2452 void r100_vga_set_state(struct radeon_device *rdev, bool state) 2453 { 2454 uint32_t temp; 2455 2456 temp = RREG32(RADEON_CONFIG_CNTL); 2457 if (state == false) { 2458 temp &= ~RADEON_CFG_VGA_RAM_EN; 2459 temp |= RADEON_CFG_VGA_IO_DIS; 2460 } else { 2461 temp &= ~RADEON_CFG_VGA_IO_DIS; 2462 } 2463 WREG32(RADEON_CONFIG_CNTL, temp); 2464 } 2465 2466 void r100_mc_init(struct radeon_device *rdev) 2467 { 2468 u64 base; 2469 2470 r100_vram_get_type(rdev); 2471 r100_vram_init_sizes(rdev); 2472 base = rdev->mc.aper_base; 2473 if (rdev->flags & RADEON_IS_IGP) 2474 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; 2475 radeon_vram_location(rdev, &rdev->mc, base); 2476 rdev->mc.gtt_base_align = 0; 2477 if (!(rdev->flags & RADEON_IS_AGP)) 2478 radeon_gtt_location(rdev, &rdev->mc); 2479 radeon_update_bandwidth_info(rdev); 2480 } 2481 2482 2483 /* 2484 * Indirect registers accessor 2485 */ 2486 void r100_pll_errata_after_index(struct radeon_device *rdev) 2487 { 2488 if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) { 2489 (void)RREG32(RADEON_CLOCK_CNTL_DATA); 2490 (void)RREG32(RADEON_CRTC_GEN_CNTL); 2491 } 2492 } 2493 2494 static void r100_pll_errata_after_data(struct radeon_device *rdev) 2495 { 2496 /* This workarounds is necessary on RV100, RS100 and RS200 chips 2497 * or the chip could hang on a subsequent access 2498 */ 2499 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) { 2500 mdelay(5); 2501 } 2502 2503 /* This function is required to workaround a hardware bug in some (all?) 2504 * revisions of the R300. This workaround should be called after every 2505 * CLOCK_CNTL_INDEX register access. If not, register reads afterward 2506 * may not be correct. 2507 */ 2508 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) { 2509 uint32_t save, tmp; 2510 2511 save = RREG32(RADEON_CLOCK_CNTL_INDEX); 2512 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 2513 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp); 2514 tmp = RREG32(RADEON_CLOCK_CNTL_DATA); 2515 WREG32(RADEON_CLOCK_CNTL_INDEX, save); 2516 } 2517 } 2518 2519 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg) 2520 { 2521 uint32_t data; 2522 2523 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f); 2524 r100_pll_errata_after_index(rdev); 2525 data = RREG32(RADEON_CLOCK_CNTL_DATA); 2526 r100_pll_errata_after_data(rdev); 2527 return data; 2528 } 2529 2530 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 2531 { 2532 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN)); 2533 r100_pll_errata_after_index(rdev); 2534 WREG32(RADEON_CLOCK_CNTL_DATA, v); 2535 r100_pll_errata_after_data(rdev); 2536 } 2537 2538 void r100_set_safe_registers(struct radeon_device *rdev) 2539 { 2540 if (ASIC_IS_RN50(rdev)) { 2541 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm; 2542 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm); 2543 } else if (rdev->family < CHIP_R200) { 2544 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm; 2545 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm); 2546 } else { 2547 r200_set_safe_registers(rdev); 2548 } 2549 } 2550 2551 /* 2552 * Debugfs info 2553 */ 2554 #if defined(CONFIG_DEBUG_FS) 2555 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data) 2556 { 2557 struct drm_info_node *node = (struct drm_info_node *) m->private; 2558 struct drm_device *dev = node->minor->dev; 2559 struct radeon_device *rdev = dev->dev_private; 2560 uint32_t reg, value; 2561 unsigned i; 2562 2563 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS)); 2564 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C)); 2565 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); 2566 for (i = 0; i < 64; i++) { 2567 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100); 2568 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2; 2569 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i); 2570 value = RREG32(RADEON_RBBM_CMDFIFO_DATA); 2571 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value); 2572 } 2573 return 0; 2574 } 2575 2576 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data) 2577 { 2578 struct drm_info_node *node = (struct drm_info_node *) m->private; 2579 struct drm_device *dev = node->minor->dev; 2580 struct radeon_device *rdev = dev->dev_private; 2581 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2582 uint32_t rdp, wdp; 2583 unsigned count, i, j; 2584 2585 radeon_ring_free_size(rdev, ring); 2586 rdp = RREG32(RADEON_CP_RB_RPTR); 2587 wdp = RREG32(RADEON_CP_RB_WPTR); 2588 count = (rdp + ring->ring_size - wdp) & ring->ptr_mask; 2589 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); 2590 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp); 2591 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp); 2592 seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw); 2593 seq_printf(m, "%u dwords in ring\n", count); 2594 for (j = 0; j <= count; j++) { 2595 i = (rdp + j) & ring->ptr_mask; 2596 seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]); 2597 } 2598 return 0; 2599 } 2600 2601 2602 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data) 2603 { 2604 struct drm_info_node *node = (struct drm_info_node *) m->private; 2605 struct drm_device *dev = node->minor->dev; 2606 struct radeon_device *rdev = dev->dev_private; 2607 uint32_t csq_stat, csq2_stat, tmp; 2608 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr; 2609 unsigned i; 2610 2611 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); 2612 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE)); 2613 csq_stat = RREG32(RADEON_CP_CSQ_STAT); 2614 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT); 2615 r_rptr = (csq_stat >> 0) & 0x3ff; 2616 r_wptr = (csq_stat >> 10) & 0x3ff; 2617 ib1_rptr = (csq_stat >> 20) & 0x3ff; 2618 ib1_wptr = (csq2_stat >> 0) & 0x3ff; 2619 ib2_rptr = (csq2_stat >> 10) & 0x3ff; 2620 ib2_wptr = (csq2_stat >> 20) & 0x3ff; 2621 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat); 2622 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat); 2623 seq_printf(m, "Ring rptr %u\n", r_rptr); 2624 seq_printf(m, "Ring wptr %u\n", r_wptr); 2625 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr); 2626 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr); 2627 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr); 2628 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr); 2629 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms 2630 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */ 2631 seq_printf(m, "Ring fifo:\n"); 2632 for (i = 0; i < 256; i++) { 2633 WREG32(RADEON_CP_CSQ_ADDR, i << 2); 2634 tmp = RREG32(RADEON_CP_CSQ_DATA); 2635 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp); 2636 } 2637 seq_printf(m, "Indirect1 fifo:\n"); 2638 for (i = 256; i <= 512; i++) { 2639 WREG32(RADEON_CP_CSQ_ADDR, i << 2); 2640 tmp = RREG32(RADEON_CP_CSQ_DATA); 2641 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp); 2642 } 2643 seq_printf(m, "Indirect2 fifo:\n"); 2644 for (i = 640; i < ib1_wptr; i++) { 2645 WREG32(RADEON_CP_CSQ_ADDR, i << 2); 2646 tmp = RREG32(RADEON_CP_CSQ_DATA); 2647 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp); 2648 } 2649 return 0; 2650 } 2651 2652 static int r100_debugfs_mc_info(struct seq_file *m, void *data) 2653 { 2654 struct drm_info_node *node = (struct drm_info_node *) m->private; 2655 struct drm_device *dev = node->minor->dev; 2656 struct radeon_device *rdev = dev->dev_private; 2657 uint32_t tmp; 2658 2659 tmp = RREG32(RADEON_CONFIG_MEMSIZE); 2660 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp); 2661 tmp = RREG32(RADEON_MC_FB_LOCATION); 2662 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp); 2663 tmp = RREG32(RADEON_BUS_CNTL); 2664 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp); 2665 tmp = RREG32(RADEON_MC_AGP_LOCATION); 2666 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp); 2667 tmp = RREG32(RADEON_AGP_BASE); 2668 seq_printf(m, "AGP_BASE 0x%08x\n", tmp); 2669 tmp = RREG32(RADEON_HOST_PATH_CNTL); 2670 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp); 2671 tmp = RREG32(0x01D0); 2672 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp); 2673 tmp = RREG32(RADEON_AIC_LO_ADDR); 2674 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp); 2675 tmp = RREG32(RADEON_AIC_HI_ADDR); 2676 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp); 2677 tmp = RREG32(0x01E4); 2678 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp); 2679 return 0; 2680 } 2681 2682 static struct drm_info_list r100_debugfs_rbbm_list[] = { 2683 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL}, 2684 }; 2685 2686 static struct drm_info_list r100_debugfs_cp_list[] = { 2687 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL}, 2688 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL}, 2689 }; 2690 2691 static struct drm_info_list r100_debugfs_mc_info_list[] = { 2692 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL}, 2693 }; 2694 #endif 2695 2696 int r100_debugfs_rbbm_init(struct radeon_device *rdev) 2697 { 2698 #if defined(CONFIG_DEBUG_FS) 2699 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1); 2700 #else 2701 return 0; 2702 #endif 2703 } 2704 2705 int r100_debugfs_cp_init(struct radeon_device *rdev) 2706 { 2707 #if defined(CONFIG_DEBUG_FS) 2708 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2); 2709 #else 2710 return 0; 2711 #endif 2712 } 2713 2714 int r100_debugfs_mc_info_init(struct radeon_device *rdev) 2715 { 2716 #if defined(CONFIG_DEBUG_FS) 2717 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1); 2718 #else 2719 return 0; 2720 #endif 2721 } 2722 2723 int r100_set_surface_reg(struct radeon_device *rdev, int reg, 2724 uint32_t tiling_flags, uint32_t pitch, 2725 uint32_t offset, uint32_t obj_size) 2726 { 2727 int surf_index = reg * 16; 2728 int flags = 0; 2729 2730 if (rdev->family <= CHIP_RS200) { 2731 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) 2732 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) 2733 flags |= RADEON_SURF_TILE_COLOR_BOTH; 2734 if (tiling_flags & RADEON_TILING_MACRO) 2735 flags |= RADEON_SURF_TILE_COLOR_MACRO; 2736 } else if (rdev->family <= CHIP_RV280) { 2737 if (tiling_flags & (RADEON_TILING_MACRO)) 2738 flags |= R200_SURF_TILE_COLOR_MACRO; 2739 if (tiling_flags & RADEON_TILING_MICRO) 2740 flags |= R200_SURF_TILE_COLOR_MICRO; 2741 } else { 2742 if (tiling_flags & RADEON_TILING_MACRO) 2743 flags |= R300_SURF_TILE_MACRO; 2744 if (tiling_flags & RADEON_TILING_MICRO) 2745 flags |= R300_SURF_TILE_MICRO; 2746 } 2747 2748 if (tiling_flags & RADEON_TILING_SWAP_16BIT) 2749 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP; 2750 if (tiling_flags & RADEON_TILING_SWAP_32BIT) 2751 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP; 2752 2753 /* when we aren't tiling the pitch seems to needs to be furtherdivided down. - tested on power5 + rn50 server */ 2754 if (tiling_flags & (RADEON_TILING_SWAP_16BIT | RADEON_TILING_SWAP_32BIT)) { 2755 if (!(tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) 2756 if (ASIC_IS_RN50(rdev)) 2757 pitch /= 16; 2758 } 2759 2760 /* r100/r200 divide by 16 */ 2761 if (rdev->family < CHIP_R300) 2762 flags |= pitch / 16; 2763 else 2764 flags |= pitch / 8; 2765 2766 2767 DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1); 2768 WREG32(RADEON_SURFACE0_INFO + surf_index, flags); 2769 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset); 2770 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1); 2771 return 0; 2772 } 2773 2774 void r100_clear_surface_reg(struct radeon_device *rdev, int reg) 2775 { 2776 int surf_index = reg * 16; 2777 WREG32(RADEON_SURFACE0_INFO + surf_index, 0); 2778 } 2779 2780 void r100_bandwidth_update(struct radeon_device *rdev) 2781 { 2782 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff; 2783 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff; 2784 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff; 2785 uint32_t temp, data, mem_trcd, mem_trp, mem_tras; 2786 fixed20_12 memtcas_ff[8] = { 2787 dfixed_init(1), 2788 dfixed_init(2), 2789 dfixed_init(3), 2790 dfixed_init(0), 2791 dfixed_init_half(1), 2792 dfixed_init_half(2), 2793 dfixed_init(0), 2794 }; 2795 fixed20_12 memtcas_rs480_ff[8] = { 2796 dfixed_init(0), 2797 dfixed_init(1), 2798 dfixed_init(2), 2799 dfixed_init(3), 2800 dfixed_init(0), 2801 dfixed_init_half(1), 2802 dfixed_init_half(2), 2803 dfixed_init_half(3), 2804 }; 2805 fixed20_12 memtcas2_ff[8] = { 2806 dfixed_init(0), 2807 dfixed_init(1), 2808 dfixed_init(2), 2809 dfixed_init(3), 2810 dfixed_init(4), 2811 dfixed_init(5), 2812 dfixed_init(6), 2813 dfixed_init(7), 2814 }; 2815 fixed20_12 memtrbs[8] = { 2816 dfixed_init(1), 2817 dfixed_init_half(1), 2818 dfixed_init(2), 2819 dfixed_init_half(2), 2820 dfixed_init(3), 2821 dfixed_init_half(3), 2822 dfixed_init(4), 2823 dfixed_init_half(4) 2824 }; 2825 fixed20_12 memtrbs_r4xx[8] = { 2826 dfixed_init(4), 2827 dfixed_init(5), 2828 dfixed_init(6), 2829 dfixed_init(7), 2830 dfixed_init(8), 2831 dfixed_init(9), 2832 dfixed_init(10), 2833 dfixed_init(11) 2834 }; 2835 fixed20_12 min_mem_eff; 2836 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1; 2837 fixed20_12 cur_latency_mclk, cur_latency_sclk; 2838 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate, 2839 disp_drain_rate2, read_return_rate; 2840 fixed20_12 time_disp1_drop_priority; 2841 int c; 2842 int cur_size = 16; /* in octawords */ 2843 int critical_point = 0, critical_point2; 2844 /* uint32_t read_return_rate, time_disp1_drop_priority; */ 2845 int stop_req, max_stop_req; 2846 struct drm_display_mode *mode1 = NULL; 2847 struct drm_display_mode *mode2 = NULL; 2848 uint32_t pixel_bytes1 = 0; 2849 uint32_t pixel_bytes2 = 0; 2850 2851 radeon_update_display_priority(rdev); 2852 2853 if (rdev->mode_info.crtcs[0]->base.enabled) { 2854 mode1 = &rdev->mode_info.crtcs[0]->base.mode; 2855 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8; 2856 } 2857 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 2858 if (rdev->mode_info.crtcs[1]->base.enabled) { 2859 mode2 = &rdev->mode_info.crtcs[1]->base.mode; 2860 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8; 2861 } 2862 } 2863 2864 min_mem_eff.full = dfixed_const_8(0); 2865 /* get modes */ 2866 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) { 2867 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER); 2868 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT); 2869 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT); 2870 /* check crtc enables */ 2871 if (mode2) 2872 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT); 2873 if (mode1) 2874 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT); 2875 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer); 2876 } 2877 2878 /* 2879 * determine is there is enough bw for current mode 2880 */ 2881 sclk_ff = rdev->pm.sclk; 2882 mclk_ff = rdev->pm.mclk; 2883 2884 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1); 2885 temp_ff.full = dfixed_const(temp); 2886 mem_bw.full = dfixed_mul(mclk_ff, temp_ff); 2887 2888 pix_clk.full = 0; 2889 pix_clk2.full = 0; 2890 peak_disp_bw.full = 0; 2891 if (mode1) { 2892 temp_ff.full = dfixed_const(1000); 2893 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */ 2894 pix_clk.full = dfixed_div(pix_clk, temp_ff); 2895 temp_ff.full = dfixed_const(pixel_bytes1); 2896 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff); 2897 } 2898 if (mode2) { 2899 temp_ff.full = dfixed_const(1000); 2900 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */ 2901 pix_clk2.full = dfixed_div(pix_clk2, temp_ff); 2902 temp_ff.full = dfixed_const(pixel_bytes2); 2903 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff); 2904 } 2905 2906 mem_bw.full = dfixed_mul(mem_bw, min_mem_eff); 2907 if (peak_disp_bw.full >= mem_bw.full) { 2908 DRM_ERROR("You may not have enough display bandwidth for current mode\n" 2909 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n"); 2910 } 2911 2912 /* Get values from the EXT_MEM_CNTL register...converting its contents. */ 2913 temp = RREG32(RADEON_MEM_TIMING_CNTL); 2914 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */ 2915 mem_trcd = ((temp >> 2) & 0x3) + 1; 2916 mem_trp = ((temp & 0x3)) + 1; 2917 mem_tras = ((temp & 0x70) >> 4) + 1; 2918 } else if (rdev->family == CHIP_R300 || 2919 rdev->family == CHIP_R350) { /* r300, r350 */ 2920 mem_trcd = (temp & 0x7) + 1; 2921 mem_trp = ((temp >> 8) & 0x7) + 1; 2922 mem_tras = ((temp >> 11) & 0xf) + 4; 2923 } else if (rdev->family == CHIP_RV350 || 2924 rdev->family <= CHIP_RV380) { 2925 /* rv3x0 */ 2926 mem_trcd = (temp & 0x7) + 3; 2927 mem_trp = ((temp >> 8) & 0x7) + 3; 2928 mem_tras = ((temp >> 11) & 0xf) + 6; 2929 } else if (rdev->family == CHIP_R420 || 2930 rdev->family == CHIP_R423 || 2931 rdev->family == CHIP_RV410) { 2932 /* r4xx */ 2933 mem_trcd = (temp & 0xf) + 3; 2934 if (mem_trcd > 15) 2935 mem_trcd = 15; 2936 mem_trp = ((temp >> 8) & 0xf) + 3; 2937 if (mem_trp > 15) 2938 mem_trp = 15; 2939 mem_tras = ((temp >> 12) & 0x1f) + 6; 2940 if (mem_tras > 31) 2941 mem_tras = 31; 2942 } else { /* RV200, R200 */ 2943 mem_trcd = (temp & 0x7) + 1; 2944 mem_trp = ((temp >> 8) & 0x7) + 1; 2945 mem_tras = ((temp >> 12) & 0xf) + 4; 2946 } 2947 /* convert to FF */ 2948 trcd_ff.full = dfixed_const(mem_trcd); 2949 trp_ff.full = dfixed_const(mem_trp); 2950 tras_ff.full = dfixed_const(mem_tras); 2951 2952 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */ 2953 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG); 2954 data = (temp & (7 << 20)) >> 20; 2955 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) { 2956 if (rdev->family == CHIP_RS480) /* don't think rs400 */ 2957 tcas_ff = memtcas_rs480_ff[data]; 2958 else 2959 tcas_ff = memtcas_ff[data]; 2960 } else 2961 tcas_ff = memtcas2_ff[data]; 2962 2963 if (rdev->family == CHIP_RS400 || 2964 rdev->family == CHIP_RS480) { 2965 /* extra cas latency stored in bits 23-25 0-4 clocks */ 2966 data = (temp >> 23) & 0x7; 2967 if (data < 5) 2968 tcas_ff.full += dfixed_const(data); 2969 } 2970 2971 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) { 2972 /* on the R300, Tcas is included in Trbs. 2973 */ 2974 temp = RREG32(RADEON_MEM_CNTL); 2975 data = (R300_MEM_NUM_CHANNELS_MASK & temp); 2976 if (data == 1) { 2977 if (R300_MEM_USE_CD_CH_ONLY & temp) { 2978 temp = RREG32(R300_MC_IND_INDEX); 2979 temp &= ~R300_MC_IND_ADDR_MASK; 2980 temp |= R300_MC_READ_CNTL_CD_mcind; 2981 WREG32(R300_MC_IND_INDEX, temp); 2982 temp = RREG32(R300_MC_IND_DATA); 2983 data = (R300_MEM_RBS_POSITION_C_MASK & temp); 2984 } else { 2985 temp = RREG32(R300_MC_READ_CNTL_AB); 2986 data = (R300_MEM_RBS_POSITION_A_MASK & temp); 2987 } 2988 } else { 2989 temp = RREG32(R300_MC_READ_CNTL_AB); 2990 data = (R300_MEM_RBS_POSITION_A_MASK & temp); 2991 } 2992 if (rdev->family == CHIP_RV410 || 2993 rdev->family == CHIP_R420 || 2994 rdev->family == CHIP_R423) 2995 trbs_ff = memtrbs_r4xx[data]; 2996 else 2997 trbs_ff = memtrbs[data]; 2998 tcas_ff.full += trbs_ff.full; 2999 } 3000 3001 sclk_eff_ff.full = sclk_ff.full; 3002 3003 if (rdev->flags & RADEON_IS_AGP) { 3004 fixed20_12 agpmode_ff; 3005 agpmode_ff.full = dfixed_const(radeon_agpmode); 3006 temp_ff.full = dfixed_const_666(16); 3007 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff); 3008 } 3009 /* TODO PCIE lanes may affect this - agpmode == 16?? */ 3010 3011 if (ASIC_IS_R300(rdev)) { 3012 sclk_delay_ff.full = dfixed_const(250); 3013 } else { 3014 if ((rdev->family == CHIP_RV100) || 3015 rdev->flags & RADEON_IS_IGP) { 3016 if (rdev->mc.vram_is_ddr) 3017 sclk_delay_ff.full = dfixed_const(41); 3018 else 3019 sclk_delay_ff.full = dfixed_const(33); 3020 } else { 3021 if (rdev->mc.vram_width == 128) 3022 sclk_delay_ff.full = dfixed_const(57); 3023 else 3024 sclk_delay_ff.full = dfixed_const(41); 3025 } 3026 } 3027 3028 mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff); 3029 3030 if (rdev->mc.vram_is_ddr) { 3031 if (rdev->mc.vram_width == 32) { 3032 k1.full = dfixed_const(40); 3033 c = 3; 3034 } else { 3035 k1.full = dfixed_const(20); 3036 c = 1; 3037 } 3038 } else { 3039 k1.full = dfixed_const(40); 3040 c = 3; 3041 } 3042 3043 temp_ff.full = dfixed_const(2); 3044 mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff); 3045 temp_ff.full = dfixed_const(c); 3046 mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff); 3047 temp_ff.full = dfixed_const(4); 3048 mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff); 3049 mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff); 3050 mc_latency_mclk.full += k1.full; 3051 3052 mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff); 3053 mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff); 3054 3055 /* 3056 HW cursor time assuming worst case of full size colour cursor. 3057 */ 3058 temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1)))); 3059 temp_ff.full += trcd_ff.full; 3060 if (temp_ff.full < tras_ff.full) 3061 temp_ff.full = tras_ff.full; 3062 cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff); 3063 3064 temp_ff.full = dfixed_const(cur_size); 3065 cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff); 3066 /* 3067 Find the total latency for the display data. 3068 */ 3069 disp_latency_overhead.full = dfixed_const(8); 3070 disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff); 3071 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full; 3072 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full; 3073 3074 if (mc_latency_mclk.full > mc_latency_sclk.full) 3075 disp_latency.full = mc_latency_mclk.full; 3076 else 3077 disp_latency.full = mc_latency_sclk.full; 3078 3079 /* setup Max GRPH_STOP_REQ default value */ 3080 if (ASIC_IS_RV100(rdev)) 3081 max_stop_req = 0x5c; 3082 else 3083 max_stop_req = 0x7c; 3084 3085 if (mode1) { 3086 /* CRTC1 3087 Set GRPH_BUFFER_CNTL register using h/w defined optimal values. 3088 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ] 3089 */ 3090 stop_req = mode1->hdisplay * pixel_bytes1 / 16; 3091 3092 if (stop_req > max_stop_req) 3093 stop_req = max_stop_req; 3094 3095 /* 3096 Find the drain rate of the display buffer. 3097 */ 3098 temp_ff.full = dfixed_const((16/pixel_bytes1)); 3099 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff); 3100 3101 /* 3102 Find the critical point of the display buffer. 3103 */ 3104 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency); 3105 crit_point_ff.full += dfixed_const_half(0); 3106 3107 critical_point = dfixed_trunc(crit_point_ff); 3108 3109 if (rdev->disp_priority == 2) { 3110 critical_point = 0; 3111 } 3112 3113 /* 3114 The critical point should never be above max_stop_req-4. Setting 3115 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time. 3116 */ 3117 if (max_stop_req - critical_point < 4) 3118 critical_point = 0; 3119 3120 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) { 3121 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/ 3122 critical_point = 0x10; 3123 } 3124 3125 temp = RREG32(RADEON_GRPH_BUFFER_CNTL); 3126 temp &= ~(RADEON_GRPH_STOP_REQ_MASK); 3127 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); 3128 temp &= ~(RADEON_GRPH_START_REQ_MASK); 3129 if ((rdev->family == CHIP_R350) && 3130 (stop_req > 0x15)) { 3131 stop_req -= 0x10; 3132 } 3133 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); 3134 temp |= RADEON_GRPH_BUFFER_SIZE; 3135 temp &= ~(RADEON_GRPH_CRITICAL_CNTL | 3136 RADEON_GRPH_CRITICAL_AT_SOF | 3137 RADEON_GRPH_STOP_CNTL); 3138 /* 3139 Write the result into the register. 3140 */ 3141 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) | 3142 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT))); 3143 3144 #if 0 3145 if ((rdev->family == CHIP_RS400) || 3146 (rdev->family == CHIP_RS480)) { 3147 /* attempt to program RS400 disp regs correctly ??? */ 3148 temp = RREG32(RS400_DISP1_REG_CNTL); 3149 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK | 3150 RS400_DISP1_STOP_REQ_LEVEL_MASK); 3151 WREG32(RS400_DISP1_REQ_CNTL1, (temp | 3152 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) | 3153 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); 3154 temp = RREG32(RS400_DMIF_MEM_CNTL1); 3155 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK | 3156 RS400_DISP1_CRITICAL_POINT_STOP_MASK); 3157 WREG32(RS400_DMIF_MEM_CNTL1, (temp | 3158 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) | 3159 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT))); 3160 } 3161 #endif 3162 3163 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n", 3164 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */ 3165 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL)); 3166 } 3167 3168 if (mode2) { 3169 u32 grph2_cntl; 3170 stop_req = mode2->hdisplay * pixel_bytes2 / 16; 3171 3172 if (stop_req > max_stop_req) 3173 stop_req = max_stop_req; 3174 3175 /* 3176 Find the drain rate of the display buffer. 3177 */ 3178 temp_ff.full = dfixed_const((16/pixel_bytes2)); 3179 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff); 3180 3181 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL); 3182 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK); 3183 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); 3184 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK); 3185 if ((rdev->family == CHIP_R350) && 3186 (stop_req > 0x15)) { 3187 stop_req -= 0x10; 3188 } 3189 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); 3190 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE; 3191 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL | 3192 RADEON_GRPH_CRITICAL_AT_SOF | 3193 RADEON_GRPH_STOP_CNTL); 3194 3195 if ((rdev->family == CHIP_RS100) || 3196 (rdev->family == CHIP_RS200)) 3197 critical_point2 = 0; 3198 else { 3199 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128; 3200 temp_ff.full = dfixed_const(temp); 3201 temp_ff.full = dfixed_mul(mclk_ff, temp_ff); 3202 if (sclk_ff.full < temp_ff.full) 3203 temp_ff.full = sclk_ff.full; 3204 3205 read_return_rate.full = temp_ff.full; 3206 3207 if (mode1) { 3208 temp_ff.full = read_return_rate.full - disp_drain_rate.full; 3209 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff); 3210 } else { 3211 time_disp1_drop_priority.full = 0; 3212 } 3213 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full; 3214 crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2); 3215 crit_point_ff.full += dfixed_const_half(0); 3216 3217 critical_point2 = dfixed_trunc(crit_point_ff); 3218 3219 if (rdev->disp_priority == 2) { 3220 critical_point2 = 0; 3221 } 3222 3223 if (max_stop_req - critical_point2 < 4) 3224 critical_point2 = 0; 3225 3226 } 3227 3228 if (critical_point2 == 0 && rdev->family == CHIP_R300) { 3229 /* some R300 cards have problem with this set to 0 */ 3230 critical_point2 = 0x10; 3231 } 3232 3233 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) | 3234 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT))); 3235 3236 if ((rdev->family == CHIP_RS400) || 3237 (rdev->family == CHIP_RS480)) { 3238 #if 0 3239 /* attempt to program RS400 disp2 regs correctly ??? */ 3240 temp = RREG32(RS400_DISP2_REQ_CNTL1); 3241 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK | 3242 RS400_DISP2_STOP_REQ_LEVEL_MASK); 3243 WREG32(RS400_DISP2_REQ_CNTL1, (temp | 3244 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) | 3245 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); 3246 temp = RREG32(RS400_DISP2_REQ_CNTL2); 3247 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK | 3248 RS400_DISP2_CRITICAL_POINT_STOP_MASK); 3249 WREG32(RS400_DISP2_REQ_CNTL2, (temp | 3250 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) | 3251 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT))); 3252 #endif 3253 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC); 3254 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000); 3255 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC); 3256 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC); 3257 } 3258 3259 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n", 3260 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL)); 3261 } 3262 } 3263 3264 static void r100_cs_track_texture_print(struct r100_cs_track_texture *t) 3265 { 3266 DRM_ERROR("pitch %d\n", t->pitch); 3267 DRM_ERROR("use_pitch %d\n", t->use_pitch); 3268 DRM_ERROR("width %d\n", t->width); 3269 DRM_ERROR("width_11 %d\n", t->width_11); 3270 DRM_ERROR("height %d\n", t->height); 3271 DRM_ERROR("height_11 %d\n", t->height_11); 3272 DRM_ERROR("num levels %d\n", t->num_levels); 3273 DRM_ERROR("depth %d\n", t->txdepth); 3274 DRM_ERROR("bpp %d\n", t->cpp); 3275 DRM_ERROR("coordinate type %d\n", t->tex_coord_type); 3276 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w); 3277 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h); 3278 DRM_ERROR("compress format %d\n", t->compress_format); 3279 } 3280 3281 static int r100_track_compress_size(int compress_format, int w, int h) 3282 { 3283 int block_width, block_height, block_bytes; 3284 int wblocks, hblocks; 3285 int min_wblocks; 3286 int sz; 3287 3288 block_width = 4; 3289 block_height = 4; 3290 3291 switch (compress_format) { 3292 case R100_TRACK_COMP_DXT1: 3293 block_bytes = 8; 3294 min_wblocks = 4; 3295 break; 3296 default: 3297 case R100_TRACK_COMP_DXT35: 3298 block_bytes = 16; 3299 min_wblocks = 2; 3300 break; 3301 } 3302 3303 hblocks = (h + block_height - 1) / block_height; 3304 wblocks = (w + block_width - 1) / block_width; 3305 if (wblocks < min_wblocks) 3306 wblocks = min_wblocks; 3307 sz = wblocks * hblocks * block_bytes; 3308 return sz; 3309 } 3310 3311 static int r100_cs_track_cube(struct radeon_device *rdev, 3312 struct r100_cs_track *track, unsigned idx) 3313 { 3314 unsigned face, w, h; 3315 struct radeon_bo *cube_robj; 3316 unsigned long size; 3317 unsigned compress_format = track->textures[idx].compress_format; 3318 3319 for (face = 0; face < 5; face++) { 3320 cube_robj = track->textures[idx].cube_info[face].robj; 3321 w = track->textures[idx].cube_info[face].width; 3322 h = track->textures[idx].cube_info[face].height; 3323 3324 if (compress_format) { 3325 size = r100_track_compress_size(compress_format, w, h); 3326 } else 3327 size = w * h; 3328 size *= track->textures[idx].cpp; 3329 3330 size += track->textures[idx].cube_info[face].offset; 3331 3332 if (size > radeon_bo_size(cube_robj)) { 3333 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n", 3334 size, radeon_bo_size(cube_robj)); 3335 r100_cs_track_texture_print(&track->textures[idx]); 3336 return -1; 3337 } 3338 } 3339 return 0; 3340 } 3341 3342 static int r100_cs_track_texture_check(struct radeon_device *rdev, 3343 struct r100_cs_track *track) 3344 { 3345 struct radeon_bo *robj; 3346 unsigned long size; 3347 unsigned u, i, w, h, d; 3348 int ret; 3349 3350 for (u = 0; u < track->num_texture; u++) { 3351 if (!track->textures[u].enabled) 3352 continue; 3353 if (track->textures[u].lookup_disable) 3354 continue; 3355 robj = track->textures[u].robj; 3356 if (robj == NULL) { 3357 DRM_ERROR("No texture bound to unit %u\n", u); 3358 return -EINVAL; 3359 } 3360 size = 0; 3361 for (i = 0; i <= track->textures[u].num_levels; i++) { 3362 if (track->textures[u].use_pitch) { 3363 if (rdev->family < CHIP_R300) 3364 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i); 3365 else 3366 w = track->textures[u].pitch / (1 << i); 3367 } else { 3368 w = track->textures[u].width; 3369 if (rdev->family >= CHIP_RV515) 3370 w |= track->textures[u].width_11; 3371 w = w / (1 << i); 3372 if (track->textures[u].roundup_w) 3373 w = roundup_pow_of_two(w); 3374 } 3375 h = track->textures[u].height; 3376 if (rdev->family >= CHIP_RV515) 3377 h |= track->textures[u].height_11; 3378 h = h / (1 << i); 3379 if (track->textures[u].roundup_h) 3380 h = roundup_pow_of_two(h); 3381 if (track->textures[u].tex_coord_type == 1) { 3382 d = (1 << track->textures[u].txdepth) / (1 << i); 3383 if (!d) 3384 d = 1; 3385 } else { 3386 d = 1; 3387 } 3388 if (track->textures[u].compress_format) { 3389 3390 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d; 3391 /* compressed textures are block based */ 3392 } else 3393 size += w * h * d; 3394 } 3395 size *= track->textures[u].cpp; 3396 3397 switch (track->textures[u].tex_coord_type) { 3398 case 0: 3399 case 1: 3400 break; 3401 case 2: 3402 if (track->separate_cube) { 3403 ret = r100_cs_track_cube(rdev, track, u); 3404 if (ret) 3405 return ret; 3406 } else 3407 size *= 6; 3408 break; 3409 default: 3410 DRM_ERROR("Invalid texture coordinate type %u for unit " 3411 "%u\n", track->textures[u].tex_coord_type, u); 3412 return -EINVAL; 3413 } 3414 if (size > radeon_bo_size(robj)) { 3415 DRM_ERROR("Texture of unit %u needs %lu bytes but is " 3416 "%lu\n", u, size, radeon_bo_size(robj)); 3417 r100_cs_track_texture_print(&track->textures[u]); 3418 return -EINVAL; 3419 } 3420 } 3421 return 0; 3422 } 3423 3424 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track) 3425 { 3426 unsigned i; 3427 unsigned long size; 3428 unsigned prim_walk; 3429 unsigned nverts; 3430 unsigned num_cb = track->cb_dirty ? track->num_cb : 0; 3431 3432 if (num_cb && !track->zb_cb_clear && !track->color_channel_mask && 3433 !track->blend_read_enable) 3434 num_cb = 0; 3435 3436 for (i = 0; i < num_cb; i++) { 3437 if (track->cb[i].robj == NULL) { 3438 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i); 3439 return -EINVAL; 3440 } 3441 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy; 3442 size += track->cb[i].offset; 3443 if (size > radeon_bo_size(track->cb[i].robj)) { 3444 DRM_ERROR("[drm] Buffer too small for color buffer %d " 3445 "(need %lu have %lu) !\n", i, size, 3446 radeon_bo_size(track->cb[i].robj)); 3447 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n", 3448 i, track->cb[i].pitch, track->cb[i].cpp, 3449 track->cb[i].offset, track->maxy); 3450 return -EINVAL; 3451 } 3452 } 3453 track->cb_dirty = false; 3454 3455 if (track->zb_dirty && track->z_enabled) { 3456 if (track->zb.robj == NULL) { 3457 DRM_ERROR("[drm] No buffer for z buffer !\n"); 3458 return -EINVAL; 3459 } 3460 size = track->zb.pitch * track->zb.cpp * track->maxy; 3461 size += track->zb.offset; 3462 if (size > radeon_bo_size(track->zb.robj)) { 3463 DRM_ERROR("[drm] Buffer too small for z buffer " 3464 "(need %lu have %lu) !\n", size, 3465 radeon_bo_size(track->zb.robj)); 3466 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n", 3467 track->zb.pitch, track->zb.cpp, 3468 track->zb.offset, track->maxy); 3469 return -EINVAL; 3470 } 3471 } 3472 track->zb_dirty = false; 3473 3474 if (track->aa_dirty && track->aaresolve) { 3475 if (track->aa.robj == NULL) { 3476 DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i); 3477 return -EINVAL; 3478 } 3479 /* I believe the format comes from colorbuffer0. */ 3480 size = track->aa.pitch * track->cb[0].cpp * track->maxy; 3481 size += track->aa.offset; 3482 if (size > radeon_bo_size(track->aa.robj)) { 3483 DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d " 3484 "(need %lu have %lu) !\n", i, size, 3485 radeon_bo_size(track->aa.robj)); 3486 DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n", 3487 i, track->aa.pitch, track->cb[0].cpp, 3488 track->aa.offset, track->maxy); 3489 return -EINVAL; 3490 } 3491 } 3492 track->aa_dirty = false; 3493 3494 prim_walk = (track->vap_vf_cntl >> 4) & 0x3; 3495 if (track->vap_vf_cntl & (1 << 14)) { 3496 nverts = track->vap_alt_nverts; 3497 } else { 3498 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF; 3499 } 3500 switch (prim_walk) { 3501 case 1: 3502 for (i = 0; i < track->num_arrays; i++) { 3503 size = track->arrays[i].esize * track->max_indx * 4; 3504 if (track->arrays[i].robj == NULL) { 3505 DRM_ERROR("(PW %u) Vertex array %u no buffer " 3506 "bound\n", prim_walk, i); 3507 return -EINVAL; 3508 } 3509 if (size > radeon_bo_size(track->arrays[i].robj)) { 3510 dev_err(rdev->dev, "(PW %u) Vertex array %u " 3511 "need %lu dwords have %lu dwords\n", 3512 prim_walk, i, size >> 2, 3513 radeon_bo_size(track->arrays[i].robj) 3514 >> 2); 3515 DRM_ERROR("Max indices %u\n", track->max_indx); 3516 return -EINVAL; 3517 } 3518 } 3519 break; 3520 case 2: 3521 for (i = 0; i < track->num_arrays; i++) { 3522 size = track->arrays[i].esize * (nverts - 1) * 4; 3523 if (track->arrays[i].robj == NULL) { 3524 DRM_ERROR("(PW %u) Vertex array %u no buffer " 3525 "bound\n", prim_walk, i); 3526 return -EINVAL; 3527 } 3528 if (size > radeon_bo_size(track->arrays[i].robj)) { 3529 dev_err(rdev->dev, "(PW %u) Vertex array %u " 3530 "need %lu dwords have %lu dwords\n", 3531 prim_walk, i, size >> 2, 3532 radeon_bo_size(track->arrays[i].robj) 3533 >> 2); 3534 return -EINVAL; 3535 } 3536 } 3537 break; 3538 case 3: 3539 size = track->vtx_size * nverts; 3540 if (size != track->immd_dwords) { 3541 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n", 3542 track->immd_dwords, size); 3543 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n", 3544 nverts, track->vtx_size); 3545 return -EINVAL; 3546 } 3547 break; 3548 default: 3549 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n", 3550 prim_walk); 3551 return -EINVAL; 3552 } 3553 3554 if (track->tex_dirty) { 3555 track->tex_dirty = false; 3556 return r100_cs_track_texture_check(rdev, track); 3557 } 3558 return 0; 3559 } 3560 3561 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track) 3562 { 3563 unsigned i, face; 3564 3565 track->cb_dirty = true; 3566 track->zb_dirty = true; 3567 track->tex_dirty = true; 3568 track->aa_dirty = true; 3569 3570 if (rdev->family < CHIP_R300) { 3571 track->num_cb = 1; 3572 if (rdev->family <= CHIP_RS200) 3573 track->num_texture = 3; 3574 else 3575 track->num_texture = 6; 3576 track->maxy = 2048; 3577 track->separate_cube = 1; 3578 } else { 3579 track->num_cb = 4; 3580 track->num_texture = 16; 3581 track->maxy = 4096; 3582 track->separate_cube = 0; 3583 track->aaresolve = false; 3584 track->aa.robj = NULL; 3585 } 3586 3587 for (i = 0; i < track->num_cb; i++) { 3588 track->cb[i].robj = NULL; 3589 track->cb[i].pitch = 8192; 3590 track->cb[i].cpp = 16; 3591 track->cb[i].offset = 0; 3592 } 3593 track->z_enabled = true; 3594 track->zb.robj = NULL; 3595 track->zb.pitch = 8192; 3596 track->zb.cpp = 4; 3597 track->zb.offset = 0; 3598 track->vtx_size = 0x7F; 3599 track->immd_dwords = 0xFFFFFFFFUL; 3600 track->num_arrays = 11; 3601 track->max_indx = 0x00FFFFFFUL; 3602 for (i = 0; i < track->num_arrays; i++) { 3603 track->arrays[i].robj = NULL; 3604 track->arrays[i].esize = 0x7F; 3605 } 3606 for (i = 0; i < track->num_texture; i++) { 3607 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 3608 track->textures[i].pitch = 16536; 3609 track->textures[i].width = 16536; 3610 track->textures[i].height = 16536; 3611 track->textures[i].width_11 = 1 << 11; 3612 track->textures[i].height_11 = 1 << 11; 3613 track->textures[i].num_levels = 12; 3614 if (rdev->family <= CHIP_RS200) { 3615 track->textures[i].tex_coord_type = 0; 3616 track->textures[i].txdepth = 0; 3617 } else { 3618 track->textures[i].txdepth = 16; 3619 track->textures[i].tex_coord_type = 1; 3620 } 3621 track->textures[i].cpp = 64; 3622 track->textures[i].robj = NULL; 3623 /* CS IB emission code makes sure texture unit are disabled */ 3624 track->textures[i].enabled = false; 3625 track->textures[i].lookup_disable = false; 3626 track->textures[i].roundup_w = true; 3627 track->textures[i].roundup_h = true; 3628 if (track->separate_cube) 3629 for (face = 0; face < 5; face++) { 3630 track->textures[i].cube_info[face].robj = NULL; 3631 track->textures[i].cube_info[face].width = 16536; 3632 track->textures[i].cube_info[face].height = 16536; 3633 track->textures[i].cube_info[face].offset = 0; 3634 } 3635 } 3636 } 3637 3638 int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) 3639 { 3640 uint32_t scratch; 3641 uint32_t tmp = 0; 3642 unsigned i; 3643 int r; 3644 3645 r = radeon_scratch_get(rdev, &scratch); 3646 if (r) { 3647 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); 3648 return r; 3649 } 3650 WREG32(scratch, 0xCAFEDEAD); 3651 r = radeon_ring_lock(rdev, ring, 2); 3652 if (r) { 3653 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 3654 radeon_scratch_free(rdev, scratch); 3655 return r; 3656 } 3657 radeon_ring_write(ring, PACKET0(scratch, 0)); 3658 radeon_ring_write(ring, 0xDEADBEEF); 3659 radeon_ring_unlock_commit(rdev, ring); 3660 for (i = 0; i < rdev->usec_timeout; i++) { 3661 tmp = RREG32(scratch); 3662 if (tmp == 0xDEADBEEF) { 3663 break; 3664 } 3665 DRM_UDELAY(1); 3666 } 3667 if (i < rdev->usec_timeout) { 3668 DRM_INFO("ring test succeeded in %d usecs\n", i); 3669 } else { 3670 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n", 3671 scratch, tmp); 3672 r = -EINVAL; 3673 } 3674 radeon_scratch_free(rdev, scratch); 3675 return r; 3676 } 3677 3678 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 3679 { 3680 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 3681 3682 radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1)); 3683 radeon_ring_write(ring, ib->gpu_addr); 3684 radeon_ring_write(ring, ib->length_dw); 3685 } 3686 3687 int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) 3688 { 3689 struct radeon_ib ib; 3690 uint32_t scratch; 3691 uint32_t tmp = 0; 3692 unsigned i; 3693 int r; 3694 3695 r = radeon_scratch_get(rdev, &scratch); 3696 if (r) { 3697 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); 3698 return r; 3699 } 3700 WREG32(scratch, 0xCAFEDEAD); 3701 r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, 256); 3702 if (r) { 3703 return r; 3704 } 3705 ib.ptr[0] = PACKET0(scratch, 0); 3706 ib.ptr[1] = 0xDEADBEEF; 3707 ib.ptr[2] = PACKET2(0); 3708 ib.ptr[3] = PACKET2(0); 3709 ib.ptr[4] = PACKET2(0); 3710 ib.ptr[5] = PACKET2(0); 3711 ib.ptr[6] = PACKET2(0); 3712 ib.ptr[7] = PACKET2(0); 3713 ib.length_dw = 8; 3714 r = radeon_ib_schedule(rdev, &ib); 3715 if (r) { 3716 radeon_scratch_free(rdev, scratch); 3717 radeon_ib_free(rdev, &ib); 3718 return r; 3719 } 3720 r = radeon_fence_wait(ib.fence, false); 3721 if (r) { 3722 return r; 3723 } 3724 for (i = 0; i < rdev->usec_timeout; i++) { 3725 tmp = RREG32(scratch); 3726 if (tmp == 0xDEADBEEF) { 3727 break; 3728 } 3729 DRM_UDELAY(1); 3730 } 3731 if (i < rdev->usec_timeout) { 3732 DRM_INFO("ib test succeeded in %u usecs\n", i); 3733 } else { 3734 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n", 3735 scratch, tmp); 3736 r = -EINVAL; 3737 } 3738 radeon_scratch_free(rdev, scratch); 3739 radeon_ib_free(rdev, &ib); 3740 return r; 3741 } 3742 3743 void r100_ib_fini(struct radeon_device *rdev) 3744 { 3745 radeon_ib_pool_suspend(rdev); 3746 radeon_ib_pool_fini(rdev); 3747 } 3748 3749 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save) 3750 { 3751 /* Shutdown CP we shouldn't need to do that but better be safe than 3752 * sorry 3753 */ 3754 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 3755 WREG32(R_000740_CP_CSQ_CNTL, 0); 3756 3757 /* Save few CRTC registers */ 3758 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT); 3759 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL); 3760 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL); 3761 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET); 3762 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3763 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL); 3764 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET); 3765 } 3766 3767 /* Disable VGA aperture access */ 3768 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT); 3769 /* Disable cursor, overlay, crtc */ 3770 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1)); 3771 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL | 3772 S_000054_CRTC_DISPLAY_DIS(1)); 3773 WREG32(R_000050_CRTC_GEN_CNTL, 3774 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) | 3775 S_000050_CRTC_DISP_REQ_EN_B(1)); 3776 WREG32(R_000420_OV0_SCALE_CNTL, 3777 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL)); 3778 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET); 3779 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3780 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET | 3781 S_000360_CUR2_LOCK(1)); 3782 WREG32(R_0003F8_CRTC2_GEN_CNTL, 3783 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) | 3784 S_0003F8_CRTC2_DISPLAY_DIS(1) | 3785 S_0003F8_CRTC2_DISP_REQ_EN_B(1)); 3786 WREG32(R_000360_CUR2_OFFSET, 3787 C_000360_CUR2_LOCK & save->CUR2_OFFSET); 3788 } 3789 } 3790 3791 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save) 3792 { 3793 /* Update base address for crtc */ 3794 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start); 3795 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3796 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start); 3797 } 3798 /* Restore CRTC registers */ 3799 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT); 3800 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL); 3801 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL); 3802 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3803 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL); 3804 } 3805 } 3806 3807 void r100_vga_render_disable(struct radeon_device *rdev) 3808 { 3809 u32 tmp; 3810 3811 tmp = RREG8(R_0003C2_GENMO_WT); 3812 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp); 3813 } 3814 3815 static void r100_debugfs(struct radeon_device *rdev) 3816 { 3817 int r; 3818 3819 r = r100_debugfs_mc_info_init(rdev); 3820 if (r) 3821 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n"); 3822 } 3823 3824 static void r100_mc_program(struct radeon_device *rdev) 3825 { 3826 struct r100_mc_save save; 3827 3828 /* Stops all mc clients */ 3829 r100_mc_stop(rdev, &save); 3830 if (rdev->flags & RADEON_IS_AGP) { 3831 WREG32(R_00014C_MC_AGP_LOCATION, 3832 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) | 3833 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); 3834 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); 3835 if (rdev->family > CHIP_RV200) 3836 WREG32(R_00015C_AGP_BASE_2, 3837 upper_32_bits(rdev->mc.agp_base) & 0xff); 3838 } else { 3839 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF); 3840 WREG32(R_000170_AGP_BASE, 0); 3841 if (rdev->family > CHIP_RV200) 3842 WREG32(R_00015C_AGP_BASE_2, 0); 3843 } 3844 /* Wait for mc idle */ 3845 if (r100_mc_wait_for_idle(rdev)) 3846 dev_warn(rdev->dev, "Wait for MC idle timeout.\n"); 3847 /* Program MC, should be a 32bits limited address space */ 3848 WREG32(R_000148_MC_FB_LOCATION, 3849 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | 3850 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); 3851 r100_mc_resume(rdev, &save); 3852 } 3853 3854 void r100_clock_startup(struct radeon_device *rdev) 3855 { 3856 u32 tmp; 3857 3858 if (radeon_dynclks != -1 && radeon_dynclks) 3859 radeon_legacy_set_clock_gating(rdev, 1); 3860 /* We need to force on some of the block */ 3861 tmp = RREG32_PLL(R_00000D_SCLK_CNTL); 3862 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); 3863 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280)) 3864 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1); 3865 WREG32_PLL(R_00000D_SCLK_CNTL, tmp); 3866 } 3867 3868 static int r100_startup(struct radeon_device *rdev) 3869 { 3870 int r; 3871 3872 /* set common regs */ 3873 r100_set_common_regs(rdev); 3874 /* program mc */ 3875 r100_mc_program(rdev); 3876 /* Resume clock */ 3877 r100_clock_startup(rdev); 3878 /* Initialize GART (initialize after TTM so we can allocate 3879 * memory through TTM but finalize after TTM) */ 3880 r100_enable_bm(rdev); 3881 if (rdev->flags & RADEON_IS_PCI) { 3882 r = r100_pci_gart_enable(rdev); 3883 if (r) 3884 return r; 3885 } 3886 3887 /* allocate wb buffer */ 3888 r = radeon_wb_init(rdev); 3889 if (r) 3890 return r; 3891 3892 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 3893 if (r) { 3894 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 3895 return r; 3896 } 3897 3898 /* Enable IRQ */ 3899 r100_irq_set(rdev); 3900 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 3901 /* 1M ring buffer */ 3902 r = r100_cp_init(rdev, 1024 * 1024); 3903 if (r) { 3904 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 3905 return r; 3906 } 3907 3908 r = radeon_ib_pool_start(rdev); 3909 if (r) 3910 return r; 3911 3912 r = radeon_ib_ring_tests(rdev); 3913 if (r) 3914 return r; 3915 3916 return 0; 3917 } 3918 3919 int r100_resume(struct radeon_device *rdev) 3920 { 3921 int r; 3922 3923 /* Make sur GART are not working */ 3924 if (rdev->flags & RADEON_IS_PCI) 3925 r100_pci_gart_disable(rdev); 3926 /* Resume clock before doing reset */ 3927 r100_clock_startup(rdev); 3928 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 3929 if (radeon_asic_reset(rdev)) { 3930 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 3931 RREG32(R_000E40_RBBM_STATUS), 3932 RREG32(R_0007C0_CP_STAT)); 3933 } 3934 /* post */ 3935 radeon_combios_asic_init(rdev->ddev); 3936 /* Resume clock after posting */ 3937 r100_clock_startup(rdev); 3938 /* Initialize surface registers */ 3939 radeon_surface_init(rdev); 3940 3941 rdev->accel_working = true; 3942 r = r100_startup(rdev); 3943 if (r) { 3944 rdev->accel_working = false; 3945 } 3946 return r; 3947 } 3948 3949 int r100_suspend(struct radeon_device *rdev) 3950 { 3951 radeon_ib_pool_suspend(rdev); 3952 r100_cp_disable(rdev); 3953 radeon_wb_disable(rdev); 3954 r100_irq_disable(rdev); 3955 if (rdev->flags & RADEON_IS_PCI) 3956 r100_pci_gart_disable(rdev); 3957 return 0; 3958 } 3959 3960 void r100_fini(struct radeon_device *rdev) 3961 { 3962 r100_cp_fini(rdev); 3963 radeon_wb_fini(rdev); 3964 r100_ib_fini(rdev); 3965 radeon_gem_fini(rdev); 3966 if (rdev->flags & RADEON_IS_PCI) 3967 r100_pci_gart_fini(rdev); 3968 radeon_agp_fini(rdev); 3969 radeon_irq_kms_fini(rdev); 3970 radeon_fence_driver_fini(rdev); 3971 radeon_bo_fini(rdev); 3972 radeon_atombios_fini(rdev); 3973 kfree(rdev->bios); 3974 rdev->bios = NULL; 3975 } 3976 3977 /* 3978 * Due to how kexec works, it can leave the hw fully initialised when it 3979 * boots the new kernel. However doing our init sequence with the CP and 3980 * WB stuff setup causes GPU hangs on the RN50 at least. So at startup 3981 * do some quick sanity checks and restore sane values to avoid this 3982 * problem. 3983 */ 3984 void r100_restore_sanity(struct radeon_device *rdev) 3985 { 3986 u32 tmp; 3987 3988 tmp = RREG32(RADEON_CP_CSQ_CNTL); 3989 if (tmp) { 3990 WREG32(RADEON_CP_CSQ_CNTL, 0); 3991 } 3992 tmp = RREG32(RADEON_CP_RB_CNTL); 3993 if (tmp) { 3994 WREG32(RADEON_CP_RB_CNTL, 0); 3995 } 3996 tmp = RREG32(RADEON_SCRATCH_UMSK); 3997 if (tmp) { 3998 WREG32(RADEON_SCRATCH_UMSK, 0); 3999 } 4000 } 4001 4002 int r100_init(struct radeon_device *rdev) 4003 { 4004 int r; 4005 4006 /* Register debugfs file specific to this group of asics */ 4007 r100_debugfs(rdev); 4008 /* Disable VGA */ 4009 r100_vga_render_disable(rdev); 4010 /* Initialize scratch registers */ 4011 radeon_scratch_init(rdev); 4012 /* Initialize surface registers */ 4013 radeon_surface_init(rdev); 4014 /* sanity check some register to avoid hangs like after kexec */ 4015 r100_restore_sanity(rdev); 4016 /* TODO: disable VGA need to use VGA request */ 4017 /* BIOS*/ 4018 if (!radeon_get_bios(rdev)) { 4019 if (ASIC_IS_AVIVO(rdev)) 4020 return -EINVAL; 4021 } 4022 if (rdev->is_atom_bios) { 4023 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); 4024 return -EINVAL; 4025 } else { 4026 r = radeon_combios_init(rdev); 4027 if (r) 4028 return r; 4029 } 4030 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 4031 if (radeon_asic_reset(rdev)) { 4032 dev_warn(rdev->dev, 4033 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 4034 RREG32(R_000E40_RBBM_STATUS), 4035 RREG32(R_0007C0_CP_STAT)); 4036 } 4037 /* check if cards are posted or not */ 4038 if (radeon_boot_test_post_card(rdev) == false) 4039 return -EINVAL; 4040 /* Set asic errata */ 4041 r100_errata(rdev); 4042 /* Initialize clocks */ 4043 radeon_get_clock_info(rdev->ddev); 4044 /* initialize AGP */ 4045 if (rdev->flags & RADEON_IS_AGP) { 4046 r = radeon_agp_init(rdev); 4047 if (r) { 4048 radeon_agp_disable(rdev); 4049 } 4050 } 4051 /* initialize VRAM */ 4052 r100_mc_init(rdev); 4053 /* Fence driver */ 4054 r = radeon_fence_driver_init(rdev); 4055 if (r) 4056 return r; 4057 r = radeon_irq_kms_init(rdev); 4058 if (r) 4059 return r; 4060 /* Memory manager */ 4061 r = radeon_bo_init(rdev); 4062 if (r) 4063 return r; 4064 if (rdev->flags & RADEON_IS_PCI) { 4065 r = r100_pci_gart_init(rdev); 4066 if (r) 4067 return r; 4068 } 4069 r100_set_safe_registers(rdev); 4070 4071 r = radeon_ib_pool_init(rdev); 4072 rdev->accel_working = true; 4073 if (r) { 4074 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 4075 rdev->accel_working = false; 4076 } 4077 4078 r = r100_startup(rdev); 4079 if (r) { 4080 /* Somethings want wront with the accel init stop accel */ 4081 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 4082 r100_cp_fini(rdev); 4083 radeon_wb_fini(rdev); 4084 r100_ib_fini(rdev); 4085 radeon_irq_kms_fini(rdev); 4086 if (rdev->flags & RADEON_IS_PCI) 4087 r100_pci_gart_fini(rdev); 4088 rdev->accel_working = false; 4089 } 4090 return 0; 4091 } 4092 4093 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg) 4094 { 4095 if (reg < rdev->rmmio_size) 4096 return readl(((void __iomem *)rdev->rmmio) + reg); 4097 else { 4098 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); 4099 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); 4100 } 4101 } 4102 4103 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 4104 { 4105 if (reg < rdev->rmmio_size) 4106 writel(v, ((void __iomem *)rdev->rmmio) + reg); 4107 else { 4108 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); 4109 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); 4110 } 4111 } 4112 4113 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg) 4114 { 4115 if (reg < rdev->rio_mem_size) 4116 return ioread32(rdev->rio_mem + reg); 4117 else { 4118 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX); 4119 return ioread32(rdev->rio_mem + RADEON_MM_DATA); 4120 } 4121 } 4122 4123 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v) 4124 { 4125 if (reg < rdev->rio_mem_size) 4126 iowrite32(v, rdev->rio_mem + reg); 4127 else { 4128 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX); 4129 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA); 4130 } 4131 } 4132