1 /* 2 * Copyright 2012 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef __NISLANDS_SMC_H__ 24 #define __NISLANDS_SMC_H__ 25 26 #pragma pack(push, 1) 27 28 #define NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE 16 29 30 struct PP_NIslands_Dpm2PerfLevel 31 { 32 uint8_t MaxPS; 33 uint8_t TgtAct; 34 uint8_t MaxPS_StepInc; 35 uint8_t MaxPS_StepDec; 36 uint8_t PSST; 37 uint8_t NearTDPDec; 38 uint8_t AboveSafeInc; 39 uint8_t BelowSafeInc; 40 uint8_t PSDeltaLimit; 41 uint8_t PSDeltaWin; 42 uint8_t Reserved[6]; 43 }; 44 45 typedef struct PP_NIslands_Dpm2PerfLevel PP_NIslands_Dpm2PerfLevel; 46 47 struct PP_NIslands_DPM2Parameters 48 { 49 uint32_t TDPLimit; 50 uint32_t NearTDPLimit; 51 uint32_t SafePowerLimit; 52 uint32_t PowerBoostLimit; 53 }; 54 typedef struct PP_NIslands_DPM2Parameters PP_NIslands_DPM2Parameters; 55 56 struct NISLANDS_SMC_SCLK_VALUE 57 { 58 uint32_t vCG_SPLL_FUNC_CNTL; 59 uint32_t vCG_SPLL_FUNC_CNTL_2; 60 uint32_t vCG_SPLL_FUNC_CNTL_3; 61 uint32_t vCG_SPLL_FUNC_CNTL_4; 62 uint32_t vCG_SPLL_SPREAD_SPECTRUM; 63 uint32_t vCG_SPLL_SPREAD_SPECTRUM_2; 64 uint32_t sclk_value; 65 }; 66 67 typedef struct NISLANDS_SMC_SCLK_VALUE NISLANDS_SMC_SCLK_VALUE; 68 69 struct NISLANDS_SMC_MCLK_VALUE 70 { 71 uint32_t vMPLL_FUNC_CNTL; 72 uint32_t vMPLL_FUNC_CNTL_1; 73 uint32_t vMPLL_FUNC_CNTL_2; 74 uint32_t vMPLL_AD_FUNC_CNTL; 75 uint32_t vMPLL_AD_FUNC_CNTL_2; 76 uint32_t vMPLL_DQ_FUNC_CNTL; 77 uint32_t vMPLL_DQ_FUNC_CNTL_2; 78 uint32_t vMCLK_PWRMGT_CNTL; 79 uint32_t vDLL_CNTL; 80 uint32_t vMPLL_SS; 81 uint32_t vMPLL_SS2; 82 uint32_t mclk_value; 83 }; 84 85 typedef struct NISLANDS_SMC_MCLK_VALUE NISLANDS_SMC_MCLK_VALUE; 86 87 struct NISLANDS_SMC_VOLTAGE_VALUE 88 { 89 uint16_t value; 90 uint8_t index; 91 uint8_t padding; 92 }; 93 94 typedef struct NISLANDS_SMC_VOLTAGE_VALUE NISLANDS_SMC_VOLTAGE_VALUE; 95 96 struct NISLANDS_SMC_HW_PERFORMANCE_LEVEL 97 { 98 uint8_t arbValue; 99 uint8_t ACIndex; 100 uint8_t displayWatermark; 101 uint8_t gen2PCIE; 102 uint8_t reserved1; 103 uint8_t reserved2; 104 uint8_t strobeMode; 105 uint8_t mcFlags; 106 uint32_t aT; 107 uint32_t bSP; 108 NISLANDS_SMC_SCLK_VALUE sclk; 109 NISLANDS_SMC_MCLK_VALUE mclk; 110 NISLANDS_SMC_VOLTAGE_VALUE vddc; 111 NISLANDS_SMC_VOLTAGE_VALUE mvdd; 112 NISLANDS_SMC_VOLTAGE_VALUE vddci; 113 NISLANDS_SMC_VOLTAGE_VALUE std_vddc; 114 uint32_t powergate_en; 115 uint8_t hUp; 116 uint8_t hDown; 117 uint8_t stateFlags; 118 uint8_t arbRefreshState; 119 uint32_t SQPowerThrottle; 120 uint32_t SQPowerThrottle_2; 121 uint32_t reserved[2]; 122 PP_NIslands_Dpm2PerfLevel dpm2; 123 }; 124 125 #define NISLANDS_SMC_STROBE_RATIO 0x0F 126 #define NISLANDS_SMC_STROBE_ENABLE 0x10 127 128 #define NISLANDS_SMC_MC_EDC_RD_FLAG 0x01 129 #define NISLANDS_SMC_MC_EDC_WR_FLAG 0x02 130 #define NISLANDS_SMC_MC_RTT_ENABLE 0x04 131 #define NISLANDS_SMC_MC_STUTTER_EN 0x08 132 133 typedef struct NISLANDS_SMC_HW_PERFORMANCE_LEVEL NISLANDS_SMC_HW_PERFORMANCE_LEVEL; 134 135 struct NISLANDS_SMC_SWSTATE 136 { 137 uint8_t flags; 138 uint8_t levelCount; 139 uint8_t padding2; 140 uint8_t padding3; 141 NISLANDS_SMC_HW_PERFORMANCE_LEVEL levels[]; 142 }; 143 144 typedef struct NISLANDS_SMC_SWSTATE NISLANDS_SMC_SWSTATE; 145 146 struct NISLANDS_SMC_SWSTATE_SINGLE { 147 uint8_t flags; 148 uint8_t levelCount; 149 uint8_t padding2; 150 uint8_t padding3; 151 NISLANDS_SMC_HW_PERFORMANCE_LEVEL level; 152 }; 153 154 #define NISLANDS_SMC_VOLTAGEMASK_VDDC 0 155 #define NISLANDS_SMC_VOLTAGEMASK_MVDD 1 156 #define NISLANDS_SMC_VOLTAGEMASK_VDDCI 2 157 #define NISLANDS_SMC_VOLTAGEMASK_MAX 4 158 159 struct NISLANDS_SMC_VOLTAGEMASKTABLE 160 { 161 uint8_t highMask[NISLANDS_SMC_VOLTAGEMASK_MAX]; 162 uint32_t lowMask[NISLANDS_SMC_VOLTAGEMASK_MAX]; 163 }; 164 165 typedef struct NISLANDS_SMC_VOLTAGEMASKTABLE NISLANDS_SMC_VOLTAGEMASKTABLE; 166 167 #define NISLANDS_MAX_NO_VREG_STEPS 32 168 169 struct NISLANDS_SMC_STATETABLE 170 { 171 uint8_t thermalProtectType; 172 uint8_t systemFlags; 173 uint8_t maxVDDCIndexInPPTable; 174 uint8_t extraFlags; 175 uint8_t highSMIO[NISLANDS_MAX_NO_VREG_STEPS]; 176 uint32_t lowSMIO[NISLANDS_MAX_NO_VREG_STEPS]; 177 NISLANDS_SMC_VOLTAGEMASKTABLE voltageMaskTable; 178 PP_NIslands_DPM2Parameters dpm2Params; 179 struct NISLANDS_SMC_SWSTATE_SINGLE initialState; 180 struct NISLANDS_SMC_SWSTATE_SINGLE ACPIState; 181 struct NISLANDS_SMC_SWSTATE_SINGLE ULVState; 182 NISLANDS_SMC_SWSTATE driverState; 183 NISLANDS_SMC_HW_PERFORMANCE_LEVEL dpmLevels[NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE]; 184 }; 185 186 typedef struct NISLANDS_SMC_STATETABLE NISLANDS_SMC_STATETABLE; 187 188 #define NI_SMC_SOFT_REGISTERS_START 0x108 189 190 #define NI_SMC_SOFT_REGISTER_mclk_chg_timeout 0x0 191 #define NI_SMC_SOFT_REGISTER_delay_bbias 0xC 192 #define NI_SMC_SOFT_REGISTER_delay_vreg 0x10 193 #define NI_SMC_SOFT_REGISTER_delay_acpi 0x2C 194 #define NI_SMC_SOFT_REGISTER_seq_index 0x64 195 #define NI_SMC_SOFT_REGISTER_mvdd_chg_time 0x68 196 #define NI_SMC_SOFT_REGISTER_mclk_switch_lim 0x78 197 #define NI_SMC_SOFT_REGISTER_watermark_threshold 0x80 198 #define NI_SMC_SOFT_REGISTER_mc_block_delay 0x84 199 #define NI_SMC_SOFT_REGISTER_uvd_enabled 0x98 200 201 #define SMC_NISLANDS_MC_TPP_CAC_NUM_OF_ENTRIES 16 202 #define SMC_NISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES 16 203 #define SMC_NISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES 16 204 #define SMC_NISLANDS_BIF_LUT_NUM_OF_ENTRIES 4 205 206 struct SMC_NISLANDS_MC_TPP_CAC_TABLE 207 { 208 uint32_t tpp[SMC_NISLANDS_MC_TPP_CAC_NUM_OF_ENTRIES]; 209 uint32_t cacValue[SMC_NISLANDS_MC_TPP_CAC_NUM_OF_ENTRIES]; 210 }; 211 212 typedef struct SMC_NISLANDS_MC_TPP_CAC_TABLE SMC_NISLANDS_MC_TPP_CAC_TABLE; 213 214 215 struct PP_NIslands_CACTABLES 216 { 217 uint32_t cac_bif_lut[SMC_NISLANDS_BIF_LUT_NUM_OF_ENTRIES]; 218 uint32_t cac_lkge_lut[SMC_NISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES][SMC_NISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES]; 219 220 uint32_t pwr_const; 221 222 uint32_t dc_cacValue; 223 uint32_t bif_cacValue; 224 uint32_t lkge_pwr; 225 226 uint8_t cac_width; 227 uint8_t window_size_p2; 228 229 uint8_t num_drop_lsb; 230 uint8_t padding_0; 231 232 uint32_t last_power; 233 234 uint8_t AllowOvrflw; 235 uint8_t MCWrWeight; 236 uint8_t MCRdWeight; 237 uint8_t padding_1[9]; 238 239 uint8_t enableWinAvg; 240 uint8_t numWin_TDP; 241 uint8_t l2numWin_TDP; 242 uint8_t WinIndex; 243 244 uint32_t dynPwr_TDP[4]; 245 uint32_t lkgePwr_TDP[4]; 246 uint32_t power_TDP[4]; 247 uint32_t avg_dynPwr_TDP; 248 uint32_t avg_lkgePwr_TDP; 249 uint32_t avg_power_TDP; 250 uint32_t lts_power_TDP; 251 uint8_t lts_truncate_n; 252 uint8_t padding_2[7]; 253 }; 254 255 typedef struct PP_NIslands_CACTABLES PP_NIslands_CACTABLES; 256 257 #define SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE 32 258 #define SMC_NISLANDS_MC_REGISTER_ARRAY_SET_COUNT 20 259 260 struct SMC_NIslands_MCRegisterAddress 261 { 262 uint16_t s0; 263 uint16_t s1; 264 }; 265 266 typedef struct SMC_NIslands_MCRegisterAddress SMC_NIslands_MCRegisterAddress; 267 268 269 struct SMC_NIslands_MCRegisterSet 270 { 271 uint32_t value[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE]; 272 }; 273 274 typedef struct SMC_NIslands_MCRegisterSet SMC_NIslands_MCRegisterSet; 275 276 struct SMC_NIslands_MCRegisters 277 { 278 uint8_t last; 279 uint8_t reserved[3]; 280 SMC_NIslands_MCRegisterAddress address[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE]; 281 SMC_NIslands_MCRegisterSet data[SMC_NISLANDS_MC_REGISTER_ARRAY_SET_COUNT]; 282 }; 283 284 typedef struct SMC_NIslands_MCRegisters SMC_NIslands_MCRegisters; 285 286 struct SMC_NIslands_MCArbDramTimingRegisterSet 287 { 288 uint32_t mc_arb_dram_timing; 289 uint32_t mc_arb_dram_timing2; 290 uint8_t mc_arb_rfsh_rate; 291 uint8_t padding[3]; 292 }; 293 294 typedef struct SMC_NIslands_MCArbDramTimingRegisterSet SMC_NIslands_MCArbDramTimingRegisterSet; 295 296 struct SMC_NIslands_MCArbDramTimingRegisters 297 { 298 uint8_t arb_current; 299 uint8_t reserved[3]; 300 SMC_NIslands_MCArbDramTimingRegisterSet data[20]; 301 }; 302 303 typedef struct SMC_NIslands_MCArbDramTimingRegisters SMC_NIslands_MCArbDramTimingRegisters; 304 305 struct SMC_NISLANDS_SPLL_DIV_TABLE 306 { 307 uint32_t freq[256]; 308 uint32_t ss[256]; 309 }; 310 311 #define SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_MASK 0x01ffffff 312 #define SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT 0 313 #define SMC_NISLANDS_SPLL_DIV_TABLE_PDIV_MASK 0xfe000000 314 #define SMC_NISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT 25 315 #define SMC_NISLANDS_SPLL_DIV_TABLE_CLKV_MASK 0x000fffff 316 #define SMC_NISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT 0 317 #define SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_MASK 0xfff00000 318 #define SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT 20 319 320 typedef struct SMC_NISLANDS_SPLL_DIV_TABLE SMC_NISLANDS_SPLL_DIV_TABLE; 321 322 #define NISLANDS_SMC_FIRMWARE_HEADER_LOCATION 0x100 323 324 #define NISLANDS_SMC_FIRMWARE_HEADER_version 0x0 325 #define NISLANDS_SMC_FIRMWARE_HEADER_flags 0x4 326 #define NISLANDS_SMC_FIRMWARE_HEADER_softRegisters 0x8 327 #define NISLANDS_SMC_FIRMWARE_HEADER_stateTable 0xC 328 #define NISLANDS_SMC_FIRMWARE_HEADER_fanTable 0x10 329 #define NISLANDS_SMC_FIRMWARE_HEADER_cacTable 0x14 330 #define NISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable 0x20 331 #define NISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable 0x2C 332 #define NISLANDS_SMC_FIRMWARE_HEADER_spllTable 0x30 333 334 #pragma pack(pop) 335 336 #endif 337 338