1 /* 2 * Copyright 2010 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 #ifndef NI_H 25 #define NI_H 26 27 #define CAYMAN_MAX_SH_GPRS 256 28 #define CAYMAN_MAX_TEMP_GPRS 16 29 #define CAYMAN_MAX_SH_THREADS 256 30 #define CAYMAN_MAX_SH_STACK_ENTRIES 4096 31 #define CAYMAN_MAX_FRC_EOV_CNT 16384 32 #define CAYMAN_MAX_BACKENDS 8 33 #define CAYMAN_MAX_BACKENDS_MASK 0xFF 34 #define CAYMAN_MAX_BACKENDS_PER_SE_MASK 0xF 35 #define CAYMAN_MAX_SIMDS 16 36 #define CAYMAN_MAX_SIMDS_MASK 0xFFFF 37 #define CAYMAN_MAX_SIMDS_PER_SE_MASK 0xFFF 38 #define CAYMAN_MAX_PIPES 8 39 #define CAYMAN_MAX_PIPES_MASK 0xFF 40 #define CAYMAN_MAX_LDS_NUM 0xFFFF 41 #define CAYMAN_MAX_TCC 16 42 #define CAYMAN_MAX_TCC_MASK 0xFF 43 44 #define CAYMAN_GB_ADDR_CONFIG_GOLDEN 0x02011003 45 #define ARUBA_GB_ADDR_CONFIG_GOLDEN 0x12010001 46 47 #define DMIF_ADDR_CONFIG 0xBD4 48 #define SRBM_GFX_CNTL 0x0E44 49 #define RINGID(x) (((x) & 0x3) << 0) 50 #define VMID(x) (((x) & 0x7) << 0) 51 #define SRBM_STATUS 0x0E50 52 53 #define SRBM_SOFT_RESET 0x0E60 54 #define SOFT_RESET_BIF (1 << 1) 55 #define SOFT_RESET_CG (1 << 2) 56 #define SOFT_RESET_DC (1 << 5) 57 #define SOFT_RESET_DMA1 (1 << 6) 58 #define SOFT_RESET_GRBM (1 << 8) 59 #define SOFT_RESET_HDP (1 << 9) 60 #define SOFT_RESET_IH (1 << 10) 61 #define SOFT_RESET_MC (1 << 11) 62 #define SOFT_RESET_RLC (1 << 13) 63 #define SOFT_RESET_ROM (1 << 14) 64 #define SOFT_RESET_SEM (1 << 15) 65 #define SOFT_RESET_VMC (1 << 17) 66 #define SOFT_RESET_DMA (1 << 20) 67 #define SOFT_RESET_TST (1 << 21) 68 #define SOFT_RESET_REGBB (1 << 22) 69 #define SOFT_RESET_ORB (1 << 23) 70 71 #define VM_CONTEXT0_REQUEST_RESPONSE 0x1470 72 #define REQUEST_TYPE(x) (((x) & 0xf) << 0) 73 #define RESPONSE_TYPE_MASK 0x000000F0 74 #define RESPONSE_TYPE_SHIFT 4 75 #define VM_L2_CNTL 0x1400 76 #define ENABLE_L2_CACHE (1 << 0) 77 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 78 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 79 #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10) 80 #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14) 81 #define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 18) 82 /* CONTEXT1_IDENTITY_ACCESS_MODE 83 * 0 physical = logical 84 * 1 logical via context1 page table 85 * 2 inside identity aperture use translation, outside physical = logical 86 * 3 inside identity aperture physical = logical, outside use translation 87 */ 88 #define VM_L2_CNTL2 0x1404 89 #define INVALIDATE_ALL_L1_TLBS (1 << 0) 90 #define INVALIDATE_L2_CACHE (1 << 1) 91 #define VM_L2_CNTL3 0x1408 92 #define BANK_SELECT(x) ((x) << 0) 93 #define CACHE_UPDATE_MODE(x) ((x) << 6) 94 #define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20) 95 #define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15) 96 #define VM_L2_STATUS 0x140C 97 #define L2_BUSY (1 << 0) 98 #define VM_CONTEXT0_CNTL 0x1410 99 #define ENABLE_CONTEXT (1 << 0) 100 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 101 #define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3) 102 #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 103 #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6) 104 #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7) 105 #define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9) 106 #define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10) 107 #define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12) 108 #define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13) 109 #define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15) 110 #define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16) 111 #define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18) 112 #define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19) 113 #define VM_CONTEXT1_CNTL 0x1414 114 #define VM_CONTEXT0_CNTL2 0x1430 115 #define VM_CONTEXT1_CNTL2 0x1434 116 #define VM_INVALIDATE_REQUEST 0x1478 117 #define VM_INVALIDATE_RESPONSE 0x147c 118 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 119 #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c 120 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C 121 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C 122 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C 123 124 #define MC_SHARED_CHMAP 0x2004 125 #define NOOFCHAN_SHIFT 12 126 #define NOOFCHAN_MASK 0x00003000 127 #define MC_SHARED_CHREMAP 0x2008 128 129 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 130 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 131 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C 132 #define MC_VM_MX_L1_TLB_CNTL 0x2064 133 #define ENABLE_L1_TLB (1 << 0) 134 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 135 #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) 136 #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) 137 #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 138 #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) 139 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 140 #define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6) 141 #define FUS_MC_VM_FB_OFFSET 0x2068 142 143 #define MC_SHARED_BLACKOUT_CNTL 0x20ac 144 #define MC_ARB_RAMCFG 0x2760 145 #define NOOFBANK_SHIFT 0 146 #define NOOFBANK_MASK 0x00000003 147 #define NOOFRANK_SHIFT 2 148 #define NOOFRANK_MASK 0x00000004 149 #define NOOFROWS_SHIFT 3 150 #define NOOFROWS_MASK 0x00000038 151 #define NOOFCOLS_SHIFT 6 152 #define NOOFCOLS_MASK 0x000000C0 153 #define CHANSIZE_SHIFT 8 154 #define CHANSIZE_MASK 0x00000100 155 #define BURSTLENGTH_SHIFT 9 156 #define BURSTLENGTH_MASK 0x00000200 157 #define CHANSIZE_OVERRIDE (1 << 11) 158 #define MC_SEQ_SUP_CNTL 0x28c8 159 #define RUN_MASK (1 << 0) 160 #define MC_SEQ_SUP_PGM 0x28cc 161 #define MC_IO_PAD_CNTL_D0 0x29d0 162 #define MEM_FALL_OUT_CMD (1 << 8) 163 #define MC_SEQ_MISC0 0x2a00 164 #define MC_SEQ_MISC0_GDDR5_SHIFT 28 165 #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000 166 #define MC_SEQ_MISC0_GDDR5_VALUE 5 167 #define MC_SEQ_IO_DEBUG_INDEX 0x2a44 168 #define MC_SEQ_IO_DEBUG_DATA 0x2a48 169 170 #define HDP_HOST_PATH_CNTL 0x2C00 171 #define HDP_NONSURFACE_BASE 0x2C04 172 #define HDP_NONSURFACE_INFO 0x2C08 173 #define HDP_NONSURFACE_SIZE 0x2C0C 174 #define HDP_ADDR_CONFIG 0x2F48 175 #define HDP_MISC_CNTL 0x2F4C 176 #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0) 177 178 #define CC_SYS_RB_BACKEND_DISABLE 0x3F88 179 #define GC_USER_SYS_RB_BACKEND_DISABLE 0x3F8C 180 #define CGTS_SYS_TCC_DISABLE 0x3F90 181 #define CGTS_USER_SYS_TCC_DISABLE 0x3F94 182 183 #define RLC_GFX_INDEX 0x3FC4 184 185 #define CONFIG_MEMSIZE 0x5428 186 187 #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 188 #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 189 190 #define GRBM_CNTL 0x8000 191 #define GRBM_READ_TIMEOUT(x) ((x) << 0) 192 #define GRBM_STATUS 0x8010 193 #define CMDFIFO_AVAIL_MASK 0x0000000F 194 #define RING2_RQ_PENDING (1 << 4) 195 #define SRBM_RQ_PENDING (1 << 5) 196 #define RING1_RQ_PENDING (1 << 6) 197 #define CF_RQ_PENDING (1 << 7) 198 #define PF_RQ_PENDING (1 << 8) 199 #define GDS_DMA_RQ_PENDING (1 << 9) 200 #define GRBM_EE_BUSY (1 << 10) 201 #define SX_CLEAN (1 << 11) 202 #define DB_CLEAN (1 << 12) 203 #define CB_CLEAN (1 << 13) 204 #define TA_BUSY (1 << 14) 205 #define GDS_BUSY (1 << 15) 206 #define VGT_BUSY_NO_DMA (1 << 16) 207 #define VGT_BUSY (1 << 17) 208 #define IA_BUSY_NO_DMA (1 << 18) 209 #define IA_BUSY (1 << 19) 210 #define SX_BUSY (1 << 20) 211 #define SH_BUSY (1 << 21) 212 #define SPI_BUSY (1 << 22) 213 #define SC_BUSY (1 << 24) 214 #define PA_BUSY (1 << 25) 215 #define DB_BUSY (1 << 26) 216 #define CP_COHERENCY_BUSY (1 << 28) 217 #define CP_BUSY (1 << 29) 218 #define CB_BUSY (1 << 30) 219 #define GUI_ACTIVE (1 << 31) 220 #define GRBM_STATUS_SE0 0x8014 221 #define GRBM_STATUS_SE1 0x8018 222 #define SE_SX_CLEAN (1 << 0) 223 #define SE_DB_CLEAN (1 << 1) 224 #define SE_CB_CLEAN (1 << 2) 225 #define SE_VGT_BUSY (1 << 23) 226 #define SE_PA_BUSY (1 << 24) 227 #define SE_TA_BUSY (1 << 25) 228 #define SE_SX_BUSY (1 << 26) 229 #define SE_SPI_BUSY (1 << 27) 230 #define SE_SH_BUSY (1 << 28) 231 #define SE_SC_BUSY (1 << 29) 232 #define SE_DB_BUSY (1 << 30) 233 #define SE_CB_BUSY (1 << 31) 234 #define GRBM_SOFT_RESET 0x8020 235 #define SOFT_RESET_CP (1 << 0) 236 #define SOFT_RESET_CB (1 << 1) 237 #define SOFT_RESET_DB (1 << 3) 238 #define SOFT_RESET_GDS (1 << 4) 239 #define SOFT_RESET_PA (1 << 5) 240 #define SOFT_RESET_SC (1 << 6) 241 #define SOFT_RESET_SPI (1 << 8) 242 #define SOFT_RESET_SH (1 << 9) 243 #define SOFT_RESET_SX (1 << 10) 244 #define SOFT_RESET_TC (1 << 11) 245 #define SOFT_RESET_TA (1 << 12) 246 #define SOFT_RESET_VGT (1 << 14) 247 #define SOFT_RESET_IA (1 << 15) 248 249 #define GRBM_GFX_INDEX 0x802C 250 #define INSTANCE_INDEX(x) ((x) << 0) 251 #define SE_INDEX(x) ((x) << 16) 252 #define INSTANCE_BROADCAST_WRITES (1 << 30) 253 #define SE_BROADCAST_WRITES (1 << 31) 254 255 #define SCRATCH_REG0 0x8500 256 #define SCRATCH_REG1 0x8504 257 #define SCRATCH_REG2 0x8508 258 #define SCRATCH_REG3 0x850C 259 #define SCRATCH_REG4 0x8510 260 #define SCRATCH_REG5 0x8514 261 #define SCRATCH_REG6 0x8518 262 #define SCRATCH_REG7 0x851C 263 #define SCRATCH_UMSK 0x8540 264 #define SCRATCH_ADDR 0x8544 265 #define CP_SEM_WAIT_TIMER 0x85BC 266 #define CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8 267 #define CP_COHER_CNTL2 0x85E8 268 #define CP_STALLED_STAT1 0x8674 269 #define CP_STALLED_STAT2 0x8678 270 #define CP_BUSY_STAT 0x867C 271 #define CP_STAT 0x8680 272 #define CP_ME_CNTL 0x86D8 273 #define CP_ME_HALT (1 << 28) 274 #define CP_PFP_HALT (1 << 26) 275 #define CP_RB2_RPTR 0x86f8 276 #define CP_RB1_RPTR 0x86fc 277 #define CP_RB0_RPTR 0x8700 278 #define CP_RB_WPTR_DELAY 0x8704 279 #define CP_MEQ_THRESHOLDS 0x8764 280 #define MEQ1_START(x) ((x) << 0) 281 #define MEQ2_START(x) ((x) << 8) 282 #define CP_PERFMON_CNTL 0x87FC 283 284 #define VGT_CACHE_INVALIDATION 0x88C4 285 #define CACHE_INVALIDATION(x) ((x) << 0) 286 #define VC_ONLY 0 287 #define TC_ONLY 1 288 #define VC_AND_TC 2 289 #define AUTO_INVLD_EN(x) ((x) << 6) 290 #define NO_AUTO 0 291 #define ES_AUTO 1 292 #define GS_AUTO 2 293 #define ES_AND_GS_AUTO 3 294 #define VGT_GS_VERTEX_REUSE 0x88D4 295 296 #define CC_GC_SHADER_PIPE_CONFIG 0x8950 297 #define GC_USER_SHADER_PIPE_CONFIG 0x8954 298 #define INACTIVE_QD_PIPES(x) ((x) << 8) 299 #define INACTIVE_QD_PIPES_MASK 0x0000FF00 300 #define INACTIVE_QD_PIPES_SHIFT 8 301 #define INACTIVE_SIMDS(x) ((x) << 16) 302 #define INACTIVE_SIMDS_MASK 0xFFFF0000 303 #define INACTIVE_SIMDS_SHIFT 16 304 305 #define VGT_PRIMITIVE_TYPE 0x8958 306 #define VGT_NUM_INSTANCES 0x8974 307 #define VGT_TF_RING_SIZE 0x8988 308 #define VGT_OFFCHIP_LDS_BASE 0x89b4 309 310 #define PA_SC_LINE_STIPPLE_STATE 0x8B10 311 #define PA_CL_ENHANCE 0x8A14 312 #define CLIP_VTX_REORDER_ENA (1 << 0) 313 #define NUM_CLIP_SEQ(x) ((x) << 1) 314 #define PA_SC_FIFO_SIZE 0x8BCC 315 #define SC_PRIM_FIFO_SIZE(x) ((x) << 0) 316 #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12) 317 #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20) 318 #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 319 #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 320 #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) 321 322 #define SQ_CONFIG 0x8C00 323 #define VC_ENABLE (1 << 0) 324 #define EXPORT_SRC_C (1 << 1) 325 #define GFX_PRIO(x) ((x) << 2) 326 #define CS1_PRIO(x) ((x) << 4) 327 #define CS2_PRIO(x) ((x) << 6) 328 #define SQ_GPR_RESOURCE_MGMT_1 0x8C04 329 #define NUM_PS_GPRS(x) ((x) << 0) 330 #define NUM_VS_GPRS(x) ((x) << 16) 331 #define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) 332 #define SQ_ESGS_RING_SIZE 0x8c44 333 #define SQ_GSVS_RING_SIZE 0x8c4c 334 #define SQ_ESTMP_RING_BASE 0x8c50 335 #define SQ_ESTMP_RING_SIZE 0x8c54 336 #define SQ_GSTMP_RING_BASE 0x8c58 337 #define SQ_GSTMP_RING_SIZE 0x8c5c 338 #define SQ_VSTMP_RING_BASE 0x8c60 339 #define SQ_VSTMP_RING_SIZE 0x8c64 340 #define SQ_PSTMP_RING_BASE 0x8c68 341 #define SQ_PSTMP_RING_SIZE 0x8c6c 342 #define SQ_MS_FIFO_SIZES 0x8CF0 343 #define CACHE_FIFO_SIZE(x) ((x) << 0) 344 #define FETCH_FIFO_HIWATER(x) ((x) << 8) 345 #define DONE_FIFO_HIWATER(x) ((x) << 16) 346 #define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) 347 #define SQ_LSTMP_RING_BASE 0x8e10 348 #define SQ_LSTMP_RING_SIZE 0x8e14 349 #define SQ_HSTMP_RING_BASE 0x8e18 350 #define SQ_HSTMP_RING_SIZE 0x8e1c 351 #define SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 0x8D8C 352 #define DYN_GPR_ENABLE (1 << 8) 353 #define SQ_CONST_MEM_BASE 0x8df8 354 355 #define SX_EXPORT_BUFFER_SIZES 0x900C 356 #define COLOR_BUFFER_SIZE(x) ((x) << 0) 357 #define POSITION_BUFFER_SIZE(x) ((x) << 8) 358 #define SMX_BUFFER_SIZE(x) ((x) << 16) 359 #define SX_DEBUG_1 0x9058 360 #define ENABLE_NEW_SMX_ADDRESS (1 << 16) 361 362 #define SPI_CONFIG_CNTL 0x9100 363 #define GPR_WRITE_PRIORITY(x) ((x) << 0) 364 #define SPI_CONFIG_CNTL_1 0x913C 365 #define VTX_DONE_DELAY(x) ((x) << 0) 366 #define INTERP_ONE_PRIM_PER_ROW (1 << 4) 367 #define CRC_SIMD_ID_WADDR_DISABLE (1 << 8) 368 369 #define CGTS_TCC_DISABLE 0x9148 370 #define CGTS_USER_TCC_DISABLE 0x914C 371 #define TCC_DISABLE_MASK 0xFFFF0000 372 #define TCC_DISABLE_SHIFT 16 373 #define CGTS_SM_CTRL_REG 0x9150 374 #define OVERRIDE (1 << 21) 375 376 #define TA_CNTL_AUX 0x9508 377 #define DISABLE_CUBE_WRAP (1 << 0) 378 #define DISABLE_CUBE_ANISO (1 << 1) 379 380 #define TCP_CHAN_STEER_LO 0x960c 381 #define TCP_CHAN_STEER_HI 0x9610 382 383 #define CC_RB_BACKEND_DISABLE 0x98F4 384 #define BACKEND_DISABLE(x) ((x) << 16) 385 #define GB_ADDR_CONFIG 0x98F8 386 #define NUM_PIPES(x) ((x) << 0) 387 #define NUM_PIPES_MASK 0x00000007 388 #define NUM_PIPES_SHIFT 0 389 #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) 390 #define PIPE_INTERLEAVE_SIZE_MASK 0x00000070 391 #define PIPE_INTERLEAVE_SIZE_SHIFT 4 392 #define BANK_INTERLEAVE_SIZE(x) ((x) << 8) 393 #define NUM_SHADER_ENGINES(x) ((x) << 12) 394 #define NUM_SHADER_ENGINES_MASK 0x00003000 395 #define NUM_SHADER_ENGINES_SHIFT 12 396 #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) 397 #define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000 398 #define SHADER_ENGINE_TILE_SIZE_SHIFT 16 399 #define NUM_GPUS(x) ((x) << 20) 400 #define NUM_GPUS_MASK 0x00700000 401 #define NUM_GPUS_SHIFT 20 402 #define MULTI_GPU_TILE_SIZE(x) ((x) << 24) 403 #define MULTI_GPU_TILE_SIZE_MASK 0x03000000 404 #define MULTI_GPU_TILE_SIZE_SHIFT 24 405 #define ROW_SIZE(x) ((x) << 28) 406 #define ROW_SIZE_MASK 0x30000000 407 #define ROW_SIZE_SHIFT 28 408 #define NUM_LOWER_PIPES(x) ((x) << 30) 409 #define NUM_LOWER_PIPES_MASK 0x40000000 410 #define NUM_LOWER_PIPES_SHIFT 30 411 #define GB_BACKEND_MAP 0x98FC 412 413 #define CB_PERF_CTR0_SEL_0 0x9A20 414 #define CB_PERF_CTR0_SEL_1 0x9A24 415 #define CB_PERF_CTR1_SEL_0 0x9A28 416 #define CB_PERF_CTR1_SEL_1 0x9A2C 417 #define CB_PERF_CTR2_SEL_0 0x9A30 418 #define CB_PERF_CTR2_SEL_1 0x9A34 419 #define CB_PERF_CTR3_SEL_0 0x9A38 420 #define CB_PERF_CTR3_SEL_1 0x9A3C 421 422 #define GC_USER_RB_BACKEND_DISABLE 0x9B7C 423 #define BACKEND_DISABLE_MASK 0x00FF0000 424 #define BACKEND_DISABLE_SHIFT 16 425 426 #define SMX_DC_CTL0 0xA020 427 #define USE_HASH_FUNCTION (1 << 0) 428 #define NUMBER_OF_SETS(x) ((x) << 1) 429 #define FLUSH_ALL_ON_EVENT (1 << 10) 430 #define STALL_ON_EVENT (1 << 11) 431 #define SMX_EVENT_CTL 0xA02C 432 #define ES_FLUSH_CTL(x) ((x) << 0) 433 #define GS_FLUSH_CTL(x) ((x) << 3) 434 #define ACK_FLUSH_CTL(x) ((x) << 6) 435 #define SYNC_FLUSH_CTL (1 << 8) 436 437 #define CP_RB0_BASE 0xC100 438 #define CP_RB0_CNTL 0xC104 439 #define RB_BUFSZ(x) ((x) << 0) 440 #define RB_BLKSZ(x) ((x) << 8) 441 #define RB_NO_UPDATE (1 << 27) 442 #define RB_RPTR_WR_ENA (1 << 31) 443 #define BUF_SWAP_32BIT (2 << 16) 444 #define CP_RB0_RPTR_ADDR 0xC10C 445 #define CP_RB0_RPTR_ADDR_HI 0xC110 446 #define CP_RB0_WPTR 0xC114 447 448 #define CP_INT_CNTL 0xC124 449 # define CNTX_BUSY_INT_ENABLE (1 << 19) 450 # define CNTX_EMPTY_INT_ENABLE (1 << 20) 451 # define TIME_STAMP_INT_ENABLE (1 << 26) 452 453 #define CP_RB1_BASE 0xC180 454 #define CP_RB1_CNTL 0xC184 455 #define CP_RB1_RPTR_ADDR 0xC188 456 #define CP_RB1_RPTR_ADDR_HI 0xC18C 457 #define CP_RB1_WPTR 0xC190 458 #define CP_RB2_BASE 0xC194 459 #define CP_RB2_CNTL 0xC198 460 #define CP_RB2_RPTR_ADDR 0xC19C 461 #define CP_RB2_RPTR_ADDR_HI 0xC1A0 462 #define CP_RB2_WPTR 0xC1A4 463 #define CP_PFP_UCODE_ADDR 0xC150 464 #define CP_PFP_UCODE_DATA 0xC154 465 #define CP_ME_RAM_RADDR 0xC158 466 #define CP_ME_RAM_WADDR 0xC15C 467 #define CP_ME_RAM_DATA 0xC160 468 #define CP_DEBUG 0xC1FC 469 470 #define VGT_EVENT_INITIATOR 0x28a90 471 # define CACHE_FLUSH_AND_INV_EVENT_TS (0x14 << 0) 472 # define CACHE_FLUSH_AND_INV_EVENT (0x16 << 0) 473 474 /* 475 * PM4 476 */ 477 #define PACKET_TYPE0 0 478 #define PACKET_TYPE1 1 479 #define PACKET_TYPE2 2 480 #define PACKET_TYPE3 3 481 482 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 483 #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 484 #define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2) 485 #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 486 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 487 (((reg) >> 2) & 0xFFFF) | \ 488 ((n) & 0x3FFF) << 16) 489 #define CP_PACKET2 0x80000000 490 #define PACKET2_PAD_SHIFT 0 491 #define PACKET2_PAD_MASK (0x3fffffff << 0) 492 493 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 494 495 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 496 (((op) & 0xFF) << 8) | \ 497 ((n) & 0x3FFF) << 16) 498 499 /* Packet 3 types */ 500 #define PACKET3_NOP 0x10 501 #define PACKET3_SET_BASE 0x11 502 #define PACKET3_CLEAR_STATE 0x12 503 #define PACKET3_INDEX_BUFFER_SIZE 0x13 504 #define PACKET3_DEALLOC_STATE 0x14 505 #define PACKET3_DISPATCH_DIRECT 0x15 506 #define PACKET3_DISPATCH_INDIRECT 0x16 507 #define PACKET3_INDIRECT_BUFFER_END 0x17 508 #define PACKET3_MODE_CONTROL 0x18 509 #define PACKET3_SET_PREDICATION 0x20 510 #define PACKET3_REG_RMW 0x21 511 #define PACKET3_COND_EXEC 0x22 512 #define PACKET3_PRED_EXEC 0x23 513 #define PACKET3_DRAW_INDIRECT 0x24 514 #define PACKET3_DRAW_INDEX_INDIRECT 0x25 515 #define PACKET3_INDEX_BASE 0x26 516 #define PACKET3_DRAW_INDEX_2 0x27 517 #define PACKET3_CONTEXT_CONTROL 0x28 518 #define PACKET3_DRAW_INDEX_OFFSET 0x29 519 #define PACKET3_INDEX_TYPE 0x2A 520 #define PACKET3_DRAW_INDEX 0x2B 521 #define PACKET3_DRAW_INDEX_AUTO 0x2D 522 #define PACKET3_DRAW_INDEX_IMMD 0x2E 523 #define PACKET3_NUM_INSTANCES 0x2F 524 #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 525 #define PACKET3_INDIRECT_BUFFER 0x32 526 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 527 #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 528 #define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36 529 #define PACKET3_WRITE_DATA 0x37 530 #define PACKET3_MEM_SEMAPHORE 0x39 531 #define PACKET3_MPEG_INDEX 0x3A 532 #define PACKET3_WAIT_REG_MEM 0x3C 533 #define PACKET3_MEM_WRITE 0x3D 534 #define PACKET3_PFP_SYNC_ME 0x42 535 #define PACKET3_SURFACE_SYNC 0x43 536 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 537 # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 538 # define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 539 # define PACKET3_CB3_DEST_BASE_ENA (1 << 9) 540 # define PACKET3_CB4_DEST_BASE_ENA (1 << 10) 541 # define PACKET3_CB5_DEST_BASE_ENA (1 << 11) 542 # define PACKET3_CB6_DEST_BASE_ENA (1 << 12) 543 # define PACKET3_CB7_DEST_BASE_ENA (1 << 13) 544 # define PACKET3_DB_DEST_BASE_ENA (1 << 14) 545 # define PACKET3_CB8_DEST_BASE_ENA (1 << 15) 546 # define PACKET3_CB9_DEST_BASE_ENA (1 << 16) 547 # define PACKET3_CB10_DEST_BASE_ENA (1 << 17) 548 # define PACKET3_CB11_DEST_BASE_ENA (1 << 18) 549 # define PACKET3_FULL_CACHE_ENA (1 << 20) 550 # define PACKET3_TC_ACTION_ENA (1 << 23) 551 # define PACKET3_CB_ACTION_ENA (1 << 25) 552 # define PACKET3_DB_ACTION_ENA (1 << 26) 553 # define PACKET3_SH_ACTION_ENA (1 << 27) 554 # define PACKET3_SX_ACTION_ENA (1 << 28) 555 #define PACKET3_ME_INITIALIZE 0x44 556 #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 557 #define PACKET3_COND_WRITE 0x45 558 #define PACKET3_EVENT_WRITE 0x46 559 #define EVENT_TYPE(x) ((x) << 0) 560 #define EVENT_INDEX(x) ((x) << 8) 561 /* 0 - any non-TS event 562 * 1 - ZPASS_DONE 563 * 2 - SAMPLE_PIPELINESTAT 564 * 3 - SAMPLE_STREAMOUTSTAT* 565 * 4 - *S_PARTIAL_FLUSH 566 * 5 - TS events 567 */ 568 #define PACKET3_EVENT_WRITE_EOP 0x47 569 #define DATA_SEL(x) ((x) << 29) 570 /* 0 - discard 571 * 1 - send low 32bit data 572 * 2 - send 64bit data 573 * 3 - send 64bit counter value 574 */ 575 #define INT_SEL(x) ((x) << 24) 576 /* 0 - none 577 * 1 - interrupt only (DATA_SEL = 0) 578 * 2 - interrupt when data write is confirmed 579 */ 580 #define PACKET3_EVENT_WRITE_EOS 0x48 581 #define PACKET3_PREAMBLE_CNTL 0x4A 582 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 583 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 584 #define PACKET3_ALU_PS_CONST_BUFFER_COPY 0x4C 585 #define PACKET3_ALU_VS_CONST_BUFFER_COPY 0x4D 586 #define PACKET3_ALU_PS_CONST_UPDATE 0x4E 587 #define PACKET3_ALU_VS_CONST_UPDATE 0x4F 588 #define PACKET3_ONE_REG_WRITE 0x57 589 #define PACKET3_SET_CONFIG_REG 0x68 590 #define PACKET3_SET_CONFIG_REG_START 0x00008000 591 #define PACKET3_SET_CONFIG_REG_END 0x0000ac00 592 #define PACKET3_SET_CONTEXT_REG 0x69 593 #define PACKET3_SET_CONTEXT_REG_START 0x00028000 594 #define PACKET3_SET_CONTEXT_REG_END 0x00029000 595 #define PACKET3_SET_ALU_CONST 0x6A 596 /* alu const buffers only; no reg file */ 597 #define PACKET3_SET_BOOL_CONST 0x6B 598 #define PACKET3_SET_BOOL_CONST_START 0x0003a500 599 #define PACKET3_SET_BOOL_CONST_END 0x0003a518 600 #define PACKET3_SET_LOOP_CONST 0x6C 601 #define PACKET3_SET_LOOP_CONST_START 0x0003a200 602 #define PACKET3_SET_LOOP_CONST_END 0x0003a500 603 #define PACKET3_SET_RESOURCE 0x6D 604 #define PACKET3_SET_RESOURCE_START 0x00030000 605 #define PACKET3_SET_RESOURCE_END 0x00038000 606 #define PACKET3_SET_SAMPLER 0x6E 607 #define PACKET3_SET_SAMPLER_START 0x0003c000 608 #define PACKET3_SET_SAMPLER_END 0x0003c600 609 #define PACKET3_SET_CTL_CONST 0x6F 610 #define PACKET3_SET_CTL_CONST_START 0x0003cff0 611 #define PACKET3_SET_CTL_CONST_END 0x0003ff0c 612 #define PACKET3_SET_RESOURCE_OFFSET 0x70 613 #define PACKET3_SET_ALU_CONST_VS 0x71 614 #define PACKET3_SET_ALU_CONST_DI 0x72 615 #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 616 #define PACKET3_SET_RESOURCE_INDIRECT 0x74 617 #define PACKET3_SET_APPEND_CNT 0x75 618 #define PACKET3_ME_WRITE 0x7A 619 620 /* ASYNC DMA - first instance at 0xd000, second at 0xd800 */ 621 #define DMA0_REGISTER_OFFSET 0x0 /* not a register */ 622 #define DMA1_REGISTER_OFFSET 0x800 /* not a register */ 623 624 #define DMA_RB_CNTL 0xd000 625 # define DMA_RB_ENABLE (1 << 0) 626 # define DMA_RB_SIZE(x) ((x) << 1) /* log2 */ 627 # define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */ 628 # define DMA_RPTR_WRITEBACK_ENABLE (1 << 12) 629 # define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */ 630 # define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */ 631 #define DMA_RB_BASE 0xd004 632 #define DMA_RB_RPTR 0xd008 633 #define DMA_RB_WPTR 0xd00c 634 635 #define DMA_RB_RPTR_ADDR_HI 0xd01c 636 #define DMA_RB_RPTR_ADDR_LO 0xd020 637 638 #define DMA_IB_CNTL 0xd024 639 # define DMA_IB_ENABLE (1 << 0) 640 # define DMA_IB_SWAP_ENABLE (1 << 4) 641 # define CMD_VMID_FORCE (1 << 31) 642 #define DMA_IB_RPTR 0xd028 643 #define DMA_CNTL 0xd02c 644 # define TRAP_ENABLE (1 << 0) 645 # define SEM_INCOMPLETE_INT_ENABLE (1 << 1) 646 # define SEM_WAIT_INT_ENABLE (1 << 2) 647 # define DATA_SWAP_ENABLE (1 << 3) 648 # define FENCE_SWAP_ENABLE (1 << 4) 649 # define CTXEMPTY_INT_ENABLE (1 << 28) 650 #define DMA_STATUS_REG 0xd034 651 # define DMA_IDLE (1 << 0) 652 #define DMA_SEM_INCOMPLETE_TIMER_CNTL 0xd044 653 #define DMA_SEM_WAIT_FAIL_TIMER_CNTL 0xd048 654 #define DMA_TILING_CONFIG 0xd0b8 655 #define DMA_MODE 0xd0bc 656 657 #define DMA_PACKET(cmd, t, s, n) ((((cmd) & 0xF) << 28) | \ 658 (((t) & 0x1) << 23) | \ 659 (((s) & 0x1) << 22) | \ 660 (((n) & 0xFFFFF) << 0)) 661 662 #define DMA_IB_PACKET(cmd, vmid, n) ((((cmd) & 0xF) << 28) | \ 663 (((vmid) & 0xF) << 20) | \ 664 (((n) & 0xFFFFF) << 0)) 665 666 /* async DMA Packet types */ 667 #define DMA_PACKET_WRITE 0x2 668 #define DMA_PACKET_COPY 0x3 669 #define DMA_PACKET_INDIRECT_BUFFER 0x4 670 #define DMA_PACKET_SEMAPHORE 0x5 671 #define DMA_PACKET_FENCE 0x6 672 #define DMA_PACKET_TRAP 0x7 673 #define DMA_PACKET_SRBM_WRITE 0x9 674 #define DMA_PACKET_CONSTANT_FILL 0xd 675 #define DMA_PACKET_NOP 0xf 676 677 #endif 678 679