1 /* 2 * Copyright 2010 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 #ifndef NI_H 25 #define NI_H 26 27 #define CAYMAN_MAX_SH_GPRS 256 28 #define CAYMAN_MAX_TEMP_GPRS 16 29 #define CAYMAN_MAX_SH_THREADS 256 30 #define CAYMAN_MAX_SH_STACK_ENTRIES 4096 31 #define CAYMAN_MAX_FRC_EOV_CNT 16384 32 #define CAYMAN_MAX_BACKENDS 8 33 #define CAYMAN_MAX_BACKENDS_MASK 0xFF 34 #define CAYMAN_MAX_BACKENDS_PER_SE_MASK 0xF 35 #define CAYMAN_MAX_SIMDS 16 36 #define CAYMAN_MAX_SIMDS_MASK 0xFFFF 37 #define CAYMAN_MAX_SIMDS_PER_SE_MASK 0xFFF 38 #define CAYMAN_MAX_PIPES 8 39 #define CAYMAN_MAX_PIPES_MASK 0xFF 40 #define CAYMAN_MAX_LDS_NUM 0xFFFF 41 #define CAYMAN_MAX_TCC 16 42 #define CAYMAN_MAX_TCC_MASK 0xFF 43 44 #define CAYMAN_GB_ADDR_CONFIG_GOLDEN 0x02011003 45 #define ARUBA_GB_ADDR_CONFIG_GOLDEN 0x12010001 46 47 #define DMIF_ADDR_CONFIG 0xBD4 48 49 /* DCE6 only */ 50 #define DMIF_ADDR_CALC 0xC00 51 52 #define SRBM_GFX_CNTL 0x0E44 53 #define RINGID(x) (((x) & 0x3) << 0) 54 #define VMID(x) (((x) & 0x7) << 0) 55 #define SRBM_STATUS 0x0E50 56 #define RLC_RQ_PENDING (1 << 3) 57 #define GRBM_RQ_PENDING (1 << 5) 58 #define VMC_BUSY (1 << 8) 59 #define MCB_BUSY (1 << 9) 60 #define MCB_NON_DISPLAY_BUSY (1 << 10) 61 #define MCC_BUSY (1 << 11) 62 #define MCD_BUSY (1 << 12) 63 #define SEM_BUSY (1 << 14) 64 #define RLC_BUSY (1 << 15) 65 #define IH_BUSY (1 << 17) 66 67 #define SRBM_SOFT_RESET 0x0E60 68 #define SOFT_RESET_BIF (1 << 1) 69 #define SOFT_RESET_CG (1 << 2) 70 #define SOFT_RESET_DC (1 << 5) 71 #define SOFT_RESET_DMA1 (1 << 6) 72 #define SOFT_RESET_GRBM (1 << 8) 73 #define SOFT_RESET_HDP (1 << 9) 74 #define SOFT_RESET_IH (1 << 10) 75 #define SOFT_RESET_MC (1 << 11) 76 #define SOFT_RESET_RLC (1 << 13) 77 #define SOFT_RESET_ROM (1 << 14) 78 #define SOFT_RESET_SEM (1 << 15) 79 #define SOFT_RESET_VMC (1 << 17) 80 #define SOFT_RESET_DMA (1 << 20) 81 #define SOFT_RESET_TST (1 << 21) 82 #define SOFT_RESET_REGBB (1 << 22) 83 #define SOFT_RESET_ORB (1 << 23) 84 85 #define SRBM_STATUS2 0x0EC4 86 #define DMA_BUSY (1 << 5) 87 #define DMA1_BUSY (1 << 6) 88 89 #define VM_CONTEXT0_REQUEST_RESPONSE 0x1470 90 #define REQUEST_TYPE(x) (((x) & 0xf) << 0) 91 #define RESPONSE_TYPE_MASK 0x000000F0 92 #define RESPONSE_TYPE_SHIFT 4 93 #define VM_L2_CNTL 0x1400 94 #define ENABLE_L2_CACHE (1 << 0) 95 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 96 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 97 #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10) 98 #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14) 99 #define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 18) 100 /* CONTEXT1_IDENTITY_ACCESS_MODE 101 * 0 physical = logical 102 * 1 logical via context1 page table 103 * 2 inside identity aperture use translation, outside physical = logical 104 * 3 inside identity aperture physical = logical, outside use translation 105 */ 106 #define VM_L2_CNTL2 0x1404 107 #define INVALIDATE_ALL_L1_TLBS (1 << 0) 108 #define INVALIDATE_L2_CACHE (1 << 1) 109 #define VM_L2_CNTL3 0x1408 110 #define BANK_SELECT(x) ((x) << 0) 111 #define CACHE_UPDATE_MODE(x) ((x) << 6) 112 #define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20) 113 #define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15) 114 #define VM_L2_STATUS 0x140C 115 #define L2_BUSY (1 << 0) 116 #define VM_CONTEXT0_CNTL 0x1410 117 #define ENABLE_CONTEXT (1 << 0) 118 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 119 #define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3) 120 #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 121 #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6) 122 #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7) 123 #define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9) 124 #define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10) 125 #define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12) 126 #define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13) 127 #define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15) 128 #define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16) 129 #define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18) 130 #define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19) 131 #define VM_CONTEXT1_CNTL 0x1414 132 #define VM_CONTEXT0_CNTL2 0x1430 133 #define VM_CONTEXT1_CNTL2 0x1434 134 #define VM_INVALIDATE_REQUEST 0x1478 135 #define VM_INVALIDATE_RESPONSE 0x147c 136 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 137 #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c 138 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C 139 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C 140 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C 141 142 #define MC_SHARED_CHMAP 0x2004 143 #define NOOFCHAN_SHIFT 12 144 #define NOOFCHAN_MASK 0x00003000 145 #define MC_SHARED_CHREMAP 0x2008 146 147 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 148 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 149 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C 150 #define MC_VM_MX_L1_TLB_CNTL 0x2064 151 #define ENABLE_L1_TLB (1 << 0) 152 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 153 #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) 154 #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) 155 #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 156 #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) 157 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 158 #define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6) 159 #define FUS_MC_VM_FB_OFFSET 0x2068 160 161 #define MC_SHARED_BLACKOUT_CNTL 0x20ac 162 #define MC_ARB_RAMCFG 0x2760 163 #define NOOFBANK_SHIFT 0 164 #define NOOFBANK_MASK 0x00000003 165 #define NOOFRANK_SHIFT 2 166 #define NOOFRANK_MASK 0x00000004 167 #define NOOFROWS_SHIFT 3 168 #define NOOFROWS_MASK 0x00000038 169 #define NOOFCOLS_SHIFT 6 170 #define NOOFCOLS_MASK 0x000000C0 171 #define CHANSIZE_SHIFT 8 172 #define CHANSIZE_MASK 0x00000100 173 #define BURSTLENGTH_SHIFT 9 174 #define BURSTLENGTH_MASK 0x00000200 175 #define CHANSIZE_OVERRIDE (1 << 11) 176 #define MC_SEQ_SUP_CNTL 0x28c8 177 #define RUN_MASK (1 << 0) 178 #define MC_SEQ_SUP_PGM 0x28cc 179 #define MC_IO_PAD_CNTL_D0 0x29d0 180 #define MEM_FALL_OUT_CMD (1 << 8) 181 #define MC_SEQ_MISC0 0x2a00 182 #define MC_SEQ_MISC0_GDDR5_SHIFT 28 183 #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000 184 #define MC_SEQ_MISC0_GDDR5_VALUE 5 185 #define MC_SEQ_IO_DEBUG_INDEX 0x2a44 186 #define MC_SEQ_IO_DEBUG_DATA 0x2a48 187 188 #define HDP_HOST_PATH_CNTL 0x2C00 189 #define HDP_NONSURFACE_BASE 0x2C04 190 #define HDP_NONSURFACE_INFO 0x2C08 191 #define HDP_NONSURFACE_SIZE 0x2C0C 192 #define HDP_ADDR_CONFIG 0x2F48 193 #define HDP_MISC_CNTL 0x2F4C 194 #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0) 195 196 #define CC_SYS_RB_BACKEND_DISABLE 0x3F88 197 #define GC_USER_SYS_RB_BACKEND_DISABLE 0x3F8C 198 #define CGTS_SYS_TCC_DISABLE 0x3F90 199 #define CGTS_USER_SYS_TCC_DISABLE 0x3F94 200 201 #define RLC_GFX_INDEX 0x3FC4 202 203 #define CONFIG_MEMSIZE 0x5428 204 205 #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 206 #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 207 208 #define GRBM_CNTL 0x8000 209 #define GRBM_READ_TIMEOUT(x) ((x) << 0) 210 #define GRBM_STATUS 0x8010 211 #define CMDFIFO_AVAIL_MASK 0x0000000F 212 #define RING2_RQ_PENDING (1 << 4) 213 #define SRBM_RQ_PENDING (1 << 5) 214 #define RING1_RQ_PENDING (1 << 6) 215 #define CF_RQ_PENDING (1 << 7) 216 #define PF_RQ_PENDING (1 << 8) 217 #define GDS_DMA_RQ_PENDING (1 << 9) 218 #define GRBM_EE_BUSY (1 << 10) 219 #define SX_CLEAN (1 << 11) 220 #define DB_CLEAN (1 << 12) 221 #define CB_CLEAN (1 << 13) 222 #define TA_BUSY (1 << 14) 223 #define GDS_BUSY (1 << 15) 224 #define VGT_BUSY_NO_DMA (1 << 16) 225 #define VGT_BUSY (1 << 17) 226 #define IA_BUSY_NO_DMA (1 << 18) 227 #define IA_BUSY (1 << 19) 228 #define SX_BUSY (1 << 20) 229 #define SH_BUSY (1 << 21) 230 #define SPI_BUSY (1 << 22) 231 #define SC_BUSY (1 << 24) 232 #define PA_BUSY (1 << 25) 233 #define DB_BUSY (1 << 26) 234 #define CP_COHERENCY_BUSY (1 << 28) 235 #define CP_BUSY (1 << 29) 236 #define CB_BUSY (1 << 30) 237 #define GUI_ACTIVE (1 << 31) 238 #define GRBM_STATUS_SE0 0x8014 239 #define GRBM_STATUS_SE1 0x8018 240 #define SE_SX_CLEAN (1 << 0) 241 #define SE_DB_CLEAN (1 << 1) 242 #define SE_CB_CLEAN (1 << 2) 243 #define SE_VGT_BUSY (1 << 23) 244 #define SE_PA_BUSY (1 << 24) 245 #define SE_TA_BUSY (1 << 25) 246 #define SE_SX_BUSY (1 << 26) 247 #define SE_SPI_BUSY (1 << 27) 248 #define SE_SH_BUSY (1 << 28) 249 #define SE_SC_BUSY (1 << 29) 250 #define SE_DB_BUSY (1 << 30) 251 #define SE_CB_BUSY (1 << 31) 252 #define GRBM_SOFT_RESET 0x8020 253 #define SOFT_RESET_CP (1 << 0) 254 #define SOFT_RESET_CB (1 << 1) 255 #define SOFT_RESET_DB (1 << 3) 256 #define SOFT_RESET_GDS (1 << 4) 257 #define SOFT_RESET_PA (1 << 5) 258 #define SOFT_RESET_SC (1 << 6) 259 #define SOFT_RESET_SPI (1 << 8) 260 #define SOFT_RESET_SH (1 << 9) 261 #define SOFT_RESET_SX (1 << 10) 262 #define SOFT_RESET_TC (1 << 11) 263 #define SOFT_RESET_TA (1 << 12) 264 #define SOFT_RESET_VGT (1 << 14) 265 #define SOFT_RESET_IA (1 << 15) 266 267 #define GRBM_GFX_INDEX 0x802C 268 #define INSTANCE_INDEX(x) ((x) << 0) 269 #define SE_INDEX(x) ((x) << 16) 270 #define INSTANCE_BROADCAST_WRITES (1 << 30) 271 #define SE_BROADCAST_WRITES (1 << 31) 272 273 #define SCRATCH_REG0 0x8500 274 #define SCRATCH_REG1 0x8504 275 #define SCRATCH_REG2 0x8508 276 #define SCRATCH_REG3 0x850C 277 #define SCRATCH_REG4 0x8510 278 #define SCRATCH_REG5 0x8514 279 #define SCRATCH_REG6 0x8518 280 #define SCRATCH_REG7 0x851C 281 #define SCRATCH_UMSK 0x8540 282 #define SCRATCH_ADDR 0x8544 283 #define CP_SEM_WAIT_TIMER 0x85BC 284 #define CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8 285 #define CP_COHER_CNTL2 0x85E8 286 #define CP_STALLED_STAT1 0x8674 287 #define CP_STALLED_STAT2 0x8678 288 #define CP_BUSY_STAT 0x867C 289 #define CP_STAT 0x8680 290 #define CP_ME_CNTL 0x86D8 291 #define CP_ME_HALT (1 << 28) 292 #define CP_PFP_HALT (1 << 26) 293 #define CP_RB2_RPTR 0x86f8 294 #define CP_RB1_RPTR 0x86fc 295 #define CP_RB0_RPTR 0x8700 296 #define CP_RB_WPTR_DELAY 0x8704 297 #define CP_MEQ_THRESHOLDS 0x8764 298 #define MEQ1_START(x) ((x) << 0) 299 #define MEQ2_START(x) ((x) << 8) 300 #define CP_PERFMON_CNTL 0x87FC 301 302 #define VGT_CACHE_INVALIDATION 0x88C4 303 #define CACHE_INVALIDATION(x) ((x) << 0) 304 #define VC_ONLY 0 305 #define TC_ONLY 1 306 #define VC_AND_TC 2 307 #define AUTO_INVLD_EN(x) ((x) << 6) 308 #define NO_AUTO 0 309 #define ES_AUTO 1 310 #define GS_AUTO 2 311 #define ES_AND_GS_AUTO 3 312 #define VGT_GS_VERTEX_REUSE 0x88D4 313 314 #define CC_GC_SHADER_PIPE_CONFIG 0x8950 315 #define GC_USER_SHADER_PIPE_CONFIG 0x8954 316 #define INACTIVE_QD_PIPES(x) ((x) << 8) 317 #define INACTIVE_QD_PIPES_MASK 0x0000FF00 318 #define INACTIVE_QD_PIPES_SHIFT 8 319 #define INACTIVE_SIMDS(x) ((x) << 16) 320 #define INACTIVE_SIMDS_MASK 0xFFFF0000 321 #define INACTIVE_SIMDS_SHIFT 16 322 323 #define VGT_PRIMITIVE_TYPE 0x8958 324 #define VGT_NUM_INSTANCES 0x8974 325 #define VGT_TF_RING_SIZE 0x8988 326 #define VGT_OFFCHIP_LDS_BASE 0x89b4 327 328 #define PA_SC_LINE_STIPPLE_STATE 0x8B10 329 #define PA_CL_ENHANCE 0x8A14 330 #define CLIP_VTX_REORDER_ENA (1 << 0) 331 #define NUM_CLIP_SEQ(x) ((x) << 1) 332 #define PA_SC_FIFO_SIZE 0x8BCC 333 #define SC_PRIM_FIFO_SIZE(x) ((x) << 0) 334 #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12) 335 #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20) 336 #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 337 #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 338 #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) 339 340 #define SQ_CONFIG 0x8C00 341 #define VC_ENABLE (1 << 0) 342 #define EXPORT_SRC_C (1 << 1) 343 #define GFX_PRIO(x) ((x) << 2) 344 #define CS1_PRIO(x) ((x) << 4) 345 #define CS2_PRIO(x) ((x) << 6) 346 #define SQ_GPR_RESOURCE_MGMT_1 0x8C04 347 #define NUM_PS_GPRS(x) ((x) << 0) 348 #define NUM_VS_GPRS(x) ((x) << 16) 349 #define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) 350 #define SQ_ESGS_RING_SIZE 0x8c44 351 #define SQ_GSVS_RING_SIZE 0x8c4c 352 #define SQ_ESTMP_RING_BASE 0x8c50 353 #define SQ_ESTMP_RING_SIZE 0x8c54 354 #define SQ_GSTMP_RING_BASE 0x8c58 355 #define SQ_GSTMP_RING_SIZE 0x8c5c 356 #define SQ_VSTMP_RING_BASE 0x8c60 357 #define SQ_VSTMP_RING_SIZE 0x8c64 358 #define SQ_PSTMP_RING_BASE 0x8c68 359 #define SQ_PSTMP_RING_SIZE 0x8c6c 360 #define SQ_MS_FIFO_SIZES 0x8CF0 361 #define CACHE_FIFO_SIZE(x) ((x) << 0) 362 #define FETCH_FIFO_HIWATER(x) ((x) << 8) 363 #define DONE_FIFO_HIWATER(x) ((x) << 16) 364 #define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) 365 #define SQ_LSTMP_RING_BASE 0x8e10 366 #define SQ_LSTMP_RING_SIZE 0x8e14 367 #define SQ_HSTMP_RING_BASE 0x8e18 368 #define SQ_HSTMP_RING_SIZE 0x8e1c 369 #define SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 0x8D8C 370 #define DYN_GPR_ENABLE (1 << 8) 371 #define SQ_CONST_MEM_BASE 0x8df8 372 373 #define SX_EXPORT_BUFFER_SIZES 0x900C 374 #define COLOR_BUFFER_SIZE(x) ((x) << 0) 375 #define POSITION_BUFFER_SIZE(x) ((x) << 8) 376 #define SMX_BUFFER_SIZE(x) ((x) << 16) 377 #define SX_DEBUG_1 0x9058 378 #define ENABLE_NEW_SMX_ADDRESS (1 << 16) 379 380 #define SPI_CONFIG_CNTL 0x9100 381 #define GPR_WRITE_PRIORITY(x) ((x) << 0) 382 #define SPI_CONFIG_CNTL_1 0x913C 383 #define VTX_DONE_DELAY(x) ((x) << 0) 384 #define INTERP_ONE_PRIM_PER_ROW (1 << 4) 385 #define CRC_SIMD_ID_WADDR_DISABLE (1 << 8) 386 387 #define CGTS_TCC_DISABLE 0x9148 388 #define CGTS_USER_TCC_DISABLE 0x914C 389 #define TCC_DISABLE_MASK 0xFFFF0000 390 #define TCC_DISABLE_SHIFT 16 391 #define CGTS_SM_CTRL_REG 0x9150 392 #define OVERRIDE (1 << 21) 393 394 #define TA_CNTL_AUX 0x9508 395 #define DISABLE_CUBE_WRAP (1 << 0) 396 #define DISABLE_CUBE_ANISO (1 << 1) 397 398 #define TCP_CHAN_STEER_LO 0x960c 399 #define TCP_CHAN_STEER_HI 0x9610 400 401 #define CC_RB_BACKEND_DISABLE 0x98F4 402 #define BACKEND_DISABLE(x) ((x) << 16) 403 #define GB_ADDR_CONFIG 0x98F8 404 #define NUM_PIPES(x) ((x) << 0) 405 #define NUM_PIPES_MASK 0x00000007 406 #define NUM_PIPES_SHIFT 0 407 #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) 408 #define PIPE_INTERLEAVE_SIZE_MASK 0x00000070 409 #define PIPE_INTERLEAVE_SIZE_SHIFT 4 410 #define BANK_INTERLEAVE_SIZE(x) ((x) << 8) 411 #define NUM_SHADER_ENGINES(x) ((x) << 12) 412 #define NUM_SHADER_ENGINES_MASK 0x00003000 413 #define NUM_SHADER_ENGINES_SHIFT 12 414 #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) 415 #define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000 416 #define SHADER_ENGINE_TILE_SIZE_SHIFT 16 417 #define NUM_GPUS(x) ((x) << 20) 418 #define NUM_GPUS_MASK 0x00700000 419 #define NUM_GPUS_SHIFT 20 420 #define MULTI_GPU_TILE_SIZE(x) ((x) << 24) 421 #define MULTI_GPU_TILE_SIZE_MASK 0x03000000 422 #define MULTI_GPU_TILE_SIZE_SHIFT 24 423 #define ROW_SIZE(x) ((x) << 28) 424 #define ROW_SIZE_MASK 0x30000000 425 #define ROW_SIZE_SHIFT 28 426 #define NUM_LOWER_PIPES(x) ((x) << 30) 427 #define NUM_LOWER_PIPES_MASK 0x40000000 428 #define NUM_LOWER_PIPES_SHIFT 30 429 #define GB_BACKEND_MAP 0x98FC 430 431 #define CB_PERF_CTR0_SEL_0 0x9A20 432 #define CB_PERF_CTR0_SEL_1 0x9A24 433 #define CB_PERF_CTR1_SEL_0 0x9A28 434 #define CB_PERF_CTR1_SEL_1 0x9A2C 435 #define CB_PERF_CTR2_SEL_0 0x9A30 436 #define CB_PERF_CTR2_SEL_1 0x9A34 437 #define CB_PERF_CTR3_SEL_0 0x9A38 438 #define CB_PERF_CTR3_SEL_1 0x9A3C 439 440 #define GC_USER_RB_BACKEND_DISABLE 0x9B7C 441 #define BACKEND_DISABLE_MASK 0x00FF0000 442 #define BACKEND_DISABLE_SHIFT 16 443 444 #define SMX_DC_CTL0 0xA020 445 #define USE_HASH_FUNCTION (1 << 0) 446 #define NUMBER_OF_SETS(x) ((x) << 1) 447 #define FLUSH_ALL_ON_EVENT (1 << 10) 448 #define STALL_ON_EVENT (1 << 11) 449 #define SMX_EVENT_CTL 0xA02C 450 #define ES_FLUSH_CTL(x) ((x) << 0) 451 #define GS_FLUSH_CTL(x) ((x) << 3) 452 #define ACK_FLUSH_CTL(x) ((x) << 6) 453 #define SYNC_FLUSH_CTL (1 << 8) 454 455 #define CP_RB0_BASE 0xC100 456 #define CP_RB0_CNTL 0xC104 457 #define RB_BUFSZ(x) ((x) << 0) 458 #define RB_BLKSZ(x) ((x) << 8) 459 #define RB_NO_UPDATE (1 << 27) 460 #define RB_RPTR_WR_ENA (1 << 31) 461 #define BUF_SWAP_32BIT (2 << 16) 462 #define CP_RB0_RPTR_ADDR 0xC10C 463 #define CP_RB0_RPTR_ADDR_HI 0xC110 464 #define CP_RB0_WPTR 0xC114 465 466 #define CP_INT_CNTL 0xC124 467 # define CNTX_BUSY_INT_ENABLE (1 << 19) 468 # define CNTX_EMPTY_INT_ENABLE (1 << 20) 469 # define TIME_STAMP_INT_ENABLE (1 << 26) 470 471 #define CP_RB1_BASE 0xC180 472 #define CP_RB1_CNTL 0xC184 473 #define CP_RB1_RPTR_ADDR 0xC188 474 #define CP_RB1_RPTR_ADDR_HI 0xC18C 475 #define CP_RB1_WPTR 0xC190 476 #define CP_RB2_BASE 0xC194 477 #define CP_RB2_CNTL 0xC198 478 #define CP_RB2_RPTR_ADDR 0xC19C 479 #define CP_RB2_RPTR_ADDR_HI 0xC1A0 480 #define CP_RB2_WPTR 0xC1A4 481 #define CP_PFP_UCODE_ADDR 0xC150 482 #define CP_PFP_UCODE_DATA 0xC154 483 #define CP_ME_RAM_RADDR 0xC158 484 #define CP_ME_RAM_WADDR 0xC15C 485 #define CP_ME_RAM_DATA 0xC160 486 #define CP_DEBUG 0xC1FC 487 488 #define VGT_EVENT_INITIATOR 0x28a90 489 # define CACHE_FLUSH_AND_INV_EVENT_TS (0x14 << 0) 490 # define CACHE_FLUSH_AND_INV_EVENT (0x16 << 0) 491 492 /* TN SMU registers */ 493 #define TN_CURRENT_GNB_TEMP 0x1F390 494 495 /* pm registers */ 496 #define SMC_MSG 0x20c 497 #define HOST_SMC_MSG(x) ((x) << 0) 498 #define HOST_SMC_MSG_MASK (0xff << 0) 499 #define HOST_SMC_MSG_SHIFT 0 500 #define HOST_SMC_RESP(x) ((x) << 8) 501 #define HOST_SMC_RESP_MASK (0xff << 8) 502 #define HOST_SMC_RESP_SHIFT 8 503 #define SMC_HOST_MSG(x) ((x) << 16) 504 #define SMC_HOST_MSG_MASK (0xff << 16) 505 #define SMC_HOST_MSG_SHIFT 16 506 #define SMC_HOST_RESP(x) ((x) << 24) 507 #define SMC_HOST_RESP_MASK (0xff << 24) 508 #define SMC_HOST_RESP_SHIFT 24 509 510 #define CG_SPLL_FUNC_CNTL 0x600 511 #define SPLL_RESET (1 << 0) 512 #define SPLL_SLEEP (1 << 1) 513 #define SPLL_BYPASS_EN (1 << 3) 514 #define SPLL_REF_DIV(x) ((x) << 4) 515 #define SPLL_REF_DIV_MASK (0x3f << 4) 516 #define SPLL_PDIV_A(x) ((x) << 20) 517 #define SPLL_PDIV_A_MASK (0x7f << 20) 518 #define SPLL_PDIV_A_SHIFT 20 519 #define CG_SPLL_FUNC_CNTL_2 0x604 520 #define SCLK_MUX_SEL(x) ((x) << 0) 521 #define SCLK_MUX_SEL_MASK (0x1ff << 0) 522 #define CG_SPLL_FUNC_CNTL_3 0x608 523 #define SPLL_FB_DIV(x) ((x) << 0) 524 #define SPLL_FB_DIV_MASK (0x3ffffff << 0) 525 #define SPLL_FB_DIV_SHIFT 0 526 #define SPLL_DITHEN (1 << 28) 527 528 #define MPLL_CNTL_MODE 0x61c 529 # define SS_SSEN (1 << 24) 530 # define SS_DSMODE_EN (1 << 25) 531 532 #define MPLL_AD_FUNC_CNTL 0x624 533 #define CLKF(x) ((x) << 0) 534 #define CLKF_MASK (0x7f << 0) 535 #define CLKR(x) ((x) << 7) 536 #define CLKR_MASK (0x1f << 7) 537 #define CLKFRAC(x) ((x) << 12) 538 #define CLKFRAC_MASK (0x1f << 12) 539 #define YCLK_POST_DIV(x) ((x) << 17) 540 #define YCLK_POST_DIV_MASK (3 << 17) 541 #define IBIAS(x) ((x) << 20) 542 #define IBIAS_MASK (0x3ff << 20) 543 #define RESET (1 << 30) 544 #define PDNB (1 << 31) 545 #define MPLL_AD_FUNC_CNTL_2 0x628 546 #define BYPASS (1 << 19) 547 #define BIAS_GEN_PDNB (1 << 24) 548 #define RESET_EN (1 << 25) 549 #define VCO_MODE (1 << 29) 550 #define MPLL_DQ_FUNC_CNTL 0x62c 551 #define MPLL_DQ_FUNC_CNTL_2 0x630 552 553 #define GENERAL_PWRMGT 0x63c 554 # define GLOBAL_PWRMGT_EN (1 << 0) 555 # define STATIC_PM_EN (1 << 1) 556 # define THERMAL_PROTECTION_DIS (1 << 2) 557 # define THERMAL_PROTECTION_TYPE (1 << 3) 558 # define ENABLE_GEN2PCIE (1 << 4) 559 # define ENABLE_GEN2XSP (1 << 5) 560 # define SW_SMIO_INDEX(x) ((x) << 6) 561 # define SW_SMIO_INDEX_MASK (3 << 6) 562 # define SW_SMIO_INDEX_SHIFT 6 563 # define LOW_VOLT_D2_ACPI (1 << 8) 564 # define LOW_VOLT_D3_ACPI (1 << 9) 565 # define VOLT_PWRMGT_EN (1 << 10) 566 # define BACKBIAS_PAD_EN (1 << 18) 567 # define BACKBIAS_VALUE (1 << 19) 568 # define DYN_SPREAD_SPECTRUM_EN (1 << 23) 569 # define AC_DC_SW (1 << 24) 570 571 #define SCLK_PWRMGT_CNTL 0x644 572 # define SCLK_PWRMGT_OFF (1 << 0) 573 # define SCLK_LOW_D1 (1 << 1) 574 # define FIR_RESET (1 << 4) 575 # define FIR_FORCE_TREND_SEL (1 << 5) 576 # define FIR_TREND_MODE (1 << 6) 577 # define DYN_GFX_CLK_OFF_EN (1 << 7) 578 # define GFX_CLK_FORCE_ON (1 << 8) 579 # define GFX_CLK_REQUEST_OFF (1 << 9) 580 # define GFX_CLK_FORCE_OFF (1 << 10) 581 # define GFX_CLK_OFF_ACPI_D1 (1 << 11) 582 # define GFX_CLK_OFF_ACPI_D2 (1 << 12) 583 # define GFX_CLK_OFF_ACPI_D3 (1 << 13) 584 # define DYN_LIGHT_SLEEP_EN (1 << 14) 585 #define MCLK_PWRMGT_CNTL 0x648 586 # define DLL_SPEED(x) ((x) << 0) 587 # define DLL_SPEED_MASK (0x1f << 0) 588 # define MPLL_PWRMGT_OFF (1 << 5) 589 # define DLL_READY (1 << 6) 590 # define MC_INT_CNTL (1 << 7) 591 # define MRDCKA0_PDNB (1 << 8) 592 # define MRDCKA1_PDNB (1 << 9) 593 # define MRDCKB0_PDNB (1 << 10) 594 # define MRDCKB1_PDNB (1 << 11) 595 # define MRDCKC0_PDNB (1 << 12) 596 # define MRDCKC1_PDNB (1 << 13) 597 # define MRDCKD0_PDNB (1 << 14) 598 # define MRDCKD1_PDNB (1 << 15) 599 # define MRDCKA0_RESET (1 << 16) 600 # define MRDCKA1_RESET (1 << 17) 601 # define MRDCKB0_RESET (1 << 18) 602 # define MRDCKB1_RESET (1 << 19) 603 # define MRDCKC0_RESET (1 << 20) 604 # define MRDCKC1_RESET (1 << 21) 605 # define MRDCKD0_RESET (1 << 22) 606 # define MRDCKD1_RESET (1 << 23) 607 # define DLL_READY_READ (1 << 24) 608 # define USE_DISPLAY_GAP (1 << 25) 609 # define USE_DISPLAY_URGENT_NORMAL (1 << 26) 610 # define MPLL_TURNOFF_D2 (1 << 28) 611 #define DLL_CNTL 0x64c 612 # define MRDCKA0_BYPASS (1 << 24) 613 # define MRDCKA1_BYPASS (1 << 25) 614 # define MRDCKB0_BYPASS (1 << 26) 615 # define MRDCKB1_BYPASS (1 << 27) 616 # define MRDCKC0_BYPASS (1 << 28) 617 # define MRDCKC1_BYPASS (1 << 29) 618 # define MRDCKD0_BYPASS (1 << 30) 619 # define MRDCKD1_BYPASS (1 << 31) 620 621 #define TARGET_AND_CURRENT_PROFILE_INDEX 0x66c 622 # define CURRENT_STATE_INDEX_MASK (0xf << 4) 623 # define CURRENT_STATE_INDEX_SHIFT 4 624 625 #define CG_AT 0x6d4 626 # define CG_R(x) ((x) << 0) 627 # define CG_R_MASK (0xffff << 0) 628 # define CG_L(x) ((x) << 16) 629 # define CG_L_MASK (0xffff << 16) 630 631 #define CG_BIF_REQ_AND_RSP 0x7f4 632 #define CG_CLIENT_REQ(x) ((x) << 0) 633 #define CG_CLIENT_REQ_MASK (0xff << 0) 634 #define CG_CLIENT_REQ_SHIFT 0 635 #define CG_CLIENT_RESP(x) ((x) << 8) 636 #define CG_CLIENT_RESP_MASK (0xff << 8) 637 #define CG_CLIENT_RESP_SHIFT 8 638 #define CLIENT_CG_REQ(x) ((x) << 16) 639 #define CLIENT_CG_REQ_MASK (0xff << 16) 640 #define CLIENT_CG_REQ_SHIFT 16 641 #define CLIENT_CG_RESP(x) ((x) << 24) 642 #define CLIENT_CG_RESP_MASK (0xff << 24) 643 #define CLIENT_CG_RESP_SHIFT 24 644 645 #define CG_SPLL_SPREAD_SPECTRUM 0x790 646 #define SSEN (1 << 0) 647 #define CLK_S(x) ((x) << 4) 648 #define CLK_S_MASK (0xfff << 4) 649 #define CLK_S_SHIFT 4 650 #define CG_SPLL_SPREAD_SPECTRUM_2 0x794 651 #define CLK_V(x) ((x) << 0) 652 #define CLK_V_MASK (0x3ffffff << 0) 653 #define CLK_V_SHIFT 0 654 655 #define SMC_SCRATCH0 0x81c 656 657 #define CG_SPLL_FUNC_CNTL_4 0x850 658 659 #define MPLL_SS1 0x85c 660 #define CLKV(x) ((x) << 0) 661 #define CLKV_MASK (0x3ffffff << 0) 662 #define MPLL_SS2 0x860 663 #define CLKS(x) ((x) << 0) 664 #define CLKS_MASK (0xfff << 0) 665 666 #define CG_CAC_CTRL 0x88c 667 #define TID_CNT(x) ((x) << 0) 668 #define TID_CNT_MASK (0x3fff << 0) 669 #define TID_UNIT(x) ((x) << 14) 670 #define TID_UNIT_MASK (0xf << 14) 671 672 #define CG_IND_ADDR 0x8f8 673 #define CG_IND_DATA 0x8fc 674 /* CGIND regs */ 675 #define CG_CGTT_LOCAL_0 0x00 676 #define CG_CGTT_LOCAL_1 0x01 677 678 #define MC_CG_CONFIG 0x25bc 679 #define MCDW_WR_ENABLE (1 << 0) 680 #define MCDX_WR_ENABLE (1 << 1) 681 #define MCDY_WR_ENABLE (1 << 2) 682 #define MCDZ_WR_ENABLE (1 << 3) 683 #define MC_RD_ENABLE(x) ((x) << 4) 684 #define MC_RD_ENABLE_MASK (3 << 4) 685 #define INDEX(x) ((x) << 6) 686 #define INDEX_MASK (0xfff << 6) 687 #define INDEX_SHIFT 6 688 689 #define MC_ARB_CAC_CNTL 0x2750 690 #define ENABLE (1 << 0) 691 #define READ_WEIGHT(x) ((x) << 1) 692 #define READ_WEIGHT_MASK (0x3f << 1) 693 #define READ_WEIGHT_SHIFT 1 694 #define WRITE_WEIGHT(x) ((x) << 7) 695 #define WRITE_WEIGHT_MASK (0x3f << 7) 696 #define WRITE_WEIGHT_SHIFT 7 697 #define ALLOW_OVERFLOW (1 << 13) 698 699 #define MC_ARB_DRAM_TIMING 0x2774 700 #define MC_ARB_DRAM_TIMING2 0x2778 701 702 #define MC_ARB_RFSH_RATE 0x27b0 703 #define POWERMODE0(x) ((x) << 0) 704 #define POWERMODE0_MASK (0xff << 0) 705 #define POWERMODE0_SHIFT 0 706 #define POWERMODE1(x) ((x) << 8) 707 #define POWERMODE1_MASK (0xff << 8) 708 #define POWERMODE1_SHIFT 8 709 #define POWERMODE2(x) ((x) << 16) 710 #define POWERMODE2_MASK (0xff << 16) 711 #define POWERMODE2_SHIFT 16 712 #define POWERMODE3(x) ((x) << 24) 713 #define POWERMODE3_MASK (0xff << 24) 714 #define POWERMODE3_SHIFT 24 715 716 #define MC_ARB_CG 0x27e8 717 #define CG_ARB_REQ(x) ((x) << 0) 718 #define CG_ARB_REQ_MASK (0xff << 0) 719 #define CG_ARB_REQ_SHIFT 0 720 #define CG_ARB_RESP(x) ((x) << 8) 721 #define CG_ARB_RESP_MASK (0xff << 8) 722 #define CG_ARB_RESP_SHIFT 8 723 #define ARB_CG_REQ(x) ((x) << 16) 724 #define ARB_CG_REQ_MASK (0xff << 16) 725 #define ARB_CG_REQ_SHIFT 16 726 #define ARB_CG_RESP(x) ((x) << 24) 727 #define ARB_CG_RESP_MASK (0xff << 24) 728 #define ARB_CG_RESP_SHIFT 24 729 730 #define MC_ARB_DRAM_TIMING_1 0x27f0 731 #define MC_ARB_DRAM_TIMING_2 0x27f4 732 #define MC_ARB_DRAM_TIMING_3 0x27f8 733 #define MC_ARB_DRAM_TIMING2_1 0x27fc 734 #define MC_ARB_DRAM_TIMING2_2 0x2800 735 #define MC_ARB_DRAM_TIMING2_3 0x2804 736 #define MC_ARB_BURST_TIME 0x2808 737 #define STATE0(x) ((x) << 0) 738 #define STATE0_MASK (0x1f << 0) 739 #define STATE0_SHIFT 0 740 #define STATE1(x) ((x) << 5) 741 #define STATE1_MASK (0x1f << 5) 742 #define STATE1_SHIFT 5 743 #define STATE2(x) ((x) << 10) 744 #define STATE2_MASK (0x1f << 10) 745 #define STATE2_SHIFT 10 746 #define STATE3(x) ((x) << 15) 747 #define STATE3_MASK (0x1f << 15) 748 #define STATE3_SHIFT 15 749 750 #define MC_CG_DATAPORT 0x2884 751 752 #define MC_SEQ_RAS_TIMING 0x28a0 753 #define MC_SEQ_CAS_TIMING 0x28a4 754 #define MC_SEQ_MISC_TIMING 0x28a8 755 #define MC_SEQ_MISC_TIMING2 0x28ac 756 #define MC_SEQ_PMG_TIMING 0x28b0 757 #define MC_SEQ_RD_CTL_D0 0x28b4 758 #define MC_SEQ_RD_CTL_D1 0x28b8 759 #define MC_SEQ_WR_CTL_D0 0x28bc 760 #define MC_SEQ_WR_CTL_D1 0x28c0 761 762 #define MC_SEQ_MISC0 0x2a00 763 #define MC_SEQ_MISC0_GDDR5_SHIFT 28 764 #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000 765 #define MC_SEQ_MISC0_GDDR5_VALUE 5 766 #define MC_SEQ_MISC1 0x2a04 767 #define MC_SEQ_RESERVE_M 0x2a08 768 #define MC_PMG_CMD_EMRS 0x2a0c 769 770 #define MC_SEQ_MISC3 0x2a2c 771 772 #define MC_SEQ_MISC5 0x2a54 773 #define MC_SEQ_MISC6 0x2a58 774 775 #define MC_SEQ_MISC7 0x2a64 776 777 #define MC_SEQ_RAS_TIMING_LP 0x2a6c 778 #define MC_SEQ_CAS_TIMING_LP 0x2a70 779 #define MC_SEQ_MISC_TIMING_LP 0x2a74 780 #define MC_SEQ_MISC_TIMING2_LP 0x2a78 781 #define MC_SEQ_WR_CTL_D0_LP 0x2a7c 782 #define MC_SEQ_WR_CTL_D1_LP 0x2a80 783 #define MC_SEQ_PMG_CMD_EMRS_LP 0x2a84 784 #define MC_SEQ_PMG_CMD_MRS_LP 0x2a88 785 786 #define MC_PMG_CMD_MRS 0x2aac 787 788 #define MC_SEQ_RD_CTL_D0_LP 0x2b1c 789 #define MC_SEQ_RD_CTL_D1_LP 0x2b20 790 791 #define MC_PMG_CMD_MRS1 0x2b44 792 #define MC_SEQ_PMG_CMD_MRS1_LP 0x2b48 793 #define MC_SEQ_PMG_TIMING_LP 0x2b4c 794 795 #define MC_PMG_CMD_MRS2 0x2b5c 796 #define MC_SEQ_PMG_CMD_MRS2_LP 0x2b60 797 798 #define LB_SYNC_RESET_SEL 0x6b28 799 #define LB_SYNC_RESET_SEL_MASK (3 << 0) 800 #define LB_SYNC_RESET_SEL_SHIFT 0 801 802 #define DC_STUTTER_CNTL 0x6b30 803 #define DC_STUTTER_ENABLE_A (1 << 0) 804 #define DC_STUTTER_ENABLE_B (1 << 1) 805 806 #define SQ_CAC_THRESHOLD 0x8e4c 807 #define VSP(x) ((x) << 0) 808 #define VSP_MASK (0xff << 0) 809 #define VSP_SHIFT 0 810 #define VSP0(x) ((x) << 8) 811 #define VSP0_MASK (0xff << 8) 812 #define VSP0_SHIFT 8 813 #define GPR(x) ((x) << 16) 814 #define GPR_MASK (0xff << 16) 815 #define GPR_SHIFT 16 816 817 #define SQ_POWER_THROTTLE 0x8e58 818 #define MIN_POWER(x) ((x) << 0) 819 #define MIN_POWER_MASK (0x3fff << 0) 820 #define MIN_POWER_SHIFT 0 821 #define MAX_POWER(x) ((x) << 16) 822 #define MAX_POWER_MASK (0x3fff << 16) 823 #define MAX_POWER_SHIFT 0 824 #define SQ_POWER_THROTTLE2 0x8e5c 825 #define MAX_POWER_DELTA(x) ((x) << 0) 826 #define MAX_POWER_DELTA_MASK (0x3fff << 0) 827 #define MAX_POWER_DELTA_SHIFT 0 828 #define STI_SIZE(x) ((x) << 16) 829 #define STI_SIZE_MASK (0x3ff << 16) 830 #define STI_SIZE_SHIFT 16 831 #define LTI_RATIO(x) ((x) << 27) 832 #define LTI_RATIO_MASK (0xf << 27) 833 #define LTI_RATIO_SHIFT 27 834 835 /* CG indirect registers */ 836 #define CG_CAC_REGION_1_WEIGHT_0 0x83 837 #define WEIGHT_TCP_SIG0(x) ((x) << 0) 838 #define WEIGHT_TCP_SIG0_MASK (0x3f << 0) 839 #define WEIGHT_TCP_SIG0_SHIFT 0 840 #define WEIGHT_TCP_SIG1(x) ((x) << 6) 841 #define WEIGHT_TCP_SIG1_MASK (0x3f << 6) 842 #define WEIGHT_TCP_SIG1_SHIFT 6 843 #define WEIGHT_TA_SIG(x) ((x) << 12) 844 #define WEIGHT_TA_SIG_MASK (0x3f << 12) 845 #define WEIGHT_TA_SIG_SHIFT 12 846 #define CG_CAC_REGION_1_WEIGHT_1 0x84 847 #define WEIGHT_TCC_EN0(x) ((x) << 0) 848 #define WEIGHT_TCC_EN0_MASK (0x3f << 0) 849 #define WEIGHT_TCC_EN0_SHIFT 0 850 #define WEIGHT_TCC_EN1(x) ((x) << 6) 851 #define WEIGHT_TCC_EN1_MASK (0x3f << 6) 852 #define WEIGHT_TCC_EN1_SHIFT 6 853 #define WEIGHT_TCC_EN2(x) ((x) << 12) 854 #define WEIGHT_TCC_EN2_MASK (0x3f << 12) 855 #define WEIGHT_TCC_EN2_SHIFT 12 856 #define WEIGHT_TCC_EN3(x) ((x) << 18) 857 #define WEIGHT_TCC_EN3_MASK (0x3f << 18) 858 #define WEIGHT_TCC_EN3_SHIFT 18 859 #define CG_CAC_REGION_2_WEIGHT_0 0x85 860 #define WEIGHT_CB_EN0(x) ((x) << 0) 861 #define WEIGHT_CB_EN0_MASK (0x3f << 0) 862 #define WEIGHT_CB_EN0_SHIFT 0 863 #define WEIGHT_CB_EN1(x) ((x) << 6) 864 #define WEIGHT_CB_EN1_MASK (0x3f << 6) 865 #define WEIGHT_CB_EN1_SHIFT 6 866 #define WEIGHT_CB_EN2(x) ((x) << 12) 867 #define WEIGHT_CB_EN2_MASK (0x3f << 12) 868 #define WEIGHT_CB_EN2_SHIFT 12 869 #define WEIGHT_CB_EN3(x) ((x) << 18) 870 #define WEIGHT_CB_EN3_MASK (0x3f << 18) 871 #define WEIGHT_CB_EN3_SHIFT 18 872 #define CG_CAC_REGION_2_WEIGHT_1 0x86 873 #define WEIGHT_DB_SIG0(x) ((x) << 0) 874 #define WEIGHT_DB_SIG0_MASK (0x3f << 0) 875 #define WEIGHT_DB_SIG0_SHIFT 0 876 #define WEIGHT_DB_SIG1(x) ((x) << 6) 877 #define WEIGHT_DB_SIG1_MASK (0x3f << 6) 878 #define WEIGHT_DB_SIG1_SHIFT 6 879 #define WEIGHT_DB_SIG2(x) ((x) << 12) 880 #define WEIGHT_DB_SIG2_MASK (0x3f << 12) 881 #define WEIGHT_DB_SIG2_SHIFT 12 882 #define WEIGHT_DB_SIG3(x) ((x) << 18) 883 #define WEIGHT_DB_SIG3_MASK (0x3f << 18) 884 #define WEIGHT_DB_SIG3_SHIFT 18 885 #define CG_CAC_REGION_2_WEIGHT_2 0x87 886 #define WEIGHT_SXM_SIG0(x) ((x) << 0) 887 #define WEIGHT_SXM_SIG0_MASK (0x3f << 0) 888 #define WEIGHT_SXM_SIG0_SHIFT 0 889 #define WEIGHT_SXM_SIG1(x) ((x) << 6) 890 #define WEIGHT_SXM_SIG1_MASK (0x3f << 6) 891 #define WEIGHT_SXM_SIG1_SHIFT 6 892 #define WEIGHT_SXM_SIG2(x) ((x) << 12) 893 #define WEIGHT_SXM_SIG2_MASK (0x3f << 12) 894 #define WEIGHT_SXM_SIG2_SHIFT 12 895 #define WEIGHT_SXS_SIG0(x) ((x) << 18) 896 #define WEIGHT_SXS_SIG0_MASK (0x3f << 18) 897 #define WEIGHT_SXS_SIG0_SHIFT 18 898 #define WEIGHT_SXS_SIG1(x) ((x) << 24) 899 #define WEIGHT_SXS_SIG1_MASK (0x3f << 24) 900 #define WEIGHT_SXS_SIG1_SHIFT 24 901 #define CG_CAC_REGION_3_WEIGHT_0 0x88 902 #define WEIGHT_XBR_0(x) ((x) << 0) 903 #define WEIGHT_XBR_0_MASK (0x3f << 0) 904 #define WEIGHT_XBR_0_SHIFT 0 905 #define WEIGHT_XBR_1(x) ((x) << 6) 906 #define WEIGHT_XBR_1_MASK (0x3f << 6) 907 #define WEIGHT_XBR_1_SHIFT 6 908 #define WEIGHT_XBR_2(x) ((x) << 12) 909 #define WEIGHT_XBR_2_MASK (0x3f << 12) 910 #define WEIGHT_XBR_2_SHIFT 12 911 #define WEIGHT_SPI_SIG0(x) ((x) << 18) 912 #define WEIGHT_SPI_SIG0_MASK (0x3f << 18) 913 #define WEIGHT_SPI_SIG0_SHIFT 18 914 #define CG_CAC_REGION_3_WEIGHT_1 0x89 915 #define WEIGHT_SPI_SIG1(x) ((x) << 0) 916 #define WEIGHT_SPI_SIG1_MASK (0x3f << 0) 917 #define WEIGHT_SPI_SIG1_SHIFT 0 918 #define WEIGHT_SPI_SIG2(x) ((x) << 6) 919 #define WEIGHT_SPI_SIG2_MASK (0x3f << 6) 920 #define WEIGHT_SPI_SIG2_SHIFT 6 921 #define WEIGHT_SPI_SIG3(x) ((x) << 12) 922 #define WEIGHT_SPI_SIG3_MASK (0x3f << 12) 923 #define WEIGHT_SPI_SIG3_SHIFT 12 924 #define WEIGHT_SPI_SIG4(x) ((x) << 18) 925 #define WEIGHT_SPI_SIG4_MASK (0x3f << 18) 926 #define WEIGHT_SPI_SIG4_SHIFT 18 927 #define WEIGHT_SPI_SIG5(x) ((x) << 24) 928 #define WEIGHT_SPI_SIG5_MASK (0x3f << 24) 929 #define WEIGHT_SPI_SIG5_SHIFT 24 930 #define CG_CAC_REGION_4_WEIGHT_0 0x8a 931 #define WEIGHT_LDS_SIG0(x) ((x) << 0) 932 #define WEIGHT_LDS_SIG0_MASK (0x3f << 0) 933 #define WEIGHT_LDS_SIG0_SHIFT 0 934 #define WEIGHT_LDS_SIG1(x) ((x) << 6) 935 #define WEIGHT_LDS_SIG1_MASK (0x3f << 6) 936 #define WEIGHT_LDS_SIG1_SHIFT 6 937 #define WEIGHT_SC(x) ((x) << 24) 938 #define WEIGHT_SC_MASK (0x3f << 24) 939 #define WEIGHT_SC_SHIFT 24 940 #define CG_CAC_REGION_4_WEIGHT_1 0x8b 941 #define WEIGHT_BIF(x) ((x) << 0) 942 #define WEIGHT_BIF_MASK (0x3f << 0) 943 #define WEIGHT_BIF_SHIFT 0 944 #define WEIGHT_CP(x) ((x) << 6) 945 #define WEIGHT_CP_MASK (0x3f << 6) 946 #define WEIGHT_CP_SHIFT 6 947 #define WEIGHT_PA_SIG0(x) ((x) << 12) 948 #define WEIGHT_PA_SIG0_MASK (0x3f << 12) 949 #define WEIGHT_PA_SIG0_SHIFT 12 950 #define WEIGHT_PA_SIG1(x) ((x) << 18) 951 #define WEIGHT_PA_SIG1_MASK (0x3f << 18) 952 #define WEIGHT_PA_SIG1_SHIFT 18 953 #define WEIGHT_VGT_SIG0(x) ((x) << 24) 954 #define WEIGHT_VGT_SIG0_MASK (0x3f << 24) 955 #define WEIGHT_VGT_SIG0_SHIFT 24 956 #define CG_CAC_REGION_4_WEIGHT_2 0x8c 957 #define WEIGHT_VGT_SIG1(x) ((x) << 0) 958 #define WEIGHT_VGT_SIG1_MASK (0x3f << 0) 959 #define WEIGHT_VGT_SIG1_SHIFT 0 960 #define WEIGHT_VGT_SIG2(x) ((x) << 6) 961 #define WEIGHT_VGT_SIG2_MASK (0x3f << 6) 962 #define WEIGHT_VGT_SIG2_SHIFT 6 963 #define WEIGHT_DC_SIG0(x) ((x) << 12) 964 #define WEIGHT_DC_SIG0_MASK (0x3f << 12) 965 #define WEIGHT_DC_SIG0_SHIFT 12 966 #define WEIGHT_DC_SIG1(x) ((x) << 18) 967 #define WEIGHT_DC_SIG1_MASK (0x3f << 18) 968 #define WEIGHT_DC_SIG1_SHIFT 18 969 #define WEIGHT_DC_SIG2(x) ((x) << 24) 970 #define WEIGHT_DC_SIG2_MASK (0x3f << 24) 971 #define WEIGHT_DC_SIG2_SHIFT 24 972 #define CG_CAC_REGION_4_WEIGHT_3 0x8d 973 #define WEIGHT_DC_SIG3(x) ((x) << 0) 974 #define WEIGHT_DC_SIG3_MASK (0x3f << 0) 975 #define WEIGHT_DC_SIG3_SHIFT 0 976 #define WEIGHT_UVD_SIG0(x) ((x) << 6) 977 #define WEIGHT_UVD_SIG0_MASK (0x3f << 6) 978 #define WEIGHT_UVD_SIG0_SHIFT 6 979 #define WEIGHT_UVD_SIG1(x) ((x) << 12) 980 #define WEIGHT_UVD_SIG1_MASK (0x3f << 12) 981 #define WEIGHT_UVD_SIG1_SHIFT 12 982 #define WEIGHT_SPARE0(x) ((x) << 18) 983 #define WEIGHT_SPARE0_MASK (0x3f << 18) 984 #define WEIGHT_SPARE0_SHIFT 18 985 #define WEIGHT_SPARE1(x) ((x) << 24) 986 #define WEIGHT_SPARE1_MASK (0x3f << 24) 987 #define WEIGHT_SPARE1_SHIFT 24 988 #define CG_CAC_REGION_5_WEIGHT_0 0x8e 989 #define WEIGHT_SQ_VSP(x) ((x) << 0) 990 #define WEIGHT_SQ_VSP_MASK (0x3fff << 0) 991 #define WEIGHT_SQ_VSP_SHIFT 0 992 #define WEIGHT_SQ_VSP0(x) ((x) << 14) 993 #define WEIGHT_SQ_VSP0_MASK (0x3fff << 14) 994 #define WEIGHT_SQ_VSP0_SHIFT 14 995 #define CG_CAC_REGION_4_OVERRIDE_4 0xab 996 #define OVR_MODE_SPARE_0(x) ((x) << 16) 997 #define OVR_MODE_SPARE_0_MASK (0x1 << 16) 998 #define OVR_MODE_SPARE_0_SHIFT 16 999 #define OVR_VAL_SPARE_0(x) ((x) << 17) 1000 #define OVR_VAL_SPARE_0_MASK (0x1 << 17) 1001 #define OVR_VAL_SPARE_0_SHIFT 17 1002 #define OVR_MODE_SPARE_1(x) ((x) << 18) 1003 #define OVR_MODE_SPARE_1_MASK (0x3f << 18) 1004 #define OVR_MODE_SPARE_1_SHIFT 18 1005 #define OVR_VAL_SPARE_1(x) ((x) << 19) 1006 #define OVR_VAL_SPARE_1_MASK (0x3f << 19) 1007 #define OVR_VAL_SPARE_1_SHIFT 19 1008 #define CG_CAC_REGION_5_WEIGHT_1 0xb7 1009 #define WEIGHT_SQ_GPR(x) ((x) << 0) 1010 #define WEIGHT_SQ_GPR_MASK (0x3fff << 0) 1011 #define WEIGHT_SQ_GPR_SHIFT 0 1012 #define WEIGHT_SQ_LDS(x) ((x) << 14) 1013 #define WEIGHT_SQ_LDS_MASK (0x3fff << 14) 1014 #define WEIGHT_SQ_LDS_SHIFT 14 1015 1016 /* PCIE link stuff */ 1017 #define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */ 1018 #define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */ 1019 # define LC_LINK_WIDTH_SHIFT 0 1020 # define LC_LINK_WIDTH_MASK 0x7 1021 # define LC_LINK_WIDTH_X0 0 1022 # define LC_LINK_WIDTH_X1 1 1023 # define LC_LINK_WIDTH_X2 2 1024 # define LC_LINK_WIDTH_X4 3 1025 # define LC_LINK_WIDTH_X8 4 1026 # define LC_LINK_WIDTH_X16 6 1027 # define LC_LINK_WIDTH_RD_SHIFT 4 1028 # define LC_LINK_WIDTH_RD_MASK 0x70 1029 # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) 1030 # define LC_RECONFIG_NOW (1 << 8) 1031 # define LC_RENEGOTIATION_SUPPORT (1 << 9) 1032 # define LC_RENEGOTIATE_EN (1 << 10) 1033 # define LC_SHORT_RECONFIG_EN (1 << 11) 1034 # define LC_UPCONFIGURE_SUPPORT (1 << 12) 1035 # define LC_UPCONFIGURE_DIS (1 << 13) 1036 #define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */ 1037 # define LC_GEN2_EN_STRAP (1 << 0) 1038 # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1) 1039 # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5) 1040 # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6) 1041 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8) 1042 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3 1043 # define LC_CURRENT_DATA_RATE (1 << 11) 1044 # define LC_HW_VOLTAGE_IF_CONTROL(x) ((x) << 12) 1045 # define LC_HW_VOLTAGE_IF_CONTROL_MASK (3 << 12) 1046 # define LC_HW_VOLTAGE_IF_CONTROL_SHIFT 12 1047 # define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14) 1048 # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21) 1049 # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23) 1050 # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24) 1051 #define MM_CFGREGS_CNTL 0x544c 1052 # define MM_WR_TO_CFG_EN (1 << 3) 1053 #define LINK_CNTL2 0x88 /* F0 */ 1054 # define TARGET_LINK_SPEED_MASK (0xf << 0) 1055 # define SELECTABLE_DEEMPHASIS (1 << 6) 1056 1057 /* 1058 * UVD 1059 */ 1060 #define UVD_SEMA_ADDR_LOW 0xEF00 1061 #define UVD_SEMA_ADDR_HIGH 0xEF04 1062 #define UVD_SEMA_CMD 0xEF08 1063 #define UVD_UDEC_ADDR_CONFIG 0xEF4C 1064 #define UVD_UDEC_DB_ADDR_CONFIG 0xEF50 1065 #define UVD_UDEC_DBW_ADDR_CONFIG 0xEF54 1066 #define UVD_RBC_RB_RPTR 0xF690 1067 #define UVD_RBC_RB_WPTR 0xF694 1068 1069 /* 1070 * PM4 1071 */ 1072 #define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \ 1073 (((reg) >> 2) & 0xFFFF) | \ 1074 ((n) & 0x3FFF) << 16) 1075 #define CP_PACKET2 0x80000000 1076 #define PACKET2_PAD_SHIFT 0 1077 #define PACKET2_PAD_MASK (0x3fffffff << 0) 1078 1079 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 1080 1081 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ 1082 (((op) & 0xFF) << 8) | \ 1083 ((n) & 0x3FFF) << 16) 1084 1085 /* Packet 3 types */ 1086 #define PACKET3_NOP 0x10 1087 #define PACKET3_SET_BASE 0x11 1088 #define PACKET3_CLEAR_STATE 0x12 1089 #define PACKET3_INDEX_BUFFER_SIZE 0x13 1090 #define PACKET3_DEALLOC_STATE 0x14 1091 #define PACKET3_DISPATCH_DIRECT 0x15 1092 #define PACKET3_DISPATCH_INDIRECT 0x16 1093 #define PACKET3_INDIRECT_BUFFER_END 0x17 1094 #define PACKET3_MODE_CONTROL 0x18 1095 #define PACKET3_SET_PREDICATION 0x20 1096 #define PACKET3_REG_RMW 0x21 1097 #define PACKET3_COND_EXEC 0x22 1098 #define PACKET3_PRED_EXEC 0x23 1099 #define PACKET3_DRAW_INDIRECT 0x24 1100 #define PACKET3_DRAW_INDEX_INDIRECT 0x25 1101 #define PACKET3_INDEX_BASE 0x26 1102 #define PACKET3_DRAW_INDEX_2 0x27 1103 #define PACKET3_CONTEXT_CONTROL 0x28 1104 #define PACKET3_DRAW_INDEX_OFFSET 0x29 1105 #define PACKET3_INDEX_TYPE 0x2A 1106 #define PACKET3_DRAW_INDEX 0x2B 1107 #define PACKET3_DRAW_INDEX_AUTO 0x2D 1108 #define PACKET3_DRAW_INDEX_IMMD 0x2E 1109 #define PACKET3_NUM_INSTANCES 0x2F 1110 #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 1111 #define PACKET3_INDIRECT_BUFFER 0x32 1112 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 1113 #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 1114 #define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36 1115 #define PACKET3_WRITE_DATA 0x37 1116 #define PACKET3_MEM_SEMAPHORE 0x39 1117 #define PACKET3_MPEG_INDEX 0x3A 1118 #define PACKET3_WAIT_REG_MEM 0x3C 1119 #define PACKET3_MEM_WRITE 0x3D 1120 #define PACKET3_PFP_SYNC_ME 0x42 1121 #define PACKET3_SURFACE_SYNC 0x43 1122 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 1123 # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 1124 # define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 1125 # define PACKET3_CB3_DEST_BASE_ENA (1 << 9) 1126 # define PACKET3_CB4_DEST_BASE_ENA (1 << 10) 1127 # define PACKET3_CB5_DEST_BASE_ENA (1 << 11) 1128 # define PACKET3_CB6_DEST_BASE_ENA (1 << 12) 1129 # define PACKET3_CB7_DEST_BASE_ENA (1 << 13) 1130 # define PACKET3_DB_DEST_BASE_ENA (1 << 14) 1131 # define PACKET3_CB8_DEST_BASE_ENA (1 << 15) 1132 # define PACKET3_CB9_DEST_BASE_ENA (1 << 16) 1133 # define PACKET3_CB10_DEST_BASE_ENA (1 << 17) 1134 # define PACKET3_CB11_DEST_BASE_ENA (1 << 18) 1135 # define PACKET3_FULL_CACHE_ENA (1 << 20) 1136 # define PACKET3_TC_ACTION_ENA (1 << 23) 1137 # define PACKET3_CB_ACTION_ENA (1 << 25) 1138 # define PACKET3_DB_ACTION_ENA (1 << 26) 1139 # define PACKET3_SH_ACTION_ENA (1 << 27) 1140 # define PACKET3_SX_ACTION_ENA (1 << 28) 1141 #define PACKET3_ME_INITIALIZE 0x44 1142 #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 1143 #define PACKET3_COND_WRITE 0x45 1144 #define PACKET3_EVENT_WRITE 0x46 1145 #define EVENT_TYPE(x) ((x) << 0) 1146 #define EVENT_INDEX(x) ((x) << 8) 1147 /* 0 - any non-TS event 1148 * 1 - ZPASS_DONE 1149 * 2 - SAMPLE_PIPELINESTAT 1150 * 3 - SAMPLE_STREAMOUTSTAT* 1151 * 4 - *S_PARTIAL_FLUSH 1152 * 5 - TS events 1153 */ 1154 #define PACKET3_EVENT_WRITE_EOP 0x47 1155 #define DATA_SEL(x) ((x) << 29) 1156 /* 0 - discard 1157 * 1 - send low 32bit data 1158 * 2 - send 64bit data 1159 * 3 - send 64bit counter value 1160 */ 1161 #define INT_SEL(x) ((x) << 24) 1162 /* 0 - none 1163 * 1 - interrupt only (DATA_SEL = 0) 1164 * 2 - interrupt when data write is confirmed 1165 */ 1166 #define PACKET3_EVENT_WRITE_EOS 0x48 1167 #define PACKET3_PREAMBLE_CNTL 0x4A 1168 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 1169 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 1170 #define PACKET3_ALU_PS_CONST_BUFFER_COPY 0x4C 1171 #define PACKET3_ALU_VS_CONST_BUFFER_COPY 0x4D 1172 #define PACKET3_ALU_PS_CONST_UPDATE 0x4E 1173 #define PACKET3_ALU_VS_CONST_UPDATE 0x4F 1174 #define PACKET3_ONE_REG_WRITE 0x57 1175 #define PACKET3_SET_CONFIG_REG 0x68 1176 #define PACKET3_SET_CONFIG_REG_START 0x00008000 1177 #define PACKET3_SET_CONFIG_REG_END 0x0000ac00 1178 #define PACKET3_SET_CONTEXT_REG 0x69 1179 #define PACKET3_SET_CONTEXT_REG_START 0x00028000 1180 #define PACKET3_SET_CONTEXT_REG_END 0x00029000 1181 #define PACKET3_SET_ALU_CONST 0x6A 1182 /* alu const buffers only; no reg file */ 1183 #define PACKET3_SET_BOOL_CONST 0x6B 1184 #define PACKET3_SET_BOOL_CONST_START 0x0003a500 1185 #define PACKET3_SET_BOOL_CONST_END 0x0003a518 1186 #define PACKET3_SET_LOOP_CONST 0x6C 1187 #define PACKET3_SET_LOOP_CONST_START 0x0003a200 1188 #define PACKET3_SET_LOOP_CONST_END 0x0003a500 1189 #define PACKET3_SET_RESOURCE 0x6D 1190 #define PACKET3_SET_RESOURCE_START 0x00030000 1191 #define PACKET3_SET_RESOURCE_END 0x00038000 1192 #define PACKET3_SET_SAMPLER 0x6E 1193 #define PACKET3_SET_SAMPLER_START 0x0003c000 1194 #define PACKET3_SET_SAMPLER_END 0x0003c600 1195 #define PACKET3_SET_CTL_CONST 0x6F 1196 #define PACKET3_SET_CTL_CONST_START 0x0003cff0 1197 #define PACKET3_SET_CTL_CONST_END 0x0003ff0c 1198 #define PACKET3_SET_RESOURCE_OFFSET 0x70 1199 #define PACKET3_SET_ALU_CONST_VS 0x71 1200 #define PACKET3_SET_ALU_CONST_DI 0x72 1201 #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 1202 #define PACKET3_SET_RESOURCE_INDIRECT 0x74 1203 #define PACKET3_SET_APPEND_CNT 0x75 1204 #define PACKET3_ME_WRITE 0x7A 1205 1206 /* ASYNC DMA - first instance at 0xd000, second at 0xd800 */ 1207 #define DMA0_REGISTER_OFFSET 0x0 /* not a register */ 1208 #define DMA1_REGISTER_OFFSET 0x800 /* not a register */ 1209 1210 #define DMA_RB_CNTL 0xd000 1211 # define DMA_RB_ENABLE (1 << 0) 1212 # define DMA_RB_SIZE(x) ((x) << 1) /* log2 */ 1213 # define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */ 1214 # define DMA_RPTR_WRITEBACK_ENABLE (1 << 12) 1215 # define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */ 1216 # define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */ 1217 #define DMA_RB_BASE 0xd004 1218 #define DMA_RB_RPTR 0xd008 1219 #define DMA_RB_WPTR 0xd00c 1220 1221 #define DMA_RB_RPTR_ADDR_HI 0xd01c 1222 #define DMA_RB_RPTR_ADDR_LO 0xd020 1223 1224 #define DMA_IB_CNTL 0xd024 1225 # define DMA_IB_ENABLE (1 << 0) 1226 # define DMA_IB_SWAP_ENABLE (1 << 4) 1227 # define CMD_VMID_FORCE (1 << 31) 1228 #define DMA_IB_RPTR 0xd028 1229 #define DMA_CNTL 0xd02c 1230 # define TRAP_ENABLE (1 << 0) 1231 # define SEM_INCOMPLETE_INT_ENABLE (1 << 1) 1232 # define SEM_WAIT_INT_ENABLE (1 << 2) 1233 # define DATA_SWAP_ENABLE (1 << 3) 1234 # define FENCE_SWAP_ENABLE (1 << 4) 1235 # define CTXEMPTY_INT_ENABLE (1 << 28) 1236 #define DMA_STATUS_REG 0xd034 1237 # define DMA_IDLE (1 << 0) 1238 #define DMA_SEM_INCOMPLETE_TIMER_CNTL 0xd044 1239 #define DMA_SEM_WAIT_FAIL_TIMER_CNTL 0xd048 1240 #define DMA_TILING_CONFIG 0xd0b8 1241 #define DMA_MODE 0xd0bc 1242 1243 #define DMA_PACKET(cmd, t, s, n) ((((cmd) & 0xF) << 28) | \ 1244 (((t) & 0x1) << 23) | \ 1245 (((s) & 0x1) << 22) | \ 1246 (((n) & 0xFFFFF) << 0)) 1247 1248 #define DMA_IB_PACKET(cmd, vmid, n) ((((cmd) & 0xF) << 28) | \ 1249 (((vmid) & 0xF) << 20) | \ 1250 (((n) & 0xFFFFF) << 0)) 1251 1252 #define DMA_PTE_PDE_PACKET(n) ((2 << 28) | \ 1253 (1 << 26) | \ 1254 (1 << 21) | \ 1255 (((n) & 0xFFFFF) << 0)) 1256 1257 /* async DMA Packet types */ 1258 #define DMA_PACKET_WRITE 0x2 1259 #define DMA_PACKET_COPY 0x3 1260 #define DMA_PACKET_INDIRECT_BUFFER 0x4 1261 #define DMA_PACKET_SEMAPHORE 0x5 1262 #define DMA_PACKET_FENCE 0x6 1263 #define DMA_PACKET_TRAP 0x7 1264 #define DMA_PACKET_SRBM_WRITE 0x9 1265 #define DMA_PACKET_CONSTANT_FILL 0xd 1266 #define DMA_PACKET_NOP 0xf 1267 1268 #endif 1269