10af62b01SAlex Deucher /* 20af62b01SAlex Deucher * Copyright 2010 Advanced Micro Devices, Inc. 30af62b01SAlex Deucher * 40af62b01SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 50af62b01SAlex Deucher * copy of this software and associated documentation files (the "Software"), 60af62b01SAlex Deucher * to deal in the Software without restriction, including without limitation 70af62b01SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 80af62b01SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 90af62b01SAlex Deucher * Software is furnished to do so, subject to the following conditions: 100af62b01SAlex Deucher * 110af62b01SAlex Deucher * The above copyright notice and this permission notice shall be included in 120af62b01SAlex Deucher * all copies or substantial portions of the Software. 130af62b01SAlex Deucher * 140af62b01SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 150af62b01SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 160af62b01SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 170af62b01SAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 180af62b01SAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 190af62b01SAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 200af62b01SAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 210af62b01SAlex Deucher * 220af62b01SAlex Deucher * Authors: Alex Deucher 230af62b01SAlex Deucher */ 240af62b01SAlex Deucher #ifndef NI_H 250af62b01SAlex Deucher #define NI_H 260af62b01SAlex Deucher 27fecf1d07SAlex Deucher #define CAYMAN_MAX_SH_GPRS 256 28fecf1d07SAlex Deucher #define CAYMAN_MAX_TEMP_GPRS 16 29fecf1d07SAlex Deucher #define CAYMAN_MAX_SH_THREADS 256 30fecf1d07SAlex Deucher #define CAYMAN_MAX_SH_STACK_ENTRIES 4096 31fecf1d07SAlex Deucher #define CAYMAN_MAX_FRC_EOV_CNT 16384 32fecf1d07SAlex Deucher #define CAYMAN_MAX_BACKENDS 8 33fecf1d07SAlex Deucher #define CAYMAN_MAX_BACKENDS_MASK 0xFF 34fecf1d07SAlex Deucher #define CAYMAN_MAX_BACKENDS_PER_SE_MASK 0xF 35fecf1d07SAlex Deucher #define CAYMAN_MAX_SIMDS 16 36fecf1d07SAlex Deucher #define CAYMAN_MAX_SIMDS_MASK 0xFFFF 37fecf1d07SAlex Deucher #define CAYMAN_MAX_SIMDS_PER_SE_MASK 0xFFF 38fecf1d07SAlex Deucher #define CAYMAN_MAX_PIPES 8 39fecf1d07SAlex Deucher #define CAYMAN_MAX_PIPES_MASK 0xFF 40fecf1d07SAlex Deucher #define CAYMAN_MAX_LDS_NUM 0xFFFF 41fecf1d07SAlex Deucher #define CAYMAN_MAX_TCC 16 42fecf1d07SAlex Deucher #define CAYMAN_MAX_TCC_MASK 0xFF 43fecf1d07SAlex Deucher 44416a2bd2SAlex Deucher #define CAYMAN_GB_ADDR_CONFIG_GOLDEN 0x02011003 45416a2bd2SAlex Deucher #define ARUBA_GB_ADDR_CONFIG_GOLDEN 0x12010001 46416a2bd2SAlex Deucher 47fecf1d07SAlex Deucher #define DMIF_ADDR_CONFIG 0xBD4 481b37078bSAlex Deucher #define SRBM_GFX_CNTL 0x0E44 491b37078bSAlex Deucher #define RINGID(x) (((x) & 0x3) << 0) 501b37078bSAlex Deucher #define VMID(x) (((x) & 0x7) << 0) 51b9952a8aSAlex Deucher #define SRBM_STATUS 0x0E50 52*168757eaSAlex Deucher #define RLC_RQ_PENDING (1 << 3) 53*168757eaSAlex Deucher #define GRBM_RQ_PENDING (1 << 5) 54*168757eaSAlex Deucher #define VMC_BUSY (1 << 8) 55*168757eaSAlex Deucher #define MCB_BUSY (1 << 9) 56*168757eaSAlex Deucher #define MCB_NON_DISPLAY_BUSY (1 << 10) 57*168757eaSAlex Deucher #define MCC_BUSY (1 << 11) 58*168757eaSAlex Deucher #define MCD_BUSY (1 << 12) 59*168757eaSAlex Deucher #define SEM_BUSY (1 << 14) 60*168757eaSAlex Deucher #define RLC_BUSY (1 << 15) 61*168757eaSAlex Deucher #define IH_BUSY (1 << 17) 62fecf1d07SAlex Deucher 63f60cbd11SAlex Deucher #define SRBM_SOFT_RESET 0x0E60 64f60cbd11SAlex Deucher #define SOFT_RESET_BIF (1 << 1) 65f60cbd11SAlex Deucher #define SOFT_RESET_CG (1 << 2) 66f60cbd11SAlex Deucher #define SOFT_RESET_DC (1 << 5) 67f60cbd11SAlex Deucher #define SOFT_RESET_DMA1 (1 << 6) 68f60cbd11SAlex Deucher #define SOFT_RESET_GRBM (1 << 8) 69f60cbd11SAlex Deucher #define SOFT_RESET_HDP (1 << 9) 70f60cbd11SAlex Deucher #define SOFT_RESET_IH (1 << 10) 71f60cbd11SAlex Deucher #define SOFT_RESET_MC (1 << 11) 72f60cbd11SAlex Deucher #define SOFT_RESET_RLC (1 << 13) 73f60cbd11SAlex Deucher #define SOFT_RESET_ROM (1 << 14) 74f60cbd11SAlex Deucher #define SOFT_RESET_SEM (1 << 15) 75f60cbd11SAlex Deucher #define SOFT_RESET_VMC (1 << 17) 76f60cbd11SAlex Deucher #define SOFT_RESET_DMA (1 << 20) 77f60cbd11SAlex Deucher #define SOFT_RESET_TST (1 << 21) 78f60cbd11SAlex Deucher #define SOFT_RESET_REGBB (1 << 22) 79f60cbd11SAlex Deucher #define SOFT_RESET_ORB (1 << 23) 80f60cbd11SAlex Deucher 81*168757eaSAlex Deucher #define SRBM_STATUS2 0x0EC4 82*168757eaSAlex Deucher #define DMA_BUSY (1 << 5) 83*168757eaSAlex Deucher #define DMA1_BUSY (1 << 6) 84*168757eaSAlex Deucher 85fa8198eaSAlex Deucher #define VM_CONTEXT0_REQUEST_RESPONSE 0x1470 86fa8198eaSAlex Deucher #define REQUEST_TYPE(x) (((x) & 0xf) << 0) 87fa8198eaSAlex Deucher #define RESPONSE_TYPE_MASK 0x000000F0 88fa8198eaSAlex Deucher #define RESPONSE_TYPE_SHIFT 4 89fa8198eaSAlex Deucher #define VM_L2_CNTL 0x1400 90fa8198eaSAlex Deucher #define ENABLE_L2_CACHE (1 << 0) 91fa8198eaSAlex Deucher #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 92fa8198eaSAlex Deucher #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 93fa8198eaSAlex Deucher #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10) 94fa8198eaSAlex Deucher #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14) 95fa8198eaSAlex Deucher #define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 18) 96fa8198eaSAlex Deucher /* CONTEXT1_IDENTITY_ACCESS_MODE 97fa8198eaSAlex Deucher * 0 physical = logical 98fa8198eaSAlex Deucher * 1 logical via context1 page table 99fa8198eaSAlex Deucher * 2 inside identity aperture use translation, outside physical = logical 100fa8198eaSAlex Deucher * 3 inside identity aperture physical = logical, outside use translation 101fa8198eaSAlex Deucher */ 102fa8198eaSAlex Deucher #define VM_L2_CNTL2 0x1404 103fa8198eaSAlex Deucher #define INVALIDATE_ALL_L1_TLBS (1 << 0) 104fa8198eaSAlex Deucher #define INVALIDATE_L2_CACHE (1 << 1) 105fa8198eaSAlex Deucher #define VM_L2_CNTL3 0x1408 106fa8198eaSAlex Deucher #define BANK_SELECT(x) ((x) << 0) 107fa8198eaSAlex Deucher #define CACHE_UPDATE_MODE(x) ((x) << 6) 108fa8198eaSAlex Deucher #define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20) 109fa8198eaSAlex Deucher #define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15) 110fa8198eaSAlex Deucher #define VM_L2_STATUS 0x140C 111fa8198eaSAlex Deucher #define L2_BUSY (1 << 0) 112fa8198eaSAlex Deucher #define VM_CONTEXT0_CNTL 0x1410 113fa8198eaSAlex Deucher #define ENABLE_CONTEXT (1 << 0) 114fa8198eaSAlex Deucher #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 115ae133a11SChristian König #define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3) 116fa8198eaSAlex Deucher #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 117ae133a11SChristian König #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6) 118ae133a11SChristian König #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7) 119ae133a11SChristian König #define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9) 120ae133a11SChristian König #define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10) 121ae133a11SChristian König #define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12) 122ae133a11SChristian König #define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13) 123ae133a11SChristian König #define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15) 124ae133a11SChristian König #define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16) 125ae133a11SChristian König #define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18) 126ae133a11SChristian König #define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19) 127fa8198eaSAlex Deucher #define VM_CONTEXT1_CNTL 0x1414 128fa8198eaSAlex Deucher #define VM_CONTEXT0_CNTL2 0x1430 129fa8198eaSAlex Deucher #define VM_CONTEXT1_CNTL2 0x1434 130fa8198eaSAlex Deucher #define VM_INVALIDATE_REQUEST 0x1478 131fa8198eaSAlex Deucher #define VM_INVALIDATE_RESPONSE 0x147c 132fa8198eaSAlex Deucher #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 133fa8198eaSAlex Deucher #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c 134fa8198eaSAlex Deucher #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C 135fa8198eaSAlex Deucher #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C 136fa8198eaSAlex Deucher #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C 137fa8198eaSAlex Deucher 138fecf1d07SAlex Deucher #define MC_SHARED_CHMAP 0x2004 139fecf1d07SAlex Deucher #define NOOFCHAN_SHIFT 12 140fecf1d07SAlex Deucher #define NOOFCHAN_MASK 0x00003000 141fecf1d07SAlex Deucher #define MC_SHARED_CHREMAP 0x2008 142fa8198eaSAlex Deucher 143fa8198eaSAlex Deucher #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 144fa8198eaSAlex Deucher #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 145fa8198eaSAlex Deucher #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C 146fa8198eaSAlex Deucher #define MC_VM_MX_L1_TLB_CNTL 0x2064 147fa8198eaSAlex Deucher #define ENABLE_L1_TLB (1 << 0) 148fa8198eaSAlex Deucher #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 149fa8198eaSAlex Deucher #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) 150fa8198eaSAlex Deucher #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) 151fa8198eaSAlex Deucher #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 152fa8198eaSAlex Deucher #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) 153fa8198eaSAlex Deucher #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 154fa8198eaSAlex Deucher #define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6) 15505b3ef69SAlex Deucher #define FUS_MC_VM_FB_OFFSET 0x2068 156fa8198eaSAlex Deucher 1570af62b01SAlex Deucher #define MC_SHARED_BLACKOUT_CNTL 0x20ac 158fecf1d07SAlex Deucher #define MC_ARB_RAMCFG 0x2760 159fecf1d07SAlex Deucher #define NOOFBANK_SHIFT 0 160fecf1d07SAlex Deucher #define NOOFBANK_MASK 0x00000003 161fecf1d07SAlex Deucher #define NOOFRANK_SHIFT 2 162fecf1d07SAlex Deucher #define NOOFRANK_MASK 0x00000004 163fecf1d07SAlex Deucher #define NOOFROWS_SHIFT 3 164fecf1d07SAlex Deucher #define NOOFROWS_MASK 0x00000038 165fecf1d07SAlex Deucher #define NOOFCOLS_SHIFT 6 166fecf1d07SAlex Deucher #define NOOFCOLS_MASK 0x000000C0 167fecf1d07SAlex Deucher #define CHANSIZE_SHIFT 8 168fecf1d07SAlex Deucher #define CHANSIZE_MASK 0x00000100 169fecf1d07SAlex Deucher #define BURSTLENGTH_SHIFT 9 170fecf1d07SAlex Deucher #define BURSTLENGTH_MASK 0x00000200 171fecf1d07SAlex Deucher #define CHANSIZE_OVERRIDE (1 << 11) 1720af62b01SAlex Deucher #define MC_SEQ_SUP_CNTL 0x28c8 1730af62b01SAlex Deucher #define RUN_MASK (1 << 0) 1740af62b01SAlex Deucher #define MC_SEQ_SUP_PGM 0x28cc 1750af62b01SAlex Deucher #define MC_IO_PAD_CNTL_D0 0x29d0 1760af62b01SAlex Deucher #define MEM_FALL_OUT_CMD (1 << 8) 1770af62b01SAlex Deucher #define MC_SEQ_MISC0 0x2a00 1780af62b01SAlex Deucher #define MC_SEQ_MISC0_GDDR5_SHIFT 28 1790af62b01SAlex Deucher #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000 1800af62b01SAlex Deucher #define MC_SEQ_MISC0_GDDR5_VALUE 5 1810af62b01SAlex Deucher #define MC_SEQ_IO_DEBUG_INDEX 0x2a44 1820af62b01SAlex Deucher #define MC_SEQ_IO_DEBUG_DATA 0x2a48 1830af62b01SAlex Deucher 184fecf1d07SAlex Deucher #define HDP_HOST_PATH_CNTL 0x2C00 185fecf1d07SAlex Deucher #define HDP_NONSURFACE_BASE 0x2C04 186fecf1d07SAlex Deucher #define HDP_NONSURFACE_INFO 0x2C08 187fecf1d07SAlex Deucher #define HDP_NONSURFACE_SIZE 0x2C0C 188fecf1d07SAlex Deucher #define HDP_ADDR_CONFIG 0x2F48 1890b65f83fSDave Airlie #define HDP_MISC_CNTL 0x2F4C 1900b65f83fSDave Airlie #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0) 191fecf1d07SAlex Deucher 192fecf1d07SAlex Deucher #define CC_SYS_RB_BACKEND_DISABLE 0x3F88 193fecf1d07SAlex Deucher #define GC_USER_SYS_RB_BACKEND_DISABLE 0x3F8C 194fecf1d07SAlex Deucher #define CGTS_SYS_TCC_DISABLE 0x3F90 195fecf1d07SAlex Deucher #define CGTS_USER_SYS_TCC_DISABLE 0x3F94 196fecf1d07SAlex Deucher 197416a2bd2SAlex Deucher #define RLC_GFX_INDEX 0x3FC4 198416a2bd2SAlex Deucher 199fecf1d07SAlex Deucher #define CONFIG_MEMSIZE 0x5428 200fecf1d07SAlex Deucher 201fa8198eaSAlex Deucher #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 202fecf1d07SAlex Deucher #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 203fecf1d07SAlex Deucher 204fecf1d07SAlex Deucher #define GRBM_CNTL 0x8000 205fecf1d07SAlex Deucher #define GRBM_READ_TIMEOUT(x) ((x) << 0) 206fecf1d07SAlex Deucher #define GRBM_STATUS 0x8010 207fecf1d07SAlex Deucher #define CMDFIFO_AVAIL_MASK 0x0000000F 208fecf1d07SAlex Deucher #define RING2_RQ_PENDING (1 << 4) 209fecf1d07SAlex Deucher #define SRBM_RQ_PENDING (1 << 5) 210fecf1d07SAlex Deucher #define RING1_RQ_PENDING (1 << 6) 211fecf1d07SAlex Deucher #define CF_RQ_PENDING (1 << 7) 212fecf1d07SAlex Deucher #define PF_RQ_PENDING (1 << 8) 213fecf1d07SAlex Deucher #define GDS_DMA_RQ_PENDING (1 << 9) 214fecf1d07SAlex Deucher #define GRBM_EE_BUSY (1 << 10) 215fecf1d07SAlex Deucher #define SX_CLEAN (1 << 11) 216fecf1d07SAlex Deucher #define DB_CLEAN (1 << 12) 217fecf1d07SAlex Deucher #define CB_CLEAN (1 << 13) 218fecf1d07SAlex Deucher #define TA_BUSY (1 << 14) 219fecf1d07SAlex Deucher #define GDS_BUSY (1 << 15) 220fecf1d07SAlex Deucher #define VGT_BUSY_NO_DMA (1 << 16) 221fecf1d07SAlex Deucher #define VGT_BUSY (1 << 17) 222fecf1d07SAlex Deucher #define IA_BUSY_NO_DMA (1 << 18) 223fecf1d07SAlex Deucher #define IA_BUSY (1 << 19) 224fecf1d07SAlex Deucher #define SX_BUSY (1 << 20) 225fecf1d07SAlex Deucher #define SH_BUSY (1 << 21) 226fecf1d07SAlex Deucher #define SPI_BUSY (1 << 22) 227fecf1d07SAlex Deucher #define SC_BUSY (1 << 24) 228fecf1d07SAlex Deucher #define PA_BUSY (1 << 25) 229fecf1d07SAlex Deucher #define DB_BUSY (1 << 26) 230fecf1d07SAlex Deucher #define CP_COHERENCY_BUSY (1 << 28) 231fecf1d07SAlex Deucher #define CP_BUSY (1 << 29) 232fecf1d07SAlex Deucher #define CB_BUSY (1 << 30) 233fecf1d07SAlex Deucher #define GUI_ACTIVE (1 << 31) 234fecf1d07SAlex Deucher #define GRBM_STATUS_SE0 0x8014 235fecf1d07SAlex Deucher #define GRBM_STATUS_SE1 0x8018 236fecf1d07SAlex Deucher #define SE_SX_CLEAN (1 << 0) 237fecf1d07SAlex Deucher #define SE_DB_CLEAN (1 << 1) 238fecf1d07SAlex Deucher #define SE_CB_CLEAN (1 << 2) 239fecf1d07SAlex Deucher #define SE_VGT_BUSY (1 << 23) 240fecf1d07SAlex Deucher #define SE_PA_BUSY (1 << 24) 241fecf1d07SAlex Deucher #define SE_TA_BUSY (1 << 25) 242fecf1d07SAlex Deucher #define SE_SX_BUSY (1 << 26) 243fecf1d07SAlex Deucher #define SE_SPI_BUSY (1 << 27) 244fecf1d07SAlex Deucher #define SE_SH_BUSY (1 << 28) 245fecf1d07SAlex Deucher #define SE_SC_BUSY (1 << 29) 246fecf1d07SAlex Deucher #define SE_DB_BUSY (1 << 30) 247fecf1d07SAlex Deucher #define SE_CB_BUSY (1 << 31) 248fecf1d07SAlex Deucher #define GRBM_SOFT_RESET 0x8020 249fecf1d07SAlex Deucher #define SOFT_RESET_CP (1 << 0) 250fecf1d07SAlex Deucher #define SOFT_RESET_CB (1 << 1) 251fecf1d07SAlex Deucher #define SOFT_RESET_DB (1 << 3) 252fecf1d07SAlex Deucher #define SOFT_RESET_GDS (1 << 4) 253fecf1d07SAlex Deucher #define SOFT_RESET_PA (1 << 5) 254fecf1d07SAlex Deucher #define SOFT_RESET_SC (1 << 6) 255fecf1d07SAlex Deucher #define SOFT_RESET_SPI (1 << 8) 256fecf1d07SAlex Deucher #define SOFT_RESET_SH (1 << 9) 257fecf1d07SAlex Deucher #define SOFT_RESET_SX (1 << 10) 258fecf1d07SAlex Deucher #define SOFT_RESET_TC (1 << 11) 259fecf1d07SAlex Deucher #define SOFT_RESET_TA (1 << 12) 260fecf1d07SAlex Deucher #define SOFT_RESET_VGT (1 << 14) 261fecf1d07SAlex Deucher #define SOFT_RESET_IA (1 << 15) 262fecf1d07SAlex Deucher 263416a2bd2SAlex Deucher #define GRBM_GFX_INDEX 0x802C 264416a2bd2SAlex Deucher #define INSTANCE_INDEX(x) ((x) << 0) 265416a2bd2SAlex Deucher #define SE_INDEX(x) ((x) << 16) 266416a2bd2SAlex Deucher #define INSTANCE_BROADCAST_WRITES (1 << 30) 267416a2bd2SAlex Deucher #define SE_BROADCAST_WRITES (1 << 31) 268416a2bd2SAlex Deucher 2690c88a02eSAlex Deucher #define SCRATCH_REG0 0x8500 2700c88a02eSAlex Deucher #define SCRATCH_REG1 0x8504 2710c88a02eSAlex Deucher #define SCRATCH_REG2 0x8508 2720c88a02eSAlex Deucher #define SCRATCH_REG3 0x850C 2730c88a02eSAlex Deucher #define SCRATCH_REG4 0x8510 2740c88a02eSAlex Deucher #define SCRATCH_REG5 0x8514 2750c88a02eSAlex Deucher #define SCRATCH_REG6 0x8518 2760c88a02eSAlex Deucher #define SCRATCH_REG7 0x851C 2770c88a02eSAlex Deucher #define SCRATCH_UMSK 0x8540 2780c88a02eSAlex Deucher #define SCRATCH_ADDR 0x8544 2790c88a02eSAlex Deucher #define CP_SEM_WAIT_TIMER 0x85BC 28011ef3f1fSAlex Deucher #define CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8 281721604a1SJerome Glisse #define CP_COHER_CNTL2 0x85E8 282440a7cd8SJerome Glisse #define CP_STALLED_STAT1 0x8674 283440a7cd8SJerome Glisse #define CP_STALLED_STAT2 0x8678 284440a7cd8SJerome Glisse #define CP_BUSY_STAT 0x867C 285440a7cd8SJerome Glisse #define CP_STAT 0x8680 2860c88a02eSAlex Deucher #define CP_ME_CNTL 0x86D8 2870c88a02eSAlex Deucher #define CP_ME_HALT (1 << 28) 2880c88a02eSAlex Deucher #define CP_PFP_HALT (1 << 26) 2890c88a02eSAlex Deucher #define CP_RB2_RPTR 0x86f8 2900c88a02eSAlex Deucher #define CP_RB1_RPTR 0x86fc 2910c88a02eSAlex Deucher #define CP_RB0_RPTR 0x8700 2920c88a02eSAlex Deucher #define CP_RB_WPTR_DELAY 0x8704 293fecf1d07SAlex Deucher #define CP_MEQ_THRESHOLDS 0x8764 294fecf1d07SAlex Deucher #define MEQ1_START(x) ((x) << 0) 295fecf1d07SAlex Deucher #define MEQ2_START(x) ((x) << 8) 296fecf1d07SAlex Deucher #define CP_PERFMON_CNTL 0x87FC 297fecf1d07SAlex Deucher 298fecf1d07SAlex Deucher #define VGT_CACHE_INVALIDATION 0x88C4 299fecf1d07SAlex Deucher #define CACHE_INVALIDATION(x) ((x) << 0) 300fecf1d07SAlex Deucher #define VC_ONLY 0 301fecf1d07SAlex Deucher #define TC_ONLY 1 302fecf1d07SAlex Deucher #define VC_AND_TC 2 303fecf1d07SAlex Deucher #define AUTO_INVLD_EN(x) ((x) << 6) 304fecf1d07SAlex Deucher #define NO_AUTO 0 305fecf1d07SAlex Deucher #define ES_AUTO 1 306fecf1d07SAlex Deucher #define GS_AUTO 2 307fecf1d07SAlex Deucher #define ES_AND_GS_AUTO 3 308fecf1d07SAlex Deucher #define VGT_GS_VERTEX_REUSE 0x88D4 309fecf1d07SAlex Deucher 310fecf1d07SAlex Deucher #define CC_GC_SHADER_PIPE_CONFIG 0x8950 311fecf1d07SAlex Deucher #define GC_USER_SHADER_PIPE_CONFIG 0x8954 312fecf1d07SAlex Deucher #define INACTIVE_QD_PIPES(x) ((x) << 8) 313fecf1d07SAlex Deucher #define INACTIVE_QD_PIPES_MASK 0x0000FF00 314fecf1d07SAlex Deucher #define INACTIVE_QD_PIPES_SHIFT 8 315fecf1d07SAlex Deucher #define INACTIVE_SIMDS(x) ((x) << 16) 316fecf1d07SAlex Deucher #define INACTIVE_SIMDS_MASK 0xFFFF0000 317fecf1d07SAlex Deucher #define INACTIVE_SIMDS_SHIFT 16 318fecf1d07SAlex Deucher 319fecf1d07SAlex Deucher #define VGT_PRIMITIVE_TYPE 0x8958 320fecf1d07SAlex Deucher #define VGT_NUM_INSTANCES 0x8974 321fecf1d07SAlex Deucher #define VGT_TF_RING_SIZE 0x8988 322fecf1d07SAlex Deucher #define VGT_OFFCHIP_LDS_BASE 0x89b4 323fecf1d07SAlex Deucher 324fecf1d07SAlex Deucher #define PA_SC_LINE_STIPPLE_STATE 0x8B10 325fecf1d07SAlex Deucher #define PA_CL_ENHANCE 0x8A14 326fecf1d07SAlex Deucher #define CLIP_VTX_REORDER_ENA (1 << 0) 327fecf1d07SAlex Deucher #define NUM_CLIP_SEQ(x) ((x) << 1) 328fecf1d07SAlex Deucher #define PA_SC_FIFO_SIZE 0x8BCC 329fecf1d07SAlex Deucher #define SC_PRIM_FIFO_SIZE(x) ((x) << 0) 330fecf1d07SAlex Deucher #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12) 331fecf1d07SAlex Deucher #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20) 332fecf1d07SAlex Deucher #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 333fecf1d07SAlex Deucher #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 334fecf1d07SAlex Deucher #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) 335fecf1d07SAlex Deucher 336fecf1d07SAlex Deucher #define SQ_CONFIG 0x8C00 337fecf1d07SAlex Deucher #define VC_ENABLE (1 << 0) 338fecf1d07SAlex Deucher #define EXPORT_SRC_C (1 << 1) 339fecf1d07SAlex Deucher #define GFX_PRIO(x) ((x) << 2) 340fecf1d07SAlex Deucher #define CS1_PRIO(x) ((x) << 4) 341fecf1d07SAlex Deucher #define CS2_PRIO(x) ((x) << 6) 342fecf1d07SAlex Deucher #define SQ_GPR_RESOURCE_MGMT_1 0x8C04 343fecf1d07SAlex Deucher #define NUM_PS_GPRS(x) ((x) << 0) 344fecf1d07SAlex Deucher #define NUM_VS_GPRS(x) ((x) << 16) 345fecf1d07SAlex Deucher #define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) 346fecf1d07SAlex Deucher #define SQ_ESGS_RING_SIZE 0x8c44 347fecf1d07SAlex Deucher #define SQ_GSVS_RING_SIZE 0x8c4c 348fecf1d07SAlex Deucher #define SQ_ESTMP_RING_BASE 0x8c50 349fecf1d07SAlex Deucher #define SQ_ESTMP_RING_SIZE 0x8c54 350fecf1d07SAlex Deucher #define SQ_GSTMP_RING_BASE 0x8c58 351fecf1d07SAlex Deucher #define SQ_GSTMP_RING_SIZE 0x8c5c 352fecf1d07SAlex Deucher #define SQ_VSTMP_RING_BASE 0x8c60 353fecf1d07SAlex Deucher #define SQ_VSTMP_RING_SIZE 0x8c64 354fecf1d07SAlex Deucher #define SQ_PSTMP_RING_BASE 0x8c68 355fecf1d07SAlex Deucher #define SQ_PSTMP_RING_SIZE 0x8c6c 356fecf1d07SAlex Deucher #define SQ_MS_FIFO_SIZES 0x8CF0 357fecf1d07SAlex Deucher #define CACHE_FIFO_SIZE(x) ((x) << 0) 358fecf1d07SAlex Deucher #define FETCH_FIFO_HIWATER(x) ((x) << 8) 359fecf1d07SAlex Deucher #define DONE_FIFO_HIWATER(x) ((x) << 16) 360fecf1d07SAlex Deucher #define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) 361fecf1d07SAlex Deucher #define SQ_LSTMP_RING_BASE 0x8e10 362fecf1d07SAlex Deucher #define SQ_LSTMP_RING_SIZE 0x8e14 363fecf1d07SAlex Deucher #define SQ_HSTMP_RING_BASE 0x8e18 364fecf1d07SAlex Deucher #define SQ_HSTMP_RING_SIZE 0x8e1c 365fecf1d07SAlex Deucher #define SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 0x8D8C 366fecf1d07SAlex Deucher #define DYN_GPR_ENABLE (1 << 8) 367fecf1d07SAlex Deucher #define SQ_CONST_MEM_BASE 0x8df8 368fecf1d07SAlex Deucher 369fecf1d07SAlex Deucher #define SX_EXPORT_BUFFER_SIZES 0x900C 370fecf1d07SAlex Deucher #define COLOR_BUFFER_SIZE(x) ((x) << 0) 371fecf1d07SAlex Deucher #define POSITION_BUFFER_SIZE(x) ((x) << 8) 372fecf1d07SAlex Deucher #define SMX_BUFFER_SIZE(x) ((x) << 16) 373fecf1d07SAlex Deucher #define SX_DEBUG_1 0x9058 374fecf1d07SAlex Deucher #define ENABLE_NEW_SMX_ADDRESS (1 << 16) 375fecf1d07SAlex Deucher 376fecf1d07SAlex Deucher #define SPI_CONFIG_CNTL 0x9100 377fecf1d07SAlex Deucher #define GPR_WRITE_PRIORITY(x) ((x) << 0) 378fecf1d07SAlex Deucher #define SPI_CONFIG_CNTL_1 0x913C 379fecf1d07SAlex Deucher #define VTX_DONE_DELAY(x) ((x) << 0) 380fecf1d07SAlex Deucher #define INTERP_ONE_PRIM_PER_ROW (1 << 4) 381fecf1d07SAlex Deucher #define CRC_SIMD_ID_WADDR_DISABLE (1 << 8) 382fecf1d07SAlex Deucher 383fecf1d07SAlex Deucher #define CGTS_TCC_DISABLE 0x9148 384fecf1d07SAlex Deucher #define CGTS_USER_TCC_DISABLE 0x914C 385fecf1d07SAlex Deucher #define TCC_DISABLE_MASK 0xFFFF0000 386fecf1d07SAlex Deucher #define TCC_DISABLE_SHIFT 16 3872498c41eSAlex Deucher #define CGTS_SM_CTRL_REG 0x9150 388fecf1d07SAlex Deucher #define OVERRIDE (1 << 21) 389fecf1d07SAlex Deucher 390fecf1d07SAlex Deucher #define TA_CNTL_AUX 0x9508 391fecf1d07SAlex Deucher #define DISABLE_CUBE_WRAP (1 << 0) 392fecf1d07SAlex Deucher #define DISABLE_CUBE_ANISO (1 << 1) 393fecf1d07SAlex Deucher 394fecf1d07SAlex Deucher #define TCP_CHAN_STEER_LO 0x960c 395fecf1d07SAlex Deucher #define TCP_CHAN_STEER_HI 0x9610 396fecf1d07SAlex Deucher 397fecf1d07SAlex Deucher #define CC_RB_BACKEND_DISABLE 0x98F4 398fecf1d07SAlex Deucher #define BACKEND_DISABLE(x) ((x) << 16) 399fecf1d07SAlex Deucher #define GB_ADDR_CONFIG 0x98F8 400fecf1d07SAlex Deucher #define NUM_PIPES(x) ((x) << 0) 401fecf1d07SAlex Deucher #define NUM_PIPES_MASK 0x00000007 402fecf1d07SAlex Deucher #define NUM_PIPES_SHIFT 0 403fecf1d07SAlex Deucher #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) 404fecf1d07SAlex Deucher #define PIPE_INTERLEAVE_SIZE_MASK 0x00000070 405fecf1d07SAlex Deucher #define PIPE_INTERLEAVE_SIZE_SHIFT 4 406fecf1d07SAlex Deucher #define BANK_INTERLEAVE_SIZE(x) ((x) << 8) 407fecf1d07SAlex Deucher #define NUM_SHADER_ENGINES(x) ((x) << 12) 408fecf1d07SAlex Deucher #define NUM_SHADER_ENGINES_MASK 0x00003000 409fecf1d07SAlex Deucher #define NUM_SHADER_ENGINES_SHIFT 12 410fecf1d07SAlex Deucher #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) 411fecf1d07SAlex Deucher #define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000 412fecf1d07SAlex Deucher #define SHADER_ENGINE_TILE_SIZE_SHIFT 16 413fecf1d07SAlex Deucher #define NUM_GPUS(x) ((x) << 20) 414fecf1d07SAlex Deucher #define NUM_GPUS_MASK 0x00700000 415fecf1d07SAlex Deucher #define NUM_GPUS_SHIFT 20 416fecf1d07SAlex Deucher #define MULTI_GPU_TILE_SIZE(x) ((x) << 24) 417fecf1d07SAlex Deucher #define MULTI_GPU_TILE_SIZE_MASK 0x03000000 418fecf1d07SAlex Deucher #define MULTI_GPU_TILE_SIZE_SHIFT 24 419fecf1d07SAlex Deucher #define ROW_SIZE(x) ((x) << 28) 420bb92091aSAlex Deucher #define ROW_SIZE_MASK 0x30000000 421fecf1d07SAlex Deucher #define ROW_SIZE_SHIFT 28 422fecf1d07SAlex Deucher #define NUM_LOWER_PIPES(x) ((x) << 30) 423fecf1d07SAlex Deucher #define NUM_LOWER_PIPES_MASK 0x40000000 424fecf1d07SAlex Deucher #define NUM_LOWER_PIPES_SHIFT 30 425fecf1d07SAlex Deucher #define GB_BACKEND_MAP 0x98FC 426fecf1d07SAlex Deucher 427fecf1d07SAlex Deucher #define CB_PERF_CTR0_SEL_0 0x9A20 428fecf1d07SAlex Deucher #define CB_PERF_CTR0_SEL_1 0x9A24 429fecf1d07SAlex Deucher #define CB_PERF_CTR1_SEL_0 0x9A28 430fecf1d07SAlex Deucher #define CB_PERF_CTR1_SEL_1 0x9A2C 431fecf1d07SAlex Deucher #define CB_PERF_CTR2_SEL_0 0x9A30 432fecf1d07SAlex Deucher #define CB_PERF_CTR2_SEL_1 0x9A34 433fecf1d07SAlex Deucher #define CB_PERF_CTR3_SEL_0 0x9A38 434fecf1d07SAlex Deucher #define CB_PERF_CTR3_SEL_1 0x9A3C 435fecf1d07SAlex Deucher 436fecf1d07SAlex Deucher #define GC_USER_RB_BACKEND_DISABLE 0x9B7C 437fecf1d07SAlex Deucher #define BACKEND_DISABLE_MASK 0x00FF0000 438fecf1d07SAlex Deucher #define BACKEND_DISABLE_SHIFT 16 439fecf1d07SAlex Deucher 440fecf1d07SAlex Deucher #define SMX_DC_CTL0 0xA020 441fecf1d07SAlex Deucher #define USE_HASH_FUNCTION (1 << 0) 442fecf1d07SAlex Deucher #define NUMBER_OF_SETS(x) ((x) << 1) 443fecf1d07SAlex Deucher #define FLUSH_ALL_ON_EVENT (1 << 10) 444fecf1d07SAlex Deucher #define STALL_ON_EVENT (1 << 11) 445fecf1d07SAlex Deucher #define SMX_EVENT_CTL 0xA02C 446fecf1d07SAlex Deucher #define ES_FLUSH_CTL(x) ((x) << 0) 447fecf1d07SAlex Deucher #define GS_FLUSH_CTL(x) ((x) << 3) 448fecf1d07SAlex Deucher #define ACK_FLUSH_CTL(x) ((x) << 6) 449fecf1d07SAlex Deucher #define SYNC_FLUSH_CTL (1 << 8) 450fecf1d07SAlex Deucher 4510c88a02eSAlex Deucher #define CP_RB0_BASE 0xC100 4520c88a02eSAlex Deucher #define CP_RB0_CNTL 0xC104 4530c88a02eSAlex Deucher #define RB_BUFSZ(x) ((x) << 0) 4540c88a02eSAlex Deucher #define RB_BLKSZ(x) ((x) << 8) 4550c88a02eSAlex Deucher #define RB_NO_UPDATE (1 << 27) 4560c88a02eSAlex Deucher #define RB_RPTR_WR_ENA (1 << 31) 4570c88a02eSAlex Deucher #define BUF_SWAP_32BIT (2 << 16) 4580c88a02eSAlex Deucher #define CP_RB0_RPTR_ADDR 0xC10C 4590c88a02eSAlex Deucher #define CP_RB0_RPTR_ADDR_HI 0xC110 4600c88a02eSAlex Deucher #define CP_RB0_WPTR 0xC114 4611b37078bSAlex Deucher 4621b37078bSAlex Deucher #define CP_INT_CNTL 0xC124 4631b37078bSAlex Deucher # define CNTX_BUSY_INT_ENABLE (1 << 19) 4641b37078bSAlex Deucher # define CNTX_EMPTY_INT_ENABLE (1 << 20) 4651b37078bSAlex Deucher # define TIME_STAMP_INT_ENABLE (1 << 26) 4661b37078bSAlex Deucher 4670c88a02eSAlex Deucher #define CP_RB1_BASE 0xC180 4680c88a02eSAlex Deucher #define CP_RB1_CNTL 0xC184 4690c88a02eSAlex Deucher #define CP_RB1_RPTR_ADDR 0xC188 4700c88a02eSAlex Deucher #define CP_RB1_RPTR_ADDR_HI 0xC18C 4710c88a02eSAlex Deucher #define CP_RB1_WPTR 0xC190 4720c88a02eSAlex Deucher #define CP_RB2_BASE 0xC194 4730c88a02eSAlex Deucher #define CP_RB2_CNTL 0xC198 4740c88a02eSAlex Deucher #define CP_RB2_RPTR_ADDR 0xC19C 4750c88a02eSAlex Deucher #define CP_RB2_RPTR_ADDR_HI 0xC1A0 4760c88a02eSAlex Deucher #define CP_RB2_WPTR 0xC1A4 4770c88a02eSAlex Deucher #define CP_PFP_UCODE_ADDR 0xC150 4780c88a02eSAlex Deucher #define CP_PFP_UCODE_DATA 0xC154 4790c88a02eSAlex Deucher #define CP_ME_RAM_RADDR 0xC158 4800c88a02eSAlex Deucher #define CP_ME_RAM_WADDR 0xC15C 4810c88a02eSAlex Deucher #define CP_ME_RAM_DATA 0xC160 4820c88a02eSAlex Deucher #define CP_DEBUG 0xC1FC 4830c88a02eSAlex Deucher 484b40e7e16SAlex Deucher #define VGT_EVENT_INITIATOR 0x28a90 485b40e7e16SAlex Deucher # define CACHE_FLUSH_AND_INV_EVENT_TS (0x14 << 0) 486b40e7e16SAlex Deucher # define CACHE_FLUSH_AND_INV_EVENT (0x16 << 0) 487b40e7e16SAlex Deucher 4880c88a02eSAlex Deucher /* 4890c88a02eSAlex Deucher * PM4 4900c88a02eSAlex Deucher */ 4914e872ae2SIlija Hadzic #define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \ 4920c88a02eSAlex Deucher (((reg) >> 2) & 0xFFFF) | \ 4930c88a02eSAlex Deucher ((n) & 0x3FFF) << 16) 4940c88a02eSAlex Deucher #define CP_PACKET2 0x80000000 4950c88a02eSAlex Deucher #define PACKET2_PAD_SHIFT 0 4960c88a02eSAlex Deucher #define PACKET2_PAD_MASK (0x3fffffff << 0) 4970c88a02eSAlex Deucher 4980c88a02eSAlex Deucher #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 4990c88a02eSAlex Deucher 5004e872ae2SIlija Hadzic #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ 5010c88a02eSAlex Deucher (((op) & 0xFF) << 8) | \ 5020c88a02eSAlex Deucher ((n) & 0x3FFF) << 16) 5030c88a02eSAlex Deucher 5040c88a02eSAlex Deucher /* Packet 3 types */ 5050c88a02eSAlex Deucher #define PACKET3_NOP 0x10 5060c88a02eSAlex Deucher #define PACKET3_SET_BASE 0x11 5070c88a02eSAlex Deucher #define PACKET3_CLEAR_STATE 0x12 5080c88a02eSAlex Deucher #define PACKET3_INDEX_BUFFER_SIZE 0x13 5090c88a02eSAlex Deucher #define PACKET3_DEALLOC_STATE 0x14 5100c88a02eSAlex Deucher #define PACKET3_DISPATCH_DIRECT 0x15 5110c88a02eSAlex Deucher #define PACKET3_DISPATCH_INDIRECT 0x16 5120c88a02eSAlex Deucher #define PACKET3_INDIRECT_BUFFER_END 0x17 513721604a1SJerome Glisse #define PACKET3_MODE_CONTROL 0x18 5140c88a02eSAlex Deucher #define PACKET3_SET_PREDICATION 0x20 5150c88a02eSAlex Deucher #define PACKET3_REG_RMW 0x21 5160c88a02eSAlex Deucher #define PACKET3_COND_EXEC 0x22 5170c88a02eSAlex Deucher #define PACKET3_PRED_EXEC 0x23 5180c88a02eSAlex Deucher #define PACKET3_DRAW_INDIRECT 0x24 5190c88a02eSAlex Deucher #define PACKET3_DRAW_INDEX_INDIRECT 0x25 5200c88a02eSAlex Deucher #define PACKET3_INDEX_BASE 0x26 5210c88a02eSAlex Deucher #define PACKET3_DRAW_INDEX_2 0x27 5220c88a02eSAlex Deucher #define PACKET3_CONTEXT_CONTROL 0x28 5230c88a02eSAlex Deucher #define PACKET3_DRAW_INDEX_OFFSET 0x29 5240c88a02eSAlex Deucher #define PACKET3_INDEX_TYPE 0x2A 5250c88a02eSAlex Deucher #define PACKET3_DRAW_INDEX 0x2B 5260c88a02eSAlex Deucher #define PACKET3_DRAW_INDEX_AUTO 0x2D 5270c88a02eSAlex Deucher #define PACKET3_DRAW_INDEX_IMMD 0x2E 5280c88a02eSAlex Deucher #define PACKET3_NUM_INSTANCES 0x2F 5290c88a02eSAlex Deucher #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 5300c88a02eSAlex Deucher #define PACKET3_INDIRECT_BUFFER 0x32 5310c88a02eSAlex Deucher #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 5320c88a02eSAlex Deucher #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 5330c88a02eSAlex Deucher #define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36 5340c88a02eSAlex Deucher #define PACKET3_WRITE_DATA 0x37 5350c88a02eSAlex Deucher #define PACKET3_MEM_SEMAPHORE 0x39 5360c88a02eSAlex Deucher #define PACKET3_MPEG_INDEX 0x3A 5370c88a02eSAlex Deucher #define PACKET3_WAIT_REG_MEM 0x3C 5380c88a02eSAlex Deucher #define PACKET3_MEM_WRITE 0x3D 53958f8cf56SChristian König #define PACKET3_PFP_SYNC_ME 0x42 5400c88a02eSAlex Deucher #define PACKET3_SURFACE_SYNC 0x43 5410c88a02eSAlex Deucher # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 5420c88a02eSAlex Deucher # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 5430c88a02eSAlex Deucher # define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 5440c88a02eSAlex Deucher # define PACKET3_CB3_DEST_BASE_ENA (1 << 9) 5450c88a02eSAlex Deucher # define PACKET3_CB4_DEST_BASE_ENA (1 << 10) 5460c88a02eSAlex Deucher # define PACKET3_CB5_DEST_BASE_ENA (1 << 11) 5470c88a02eSAlex Deucher # define PACKET3_CB6_DEST_BASE_ENA (1 << 12) 5480c88a02eSAlex Deucher # define PACKET3_CB7_DEST_BASE_ENA (1 << 13) 5490c88a02eSAlex Deucher # define PACKET3_DB_DEST_BASE_ENA (1 << 14) 5500c88a02eSAlex Deucher # define PACKET3_CB8_DEST_BASE_ENA (1 << 15) 5510c88a02eSAlex Deucher # define PACKET3_CB9_DEST_BASE_ENA (1 << 16) 5520c88a02eSAlex Deucher # define PACKET3_CB10_DEST_BASE_ENA (1 << 17) 5530c88a02eSAlex Deucher # define PACKET3_CB11_DEST_BASE_ENA (1 << 18) 5540c88a02eSAlex Deucher # define PACKET3_FULL_CACHE_ENA (1 << 20) 5550c88a02eSAlex Deucher # define PACKET3_TC_ACTION_ENA (1 << 23) 5560c88a02eSAlex Deucher # define PACKET3_CB_ACTION_ENA (1 << 25) 5570c88a02eSAlex Deucher # define PACKET3_DB_ACTION_ENA (1 << 26) 5580c88a02eSAlex Deucher # define PACKET3_SH_ACTION_ENA (1 << 27) 5590c88a02eSAlex Deucher # define PACKET3_SX_ACTION_ENA (1 << 28) 5600c88a02eSAlex Deucher #define PACKET3_ME_INITIALIZE 0x44 5610c88a02eSAlex Deucher #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 5620c88a02eSAlex Deucher #define PACKET3_COND_WRITE 0x45 5630c88a02eSAlex Deucher #define PACKET3_EVENT_WRITE 0x46 564b40e7e16SAlex Deucher #define EVENT_TYPE(x) ((x) << 0) 565b40e7e16SAlex Deucher #define EVENT_INDEX(x) ((x) << 8) 566b40e7e16SAlex Deucher /* 0 - any non-TS event 567b40e7e16SAlex Deucher * 1 - ZPASS_DONE 568b40e7e16SAlex Deucher * 2 - SAMPLE_PIPELINESTAT 569b40e7e16SAlex Deucher * 3 - SAMPLE_STREAMOUTSTAT* 570b40e7e16SAlex Deucher * 4 - *S_PARTIAL_FLUSH 571b40e7e16SAlex Deucher * 5 - TS events 572b40e7e16SAlex Deucher */ 5730c88a02eSAlex Deucher #define PACKET3_EVENT_WRITE_EOP 0x47 574b40e7e16SAlex Deucher #define DATA_SEL(x) ((x) << 29) 575b40e7e16SAlex Deucher /* 0 - discard 576b40e7e16SAlex Deucher * 1 - send low 32bit data 577b40e7e16SAlex Deucher * 2 - send 64bit data 578b40e7e16SAlex Deucher * 3 - send 64bit counter value 579b40e7e16SAlex Deucher */ 580b40e7e16SAlex Deucher #define INT_SEL(x) ((x) << 24) 581b40e7e16SAlex Deucher /* 0 - none 582b40e7e16SAlex Deucher * 1 - interrupt only (DATA_SEL = 0) 583b40e7e16SAlex Deucher * 2 - interrupt when data write is confirmed 584b40e7e16SAlex Deucher */ 5850c88a02eSAlex Deucher #define PACKET3_EVENT_WRITE_EOS 0x48 5860c88a02eSAlex Deucher #define PACKET3_PREAMBLE_CNTL 0x4A 5870c88a02eSAlex Deucher # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 5880c88a02eSAlex Deucher # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 5890c88a02eSAlex Deucher #define PACKET3_ALU_PS_CONST_BUFFER_COPY 0x4C 5900c88a02eSAlex Deucher #define PACKET3_ALU_VS_CONST_BUFFER_COPY 0x4D 5910c88a02eSAlex Deucher #define PACKET3_ALU_PS_CONST_UPDATE 0x4E 5920c88a02eSAlex Deucher #define PACKET3_ALU_VS_CONST_UPDATE 0x4F 5930c88a02eSAlex Deucher #define PACKET3_ONE_REG_WRITE 0x57 5940c88a02eSAlex Deucher #define PACKET3_SET_CONFIG_REG 0x68 5950c88a02eSAlex Deucher #define PACKET3_SET_CONFIG_REG_START 0x00008000 5960c88a02eSAlex Deucher #define PACKET3_SET_CONFIG_REG_END 0x0000ac00 5970c88a02eSAlex Deucher #define PACKET3_SET_CONTEXT_REG 0x69 5980c88a02eSAlex Deucher #define PACKET3_SET_CONTEXT_REG_START 0x00028000 5990c88a02eSAlex Deucher #define PACKET3_SET_CONTEXT_REG_END 0x00029000 6000c88a02eSAlex Deucher #define PACKET3_SET_ALU_CONST 0x6A 6010c88a02eSAlex Deucher /* alu const buffers only; no reg file */ 6020c88a02eSAlex Deucher #define PACKET3_SET_BOOL_CONST 0x6B 6030c88a02eSAlex Deucher #define PACKET3_SET_BOOL_CONST_START 0x0003a500 6040c88a02eSAlex Deucher #define PACKET3_SET_BOOL_CONST_END 0x0003a518 6050c88a02eSAlex Deucher #define PACKET3_SET_LOOP_CONST 0x6C 6060c88a02eSAlex Deucher #define PACKET3_SET_LOOP_CONST_START 0x0003a200 6070c88a02eSAlex Deucher #define PACKET3_SET_LOOP_CONST_END 0x0003a500 6080c88a02eSAlex Deucher #define PACKET3_SET_RESOURCE 0x6D 6090c88a02eSAlex Deucher #define PACKET3_SET_RESOURCE_START 0x00030000 6100c88a02eSAlex Deucher #define PACKET3_SET_RESOURCE_END 0x00038000 6110c88a02eSAlex Deucher #define PACKET3_SET_SAMPLER 0x6E 6120c88a02eSAlex Deucher #define PACKET3_SET_SAMPLER_START 0x0003c000 6130c88a02eSAlex Deucher #define PACKET3_SET_SAMPLER_END 0x0003c600 6140c88a02eSAlex Deucher #define PACKET3_SET_CTL_CONST 0x6F 6150c88a02eSAlex Deucher #define PACKET3_SET_CTL_CONST_START 0x0003cff0 6160c88a02eSAlex Deucher #define PACKET3_SET_CTL_CONST_END 0x0003ff0c 6170c88a02eSAlex Deucher #define PACKET3_SET_RESOURCE_OFFSET 0x70 6180c88a02eSAlex Deucher #define PACKET3_SET_ALU_CONST_VS 0x71 6190c88a02eSAlex Deucher #define PACKET3_SET_ALU_CONST_DI 0x72 6200c88a02eSAlex Deucher #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 6210c88a02eSAlex Deucher #define PACKET3_SET_RESOURCE_INDIRECT 0x74 6220c88a02eSAlex Deucher #define PACKET3_SET_APPEND_CNT 0x75 6232a6f1abbSChristian König #define PACKET3_ME_WRITE 0x7A 6240c88a02eSAlex Deucher 625f60cbd11SAlex Deucher /* ASYNC DMA - first instance at 0xd000, second at 0xd800 */ 626f60cbd11SAlex Deucher #define DMA0_REGISTER_OFFSET 0x0 /* not a register */ 627f60cbd11SAlex Deucher #define DMA1_REGISTER_OFFSET 0x800 /* not a register */ 628f60cbd11SAlex Deucher 629f60cbd11SAlex Deucher #define DMA_RB_CNTL 0xd000 630f60cbd11SAlex Deucher # define DMA_RB_ENABLE (1 << 0) 631f60cbd11SAlex Deucher # define DMA_RB_SIZE(x) ((x) << 1) /* log2 */ 632f60cbd11SAlex Deucher # define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */ 633f60cbd11SAlex Deucher # define DMA_RPTR_WRITEBACK_ENABLE (1 << 12) 634f60cbd11SAlex Deucher # define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */ 635f60cbd11SAlex Deucher # define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */ 636f60cbd11SAlex Deucher #define DMA_RB_BASE 0xd004 637f60cbd11SAlex Deucher #define DMA_RB_RPTR 0xd008 638f60cbd11SAlex Deucher #define DMA_RB_WPTR 0xd00c 639f60cbd11SAlex Deucher 640f60cbd11SAlex Deucher #define DMA_RB_RPTR_ADDR_HI 0xd01c 641f60cbd11SAlex Deucher #define DMA_RB_RPTR_ADDR_LO 0xd020 642f60cbd11SAlex Deucher 643f60cbd11SAlex Deucher #define DMA_IB_CNTL 0xd024 644f60cbd11SAlex Deucher # define DMA_IB_ENABLE (1 << 0) 645f60cbd11SAlex Deucher # define DMA_IB_SWAP_ENABLE (1 << 4) 646f60cbd11SAlex Deucher # define CMD_VMID_FORCE (1 << 31) 647f60cbd11SAlex Deucher #define DMA_IB_RPTR 0xd028 648f60cbd11SAlex Deucher #define DMA_CNTL 0xd02c 649f60cbd11SAlex Deucher # define TRAP_ENABLE (1 << 0) 650f60cbd11SAlex Deucher # define SEM_INCOMPLETE_INT_ENABLE (1 << 1) 651f60cbd11SAlex Deucher # define SEM_WAIT_INT_ENABLE (1 << 2) 652f60cbd11SAlex Deucher # define DATA_SWAP_ENABLE (1 << 3) 653f60cbd11SAlex Deucher # define FENCE_SWAP_ENABLE (1 << 4) 654f60cbd11SAlex Deucher # define CTXEMPTY_INT_ENABLE (1 << 28) 655f60cbd11SAlex Deucher #define DMA_STATUS_REG 0xd034 656f60cbd11SAlex Deucher # define DMA_IDLE (1 << 0) 657f60cbd11SAlex Deucher #define DMA_SEM_INCOMPLETE_TIMER_CNTL 0xd044 658f60cbd11SAlex Deucher #define DMA_SEM_WAIT_FAIL_TIMER_CNTL 0xd048 659f60cbd11SAlex Deucher #define DMA_TILING_CONFIG 0xd0b8 660f60cbd11SAlex Deucher #define DMA_MODE 0xd0bc 661f60cbd11SAlex Deucher 662f60cbd11SAlex Deucher #define DMA_PACKET(cmd, t, s, n) ((((cmd) & 0xF) << 28) | \ 663f60cbd11SAlex Deucher (((t) & 0x1) << 23) | \ 664f60cbd11SAlex Deucher (((s) & 0x1) << 22) | \ 665f60cbd11SAlex Deucher (((n) & 0xFFFFF) << 0)) 666f60cbd11SAlex Deucher 667f60cbd11SAlex Deucher #define DMA_IB_PACKET(cmd, vmid, n) ((((cmd) & 0xF) << 28) | \ 668f60cbd11SAlex Deucher (((vmid) & 0xF) << 20) | \ 669f60cbd11SAlex Deucher (((n) & 0xFFFFF) << 0)) 670f60cbd11SAlex Deucher 671f60cbd11SAlex Deucher /* async DMA Packet types */ 672f60cbd11SAlex Deucher #define DMA_PACKET_WRITE 0x2 673f60cbd11SAlex Deucher #define DMA_PACKET_COPY 0x3 674f60cbd11SAlex Deucher #define DMA_PACKET_INDIRECT_BUFFER 0x4 675f60cbd11SAlex Deucher #define DMA_PACKET_SEMAPHORE 0x5 676f60cbd11SAlex Deucher #define DMA_PACKET_FENCE 0x6 677f60cbd11SAlex Deucher #define DMA_PACKET_TRAP 0x7 678f60cbd11SAlex Deucher #define DMA_PACKET_SRBM_WRITE 0x9 679f60cbd11SAlex Deucher #define DMA_PACKET_CONSTANT_FILL 0xd 680f60cbd11SAlex Deucher #define DMA_PACKET_NOP 0xf 681f60cbd11SAlex Deucher 6820af62b01SAlex Deucher #endif 683